[PATCH v2 0/9] imx8mm: add pwm-imx backlight support

[PATCH v2 0/9] imx8mm: add pwm-imx backlight support

[Tommaso Merciai]

Hi,
This series add support for pwm/backlight on i.MX8MM evk:

1. Add pwm1/pwm2 base address registers defines
2. Add defines for pwm control register field
3. Add struct pwm_regs
4. Add enable_pwm_clk function, configure and enable pwm clock control register
5. Add enable_pwm_clk function in clock.h
6. Add CONFIG_IMX6_PWM_PER_CLK in imx8mm_evk.h
7. Add backlight/pwm1 dts nodes support for iMX8MM evk
8. Enable pwm clk into spl
9. Enable support for pwm-imx/backlight for iMX8MM evk

Regards,
Tommaso

Tommaso Merciai (9):
  arch: mach-imx: imx8m: add pwm1/pwm2 base address
  arch: mach-imx: imx8m: add pwm ctrl registers fields defines
  arch: mach-imx: imx8m: add pwm_regs struct in imx-regs
  arm: imx: imx8mm: add enable_pwm_clk function
  imx8m: clock: add enable_pwm_clk function
  configs: imx8mm_evk: add CONFIG_IMX6_PWM_PER_CLK config
  imx8mm_evk: spl: enable pwm clock
  arm: dts: imx8mm_evk: add pwm1/backlight support
  configs: imx8mm_evk: add pwm backlight support

 arch/arm/dts/imx8mm-evk.dtsi               | 21 +++++++++
 arch/arm/include/asm/arch-imx8m/clock.h    |  1 +
 arch/arm/include/asm/arch-imx8m/imx-regs.h | 19 ++++++++
 arch/arm/mach-imx/imx8m/clock_imx8mm.c     | 53 ++++++++++++++++++++++
 board/freescale/imx8mm_evk/spl.c           |  4 ++
 configs/imx8mm_evk_defconfig               |  5 ++
 include/configs/imx8mm_evk.h               |  3 ++
 7 files changed, 106 insertions(+)

-- 
2.25.1

[PATCH v2 1/9] arch: mach-imx: imx8m: add pwm1/pwm2 base address

[Tommaso Merciai]

Add pwm1/pwm2 base address defines into imx-regs file

References:
 - IMX8MMRM.pdf p 3882

Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
---
 arch/arm/include/asm/arch-imx8m/imx-regs.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 11389a0f4d..38f8ba41c3 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -31,6 +31,8 @@
 #define SRC_BASE_ADDR		0x30390000
 #define GPC_BASE_ADDR		0x303A0000
 
+#define PWM1_BASE_ADDR		0x30660000
+#define PWM2_BASE_ADDR		0x30670000
 #define SYSCNT_RD_BASE_ADDR	0x306A0000
 #define SYSCNT_CMP_BASE_ADDR	0x306B0000
 #define SYSCNT_CTRL_BASE_ADDR	0x306C0000
-- 
2.25.1

[PATCH v2 2/9] arch: mach-imx: imx8m: add pwm ctrl registers fields defines

[Tommaso Merciai]

Add pwm control registers fields defines into imx-regs.h:

 - prescaler
 - dozeen
 - waiten
 - dbgen
 - clksrc_ipg_high
 - clksrc_ipg, en field

References:
 - iMX8MMRM.pdf p 3884

Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
---
 arch/arm/include/asm/arch-imx8m/imx-regs.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 38f8ba41c3..13538ba5f6 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -353,6 +353,14 @@ struct src {
 	u32 ddr2_rcr;
 };
 
+#define PWMCR_PRESCALER(x)	(((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN		(1 << 24)
+#define PWMCR_WAITEN		(1 << 23)
+#define PWMCR_DBGEN		(1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH	(2 << 16)
+#define PWMCR_CLKSRC_IPG	(1 << 16)
+#define PWMCR_EN		(1 << 0)
+
 #define WDOG_WDT_MASK	BIT(3)
 #define WDOG_WDZST_MASK	BIT(0)
 struct wdog_regs {
-- 
2.25.1

[PATCH v2 3/9] arch: mach-imx: imx8m: add pwm_regs struct in imx-regs

[Tommaso Merciai]

Add pwm_regs struct for i.MX8MM SOC

Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
---
 arch/arm/include/asm/arch-imx8m/imx-regs.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 13538ba5f6..9217f93a50 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -361,6 +361,15 @@ struct src {
 #define PWMCR_CLKSRC_IPG	(1 << 16)
 #define PWMCR_EN		(1 << 0)
 
+struct pwm_regs {
+	u32	cr;
+	u32	sr;
+	u32	ir;
+	u32	sar;
+	u32	pr;
+	u32	cnr;
+};
+
 #define WDOG_WDT_MASK	BIT(3)
 #define WDOG_WDZST_MASK	BIT(0)
 struct wdog_regs {
-- 
2.25.1

[PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function

[Tommaso Merciai]

Add function enable_pwm_clk into in clock_imx8mm.c. This
function first configure, then enable pwm clock from clock control
register. The following configuration is used:

source(0) -> 24 MHz ref clock
div(0)    -> no division for this clock

References:
 - iMX8MMRM.pdf p 303

Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
---
Changes since v1:
 - Fix enable_pwm_clk function implementation. Now is generic for all pwm clks

 arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 ++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 49945faf2c..ffb9456607 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -313,6 +313,59 @@ void enable_usboh3_clk(unsigned int enable)
 	}
 }
 
+void enable_pwm_clk(u32 index, unsigned char enable)
+{
+	switch (index) {
+	case 0:
+		if (enable) {
+			clock_enable(CCGR_PWM1, false);
+			clock_set_target_val(PWM1_CLK_ROOT, CLK_ROOT_ON |
+						CLK_ROOT_SOURCE_SEL(0) |
+						CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
+			clock_enable(CCGR_PWM1, true);
+		} else {
+			clock_enable(CCGR_PWM1, false);
+		}
+		return;
+	case 1:
+		if (enable) {
+			clock_enable(CCGR_PWM2, false);
+			clock_set_target_val(PWM2_CLK_ROOT, CLK_ROOT_ON |
+						CLK_ROOT_SOURCE_SEL(0) |
+						CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
+			clock_enable(CCGR_PWM2, true);
+		} else {
+			clock_enable(CCGR_PWM2, false);
+		}
+		return;
+	case 2:
+		if (enable) {
+			clock_enable(CCGR_PWM3, false);
+			clock_set_target_val(PWM3_CLK_ROOT, CLK_ROOT_ON |
+						CLK_ROOT_SOURCE_SEL(0) |
+						CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
+			clock_enable(CCGR_PWM3, true);
+		} else {
+			clock_enable(CCGR_PWM3, false);
+		}
+		return;
+	case 3:
+		if (enable) {
+			clock_enable(CCGR_PWM4, false);
+			clock_set_target_val(PWM4_CLK_ROOT, CLK_ROOT_ON |
+						CLK_ROOT_SOURCE_SEL(0) |
+						CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
+			clock_enable(CCGR_PWM4, true);
+		} else {
+			clock_enable(CCGR_PWM4, false);
+		}
+		return;
+	default:
+		printf("Invalid pwm index\n");
+		return;
+	}
+}
+
 void init_uart_clk(u32 index)
 {
 	/*
-- 
2.25.1

[PATCH v2 5/9] imx8m: clock: add enable_pwm_clk function

[Tommaso Merciai]

Add enable_pwm_clk function in clock.h

Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
---
Changes since v1:
 - Fix enable_pwm_clk function implementation. Now is generic for all pwm clks

 arch/arm/include/asm/arch-imx8m/clock.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h
index 50359d8e46..e320025990 100644
--- a/arch/arm/include/asm/arch-imx8m/clock.h
+++ b/arch/arm/include/asm/arch-imx8m/clock.h
@@ -278,3 +278,4 @@ int set_clk_enet(enum enet_freq type);
 int set_clk_eqos(enum enet_freq type);
 void hab_caam_clock_enable(unsigned char enable);
 void enable_usboh3_clk(unsigned int enable);
+void enable_pwm_clk(u32 index, unsigned char enable);
-- 
2.25.1

[PATCH v2 6/9] configs: imx8mm_evk: add CONFIG_IMX6_PWM_PER_CLK config

[Tommaso Merciai]

In order to support pwm-imx-util CONFIG_IMX6_PWM_PER_CLK is needed.
At the moment driver don't support clock framework

Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
---
 include/configs/imx8mm_evk.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
index c7022ef0f7..3c17dd3773 100644
--- a/include/configs/imx8mm_evk.h
+++ b/include/configs/imx8mm_evk.h
@@ -91,4 +91,7 @@
 
 #define IMX_FEC_BASE			0x30BE0000
 
+#ifdef CONFIG_PWM_IMX
+	#define CONFIG_IMX6_PWM_PER_CLK	66000000
+#endif
 #endif
-- 
2.25.1

[PATCH v2 7/9] imx8mm_evk: spl: enable pwm clock

[Tommaso Merciai]

Enable pwm1 clock into spl

Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
---
Changes since v1:
 - Fix enable_pwm_clk call

 board/freescale/imx8mm_evk/spl.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c
index 4ef7f6f180..cf173b885f 100644
--- a/board/freescale/imx8mm_evk/spl.c
+++ b/board/freescale/imx8mm_evk/spl.c
@@ -135,6 +135,10 @@ void board_init_f(ulong dummy)
 
 	init_uart_clk(1);
 
+#ifdef CONFIG_PWM_IMX
+	enable_pwm_clk(0, 1);
+#endif
+
 	board_early_init_f();
 
 	timer_init();
-- 
2.25.1

[PATCH v2 8/9] arm: dts: imx8mm_evk: add pwm1/backlight support

[Tommaso Merciai]

Add pwm1/backlight support nodes for imx8mm_evk board

Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
---
 arch/arm/dts/imx8mm-evk.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi
index 60179e006d..e7a2bd8a64 100644
--- a/arch/arm/dts/imx8mm-evk.dtsi
+++ b/arch/arm/dts/imx8mm-evk.dtsi
@@ -41,6 +41,15 @@
 		enable-active-high;
 	};
 
+	backlight: backlight {
+		status = "disabled";
+		compatible = "pwm-backlight";
+		pwms = <&pwm1 0 5000000>;
+		brightness-levels = <0 255>;
+		num-interpolated-steps = <255>;
+		default-brightness-level = <250>;
+	};
+
 	ir-receiver {
 		compatible = "gpio-ir-receiver";
 		gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
@@ -350,6 +359,12 @@
 	status = "okay";
 };
 
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_backlight>;
+	status = "disabled";
+};
+
 &iomuxc {
 	pinctrl_fec1: fec1grp {
 		fsl,pins = <
@@ -491,4 +506,10 @@
 			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x166
 		>;
 	};
+
+	pinctrl_backlight: backlightgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT	0x06
+		>;
+	};
 };
-- 
2.25.1

[PATCH v2 9/9] configs: imx8mm_evk: add pwm backlight support

[Tommaso Merciai]

Enable support for backlight/pwm-imx driver

Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
---
 configs/imx8mm_evk_defconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index 01395fc7eb..cfba6cc673 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -84,3 +84,8 @@ CONFIG_SYSRESET_PSCI=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
 CONFIG_IMX_WATCHDOG=y
+CONFIG_DM_VIDEO=y
+CONFIG_BACKLIGHT=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_IMX=y
\ No newline at end of file
-- 
2.25.1

Re: [PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function

[Michael Nazzareno Trimarchi]

Hi  Tommaaso


On Wed, Mar 16, 2022 at 4:28 PM Tommaso Merciai
<tommaso.merciai@amarulasolutions.com> wrote:
>
> Add function enable_pwm_clk into in clock_imx8mm.c. This
> function first configure, then enable pwm clock from clock control
> register. The following configuration is used:
>
> source(0) -> 24 MHz ref clock
> div(0)    -> no division for this clock
>
> References:
>  - iMX8MMRM.pdf p 303
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> ---
> Changes since v1:
>  - Fix enable_pwm_clk function implementation. Now is generic for all pwm clks
>
>  arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 ++++++++++++++++++++++++++
>  1 file changed, 53 insertions(+)
>
> diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> index 49945faf2c..ffb9456607 100644
> --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> @@ -313,6 +313,59 @@ void enable_usboh3_clk(unsigned int enable)
>         }
>  }
>
> +void enable_pwm_clk(u32 index, unsigned char enable)
> +{
> +       switch (index) {
> +       case 0:
> +               if (enable) {
> +                       clock_enable(CCGR_PWM1, false);
> +                       clock_set_target_val(PWM1_CLK_ROOT, CLK_ROOT_ON |
> +                                               CLK_ROOT_SOURCE_SEL(0) |
> +                                               CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
> +                       clock_enable(CCGR_PWM1, true);
> +               } else {
> +                       clock_enable(CCGR_PWM1, false);

Pwm is alway before set to false and then enable. Make sense to move
out. Then all the code is look quite the same apart
minior change

Can you clean up in order to have a more compact implementation?

Michael

> +               }


> +               return;
> +       case 1:
> +               if (enable) {
> +                       clock_enable(CCGR_PWM2, false);
> +                       clock_set_target_val(PWM2_CLK_ROOT, CLK_ROOT_ON |
> +                                               CLK_ROOT_SOURCE_SEL(0) |
> +                                               CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
> +                       clock_enable(CCGR_PWM2, true);
> +               } else {
> +                       clock_enable(CCGR_PWM2, false);
> +               }
> +               return;
> +       case 2:
> +               if (enable) {
> +                       clock_enable(CCGR_PWM3, false);
> +                       clock_set_target_val(PWM3_CLK_ROOT, CLK_ROOT_ON |
> +                                               CLK_ROOT_SOURCE_SEL(0) |
> +                                               CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
> +                       clock_enable(CCGR_PWM3, true);
> +               } else {
> +                       clock_enable(CCGR_PWM3, false);
> +               }
> +               return;
> +       case 3:
> +               if (enable) {
> +                       clock_enable(CCGR_PWM4, false);
> +                       clock_set_target_val(PWM4_CLK_ROOT, CLK_ROOT_ON |
> +                                               CLK_ROOT_SOURCE_SEL(0) |
> +                                               CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
> +                       clock_enable(CCGR_PWM4, true);
> +               } else {
> +                       clock_enable(CCGR_PWM4, false);
> +               }
> +               return;
> +       default:
> +               printf("Invalid pwm index\n");
> +               return;
> +       }
> +}
> +

Please factorize things that are always eegual
>  void init_uart_clk(u32 index)
>  {
>         /*
> --
> 2.25.1
>


--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com

Re: [PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function

[Marek Vasut]

On 3/16/22 16:27, Tommaso Merciai wrote:
> Add function enable_pwm_clk into in clock_imx8mm.c. This
> function first configure, then enable pwm clock from clock control
> register. The following configuration is used:
> 
> source(0) -> 24 MHz ref clock
> div(0)    -> no division for this clock
> 
> References:
>   - iMX8MMRM.pdf p 303
> 
> Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> ---
> Changes since v1:
>   - Fix enable_pwm_clk function implementation. Now is generic for all pwm clks
> 
>   arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 ++++++++++++++++++++++++++
>   1 file changed, 53 insertions(+)

Why is this not in drivers/clk/imx/ DM driver ?

Re: [PATCH v2 7/9] imx8mm_evk: spl: enable pwm clock

[Fabio Estevam]

Hi Tommaso,

On Wed, Mar 16, 2022 at 12:28 PM Tommaso Merciai
<tommaso.merciai@amarulasolutions.com> wrote:
>
> Enable pwm1 clock into spl

Please improve the commit log and explain why you need to enable the
PWM clock in SPL.

What is the PWM use case in PWM that you plan to use?

Re: [PATCH v2 7/9] imx8mm_evk: spl: enable pwm clock

[Fabio Estevam]

On Wed, Mar 16, 2022 at 8:55 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi Tommaso,
>
> On Wed, Mar 16, 2022 at 12:28 PM Tommaso Merciai
> <tommaso.merciai@amarulasolutions.com> wrote:
> >
> > Enable pwm1 clock into spl
>
> Please improve the commit log and explain why you need to enable the
> PWM clock in SPL.
>
> What is the PWM use case in PWM that you plan to use?

I meant: "What is the PWM use case in SPL that you plan to use?"

Re: [PATCH v2 7/9] imx8mm_evk: spl: enable pwm clock

[Tommaso Merciai]

On Wed, Mar 16, 2022 at 09:48:57PM -0300, Fabio Estevam wrote:
> On Wed, Mar 16, 2022 at 8:55 PM Fabio Estevam <festevam@gmail.com> wrote:
> >
> > Hi Tommaso,
> >
> > On Wed, Mar 16, 2022 at 12:28 PM Tommaso Merciai
> > <tommaso.merciai@amarulasolutions.com> wrote:
> > >
> > > Enable pwm1 clock into spl
> >
> > Please improve the commit log and explain why you need to enable the
> > PWM clock in SPL.
> >
> > What is the PWM use case in PWM that you plan to use?
> 
> I meant: "What is the PWM use case in SPL that you plan to use?"

Hi Fabio,
You mean is better to move the clock enable into board_late_init function?
I plan to provide support for display panel at u-boot level in particular
I plan to use lcdif->mipi_dsi->sn65dsi84->display video pipeline.
Let me know.

Thanks,
Tommaso

-- 
Tommaso Merciai
Embedded Linux Engineer
tommaso.merciai@amarulasolutions.com
__________________________________

Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
info@amarulasolutions.com
www.amarulasolutions.com

Re: [PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function

[Tommaso Merciai]

On Wed, Mar 16, 2022 at 09:54:34PM +0100, Marek Vasut wrote:
> On 3/16/22 16:27, Tommaso Merciai wrote:
> > Add function enable_pwm_clk into in clock_imx8mm.c. This
> > function first configure, then enable pwm clock from clock control
> > register. The following configuration is used:
> > 
> > source(0) -> 24 MHz ref clock
> > div(0)    -> no division for this clock
> > 
> > References:
> >   - iMX8MMRM.pdf p 303
> > 
> > Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> > ---
> > Changes since v1:
> >   - Fix enable_pwm_clk function implementation. Now is generic for all pwm clks
> > 
> >   arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 ++++++++++++++++++++++++++
> >   1 file changed, 53 insertions(+)
> 
> Why is this not in drivers/clk/imx/ DM driver ?

Hi Marek,
All function that enable/configure clk from CCGR are in arch/arm/mach-imx/imx8m/clock_imx8mm.c.
For that I continue to put here the implementation. After we can port
the clk dm part to manipulate clock in drivers/clk/imx/ DM driver.
What do you think about? Let me know.

Thanks,
Tommaso

-- 
Tommaso Merciai
Embedded Linux Engineer
tommaso.merciai@amarulasolutions.com
__________________________________

Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
info@amarulasolutions.com
www.amarulasolutions.com

Re: [PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function

[Tommaso Merciai]

On Wed, Mar 16, 2022 at 08:07:01PM +0100, Michael Nazzareno Trimarchi wrote:
> Hi  Tommaaso
> 
> 
> On Wed, Mar 16, 2022 at 4:28 PM Tommaso Merciai
> <tommaso.merciai@amarulasolutions.com> wrote:
> >
> > Add function enable_pwm_clk into in clock_imx8mm.c. This
> > function first configure, then enable pwm clock from clock control
> > register. The following configuration is used:
> >
> > source(0) -> 24 MHz ref clock
> > div(0)    -> no division for this clock
> >
> > References:
> >  - iMX8MMRM.pdf p 303
> >
> > Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> > ---
> > Changes since v1:
> >  - Fix enable_pwm_clk function implementation. Now is generic for all pwm clks
> >
> >  arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 ++++++++++++++++++++++++++
> >  1 file changed, 53 insertions(+)
> >
> > diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > index 49945faf2c..ffb9456607 100644
> > --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > @@ -313,6 +313,59 @@ void enable_usboh3_clk(unsigned int enable)
> >         }
> >  }
> >
> > +void enable_pwm_clk(u32 index, unsigned char enable)
> > +{
> > +       switch (index) {
> > +       case 0:
> > +               if (enable) {
> > +                       clock_enable(CCGR_PWM1, false);
> > +                       clock_set_target_val(PWM1_CLK_ROOT, CLK_ROOT_ON |
> > +                                               CLK_ROOT_SOURCE_SEL(0) |
> > +                                               CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
> > +                       clock_enable(CCGR_PWM1, true);
> > +               } else {
> > +                       clock_enable(CCGR_PWM1, false);
> 
> Pwm is alway before set to false and then enable. Make sense to move
> out. Then all the code is look quite the same apart
> minior change
> 
> Can you clean up in order to have a more compact implementation?

Hi Michael,
Ok, I remove the else in the implementation in v3.

Thanks,
Tommaso

> 
> Michael
> 
> > +               }
> 
> 
> > +               return;
> > +       case 1:
> > +               if (enable) {
> > +                       clock_enable(CCGR_PWM2, false);
> > +                       clock_set_target_val(PWM2_CLK_ROOT, CLK_ROOT_ON |
> > +                                               CLK_ROOT_SOURCE_SEL(0) |
> > +                                               CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
> > +                       clock_enable(CCGR_PWM2, true);
> > +               } else {
> > +                       clock_enable(CCGR_PWM2, false);
> > +               }
> > +               return;
> > +       case 2:
> > +               if (enable) {
> > +                       clock_enable(CCGR_PWM3, false);
> > +                       clock_set_target_val(PWM3_CLK_ROOT, CLK_ROOT_ON |
> > +                                               CLK_ROOT_SOURCE_SEL(0) |
> > +                                               CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
> > +                       clock_enable(CCGR_PWM3, true);
> > +               } else {
> > +                       clock_enable(CCGR_PWM3, false);
> > +               }
> > +               return;
> > +       case 3:
> > +               if (enable) {
> > +                       clock_enable(CCGR_PWM4, false);
> > +                       clock_set_target_val(PWM4_CLK_ROOT, CLK_ROOT_ON |
> > +                                               CLK_ROOT_SOURCE_SEL(0) |
> > +                                               CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
> > +                       clock_enable(CCGR_PWM4, true);
> > +               } else {
> > +                       clock_enable(CCGR_PWM4, false);
> > +               }
> > +               return;
> > +       default:
> > +               printf("Invalid pwm index\n");
> > +               return;
> > +       }
> > +}
> > +
> 
> Please factorize things that are always eegual
> >  void init_uart_clk(u32 index)
> >  {
> >         /*
> > --
> > 2.25.1
> >
> 
> 
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> michael@amarulasolutions.com
> __________________________________
> 
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> info@amarulasolutions.com
> www.amarulasolutions.com

-- 
Tommaso Merciai
Embedded Linux Engineer
tommaso.merciai@amarulasolutions.com
__________________________________

Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
info@amarulasolutions.com
www.amarulasolutions.com

Re: [PATCH v2 7/9] imx8mm_evk: spl: enable pwm clock

[Fabio Estevam]

Hi Tommaso,

On Thu, Mar 17, 2022 at 4:34 AM Tommaso Merciai
<tommaso.merciai@amarulasolutions.com> wrote:

> Hi Fabio,
> You mean is better to move the clock enable into board_late_init function?

Yes, you would only need PWM support in U-Boot proper, not in SPL, so better to
turn on the PWM clock inside U-Boot proper.

> I plan to provide support for display panel at u-boot level in particular
> I plan to use lcdif->mipi_dsi->sn65dsi84->display video pipeline.

Ok, great. It would be great to have i.MX8MM display driver in kernel
mainline and U-Boot mainline.

Re: [PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function

[Marek Vasut]

On 3/17/22 08:39, Tommaso Merciai wrote:
> On Wed, Mar 16, 2022 at 09:54:34PM +0100, Marek Vasut wrote:
>> On 3/16/22 16:27, Tommaso Merciai wrote:
>>> Add function enable_pwm_clk into in clock_imx8mm.c. This
>>> function first configure, then enable pwm clock from clock control
>>> register. The following configuration is used:
>>>
>>> source(0) -> 24 MHz ref clock
>>> div(0)    -> no division for this clock
>>>
>>> References:
>>>    - iMX8MMRM.pdf p 303
>>>
>>> Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
>>> ---
>>> Changes since v1:
>>>    - Fix enable_pwm_clk function implementation. Now is generic for all pwm clks
>>>
>>>    arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 ++++++++++++++++++++++++++
>>>    1 file changed, 53 insertions(+)
>>
>> Why is this not in drivers/clk/imx/ DM driver ?
> 
> Hi Marek,
> All function that enable/configure clk from CCGR are in arch/arm/mach-imx/imx8m/clock_imx8mm.c.

These seems to be CCGR:

$ grep -C 2 '0x4[0-9a-f]\{3\}' drivers/clk/imx/clk-imx8mm.c | sed "s@^.@@"

clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
        imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
        imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
        imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
clk_dm(IMX8MM_CLK_I2C1_ROOT,
        imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
clk_dm(IMX8MM_CLK_I2C2_ROOT,
        imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
clk_dm(IMX8MM_CLK_I2C3_ROOT,
        imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
clk_dm(IMX8MM_CLK_I2C4_ROOT,
        imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
clk_dm(IMX8MM_CLK_OCOTP_ROOT,
        imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
clk_dm(IMX8MM_CLK_USDHC1_ROOT,
        imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
clk_dm(IMX8MM_CLK_USDHC2_ROOT,
        imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
clk_dm(IMX8MM_CLK_WDOG1_ROOT,
        imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
clk_dm(IMX8MM_CLK_WDOG2_ROOT,
        imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
clk_dm(IMX8MM_CLK_WDOG3_ROOT,
        imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
clk_dm(IMX8MM_CLK_USDHC3_ROOT,
        imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
clk_dm(IMX8MM_CLK_QSPI_ROOT,
        imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
         imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));

/* clks not needed in SPL stage */
-
clk_dm(IMX8MM_CLK_ENET1_ROOT,
        imx_clk_gate4("enet1_root_clk", "enet_axi",
        base + 0x40a0, 0));
endif

> For that I continue to put here the implementation. After we can port
> the clk dm part to manipulate clock in drivers/clk/imx/ DM driver.
> What do you think about? Let me know.

Seems like the clk_dm part is already in place and all you have to do is 
extend it.

Re: [PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function

[Tommaso Merciai]

On Thu, Mar 17, 2022 at 12:58:31PM +0100, Marek Vasut wrote:
> On 3/17/22 08:39, Tommaso Merciai wrote:
> > On Wed, Mar 16, 2022 at 09:54:34PM +0100, Marek Vasut wrote:
> > > On 3/16/22 16:27, Tommaso Merciai wrote:
> > > > Add function enable_pwm_clk into in clock_imx8mm.c. This
> > > > function first configure, then enable pwm clock from clock control
> > > > register. The following configuration is used:
> > > > 
> > > > source(0) -> 24 MHz ref clock
> > > > div(0)    -> no division for this clock
> > > > 
> > > > References:
> > > >    - iMX8MMRM.pdf p 303
> > > > 
> > > > Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> > > > ---
> > > > Changes since v1:
> > > >    - Fix enable_pwm_clk function implementation. Now is generic for all pwm clks
> > > > 
> > > >    arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 ++++++++++++++++++++++++++
> > > >    1 file changed, 53 insertions(+)
> > > 
> > > Why is this not in drivers/clk/imx/ DM driver ?
> > 
> > Hi Marek,
> > All function that enable/configure clk from CCGR are in arch/arm/mach-imx/imx8m/clock_imx8mm.c.
> 
> These seems to be CCGR:
> 
> $ grep -C 2 '0x4[0-9a-f]\{3\}' drivers/clk/imx/clk-imx8mm.c | sed "s@^.@@"
> 
> clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
>        imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
> clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
>        imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
> clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
>        imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
> clk_dm(IMX8MM_CLK_I2C1_ROOT,
>        imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
> clk_dm(IMX8MM_CLK_I2C2_ROOT,
>        imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
> clk_dm(IMX8MM_CLK_I2C3_ROOT,
>        imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
> clk_dm(IMX8MM_CLK_I2C4_ROOT,
>        imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
> clk_dm(IMX8MM_CLK_OCOTP_ROOT,
>        imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
> clk_dm(IMX8MM_CLK_USDHC1_ROOT,
>        imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
> clk_dm(IMX8MM_CLK_USDHC2_ROOT,
>        imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
> clk_dm(IMX8MM_CLK_WDOG1_ROOT,
>        imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
> clk_dm(IMX8MM_CLK_WDOG2_ROOT,
>        imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
> clk_dm(IMX8MM_CLK_WDOG3_ROOT,
>        imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
> clk_dm(IMX8MM_CLK_USDHC3_ROOT,
>        imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
> clk_dm(IMX8MM_CLK_QSPI_ROOT,
>        imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
> clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
>         imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
> 
> /* clks not needed in SPL stage */
> -
> clk_dm(IMX8MM_CLK_ENET1_ROOT,
>        imx_clk_gate4("enet1_root_clk", "enet_axi",
>        base + 0x40a0, 0));
> endif
> 
> > For that I continue to put here the implementation. After we can port
> > the clk dm part to manipulate clock in drivers/clk/imx/ DM driver.
> > What do you think about? Let me know.
> 
> Seems like the clk_dm part is already in place and all you have to do is
> extend it.

Hi Marek,
I'll try also this way and let you know.

Thanks,
Tommaso

-- 
Tommaso Merciai
Embedded Linux Engineer
tommaso.merciai@amarulasolutions.com
__________________________________

Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
info@amarulasolutions.com
www.amarulasolutions.com

Re: [PATCH v2 7/9] imx8mm_evk: spl: enable pwm clock

[Tommaso Merciai]

On Thu, Mar 17, 2022 at 07:55:40AM -0300, Fabio Estevam wrote:
> Hi Tommaso,
> 
> On Thu, Mar 17, 2022 at 4:34 AM Tommaso Merciai
> <tommaso.merciai@amarulasolutions.com> wrote:
> 
> > Hi Fabio,
> > You mean is better to move the clock enable into board_late_init function?
> 
> Yes, you would only need PWM support in U-Boot proper, not in SPL, so better to
> turn on the PWM clock inside U-Boot proper.

Hi Fabio,
Ok, I move the function on board_late_init in v3.

Thanks,
Tommaso

> 
> > I plan to provide support for display panel at u-boot level in particular
> > I plan to use lcdif->mipi_dsi->sn65dsi84->display video pipeline.
> 
> Ok, great. It would be great to have i.MX8MM display driver in kernel
> mainline and U-Boot mainline.

-- 
Tommaso Merciai
Embedded Linux Engineer
tommaso.merciai@amarulasolutions.com
__________________________________

Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
info@amarulasolutions.com
www.amarulasolutions.com

Re: [PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function

[Marek Vasut]

On 3/17/22 13:38, Tommaso Merciai wrote:
> On Thu, Mar 17, 2022 at 12:58:31PM +0100, Marek Vasut wrote:
>> On 3/17/22 08:39, Tommaso Merciai wrote:
>>> On Wed, Mar 16, 2022 at 09:54:34PM +0100, Marek Vasut wrote:
>>>> On 3/16/22 16:27, Tommaso Merciai wrote:
>>>>> Add function enable_pwm_clk into in clock_imx8mm.c. This
>>>>> function first configure, then enable pwm clock from clock control
>>>>> register. The following configuration is used:
>>>>>
>>>>> source(0) -> 24 MHz ref clock
>>>>> div(0)    -> no division for this clock
>>>>>
>>>>> References:
>>>>>     - iMX8MMRM.pdf p 303
>>>>>
>>>>> Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
>>>>> ---
>>>>> Changes since v1:
>>>>>     - Fix enable_pwm_clk function implementation. Now is generic for all pwm clks
>>>>>
>>>>>     arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 ++++++++++++++++++++++++++
>>>>>     1 file changed, 53 insertions(+)
>>>>
>>>> Why is this not in drivers/clk/imx/ DM driver ?
>>>
>>> Hi Marek,
>>> All function that enable/configure clk from CCGR are in arch/arm/mach-imx/imx8m/clock_imx8mm.c.
>>
>> These seems to be CCGR:
>>
>> $ grep -C 2 '0x4[0-9a-f]\{3\}' drivers/clk/imx/clk-imx8mm.c | sed "s@^.@@"
>>
>> clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
>>         imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
>> clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
>>         imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
>> clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
>>         imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
>> clk_dm(IMX8MM_CLK_I2C1_ROOT,
>>         imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
>> clk_dm(IMX8MM_CLK_I2C2_ROOT,
>>         imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
>> clk_dm(IMX8MM_CLK_I2C3_ROOT,
>>         imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
>> clk_dm(IMX8MM_CLK_I2C4_ROOT,
>>         imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
>> clk_dm(IMX8MM_CLK_OCOTP_ROOT,
>>         imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
>> clk_dm(IMX8MM_CLK_USDHC1_ROOT,
>>         imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
>> clk_dm(IMX8MM_CLK_USDHC2_ROOT,
>>         imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
>> clk_dm(IMX8MM_CLK_WDOG1_ROOT,
>>         imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
>> clk_dm(IMX8MM_CLK_WDOG2_ROOT,
>>         imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
>> clk_dm(IMX8MM_CLK_WDOG3_ROOT,
>>         imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
>> clk_dm(IMX8MM_CLK_USDHC3_ROOT,
>>         imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
>> clk_dm(IMX8MM_CLK_QSPI_ROOT,
>>         imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
>> clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
>>          imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
>>
>> /* clks not needed in SPL stage */
>> -
>> clk_dm(IMX8MM_CLK_ENET1_ROOT,
>>         imx_clk_gate4("enet1_root_clk", "enet_axi",
>>         base + 0x40a0, 0));
>> endif
>>
>>> For that I continue to put here the implementation. After we can port
>>> the clk dm part to manipulate clock in drivers/clk/imx/ DM driver.
>>> What do you think about? Let me know.
>>
>> Seems like the clk_dm part is already in place and all you have to do is
>> extend it.
> 
> Hi Marek,
> I'll try also this way and let you know.

Thanks

Re: [PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function

[Tommaso Merciai]

On Thu, Mar 17, 2022 at 01:38:18PM +0100, Tommaso Merciai wrote:
> On Thu, Mar 17, 2022 at 12:58:31PM +0100, Marek Vasut wrote:
> > On 3/17/22 08:39, Tommaso Merciai wrote:
> > > On Wed, Mar 16, 2022 at 09:54:34PM +0100, Marek Vasut wrote:
> > > > On 3/16/22 16:27, Tommaso Merciai wrote:
> > > > > Add function enable_pwm_clk into in clock_imx8mm.c. This
> > > > > function first configure, then enable pwm clock from clock control
> > > > > register. The following configuration is used:
> > > > > 
> > > > > source(0) -> 24 MHz ref clock
> > > > > div(0)    -> no division for this clock
> > > > > 
> > > > > References:
> > > > >    - iMX8MMRM.pdf p 303
> > > > > 
> > > > > Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> > > > > ---
> > > > > Changes since v1:
> > > > >    - Fix enable_pwm_clk function implementation. Now is generic for all pwm clks
> > > > > 
> > > > >    arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 ++++++++++++++++++++++++++
> > > > >    1 file changed, 53 insertions(+)
> > > > 
> > > > Why is this not in drivers/clk/imx/ DM driver ?
> > > 
> > > Hi Marek,
> > > All function that enable/configure clk from CCGR are in arch/arm/mach-imx/imx8m/clock_imx8mm.c.
> > 
> > These seems to be CCGR:
> > 
> > $ grep -C 2 '0x4[0-9a-f]\{3\}' drivers/clk/imx/clk-imx8mm.c | sed "s@^.@@"
> > 
> > clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
> >        imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
> > clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
> >        imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
> > clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
> >        imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
> > clk_dm(IMX8MM_CLK_I2C1_ROOT,
> >        imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
> > clk_dm(IMX8MM_CLK_I2C2_ROOT,
> >        imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
> > clk_dm(IMX8MM_CLK_I2C3_ROOT,
> >        imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
> > clk_dm(IMX8MM_CLK_I2C4_ROOT,
> >        imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
> > clk_dm(IMX8MM_CLK_OCOTP_ROOT,
> >        imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
> > clk_dm(IMX8MM_CLK_USDHC1_ROOT,
> >        imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
> > clk_dm(IMX8MM_CLK_USDHC2_ROOT,
> >        imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
> > clk_dm(IMX8MM_CLK_WDOG1_ROOT,
> >        imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
> > clk_dm(IMX8MM_CLK_WDOG2_ROOT,
> >        imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
> > clk_dm(IMX8MM_CLK_WDOG3_ROOT,
> >        imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
> > clk_dm(IMX8MM_CLK_USDHC3_ROOT,
> >        imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
> > clk_dm(IMX8MM_CLK_QSPI_ROOT,
> >        imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
> > clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
> >         imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
> > 
> > /* clks not needed in SPL stage */
> > -
> > clk_dm(IMX8MM_CLK_ENET1_ROOT,
> >        imx_clk_gate4("enet1_root_clk", "enet_axi",
> >        base + 0x40a0, 0));
> > endif
> > 
> > > For that I continue to put here the implementation. After we can port
> > > the clk dm part to manipulate clock in drivers/clk/imx/ DM driver.
> > > What do you think about? Let me know.
> > 
> > Seems like the clk_dm part is already in place and all you have to do is
> > extend it.

Hi Marek,
I test the solution using DM model, it work:

u-boot=> clk dump

 24000000             2        |   |-- pwm1
 24000000             3        |   |   `-- pwm1_root_clk
 24000000             0        |   |-- pwm2
 24000000             0        |   |   `-- pwm2_root_clk
 24000000             0        |   |-- pwm3
 24000000             0        |   |   `-- pwm3_root_clk
 24000000             0        |   |-- pwm4
 24000000             0        |   |   `-- pwm4_root_clk


I test it using the following call on a dummy driver:

ret = uclass_get_device_by_name(UCLASS_PWM, "pwm@30660000", &pwm);
if (ret)
	printk("Failed to get pwm dev\n");

ret = clk_get_by_name(pwm, "per", &per_clk);
if (ret) {
	printf("Failed to get per_clk\n");
	return ret;
}
ret = clk_enable(&per_clk);
if (ret) {
	printf("Failed to enable per_clk\n");
	return ret;
}

ret = clk_get_by_name(pwm, "ipg", &ipg_clk);
if (ret) {
	printf("Failed to get ipg_clk\n");
	return ret;
}
ret = clk_enable(&ipg_clk);
if (ret) {
	printf("Failed to enable ipg_clk\n");
	return ret;
}

It's better to keep both the solutions or only
based on DM model? I think we can put this initialization into
drivers/pwm/pwm-imx.c imx_pwm_of_to_plat function.
What do you think about?
Let me know.

Thanks,
Tommaso


> 
> Hi Marek,
> I'll try also this way and let you know.
> 
> Thanks,
> Tommaso
> 
> -- 
> Tommaso Merciai
> Embedded Linux Engineer
> tommaso.merciai@amarulasolutions.com
> __________________________________
> 
> Amarula Solutions SRL
> Via Le Canevare 30, 31100 Treviso, Veneto, IT
> T. +39 042 243 5310
> info@amarulasolutions.com
> www.amarulasolutions.com

-- 
Tommaso Merciai
Embedded Linux Engineer
tommaso.merciai@amarulasolutions.com
__________________________________

Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
info@amarulasolutions.com
www.amarulasolutions.com

Re: [PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function

[Marek Vasut]

On 3/17/22 16:13, Tommaso Merciai wrote:
> On Thu, Mar 17, 2022 at 01:38:18PM +0100, Tommaso Merciai wrote:
>> On Thu, Mar 17, 2022 at 12:58:31PM +0100, Marek Vasut wrote:
>>> On 3/17/22 08:39, Tommaso Merciai wrote:
>>>> On Wed, Mar 16, 2022 at 09:54:34PM +0100, Marek Vasut wrote:
>>>>> On 3/16/22 16:27, Tommaso Merciai wrote:
>>>>>> Add function enable_pwm_clk into in clock_imx8mm.c. This
>>>>>> function first configure, then enable pwm clock from clock control
>>>>>> register. The following configuration is used:
>>>>>>
>>>>>> source(0) -> 24 MHz ref clock
>>>>>> div(0)    -> no division for this clock
>>>>>>
>>>>>> References:
>>>>>>     - iMX8MMRM.pdf p 303
>>>>>>
>>>>>> Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
>>>>>> ---
>>>>>> Changes since v1:
>>>>>>     - Fix enable_pwm_clk function implementation. Now is generic for all pwm clks
>>>>>>
>>>>>>     arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 ++++++++++++++++++++++++++
>>>>>>     1 file changed, 53 insertions(+)
>>>>>
>>>>> Why is this not in drivers/clk/imx/ DM driver ?
>>>>
>>>> Hi Marek,
>>>> All function that enable/configure clk from CCGR are in arch/arm/mach-imx/imx8m/clock_imx8mm.c.
>>>
>>> These seems to be CCGR:
>>>
>>> $ grep -C 2 '0x4[0-9a-f]\{3\}' drivers/clk/imx/clk-imx8mm.c | sed "s@^.@@"
>>>
>>> clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
>>>         imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
>>> clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
>>>         imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
>>> clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
>>>         imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
>>> clk_dm(IMX8MM_CLK_I2C1_ROOT,
>>>         imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
>>> clk_dm(IMX8MM_CLK_I2C2_ROOT,
>>>         imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
>>> clk_dm(IMX8MM_CLK_I2C3_ROOT,
>>>         imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
>>> clk_dm(IMX8MM_CLK_I2C4_ROOT,
>>>         imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
>>> clk_dm(IMX8MM_CLK_OCOTP_ROOT,
>>>         imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
>>> clk_dm(IMX8MM_CLK_USDHC1_ROOT,
>>>         imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
>>> clk_dm(IMX8MM_CLK_USDHC2_ROOT,
>>>         imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
>>> clk_dm(IMX8MM_CLK_WDOG1_ROOT,
>>>         imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
>>> clk_dm(IMX8MM_CLK_WDOG2_ROOT,
>>>         imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
>>> clk_dm(IMX8MM_CLK_WDOG3_ROOT,
>>>         imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
>>> clk_dm(IMX8MM_CLK_USDHC3_ROOT,
>>>         imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
>>> clk_dm(IMX8MM_CLK_QSPI_ROOT,
>>>         imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
>>> clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
>>>          imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
>>>
>>> /* clks not needed in SPL stage */
>>> -
>>> clk_dm(IMX8MM_CLK_ENET1_ROOT,
>>>         imx_clk_gate4("enet1_root_clk", "enet_axi",
>>>         base + 0x40a0, 0));
>>> endif
>>>
>>>> For that I continue to put here the implementation. After we can port
>>>> the clk dm part to manipulate clock in drivers/clk/imx/ DM driver.
>>>> What do you think about? Let me know.
>>>
>>> Seems like the clk_dm part is already in place and all you have to do is
>>> extend it.
> 
> Hi Marek,
> I test the solution using DM model, it work:
> 
> u-boot=> clk dump
> 
>   24000000             2        |   |-- pwm1
>   24000000             3        |   |   `-- pwm1_root_clk
>   24000000             0        |   |-- pwm2
>   24000000             0        |   |   `-- pwm2_root_clk
>   24000000             0        |   |-- pwm3
>   24000000             0        |   |   `-- pwm3_root_clk
>   24000000             0        |   |-- pwm4
>   24000000             0        |   |   `-- pwm4_root_clk
> 
> 
> I test it using the following call on a dummy driver:
> 
> ret = uclass_get_device_by_name(UCLASS_PWM, "pwm@30660000", &pwm);
> if (ret)
> 	printk("Failed to get pwm dev\n");
> 
> ret = clk_get_by_name(pwm, "per", &per_clk);
> if (ret) {
> 	printf("Failed to get per_clk\n");
> 	return ret;
> }
> ret = clk_enable(&per_clk);
> if (ret) {
> 	printf("Failed to enable per_clk\n");
> 	return ret;
> }
> 
> ret = clk_get_by_name(pwm, "ipg", &ipg_clk);
> if (ret) {
> 	printf("Failed to get ipg_clk\n");
> 	return ret;
> }
> ret = clk_enable(&ipg_clk);
> if (ret) {
> 	printf("Failed to enable ipg_clk\n");
> 	return ret;
> }
> 
> It's better to keep both the solutions or only
> based on DM model? I think we can put this initialization into
> drivers/pwm/pwm-imx.c imx_pwm_of_to_plat function.
> What do you think about?
> Let me know.

DM is the preferred way, non-DM is fading away.

Re: [PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function

[Tommaso Merciai]

On Thu, Mar 17, 2022 at 04:31:15PM +0100, Marek Vasut wrote:
> On 3/17/22 16:13, Tommaso Merciai wrote:
> > On Thu, Mar 17, 2022 at 01:38:18PM +0100, Tommaso Merciai wrote:
> > > On Thu, Mar 17, 2022 at 12:58:31PM +0100, Marek Vasut wrote:
> > > > On 3/17/22 08:39, Tommaso Merciai wrote:
> > > > > On Wed, Mar 16, 2022 at 09:54:34PM +0100, Marek Vasut wrote:
> > > > > > On 3/16/22 16:27, Tommaso Merciai wrote:
> > > > > > > Add function enable_pwm_clk into in clock_imx8mm.c. This
> > > > > > > function first configure, then enable pwm clock from clock control
> > > > > > > register. The following configuration is used:
> > > > > > > 
> > > > > > > source(0) -> 24 MHz ref clock
> > > > > > > div(0)    -> no division for this clock
> > > > > > > 
> > > > > > > References:
> > > > > > >     - iMX8MMRM.pdf p 303
> > > > > > > 
> > > > > > > Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> > > > > > > ---
> > > > > > > Changes since v1:
> > > > > > >     - Fix enable_pwm_clk function implementation. Now is generic for all pwm clks
> > > > > > > 
> > > > > > >     arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 ++++++++++++++++++++++++++
> > > > > > >     1 file changed, 53 insertions(+)
> > > > > > 
> > > > > > Why is this not in drivers/clk/imx/ DM driver ?
> > > > > 
> > > > > Hi Marek,
> > > > > All function that enable/configure clk from CCGR are in arch/arm/mach-imx/imx8m/clock_imx8mm.c.
> > > > 
> > > > These seems to be CCGR:
> > > > 
> > > > $ grep -C 2 '0x4[0-9a-f]\{3\}' drivers/clk/imx/clk-imx8mm.c | sed "s@^.@@"
> > > > 
> > > > clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
> > > >         imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
> > > > clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
> > > >         imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
> > > > clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
> > > >         imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
> > > > clk_dm(IMX8MM_CLK_I2C1_ROOT,
> > > >         imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
> > > > clk_dm(IMX8MM_CLK_I2C2_ROOT,
> > > >         imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
> > > > clk_dm(IMX8MM_CLK_I2C3_ROOT,
> > > >         imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
> > > > clk_dm(IMX8MM_CLK_I2C4_ROOT,
> > > >         imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
> > > > clk_dm(IMX8MM_CLK_OCOTP_ROOT,
> > > >         imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
> > > > clk_dm(IMX8MM_CLK_USDHC1_ROOT,
> > > >         imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
> > > > clk_dm(IMX8MM_CLK_USDHC2_ROOT,
> > > >         imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
> > > > clk_dm(IMX8MM_CLK_WDOG1_ROOT,
> > > >         imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
> > > > clk_dm(IMX8MM_CLK_WDOG2_ROOT,
> > > >         imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
> > > > clk_dm(IMX8MM_CLK_WDOG3_ROOT,
> > > >         imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
> > > > clk_dm(IMX8MM_CLK_USDHC3_ROOT,
> > > >         imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
> > > > clk_dm(IMX8MM_CLK_QSPI_ROOT,
> > > >         imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
> > > > clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
> > > >          imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
> > > > 
> > > > /* clks not needed in SPL stage */
> > > > -
> > > > clk_dm(IMX8MM_CLK_ENET1_ROOT,
> > > >         imx_clk_gate4("enet1_root_clk", "enet_axi",
> > > >         base + 0x40a0, 0));
> > > > endif
> > > > 
> > > > > For that I continue to put here the implementation. After we can port
> > > > > the clk dm part to manipulate clock in drivers/clk/imx/ DM driver.
> > > > > What do you think about? Let me know.
> > > > 
> > > > Seems like the clk_dm part is already in place and all you have to do is
> > > > extend it.
> > 
> > Hi Marek,
> > I test the solution using DM model, it work:
> > 
> > u-boot=> clk dump
> > 
> >   24000000             2        |   |-- pwm1
> >   24000000             3        |   |   `-- pwm1_root_clk
> >   24000000             0        |   |-- pwm2
> >   24000000             0        |   |   `-- pwm2_root_clk
> >   24000000             0        |   |-- pwm3
> >   24000000             0        |   |   `-- pwm3_root_clk
> >   24000000             0        |   |-- pwm4
> >   24000000             0        |   |   `-- pwm4_root_clk
> > 
> > 
> > I test it using the following call on a dummy driver:
> > 
> > ret = uclass_get_device_by_name(UCLASS_PWM, "pwm@30660000", &pwm);
> > if (ret)
> > 	printk("Failed to get pwm dev\n");
> > 
> > ret = clk_get_by_name(pwm, "per", &per_clk);
> > if (ret) {
> > 	printf("Failed to get per_clk\n");
> > 	return ret;
> > }
> > ret = clk_enable(&per_clk);
> > if (ret) {
> > 	printf("Failed to enable per_clk\n");
> > 	return ret;
> > }
> > 
> > ret = clk_get_by_name(pwm, "ipg", &ipg_clk);
> > if (ret) {
> > 	printf("Failed to get ipg_clk\n");
> > 	return ret;
> > }
> > ret = clk_enable(&ipg_clk);
> > if (ret) {
> > 	printf("Failed to enable ipg_clk\n");
> > 	return ret;
> > }
> > 
> > It's better to keep both the solutions or only
> > based on DM model? I think we can put this initialization into
> > drivers/pwm/pwm-imx.c imx_pwm_of_to_plat function.
> > What do you think about?
> > Let me know.
> 
> DM is the preferred way, non-DM is fading away.

Hi All,
I'm working on pwm-imx drv, what do you think about move pwm-imx-utils
and put all the 2 function inside pwm-imx.c under an ifndef
CONFIG_DM_PWM. Using DM on pwm-imx make pwm-imx-utils.c no sense to exist. 

Example:

#ifndef CONFIG_DM_PWM
int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned long *period_c,
		      unsigned long *duty_c, unsigned long *prescale){
....

struct pwm_regs *pwm_id_to_reg(int pwm_id)
{
...

+ all non dm implementation

#else 

struct imx_pwm_priv {
	struct pwm_regs *regs;
	bool invert;
	struct clk *per_clk;
	struct clk *ipg_clk;
};

int pwm_dm_imx_get_parms(struct imx_pwm_priv *priv, int period_ns,
		      int duty_ns, unsigned long *period_c, unsigned long *duty_c,
		      unsigned long *prescale)
{
....

+ all dm implementation

#endif

What do you think about?
Let me know.

Thanks
Tommaso


-- 
Tommaso Merciai
Embedded Linux Engineer
tommaso.merciai@amarulasolutions.com
__________________________________

Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
info@amarulasolutions.com
www.amarulasolutions.com