* [Intel-gfx] [PATCH 01/13] drm/i915: Make .get_dplls() return int
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
@ 2022-03-25 12:31 ` Ville Syrjala
2022-03-28 10:57 ` Jani Nikula
2022-03-25 12:31 ` [Intel-gfx] [PATCH 02/13] drm/i915: Pass dev_priv to intel_shared_dpll_init() Ville Syrjala
` (30 subsequent siblings)
31 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2022-03-25 12:31 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Get rid of the confusing back and forth between bools and ints
in the .get_dplls() stuff. Just make everything return an int.
Initial conversion done with cocci, with some manual fixups on top:
@find@
identifier func !~ "get_hw_state|_is_|needed";
typedef bool;
parameter list[N] P;
@@
- bool
+ int
func(P)
{
<...
(
- return true;
+ return 0;
|
- return false;
+ return -EINVAL;
)
...>
}
@@
identifier find.func;
expression list[find.N] E;
expression X;
@@
- if (!func(E))
+ ret = func(E);
+ if (ret)
{
...
- return X;
+ return ret;
}
@@
identifier find.func;
expression X;
expression list[find.N] E;
@@
- if (!func(E))
+ ret = func(E);
+ if (ret)
- return X;
+ return ret;
@@
identifier find.func;
expression list[find.N] E;
expression O, X;
typedef bool;
bool B;
@@
- B = func(E);
- if (O && !B)
+ if (O) {
+ ret = func(E);
+ if (ret)
- return X;
+ return ret;
+ }
@@
identifier find.func;
expression list[find.N] E;
expression O, X;
@@
- if (O && !func(E))
+ if (O) {
+ ret = func(E);
+ if (ret)
- return X;
+ return ret;
+ }
@@
identifier find.func;
expression list[find.N] E;
expression X;
typedef bool;
bool B;
@@
- B = func(E);
- if (!B)
+ ret = func(E);
+ if (ret)
{
...
- return X;
+ return ret;
}
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 12 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 242 +++++++++---------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 6 +-
3 files changed, 131 insertions(+), 129 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 95b9d327ed4d..1bd4a05dff7c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -935,6 +935,7 @@ static int hsw_crtc_compute_clock(struct intel_crtc_state *crtc_state)
to_intel_atomic_state(crtc_state->uapi.state);
struct intel_encoder *encoder =
intel_get_crtc_new_encoder(state, crtc_state);
+ int ret;
if (IS_DG2(dev_priv))
return intel_mpllb_calc_state(crtc_state, encoder);
@@ -943,11 +944,12 @@ static int hsw_crtc_compute_clock(struct intel_crtc_state *crtc_state)
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
return 0;
- if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
+ ret = intel_reserve_shared_dplls(state, crtc, encoder);
+ if (ret) {
drm_dbg_kms(&dev_priv->drm,
"failed to find PLL for pipe %c\n",
pipe_name(crtc->pipe));
- return -EINVAL;
+ return ret;
}
return 0;
@@ -1076,6 +1078,7 @@ static int ilk_crtc_compute_clock(struct intel_crtc_state *crtc_state)
to_intel_atomic_state(crtc_state->uapi.state);
const struct intel_limit *limit;
int refclk = 120000;
+ int ret;
memset(&crtc_state->dpll_hw_state, 0,
sizeof(crtc_state->dpll_hw_state));
@@ -1118,11 +1121,12 @@ static int ilk_crtc_compute_clock(struct intel_crtc_state *crtc_state)
ilk_compute_dpll(crtc_state, &crtc_state->dpll,
&crtc_state->dpll);
- if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
+ ret = intel_reserve_shared_dplls(state, crtc, NULL);
+ if (ret) {
drm_dbg_kms(&dev_priv->drm,
"failed to find PLL for pipe %c\n",
pipe_name(crtc->pipe));
- return -EINVAL;
+ return ret;
}
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index b7071da4b7e5..1d52796333ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -90,9 +90,9 @@ struct intel_shared_dpll_funcs {
struct intel_dpll_mgr {
const struct dpll_info *dpll_info;
- bool (*get_dplls)(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder);
+ int (*get_dplls)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder);
void (*put_dplls)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void (*update_active_dpll)(struct intel_atomic_state *state,
@@ -514,9 +514,9 @@ static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
udelay(200);
}
-static bool ibx_get_dpll(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder)
+static int ibx_get_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
@@ -541,7 +541,7 @@ static bool ibx_get_dpll(struct intel_atomic_state *state,
}
if (!pll)
- return false;
+ return -EINVAL;
/* reference the pll */
intel_reference_shared_dpll(state, crtc,
@@ -549,7 +549,7 @@ static bool ibx_get_dpll(struct intel_atomic_state *state,
crtc_state->shared_dpll = pll;
- return true;
+ return 0;
}
static void ibx_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -584,7 +584,7 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
};
static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
- struct intel_shared_dpll *pll)
+ struct intel_shared_dpll *pll)
{
const enum intel_dpll_id id = pll->info->id;
@@ -1060,13 +1060,13 @@ static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
return link_clock * 2;
}
-static bool hsw_get_dpll(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder)
+static int hsw_get_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct intel_shared_dpll *pll;
+ struct intel_shared_dpll *pll = NULL;
memset(&crtc_state->dpll_hw_state, 0,
sizeof(crtc_state->dpll_hw_state));
@@ -1077,18 +1077,16 @@ static bool hsw_get_dpll(struct intel_atomic_state *state,
pll = hsw_ddi_lcpll_get_dpll(crtc_state);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
pll = hsw_ddi_spll_get_dpll(state, crtc);
- else
- return false;
if (!pll)
- return false;
+ return -EINVAL;
intel_reference_shared_dpll(state, crtc,
pll, &crtc_state->dpll_hw_state);
crtc_state->shared_dpll = pll;
- return true;
+ return 0;
}
static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915)
@@ -1493,7 +1491,7 @@ static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
params->dco_integer * MHz(1)) * 0x8000, MHz(1));
}
-static bool
+static int
skl_ddi_calculate_wrpll(int clock /* in Hz */,
int ref_clock,
struct skl_wrpll_params *wrpll_params)
@@ -1552,7 +1550,7 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
if (!ctx.p) {
DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
- return false;
+ return -EINVAL;
}
/*
@@ -1564,14 +1562,15 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
skl_wrpll_params_populate(wrpll_params, afe_clock, ref_clock,
ctx.central_freq, p0, p1, p2);
- return true;
+ return 0;
}
-static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
+static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
struct skl_wrpll_params wrpll_params = {};
u32 ctrl1, cfgcr1, cfgcr2;
+ int ret;
/*
* See comment in intel_dpll_hw_state to understand why we always use 0
@@ -1581,10 +1580,10 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
- if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
- i915->dpll.ref_clks.nssc,
- &wrpll_params))
- return false;
+ ret = skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
+ i915->dpll.ref_clks.nssc, &wrpll_params);
+ if (ret)
+ return ret;
cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
@@ -1602,7 +1601,8 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
crtc_state->dpll_hw_state.ctrl1 = ctrl1;
crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
- return true;
+
+ return 0;
}
static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
@@ -1676,7 +1676,7 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
return dco_freq / (p0 * p1 * p2 * 5);
}
-static bool
+static int
skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
{
u32 ctrl1;
@@ -1713,7 +1713,7 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
crtc_state->dpll_hw_state.ctrl1 = ctrl1;
- return true;
+ return 0;
}
static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
@@ -1750,33 +1750,23 @@ static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
return link_clock * 2;
}
-static bool skl_get_dpll(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder)
+static int skl_get_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll;
- bool bret;
+ int ret;
- if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
- bret = skl_ddi_hdmi_pll_dividers(crtc_state);
- if (!bret) {
- drm_dbg_kms(&i915->drm,
- "Could not get HDMI pll dividers.\n");
- return false;
- }
- } else if (intel_crtc_has_dp_encoder(crtc_state)) {
- bret = skl_ddi_dp_set_dpll_hw_state(crtc_state);
- if (!bret) {
- drm_dbg_kms(&i915->drm,
- "Could not set DP dpll HW state.\n");
- return false;
- }
- } else {
- return false;
- }
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ ret = skl_ddi_hdmi_pll_dividers(crtc_state);
+ else if (intel_crtc_has_dp_encoder(crtc_state))
+ ret = skl_ddi_dp_set_dpll_hw_state(crtc_state);
+ else
+ ret = -EINVAL;
+ if (ret)
+ return ret;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
pll = intel_find_shared_dpll(state, crtc,
@@ -1789,14 +1779,14 @@ static bool skl_get_dpll(struct intel_atomic_state *state,
BIT(DPLL_ID_SKL_DPLL2) |
BIT(DPLL_ID_SKL_DPLL1));
if (!pll)
- return false;
+ return -EINVAL;
intel_reference_shared_dpll(state, crtc,
pll, &crtc_state->dpll_hw_state);
crtc_state->shared_dpll = pll;
- return true;
+ return 0;
}
static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
@@ -2095,7 +2085,7 @@ static const struct dpll bxt_dp_clk_val[] = {
{ .dot = 432000, .p1 = 3, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
};
-static bool
+static int
bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
struct dpll *clk_div)
{
@@ -2111,12 +2101,12 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
drm_dbg(&i915->drm, "no PLL dividers found for clock %d pipe %c\n",
crtc_state->port_clock,
pipe_name(crtc->pipe));
- return false;
+ return -EINVAL;
}
drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
- return true;
+ return 0;
}
static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
@@ -2139,8 +2129,8 @@ static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
clk_div->dot != crtc_state->port_clock);
}
-static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
- const struct dpll *clk_div)
+static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
+ const struct dpll *clk_div)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state;
@@ -2169,7 +2159,7 @@ static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
targ_cnt = 9;
} else {
drm_err(&i915->drm, "Invalid VCO\n");
- return false;
+ return -EINVAL;
}
if (clock > 270000)
@@ -2206,10 +2196,10 @@ static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
dpll_hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger;
- return true;
+ return 0;
}
-static bool
+static int
bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
{
struct dpll clk_div = {};
@@ -2219,7 +2209,7 @@ bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
}
-static bool
+static int
bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
{
struct dpll clk_div = {};
@@ -2246,23 +2236,25 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock);
}
-static bool bxt_get_dpll(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder)
+static int bxt_get_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll;
enum intel_dpll_id id;
+ int ret;
- if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
- !bxt_ddi_hdmi_set_dpll_hw_state(crtc_state))
- return false;
-
- if (intel_crtc_has_dp_encoder(crtc_state) &&
- !bxt_ddi_dp_set_dpll_hw_state(crtc_state))
- return false;
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ ret = bxt_ddi_hdmi_set_dpll_hw_state(crtc_state);
+ else if (intel_crtc_has_dp_encoder(crtc_state))
+ ret = bxt_ddi_dp_set_dpll_hw_state(crtc_state);
+ else
+ ret = -EINVAL;
+ if (ret)
+ return ret;
/* 1:1 mapping between ports and PLLs */
id = (enum intel_dpll_id) encoder->port;
@@ -2276,7 +2268,7 @@ static bool bxt_get_dpll(struct intel_atomic_state *state,
crtc_state->shared_dpll = pll;
- return true;
+ return 0;
}
static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915)
@@ -2513,8 +2505,8 @@ static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
/* the following params are unused */
};
-static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
- struct skl_wrpll_params *pll_params)
+static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
+ struct skl_wrpll_params *pll_params)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
const struct icl_combo_pll_params *params =
@@ -2527,16 +2519,16 @@ static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
for (i = 0; i < ARRAY_SIZE(icl_dp_combo_pll_24MHz_values); i++) {
if (clock == params[i].clock) {
*pll_params = params[i].wrpll;
- return true;
+ return 0;
}
}
MISSING_CASE(clock);
- return false;
+ return -EINVAL;
}
-static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
- struct skl_wrpll_params *pll_params)
+static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
+ struct skl_wrpll_params *pll_params)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
@@ -2568,7 +2560,7 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
}
}
- return true;
+ return 0;
}
static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
@@ -2598,7 +2590,7 @@ static int icl_wrpll_ref_clock(struct drm_i915_private *i915)
return ref_clock;
}
-static bool
+static int
icl_calc_wrpll(struct intel_crtc_state *crtc_state,
struct skl_wrpll_params *wrpll_params)
{
@@ -2633,13 +2625,13 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
}
if (best_div == 0)
- return false;
+ return -EINVAL;
icl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
icl_wrpll_params_populate(wrpll_params, best_dco, ref_clock,
pdiv, qdiv, kdiv);
- return true;
+ return 0;
}
static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
@@ -2731,10 +2723,10 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
pll_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->vbt.override_afc_startup_val);
}
-static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
- u32 *target_dco_khz,
- struct intel_dpll_hw_state *state,
- bool is_dkl)
+static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
+ u32 *target_dco_khz,
+ struct intel_dpll_hw_state *state,
+ bool is_dkl)
{
static const u8 div1_vals[] = { 7, 5, 3, 2 };
u32 dco_min_freq, dco_max_freq;
@@ -2800,19 +2792,19 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
hsdiv |
MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2);
- return true;
+ return 0;
}
}
- return false;
+ return -EINVAL;
}
/*
* The specification for this function uses real numbers, so the math had to be
* adapted to integer-only calculation, that's why it looks so different.
*/
-static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
- struct intel_dpll_hw_state *pll_state)
+static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
+ struct intel_dpll_hw_state *pll_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int refclk_khz = dev_priv->dpll.ref_clks.nssc;
@@ -2826,14 +2818,16 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
bool use_ssc = false;
bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
bool is_dkl = DISPLAY_VER(dev_priv) >= 12;
+ int ret;
memset(pll_state, 0, sizeof(*pll_state));
- if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
- pll_state, is_dkl)) {
+ ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
+ pll_state, is_dkl);
+ if (ret) {
drm_dbg_kms(&dev_priv->drm,
"Failed to find divisors for clock %d\n", clock);
- return false;
+ return ret;
}
m1div = 2;
@@ -2848,7 +2842,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
drm_dbg_kms(&dev_priv->drm,
"Failed to find mdiv for clock %d\n",
clock);
- return false;
+ return -EINVAL;
}
}
m2div_rem = dco_khz % (refclk_khz * m1div);
@@ -2875,7 +2869,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
break;
default:
MISSING_CASE(refclk_khz);
- return false;
+ return -EINVAL;
}
/*
@@ -3018,7 +3012,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
}
- return true;
+ return 0;
}
static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv,
@@ -3140,9 +3134,9 @@ static u32 intel_get_hti_plls(struct drm_i915_private *i915)
return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->hti_state);
}
-static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder)
+static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
@@ -3160,11 +3154,10 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
else
ret = icl_calc_dp_combo_pll(crtc_state, &pll_params);
- if (!ret) {
+ if (ret) {
drm_dbg_kms(&dev_priv->drm,
"Could not calculate combo PHY PLL state.\n");
-
- return false;
+ return ret;
}
icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
@@ -3209,7 +3202,7 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
drm_dbg_kms(&dev_priv->drm,
"No combo PHY PLL found for [ENCODER:%d:%s]\n",
encoder->base.base.id, encoder->base.name);
- return false;
+ return -EINVAL;
}
intel_reference_shared_dpll(state, crtc,
@@ -3217,12 +3210,12 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
icl_update_active_dpll(state, crtc, encoder);
- return true;
+ return 0;
}
-static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder)
+static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state =
@@ -3230,12 +3223,14 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
struct skl_wrpll_params pll_params = { };
struct icl_port_dpll *port_dpll;
enum intel_dpll_id dpll_id;
+ int ret;
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
- if (!icl_calc_tbt_pll(crtc_state, &pll_params)) {
+ ret = icl_calc_tbt_pll(crtc_state, &pll_params);
+ if (ret) {
drm_dbg_kms(&dev_priv->drm,
"Could not calculate TBT PLL state.\n");
- return false;
+ return ret;
}
icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
@@ -3245,14 +3240,15 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
BIT(DPLL_ID_ICL_TBTPLL));
if (!port_dpll->pll) {
drm_dbg_kms(&dev_priv->drm, "No TBT-ALT PLL found\n");
- return false;
+ return -EINVAL;
}
intel_reference_shared_dpll(state, crtc,
port_dpll->pll, &port_dpll->hw_state);
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
- if (!icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state)) {
+ ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
+ if (ret) {
drm_dbg_kms(&dev_priv->drm,
"Could not calculate MG PHY PLL state.\n");
goto err_unreference_tbt_pll;
@@ -3264,6 +3260,7 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
&port_dpll->hw_state,
BIT(dpll_id));
if (!port_dpll->pll) {
+ ret = -EINVAL;
drm_dbg_kms(&dev_priv->drm, "No MG PHY PLL found\n");
goto err_unreference_tbt_pll;
}
@@ -3272,18 +3269,18 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
icl_update_active_dpll(state, crtc, encoder);
- return true;
+ return 0;
err_unreference_tbt_pll:
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
intel_unreference_shared_dpll(state, crtc, port_dpll->pll);
- return false;
+ return ret;
}
-static bool icl_get_dplls(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder)
+static int icl_get_dplls(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
@@ -3295,7 +3292,7 @@ static bool icl_get_dplls(struct intel_atomic_state *state,
MISSING_CASE(phy);
- return false;
+ return -EINVAL;
}
static void icl_put_dplls(struct intel_atomic_state *state,
@@ -4154,17 +4151,18 @@ void intel_shared_dpll_init(struct drm_device *dev)
* intel_release_shared_dplls().
*
* Returns:
- * True if all required DPLLs were successfully reserved.
+ * 0 if all required DPLLs were successfully reserved,
+ * negative error code otherwise.
*/
-bool intel_reserve_shared_dplls(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder)
+int intel_reserve_shared_dplls(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
- return false;
+ return -EINVAL;
return dpll_mgr->get_dplls(state, crtc, encoder);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index ba2fdfce1579..499a43e39123 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -337,9 +337,9 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
bool state);
#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
-bool intel_reserve_shared_dplls(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder);
+int intel_reserve_shared_dplls(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder);
void intel_release_shared_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
--
2.34.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [Intel-gfx] [PATCH 01/13] drm/i915: Make .get_dplls() return int
2022-03-25 12:31 ` [Intel-gfx] [PATCH 01/13] drm/i915: Make .get_dplls() return int Ville Syrjala
@ 2022-03-28 10:57 ` Jani Nikula
0 siblings, 0 replies; 44+ messages in thread
From: Jani Nikula @ 2022-03-28 10:57 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 25 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Get rid of the confusing back and forth between bools and ints
> in the .get_dplls() stuff. Just make everything return an int.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
There was at least one call to bxt_ddi_hdmi_pll_dividers() where the
return value wasn't propagated, and perhaps should. That's a functional
change that's not part of this patch, however.
>
> Initial conversion done with cocci, with some manual fixups on top:
> @find@
> identifier func !~ "get_hw_state|_is_|needed";
> typedef bool;
> parameter list[N] P;
> @@
> - bool
> + int
> func(P)
> {
> <...
> (
> - return true;
> + return 0;
> |
> - return false;
> + return -EINVAL;
> )
> ...>
> }
>
> @@
> identifier find.func;
> expression list[find.N] E;
> expression X;
> @@
> - if (!func(E))
> + ret = func(E);
> + if (ret)
> {
> ...
> - return X;
> + return ret;
> }
>
> @@
> identifier find.func;
> expression X;
> expression list[find.N] E;
> @@
> - if (!func(E))
> + ret = func(E);
> + if (ret)
> - return X;
> + return ret;
>
> @@
> identifier find.func;
> expression list[find.N] E;
> expression O, X;
> typedef bool;
> bool B;
> @@
> - B = func(E);
> - if (O && !B)
> + if (O) {
> + ret = func(E);
> + if (ret)
> - return X;
> + return ret;
> + }
>
> @@
> identifier find.func;
> expression list[find.N] E;
> expression O, X;
> @@
> - if (O && !func(E))
> + if (O) {
> + ret = func(E);
> + if (ret)
> - return X;
> + return ret;
> + }
>
> @@
> identifier find.func;
> expression list[find.N] E;
> expression X;
> typedef bool;
> bool B;
> @@
> - B = func(E);
> - if (!B)
> + ret = func(E);
> + if (ret)
> {
> ...
> - return X;
> + return ret;
> }
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll.c | 12 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 242 +++++++++---------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 6 +-
> 3 files changed, 131 insertions(+), 129 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 95b9d327ed4d..1bd4a05dff7c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -935,6 +935,7 @@ static int hsw_crtc_compute_clock(struct intel_crtc_state *crtc_state)
> to_intel_atomic_state(crtc_state->uapi.state);
> struct intel_encoder *encoder =
> intel_get_crtc_new_encoder(state, crtc_state);
> + int ret;
>
> if (IS_DG2(dev_priv))
> return intel_mpllb_calc_state(crtc_state, encoder);
> @@ -943,11 +944,12 @@ static int hsw_crtc_compute_clock(struct intel_crtc_state *crtc_state)
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> return 0;
>
> - if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
> + ret = intel_reserve_shared_dplls(state, crtc, encoder);
> + if (ret) {
> drm_dbg_kms(&dev_priv->drm,
> "failed to find PLL for pipe %c\n",
> pipe_name(crtc->pipe));
> - return -EINVAL;
> + return ret;
> }
>
> return 0;
> @@ -1076,6 +1078,7 @@ static int ilk_crtc_compute_clock(struct intel_crtc_state *crtc_state)
> to_intel_atomic_state(crtc_state->uapi.state);
> const struct intel_limit *limit;
> int refclk = 120000;
> + int ret;
>
> memset(&crtc_state->dpll_hw_state, 0,
> sizeof(crtc_state->dpll_hw_state));
> @@ -1118,11 +1121,12 @@ static int ilk_crtc_compute_clock(struct intel_crtc_state *crtc_state)
> ilk_compute_dpll(crtc_state, &crtc_state->dpll,
> &crtc_state->dpll);
>
> - if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
> + ret = intel_reserve_shared_dplls(state, crtc, NULL);
> + if (ret) {
> drm_dbg_kms(&dev_priv->drm,
> "failed to find PLL for pipe %c\n",
> pipe_name(crtc->pipe));
> - return -EINVAL;
> + return ret;
> }
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index b7071da4b7e5..1d52796333ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -90,9 +90,9 @@ struct intel_shared_dpll_funcs {
> struct intel_dpll_mgr {
> const struct dpll_info *dpll_info;
>
> - bool (*get_dplls)(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct intel_encoder *encoder);
> + int (*get_dplls)(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder);
> void (*put_dplls)(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> void (*update_active_dpll)(struct intel_atomic_state *state,
> @@ -514,9 +514,9 @@ static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
> udelay(200);
> }
>
> -static bool ibx_get_dpll(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct intel_encoder *encoder)
> +static int ibx_get_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder)
> {
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> @@ -541,7 +541,7 @@ static bool ibx_get_dpll(struct intel_atomic_state *state,
> }
>
> if (!pll)
> - return false;
> + return -EINVAL;
>
> /* reference the pll */
> intel_reference_shared_dpll(state, crtc,
> @@ -549,7 +549,7 @@ static bool ibx_get_dpll(struct intel_atomic_state *state,
>
> crtc_state->shared_dpll = pll;
>
> - return true;
> + return 0;
> }
>
> static void ibx_dump_hw_state(struct drm_i915_private *dev_priv,
> @@ -584,7 +584,7 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
> };
>
> static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
> - struct intel_shared_dpll *pll)
> + struct intel_shared_dpll *pll)
> {
> const enum intel_dpll_id id = pll->info->id;
>
> @@ -1060,13 +1060,13 @@ static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
> return link_clock * 2;
> }
>
> -static bool hsw_get_dpll(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct intel_encoder *encoder)
> +static int hsw_get_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder)
> {
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - struct intel_shared_dpll *pll;
> + struct intel_shared_dpll *pll = NULL;
>
> memset(&crtc_state->dpll_hw_state, 0,
> sizeof(crtc_state->dpll_hw_state));
> @@ -1077,18 +1077,16 @@ static bool hsw_get_dpll(struct intel_atomic_state *state,
> pll = hsw_ddi_lcpll_get_dpll(crtc_state);
> else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
> pll = hsw_ddi_spll_get_dpll(state, crtc);
> - else
> - return false;
>
> if (!pll)
> - return false;
> + return -EINVAL;
>
> intel_reference_shared_dpll(state, crtc,
> pll, &crtc_state->dpll_hw_state);
>
> crtc_state->shared_dpll = pll;
>
> - return true;
> + return 0;
> }
>
> static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915)
> @@ -1493,7 +1491,7 @@ static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
> params->dco_integer * MHz(1)) * 0x8000, MHz(1));
> }
>
> -static bool
> +static int
> skl_ddi_calculate_wrpll(int clock /* in Hz */,
> int ref_clock,
> struct skl_wrpll_params *wrpll_params)
> @@ -1552,7 +1550,7 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
>
> if (!ctx.p) {
> DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
> - return false;
> + return -EINVAL;
> }
>
> /*
> @@ -1564,14 +1562,15 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
> skl_wrpll_params_populate(wrpll_params, afe_clock, ref_clock,
> ctx.central_freq, p0, p1, p2);
>
> - return true;
> + return 0;
> }
>
> -static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
> +static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> struct skl_wrpll_params wrpll_params = {};
> u32 ctrl1, cfgcr1, cfgcr2;
> + int ret;
>
> /*
> * See comment in intel_dpll_hw_state to understand why we always use 0
> @@ -1581,10 +1580,10 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
>
> ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
>
> - if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
> - i915->dpll.ref_clks.nssc,
> - &wrpll_params))
> - return false;
> + ret = skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
> + i915->dpll.ref_clks.nssc, &wrpll_params);
> + if (ret)
> + return ret;
>
> cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
> DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
> @@ -1602,7 +1601,8 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
> crtc_state->dpll_hw_state.ctrl1 = ctrl1;
> crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
> crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
> - return true;
> +
> + return 0;
> }
>
> static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> @@ -1676,7 +1676,7 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> return dco_freq / (p0 * p1 * p2 * 5);
> }
>
> -static bool
> +static int
> skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> {
> u32 ctrl1;
> @@ -1713,7 +1713,7 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
>
> crtc_state->dpll_hw_state.ctrl1 = ctrl1;
>
> - return true;
> + return 0;
> }
>
> static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
> @@ -1750,33 +1750,23 @@ static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
> return link_clock * 2;
> }
>
> -static bool skl_get_dpll(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct intel_encoder *encoder)
> +static int skl_get_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder)
> {
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> struct intel_shared_dpll *pll;
> - bool bret;
> + int ret;
>
> - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> - bret = skl_ddi_hdmi_pll_dividers(crtc_state);
> - if (!bret) {
> - drm_dbg_kms(&i915->drm,
> - "Could not get HDMI pll dividers.\n");
> - return false;
> - }
> - } else if (intel_crtc_has_dp_encoder(crtc_state)) {
> - bret = skl_ddi_dp_set_dpll_hw_state(crtc_state);
> - if (!bret) {
> - drm_dbg_kms(&i915->drm,
> - "Could not set DP dpll HW state.\n");
> - return false;
> - }
> - } else {
> - return false;
> - }
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> + ret = skl_ddi_hdmi_pll_dividers(crtc_state);
> + else if (intel_crtc_has_dp_encoder(crtc_state))
> + ret = skl_ddi_dp_set_dpll_hw_state(crtc_state);
> + else
> + ret = -EINVAL;
> + if (ret)
> + return ret;
>
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> pll = intel_find_shared_dpll(state, crtc,
> @@ -1789,14 +1779,14 @@ static bool skl_get_dpll(struct intel_atomic_state *state,
> BIT(DPLL_ID_SKL_DPLL2) |
> BIT(DPLL_ID_SKL_DPLL1));
> if (!pll)
> - return false;
> + return -EINVAL;
>
> intel_reference_shared_dpll(state, crtc,
> pll, &crtc_state->dpll_hw_state);
>
> crtc_state->shared_dpll = pll;
>
> - return true;
> + return 0;
> }
>
> static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
> @@ -2095,7 +2085,7 @@ static const struct dpll bxt_dp_clk_val[] = {
> { .dot = 432000, .p1 = 3, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
> };
>
> -static bool
> +static int
> bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
> struct dpll *clk_div)
> {
> @@ -2111,12 +2101,12 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
> drm_dbg(&i915->drm, "no PLL dividers found for clock %d pipe %c\n",
> crtc_state->port_clock,
> pipe_name(crtc->pipe));
> - return false;
> + return -EINVAL;
> }
>
> drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
>
> - return true;
> + return 0;
> }
>
> static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
> @@ -2139,8 +2129,8 @@ static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
> clk_div->dot != crtc_state->port_clock);
> }
>
> -static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
> - const struct dpll *clk_div)
> +static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
> + const struct dpll *clk_div)
> {
> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state;
> @@ -2169,7 +2159,7 @@ static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
> targ_cnt = 9;
> } else {
> drm_err(&i915->drm, "Invalid VCO\n");
> - return false;
> + return -EINVAL;
> }
>
> if (clock > 270000)
> @@ -2206,10 +2196,10 @@ static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
>
> dpll_hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger;
>
> - return true;
> + return 0;
> }
>
> -static bool
> +static int
> bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> {
> struct dpll clk_div = {};
> @@ -2219,7 +2209,7 @@ bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
> }
>
> -static bool
> +static int
> bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> {
> struct dpll clk_div = {};
> @@ -2246,23 +2236,25 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
> return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock);
> }
>
> -static bool bxt_get_dpll(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct intel_encoder *encoder)
> +static int bxt_get_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder)
> {
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_shared_dpll *pll;
> enum intel_dpll_id id;
> + int ret;
>
> - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> - !bxt_ddi_hdmi_set_dpll_hw_state(crtc_state))
> - return false;
> -
> - if (intel_crtc_has_dp_encoder(crtc_state) &&
> - !bxt_ddi_dp_set_dpll_hw_state(crtc_state))
> - return false;
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> + ret = bxt_ddi_hdmi_set_dpll_hw_state(crtc_state);
> + else if (intel_crtc_has_dp_encoder(crtc_state))
> + ret = bxt_ddi_dp_set_dpll_hw_state(crtc_state);
> + else
> + ret = -EINVAL;
> + if (ret)
> + return ret;
>
> /* 1:1 mapping between ports and PLLs */
> id = (enum intel_dpll_id) encoder->port;
> @@ -2276,7 +2268,7 @@ static bool bxt_get_dpll(struct intel_atomic_state *state,
>
> crtc_state->shared_dpll = pll;
>
> - return true;
> + return 0;
> }
>
> static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915)
> @@ -2513,8 +2505,8 @@ static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
> /* the following params are unused */
> };
>
> -static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
> - struct skl_wrpll_params *pll_params)
> +static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
> + struct skl_wrpll_params *pll_params)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> const struct icl_combo_pll_params *params =
> @@ -2527,16 +2519,16 @@ static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
> for (i = 0; i < ARRAY_SIZE(icl_dp_combo_pll_24MHz_values); i++) {
> if (clock == params[i].clock) {
> *pll_params = params[i].wrpll;
> - return true;
> + return 0;
> }
> }
>
> MISSING_CASE(clock);
> - return false;
> + return -EINVAL;
> }
>
> -static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
> - struct skl_wrpll_params *pll_params)
> +static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
> + struct skl_wrpll_params *pll_params)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> @@ -2568,7 +2560,7 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
> }
> }
>
> - return true;
> + return 0;
> }
>
> static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
> @@ -2598,7 +2590,7 @@ static int icl_wrpll_ref_clock(struct drm_i915_private *i915)
> return ref_clock;
> }
>
> -static bool
> +static int
> icl_calc_wrpll(struct intel_crtc_state *crtc_state,
> struct skl_wrpll_params *wrpll_params)
> {
> @@ -2633,13 +2625,13 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
> }
>
> if (best_div == 0)
> - return false;
> + return -EINVAL;
>
> icl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
> icl_wrpll_params_populate(wrpll_params, best_dco, ref_clock,
> pdiv, qdiv, kdiv);
>
> - return true;
> + return 0;
> }
>
> static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
> @@ -2731,10 +2723,10 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
> pll_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->vbt.override_afc_startup_val);
> }
>
> -static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
> - u32 *target_dco_khz,
> - struct intel_dpll_hw_state *state,
> - bool is_dkl)
> +static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
> + u32 *target_dco_khz,
> + struct intel_dpll_hw_state *state,
> + bool is_dkl)
> {
> static const u8 div1_vals[] = { 7, 5, 3, 2 };
> u32 dco_min_freq, dco_max_freq;
> @@ -2800,19 +2792,19 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
> hsdiv |
> MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2);
>
> - return true;
> + return 0;
> }
> }
>
> - return false;
> + return -EINVAL;
> }
>
> /*
> * The specification for this function uses real numbers, so the math had to be
> * adapted to integer-only calculation, that's why it looks so different.
> */
> -static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> - struct intel_dpll_hw_state *pll_state)
> +static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> + struct intel_dpll_hw_state *pll_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> int refclk_khz = dev_priv->dpll.ref_clks.nssc;
> @@ -2826,14 +2818,16 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> bool use_ssc = false;
> bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
> bool is_dkl = DISPLAY_VER(dev_priv) >= 12;
> + int ret;
>
> memset(pll_state, 0, sizeof(*pll_state));
>
> - if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
> - pll_state, is_dkl)) {
> + ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
> + pll_state, is_dkl);
> + if (ret) {
> drm_dbg_kms(&dev_priv->drm,
> "Failed to find divisors for clock %d\n", clock);
> - return false;
> + return ret;
> }
>
> m1div = 2;
> @@ -2848,7 +2842,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> drm_dbg_kms(&dev_priv->drm,
> "Failed to find mdiv for clock %d\n",
> clock);
> - return false;
> + return -EINVAL;
> }
> }
> m2div_rem = dco_khz % (refclk_khz * m1div);
> @@ -2875,7 +2869,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> break;
> default:
> MISSING_CASE(refclk_khz);
> - return false;
> + return -EINVAL;
> }
>
> /*
> @@ -3018,7 +3012,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
> }
>
> - return true;
> + return 0;
> }
>
> static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv,
> @@ -3140,9 +3134,9 @@ static u32 intel_get_hti_plls(struct drm_i915_private *i915)
> return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->hti_state);
> }
>
> -static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct intel_encoder *encoder)
> +static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder)
> {
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> @@ -3160,11 +3154,10 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> else
> ret = icl_calc_dp_combo_pll(crtc_state, &pll_params);
>
> - if (!ret) {
> + if (ret) {
> drm_dbg_kms(&dev_priv->drm,
> "Could not calculate combo PHY PLL state.\n");
> -
> - return false;
> + return ret;
> }
>
> icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
> @@ -3209,7 +3202,7 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> drm_dbg_kms(&dev_priv->drm,
> "No combo PHY PLL found for [ENCODER:%d:%s]\n",
> encoder->base.base.id, encoder->base.name);
> - return false;
> + return -EINVAL;
> }
>
> intel_reference_shared_dpll(state, crtc,
> @@ -3217,12 +3210,12 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
>
> icl_update_active_dpll(state, crtc, encoder);
>
> - return true;
> + return 0;
> }
>
> -static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct intel_encoder *encoder)
> +static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc_state *crtc_state =
> @@ -3230,12 +3223,14 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
> struct skl_wrpll_params pll_params = { };
> struct icl_port_dpll *port_dpll;
> enum intel_dpll_id dpll_id;
> + int ret;
>
> port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> - if (!icl_calc_tbt_pll(crtc_state, &pll_params)) {
> + ret = icl_calc_tbt_pll(crtc_state, &pll_params);
> + if (ret) {
> drm_dbg_kms(&dev_priv->drm,
> "Could not calculate TBT PLL state.\n");
> - return false;
> + return ret;
> }
>
> icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
> @@ -3245,14 +3240,15 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
> BIT(DPLL_ID_ICL_TBTPLL));
> if (!port_dpll->pll) {
> drm_dbg_kms(&dev_priv->drm, "No TBT-ALT PLL found\n");
> - return false;
> + return -EINVAL;
> }
> intel_reference_shared_dpll(state, crtc,
> port_dpll->pll, &port_dpll->hw_state);
>
>
> port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
> - if (!icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state)) {
> + ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
> + if (ret) {
> drm_dbg_kms(&dev_priv->drm,
> "Could not calculate MG PHY PLL state.\n");
> goto err_unreference_tbt_pll;
> @@ -3264,6 +3260,7 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
> &port_dpll->hw_state,
> BIT(dpll_id));
> if (!port_dpll->pll) {
> + ret = -EINVAL;
> drm_dbg_kms(&dev_priv->drm, "No MG PHY PLL found\n");
> goto err_unreference_tbt_pll;
> }
> @@ -3272,18 +3269,18 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
>
> icl_update_active_dpll(state, crtc, encoder);
>
> - return true;
> + return 0;
>
> err_unreference_tbt_pll:
> port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> intel_unreference_shared_dpll(state, crtc, port_dpll->pll);
>
> - return false;
> + return ret;
> }
>
> -static bool icl_get_dplls(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct intel_encoder *encoder)
> +static int icl_get_dplls(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> @@ -3295,7 +3292,7 @@ static bool icl_get_dplls(struct intel_atomic_state *state,
>
> MISSING_CASE(phy);
>
> - return false;
> + return -EINVAL;
> }
>
> static void icl_put_dplls(struct intel_atomic_state *state,
> @@ -4154,17 +4151,18 @@ void intel_shared_dpll_init(struct drm_device *dev)
> * intel_release_shared_dplls().
> *
> * Returns:
> - * True if all required DPLLs were successfully reserved.
> + * 0 if all required DPLLs were successfully reserved,
> + * negative error code otherwise.
> */
> -bool intel_reserve_shared_dplls(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct intel_encoder *encoder)
> +int intel_reserve_shared_dplls(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
>
> if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
> - return false;
> + return -EINVAL;
>
> return dpll_mgr->get_dplls(state, crtc, encoder);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index ba2fdfce1579..499a43e39123 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -337,9 +337,9 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
> bool state);
> #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
> #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
> -bool intel_reserve_shared_dplls(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct intel_encoder *encoder);
> +int intel_reserve_shared_dplls(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder);
> void intel_release_shared_dplls(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 44+ messages in thread
* [Intel-gfx] [PATCH 02/13] drm/i915: Pass dev_priv to intel_shared_dpll_init()
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
2022-03-25 12:31 ` [Intel-gfx] [PATCH 01/13] drm/i915: Make .get_dplls() return int Ville Syrjala
@ 2022-03-25 12:31 ` Ville Syrjala
2022-03-28 10:57 ` Jani Nikula
2022-03-25 12:31 ` [Intel-gfx] [PATCH 03/13] drm/i915: Remove pointless dpll_funcs checks Ville Syrjala
` (29 subsequent siblings)
31 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2022-03-25 12:31 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Stop passing around the drm_device and just pass the
dev_priv instead.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 9 ++++-----
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 3 +--
3 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3d2ff258f0a9..986e2e67ef91 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9754,7 +9754,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
}
intel_plane_possible_crtcs_init(i915);
- intel_shared_dpll_init(dev);
+ intel_shared_dpll_init(i915);
intel_fdi_pll_freq_update(i915);
intel_update_czclk(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 1d52796333ab..dc3c889b0aa6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4078,13 +4078,12 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
/**
* intel_shared_dpll_init - Initialize shared DPLLs
- * @dev: drm device
+ * @dev_priv: i915 device
*
- * Initialize shared DPLLs for @dev.
+ * Initialize shared DPLLs for @dev_priv.
*/
-void intel_shared_dpll_init(struct drm_device *dev)
+void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
const struct intel_dpll_mgr *dpll_mgr = NULL;
const struct dpll_info *dpll_info;
int i;
@@ -4123,7 +4122,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
dpll_info = dpll_mgr->dpll_info;
for (i = 0; dpll_info[i].name; i++) {
- drm_WARN_ON(dev, i != dpll_info[i].id);
+ drm_WARN_ON(&dev_priv->drm, i != dpll_info[i].id);
dev_priv->dpll.shared_dplls[i].info = &dpll_info[i];
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 499a43e39123..f7c96a1f13c8 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -37,7 +37,6 @@
__a > __b ? (__a - __b) : (__b - __a); })
enum tc_port;
-struct drm_device;
struct drm_i915_private;
struct intel_atomic_state;
struct intel_crtc;
@@ -356,7 +355,7 @@ bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
-void intel_shared_dpll_init(struct drm_device *dev);
+void intel_shared_dpll_init(struct drm_i915_private *dev_priv);
void intel_dpll_update_ref_clks(struct drm_i915_private *dev_priv);
void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv);
void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
--
2.34.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [Intel-gfx] [PATCH 02/13] drm/i915: Pass dev_priv to intel_shared_dpll_init()
2022-03-25 12:31 ` [Intel-gfx] [PATCH 02/13] drm/i915: Pass dev_priv to intel_shared_dpll_init() Ville Syrjala
@ 2022-03-28 10:57 ` Jani Nikula
0 siblings, 0 replies; 44+ messages in thread
From: Jani Nikula @ 2022-03-28 10:57 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 25 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Stop passing around the drm_device and just pass the
> dev_priv instead.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 9 ++++-----
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 3 +--
> 3 files changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 3d2ff258f0a9..986e2e67ef91 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9754,7 +9754,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
> }
>
> intel_plane_possible_crtcs_init(i915);
> - intel_shared_dpll_init(dev);
> + intel_shared_dpll_init(i915);
> intel_fdi_pll_freq_update(i915);
>
> intel_update_czclk(i915);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 1d52796333ab..dc3c889b0aa6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4078,13 +4078,12 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
>
> /**
> * intel_shared_dpll_init - Initialize shared DPLLs
> - * @dev: drm device
> + * @dev_priv: i915 device
> *
> - * Initialize shared DPLLs for @dev.
> + * Initialize shared DPLLs for @dev_priv.
> */
> -void intel_shared_dpll_init(struct drm_device *dev)
> +void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> const struct intel_dpll_mgr *dpll_mgr = NULL;
> const struct dpll_info *dpll_info;
> int i;
> @@ -4123,7 +4122,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
> dpll_info = dpll_mgr->dpll_info;
>
> for (i = 0; dpll_info[i].name; i++) {
> - drm_WARN_ON(dev, i != dpll_info[i].id);
> + drm_WARN_ON(&dev_priv->drm, i != dpll_info[i].id);
> dev_priv->dpll.shared_dplls[i].info = &dpll_info[i];
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 499a43e39123..f7c96a1f13c8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -37,7 +37,6 @@
> __a > __b ? (__a - __b) : (__b - __a); })
>
> enum tc_port;
> -struct drm_device;
> struct drm_i915_private;
> struct intel_atomic_state;
> struct intel_crtc;
> @@ -356,7 +355,7 @@ bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
> void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
> void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
> void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
> -void intel_shared_dpll_init(struct drm_device *dev);
> +void intel_shared_dpll_init(struct drm_i915_private *dev_priv);
> void intel_dpll_update_ref_clks(struct drm_i915_private *dev_priv);
> void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv);
> void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 44+ messages in thread
* [Intel-gfx] [PATCH 03/13] drm/i915: Remove pointless dpll_funcs checks
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
2022-03-25 12:31 ` [Intel-gfx] [PATCH 01/13] drm/i915: Make .get_dplls() return int Ville Syrjala
2022-03-25 12:31 ` [Intel-gfx] [PATCH 02/13] drm/i915: Pass dev_priv to intel_shared_dpll_init() Ville Syrjala
@ 2022-03-25 12:31 ` Ville Syrjala
2022-03-28 10:59 ` Jani Nikula
2022-03-25 12:31 ` [Intel-gfx] [PATCH 04/13] drm/i915: Adjust .crtc_compute_clock() calling convention Ville Syrjala
` (28 subsequent siblings)
31 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2022-03-25 12:31 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
All platforms have dpll_funcs. Remove the pointless NULL checks.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 986e2e67ef91..57d9b065622f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7053,14 +7053,10 @@ intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
static void intel_modeset_clear_plls(struct intel_atomic_state *state)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state;
struct intel_crtc *crtc;
int i;
- if (!dev_priv->dpll_funcs)
- return;
-
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (!intel_crtc_needs_modeset(new_crtc_state))
continue;
--
2.34.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [Intel-gfx] [PATCH 03/13] drm/i915: Remove pointless dpll_funcs checks
2022-03-25 12:31 ` [Intel-gfx] [PATCH 03/13] drm/i915: Remove pointless dpll_funcs checks Ville Syrjala
@ 2022-03-28 10:59 ` Jani Nikula
0 siblings, 0 replies; 44+ messages in thread
From: Jani Nikula @ 2022-03-28 10:59 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 25 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> All platforms have dpll_funcs. Remove the pointless NULL checks.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 ----
> 1 file changed, 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 986e2e67ef91..57d9b065622f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7053,14 +7053,10 @@ intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
>
> static void intel_modeset_clear_plls(struct intel_atomic_state *state)
> {
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc_state *new_crtc_state;
> struct intel_crtc *crtc;
> int i;
>
> - if (!dev_priv->dpll_funcs)
> - return;
> -
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> if (!intel_crtc_needs_modeset(new_crtc_state))
> continue;
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 44+ messages in thread
* [Intel-gfx] [PATCH 04/13] drm/i915: Adjust .crtc_compute_clock() calling convention
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (2 preceding siblings ...)
2022-03-25 12:31 ` [Intel-gfx] [PATCH 03/13] drm/i915: Remove pointless dpll_funcs checks Ville Syrjala
@ 2022-03-25 12:31 ` Ville Syrjala
2022-03-28 11:01 ` Jani Nikula
2022-03-25 12:31 ` [Intel-gfx] [PATCH 05/13] drm/i915: Move stuff into intel_dpll_crtc_compute_clock() Ville Syrjala
` (27 subsequent siblings)
31 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2022-03-25 12:31 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pass the full atomic state+crtc rather than the redundant
crtc+crtc_state pair. We already need the full atomic state
in the hsw+ codepath anyway.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 83 ++++++++++++--------
drivers/gpu/drm/i915/display/intel_dpll.h | 4 +-
3 files changed, 53 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 57d9b065622f..bb1ababe4577 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5001,7 +5001,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
if (mode_changed && crtc_state->hw.enable &&
!drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
- ret = intel_dpll_crtc_compute_clock(crtc_state);
+ ret = intel_dpll_crtc_compute_clock(state, crtc);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 1bd4a05dff7c..1c05ec167046 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -18,7 +18,8 @@
#include "vlv_sideband.h"
struct intel_dpll_funcs {
- int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
+ int (*crtc_compute_clock)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
};
struct intel_limit {
@@ -759,8 +760,8 @@ chv_find_best_dpll(const struct intel_limit *limit,
bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
struct dpll *best_clock)
{
- int refclk = 100000;
const struct intel_limit *limit = &intel_limits_bxt;
+ int refclk = 100000;
return chv_find_best_dpll(limit, crtc_state,
crtc_state->port_clock, refclk,
@@ -927,12 +928,12 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
crtc_state->dpll_hw_state.dpll = dpll;
}
-static int hsw_crtc_compute_clock(struct intel_crtc_state *crtc_state)
+static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_atomic_state *state =
- to_intel_atomic_state(crtc_state->uapi.state);
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct intel_encoder *encoder =
intel_get_crtc_new_encoder(state, crtc_state);
int ret;
@@ -1070,12 +1071,12 @@ static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
crtc_state->dpll_hw_state.dpll = dpll;
}
-static int ilk_crtc_compute_clock(struct intel_crtc_state *crtc_state)
+static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_atomic_state *state =
- to_intel_atomic_state(crtc_state->uapi.state);
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_limit *limit;
int refclk = 120000;
int ret;
@@ -1167,11 +1168,14 @@ void chv_compute_dpll(struct intel_crtc_state *crtc_state)
(crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
}
-static int chv_crtc_compute_clock(struct intel_crtc_state *crtc_state)
+static int chv_crtc_compute_clock(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- int refclk = 100000;
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_limit *limit = &intel_limits_chv;
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ int refclk = 100000;
memset(&crtc_state->dpll_hw_state, 0,
sizeof(crtc_state->dpll_hw_state));
@@ -1188,11 +1192,14 @@ static int chv_crtc_compute_clock(struct intel_crtc_state *crtc_state)
return 0;
}
-static int vlv_crtc_compute_clock(struct intel_crtc_state *crtc_state)
+static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- int refclk = 100000;
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_limit *limit = &intel_limits_vlv;
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ int refclk = 100000;
memset(&crtc_state->dpll_hw_state, 0,
sizeof(crtc_state->dpll_hw_state));
@@ -1209,10 +1216,12 @@ static int vlv_crtc_compute_clock(struct intel_crtc_state *crtc_state)
return 0;
}
-static int g4x_crtc_compute_clock(struct intel_crtc_state *crtc_state)
+static int g4x_crtc_compute_clock(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_limit *limit;
int refclk = 96000;
@@ -1255,10 +1264,12 @@ static int g4x_crtc_compute_clock(struct intel_crtc_state *crtc_state)
return 0;
}
-static int pnv_crtc_compute_clock(struct intel_crtc_state *crtc_state)
+static int pnv_crtc_compute_clock(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_limit *limit;
int refclk = 96000;
@@ -1292,10 +1303,12 @@ static int pnv_crtc_compute_clock(struct intel_crtc_state *crtc_state)
return 0;
}
-static int i9xx_crtc_compute_clock(struct intel_crtc_state *crtc_state)
+static int i9xx_crtc_compute_clock(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_limit *limit;
int refclk = 96000;
@@ -1329,10 +1342,12 @@ static int i9xx_crtc_compute_clock(struct intel_crtc_state *crtc_state)
return 0;
}
-static int i8xx_crtc_compute_clock(struct intel_crtc_state *crtc_state)
+static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_limit *limit;
int refclk = 48000;
@@ -1400,12 +1415,12 @@ static const struct intel_dpll_funcs i8xx_dpll_funcs = {
.crtc_compute_clock = i8xx_crtc_compute_clock,
};
-int intel_dpll_crtc_compute_clock(struct intel_crtc_state *crtc_state)
+int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
- return i915->dpll_funcs->crtc_compute_clock(crtc_state);
+ return i915->dpll_funcs->crtc_compute_clock(state, crtc);
}
void
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h
index 69b06a9e473e..e9731b2dd01c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll.h
@@ -10,12 +10,14 @@
struct dpll;
struct drm_i915_private;
+struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
enum pipe;
void intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv);
-int intel_dpll_crtc_compute_clock(struct intel_crtc_state *crtc_state);
+int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
int vlv_calc_dpll_params(int refclk, struct dpll *clock);
int pnv_calc_dpll_params(int refclk, struct dpll *clock);
int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
--
2.34.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [Intel-gfx] [PATCH 04/13] drm/i915: Adjust .crtc_compute_clock() calling convention
2022-03-25 12:31 ` [Intel-gfx] [PATCH 04/13] drm/i915: Adjust .crtc_compute_clock() calling convention Ville Syrjala
@ 2022-03-28 11:01 ` Jani Nikula
0 siblings, 0 replies; 44+ messages in thread
From: Jani Nikula @ 2022-03-28 11:01 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 25 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pass the full atomic state+crtc rather than the redundant
> crtc+crtc_state pair. We already need the full atomic state
> in the hsw+ codepath anyway.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dpll.c | 83 ++++++++++++--------
> drivers/gpu/drm/i915/display/intel_dpll.h | 4 +-
> 3 files changed, 53 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 57d9b065622f..bb1ababe4577 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5001,7 +5001,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>
> if (mode_changed && crtc_state->hw.enable &&
> !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
> - ret = intel_dpll_crtc_compute_clock(crtc_state);
> + ret = intel_dpll_crtc_compute_clock(state, crtc);
> if (ret)
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 1bd4a05dff7c..1c05ec167046 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -18,7 +18,8 @@
> #include "vlv_sideband.h"
>
> struct intel_dpll_funcs {
> - int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
> + int (*crtc_compute_clock)(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> };
>
> struct intel_limit {
> @@ -759,8 +760,8 @@ chv_find_best_dpll(const struct intel_limit *limit,
> bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
> struct dpll *best_clock)
> {
> - int refclk = 100000;
> const struct intel_limit *limit = &intel_limits_bxt;
> + int refclk = 100000;
>
> return chv_find_best_dpll(limit, crtc_state,
> crtc_state->port_clock, refclk,
> @@ -927,12 +928,12 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
> crtc_state->dpll_hw_state.dpll = dpll;
> }
>
> -static int hsw_crtc_compute_clock(struct intel_crtc_state *crtc_state)
> +static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - struct intel_atomic_state *state =
> - to_intel_atomic_state(crtc_state->uapi.state);
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> struct intel_encoder *encoder =
> intel_get_crtc_new_encoder(state, crtc_state);
> int ret;
> @@ -1070,12 +1071,12 @@ static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
> crtc_state->dpll_hw_state.dpll = dpll;
> }
>
> -static int ilk_crtc_compute_clock(struct intel_crtc_state *crtc_state)
> +static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - struct intel_atomic_state *state =
> - to_intel_atomic_state(crtc_state->uapi.state);
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> const struct intel_limit *limit;
> int refclk = 120000;
> int ret;
> @@ -1167,11 +1168,14 @@ void chv_compute_dpll(struct intel_crtc_state *crtc_state)
> (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> }
>
> -static int chv_crtc_compute_clock(struct intel_crtc_state *crtc_state)
> +static int chv_crtc_compute_clock(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - int refclk = 100000;
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> const struct intel_limit *limit = &intel_limits_chv;
> - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> + int refclk = 100000;
>
> memset(&crtc_state->dpll_hw_state, 0,
> sizeof(crtc_state->dpll_hw_state));
> @@ -1188,11 +1192,14 @@ static int chv_crtc_compute_clock(struct intel_crtc_state *crtc_state)
> return 0;
> }
>
> -static int vlv_crtc_compute_clock(struct intel_crtc_state *crtc_state)
> +static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - int refclk = 100000;
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> const struct intel_limit *limit = &intel_limits_vlv;
> - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> + int refclk = 100000;
>
> memset(&crtc_state->dpll_hw_state, 0,
> sizeof(crtc_state->dpll_hw_state));
> @@ -1209,10 +1216,12 @@ static int vlv_crtc_compute_clock(struct intel_crtc_state *crtc_state)
> return 0;
> }
>
> -static int g4x_crtc_compute_clock(struct intel_crtc_state *crtc_state)
> +static int g4x_crtc_compute_clock(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> const struct intel_limit *limit;
> int refclk = 96000;
>
> @@ -1255,10 +1264,12 @@ static int g4x_crtc_compute_clock(struct intel_crtc_state *crtc_state)
> return 0;
> }
>
> -static int pnv_crtc_compute_clock(struct intel_crtc_state *crtc_state)
> +static int pnv_crtc_compute_clock(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> const struct intel_limit *limit;
> int refclk = 96000;
>
> @@ -1292,10 +1303,12 @@ static int pnv_crtc_compute_clock(struct intel_crtc_state *crtc_state)
> return 0;
> }
>
> -static int i9xx_crtc_compute_clock(struct intel_crtc_state *crtc_state)
> +static int i9xx_crtc_compute_clock(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> const struct intel_limit *limit;
> int refclk = 96000;
>
> @@ -1329,10 +1342,12 @@ static int i9xx_crtc_compute_clock(struct intel_crtc_state *crtc_state)
> return 0;
> }
>
> -static int i8xx_crtc_compute_clock(struct intel_crtc_state *crtc_state)
> +static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> const struct intel_limit *limit;
> int refclk = 48000;
>
> @@ -1400,12 +1415,12 @@ static const struct intel_dpll_funcs i8xx_dpll_funcs = {
> .crtc_compute_clock = i8xx_crtc_compute_clock,
> };
>
> -int intel_dpll_crtc_compute_clock(struct intel_crtc_state *crtc_state)
> +int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
>
> - return i915->dpll_funcs->crtc_compute_clock(crtc_state);
> + return i915->dpll_funcs->crtc_compute_clock(state, crtc);
> }
>
> void
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h
> index 69b06a9e473e..e9731b2dd01c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.h
> @@ -10,12 +10,14 @@
>
> struct dpll;
> struct drm_i915_private;
> +struct intel_atomic_state;
> struct intel_crtc;
> struct intel_crtc_state;
> enum pipe;
>
> void intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv);
> -int intel_dpll_crtc_compute_clock(struct intel_crtc_state *crtc_state);
> +int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> int vlv_calc_dpll_params(int refclk, struct dpll *clock);
> int pnv_calc_dpll_params(int refclk, struct dpll *clock);
> int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 44+ messages in thread
* [Intel-gfx] [PATCH 05/13] drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (3 preceding siblings ...)
2022-03-25 12:31 ` [Intel-gfx] [PATCH 04/13] drm/i915: Adjust .crtc_compute_clock() calling convention Ville Syrjala
@ 2022-03-25 12:31 ` Ville Syrjala
2022-03-28 11:02 ` Jani Nikula
2022-03-25 12:31 ` [Intel-gfx] [PATCH 06/13] drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock() Ville Syrjala
` (26 subsequent siblings)
31 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2022-03-25 12:31 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move some checks into intel_dpll_crtc_compute_clock() from the
caller. Avoids the caller from having to worry about all this
crap.
We'll also reorder the hw.enable vs. shared_dpll checks since
it makes sense to sanity check that we've cleared out the
old shared_dpll even if the pipe is getting disabled.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +--
drivers/gpu/drm/i915/display/intel_dpll.c | 10 ++++++++++
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index bb1ababe4577..7c68bc07c925 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4999,8 +4999,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
mode_changed && !crtc_state->hw.active)
crtc_state->update_wm_post = true;
- if (mode_changed && crtc_state->hw.enable &&
- !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
+ if (mode_changed) {
ret = intel_dpll_crtc_compute_clock(state, crtc);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 1c05ec167046..88d78a585304 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1419,6 +1419,16 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
+
+ if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
+ return 0;
+
+ if (!crtc_state->hw.enable)
+ return 0;
return i915->dpll_funcs->crtc_compute_clock(state, crtc);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [Intel-gfx] [PATCH 05/13] drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
2022-03-25 12:31 ` [Intel-gfx] [PATCH 05/13] drm/i915: Move stuff into intel_dpll_crtc_compute_clock() Ville Syrjala
@ 2022-03-28 11:02 ` Jani Nikula
0 siblings, 0 replies; 44+ messages in thread
From: Jani Nikula @ 2022-03-28 11:02 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 25 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move some checks into intel_dpll_crtc_compute_clock() from the
> caller. Avoids the caller from having to worry about all this
> crap.
>
> We'll also reorder the hw.enable vs. shared_dpll checks since
> it makes sense to sanity check that we've cleared out the
> old shared_dpll even if the pipe is getting disabled.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 3 +--
> drivers/gpu/drm/i915/display/intel_dpll.c | 10 ++++++++++
> 2 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index bb1ababe4577..7c68bc07c925 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4999,8 +4999,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
> mode_changed && !crtc_state->hw.active)
> crtc_state->update_wm_post = true;
>
> - if (mode_changed && crtc_state->hw.enable &&
> - !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
> + if (mode_changed) {
> ret = intel_dpll_crtc_compute_clock(state, crtc);
> if (ret)
> return ret;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 1c05ec167046..88d78a585304 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1419,6 +1419,16 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> +
> + drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
> +
> + if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
> + return 0;
> +
> + if (!crtc_state->hw.enable)
> + return 0;
>
> return i915->dpll_funcs->crtc_compute_clock(state, crtc);
> }
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 44+ messages in thread
* [Intel-gfx] [PATCH 06/13] drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (4 preceding siblings ...)
2022-03-25 12:31 ` [Intel-gfx] [PATCH 05/13] drm/i915: Move stuff into intel_dpll_crtc_compute_clock() Ville Syrjala
@ 2022-03-25 12:31 ` Ville Syrjala
2022-03-28 11:05 ` Jani Nikula
2022-03-25 12:31 ` [Intel-gfx] [PATCH 07/13] drm/i915: Clear the dpll_hw_state when disabling a pipe Ville Syrjala
` (25 subsequent siblings)
31 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2022-03-25 12:31 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
All .crtc_compute_clock() implementations do the same memset() to
clear the dpll_hw_state (since we preserve it across
intel_crtc_prepare_cleared_state()). Move the memset() to the common
wrapper.
Also clear it when we're about disable the pipe. Previously
it looks like we just left the old junk in there.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 24 +++----------------
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 15 ------------
2 files changed, 3 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 88d78a585304..494a343850e7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1081,9 +1081,6 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
int refclk = 120000;
int ret;
- memset(&crtc_state->dpll_hw_state, 0,
- sizeof(crtc_state->dpll_hw_state));
-
/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
if (!crtc_state->has_pch_encoder)
return 0;
@@ -1177,9 +1174,6 @@ static int chv_crtc_compute_clock(struct intel_atomic_state *state,
const struct intel_limit *limit = &intel_limits_chv;
int refclk = 100000;
- memset(&crtc_state->dpll_hw_state, 0,
- sizeof(crtc_state->dpll_hw_state));
-
if (!crtc_state->clock_set &&
!chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
refclk, NULL, &crtc_state->dpll)) {
@@ -1201,9 +1195,6 @@ static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
const struct intel_limit *limit = &intel_limits_vlv;
int refclk = 100000;
- memset(&crtc_state->dpll_hw_state, 0,
- sizeof(crtc_state->dpll_hw_state));
-
if (!crtc_state->clock_set &&
!vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
refclk, NULL, &crtc_state->dpll)) {
@@ -1225,9 +1216,6 @@ static int g4x_crtc_compute_clock(struct intel_atomic_state *state,
const struct intel_limit *limit;
int refclk = 96000;
- memset(&crtc_state->dpll_hw_state, 0,
- sizeof(crtc_state->dpll_hw_state));
-
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_panel_use_ssc(dev_priv)) {
refclk = dev_priv->vbt.lvds_ssc_freq;
@@ -1273,9 +1261,6 @@ static int pnv_crtc_compute_clock(struct intel_atomic_state *state,
const struct intel_limit *limit;
int refclk = 96000;
- memset(&crtc_state->dpll_hw_state, 0,
- sizeof(crtc_state->dpll_hw_state));
-
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_panel_use_ssc(dev_priv)) {
refclk = dev_priv->vbt.lvds_ssc_freq;
@@ -1312,9 +1297,6 @@ static int i9xx_crtc_compute_clock(struct intel_atomic_state *state,
const struct intel_limit *limit;
int refclk = 96000;
- memset(&crtc_state->dpll_hw_state, 0,
- sizeof(crtc_state->dpll_hw_state));
-
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_panel_use_ssc(dev_priv)) {
refclk = dev_priv->vbt.lvds_ssc_freq;
@@ -1351,9 +1333,6 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
const struct intel_limit *limit;
int refclk = 48000;
- memset(&crtc_state->dpll_hw_state, 0,
- sizeof(crtc_state->dpll_hw_state));
-
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_panel_use_ssc(dev_priv)) {
refclk = dev_priv->vbt.lvds_ssc_freq;
@@ -1430,6 +1409,9 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
if (!crtc_state->hw.enable)
return 0;
+ memset(&crtc_state->dpll_hw_state, 0,
+ sizeof(crtc_state->dpll_hw_state));
+
return i915->dpll_funcs->crtc_compute_clock(state, crtc);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index dc3c889b0aa6..22f55574a35c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1068,9 +1068,6 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_shared_dpll *pll = NULL;
- memset(&crtc_state->dpll_hw_state, 0,
- sizeof(crtc_state->dpll_hw_state));
-
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
pll = hsw_ddi_wrpll_get_dpll(state, crtc);
else if (intel_crtc_has_dp_encoder(crtc_state))
@@ -1595,9 +1592,6 @@ static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
wrpll_params.central_freq;
- memset(&crtc_state->dpll_hw_state, 0,
- sizeof(crtc_state->dpll_hw_state));
-
crtc_state->dpll_hw_state.ctrl1 = ctrl1;
crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
@@ -1708,9 +1702,6 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
break;
}
- memset(&crtc_state->dpll_hw_state, 0,
- sizeof(crtc_state->dpll_hw_state));
-
crtc_state->dpll_hw_state.ctrl1 = ctrl1;
return 0;
@@ -2139,8 +2130,6 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
u32 prop_coef, int_coef, gain_ctl, targ_cnt;
u32 lanestagger;
- memset(dpll_hw_state, 0, sizeof(*dpll_hw_state));
-
if (vco >= 6200000 && vco <= 6700000) {
prop_coef = 4;
int_coef = 9;
@@ -2701,8 +2690,6 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
{
u32 dco_fraction = pll_params->dco_fraction;
- memset(pll_state, 0, sizeof(*pll_state));
-
if (ehl_combo_pll_div_frac_wa_needed(i915))
dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
@@ -2820,8 +2807,6 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
bool is_dkl = DISPLAY_VER(dev_priv) >= 12;
int ret;
- memset(pll_state, 0, sizeof(*pll_state));
-
ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
pll_state, is_dkl);
if (ret) {
--
2.34.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [Intel-gfx] [PATCH 06/13] drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()
2022-03-25 12:31 ` [Intel-gfx] [PATCH 06/13] drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock() Ville Syrjala
@ 2022-03-28 11:05 ` Jani Nikula
0 siblings, 0 replies; 44+ messages in thread
From: Jani Nikula @ 2022-03-28 11:05 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 25 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> All .crtc_compute_clock() implementations do the same memset() to
> clear the dpll_hw_state (since we preserve it across
> intel_crtc_prepare_cleared_state()). Move the memset() to the common
> wrapper.
>
> Also clear it when we're about disable the pipe. Previously
> it looks like we just left the old junk in there.
Looks like you split this part to a separate patch. Which is good. Apart
from the stale commit message. ;)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll.c | 24 +++----------------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 15 ------------
> 2 files changed, 3 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 88d78a585304..494a343850e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1081,9 +1081,6 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
> int refclk = 120000;
> int ret;
>
> - memset(&crtc_state->dpll_hw_state, 0,
> - sizeof(crtc_state->dpll_hw_state));
> -
> /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
> if (!crtc_state->has_pch_encoder)
> return 0;
> @@ -1177,9 +1174,6 @@ static int chv_crtc_compute_clock(struct intel_atomic_state *state,
> const struct intel_limit *limit = &intel_limits_chv;
> int refclk = 100000;
>
> - memset(&crtc_state->dpll_hw_state, 0,
> - sizeof(crtc_state->dpll_hw_state));
> -
> if (!crtc_state->clock_set &&
> !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> refclk, NULL, &crtc_state->dpll)) {
> @@ -1201,9 +1195,6 @@ static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
> const struct intel_limit *limit = &intel_limits_vlv;
> int refclk = 100000;
>
> - memset(&crtc_state->dpll_hw_state, 0,
> - sizeof(crtc_state->dpll_hw_state));
> -
> if (!crtc_state->clock_set &&
> !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> refclk, NULL, &crtc_state->dpll)) {
> @@ -1225,9 +1216,6 @@ static int g4x_crtc_compute_clock(struct intel_atomic_state *state,
> const struct intel_limit *limit;
> int refclk = 96000;
>
> - memset(&crtc_state->dpll_hw_state, 0,
> - sizeof(crtc_state->dpll_hw_state));
> -
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
> if (intel_panel_use_ssc(dev_priv)) {
> refclk = dev_priv->vbt.lvds_ssc_freq;
> @@ -1273,9 +1261,6 @@ static int pnv_crtc_compute_clock(struct intel_atomic_state *state,
> const struct intel_limit *limit;
> int refclk = 96000;
>
> - memset(&crtc_state->dpll_hw_state, 0,
> - sizeof(crtc_state->dpll_hw_state));
> -
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
> if (intel_panel_use_ssc(dev_priv)) {
> refclk = dev_priv->vbt.lvds_ssc_freq;
> @@ -1312,9 +1297,6 @@ static int i9xx_crtc_compute_clock(struct intel_atomic_state *state,
> const struct intel_limit *limit;
> int refclk = 96000;
>
> - memset(&crtc_state->dpll_hw_state, 0,
> - sizeof(crtc_state->dpll_hw_state));
> -
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
> if (intel_panel_use_ssc(dev_priv)) {
> refclk = dev_priv->vbt.lvds_ssc_freq;
> @@ -1351,9 +1333,6 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
> const struct intel_limit *limit;
> int refclk = 48000;
>
> - memset(&crtc_state->dpll_hw_state, 0,
> - sizeof(crtc_state->dpll_hw_state));
> -
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
> if (intel_panel_use_ssc(dev_priv)) {
> refclk = dev_priv->vbt.lvds_ssc_freq;
> @@ -1430,6 +1409,9 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
> if (!crtc_state->hw.enable)
> return 0;
>
> + memset(&crtc_state->dpll_hw_state, 0,
> + sizeof(crtc_state->dpll_hw_state));
> +
> return i915->dpll_funcs->crtc_compute_clock(state, crtc);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index dc3c889b0aa6..22f55574a35c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -1068,9 +1068,6 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
> intel_atomic_get_new_crtc_state(state, crtc);
> struct intel_shared_dpll *pll = NULL;
>
> - memset(&crtc_state->dpll_hw_state, 0,
> - sizeof(crtc_state->dpll_hw_state));
> -
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> pll = hsw_ddi_wrpll_get_dpll(state, crtc);
> else if (intel_crtc_has_dp_encoder(crtc_state))
> @@ -1595,9 +1592,6 @@ static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
> DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
> wrpll_params.central_freq;
>
> - memset(&crtc_state->dpll_hw_state, 0,
> - sizeof(crtc_state->dpll_hw_state));
> -
> crtc_state->dpll_hw_state.ctrl1 = ctrl1;
> crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
> crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
> @@ -1708,9 +1702,6 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> break;
> }
>
> - memset(&crtc_state->dpll_hw_state, 0,
> - sizeof(crtc_state->dpll_hw_state));
> -
> crtc_state->dpll_hw_state.ctrl1 = ctrl1;
>
> return 0;
> @@ -2139,8 +2130,6 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
> u32 prop_coef, int_coef, gain_ctl, targ_cnt;
> u32 lanestagger;
>
> - memset(dpll_hw_state, 0, sizeof(*dpll_hw_state));
> -
> if (vco >= 6200000 && vco <= 6700000) {
> prop_coef = 4;
> int_coef = 9;
> @@ -2701,8 +2690,6 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
> {
> u32 dco_fraction = pll_params->dco_fraction;
>
> - memset(pll_state, 0, sizeof(*pll_state));
> -
> if (ehl_combo_pll_div_frac_wa_needed(i915))
> dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
>
> @@ -2820,8 +2807,6 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> bool is_dkl = DISPLAY_VER(dev_priv) >= 12;
> int ret;
>
> - memset(pll_state, 0, sizeof(*pll_state));
> -
> ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
> pll_state, is_dkl);
> if (ret) {
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 44+ messages in thread
* [Intel-gfx] [PATCH 07/13] drm/i915: Clear the dpll_hw_state when disabling a pipe
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (5 preceding siblings ...)
2022-03-25 12:31 ` [Intel-gfx] [PATCH 06/13] drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock() Ville Syrjala
@ 2022-03-25 12:31 ` Ville Syrjala
2022-03-28 11:06 ` Jani Nikula
2022-03-25 12:32 ` [Intel-gfx] [PATCH 08/13] drm/i915: Split out dg2_crtc_compute_clock() Ville Syrjala
` (24 subsequent siblings)
31 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2022-03-25 12:31 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Clear the dpll_hw_state when we're about disable the pipe.
Previously it looks like we just left the old junk in there.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 494a343850e7..7960f1d52eaa 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1406,12 +1406,12 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
return 0;
- if (!crtc_state->hw.enable)
- return 0;
-
memset(&crtc_state->dpll_hw_state, 0,
sizeof(crtc_state->dpll_hw_state));
+ if (!crtc_state->hw.enable)
+ return 0;
+
return i915->dpll_funcs->crtc_compute_clock(state, crtc);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [Intel-gfx] [PATCH 07/13] drm/i915: Clear the dpll_hw_state when disabling a pipe
2022-03-25 12:31 ` [Intel-gfx] [PATCH 07/13] drm/i915: Clear the dpll_hw_state when disabling a pipe Ville Syrjala
@ 2022-03-28 11:06 ` Jani Nikula
0 siblings, 0 replies; 44+ messages in thread
From: Jani Nikula @ 2022-03-28 11:06 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 25 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Clear the dpll_hw_state when we're about disable the pipe.
> Previously it looks like we just left the old junk in there.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 494a343850e7..7960f1d52eaa 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1406,12 +1406,12 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
> if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
> return 0;
>
> - if (!crtc_state->hw.enable)
> - return 0;
> -
> memset(&crtc_state->dpll_hw_state, 0,
> sizeof(crtc_state->dpll_hw_state));
>
> + if (!crtc_state->hw.enable)
> + return 0;
> +
> return i915->dpll_funcs->crtc_compute_clock(state, crtc);
> }
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 44+ messages in thread
* [Intel-gfx] [PATCH 08/13] drm/i915: Split out dg2_crtc_compute_clock()
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (6 preceding siblings ...)
2022-03-25 12:31 ` [Intel-gfx] [PATCH 07/13] drm/i915: Clear the dpll_hw_state when disabling a pipe Ville Syrjala
@ 2022-03-25 12:32 ` Ville Syrjala
2022-03-28 11:07 ` Jani Nikula
2022-03-25 12:32 ` [Intel-gfx] [PATCH 09/13] drm/i915: Add crtc .crtc_get_shared_dpll() Ville Syrjala
` (23 subsequent siblings)
31 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2022-03-25 12:32 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
DG2 doesn't currently used the shared_dpll stuff so let's just
split it out from hsw_crtc_compute_clock() entirely.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 7960f1d52eaa..bc59efe18e89 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -938,9 +938,6 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
intel_get_crtc_new_encoder(state, crtc_state);
int ret;
- if (IS_DG2(dev_priv))
- return intel_mpllb_calc_state(crtc_state, encoder);
-
if (DISPLAY_VER(dev_priv) < 11 &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
return 0;
@@ -956,6 +953,17 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
return 0;
}
+static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ struct intel_encoder *encoder =
+ intel_get_crtc_new_encoder(state, crtc_state);
+
+ return intel_mpllb_calc_state(crtc_state, encoder);
+}
+
static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
{
return dpll->m < factor * dpll->n;
@@ -1362,6 +1370,10 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
return 0;
}
+static const struct intel_dpll_funcs dg2_dpll_funcs = {
+ .crtc_compute_clock = dg2_crtc_compute_clock,
+};
+
static const struct intel_dpll_funcs hsw_dpll_funcs = {
.crtc_compute_clock = hsw_crtc_compute_clock,
};
@@ -1418,7 +1430,9 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
void
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
{
- if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
+ if (IS_DG2(dev_priv))
+ dev_priv->dpll_funcs = &dg2_dpll_funcs;
+ else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
dev_priv->dpll_funcs = &hsw_dpll_funcs;
else if (HAS_PCH_SPLIT(dev_priv))
dev_priv->dpll_funcs = &ilk_dpll_funcs;
--
2.34.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [Intel-gfx] [PATCH 08/13] drm/i915: Split out dg2_crtc_compute_clock()
2022-03-25 12:32 ` [Intel-gfx] [PATCH 08/13] drm/i915: Split out dg2_crtc_compute_clock() Ville Syrjala
@ 2022-03-28 11:07 ` Jani Nikula
0 siblings, 0 replies; 44+ messages in thread
From: Jani Nikula @ 2022-03-28 11:07 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 25 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> DG2 doesn't currently used the shared_dpll stuff so let's just
> split it out from hsw_crtc_compute_clock() entirely.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll.c | 22 ++++++++++++++++++----
> 1 file changed, 18 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 7960f1d52eaa..bc59efe18e89 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -938,9 +938,6 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
> intel_get_crtc_new_encoder(state, crtc_state);
> int ret;
>
> - if (IS_DG2(dev_priv))
> - return intel_mpllb_calc_state(crtc_state, encoder);
> -
> if (DISPLAY_VER(dev_priv) < 11 &&
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> return 0;
> @@ -956,6 +953,17 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
> return 0;
> }
>
> +static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> +{
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + struct intel_encoder *encoder =
> + intel_get_crtc_new_encoder(state, crtc_state);
> +
> + return intel_mpllb_calc_state(crtc_state, encoder);
> +}
> +
> static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
> {
> return dpll->m < factor * dpll->n;
> @@ -1362,6 +1370,10 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
> return 0;
> }
>
> +static const struct intel_dpll_funcs dg2_dpll_funcs = {
> + .crtc_compute_clock = dg2_crtc_compute_clock,
> +};
> +
> static const struct intel_dpll_funcs hsw_dpll_funcs = {
> .crtc_compute_clock = hsw_crtc_compute_clock,
> };
> @@ -1418,7 +1430,9 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
> void
> intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
> {
> - if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
> + if (IS_DG2(dev_priv))
> + dev_priv->dpll_funcs = &dg2_dpll_funcs;
> + else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
> dev_priv->dpll_funcs = &hsw_dpll_funcs;
> else if (HAS_PCH_SPLIT(dev_priv))
> dev_priv->dpll_funcs = &ilk_dpll_funcs;
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 44+ messages in thread
* [Intel-gfx] [PATCH 09/13] drm/i915: Add crtc .crtc_get_shared_dpll()
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (7 preceding siblings ...)
2022-03-25 12:32 ` [Intel-gfx] [PATCH 08/13] drm/i915: Split out dg2_crtc_compute_clock() Ville Syrjala
@ 2022-03-25 12:32 ` Ville Syrjala
2022-03-28 11:10 ` Jani Nikula
2022-03-25 12:32 ` [Intel-gfx] [PATCH 10/13] drm/i915: Split shared dpll .get_dplls() into compute and get phases Ville Syrjala
` (22 subsequent siblings)
31 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2022-03-25 12:32 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Start splitting the .compute_crtc_clock() into two parts; one
part does the computation, the second part does the shared dpll
assignment. I want to move the actual computation part much earlier
into the compute_config() phase.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++
drivers/gpu/drm/i915/display/intel_dpll.c | 54 +++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_dpll.h | 2 +
3 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7c68bc07c925..1b7bc764498c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5003,6 +5003,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
ret = intel_dpll_crtc_compute_clock(state, crtc);
if (ret)
return ret;
+
+ ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
+ if (ret)
+ return ret;
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index bc59efe18e89..2ee7255f3c36 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -20,6 +20,8 @@
struct intel_dpll_funcs {
int (*crtc_compute_clock)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
+ int (*crtc_get_shared_dpll)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
};
struct intel_limit {
@@ -930,6 +932,12 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
struct intel_crtc *crtc)
+{
+ return 0;
+}
+
+static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state =
@@ -964,6 +972,12 @@ static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
return intel_mpllb_calc_state(crtc_state, encoder);
}
+static int dg2_crtc_get_shared_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ return 0;
+}
+
static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
{
return dpll->m < factor * dpll->n;
@@ -1087,7 +1101,6 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_limit *limit;
int refclk = 120000;
- int ret;
/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
if (!crtc_state->has_pch_encoder)
@@ -1127,6 +1140,21 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
ilk_compute_dpll(crtc_state, &crtc_state->dpll,
&crtc_state->dpll);
+ return 0;
+}
+
+static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ int ret;
+
+ /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
+ if (!crtc_state->has_pch_encoder)
+ return 0;
+
ret = intel_reserve_shared_dplls(state, crtc, NULL);
if (ret) {
drm_dbg_kms(&dev_priv->drm,
@@ -1372,14 +1400,17 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
static const struct intel_dpll_funcs dg2_dpll_funcs = {
.crtc_compute_clock = dg2_crtc_compute_clock,
+ .crtc_get_shared_dpll = dg2_crtc_get_shared_dpll,
};
static const struct intel_dpll_funcs hsw_dpll_funcs = {
.crtc_compute_clock = hsw_crtc_compute_clock,
+ .crtc_get_shared_dpll = hsw_crtc_get_shared_dpll,
};
static const struct intel_dpll_funcs ilk_dpll_funcs = {
.crtc_compute_clock = ilk_crtc_compute_clock,
+ .crtc_get_shared_dpll = ilk_crtc_get_shared_dpll,
};
static const struct intel_dpll_funcs chv_dpll_funcs = {
@@ -1427,6 +1458,27 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
return i915->dpll_funcs->crtc_compute_clock(state, crtc);
}
+int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
+
+ if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
+ return 0;
+
+ if (!crtc_state->hw.enable)
+ return 0;
+
+ if (!i915->dpll_funcs->crtc_get_shared_dpll)
+ return 0;
+
+ return i915->dpll_funcs->crtc_get_shared_dpll(state, crtc);
+}
+
void
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
{
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h
index e9731b2dd01c..bbc30542f29f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll.h
@@ -18,6 +18,8 @@ enum pipe;
void intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv);
int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
struct intel_crtc *crtc);
+int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
int vlv_calc_dpll_params(int refclk, struct dpll *clock);
int pnv_calc_dpll_params(int refclk, struct dpll *clock);
int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
--
2.34.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [Intel-gfx] [PATCH 09/13] drm/i915: Add crtc .crtc_get_shared_dpll()
2022-03-25 12:32 ` [Intel-gfx] [PATCH 09/13] drm/i915: Add crtc .crtc_get_shared_dpll() Ville Syrjala
@ 2022-03-28 11:10 ` Jani Nikula
0 siblings, 0 replies; 44+ messages in thread
From: Jani Nikula @ 2022-03-28 11:10 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 25 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Start splitting the .compute_crtc_clock() into two parts; one
> part does the computation, the second part does the shared dpll
> assignment. I want to move the actual computation part much earlier
> into the compute_config() phase.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++
> drivers/gpu/drm/i915/display/intel_dpll.c | 54 +++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_dpll.h | 2 +
> 3 files changed, 59 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7c68bc07c925..1b7bc764498c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5003,6 +5003,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
> ret = intel_dpll_crtc_compute_clock(state, crtc);
> if (ret)
> return ret;
> +
> + ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
> + if (ret)
> + return ret;
> }
>
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index bc59efe18e89..2ee7255f3c36 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -20,6 +20,8 @@
> struct intel_dpll_funcs {
> int (*crtc_compute_clock)(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> + int (*crtc_get_shared_dpll)(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> };
>
> struct intel_limit {
> @@ -930,6 +932,12 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
>
> static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> +{
> + return 0;
> +}
> +
> +static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc_state *crtc_state =
> @@ -964,6 +972,12 @@ static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
> return intel_mpllb_calc_state(crtc_state, encoder);
> }
>
> +static int dg2_crtc_get_shared_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> +{
> + return 0;
> +}
> +
This seems superfluous at this time because
intel_dpll_crtc_get_shared_dpll() checks for NULL
.crtc_get_shared_dpll() and does exactly that.
Not a biggie.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
> {
> return dpll->m < factor * dpll->n;
> @@ -1087,7 +1101,6 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
> intel_atomic_get_new_crtc_state(state, crtc);
> const struct intel_limit *limit;
> int refclk = 120000;
> - int ret;
>
> /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
> if (!crtc_state->has_pch_encoder)
> @@ -1127,6 +1140,21 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
> ilk_compute_dpll(crtc_state, &crtc_state->dpll,
> &crtc_state->dpll);
>
> + return 0;
> +}
> +
> +static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + int ret;
> +
> + /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
> + if (!crtc_state->has_pch_encoder)
> + return 0;
> +
> ret = intel_reserve_shared_dplls(state, crtc, NULL);
> if (ret) {
> drm_dbg_kms(&dev_priv->drm,
> @@ -1372,14 +1400,17 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
>
> static const struct intel_dpll_funcs dg2_dpll_funcs = {
> .crtc_compute_clock = dg2_crtc_compute_clock,
> + .crtc_get_shared_dpll = dg2_crtc_get_shared_dpll,
> };
>
> static const struct intel_dpll_funcs hsw_dpll_funcs = {
> .crtc_compute_clock = hsw_crtc_compute_clock,
> + .crtc_get_shared_dpll = hsw_crtc_get_shared_dpll,
> };
>
> static const struct intel_dpll_funcs ilk_dpll_funcs = {
> .crtc_compute_clock = ilk_crtc_compute_clock,
> + .crtc_get_shared_dpll = ilk_crtc_get_shared_dpll,
> };
>
> static const struct intel_dpll_funcs chv_dpll_funcs = {
> @@ -1427,6 +1458,27 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
> return i915->dpll_funcs->crtc_compute_clock(state, crtc);
> }
>
> +int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> +
> + drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
> +
> + if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
> + return 0;
> +
> + if (!crtc_state->hw.enable)
> + return 0;
> +
> + if (!i915->dpll_funcs->crtc_get_shared_dpll)
> + return 0;
> +
> + return i915->dpll_funcs->crtc_get_shared_dpll(state, crtc);
> +}
> +
> void
> intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h
> index e9731b2dd01c..bbc30542f29f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.h
> @@ -18,6 +18,8 @@ enum pipe;
> void intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv);
> int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> +int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> int vlv_calc_dpll_params(int refclk, struct dpll *clock);
> int pnv_calc_dpll_params(int refclk, struct dpll *clock);
> int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 44+ messages in thread
* [Intel-gfx] [PATCH 10/13] drm/i915: Split shared dpll .get_dplls() into compute and get phases
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (8 preceding siblings ...)
2022-03-25 12:32 ` [Intel-gfx] [PATCH 09/13] drm/i915: Add crtc .crtc_get_shared_dpll() Ville Syrjala
@ 2022-03-25 12:32 ` Ville Syrjala
2022-03-28 11:18 ` Jani Nikula
2022-03-25 12:32 ` [Intel-gfx] [PATCH 11/13] drm/i915: Do .crtc_compute_clock() earlier Ville Syrjala
` (21 subsequent siblings)
31 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2022-03-25 12:32 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Split the DPLL state computation into a separate function
from the current .get_dplls() which currently serves a dual duty
by also reserving the shared DPLLs.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 14 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 291 +++++++++++++-----
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 3 +
3 files changed, 235 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 2ee7255f3c36..32918e082e9f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -933,7 +933,17 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- return 0;
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ struct intel_encoder *encoder =
+ intel_get_crtc_new_encoder(state, crtc_state);
+
+ if (DISPLAY_VER(dev_priv) < 11 &&
+ intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+ return 0;
+
+ return intel_compute_shared_dplls(state, crtc, encoder);
}
static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
@@ -1140,7 +1150,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
ilk_compute_dpll(crtc_state, &crtc_state->dpll,
&crtc_state->dpll);
- return 0;
+ return intel_compute_shared_dplls(state, crtc, NULL);
}
static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 22f55574a35c..d426724d5a2e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -90,6 +90,9 @@ struct intel_shared_dpll_funcs {
struct intel_dpll_mgr {
const struct dpll_info *dpll_info;
+ int (*compute_dplls)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder);
int (*get_dplls)(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
@@ -514,6 +517,13 @@ static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
udelay(200);
}
+static int ibx_compute_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
+{
+ return 0;
+}
+
static int ibx_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
@@ -578,6 +588,7 @@ static const struct dpll_info pch_plls[] = {
static const struct intel_dpll_mgr pch_pll_mgr = {
.dpll_info = pch_plls,
+ .compute_dplls = ibx_compute_dpll,
.get_dplls = ibx_get_dpll,
.put_dplls = intel_put_dpll,
.dump_hw_state = ibx_dump_hw_state,
@@ -894,33 +905,35 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
*r2_out = best.r2;
}
-static struct intel_shared_dpll *
-hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+static int
+hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct intel_shared_dpll *pll;
- u32 val;
unsigned int p, n2, r2;
hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p);
- val = WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
- WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
- WRPLL_DIVIDER_POST(p);
+ crtc_state->dpll_hw_state.wrpll =
+ WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
+ WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
+ WRPLL_DIVIDER_POST(p);
- crtc_state->dpll_hw_state.wrpll = val;
+ return 0;
+}
- pll = intel_find_shared_dpll(state, crtc,
- &crtc_state->dpll_hw_state,
- BIT(DPLL_ID_WRPLL2) |
- BIT(DPLL_ID_WRPLL1));
+static struct intel_shared_dpll *
+hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
- if (!pll)
- return NULL;
-
- return pll;
+ return intel_find_shared_dpll(state, crtc,
+ &crtc_state->dpll_hw_state,
+ BIT(DPLL_ID_WRPLL2) |
+ BIT(DPLL_ID_WRPLL1));
}
static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
@@ -963,6 +976,24 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
return (refclk * n / 10) / (p * r) * 2;
}
+static int
+hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ int clock = crtc_state->port_clock;
+
+ switch (clock / 2) {
+ case 81000:
+ case 135000:
+ case 270000:
+ return 0;
+ default:
+ drm_dbg_kms(&dev_priv->drm, "Invalid clock for DP: %d\n",
+ clock);
+ return -EINVAL;
+ }
+}
+
static struct intel_shared_dpll *
hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
{
@@ -982,8 +1013,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
pll_id = DPLL_ID_LCPLL_2700;
break;
default:
- drm_dbg_kms(&dev_priv->drm, "Invalid clock for DP: %d\n",
- clock);
+ MISSING_CASE(clock / 2);
return NULL;
}
@@ -1019,6 +1049,22 @@ static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
return link_clock * 2;
}
+static int
+hsw_ddi_spll_compute_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000))
+ return -EINVAL;
+
+ crtc_state->dpll_hw_state.spll =
+ SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;
+
+ return 0;
+}
+
static struct intel_shared_dpll *
hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
@@ -1026,12 +1072,6 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000))
- return NULL;
-
- crtc_state->dpll_hw_state.spll = SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz |
- SPLL_REF_MUXED_SSC;
-
return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
BIT(DPLL_ID_SPLL));
}
@@ -1060,6 +1100,23 @@ static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
return link_clock * 2;
}
+static int hsw_compute_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
+{
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ return hsw_ddi_wrpll_compute_dpll(state, crtc);
+ else if (intel_crtc_has_dp_encoder(crtc_state))
+ return hsw_ddi_lcpll_compute_dpll(crtc_state);
+ else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
+ return hsw_ddi_spll_compute_dpll(state, crtc);
+ else
+ return -EINVAL;
+}
+
static int hsw_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
@@ -1153,6 +1210,7 @@ static const struct dpll_info hsw_plls[] = {
static const struct intel_dpll_mgr hsw_pll_mgr = {
.dpll_info = hsw_plls,
+ .compute_dplls = hsw_compute_dpll,
.get_dplls = hsw_get_dpll,
.put_dplls = intel_put_dpll,
.update_ref_clks = hsw_update_dpll_ref_clks,
@@ -1741,6 +1799,21 @@ static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
return link_clock * 2;
}
+static int skl_compute_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
+{
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ return skl_ddi_hdmi_pll_dividers(crtc_state);
+ else if (intel_crtc_has_dp_encoder(crtc_state))
+ return skl_ddi_dp_set_dpll_hw_state(crtc_state);
+ else
+ return -EINVAL;
+}
+
static int skl_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
@@ -1748,16 +1821,6 @@ static int skl_get_dpll(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_shared_dpll *pll;
- int ret;
-
- if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
- ret = skl_ddi_hdmi_pll_dividers(crtc_state);
- else if (intel_crtc_has_dp_encoder(crtc_state))
- ret = skl_ddi_dp_set_dpll_hw_state(crtc_state);
- else
- ret = -EINVAL;
- if (ret)
- return ret;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
pll = intel_find_shared_dpll(state, crtc,
@@ -1834,6 +1897,7 @@ static const struct dpll_info skl_plls[] = {
static const struct intel_dpll_mgr skl_pll_mgr = {
.dpll_info = skl_plls,
+ .compute_dplls = skl_compute_dpll,
.get_dplls = skl_get_dpll,
.put_dplls = intel_put_dpll,
.update_ref_clks = skl_update_dpll_ref_clks,
@@ -2225,6 +2289,21 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock);
}
+static int bxt_compute_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
+{
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ return bxt_ddi_hdmi_set_dpll_hw_state(crtc_state);
+ else if (intel_crtc_has_dp_encoder(crtc_state))
+ return bxt_ddi_dp_set_dpll_hw_state(crtc_state);
+ else
+ return -EINVAL;
+}
+
static int bxt_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
@@ -2234,16 +2313,6 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll;
enum intel_dpll_id id;
- int ret;
-
- if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
- ret = bxt_ddi_hdmi_set_dpll_hw_state(crtc_state);
- else if (intel_crtc_has_dp_encoder(crtc_state))
- ret = bxt_ddi_dp_set_dpll_hw_state(crtc_state);
- else
- ret = -EINVAL;
- if (ret)
- return ret;
/* 1:1 mapping between ports and PLLs */
id = (enum intel_dpll_id) encoder->port;
@@ -2302,6 +2371,7 @@ static const struct dpll_info bxt_plls[] = {
static const struct intel_dpll_mgr bxt_pll_mgr = {
.dpll_info = bxt_plls,
+ .compute_dplls = bxt_compute_dpll,
.get_dplls = bxt_get_dpll,
.put_dplls = intel_put_dpll,
.update_ref_clks = bxt_update_dpll_ref_clks,
@@ -3119,19 +3189,16 @@ static u32 intel_get_hti_plls(struct drm_i915_private *i915)
return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->hti_state);
}
-static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder)
+static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct skl_wrpll_params pll_params = { };
struct icl_port_dpll *port_dpll =
&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum port port = encoder->port;
- unsigned long dpll_mask;
- int ret;
+ struct skl_wrpll_params pll_params = {};
+ bool ret;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
@@ -3147,6 +3214,21 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
+ return 0;
+}
+
+static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ struct icl_port_dpll *port_dpll =
+ &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
+ enum port port = encoder->port;
+ unsigned long dpll_mask;
+
if (IS_ALDERLAKE_S(dev_priv)) {
dpll_mask =
BIT(DPLL_ID_DG1_DPLL3) |
@@ -3198,6 +3280,38 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
return 0;
}
+static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ struct icl_port_dpll *port_dpll =
+ &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
+ struct skl_wrpll_params pll_params = {};
+ int ret;
+
+ port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
+ ret = icl_calc_tbt_pll(crtc_state, &pll_params);
+ if (ret) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Could not calculate TBT PLL state.\n");
+ return ret;
+ }
+
+ icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
+
+ port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
+ ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
+ if (ret) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Could not calculate MG PHY PLL state.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
@@ -3205,21 +3319,12 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct skl_wrpll_params pll_params = { };
- struct icl_port_dpll *port_dpll;
+ struct icl_port_dpll *port_dpll =
+ &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
enum intel_dpll_id dpll_id;
int ret;
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
- ret = icl_calc_tbt_pll(crtc_state, &pll_params);
- if (ret) {
- drm_dbg_kms(&dev_priv->drm,
- "Could not calculate TBT PLL state.\n");
- return ret;
- }
-
- icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
-
port_dpll->pll = intel_find_shared_dpll(state, crtc,
&port_dpll->hw_state,
BIT(DPLL_ID_ICL_TBTPLL));
@@ -3232,13 +3337,6 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
- ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
- if (ret) {
- drm_dbg_kms(&dev_priv->drm,
- "Could not calculate MG PHY PLL state.\n");
- goto err_unreference_tbt_pll;
- }
-
dpll_id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
encoder->port));
port_dpll->pll = intel_find_shared_dpll(state, crtc,
@@ -3263,6 +3361,23 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
return ret;
}
+static int icl_compute_dplls(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+ if (intel_phy_is_combo(dev_priv, phy))
+ return icl_compute_combo_phy_dpll(state, crtc);
+ else if (intel_phy_is_tc(dev_priv, phy))
+ return icl_compute_tc_phy_dplls(state, crtc);
+
+ MISSING_CASE(phy);
+
+ return 0;
+}
+
static int icl_get_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
@@ -3943,6 +4058,7 @@ static const struct dpll_info icl_plls[] = {
static const struct intel_dpll_mgr icl_pll_mgr = {
.dpll_info = icl_plls,
+ .compute_dplls = icl_compute_dplls,
.get_dplls = icl_get_dplls,
.put_dplls = icl_put_dplls,
.update_active_dpll = icl_update_active_dpll,
@@ -3959,6 +4075,7 @@ static const struct dpll_info ehl_plls[] = {
static const struct intel_dpll_mgr ehl_pll_mgr = {
.dpll_info = ehl_plls,
+ .compute_dplls = icl_compute_dplls,
.get_dplls = icl_get_dplls,
.put_dplls = icl_put_dplls,
.update_ref_clks = icl_update_dpll_ref_clks,
@@ -3987,6 +4104,7 @@ static const struct dpll_info tgl_plls[] = {
static const struct intel_dpll_mgr tgl_pll_mgr = {
.dpll_info = tgl_plls,
+ .compute_dplls = icl_compute_dplls,
.get_dplls = icl_get_dplls,
.put_dplls = icl_put_dplls,
.update_active_dpll = icl_update_active_dpll,
@@ -4003,6 +4121,7 @@ static const struct dpll_info rkl_plls[] = {
static const struct intel_dpll_mgr rkl_pll_mgr = {
.dpll_info = rkl_plls,
+ .compute_dplls = icl_compute_dplls,
.get_dplls = icl_get_dplls,
.put_dplls = icl_put_dplls,
.update_ref_clks = icl_update_dpll_ref_clks,
@@ -4019,6 +4138,7 @@ static const struct dpll_info dg1_plls[] = {
static const struct intel_dpll_mgr dg1_pll_mgr = {
.dpll_info = dg1_plls,
+ .compute_dplls = icl_compute_dplls,
.get_dplls = icl_get_dplls,
.put_dplls = icl_put_dplls,
.update_ref_clks = icl_update_dpll_ref_clks,
@@ -4035,6 +4155,7 @@ static const struct dpll_info adls_plls[] = {
static const struct intel_dpll_mgr adls_pll_mgr = {
.dpll_info = adls_plls,
+ .compute_dplls = icl_compute_dplls,
.get_dplls = icl_get_dplls,
.put_dplls = icl_put_dplls,
.update_ref_clks = icl_update_dpll_ref_clks,
@@ -4054,6 +4175,7 @@ static const struct dpll_info adlp_plls[] = {
static const struct intel_dpll_mgr adlp_pll_mgr = {
.dpll_info = adlp_plls,
+ .compute_dplls = icl_compute_dplls,
.get_dplls = icl_get_dplls,
.put_dplls = icl_put_dplls,
.update_active_dpll = icl_update_active_dpll,
@@ -4118,6 +4240,33 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
BUG_ON(dev_priv->dpll.num_shared_dpll > I915_NUM_PLLS);
}
+/**
+ * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination
+ * @state: atomic state
+ * @crtc: CRTC to compute DPLLs for
+ * @encoder: encoder
+ *
+ * This function computes the DPLL state for the given CRTC and encoder.
+ *
+ * The new configuration in the atomic commit @state is made effective by
+ * calling intel_shared_dpll_swap_state().
+ *
+ * Returns:
+ * 0 on success, negative error code on falure.
+ */
+int intel_compute_shared_dplls(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
+
+ if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
+ return false;
+
+ return dpll_mgr->compute_dplls(state, crtc, encoder);
+}
+
/**
* intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
* @state: atomic state
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index f7c96a1f13c8..02412bf7625c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -336,6 +336,9 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
bool state);
#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
+int intel_compute_shared_dplls(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder);
int intel_reserve_shared_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
--
2.34.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [Intel-gfx] [PATCH 10/13] drm/i915: Split shared dpll .get_dplls() into compute and get phases
2022-03-25 12:32 ` [Intel-gfx] [PATCH 10/13] drm/i915: Split shared dpll .get_dplls() into compute and get phases Ville Syrjala
@ 2022-03-28 11:18 ` Jani Nikula
0 siblings, 0 replies; 44+ messages in thread
From: Jani Nikula @ 2022-03-28 11:18 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 25 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Split the DPLL state computation into a separate function
> from the current .get_dplls() which currently serves a dual duty
> by also reserving the shared DPLLs.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Didn't do a thorough review yet, but spotted one issue near the end.
> ---
> drivers/gpu/drm/i915/display/intel_dpll.c | 14 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 291 +++++++++++++-----
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 3 +
> 3 files changed, 235 insertions(+), 73 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 2ee7255f3c36..32918e082e9f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -933,7 +933,17 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
> static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> - return 0;
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + struct intel_encoder *encoder =
> + intel_get_crtc_new_encoder(state, crtc_state);
> +
> + if (DISPLAY_VER(dev_priv) < 11 &&
> + intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> + return 0;
> +
> + return intel_compute_shared_dplls(state, crtc, encoder);
> }
>
> static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
> @@ -1140,7 +1150,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
> ilk_compute_dpll(crtc_state, &crtc_state->dpll,
> &crtc_state->dpll);
>
> - return 0;
> + return intel_compute_shared_dplls(state, crtc, NULL);
> }
>
> static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 22f55574a35c..d426724d5a2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -90,6 +90,9 @@ struct intel_shared_dpll_funcs {
> struct intel_dpll_mgr {
> const struct dpll_info *dpll_info;
>
> + int (*compute_dplls)(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder);
> int (*get_dplls)(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder);
> @@ -514,6 +517,13 @@ static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
> udelay(200);
> }
>
> +static int ibx_compute_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder)
> +{
> + return 0;
> +}
> +
> static int ibx_get_dpll(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder)
> @@ -578,6 +588,7 @@ static const struct dpll_info pch_plls[] = {
>
> static const struct intel_dpll_mgr pch_pll_mgr = {
> .dpll_info = pch_plls,
> + .compute_dplls = ibx_compute_dpll,
> .get_dplls = ibx_get_dpll,
> .put_dplls = intel_put_dpll,
> .dump_hw_state = ibx_dump_hw_state,
> @@ -894,33 +905,35 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
> *r2_out = best.r2;
> }
>
> -static struct intel_shared_dpll *
> -hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +static int
> +hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - struct intel_shared_dpll *pll;
> - u32 val;
> unsigned int p, n2, r2;
>
> hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p);
>
> - val = WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
> - WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
> - WRPLL_DIVIDER_POST(p);
> + crtc_state->dpll_hw_state.wrpll =
> + WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
> + WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
> + WRPLL_DIVIDER_POST(p);
>
> - crtc_state->dpll_hw_state.wrpll = val;
> + return 0;
> +}
>
> - pll = intel_find_shared_dpll(state, crtc,
> - &crtc_state->dpll_hw_state,
> - BIT(DPLL_ID_WRPLL2) |
> - BIT(DPLL_ID_WRPLL1));
> +static struct intel_shared_dpll *
> +hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> +{
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
>
> - if (!pll)
> - return NULL;
> -
> - return pll;
> + return intel_find_shared_dpll(state, crtc,
> + &crtc_state->dpll_hw_state,
> + BIT(DPLL_ID_WRPLL2) |
> + BIT(DPLL_ID_WRPLL1));
> }
>
> static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> @@ -963,6 +976,24 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> return (refclk * n / 10) / (p * r) * 2;
> }
>
> +static int
> +hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + int clock = crtc_state->port_clock;
> +
> + switch (clock / 2) {
> + case 81000:
> + case 135000:
> + case 270000:
> + return 0;
> + default:
> + drm_dbg_kms(&dev_priv->drm, "Invalid clock for DP: %d\n",
> + clock);
> + return -EINVAL;
> + }
> +}
> +
> static struct intel_shared_dpll *
> hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
> {
> @@ -982,8 +1013,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
> pll_id = DPLL_ID_LCPLL_2700;
> break;
> default:
> - drm_dbg_kms(&dev_priv->drm, "Invalid clock for DP: %d\n",
> - clock);
> + MISSING_CASE(clock / 2);
> return NULL;
> }
>
> @@ -1019,6 +1049,22 @@ static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
> return link_clock * 2;
> }
>
> +static int
> +hsw_ddi_spll_compute_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> +{
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> +
> + if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000))
> + return -EINVAL;
> +
> + crtc_state->dpll_hw_state.spll =
> + SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;
> +
> + return 0;
> +}
> +
> static struct intel_shared_dpll *
> hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> @@ -1026,12 +1072,6 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
>
> - if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000))
> - return NULL;
> -
> - crtc_state->dpll_hw_state.spll = SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz |
> - SPLL_REF_MUXED_SSC;
> -
> return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
> BIT(DPLL_ID_SPLL));
> }
> @@ -1060,6 +1100,23 @@ static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
> return link_clock * 2;
> }
>
> +static int hsw_compute_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder)
> +{
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> +
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> + return hsw_ddi_wrpll_compute_dpll(state, crtc);
> + else if (intel_crtc_has_dp_encoder(crtc_state))
> + return hsw_ddi_lcpll_compute_dpll(crtc_state);
> + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
> + return hsw_ddi_spll_compute_dpll(state, crtc);
> + else
> + return -EINVAL;
> +}
> +
> static int hsw_get_dpll(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder)
> @@ -1153,6 +1210,7 @@ static const struct dpll_info hsw_plls[] = {
>
> static const struct intel_dpll_mgr hsw_pll_mgr = {
> .dpll_info = hsw_plls,
> + .compute_dplls = hsw_compute_dpll,
> .get_dplls = hsw_get_dpll,
> .put_dplls = intel_put_dpll,
> .update_ref_clks = hsw_update_dpll_ref_clks,
> @@ -1741,6 +1799,21 @@ static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
> return link_clock * 2;
> }
>
> +static int skl_compute_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder)
> +{
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> +
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> + return skl_ddi_hdmi_pll_dividers(crtc_state);
> + else if (intel_crtc_has_dp_encoder(crtc_state))
> + return skl_ddi_dp_set_dpll_hw_state(crtc_state);
> + else
> + return -EINVAL;
> +}
> +
> static int skl_get_dpll(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder)
> @@ -1748,16 +1821,6 @@ static int skl_get_dpll(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> struct intel_shared_dpll *pll;
> - int ret;
> -
> - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> - ret = skl_ddi_hdmi_pll_dividers(crtc_state);
> - else if (intel_crtc_has_dp_encoder(crtc_state))
> - ret = skl_ddi_dp_set_dpll_hw_state(crtc_state);
> - else
> - ret = -EINVAL;
> - if (ret)
> - return ret;
>
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> pll = intel_find_shared_dpll(state, crtc,
> @@ -1834,6 +1897,7 @@ static const struct dpll_info skl_plls[] = {
>
> static const struct intel_dpll_mgr skl_pll_mgr = {
> .dpll_info = skl_plls,
> + .compute_dplls = skl_compute_dpll,
> .get_dplls = skl_get_dpll,
> .put_dplls = intel_put_dpll,
> .update_ref_clks = skl_update_dpll_ref_clks,
> @@ -2225,6 +2289,21 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
> return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock);
> }
>
> +static int bxt_compute_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder)
> +{
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> +
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> + return bxt_ddi_hdmi_set_dpll_hw_state(crtc_state);
> + else if (intel_crtc_has_dp_encoder(crtc_state))
> + return bxt_ddi_dp_set_dpll_hw_state(crtc_state);
> + else
> + return -EINVAL;
> +}
> +
> static int bxt_get_dpll(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder)
> @@ -2234,16 +2313,6 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_shared_dpll *pll;
> enum intel_dpll_id id;
> - int ret;
> -
> - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> - ret = bxt_ddi_hdmi_set_dpll_hw_state(crtc_state);
> - else if (intel_crtc_has_dp_encoder(crtc_state))
> - ret = bxt_ddi_dp_set_dpll_hw_state(crtc_state);
> - else
> - ret = -EINVAL;
> - if (ret)
> - return ret;
>
> /* 1:1 mapping between ports and PLLs */
> id = (enum intel_dpll_id) encoder->port;
> @@ -2302,6 +2371,7 @@ static const struct dpll_info bxt_plls[] = {
>
> static const struct intel_dpll_mgr bxt_pll_mgr = {
> .dpll_info = bxt_plls,
> + .compute_dplls = bxt_compute_dpll,
> .get_dplls = bxt_get_dpll,
> .put_dplls = intel_put_dpll,
> .update_ref_clks = bxt_update_dpll_ref_clks,
> @@ -3119,19 +3189,16 @@ static u32 intel_get_hti_plls(struct drm_i915_private *i915)
> return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->hti_state);
> }
>
> -static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct intel_encoder *encoder)
> +static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - struct skl_wrpll_params pll_params = { };
> struct icl_port_dpll *port_dpll =
> &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - enum port port = encoder->port;
> - unsigned long dpll_mask;
> - int ret;
> + struct skl_wrpll_params pll_params = {};
> + bool ret;
>
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> @@ -3147,6 +3214,21 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
>
> icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
>
> + return 0;
> +}
> +
> +static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + struct icl_port_dpll *port_dpll =
> + &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> + enum port port = encoder->port;
> + unsigned long dpll_mask;
> +
> if (IS_ALDERLAKE_S(dev_priv)) {
> dpll_mask =
> BIT(DPLL_ID_DG1_DPLL3) |
> @@ -3198,6 +3280,38 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> return 0;
> }
>
> +static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + struct icl_port_dpll *port_dpll =
> + &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> + struct skl_wrpll_params pll_params = {};
> + int ret;
> +
> + port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> + ret = icl_calc_tbt_pll(crtc_state, &pll_params);
> + if (ret) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Could not calculate TBT PLL state.\n");
> + return ret;
> + }
> +
> + icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
> +
> + port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
> + ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
> + if (ret) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Could not calculate MG PHY PLL state.\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder)
> @@ -3205,21 +3319,12 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - struct skl_wrpll_params pll_params = { };
> - struct icl_port_dpll *port_dpll;
> + struct icl_port_dpll *port_dpll =
> + &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> enum intel_dpll_id dpll_id;
> int ret;
>
> port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> - ret = icl_calc_tbt_pll(crtc_state, &pll_params);
> - if (ret) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Could not calculate TBT PLL state.\n");
> - return ret;
> - }
> -
> - icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
> -
> port_dpll->pll = intel_find_shared_dpll(state, crtc,
> &port_dpll->hw_state,
> BIT(DPLL_ID_ICL_TBTPLL));
> @@ -3232,13 +3337,6 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
>
>
> port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
> - ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
> - if (ret) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Could not calculate MG PHY PLL state.\n");
> - goto err_unreference_tbt_pll;
> - }
> -
> dpll_id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
> encoder->port));
> port_dpll->pll = intel_find_shared_dpll(state, crtc,
> @@ -3263,6 +3361,23 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
> return ret;
> }
>
> +static int icl_compute_dplls(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> +
> + if (intel_phy_is_combo(dev_priv, phy))
> + return icl_compute_combo_phy_dpll(state, crtc);
> + else if (intel_phy_is_tc(dev_priv, phy))
> + return icl_compute_tc_phy_dplls(state, crtc);
> +
> + MISSING_CASE(phy);
> +
> + return 0;
> +}
> +
> static int icl_get_dplls(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder)
> @@ -3943,6 +4058,7 @@ static const struct dpll_info icl_plls[] = {
>
> static const struct intel_dpll_mgr icl_pll_mgr = {
> .dpll_info = icl_plls,
> + .compute_dplls = icl_compute_dplls,
> .get_dplls = icl_get_dplls,
> .put_dplls = icl_put_dplls,
> .update_active_dpll = icl_update_active_dpll,
> @@ -3959,6 +4075,7 @@ static const struct dpll_info ehl_plls[] = {
>
> static const struct intel_dpll_mgr ehl_pll_mgr = {
> .dpll_info = ehl_plls,
> + .compute_dplls = icl_compute_dplls,
> .get_dplls = icl_get_dplls,
> .put_dplls = icl_put_dplls,
> .update_ref_clks = icl_update_dpll_ref_clks,
> @@ -3987,6 +4104,7 @@ static const struct dpll_info tgl_plls[] = {
>
> static const struct intel_dpll_mgr tgl_pll_mgr = {
> .dpll_info = tgl_plls,
> + .compute_dplls = icl_compute_dplls,
> .get_dplls = icl_get_dplls,
> .put_dplls = icl_put_dplls,
> .update_active_dpll = icl_update_active_dpll,
> @@ -4003,6 +4121,7 @@ static const struct dpll_info rkl_plls[] = {
>
> static const struct intel_dpll_mgr rkl_pll_mgr = {
> .dpll_info = rkl_plls,
> + .compute_dplls = icl_compute_dplls,
> .get_dplls = icl_get_dplls,
> .put_dplls = icl_put_dplls,
> .update_ref_clks = icl_update_dpll_ref_clks,
> @@ -4019,6 +4138,7 @@ static const struct dpll_info dg1_plls[] = {
>
> static const struct intel_dpll_mgr dg1_pll_mgr = {
> .dpll_info = dg1_plls,
> + .compute_dplls = icl_compute_dplls,
> .get_dplls = icl_get_dplls,
> .put_dplls = icl_put_dplls,
> .update_ref_clks = icl_update_dpll_ref_clks,
> @@ -4035,6 +4155,7 @@ static const struct dpll_info adls_plls[] = {
>
> static const struct intel_dpll_mgr adls_pll_mgr = {
> .dpll_info = adls_plls,
> + .compute_dplls = icl_compute_dplls,
> .get_dplls = icl_get_dplls,
> .put_dplls = icl_put_dplls,
> .update_ref_clks = icl_update_dpll_ref_clks,
> @@ -4054,6 +4175,7 @@ static const struct dpll_info adlp_plls[] = {
>
> static const struct intel_dpll_mgr adlp_pll_mgr = {
> .dpll_info = adlp_plls,
> + .compute_dplls = icl_compute_dplls,
> .get_dplls = icl_get_dplls,
> .put_dplls = icl_put_dplls,
> .update_active_dpll = icl_update_active_dpll,
> @@ -4118,6 +4240,33 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
> BUG_ON(dev_priv->dpll.num_shared_dpll > I915_NUM_PLLS);
> }
>
> +/**
> + * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination
> + * @state: atomic state
> + * @crtc: CRTC to compute DPLLs for
> + * @encoder: encoder
> + *
> + * This function computes the DPLL state for the given CRTC and encoder.
> + *
> + * The new configuration in the atomic commit @state is made effective by
> + * calling intel_shared_dpll_swap_state().
> + *
> + * Returns:
> + * 0 on success, negative error code on falure.
> + */
> +int intel_compute_shared_dplls(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
> +
> + if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
> + return false;
Leftover bool return.
> +
> + return dpll_mgr->compute_dplls(state, crtc, encoder);
> +}
> +
> /**
> * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
> * @state: atomic state
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index f7c96a1f13c8..02412bf7625c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -336,6 +336,9 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
> bool state);
> #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
> #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
> +int intel_compute_shared_dplls(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder);
> int intel_reserve_shared_dplls(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder);
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 44+ messages in thread
* [Intel-gfx] [PATCH 11/13] drm/i915: Do .crtc_compute_clock() earlier
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (9 preceding siblings ...)
2022-03-25 12:32 ` [Intel-gfx] [PATCH 10/13] drm/i915: Split shared dpll .get_dplls() into compute and get phases Ville Syrjala
@ 2022-03-25 12:32 ` Ville Syrjala
2022-03-25 12:32 ` [Intel-gfx] [PATCH 12/13] drm/i915: Clean up DPLL related debugs Ville Syrjala
` (20 subsequent siblings)
31 siblings, 0 replies; 44+ messages in thread
From: Ville Syrjala @ 2022-03-25 12:32 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Currently we calculate a lot of things (pixel rate, watermarks,
cdclk) trusting that the DPLL can generate the exact frequency
we ask it. In practice that is not true and there can be
certain amount of rounding involved.
To allows us to eventually get accurate numbers for all our
DPLL clock derived state we need to move the DPLL calculation
to hapen much earlier. To that end we hoist it up to the just
after the fastset checks. For now we just do the easy code
motion, and the actual back feeding of the final DPLL clock
into the state will come later.
A slight change here is that now .crtc_compute_clock()
can get called while the shared_dpll is still assigned.
But since .crtc_compute_clock() no longer assignes new
shared_dplls this is perfectly fine.
TODO: I'd actually like to do this before the fastset check
so that if the DPLL state should change we actually do the
modeset. Which I think is what the video aficionados want,
but it might not be what the fans of fastboot want. Not yet
sure how to reconcile those conflicting requirements...
v2: s/return/goto/ in error handling
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +++++----
drivers/gpu/drm/i915/display/intel_dpll.c | 3 ---
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1b7bc764498c..f6db0bd2da6f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5000,10 +5000,6 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
crtc_state->update_wm_post = true;
if (mode_changed) {
- ret = intel_dpll_crtc_compute_clock(state, crtc);
- if (ret)
- return ret;
-
ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
if (ret)
return ret;
@@ -7896,6 +7892,11 @@ static int intel_atomic_check(struct drm_device *dev,
new_crtc_state, i) {
if (intel_crtc_needs_modeset(new_crtc_state)) {
any_ms = true;
+
+ ret = intel_dpll_crtc_compute_clock(state, crtc);
+ if (ret)
+ goto fail;
+
continue;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 32918e082e9f..7c6e72555b82 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1456,9 +1456,6 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
- if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
- return 0;
-
memset(&crtc_state->dpll_hw_state, 0,
sizeof(crtc_state->dpll_hw_state));
--
2.34.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Intel-gfx] [PATCH 12/13] drm/i915: Clean up DPLL related debugs
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (10 preceding siblings ...)
2022-03-25 12:32 ` [Intel-gfx] [PATCH 11/13] drm/i915: Do .crtc_compute_clock() earlier Ville Syrjala
@ 2022-03-25 12:32 ` Ville Syrjala
2022-03-28 11:14 ` Jani Nikula
2022-03-25 12:32 ` [Intel-gfx] [PATCH 13/13] drm/i915: Reassign DPLLs only for crtcs going throug .compute_config() Ville Syrjala
` (19 subsequent siblings)
31 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2022-03-25 12:32 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The debugs in lower level DPLL code don't really provide any
useful extra information AFAICS. Better just streamline the
code and just put the necessary debugs (to identify at which
step the modeset failed) into the higher level code. In
addition we'll get the full state dump as well, which should
hopefully have enough information to figure out what went wrong.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 75 +++++++------------
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 48 +++---------
2 files changed, 35 insertions(+), 88 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 7c6e72555b82..cbb444a2ba9d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -954,21 +954,12 @@ static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_encoder *encoder =
intel_get_crtc_new_encoder(state, crtc_state);
- int ret;
if (DISPLAY_VER(dev_priv) < 11 &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
return 0;
- ret = intel_reserve_shared_dplls(state, crtc, encoder);
- if (ret) {
- drm_dbg_kms(&dev_priv->drm,
- "failed to find PLL for pipe %c\n",
- pipe_name(crtc->pipe));
- return ret;
- }
-
- return 0;
+ return intel_reserve_shared_dplls(state, crtc, encoder);
}
static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
@@ -1141,11 +1132,8 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
if (!crtc_state->clock_set &&
!g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
- refclk, NULL, &crtc_state->dpll)) {
- drm_err(&dev_priv->drm,
- "Couldn't find PLL settings for mode!\n");
+ refclk, NULL, &crtc_state->dpll))
return -EINVAL;
- }
ilk_compute_dpll(crtc_state, &crtc_state->dpll,
&crtc_state->dpll);
@@ -1156,24 +1144,14 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- int ret;
/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
if (!crtc_state->has_pch_encoder)
return 0;
- ret = intel_reserve_shared_dplls(state, crtc, NULL);
- if (ret) {
- drm_dbg_kms(&dev_priv->drm,
- "failed to find PLL for pipe %c\n",
- pipe_name(crtc->pipe));
- return ret;
- }
-
- return 0;
+ return intel_reserve_shared_dplls(state, crtc, NULL);
}
void vlv_compute_dpll(struct intel_crtc_state *crtc_state)
@@ -1214,7 +1192,6 @@ void chv_compute_dpll(struct intel_crtc_state *crtc_state)
static int chv_crtc_compute_clock(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_limit *limit = &intel_limits_chv;
@@ -1222,10 +1199,8 @@ static int chv_crtc_compute_clock(struct intel_atomic_state *state,
if (!crtc_state->clock_set &&
!chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
- refclk, NULL, &crtc_state->dpll)) {
- drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
+ refclk, NULL, &crtc_state->dpll))
return -EINVAL;
- }
chv_compute_dpll(crtc_state);
@@ -1235,7 +1210,6 @@ static int chv_crtc_compute_clock(struct intel_atomic_state *state,
static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_limit *limit = &intel_limits_vlv;
@@ -1244,7 +1218,6 @@ static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
if (!crtc_state->clock_set &&
!vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
refclk, NULL, &crtc_state->dpll)) {
- drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
return -EINVAL;
}
@@ -1286,11 +1259,8 @@ static int g4x_crtc_compute_clock(struct intel_atomic_state *state,
if (!crtc_state->clock_set &&
!g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
- refclk, NULL, &crtc_state->dpll)) {
- drm_err(&dev_priv->drm,
- "Couldn't find PLL settings for mode!\n");
+ refclk, NULL, &crtc_state->dpll))
return -EINVAL;
- }
i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
&crtc_state->dpll);
@@ -1322,11 +1292,8 @@ static int pnv_crtc_compute_clock(struct intel_atomic_state *state,
if (!crtc_state->clock_set &&
!pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
- refclk, NULL, &crtc_state->dpll)) {
- drm_err(&dev_priv->drm,
- "Couldn't find PLL settings for mode!\n");
+ refclk, NULL, &crtc_state->dpll))
return -EINVAL;
- }
i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
&crtc_state->dpll);
@@ -1358,11 +1325,8 @@ static int i9xx_crtc_compute_clock(struct intel_atomic_state *state,
if (!crtc_state->clock_set &&
!i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
- refclk, NULL, &crtc_state->dpll)) {
- drm_err(&dev_priv->drm,
- "Couldn't find PLL settings for mode!\n");
+ refclk, NULL, &crtc_state->dpll))
return -EINVAL;
- }
i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
&crtc_state->dpll);
@@ -1396,11 +1360,8 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
if (!crtc_state->clock_set &&
!i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
- refclk, NULL, &crtc_state->dpll)) {
- drm_err(&dev_priv->drm,
- "Couldn't find PLL settings for mode!\n");
+ refclk, NULL, &crtc_state->dpll))
return -EINVAL;
- }
i8xx_compute_dpll(crtc_state, &crtc_state->dpll,
&crtc_state->dpll);
@@ -1453,6 +1414,7 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
+ int ret;
drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
@@ -1462,7 +1424,14 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
if (!crtc_state->hw.enable)
return 0;
- return i915->dpll_funcs->crtc_compute_clock(state, crtc);
+ ret = i915->dpll_funcs->crtc_compute_clock(state, crtc);
+ if (ret) {
+ drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n",
+ crtc->base.base.id, crtc->base.name);
+ return ret;
+ }
+
+ return 0;
}
int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
@@ -1471,6 +1440,7 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
+ int ret;
drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
@@ -1483,7 +1453,14 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
if (!i915->dpll_funcs->crtc_get_shared_dpll)
return 0;
- return i915->dpll_funcs->crtc_get_shared_dpll(state, crtc);
+ ret = i915->dpll_funcs->crtc_get_shared_dpll(state, crtc);
+ if (ret) {
+ drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",
+ crtc->base.base.id, crtc->base.name);
+ return ret;
+ }
+
+ return 0;
}
void
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index d426724d5a2e..4c24cd563560 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1603,10 +1603,8 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
break;
}
- if (!ctx.p) {
- DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
+ if (!ctx.p)
return -EINVAL;
- }
/*
* gcc incorrectly analyses that these can be used without being
@@ -2145,19 +2143,14 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
struct dpll *clk_div)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
/* Calculate HDMI div */
/*
* FIXME: tie the following calculation into
* i9xx_crtc_compute_clock
*/
- if (!bxt_find_best_dpll(crtc_state, clk_div)) {
- drm_dbg(&i915->drm, "no PLL dividers found for clock %d pipe %c\n",
- crtc_state->port_clock,
- pipe_name(crtc->pipe));
+ if (!bxt_find_best_dpll(crtc_state, clk_div))
return -EINVAL;
- }
drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
@@ -2879,11 +2872,8 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
pll_state, is_dkl);
- if (ret) {
- drm_dbg_kms(&dev_priv->drm,
- "Failed to find divisors for clock %d\n", clock);
+ if (ret)
return ret;
- }
m1div = 2;
m2div_int = dco_khz / (refclk_khz * m1div);
@@ -2893,12 +2883,8 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
m2div_int = dco_khz / (refclk_khz * m1div);
}
- if (m2div_int > 255) {
- drm_dbg_kms(&dev_priv->drm,
- "Failed to find mdiv for clock %d\n",
- clock);
+ if (m2div_int > 255)
return -EINVAL;
- }
}
m2div_rem = dco_khz % (refclk_khz * m1div);
@@ -3206,11 +3192,8 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
else
ret = icl_calc_dp_combo_pll(crtc_state, &pll_params);
- if (ret) {
- drm_dbg_kms(&dev_priv->drm,
- "Could not calculate combo PHY PLL state.\n");
+ if (ret)
return ret;
- }
icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
@@ -3265,12 +3248,8 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
port_dpll->pll = intel_find_shared_dpll(state, crtc,
&port_dpll->hw_state,
dpll_mask);
- if (!port_dpll->pll) {
- drm_dbg_kms(&dev_priv->drm,
- "No combo PHY PLL found for [ENCODER:%d:%s]\n",
- encoder->base.base.id, encoder->base.name);
+ if (!port_dpll->pll)
return -EINVAL;
- }
intel_reference_shared_dpll(state, crtc,
port_dpll->pll, &port_dpll->hw_state);
@@ -3293,21 +3272,15 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
ret = icl_calc_tbt_pll(crtc_state, &pll_params);
- if (ret) {
- drm_dbg_kms(&dev_priv->drm,
- "Could not calculate TBT PLL state.\n");
+ if (ret)
return ret;
- }
icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
- if (ret) {
- drm_dbg_kms(&dev_priv->drm,
- "Could not calculate MG PHY PLL state.\n");
+ if (ret)
return ret;
- }
return 0;
}
@@ -3328,10 +3301,8 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
port_dpll->pll = intel_find_shared_dpll(state, crtc,
&port_dpll->hw_state,
BIT(DPLL_ID_ICL_TBTPLL));
- if (!port_dpll->pll) {
- drm_dbg_kms(&dev_priv->drm, "No TBT-ALT PLL found\n");
+ if (!port_dpll->pll)
return -EINVAL;
- }
intel_reference_shared_dpll(state, crtc,
port_dpll->pll, &port_dpll->hw_state);
@@ -3344,7 +3315,6 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
BIT(dpll_id));
if (!port_dpll->pll) {
ret = -EINVAL;
- drm_dbg_kms(&dev_priv->drm, "No MG PHY PLL found\n");
goto err_unreference_tbt_pll;
}
intel_reference_shared_dpll(state, crtc,
--
2.34.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [Intel-gfx] [PATCH 12/13] drm/i915: Clean up DPLL related debugs
2022-03-25 12:32 ` [Intel-gfx] [PATCH 12/13] drm/i915: Clean up DPLL related debugs Ville Syrjala
@ 2022-03-28 11:14 ` Jani Nikula
0 siblings, 0 replies; 44+ messages in thread
From: Jani Nikula @ 2022-03-28 11:14 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 25 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The debugs in lower level DPLL code don't really provide any
> useful extra information AFAICS. Better just streamline the
> code and just put the necessary debugs (to identify at which
> step the modeset failed) into the higher level code. In
> addition we'll get the full state dump as well, which should
> hopefully have enough information to figure out what went wrong.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll.c | 75 +++++++------------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 48 +++---------
> 2 files changed, 35 insertions(+), 88 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 7c6e72555b82..cbb444a2ba9d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -954,21 +954,12 @@ static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
> intel_atomic_get_new_crtc_state(state, crtc);
> struct intel_encoder *encoder =
> intel_get_crtc_new_encoder(state, crtc_state);
> - int ret;
>
> if (DISPLAY_VER(dev_priv) < 11 &&
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> return 0;
>
> - ret = intel_reserve_shared_dplls(state, crtc, encoder);
> - if (ret) {
> - drm_dbg_kms(&dev_priv->drm,
> - "failed to find PLL for pipe %c\n",
> - pipe_name(crtc->pipe));
> - return ret;
> - }
> -
> - return 0;
> + return intel_reserve_shared_dplls(state, crtc, encoder);
> }
>
> static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
> @@ -1141,11 +1132,8 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
>
> if (!crtc_state->clock_set &&
> !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> - refclk, NULL, &crtc_state->dpll)) {
> - drm_err(&dev_priv->drm,
> - "Couldn't find PLL settings for mode!\n");
> + refclk, NULL, &crtc_state->dpll))
> return -EINVAL;
> - }
>
> ilk_compute_dpll(crtc_state, &crtc_state->dpll,
> &crtc_state->dpll);
> @@ -1156,24 +1144,14 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
> static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - int ret;
>
> /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
> if (!crtc_state->has_pch_encoder)
> return 0;
>
> - ret = intel_reserve_shared_dplls(state, crtc, NULL);
> - if (ret) {
> - drm_dbg_kms(&dev_priv->drm,
> - "failed to find PLL for pipe %c\n",
> - pipe_name(crtc->pipe));
> - return ret;
> - }
> -
> - return 0;
> + return intel_reserve_shared_dplls(state, crtc, NULL);
> }
>
> void vlv_compute_dpll(struct intel_crtc_state *crtc_state)
> @@ -1214,7 +1192,6 @@ void chv_compute_dpll(struct intel_crtc_state *crtc_state)
> static int chv_crtc_compute_clock(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> - struct drm_i915_private *i915 = to_i915(state->base.dev);
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> const struct intel_limit *limit = &intel_limits_chv;
> @@ -1222,10 +1199,8 @@ static int chv_crtc_compute_clock(struct intel_atomic_state *state,
>
> if (!crtc_state->clock_set &&
> !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> - refclk, NULL, &crtc_state->dpll)) {
> - drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
> + refclk, NULL, &crtc_state->dpll))
> return -EINVAL;
> - }
>
> chv_compute_dpll(crtc_state);
>
> @@ -1235,7 +1210,6 @@ static int chv_crtc_compute_clock(struct intel_atomic_state *state,
> static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> - struct drm_i915_private *i915 = to_i915(state->base.dev);
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> const struct intel_limit *limit = &intel_limits_vlv;
> @@ -1244,7 +1218,6 @@ static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
> if (!crtc_state->clock_set &&
> !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> refclk, NULL, &crtc_state->dpll)) {
> - drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
> return -EINVAL;
> }
>
> @@ -1286,11 +1259,8 @@ static int g4x_crtc_compute_clock(struct intel_atomic_state *state,
>
> if (!crtc_state->clock_set &&
> !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> - refclk, NULL, &crtc_state->dpll)) {
> - drm_err(&dev_priv->drm,
> - "Couldn't find PLL settings for mode!\n");
> + refclk, NULL, &crtc_state->dpll))
> return -EINVAL;
> - }
>
> i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
> &crtc_state->dpll);
> @@ -1322,11 +1292,8 @@ static int pnv_crtc_compute_clock(struct intel_atomic_state *state,
>
> if (!crtc_state->clock_set &&
> !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> - refclk, NULL, &crtc_state->dpll)) {
> - drm_err(&dev_priv->drm,
> - "Couldn't find PLL settings for mode!\n");
> + refclk, NULL, &crtc_state->dpll))
> return -EINVAL;
> - }
>
> i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
> &crtc_state->dpll);
> @@ -1358,11 +1325,8 @@ static int i9xx_crtc_compute_clock(struct intel_atomic_state *state,
>
> if (!crtc_state->clock_set &&
> !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> - refclk, NULL, &crtc_state->dpll)) {
> - drm_err(&dev_priv->drm,
> - "Couldn't find PLL settings for mode!\n");
> + refclk, NULL, &crtc_state->dpll))
> return -EINVAL;
> - }
>
> i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
> &crtc_state->dpll);
> @@ -1396,11 +1360,8 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
>
> if (!crtc_state->clock_set &&
> !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> - refclk, NULL, &crtc_state->dpll)) {
> - drm_err(&dev_priv->drm,
> - "Couldn't find PLL settings for mode!\n");
> + refclk, NULL, &crtc_state->dpll))
> return -EINVAL;
> - }
>
> i8xx_compute_dpll(crtc_state, &crtc_state->dpll,
> &crtc_state->dpll);
> @@ -1453,6 +1414,7 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
> struct drm_i915_private *i915 = to_i915(state->base.dev);
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> + int ret;
>
> drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
>
> @@ -1462,7 +1424,14 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
> if (!crtc_state->hw.enable)
> return 0;
>
> - return i915->dpll_funcs->crtc_compute_clock(state, crtc);
> + ret = i915->dpll_funcs->crtc_compute_clock(state, crtc);
> + if (ret) {
> + drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n",
> + crtc->base.base.id, crtc->base.name);
> + return ret;
> + }
> +
> + return 0;
> }
>
> int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
> @@ -1471,6 +1440,7 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
> struct drm_i915_private *i915 = to_i915(state->base.dev);
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> + int ret;
>
> drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
>
> @@ -1483,7 +1453,14 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
> if (!i915->dpll_funcs->crtc_get_shared_dpll)
> return 0;
>
> - return i915->dpll_funcs->crtc_get_shared_dpll(state, crtc);
> + ret = i915->dpll_funcs->crtc_get_shared_dpll(state, crtc);
> + if (ret) {
> + drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",
> + crtc->base.base.id, crtc->base.name);
> + return ret;
> + }
> +
> + return 0;
> }
>
> void
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index d426724d5a2e..4c24cd563560 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -1603,10 +1603,8 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
> break;
> }
>
> - if (!ctx.p) {
> - DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
> + if (!ctx.p)
> return -EINVAL;
> - }
>
> /*
> * gcc incorrectly analyses that these can be used without being
> @@ -2145,19 +2143,14 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
> struct dpll *clk_div)
> {
> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> /* Calculate HDMI div */
> /*
> * FIXME: tie the following calculation into
> * i9xx_crtc_compute_clock
> */
> - if (!bxt_find_best_dpll(crtc_state, clk_div)) {
> - drm_dbg(&i915->drm, "no PLL dividers found for clock %d pipe %c\n",
> - crtc_state->port_clock,
> - pipe_name(crtc->pipe));
> + if (!bxt_find_best_dpll(crtc_state, clk_div))
> return -EINVAL;
> - }
>
> drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
>
> @@ -2879,11 +2872,8 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
>
> ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
> pll_state, is_dkl);
> - if (ret) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Failed to find divisors for clock %d\n", clock);
> + if (ret)
> return ret;
> - }
>
> m1div = 2;
> m2div_int = dco_khz / (refclk_khz * m1div);
> @@ -2893,12 +2883,8 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> m2div_int = dco_khz / (refclk_khz * m1div);
> }
>
> - if (m2div_int > 255) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Failed to find mdiv for clock %d\n",
> - clock);
> + if (m2div_int > 255)
> return -EINVAL;
> - }
> }
> m2div_rem = dco_khz % (refclk_khz * m1div);
>
> @@ -3206,11 +3192,8 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
> else
> ret = icl_calc_dp_combo_pll(crtc_state, &pll_params);
>
> - if (ret) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Could not calculate combo PHY PLL state.\n");
> + if (ret)
> return ret;
> - }
>
> icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
>
> @@ -3265,12 +3248,8 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> port_dpll->pll = intel_find_shared_dpll(state, crtc,
> &port_dpll->hw_state,
> dpll_mask);
> - if (!port_dpll->pll) {
> - drm_dbg_kms(&dev_priv->drm,
> - "No combo PHY PLL found for [ENCODER:%d:%s]\n",
> - encoder->base.base.id, encoder->base.name);
> + if (!port_dpll->pll)
> return -EINVAL;
> - }
>
> intel_reference_shared_dpll(state, crtc,
> port_dpll->pll, &port_dpll->hw_state);
> @@ -3293,21 +3272,15 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
>
> port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> ret = icl_calc_tbt_pll(crtc_state, &pll_params);
> - if (ret) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Could not calculate TBT PLL state.\n");
> + if (ret)
> return ret;
> - }
>
> icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
>
> port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
> ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
> - if (ret) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Could not calculate MG PHY PLL state.\n");
> + if (ret)
> return ret;
> - }
>
> return 0;
> }
> @@ -3328,10 +3301,8 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
> port_dpll->pll = intel_find_shared_dpll(state, crtc,
> &port_dpll->hw_state,
> BIT(DPLL_ID_ICL_TBTPLL));
> - if (!port_dpll->pll) {
> - drm_dbg_kms(&dev_priv->drm, "No TBT-ALT PLL found\n");
> + if (!port_dpll->pll)
> return -EINVAL;
> - }
> intel_reference_shared_dpll(state, crtc,
> port_dpll->pll, &port_dpll->hw_state);
>
> @@ -3344,7 +3315,6 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
> BIT(dpll_id));
> if (!port_dpll->pll) {
> ret = -EINVAL;
> - drm_dbg_kms(&dev_priv->drm, "No MG PHY PLL found\n");
> goto err_unreference_tbt_pll;
> }
> intel_reference_shared_dpll(state, crtc,
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 44+ messages in thread
* [Intel-gfx] [PATCH 13/13] drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (11 preceding siblings ...)
2022-03-25 12:32 ` [Intel-gfx] [PATCH 12/13] drm/i915: Clean up DPLL related debugs Ville Syrjala
@ 2022-03-25 12:32 ` Ville Syrjala
2022-03-25 14:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations Patchwork
` (18 subsequent siblings)
31 siblings, 0 replies; 44+ messages in thread
From: Ville Syrjala @ 2022-03-25 12:32 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Only reassign the pipe's DPLL if it's going through a full
.compute_config() cycle. If OTOH it's just getting modeset
eg. in order to change cdclk there doesn't seem much point in
picking a new DPLL for it.
This should also prevent .get_dplls() from seeing a funky port_clock
for DP even in cases where the readout produces a non-standard
clock and we (for some reason) have decided to not fully recompute
the state to remedy the situation.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 17 +----------------
drivers/gpu/drm/i915/display/intel_dpll.c | 6 ++----
2 files changed, 3 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f6db0bd2da6f..41442a1635d9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7050,20 +7050,6 @@ intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
}
}
-static void intel_modeset_clear_plls(struct intel_atomic_state *state)
-{
- struct intel_crtc_state *new_crtc_state;
- struct intel_crtc *crtc;
- int i;
-
- for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
- if (!intel_crtc_needs_modeset(new_crtc_state))
- continue;
-
- intel_release_shared_dplls(state, crtc);
- }
-}
-
/*
* This implements the workaround described in the "notes" section of the mode
* set sequence documentation. When going from no pipes or single pipe to
@@ -7897,6 +7883,7 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
+ intel_release_shared_dplls(state, crtc);
continue;
}
@@ -7944,8 +7931,6 @@ static int intel_atomic_check(struct drm_device *dev,
ret = intel_modeset_calc_cdclk(state);
if (ret)
return ret;
-
- intel_modeset_clear_plls(state);
}
ret = intel_atomic_check_crtcs(state);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index cbb444a2ba9d..23b3171bd0d6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1443,11 +1443,9 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
int ret;
drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
+ drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll);
- if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
- return 0;
-
- if (!crtc_state->hw.enable)
+ if (!crtc_state->hw.enable || crtc_state->shared_dpll)
return 0;
if (!i915->dpll_funcs->crtc_get_shared_dpll)
--
2.34.1
^ permalink raw reply related [flat|nested] 44+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (12 preceding siblings ...)
2022-03-25 12:32 ` [Intel-gfx] [PATCH 13/13] drm/i915: Reassign DPLLs only for crtcs going throug .compute_config() Ville Syrjala
@ 2022-03-25 14:19 ` Patchwork
2022-03-25 14:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (17 subsequent siblings)
31 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2022-03-25 14:19 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations
URL : https://patchwork.freedesktop.org/series/101789/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3b931b51817a drm/i915: Make .get_dplls() return int
1b2d4a4a599e drm/i915: Pass dev_priv to intel_shared_dpll_init()
33ae484eb053 drm/i915: Remove pointless dpll_funcs checks
4a49b686c648 drm/i915: Adjust .crtc_compute_clock() calling convention
2e1ac19c4047 drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
4e89276790b2 drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()
3f11772ea836 drm/i915: Clear the dpll_hw_state when disabling a pipe
ca60dc3a2f8a drm/i915: Split out dg2_crtc_compute_clock()
f71777efae30 drm/i915: Add crtc .crtc_get_shared_dpll()
c64fe9a7ba0c drm/i915: Split shared dpll .get_dplls() into compute and get phases
-:191: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_1350MHz>
#191: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1063:
+ SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;
total: 0 errors, 0 warnings, 1 checks, 516 lines checked
f78032f898c7 drm/i915: Do .crtc_compute_clock() earlier
4d0d47819c90 drm/i915: Clean up DPLL related debugs
5d0098769f10 drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
^ permalink raw reply [flat|nested] 44+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Start reordering modeset clock calculations
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (13 preceding siblings ...)
2022-03-25 14:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations Patchwork
@ 2022-03-25 14:20 ` Patchwork
2022-03-25 14:24 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
` (16 subsequent siblings)
31 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2022-03-25 14:20 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations
URL : https://patchwork.freedesktop.org/series/101789/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 44+ messages in thread* [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Start reordering modeset clock calculations
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (14 preceding siblings ...)
2022-03-25 14:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-03-25 14:24 ` Patchwork
2022-03-25 14:41 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (15 subsequent siblings)
31 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2022-03-25 14:24 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations
URL : https://patchwork.freedesktop.org/series/101789/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' not found
^ permalink raw reply [flat|nested] 44+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Start reordering modeset clock calculations
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (15 preceding siblings ...)
2022-03-25 14:24 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
@ 2022-03-25 14:41 ` Patchwork
2022-03-29 13:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev2) Patchwork
` (14 subsequent siblings)
31 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2022-03-25 14:41 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 14832 bytes --]
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations
URL : https://patchwork.freedesktop.org/series/101789/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11405 -> Patchwork_22683
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22683 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22683, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/index.html
Participating hosts (45 -> 34)
------------------------------
Missing (11): fi-bdw-samus bat-dg1-6 bat-dg2-8 bat-dg2-9 fi-bsw-cyan bat-adlp-6 bat-adlp-4 bat-rpls-1 bat-rpls-2 bat-jsl-2 bat-jsl-1
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22683:
### IGT changes ###
#### Possible regressions ####
* igt@core_hotunplug@unbind-rebind:
- fi-cfl-guc: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-cfl-guc/igt@core_hotunplug@unbind-rebind.html
- fi-bsw-nick: NOTRUN -> [INCOMPLETE][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-bsw-nick/igt@core_hotunplug@unbind-rebind.html
* igt@gem_render_linear_blits@basic:
- fi-bwr-2160: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-bwr-2160/igt@gem_render_linear_blits@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-bwr-2160/igt@gem_render_linear_blits@basic.html
* igt@gem_render_tiled_blits@basic:
- fi-kbl-guc: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-kbl-guc/igt@gem_render_tiled_blits@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-kbl-guc/igt@gem_render_tiled_blits@basic.html
- fi-rkl-guc: [PASS][7] -> [INCOMPLETE][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-rkl-guc/igt@gem_render_tiled_blits@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-rkl-guc/igt@gem_render_tiled_blits@basic.html
* igt@gem_tiled_blits@basic:
- fi-elk-e7500: [PASS][9] -> [INCOMPLETE][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-elk-e7500/igt@gem_tiled_blits@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-elk-e7500/igt@gem_tiled_blits@basic.html
- fi-skl-6700k2: [PASS][11] -> [INCOMPLETE][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-skl-6700k2/igt@gem_tiled_blits@basic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-skl-6700k2/igt@gem_tiled_blits@basic.html
- fi-ilk-650: NOTRUN -> [INCOMPLETE][13]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-ilk-650/igt@gem_tiled_blits@basic.html
- fi-cfl-8109u: NOTRUN -> [INCOMPLETE][14]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-cfl-8109u/igt@gem_tiled_blits@basic.html
- fi-kbl-8809g: [PASS][15] -> [INCOMPLETE][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-kbl-8809g/igt@gem_tiled_blits@basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-kbl-8809g/igt@gem_tiled_blits@basic.html
#### Warnings ####
* igt@core_hotunplug@unbind-rebind:
- fi-cfl-8700k: [INCOMPLETE][17] ([i915#1982]) -> [INCOMPLETE][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-cfl-8700k/igt@core_hotunplug@unbind-rebind.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-cfl-8700k/igt@core_hotunplug@unbind-rebind.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@core_hotunplug@unbind-rebind:
- {fi-hsw-g3258}: [PASS][19] -> [INCOMPLETE][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-hsw-g3258/igt@core_hotunplug@unbind-rebind.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-hsw-g3258/igt@core_hotunplug@unbind-rebind.html
Known issues
------------
Here are the changes found in Patchwork_22683 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-gfx:
- fi-hsw-4770: NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#109315]) +17 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-hsw-4770/igt@amdgpu/amd_basic@cs-gfx.html
* igt@amdgpu/amd_basic@cs-multi-fence:
- fi-blb-e6850: NOTRUN -> [SKIP][22] ([fdo#109271]) +17 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-blb-e6850/igt@amdgpu/amd_basic@cs-multi-fence.html
* igt@gem_softpin@allocator-basic-reserve:
- fi-ilk-650: NOTRUN -> [SKIP][23] ([fdo#109271]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-ilk-650/igt@gem_softpin@allocator-basic-reserve.html
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#3012])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-hsw-4770/igt@i915_pm_backlight@basic-brightness.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770: NOTRUN -> [SKIP][25] ([fdo#109271] / [fdo#111827]) +8 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-hsw-4770/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-bsw-nick: NOTRUN -> [SKIP][26] ([fdo#109271] / [fdo#111827]) +8 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-bsw-nick/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@dp-edid-read:
- fi-cfl-guc: NOTRUN -> [SKIP][27] ([fdo#109271] / [fdo#111827]) +8 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-cfl-guc/igt@kms_chamelium@dp-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-cfl-guc: NOTRUN -> [SKIP][28] ([fdo#109271]) +9 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-cfl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-bsw-nick: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#5341])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-bsw-nick/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-hsw-4770: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#533])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-hsw-4770/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-cfl-guc: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#533])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-cfl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-hsw-4770: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#1072]) +3 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html
* igt@prime_vgem@basic-fence-flip:
- fi-bsw-nick: NOTRUN -> [SKIP][33] ([fdo#109271]) +37 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-bsw-nick/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-userptr:
- fi-hsw-4770: NOTRUN -> [SKIP][34] ([fdo#109271]) +2 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-hsw-4770/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-kbl-guc: NOTRUN -> [FAIL][35] ([i915#4312])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-kbl-guc/igt@runner@aborted.html
- fi-rkl-guc: NOTRUN -> [FAIL][36] ([i915#4312])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-rkl-guc/igt@runner@aborted.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- {fi-ehl-2}: [INCOMPLETE][37] -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-ehl-2/igt@core_hotunplug@unbind-rebind.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-ehl-2/igt@core_hotunplug@unbind-rebind.html
- {fi-jsl-1}: [INCOMPLETE][39] ([i915#1373]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-jsl-1/igt@core_hotunplug@unbind-rebind.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-jsl-1/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_suspend@basic-s3@smem:
- {fi-rkl-11600}: [INCOMPLETE][41] ([i915#5127]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-rkl-11600/igt@gem_exec_suspend@basic-s3@smem.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-rkl-11600/igt@gem_exec_suspend@basic-s3@smem.html
* igt@gem_render_linear_blits@basic:
- fi-ilk-650: [INCOMPLETE][43] -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-ilk-650/igt@gem_render_linear_blits@basic.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-ilk-650/igt@gem_render_linear_blits@basic.html
* igt@gem_render_tiled_blits@basic:
- fi-bsw-nick: [INCOMPLETE][45] -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-bsw-nick/igt@gem_render_tiled_blits@basic.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-bsw-nick/igt@gem_render_tiled_blits@basic.html
- fi-cfl-8109u: [INCOMPLETE][47] -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-cfl-8109u/igt@gem_render_tiled_blits@basic.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-cfl-8109u/igt@gem_render_tiled_blits@basic.html
* igt@gem_tiled_blits@basic:
- fi-cfl-guc: [INCOMPLETE][49] -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-cfl-guc/igt@gem_tiled_blits@basic.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-cfl-guc/igt@gem_tiled_blits@basic.html
- fi-hsw-4770: [INCOMPLETE][51] -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-hsw-4770/igt@gem_tiled_blits@basic.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-hsw-4770/igt@gem_tiled_blits@basic.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [DMESG-FAIL][53] ([i915#4528]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-blb-e6850/igt@i915_selftest@live@requests.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-blb-e6850/igt@i915_selftest@live@requests.html
#### Warnings ####
* igt@runner@aborted:
- fi-bsw-nick: [FAIL][55] ([i915#3428] / [i915#4312]) -> [FAIL][56] ([i915#4312])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-bsw-nick/igt@runner@aborted.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/fi-bsw-nick/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1373]: https://gitlab.freedesktop.org/drm/intel/issues/1373
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
Build changes
-------------
* Linux: CI_DRM_11405 -> Patchwork_22683
CI-20190529: 20190529
CI_DRM_11405: 631579c25b67cc4a6ee014440ddcac6c72b9bf50 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6393: 1d267ea1b829fa10b31a37ccf6b4a970f032784a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22683: 5d0098769f1066470c1b7cdb22c0b066ff517a34 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5d0098769f10 drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
4d0d47819c90 drm/i915: Clean up DPLL related debugs
f78032f898c7 drm/i915: Do .crtc_compute_clock() earlier
c64fe9a7ba0c drm/i915: Split shared dpll .get_dplls() into compute and get phases
f71777efae30 drm/i915: Add crtc .crtc_get_shared_dpll()
ca60dc3a2f8a drm/i915: Split out dg2_crtc_compute_clock()
3f11772ea836 drm/i915: Clear the dpll_hw_state when disabling a pipe
4e89276790b2 drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()
2e1ac19c4047 drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
4a49b686c648 drm/i915: Adjust .crtc_compute_clock() calling convention
33ae484eb053 drm/i915: Remove pointless dpll_funcs checks
1b2d4a4a599e drm/i915: Pass dev_priv to intel_shared_dpll_init()
3b931b51817a drm/i915: Make .get_dplls() return int
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22683/index.html
[-- Attachment #2: Type: text/html, Size: 16884 bytes --]
^ permalink raw reply [flat|nested] 44+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev2)
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (16 preceding siblings ...)
2022-03-25 14:41 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2022-03-29 13:18 ` Patchwork
2022-03-29 13:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (13 subsequent siblings)
31 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2022-03-29 13:18 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations (rev2)
URL : https://patchwork.freedesktop.org/series/101789/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0cc647463e24 drm/i915: Make .get_dplls() return int
26c2cde200f7 drm/i915: Pass dev_priv to intel_shared_dpll_init()
9cf895d61032 drm/i915: Remove pointless dpll_funcs checks
b7d2de662b35 drm/i915: Adjust .crtc_compute_clock() calling convention
9c981811d68a drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
b0721bb72949 drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()
9ecae4f49f80 drm/i915: Clear the dpll_hw_state when disabling a pipe
beebcc4f0775 drm/i915: Split out dg2_crtc_compute_clock()
c5be89e9a6f5 drm/i915: Add crtc .crtc_get_shared_dpll()
0ae7daafcb24 drm/i915: Split shared dpll .get_dplls() into compute and get phases
-:191: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_1350MHz>
#191: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1063:
+ SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;
total: 0 errors, 0 warnings, 1 checks, 516 lines checked
6bcc7005f5e4 drm/i915: Do .crtc_compute_clock() earlier
1d25064542ce drm/i915: Clean up DPLL related debugs
1ebfaa21192e drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
^ permalink raw reply [flat|nested] 44+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Start reordering modeset clock calculations (rev2)
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (17 preceding siblings ...)
2022-03-29 13:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev2) Patchwork
@ 2022-03-29 13:19 ` Patchwork
2022-03-29 13:23 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
` (12 subsequent siblings)
31 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2022-03-29 13:19 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations (rev2)
URL : https://patchwork.freedesktop.org/series/101789/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 44+ messages in thread* [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Start reordering modeset clock calculations (rev2)
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (18 preceding siblings ...)
2022-03-29 13:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-03-29 13:23 ` Patchwork
2022-03-29 13:59 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (11 subsequent siblings)
31 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2022-03-29 13:23 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations (rev2)
URL : https://patchwork.freedesktop.org/series/101789/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' not found
^ permalink raw reply [flat|nested] 44+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Start reordering modeset clock calculations (rev2)
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (19 preceding siblings ...)
2022-03-29 13:23 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
@ 2022-03-29 13:59 ` Patchwork
2022-03-30 1:29 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev3) Patchwork
` (10 subsequent siblings)
31 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2022-03-29 13:59 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 17736 bytes --]
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations (rev2)
URL : https://patchwork.freedesktop.org/series/101789/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22717
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22717 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22717, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/index.html
Participating hosts (42 -> 45)
------------------------------
Additional (7): fi-cml-u2 fi-tgl-u2 fi-skl-guc fi-icl-u2 fi-cfl-8700k bat-adlp-4 fi-ivb-3770
Missing (4): fi-bsw-cyan fi-bdw-samus shard-tglu fi-ilk-650
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22717:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_suspend@basic-s3@smem:
- fi-cml-u2: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-cml-u2/igt@gem_exec_suspend@basic-s3@smem.html
* igt@runner@aborted:
- bat-adlp-4: NOTRUN -> [FAIL][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/bat-adlp-4/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_22717 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-bsw-kefka/igt@amdgpu/amd_basic@query-info.html
* igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770: NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#109315]) +17 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-hsw-4770/igt@amdgpu/amd_basic@semaphore.html
* igt@amdgpu/amd_basic@userptr:
- fi-cfl-8700k: NOTRUN -> [SKIP][5] ([fdo#109271]) +29 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-cfl-8700k/igt@amdgpu/amd_basic@userptr.html
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][6] ([fdo#109315]) +17 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2: NOTRUN -> [SKIP][7] ([i915#1208]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-cml-u2/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-u2: NOTRUN -> [SKIP][8] ([i915#2190])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html
- fi-cfl-8700k: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-cfl-8700k/igt@gem_huc_copy@huc-copy.html
- fi-icl-u2: NOTRUN -> [SKIP][10] ([i915#2190])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][11] ([i915#4613]) +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@random-engines:
- fi-skl-guc: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +3 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-skl-guc/igt@gem_lmem_swapping@random-engines.html
- fi-ivb-3770: NOTRUN -> [SKIP][13] ([fdo#109271]) +18 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-ivb-3770/igt@gem_lmem_swapping@random-engines.html
- fi-cfl-8700k: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +3 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-cfl-8700k/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- fi-tgl-u2: NOTRUN -> [SKIP][15] ([i915#4613]) +3 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-tgl-u2/igt@gem_lmem_swapping@verify-random.html
* igt@i915_selftest@live@gt_engines:
- bat-dg1-6: [PASS][16] -> [INCOMPLETE][17] ([i915#4418])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@hangcheck:
- fi-ivb-3770: NOTRUN -> [INCOMPLETE][18] ([i915#3303] / [i915#5370])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-ivb-3770/igt@i915_selftest@live@hangcheck.html
* igt@kms_busy@basic@flip:
- fi-tgl-u2: NOTRUN -> [DMESG-WARN][19] ([i915#402]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-tgl-u2/igt@kms_busy@basic@flip.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-u2: NOTRUN -> [SKIP][20] ([fdo#109284] / [fdo#111827]) +8 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-tgl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
- fi-skl-guc: NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827]) +8 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-skl-guc/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cfl-8700k: NOTRUN -> [SKIP][22] ([fdo#109271] / [fdo#111827]) +8 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-cfl-8700k/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-ivb-3770: NOTRUN -> [SKIP][23] ([fdo#109271] / [fdo#111827]) +8 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-ivb-3770/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][24] ([fdo#111827]) +8 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2: NOTRUN -> [SKIP][25] ([i915#4103]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-icl-u2: NOTRUN -> [SKIP][26] ([fdo#109278]) +2 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-modeset@c-dp3:
- fi-tgl-1115g4: [PASS][27] -> [DMESG-WARN][28] ([i915#4002]) +63 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-tgl-1115g4/igt@kms_flip@basic-flip-vs-modeset@c-dp3.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-tgl-1115g4/igt@kms_flip@basic-flip-vs-modeset@c-dp3.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-u2: NOTRUN -> [SKIP][29] ([fdo#109285])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html
- fi-icl-u2: NOTRUN -> [SKIP][30] ([fdo#109285])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-tgl-1115g4: [PASS][31] -> [DMESG-WARN][32] ([i915#4002] / [i915#5341])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-tgl-1115g4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-tgl-1115g4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-guc: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#533])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-skl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-cfl-8700k: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#533])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-cfl-8700k/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-skl-guc: NOTRUN -> [SKIP][35] ([fdo#109271]) +29 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-skl-guc/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-tgl-u2: NOTRUN -> [SKIP][36] ([i915#3555])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-tgl-u2/igt@kms_setmode@basic-clone-single-crtc.html
- fi-icl-u2: NOTRUN -> [SKIP][37] ([i915#3555])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-icl-u2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- fi-icl-u2: NOTRUN -> [SKIP][38] ([i915#3301])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-icl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-ivb-3770: NOTRUN -> [FAIL][39] ([fdo#109271] / [i915#4312])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-ivb-3770/igt@runner@aborted.html
- bat-dg1-6: NOTRUN -> [FAIL][40] ([i915#4312] / [i915#5257])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/bat-dg1-6/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [INCOMPLETE][41] ([i915#2940]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_lrc:
- {bat-adlp-6}: [INCOMPLETE][43] -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-adlp-6/igt@i915_selftest@live@gt_lrc.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/bat-adlp-6/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@guc_multi_lrc:
- {bat-rpls-2}: [DMESG-WARN][45] ([i915#4391]) -> [PASS][46] +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-rpls-2/igt@i915_selftest@live@guc_multi_lrc.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/bat-rpls-2/igt@i915_selftest@live@guc_multi_lrc.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][47] ([i915#4785]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
- {fi-hsw-g3258}: [INCOMPLETE][49] ([i915#3303] / [i915#4785]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
- {fi-ehl-2}: [INCOMPLETE][51] -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-ehl-2/igt@i915_selftest@live@hangcheck.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-ehl-2/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@workarounds:
- {bat-adlp-6}: [DMESG-WARN][53] ([i915#5068]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-adlp-6/igt@i915_selftest@live@workarounds.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/bat-adlp-6/igt@i915_selftest@live@workarounds.html
* igt@kms_busy@basic@flip:
- {bat-adlp-6}: [DMESG-WARN][55] ([i915#3576]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-adlp-6/igt@kms_busy@basic@flip.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/bat-adlp-6/igt@kms_busy@basic@flip.html
- {bat-dg2-9}: [DMESG-WARN][57] ([i915#5291]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg2-9/igt@kms_busy@basic@flip.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/bat-dg2-9/igt@kms_busy@basic@flip.html
#### Warnings ####
* igt@gem_lmem_swapping@basic:
- fi-tgl-1115g4: [SKIP][59] ([i915#4613]) -> [SKIP][60] ([i915#1385] / [i915#4613]) +3 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-tgl-1115g4/igt@gem_lmem_swapping@basic.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/fi-tgl-1115g4/igt@gem_lmem_swapping@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1208]: https://gitlab.freedesktop.org/drm/intel/issues/1208
[i915#1385]: https://gitlab.freedesktop.org/drm/intel/issues/1385
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4002]: https://gitlab.freedesktop.org/drm/intel/issues/4002
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
[i915#5068]: https://gitlab.freedesktop.org/drm/intel/issues/5068
[i915#5195]: https://gitlab.freedesktop.org/drm/intel/issues/5195
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5291]: https://gitlab.freedesktop.org/drm/intel/issues/5291
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
[i915#5370]: https://gitlab.freedesktop.org/drm/intel/issues/5370
Build changes
-------------
* Linux: CI_DRM_11416 -> Patchwork_22717
CI-20190529: 20190529
CI_DRM_11416: 1dc2c6953e2689a0e5b7cca8450da14059d35f03 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6399: 9ba6cb16f04319226383b57975db203561c75781 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22717: 1ebfaa21192e6c417f930bb65c4de38d4365ff43 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1ebfaa21192e drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
1d25064542ce drm/i915: Clean up DPLL related debugs
6bcc7005f5e4 drm/i915: Do .crtc_compute_clock() earlier
0ae7daafcb24 drm/i915: Split shared dpll .get_dplls() into compute and get phases
c5be89e9a6f5 drm/i915: Add crtc .crtc_get_shared_dpll()
beebcc4f0775 drm/i915: Split out dg2_crtc_compute_clock()
9ecae4f49f80 drm/i915: Clear the dpll_hw_state when disabling a pipe
b0721bb72949 drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()
9c981811d68a drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
b7d2de662b35 drm/i915: Adjust .crtc_compute_clock() calling convention
9cf895d61032 drm/i915: Remove pointless dpll_funcs checks
26c2cde200f7 drm/i915: Pass dev_priv to intel_shared_dpll_init()
0cc647463e24 drm/i915: Make .get_dplls() return int
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22717/index.html
[-- Attachment #2: Type: text/html, Size: 20702 bytes --]
^ permalink raw reply [flat|nested] 44+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev3)
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (20 preceding siblings ...)
2022-03-29 13:59 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2022-03-30 1:29 ` Patchwork
2022-03-30 1:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (9 subsequent siblings)
31 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2022-03-30 1:29 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations (rev3)
URL : https://patchwork.freedesktop.org/series/101789/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
eef669f225cd drm/i915: Make .get_dplls() return int
526bd16336db drm/i915: Pass dev_priv to intel_shared_dpll_init()
657130d86c57 drm/i915: Remove pointless dpll_funcs checks
d97da58c081b drm/i915: Adjust .crtc_compute_clock() calling convention
8229e8880231 drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
fc05b45e8924 drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()
afcd83860b16 drm/i915: Clear the dpll_hw_state when disabling a pipe
871f0d8b7c92 drm/i915: Split out dg2_crtc_compute_clock()
2ebb495949cc drm/i915: Add crtc .crtc_get_shared_dpll()
1d067b0daf49 drm/i915: Split shared dpll .get_dplls() into compute and get phases
-:191: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_1350MHz>
#191: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1063:
+ SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;
total: 0 errors, 0 warnings, 1 checks, 516 lines checked
f52d29ef90c2 drm/i915: Do .crtc_compute_clock() earlier
282084c82d01 drm/i915: Clean up DPLL related debugs
0c8cf5704839 drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
^ permalink raw reply [flat|nested] 44+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Start reordering modeset clock calculations (rev3)
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (21 preceding siblings ...)
2022-03-30 1:29 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev3) Patchwork
@ 2022-03-30 1:31 ` Patchwork
2022-03-30 1:35 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
` (8 subsequent siblings)
31 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2022-03-30 1:31 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations (rev3)
URL : https://patchwork.freedesktop.org/series/101789/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 44+ messages in thread* [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Start reordering modeset clock calculations (rev3)
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (22 preceding siblings ...)
2022-03-30 1:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-03-30 1:35 ` Patchwork
2022-03-30 2:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (7 subsequent siblings)
31 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2022-03-30 1:35 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations (rev3)
URL : https://patchwork.freedesktop.org/series/101789/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' not found
^ permalink raw reply [flat|nested] 44+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Start reordering modeset clock calculations (rev3)
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (23 preceding siblings ...)
2022-03-30 1:35 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
@ 2022-03-30 2:09 ` Patchwork
2022-03-30 3:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (6 subsequent siblings)
31 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2022-03-30 2:09 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 14795 bytes --]
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations (rev3)
URL : https://patchwork.freedesktop.org/series/101789/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22729
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/index.html
Participating hosts (44 -> 45)
------------------------------
Additional (6): fi-tgl-u2 fi-skl-guc fi-icl-u2 fi-cfl-8700k fi-ivb-3770 fi-pnv-d510
Missing (5): shard-tglu fi-bsw-cyan shard-rkl shard-dg1 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_22729 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-bsw-kefka/igt@amdgpu/amd_basic@query-info.html
* igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770: NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#109315]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-hsw-4770/igt@amdgpu/amd_basic@semaphore.html
* igt@amdgpu/amd_basic@userptr:
- fi-cfl-8700k: NOTRUN -> [SKIP][3] ([fdo#109271]) +29 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-cfl-8700k/igt@amdgpu/amd_basic@userptr.html
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][4] ([fdo#109315]) +17 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html
* igt@gem_huc_copy@huc-copy:
- fi-pnv-d510: NOTRUN -> [SKIP][5] ([fdo#109271]) +57 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-pnv-d510/igt@gem_huc_copy@huc-copy.html
- fi-tgl-u2: NOTRUN -> [SKIP][6] ([i915#2190])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html
- fi-cfl-8700k: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-cfl-8700k/igt@gem_huc_copy@huc-copy.html
- fi-icl-u2: NOTRUN -> [SKIP][8] ([i915#2190])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@random-engines:
- fi-skl-guc: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-skl-guc/igt@gem_lmem_swapping@random-engines.html
- fi-ivb-3770: NOTRUN -> [SKIP][11] ([fdo#109271]) +36 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-ivb-3770/igt@gem_lmem_swapping@random-engines.html
- fi-cfl-8700k: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +3 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-cfl-8700k/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- fi-tgl-u2: NOTRUN -> [SKIP][13] ([i915#4613]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-tgl-u2/igt@gem_lmem_swapping@verify-random.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-u2: NOTRUN -> [SKIP][14] ([fdo#109284] / [fdo#111827]) +8 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-tgl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
- fi-skl-guc: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +8 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-skl-guc/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cfl-8700k: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-cfl-8700k/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-ivb-3770: NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +8 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-ivb-3770/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][18] ([fdo#111827]) +8 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2: NOTRUN -> [SKIP][19] ([i915#4103]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-icl-u2: NOTRUN -> [SKIP][20] ([fdo#109278]) +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-dpms@a-edp1:
- fi-tgl-u2: NOTRUN -> [DMESG-WARN][21] ([i915#402]) +2 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-tgl-u2/igt@kms_flip@basic-flip-vs-dpms@a-edp1.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-u2: NOTRUN -> [SKIP][22] ([fdo#109285])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html
- fi-icl-u2: NOTRUN -> [SKIP][23] ([fdo#109285])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-pnv-d510: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#5341])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-pnv-d510/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-guc: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#533])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-skl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-cfl-8700k: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#533])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-cfl-8700k/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-skl-guc: NOTRUN -> [SKIP][27] ([fdo#109271]) +29 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-skl-guc/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-tgl-u2: NOTRUN -> [SKIP][28] ([i915#3555])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-tgl-u2/igt@kms_setmode@basic-clone-single-crtc.html
- fi-icl-u2: NOTRUN -> [SKIP][29] ([i915#3555])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-icl-u2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- fi-icl-u2: NOTRUN -> [SKIP][30] ([i915#3301])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-icl-u2/igt@prime_vgem@basic-userptr.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [INCOMPLETE][31] ([i915#2940]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_lrc:
- {bat-adlp-6}: [INCOMPLETE][33] -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-adlp-6/igt@i915_selftest@live@gt_lrc.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/bat-adlp-6/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@guc_multi_lrc:
- {bat-rpls-2}: [DMESG-WARN][35] ([i915#4391]) -> [PASS][36] +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-rpls-2/igt@i915_selftest@live@guc_multi_lrc.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/bat-rpls-2/igt@i915_selftest@live@guc_multi_lrc.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][37] ([i915#4785]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
- {fi-hsw-g3258}: [INCOMPLETE][39] ([i915#3303] / [i915#4785]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
- {fi-ehl-2}: [INCOMPLETE][41] -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-ehl-2/igt@i915_selftest@live@hangcheck.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-ehl-2/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- {bat-rpls-2}: [DMESG-FAIL][43] ([i915#5087]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-rpls-2/igt@i915_selftest@live@requests.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/bat-rpls-2/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@workarounds:
- {bat-adlp-6}: [DMESG-WARN][45] ([i915#5068]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-adlp-6/igt@i915_selftest@live@workarounds.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/bat-adlp-6/igt@i915_selftest@live@workarounds.html
* igt@kms_busy@basic@flip:
- {bat-dg2-9}: [DMESG-WARN][47] ([i915#5291]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg2-9/igt@kms_busy@basic@flip.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/bat-dg2-9/igt@kms_busy@basic@flip.html
* igt@kms_busy@basic@modeset:
- {bat-adlp-6}: [DMESG-WARN][49] ([i915#3576]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-adlp-6/igt@kms_busy@basic@modeset.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/bat-adlp-6/igt@kms_busy@basic@modeset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#5068]: https://gitlab.freedesktop.org/drm/intel/issues/5068
[i915#5087]: https://gitlab.freedesktop.org/drm/intel/issues/5087
[i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
[i915#5193]: https://gitlab.freedesktop.org/drm/intel/issues/5193
[i915#5270]: https://gitlab.freedesktop.org/drm/intel/issues/5270
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5275]: https://gitlab.freedesktop.org/drm/intel/issues/5275
[i915#5291]: https://gitlab.freedesktop.org/drm/intel/issues/5291
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
Build changes
-------------
* Linux: CI_DRM_11416 -> Patchwork_22729
CI-20190529: 20190529
CI_DRM_11416: 1dc2c6953e2689a0e5b7cca8450da14059d35f03 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6399: 9ba6cb16f04319226383b57975db203561c75781 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22729: 0c8cf5704839e297033c0ab340f1cbeca764f85c @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0c8cf5704839 drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
282084c82d01 drm/i915: Clean up DPLL related debugs
f52d29ef90c2 drm/i915: Do .crtc_compute_clock() earlier
1d067b0daf49 drm/i915: Split shared dpll .get_dplls() into compute and get phases
2ebb495949cc drm/i915: Add crtc .crtc_get_shared_dpll()
871f0d8b7c92 drm/i915: Split out dg2_crtc_compute_clock()
afcd83860b16 drm/i915: Clear the dpll_hw_state when disabling a pipe
fc05b45e8924 drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()
8229e8880231 drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
d97da58c081b drm/i915: Adjust .crtc_compute_clock() calling convention
657130d86c57 drm/i915: Remove pointless dpll_funcs checks
526bd16336db drm/i915: Pass dev_priv to intel_shared_dpll_init()
eef669f225cd drm/i915: Make .get_dplls() return int
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/index.html
[-- Attachment #2: Type: text/html, Size: 17436 bytes --]
^ permalink raw reply [flat|nested] 44+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Start reordering modeset clock calculations (rev3)
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (24 preceding siblings ...)
2022-03-30 2:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-03-30 3:37 ` Patchwork
2022-04-14 2:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev4) Patchwork
` (5 subsequent siblings)
31 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2022-03-30 3:37 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30284 bytes --]
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations (rev3)
URL : https://patchwork.freedesktop.org/series/101789/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11416_full -> Patchwork_22729_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22729_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22729_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22729_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@flip-vs-suspend@b-edp1:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglb7/igt@kms_flip@flip-vs-suspend@b-edp1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb1/igt@kms_flip@flip-vs-suspend@b-edp1.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_psr_stress_test@flip-primary-invalidate-overlay}:
- shard-tglb: [PASS][3] -> [SKIP][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglb6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb5/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
Known issues
------------
Here are the changes found in Patchwork_22729_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-snb5/igt@gem_ctx_persistence@legacy-engines-queued.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-tglb: NOTRUN -> [SKIP][6] ([i915#280])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-apl: [PASS][7] -> [TIMEOUT][8] ([i915#3063])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-apl2/igt@gem_eio@in-flight-contexts-10ms.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-apl7/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#232])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglb7/igt@gem_eio@unwedge-stress.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb3/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#4547])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-skl2/igt@gem_exec_capture@pi@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl10/igt@gem_exec_capture@pi@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][15] -> [FAIL][16] ([i915#2842])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-iclb5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
- shard-glk: [PASS][17] -> [FAIL][18] ([i915#2842])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-glk8/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-glk4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_schedule@submit-early-slice@bcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][19] ([i915#3797])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl3/igt@gem_exec_schedule@submit-early-slice@bcs0.html
* igt@gem_lmem_swapping@parallel-random:
- shard-tglb: NOTRUN -> [SKIP][20] ([i915#4613])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_lmem_swapping@smem-oom:
- shard-apl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-apl8/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_lmem_swapping@verify-random:
- shard-skl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#4613]) +2 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl7/igt@gem_lmem_swapping@verify-random.html
* igt@gem_pread@exhaustion:
- shard-snb: NOTRUN -> [WARN][23] ([i915#2658])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-snb5/igt@gem_pread@exhaustion.html
* igt@gem_pxp@reject-modify-context-protection-off-2:
- shard-iclb: NOTRUN -> [SKIP][24] ([i915#4270])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-iclb8/igt@gem_pxp@reject-modify-context-protection-off-2.html
* igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
- shard-tglb: NOTRUN -> [SKIP][25] ([i915#4270])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][26] ([i915#768])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-iclb8/igt@gem_render_copy@linear-to-vebox-y-tiled.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-skl: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3323])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl1/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@input-checking:
- shard-kbl: NOTRUN -> [DMESG-WARN][28] ([i915#4991])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-kbl6/igt@gem_userptr_blits@input-checking.html
* igt@gen7_exec_parse@basic-allowed:
- shard-tglb: NOTRUN -> [SKIP][29] ([fdo#109289]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@gen7_exec_parse@basic-allowed.html
* igt@gen9_exec_parse@basic-rejected-ctx-param:
- shard-iclb: NOTRUN -> [SKIP][30] ([i915#2856])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-iclb8/igt@gen9_exec_parse@basic-rejected-ctx-param.html
* igt@gen9_exec_parse@cmd-crossing-page:
- shard-tglb: NOTRUN -> [SKIP][31] ([i915#2527] / [i915#2856])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@i915_pm_rpm@gem-mmap-type@gtt:
- shard-tglb: [PASS][32] -> [INCOMPLETE][33] ([i915#2411])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglb7/igt@i915_pm_rpm@gem-mmap-type@gtt.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb7/igt@i915_pm_rpm@gem-mmap-type@gtt.html
* igt@i915_selftest@live@gt_lrc:
- shard-tglb: NOTRUN -> [DMESG-FAIL][34] ([i915#2373])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@gt_pm:
- shard-tglb: NOTRUN -> [DMESG-FAIL][35] ([i915#1759])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@i915_selftest@live@gt_pm.html
* igt@kms_async_flips@crc:
- shard-skl: NOTRUN -> [FAIL][36] ([i915#4272])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl6/igt@kms_async_flips@crc.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-180:
- shard-tglb: NOTRUN -> [SKIP][37] ([i915#5286])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@kms_big_fb@4-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@linear-32bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][38] ([fdo#111614])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@kms_big_fb@linear-32bpp-rotate-270.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][39] ([fdo#110725] / [fdo#111614])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-iclb8/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][40] ([i915#3743]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-apl: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#3777])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-apl8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-tglb: NOTRUN -> [SKIP][42] ([fdo#111615])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-skl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#3777]) +5 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][44] ([fdo#109278]) +3 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-iclb8/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][45] ([i915#3689] / [i915#3886])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#3886]) +8 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl7/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-rotation-90-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][47] ([fdo#111615] / [i915#3689])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@kms_ccs@pipe-b-bad-rotation-90-yf_tiled_ccs.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#3886]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-kbl6/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#3886])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-apl7/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][50] ([i915#3689]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs.html
* igt@kms_chamelium@hdmi-hpd-storm-disable:
- shard-skl: NOTRUN -> [SKIP][51] ([fdo#109271] / [fdo#111827]) +20 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl1/igt@kms_chamelium@hdmi-hpd-storm-disable.html
* igt@kms_color_chamelium@pipe-b-ctm-blue-to-red:
- shard-kbl: NOTRUN -> [SKIP][52] ([fdo#109271] / [fdo#111827])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-kbl6/igt@kms_color_chamelium@pipe-b-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-c-ctm-0-25:
- shard-tglb: NOTRUN -> [SKIP][53] ([fdo#109284] / [fdo#111827]) +3 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@kms_color_chamelium@pipe-c-ctm-0-25.html
* igt@kms_color_chamelium@pipe-d-ctm-limited-range:
- shard-apl: NOTRUN -> [SKIP][54] ([fdo#109271] / [fdo#111827]) +4 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-apl8/igt@kms_color_chamelium@pipe-d-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-d-ctm-negative:
- shard-iclb: NOTRUN -> [SKIP][55] ([fdo#109278] / [fdo#109284] / [fdo#111827]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-iclb8/igt@kms_color_chamelium@pipe-d-ctm-negative.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-tglb: NOTRUN -> [SKIP][56] ([i915#3116] / [i915#3299])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding:
- shard-tglb: NOTRUN -> [SKIP][57] ([i915#3359]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [PASS][58] -> [DMESG-WARN][59] ([i915#180])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-tglb: NOTRUN -> [SKIP][60] ([i915#4103])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][61] -> [FAIL][62] ([i915#2346] / [i915#533])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic:
- shard-skl: [PASS][63] -> [FAIL][64] ([i915#2346])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
- shard-iclb: [PASS][65] -> [FAIL][66] ([i915#2346])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb2/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-4tiled:
- shard-tglb: NOTRUN -> [SKIP][67] ([i915#5287])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-4tiled.html
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
- shard-tglb: NOTRUN -> [SKIP][68] ([fdo#109274] / [fdo#111825]) +2 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
- shard-apl: NOTRUN -> [SKIP][69] ([fdo#109271]) +70 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-apl3/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][70] -> [FAIL][71] ([i915#79])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [PASS][72] -> [FAIL][73] ([i915#79])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@a-dp1:
- shard-apl: [PASS][74] -> [FAIL][75] ([i915#79])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-apl4/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-apl8/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: NOTRUN -> [FAIL][76] ([i915#2122]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_flip@plain-flip-fb-recreate@a-edp1:
- shard-skl: [PASS][77] -> [FAIL][78] ([i915#2122])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-skl4/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl4/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite:
- shard-iclb: NOTRUN -> [SKIP][79] ([fdo#109280])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [PASS][80] -> [DMESG-WARN][81] ([i915#180]) +2 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][82] ([fdo#109271]) +266 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl7/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-tglb: NOTRUN -> [SKIP][83] ([fdo#109280] / [fdo#111825]) +6 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a:
- shard-skl: NOTRUN -> [FAIL][84] ([i915#1188])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl6/igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#533]) +2 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl3/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
- shard-apl: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#533])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-apl8/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl: NOTRUN -> [FAIL][87] ([fdo#108145] / [i915#265]) +2 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-kbl: NOTRUN -> [FAIL][88] ([fdo#108145] / [i915#265])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-kbl6/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][89] ([i915#265])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][90] -> [FAIL][91] ([fdo#108145] / [i915#265])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-4:
- shard-tglb: NOTRUN -> [SKIP][92] ([i915#5288])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@kms_plane_lowres@pipe-a-tiling-4.html
* igt@kms_plane_lowres@pipe-b-tiling-y:
- shard-iclb: NOTRUN -> [SKIP][93] ([i915#3536])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-iclb8/igt@kms_plane_lowres@pipe-b-tiling-y.html
* igt@kms_plane_multiple@atomic-pipe-d-tiling-x:
- shard-kbl: NOTRUN -> [SKIP][94] ([fdo#109271]) +31 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-kbl6/igt@kms_plane_multiple@atomic-pipe-d-tiling-x.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-edp-1-planes-upscale-downscale:
- shard-iclb: [PASS][95] -> [SKIP][96] ([i915#5235]) +2 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-edp-1-planes-upscale-downscale.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-edp-1-planes-upscale-downscale.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-skl: NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#658]) +1 similar issue
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-apl: NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#658])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-apl8/igt@kms_psr2_su@frontbuffer-xrgb8888.html
- shard-iclb: NOTRUN -> [SKIP][99] ([fdo#109642] / [fdo#111068] / [i915#658])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-iclb8/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-tglb: NOTRUN -> [FAIL][100] ([i915#132] / [i915#3467])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: [PASS][101] -> [SKIP][102] ([fdo#109441]) +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-iclb7/igt@kms_psr@psr2_sprite_render.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
- shard-snb: NOTRUN -> [SKIP][103] ([fdo#109271]) +76 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-snb5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][104] -> [DMESG-WARN][105] ([i915#180] / [i915#295])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-apl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-apl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-kbl: [PASS][106] -> [INCOMPLETE][107] ([i915#2828])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-kbl6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-kbl4/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-tglb: NOTRUN -> [SKIP][108] ([i915#2437])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-c-ctx-flip-skip-current-frame:
- shard-iclb: NOTRUN -> [SKIP][109] ([i915#2530])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-iclb8/igt@nouveau_crc@pipe-c-ctx-flip-skip-current-frame.html
* igt@perf@polling-parameterized:
- shard-glk: [PASS][110] -> [FAIL][111] ([i915#1542])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-glk5/igt@perf@polling-parameterized.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-glk1/igt@perf@polling-parameterized.html
* igt@perf_pmu@rc6-suspend:
- shard-kbl: NOTRUN -> [DMESG-WARN][112] ([i915#180])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-kbl6/igt@perf_pmu@rc6-suspend.html
* igt@prime_nv_api@i915_nv_import_twice:
- shard-iclb: NOTRUN -> [SKIP][113] ([fdo#109291])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-iclb8/igt@prime_nv_api@i915_nv_import_twice.html
* igt@prime_nv_pcopy@test3_2:
- shard-tglb: NOTRUN -> [SKIP][114] ([fdo#109291])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@prime_nv_pcopy@test3_2.html
* igt@syncobj_timeline@transfer-timeline-point:
- shard-apl: NOTRUN -> [DMESG-FAIL][115] ([i915#5098])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-apl3/igt@syncobj_timeline@transfer-timeline-point.html
* igt@sysfs_clients@busy:
- shard-kbl: NOTRUN -> [SKIP][116] ([fdo#109271] / [i915#2994])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-kbl6/igt@sysfs_clients@busy.html
* igt@sysfs_clients@fair-7:
- shard-iclb: NOTRUN -> [SKIP][117] ([i915#2994])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-iclb8/igt@sysfs_clients@fair-7.html
* igt@sysfs_clients@sema-10:
- shard-skl: NOTRUN -> [SKIP][118] ([fdo#109271] / [i915#2994]) +2 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl3/igt@sysfs_clients@sema-10.html
* igt@sysfs_clients@split-25:
- shard-tglb: NOTRUN -> [SKIP][119] ([i915#2994])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@sysfs_clients@split-25.html
* igt@sysfs_heartbeat_interval@mixed@vcs0:
- shard-skl: [PASS][120] -> [WARN][121] ([i915#4055])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-skl4/igt@sysfs_heartbeat_interval@mixed@vcs0.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl4/igt@sysfs_heartbeat_interval@mixed@vcs0.html
* igt@sysfs_heartbeat_interval@mixed@vecs0:
- shard-skl: [PASS][122] -> [FAIL][123] ([i915#1731])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-skl4/igt@sysfs_heartbeat_interval@mixed@vecs0.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl4/igt@sysfs_heartbeat_interval@mixed@vecs0.html
* igt@tools_test@sysfs_l3_parity:
- shard-tglb: NOTRUN -> [SKIP][124] ([fdo#109307])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@tools_test@sysfs_l3_parity.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][125] ([i915#658]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb5/igt@feature_discovery@psr2.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_caching@reads:
- shard-glk: [DMESG-WARN][127] ([i915#118]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-glk5/igt@gem_caching@reads.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-glk1/igt@gem_caching@reads.html
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-kbl: [DMESG-WARN][129] ([i915#180]) -> [PASS][130] +3 similar issues
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_eio@unwedge-stress:
- {shard-tglu}: [TIMEOUT][131] ([i915#3063] / [i915#3648]) -> [
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/index.html
[-- Attachment #2: Type: text/html, Size: 33700 bytes --]
^ permalink raw reply [flat|nested] 44+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev4)
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (25 preceding siblings ...)
2022-03-30 3:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2022-04-14 2:10 ` Patchwork
2022-04-14 2:10 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (4 subsequent siblings)
31 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2022-04-14 2:10 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations (rev4)
URL : https://patchwork.freedesktop.org/series/101789/
State : warning
== Summary ==
Error: dim checkpatch failed
380dc39b162a drm/i915: Make .get_dplls() return int
83841bcb2f20 drm/i915: Pass dev_priv to intel_shared_dpll_init()
f345e1d232bc drm/i915: Remove pointless dpll_funcs checks
3d66d884647b drm/i915: Adjust .crtc_compute_clock() calling convention
8af7100894c2 drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
57a731414cc5 drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()
4ed6a2773750 drm/i915: Clear the dpll_hw_state when disabling a pipe
b472e0b43e0f drm/i915: Split out dg2_crtc_compute_clock()
d127bc94034e drm/i915: Add crtc .crtc_get_shared_dpll()
71ccbd8a3e79 drm/i915: Split shared dpll .get_dplls() into compute and get phases
-:191: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_1350MHz>
#191: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1063:
+ SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;
total: 0 errors, 0 warnings, 1 checks, 516 lines checked
351839dec9ab drm/i915: Do .crtc_compute_clock() earlier
dbf225e1d964 drm/i915: Clean up DPLL related debugs
ff4fddbbc9c9 drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
^ permalink raw reply [flat|nested] 44+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Start reordering modeset clock calculations (rev4)
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (26 preceding siblings ...)
2022-04-14 2:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev4) Patchwork
@ 2022-04-14 2:10 ` Patchwork
2022-04-14 2:33 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (3 subsequent siblings)
31 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2022-04-14 2:10 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations (rev4)
URL : https://patchwork.freedesktop.org/series/101789/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 44+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Start reordering modeset clock calculations (rev4)
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (27 preceding siblings ...)
2022-04-14 2:10 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-04-14 2:33 ` Patchwork
2022-04-21 16:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev5) Patchwork
` (2 subsequent siblings)
31 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2022-04-14 2:33 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 18615 bytes --]
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations (rev4)
URL : https://patchwork.freedesktop.org/series/101789/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11497 -> Patchwork_101789v4
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_101789v4 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_101789v4, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/index.html
Participating hosts (39 -> 45)
------------------------------
Additional (9): bat-dg1-6 bat-dg1-5 bat-dg2-8 bat-dg2-9 bat-adlp-6 bat-adlp-4 bat-rpls-1 bat-rpls-2 bat-jsl-1
Missing (3): fi-bsw-cyan bat-jsl-2 fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_101789v4:
### IGT changes ###
#### Possible regressions ####
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-dg1-5: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-5/igt@gem_lmem_swapping@parallel-random-engines.html
- bat-dg1-6: NOTRUN -> [FAIL][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-6/igt@gem_lmem_swapping@parallel-random-engines.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_lmem_swapping@random-engines:
- {bat-dg2-8}: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg2-8/igt@gem_lmem_swapping@random-engines.html
* igt@i915_pm_rpm@module-reload:
- {bat-dg2-9}: NOTRUN -> [SKIP][4] +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg2-9/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@gem:
- {bat-dg2-9}: NOTRUN -> [FAIL][5] +35 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg2-9/igt@i915_selftest@live@gem.html
Known issues
------------
Here are the changes found in Patchwork_101789v4 that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- fi-ilk-650: [FAIL][6] -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11497/fi-ilk-650/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/fi-ilk-650/boot.html
### IGT changes ###
#### Issues hit ####
* igt@fbdev@write:
- bat-dg1-5: NOTRUN -> [SKIP][8] ([i915#2582]) +4 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-5/igt@fbdev@write.html
* igt@gem_huc_copy@huc-copy:
- fi-ilk-650: NOTRUN -> [SKIP][9] ([fdo#109271]) +21 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/fi-ilk-650/igt@gem_huc_copy@huc-copy.html
* igt@gem_mmap@basic:
- bat-dg1-6: NOTRUN -> [SKIP][10] ([i915#4083])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-6/igt@gem_mmap@basic.html
- bat-dg1-5: NOTRUN -> [SKIP][11] ([i915#4083])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-5/igt@gem_mmap@basic.html
* igt@gem_tiled_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][12] ([i915#4077]) +2 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-6/igt@gem_tiled_blits@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg1-5: NOTRUN -> [SKIP][13] ([i915#4077]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-5/igt@gem_tiled_fence_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg1-5: NOTRUN -> [SKIP][14] ([i915#4079]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-5/igt@gem_tiled_pread_basic.html
- bat-dg1-6: NOTRUN -> [SKIP][15] ([i915#4079]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-6/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-dg1-5: NOTRUN -> [SKIP][16] ([i915#1155])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-5/igt@i915_pm_backlight@basic-brightness.html
- bat-dg1-6: NOTRUN -> [SKIP][17] ([i915#1155])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-6/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [PASS][18] -> [INCOMPLETE][19] ([i915#4785])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11497/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510: [PASS][20] -> [DMESG-FAIL][21] ([i915#2927] / [i915#4528])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11497/fi-pnv-d510/igt@i915_selftest@live@requests.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/fi-pnv-d510/igt@i915_selftest@live@requests.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-dg1-6: NOTRUN -> [SKIP][22] ([i915#4212]) +7 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-5: NOTRUN -> [SKIP][23] ([i915#4215])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-5/igt@kms_addfb_basic@basic-y-tiled-legacy.html
- bat-dg1-6: NOTRUN -> [SKIP][24] ([i915#4215])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-6/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg1-5: NOTRUN -> [SKIP][25] ([i915#4212]) +7 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-5/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_busy@basic:
- bat-dg1-5: NOTRUN -> [SKIP][26] ([i915#4303])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-5/igt@kms_busy@basic.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-ilk-650: NOTRUN -> [SKIP][27] ([fdo#109271] / [fdo#111827]) +8 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/fi-ilk-650/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_chamelium@hdmi-edid-read:
- bat-dg1-6: NOTRUN -> [SKIP][28] ([fdo#111827]) +8 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-6/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- bat-dg1-5: NOTRUN -> [SKIP][29] ([fdo#111827]) +8 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-5/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-dg1-6: NOTRUN -> [SKIP][30] ([i915#4103] / [i915#4213]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg1-5: NOTRUN -> [SKIP][31] ([i915#4103] / [i915#4213]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_flip@basic-flip-vs-dpms:
- bat-dg1-5: NOTRUN -> [SKIP][32] ([i915#4078]) +23 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-5/igt@kms_flip@basic-flip-vs-dpms.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg1-6: NOTRUN -> [SKIP][33] ([fdo#109285])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-6/igt@kms_force_connector_basic@force-load-detect.html
- bat-dg1-5: NOTRUN -> [SKIP][34] ([fdo#109285])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-5/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- bat-dg1-5: NOTRUN -> [SKIP][35] ([i915#4078] / [i915#5341])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-5/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
- fi-ilk-650: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#5341])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/fi-ilk-650/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
* igt@kms_psr@primary_page_flip:
- bat-dg1-5: NOTRUN -> [SKIP][37] ([i915#1072] / [i915#4078]) +3 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-5/igt@kms_psr@primary_page_flip.html
* igt@kms_psr@sprite_plane_onoff:
- bat-dg1-6: NOTRUN -> [SKIP][38] ([i915#1072] / [i915#4078]) +3 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-6/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg1-6: NOTRUN -> [SKIP][39] ([i915#3555])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-6/igt@kms_setmode@basic-clone-single-crtc.html
- bat-dg1-5: NOTRUN -> [SKIP][40] ([i915#3555])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-5/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-mmap:
- bat-dg1-5: NOTRUN -> [SKIP][41] ([i915#3708] / [i915#4077]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-5/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-gtt:
- bat-dg1-6: NOTRUN -> [SKIP][42] ([i915#3708] / [i915#4077]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-6/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-userptr:
- bat-dg1-6: NOTRUN -> [SKIP][43] ([i915#3708] / [i915#4873])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-6/igt@prime_vgem@basic-userptr.html
- bat-dg1-5: NOTRUN -> [SKIP][44] ([i915#3708] / [i915#4873])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-5/igt@prime_vgem@basic-userptr.html
* igt@prime_vgem@basic-write:
- bat-dg1-5: NOTRUN -> [SKIP][45] ([i915#3708]) +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-5/igt@prime_vgem@basic-write.html
- bat-dg1-6: NOTRUN -> [SKIP][46] ([i915#3708]) +3 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-6/igt@prime_vgem@basic-write.html
* igt@runner@aborted:
- fi-pnv-d510: NOTRUN -> [FAIL][47] ([fdo#109271] / [i915#2403] / [i915#4312])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/fi-pnv-d510/igt@runner@aborted.html
- bat-dg1-5: NOTRUN -> [FAIL][48] ([i915#4312])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-5/igt@runner@aborted.html
- fi-hsw-4770: NOTRUN -> [FAIL][49] ([fdo#109271] / [i915#2722] / [i915#4312] / [i915#5594])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/fi-hsw-4770/igt@runner@aborted.html
- bat-adlp-4: NOTRUN -> [FAIL][50] ([i915#5457])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-adlp-4/igt@runner@aborted.html
- bat-dg1-6: NOTRUN -> [FAIL][51] ([i915#4312])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/bat-dg1-6/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_heartbeat:
- fi-skl-guc: [DMESG-FAIL][52] -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11497/fi-skl-guc/igt@i915_selftest@live@gt_heartbeat.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/fi-skl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [INCOMPLETE][54] ([i915#3921]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11497/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_busy@basic@flip:
- fi-tgl-u2: [DMESG-WARN][56] ([i915#402]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11497/fi-tgl-u2/igt@kms_busy@basic@flip.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/fi-tgl-u2/igt@kms_busy@basic@flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#3003]: https://gitlab.freedesktop.org/drm/intel/issues/3003
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4303]: https://gitlab.freedesktop.org/drm/intel/issues/4303
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#5171]: https://gitlab.freedesktop.org/drm/intel/issues/5171
[i915#5174]: https://gitlab.freedesktop.org/drm/intel/issues/5174
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5193]: https://gitlab.freedesktop.org/drm/intel/issues/5193
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5275]: https://gitlab.freedesktop.org/drm/intel/issues/5275
[i915#5329]: https://gitlab.freedesktop.org/drm/intel/issues/5329
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5457]: https://gitlab.freedesktop.org/drm/intel/issues/5457
[i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
[i915#5606]: https://gitlab.freedesktop.org/drm/intel/issues/5606
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#5634]: https://gitlab.freedesktop.org/drm/intel/issues/5634
Build changes
-------------
* Linux: CI_DRM_11497 -> Patchwork_101789v4
CI-20190529: 20190529
CI_DRM_11497: d883cffbf2383a96420fd6dc099056295de24a12 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6420: a3885810ccc0ce9e6552a20c910a0a322eca466c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_101789v4: d883cffbf2383a96420fd6dc099056295de24a12 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8bcbf1a105f0 drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
657d62592078 drm/i915: Clean up DPLL related debugs
6620e6ec0c7f drm/i915: Do .crtc_compute_clock() earlier
15abcdf728b5 drm/i915: Split shared dpll .get_dplls() into compute and get phases
e040f7af5409 drm/i915: Add crtc .crtc_get_shared_dpll()
7bc23b9fd1e3 drm/i915: Split out dg2_crtc_compute_clock()
dc2a3124a12b drm/i915: Clear the dpll_hw_state when disabling a pipe
1a3d3d447b9f drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()
0c9c9bad8151 drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
1dfb11c67732 drm/i915: Adjust .crtc_compute_clock() calling convention
835043046151 drm/i915: Remove pointless dpll_funcs checks
bb8310aa0f7c drm/i915: Pass dev_priv to intel_shared_dpll_init()
6f8661ef40a9 drm/i915: Make .get_dplls() return int
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/index.html
[-- Attachment #2: Type: text/html, Size: 20846 bytes --]
^ permalink raw reply [flat|nested] 44+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev5)
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (28 preceding siblings ...)
2022-04-14 2:33 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2022-04-21 16:59 ` Patchwork
2022-04-21 17:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-04-21 21:51 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
31 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2022-04-21 16:59 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations (rev5)
URL : https://patchwork.freedesktop.org/series/101789/
State : warning
== Summary ==
Error: dim checkpatch failed
32e8671c097f drm/i915: Make .get_dplls() return int
d501feb0cac1 drm/i915: Pass dev_priv to intel_shared_dpll_init()
695e9aa8b693 drm/i915: Remove pointless dpll_funcs checks
bfaac2c12523 drm/i915: Adjust .crtc_compute_clock() calling convention
88dbf174e03e drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
51418ba48534 drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()
a25f16fe3e1c drm/i915: Clear the dpll_hw_state when disabling a pipe
d644f564dffe drm/i915: Split out dg2_crtc_compute_clock()
18d0698dce4c drm/i915: Add crtc .crtc_get_shared_dpll()
1545f8bc7636 drm/i915: Split shared dpll .get_dplls() into compute and get phases
-:191: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_1350MHz>
#191: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1063:
+ SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;
total: 0 errors, 0 warnings, 1 checks, 516 lines checked
7cd29893d822 drm/i915: Do .crtc_compute_clock() earlier
8d6be41a83c2 drm/i915: Clean up DPLL related debugs
2bfb6a621728 drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
^ permalink raw reply [flat|nested] 44+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Start reordering modeset clock calculations (rev5)
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (29 preceding siblings ...)
2022-04-21 16:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev5) Patchwork
@ 2022-04-21 17:28 ` Patchwork
2022-04-21 21:51 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
31 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2022-04-21 17:28 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 10639 bytes --]
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations (rev5)
URL : https://patchwork.freedesktop.org/series/101789/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11536 -> Patchwork_101789v5
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/index.html
Participating hosts (45 -> 45)
------------------------------
Additional (2): fi-cml-u2 bat-dg2-8
Missing (2): fi-hsw-4770 fi-bsw-cyan
Known issues
------------
Here are the changes found in Patchwork_101789v5 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2: NOTRUN -> [SKIP][1] ([i915#1208]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/fi-cml-u2/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-cml-u2: NOTRUN -> [SKIP][2] ([i915#2190])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/fi-cml-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-cml-u2: NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/fi-cml-u2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_selftest@live@hangcheck:
- fi-bdw-5557u: NOTRUN -> [INCOMPLETE][4] ([i915#3921])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/fi-bdw-5557u/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-cml-u2: NOTRUN -> [SKIP][6] ([fdo#109284] / [fdo#111827]) +8 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/fi-cml-u2/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-cml-u2: NOTRUN -> [SKIP][7] ([fdo#109278]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/fi-cml-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- bat-adlp-4: [PASS][8] -> [DMESG-WARN][9] ([i915#3576])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2: NOTRUN -> [SKIP][10] ([fdo#109285])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/fi-cml-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cml-u2: NOTRUN -> [SKIP][11] ([fdo#109278] / [i915#533])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/fi-cml-u2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-bdw-5557u: NOTRUN -> [SKIP][12] ([fdo#109271]) +14 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/fi-bdw-5557u/igt@kms_setmode@basic-clone-single-crtc.html
- fi-cml-u2: NOTRUN -> [SKIP][13] ([i915#3555])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/fi-cml-u2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- fi-cml-u2: NOTRUN -> [SKIP][14] ([i915#3301])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/fi-cml-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- bat-adlp-4: NOTRUN -> [FAIL][15] ([i915#4312])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/bat-adlp-4/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- bat-adlp-4: [DMESG-WARN][16] ([i915#3576]) -> [PASS][17] +2 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/bat-adlp-4/igt@i915_pm_rpm@module-reload.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/bat-adlp-4/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@gem:
- fi-blb-e6850: [DMESG-FAIL][18] -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/fi-blb-e6850/igt@i915_selftest@live@gem.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/fi-blb-e6850/igt@i915_selftest@live@gem.html
* igt@i915_selftest@live@gt_lrc:
- fi-bsw-n3050: [DMESG-FAIL][20] -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
* igt@kms_busy@basic@modeset:
- {bat-adlp-6}: [DMESG-WARN][22] ([i915#3576]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/bat-adlp-6/igt@kms_busy@basic@modeset.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/bat-adlp-6/igt@kms_busy@basic@modeset.html
#### Warnings ####
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][24] ([i915#4494] / [i915#4957]) -> [INCOMPLETE][25] ([i915#5757])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1208]: https://gitlab.freedesktop.org/drm/intel/issues/1208
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5270]: https://gitlab.freedesktop.org/drm/intel/issues/5270
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5275]: https://gitlab.freedesktop.org/drm/intel/issues/5275
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5356]: https://gitlab.freedesktop.org/drm/intel/issues/5356
[i915#5757]: https://gitlab.freedesktop.org/drm/intel/issues/5757
[i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
Build changes
-------------
* Linux: CI_DRM_11536 -> Patchwork_101789v5
CI-20190529: 20190529
CI_DRM_11536: c4d0bd916d243bad13ce7d4c3a7a00a50e13b73d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6444: df584c804e3a44431b0e5ae21c190b6e9acb35ab @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_101789v5: c4d0bd916d243bad13ce7d4c3a7a00a50e13b73d @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
0f670a39fa21 drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
a886e4ec3c73 drm/i915: Clean up DPLL related debugs
1eb7712774b4 drm/i915: Do .crtc_compute_clock() earlier
1857e0fd77d8 drm/i915: Split shared dpll .get_dplls() into compute and get phases
b84885d61b59 drm/i915: Add crtc .crtc_get_shared_dpll()
b218554272e7 drm/i915: Split out dg2_crtc_compute_clock()
e63de3d4a8d5 drm/i915: Clear the dpll_hw_state when disabling a pipe
d09c0685dd19 drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()
4037d50836e8 drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
1c5adb67ff46 drm/i915: Adjust .crtc_compute_clock() calling convention
1f49c2d7f8bb drm/i915: Remove pointless dpll_funcs checks
262e89722be2 drm/i915: Pass dev_priv to intel_shared_dpll_init()
a5bfbf68789c drm/i915: Make .get_dplls() return int
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/index.html
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^ permalink raw reply [flat|nested] 44+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Start reordering modeset clock calculations (rev5)
2022-03-25 12:31 [Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations Ville Syrjala
` (30 preceding siblings ...)
2022-04-21 17:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-04-21 21:51 ` Patchwork
31 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2022-04-21 21:51 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 47309 bytes --]
== Series Details ==
Series: drm/i915: Start reordering modeset clock calculations (rev5)
URL : https://patchwork.freedesktop.org/series/101789/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11536_full -> Patchwork_101789v5_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_101789v5_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_101789v5_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 13)
------------------------------
Additional (3): shard-rkl shard-dg1 shard-tglu
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_101789v5_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@hangcheck:
- shard-tglb: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-tglb6/igt@i915_selftest@live@hangcheck.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb1/igt@i915_selftest@live@hangcheck.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_eio@unwedge-stress:
- {shard-dg1}: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-dg1-12/igt@gem_eio@unwedge-stress.html
* {igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0}:
- {shard-dg1}: NOTRUN -> [SKIP][4] +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-dg1-15/igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0.html
Known issues
------------
Here are the changes found in Patchwork_101789v5_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-skl: NOTRUN -> [DMESG-WARN][5] ([i915#4991])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-skl1/igt@gem_create@create-massive.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-kbl: NOTRUN -> [DMESG-WARN][6] ([i915#5076] / [i915#5614])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl4/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-tglb6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [PASS][9] -> [FAIL][10] ([i915#2842]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_flush@basic-batch-kernel-default-wb:
- shard-snb: [PASS][11] -> [SKIP][12] ([fdo#109271]) +5 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-snb5/igt@gem_exec_flush@basic-batch-kernel-default-wb.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-snb6/igt@gem_exec_flush@basic-batch-kernel-default-wb.html
* igt@gem_exec_params@no-vebox:
- shard-iclb: NOTRUN -> [SKIP][13] ([fdo#109283])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb4/igt@gem_exec_params@no-vebox.html
- shard-tglb: NOTRUN -> [SKIP][14] ([fdo#109283] / [i915#4877])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb1/igt@gem_exec_params@no-vebox.html
* igt@gem_exec_suspend@basic-s3@smem:
- shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-kbl1/igt@gem_exec_suspend@basic-s3@smem.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-tglb: NOTRUN -> [SKIP][17] ([i915#4613])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb2/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@smem-oom:
- shard-kbl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl4/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-tglb: NOTRUN -> [SKIP][19] ([i915#4270]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb2/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
* igt@gem_render_copy@x-tiled-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#768])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb4/igt@gem_render_copy@x-tiled-to-vebox-y-tiled.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-tglb: NOTRUN -> [SKIP][21] ([i915#3323])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb2/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@input-checking:
- shard-tglb: NOTRUN -> [DMESG-WARN][22] ([i915#4991])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb2/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@vma-merge:
- shard-snb: NOTRUN -> [FAIL][23] ([i915#2724])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-snb2/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@allowed-single:
- shard-kbl: [PASS][24] -> [DMESG-WARN][25] ([i915#5566] / [i915#716])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-kbl7/igt@gen9_exec_parse@allowed-single.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl1/igt@gen9_exec_parse@allowed-single.html
* igt@kms_atomic_transition@plane-use-after-nonblocking-unbind@edp-1-pipe-a:
- shard-skl: [PASS][26] -> [DMESG-WARN][27] ([i915#1982])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-skl10/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind@edp-1-pipe-a.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-skl1/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind@edp-1-pipe-a.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-0:
- shard-tglb: NOTRUN -> [SKIP][28] ([i915#5286])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb2/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180:
- shard-iclb: NOTRUN -> [SKIP][29] ([i915#5286])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_big_fb@linear-32bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][30] ([fdo#111614])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb2/igt@kms_big_fb@linear-32bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- shard-glk: [PASS][31] -> [DMESG-WARN][32] ([i915#118])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-glk5/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-glk9/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-tglb: NOTRUN -> [SKIP][33] ([fdo#111615])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-iclb: NOTRUN -> [SKIP][34] ([fdo#110723])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb6/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3886])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-apl1/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][36] ([fdo#111615] / [i915#3689]) +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb2/igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3886])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-skl4/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][38] ([i915#3689] / [i915#3886])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb2/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109278] / [i915#3886]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb6/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-audio:
- shard-apl: NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +2 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-apl2/igt@kms_chamelium@dp-audio.html
* igt@kms_chamelium@hdmi-crc-multiple:
- shard-skl: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +2 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-skl1/igt@kms_chamelium@hdmi-crc-multiple.html
* igt@kms_chamelium@hdmi-hpd-for-each-pipe:
- shard-snb: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-snb2/igt@kms_chamelium@hdmi-hpd-for-each-pipe.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-tglb: NOTRUN -> [SKIP][43] ([fdo#109284] / [fdo#111827]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb1/igt@kms_chamelium@hdmi-hpd-storm.html
- shard-iclb: NOTRUN -> [SKIP][44] ([fdo#109284] / [fdo#111827])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb4/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_color@pipe-c-deep-color:
- shard-tglb: NOTRUN -> [SKIP][45] ([i915#3555])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb2/igt@kms_color@pipe-c-deep-color.html
* igt@kms_color_chamelium@pipe-d-ctm-green-to-red:
- shard-kbl: NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl4/igt@kms_color_chamelium@pipe-d-ctm-green-to-red.html
* igt@kms_content_protection@srm:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109300] / [fdo#111066])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb6/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@pipe-b-cursor-512x170-onscreen:
- shard-tglb: NOTRUN -> [SKIP][48] ([fdo#109279] / [i915#3359])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb2/igt@kms_cursor_crc@pipe-b-cursor-512x170-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-512x512-random:
- shard-iclb: NOTRUN -> [SKIP][49] ([fdo#109278] / [fdo#109279])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb6/igt@kms_cursor_crc@pipe-b-cursor-512x512-random.html
* igt@kms_cursor_crc@pipe-c-cursor-max-size-random:
- shard-tglb: NOTRUN -> [SKIP][50] ([i915#3359])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb1/igt@kms_cursor_crc@pipe-c-cursor-max-size-random.html
* igt@kms_cursor_crc@pipe-d-cursor-64x21-random:
- shard-skl: NOTRUN -> [SKIP][51] ([fdo#109271]) +24 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-skl1/igt@kms_cursor_crc@pipe-d-cursor-64x21-random.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
- shard-iclb: NOTRUN -> [SKIP][52] ([fdo#109274] / [fdo#109278])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb4/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-tglb: NOTRUN -> [SKIP][53] ([fdo#109274] / [fdo#111825] / [i915#3966])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb2/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-busy-flip:
- shard-tglb: NOTRUN -> [SKIP][54] ([fdo#109274] / [fdo#111825]) +3 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb2/igt@kms_flip@2x-busy-flip.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
- shard-kbl: NOTRUN -> [SKIP][55] ([fdo#109271]) +9 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl4/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
- shard-iclb: [PASS][56] -> [SKIP][57] ([i915#3701])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-iclb8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
* igt@kms_force_connector_basic@prune-stale-modes:
- shard-apl: NOTRUN -> [SKIP][58] ([fdo#109271]) +33 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-apl2/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@fbc-2p-rte:
- shard-iclb: NOTRUN -> [SKIP][59] ([fdo#109280]) +3 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-2p-rte.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-tglb: NOTRUN -> [SKIP][60] ([fdo#109280] / [fdo#111825]) +4 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes:
- shard-tglb: NOTRUN -> [SKIP][61] ([fdo#109289]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb2/igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-apl: [PASS][62] -> [DMESG-WARN][63] ([i915#180])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][64] ([fdo#108145] / [i915#265])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-apl2/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale:
- shard-iclb: [PASS][65] -> [SKIP][66] ([i915#5235]) +2 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-iclb8/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
* igt@kms_psr2_su@page_flip-p010:
- shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#658])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-apl2/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-tglb: NOTRUN -> [SKIP][68] ([i915#1911])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb2/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][69] -> [SKIP][70] ([fdo#109441])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb7/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_psr@suspend:
- shard-snb: NOTRUN -> [SKIP][71] ([fdo#109271]) +24 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-snb2/igt@kms_psr@suspend.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
- shard-tglb: NOTRUN -> [SKIP][72] ([i915#5289])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb2/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
* igt@kms_universal_plane@universal-plane-pipe-d-sanity:
- shard-iclb: NOTRUN -> [SKIP][73] ([fdo#109278]) +4 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb4/igt@kms_universal_plane@universal-plane-pipe-d-sanity.html
* igt@kms_vblank@pipe-c-accuracy-idle:
- shard-glk: [PASS][74] -> [FAIL][75] ([i915#43])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-glk1/igt@kms_vblank@pipe-c-accuracy-idle.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-glk6/igt@kms_vblank@pipe-c-accuracy-idle.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-apl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#2437])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-apl2/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-d-source-outp-inactive:
- shard-iclb: NOTRUN -> [SKIP][77] ([fdo#109278] / [i915#2530])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb4/igt@nouveau_crc@pipe-d-source-outp-inactive.html
- shard-tglb: NOTRUN -> [SKIP][78] ([i915#2530])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb1/igt@nouveau_crc@pipe-d-source-outp-inactive.html
* igt@perf@polling-parameterized:
- shard-skl: [PASS][79] -> [FAIL][80] ([i915#5639])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-skl1/igt@perf@polling-parameterized.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-skl4/igt@perf@polling-parameterized.html
* igt@prime_nv_api@i915_nv_double_import:
- shard-tglb: NOTRUN -> [SKIP][81] ([fdo#109291]) +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb1/igt@prime_nv_api@i915_nv_double_import.html
* igt@prime_nv_pcopy@test3_1:
- shard-iclb: NOTRUN -> [SKIP][82] ([fdo#109291]) +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb6/igt@prime_nv_pcopy@test3_1.html
* igt@syncobj_timeline@invalid-transfer-non-existent-point:
- shard-apl: NOTRUN -> [DMESG-WARN][83] ([i915#5098])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-apl1/igt@syncobj_timeline@invalid-transfer-non-existent-point.html
#### Possible fixes ####
* {igt@drm_buddy@all@buddy_alloc_smoke}:
- shard-apl: [INCOMPLETE][84] -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-apl6/igt@drm_buddy@all@buddy_alloc_smoke.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-apl3/igt@drm_buddy@all@buddy_alloc_smoke.html
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-skl: [INCOMPLETE][86] ([i915#4793]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-skl6/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-skl4/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_eio@in-flight-10ms:
- shard-tglb: [TIMEOUT][88] ([i915#3063]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-tglb8/igt@gem_eio@in-flight-10ms.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb2/igt@gem_eio@in-flight-10ms.html
* igt@gem_eio@kms:
- shard-tglb: [FAIL][90] ([i915#232]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-tglb1/igt@gem_eio@kms.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb6/igt@gem_eio@kms.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl: [FAIL][92] ([i915#2842]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-kbl7/igt@gem_exec_fair@basic-none@rcs0.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl1/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [FAIL][94] ([i915#2842]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-apl2/igt@gem_exec_fair@basic-none@vcs0.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-apl4/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][96] ([i915#2842]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_mmap_wc@coherency:
- shard-snb: [SKIP][98] ([fdo#109271]) -> [PASS][99] +2 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-snb6/igt@gem_mmap_wc@coherency.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-snb5/igt@gem_mmap_wc@coherency.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [DMESG-WARN][100] ([i915#5566] / [i915#716]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-apl2/igt@gen9_exec_parse@allowed-single.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-apl1/igt@gen9_exec_parse@allowed-single.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][102] ([i915#3921]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-snb4/igt@i915_selftest@live@hangcheck.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-snb2/igt@i915_selftest@live@hangcheck.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-iclb: [FAIL][104] ([i915#5072]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-iclb7/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb7/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_flip@basic-flip-vs-dpms@c-edp1:
- shard-tglb: [INCOMPLETE][106] -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-tglb8/igt@kms_flip@basic-flip-vs-dpms@c-edp1.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb2/igt@kms_flip@basic-flip-vs-dpms@c-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-apl: [DMESG-WARN][108] ([i915#180]) -> [PASS][109] +2 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
* igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-b-edp-1-downscale-with-pixel-format:
- shard-iclb: [INCOMPLETE][110] ([i915#5293]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-iclb2/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-b-edp-1-downscale-with-pixel-format.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb7/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-b-edp-1-downscale-with-pixel-format.html
* igt@kms_plane_scaling@scaler-with-pixel-format-unity-scaling@pipe-a-hdmi-a-1-scaler-with-pixel-format:
- shard-glk: [DMESG-WARN][112] ([i915#118]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-glk2/igt@kms_plane_scaling@scaler-with-pixel-format-unity-scaling@pipe-a-hdmi-a-1-scaler-with-pixel-format.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-glk7/igt@kms_plane_scaling@scaler-with-pixel-format-unity-scaling@pipe-a-hdmi-a-1-scaler-with-pixel-format.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][114] ([fdo#109441]) -> [PASS][115] +1 similar issue
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-iclb8/igt@kms_psr@psr2_cursor_blt.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
* igt@perf@polling-parameterized:
- shard-glk: [FAIL][116] ([i915#5639]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-glk1/igt@perf@polling-parameterized.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-glk6/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][118] ([i915#3063] / [i915#3648]) -> [FAIL][119] ([i915#232])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-tglb7/igt@gem_eio@unwedge-stress.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-tglb8/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [DMESG-WARN][120] ([i915#5614]) -> [SKIP][121] ([i915#4525])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-iclb4/igt@gem_exec_balancer@parallel-keep-in-fence.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb6/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][122] ([i915#4525]) -> [DMESG-FAIL][123] ([i915#5614])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-iclb8/igt@gem_exec_balancer@parallel-ordering.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-skl: [SKIP][124] ([fdo#109271]) -> [SKIP][125] ([fdo#109271] / [i915#1888])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-skl8/igt@kms_flip@2x-flip-vs-suspend.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-skl4/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc:
- shard-glk: [SKIP][126] ([fdo#109271] / [i915#1888]) -> [SKIP][127] ([fdo#109271])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-glk3/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-glk4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][128] ([fdo#111068] / [i915#658]) -> [SKIP][129] ([i915#2920]) +1 similar issue
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-iclb8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@runner@aborted:
- shard-apl: ([FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140]) ([i915#3002] / [i915#4312] / [i915#5257])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-apl2/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-apl6/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-apl6/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-apl4/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-apl3/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-apl7/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-apl2/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-apl8/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-apl6/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-apl7/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-apl1/igt@runner@aborted.html
- shard-kbl: ([FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149], [FAIL][150]) ([i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][151], [FAIL][152], [FAIL][153], [FAIL][154], [FAIL][155], [FAIL][156], [FAIL][157], [FAIL][158], [FAIL][159], [FAIL][160], [FAIL][161], [FAIL][162], [FAIL][163]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#716])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-kbl6/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-kbl4/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-kbl6/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-kbl7/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-kbl1/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-kbl4/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-kbl7/igt@runner@aborted.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-kbl4/igt@runner@aborted.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-kbl3/igt@runner@aborted.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11536/shard-kbl4/igt@runner@aborted.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl4/igt@runner@aborted.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl6/igt@runner@aborted.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl7/igt@runner@aborted.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl4/igt@runner@aborted.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl7/igt@runner@aborted.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl3/igt@runner@aborted.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl6/igt@runner@aborted.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl1/igt@runner@aborted.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl7/igt@runner@aborted.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl6/igt@runner@aborted.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl1/igt@runner@aborted.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl1/igt@runner@aborted.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/shard-kbl1/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110254]: https://bugs.freedesktop.org/show_bug.cgi?id=110254
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#232]: https://gitlab.freedesktop.org/drm/intel/issues/232
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3464]: https://gitlab.freedesktop.org/drm/intel/issues/3464
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3648]: https://gitlab.freedesktop.org/drm/intel/issues/3648
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#4032]: https://gitlab.freedesktop.org/drm/intel/issues/4032
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4793]: https://gitlab.freedesktop.org/drm/intel/issues/4793
[i915#4807]: https://gitlab.freedesktop.org/drm/intel/issues/4807
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884
[i915#4886]: https://gitlab.freedesktop.org/drm/intel/issues/4886
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4904]: https://gitlab.freedesktop.org/drm/intel/issues/4904
[i915#4941]: https://gitlab.freedesktop.org/drm/intel/issues/4941
[i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5072]: https://gitlab.freedesktop.org/drm/intel/issues/5072
[i915#5076]: https://gitlab.freedesktop.org/drm/intel/issues/5076
[i915#5080]: https://gitlab.freedesktop.org/drm/intel/issues/5080
[i915#5098]: https://gitlab.freedesktop.org/drm/intel/issues/5098
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5293]: https://gitlab.freedesktop.org/drm/intel/issues/5293
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5614]: https://gitlab.freedesktop.org/drm/intel/issues/5614
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#5691]: https://gitlab.freedesktop.org/drm/intel/issues/5691
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
Build changes
-------------
* Linux: CI_DRM_11536 -> Patchwork_101789v5
CI-20190529: 20190529
CI_DRM_11536: c4d0bd916d243bad13ce7d4c3a7a00a50e13b73d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6444: df584c804e3a44431b0e5ae21c190b6e9acb35ab @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_101789v5: c4d0bd916d243bad13ce7d4c3a7a00a50e13b73d @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/index.html
[-- Attachment #2: Type: text/html, Size: 47194 bytes --]
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