[U-Boot] [PATCH v2 00/19] Add FPGA, SDRAM, SPL loads U-boot & booting to console

[U-Boot] [PATCH v2 00/19] Add FPGA, SDRAM, SPL loads U-boot & booting to console

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

This patchset adding FPGA and SDRAM drivers, enable fpga loadfs to program FPGA
, SPL loading U-boot and booting to U-boot console. This version mainly resolved
comments from Marek in [v1].
This series is working on top of u-boot.git - http://git.denx.de/u-boot.git .

[v1]: https://www.mail-archive.com/u-boot at lists.denx.de/msg261831.html

Tien Fong Chee (19):
  ARM: socfpga: add bindings doc for arria10 fpga manager
  doc: dtbinding: Description on FPGA RBF properties at Arria 10 FPGA
    manager
  dts: Add FPGA bitstream properties to Arria 10 DTS
  arm: socfpga: Add Arria 10 SoCFPGA programming interface
  arm: socfpga: Enhance FPGA program write rbf data with size >= 4 bytes
  dts: Enable fpga-mgr node build for Arria 10 SPL
  fdt: Add compatible strings for Arria 10
  fs: Enable generic filesystems interface support in SPL.
  arm: socfpga: Add drivers for programing FPGA from flash
  arm: socfpga: Rename the gen5 sdram driver to more specific name
  arm: socfpga: Add DRAM bank size initialization function
  arm: socfpga: Add DDR driver for Arria 10
  configs: Add DDR Kconfig support for Arria 10
  arm: socfpga: Enable build for DDR Arria 10
  arm: socfpga: Add support to memory allocation in SPL
  arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10
  arm: socfpga: Adding clock frequency info for U-boot
  arm: socfpga: Adding SoCFPGA info for both SPL and U-boot
  arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot

 arch/arm/dts/socfpga_arria10.dtsi                  |   4 +
 arch/arm/mach-socfpga/Kconfig                      |   1 +
 arch/arm/mach-socfpga/board.c                      |  16 +
 arch/arm/mach-socfpga/include/mach/boot0.h         |  11 +-
 .../include/mach/fpga_manager_arria10.h            |  27 +
 arch/arm/mach-socfpga/include/mach/sdram.h         | 436 +-----------
 arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-
 .../include/mach/{sdram.h => sdram_gen5.h}         |   6 +-
 arch/arm/mach-socfpga/misc_arria10.c               |   5 -
 arch/arm/mach-socfpga/spl.c                        |  61 ++
 cmd/fpga.c                                         |   2 +-
 common/spl/Kconfig                                 |   8 +
 common/spl/spl_mmc.c                               |   2 +-
 configs/socfpga_arria10_defconfig                  |  57 +-
 doc/README.SPL                                     |   1 +
 .../fpga/altera-socfpga-a10-fpga-mgr.txt           |  30 +
 drivers/ddr/altera/Kconfig                         |   2 +-
 drivers/ddr/altera/Makefile                        |   3 +-
 drivers/ddr/altera/sdram_arria10.c                 | 735 +++++++++++++++++++++
 drivers/ddr/altera/{sdram.c => sdram_gen5.c}       |   0
 drivers/fpga/altera.c                              |  39 +-
 drivers/fpga/fpga.c                                |   8 +
 drivers/fpga/socfpga.c                             |  14 +-
 drivers/fpga/socfpga_arria10.c                     | 391 ++++++++++-
 fs/Makefile                                        |   1 +
 include/altera.h                                   |   6 +
 include/configs/socfpga_common.h                   |  28 +-
 include/fdtdec.h                                   |   2 +
 include/fpga.h                                     |   2 +
 include/spl.h                                      |   2 +
 lib/fdtdec.c                                       |   2 +
 31 files changed, 1535 insertions(+), 470 deletions(-)
 copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h} (99%)
 create mode 100644 doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
 create mode 100644 drivers/ddr/altera/sdram_arria10.c
 rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)

-- 
2.2.0

[U-Boot] [PATCH v2 01/19] ARM: socfpga: add bindings doc for arria10 fpga manager

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

This DT binding doc is porting from Linux DT binding doc.
commit 1adcbea4201a6852362aa5ece573f1f169b28113

Add a device tree bindings document for the SoCFPGA Arria10
FPGA Manager driver.

Signed-off-by: Alan Tull <atull@opensource.altera.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-By: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 .../fpga/altera-socfpga-a10-fpga-mgr.txt              | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt

diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
new file mode 100644
index 0000000..2fd8e7a
--- /dev/null
+++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
@@ -0,0 +1,19 @@
+Altera SOCFPGA Arria10 FPGA Manager
+
+Required properties:
+- compatible : should contain "altr,socfpga-a10-fpga-mgr"
+- reg        : base address and size for memory mapped io.
+               - The first index is for FPGA manager register access.
+               - The second index is for writing FPGA configuration data.
+- resets     : Phandle and reset specifier for the device's reset.
+- clocks     : Clocks used by the device.
+
+Example:
+
+	fpga_mgr: fpga-mgr at ffd03000 {
+		compatible = "altr,socfpga-a10-fpga-mgr";
+		reg = <0xffd03000 0x100
+		       0xffcfe400 0x20>;
+		clocks = <&l4_mp_clk>;
+		resets = <&rst FPGAMGR_RESET>;
+	};
-- 
2.2.0

[U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA RBF properties at Arria 10 FPGA manager

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

This patch adds description on properties about location of FPGA RBFs are
stored, type and functionality of RBF used to configure FPGA.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
index 2fd8e7a..7abb746 100644
--- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
+++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
@@ -7,6 +7,14 @@ Required properties:
                - The second index is for writing FPGA configuration data.
 - resets     : Phandle and reset specifier for the device's reset.
 - clocks     : Clocks used by the device.
+- bitstream_periph : FPGA peripheral raw binary file which is used to
+                     initialize FPGA IOs, PLL, IO48 and DDR.
+- bitstream_core : FPGA core raw binary file contains FPGA design which is used
+                   to program FPGA CRAM and ERAM.
+- bitstream_devpart : Partition of flash device where bitstream files are
+		       stored.
+                      <dev[:part]> - dev is flash device number, part is flash
+                                     device partition.
 
 Example:
 
@@ -16,4 +24,7 @@ Example:
 		       0xffcfe400 0x20>;
 		clocks = <&l4_mp_clk>;
 		resets = <&rst FPGAMGR_RESET>;
+		bitstream_periph = "ghrd_10as066n2.periph.rbf.mkimage";
+		bitstream_core = "ghrd_10as066n2.core.rbf.mkimage";
+		bitstream_devpart = "0:1";
 	};
-- 
2.2.0

[U-Boot] [PATCH v2 03/19] dts: Add FPGA bitstream properties to Arria 10 DTS

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

These FPGA bitstream properties would help bootloader to understand
how to configure FPGA and where to look the FPGA RBF files during
booting.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/dts/socfpga_arria10.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index 377700d..d4368ce 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -538,6 +538,9 @@
 			clocks = <&l4_mp_clk>;
 			resets = <&rst FPGAMGR_RESET>;
 			reset-names = "fpgamgr";
+			bitstream_periph = "ghrd_10as066n2.periph.rbf.mkimage";
+			bitstream_core = "ghrd_10as066n2.core.rbf.mkimage";
+			bitstream_devpart = "0:1";
 		};
 
 		i2c0: i2c at ffc02200 {
-- 
2.2.0

[U-Boot] [PATCH v2 04/19] arm: socfpga: Add Arria 10 SoCFPGA programming interface

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Add code necessary into the FPGA driver framework in U-Boot
so it can be used via the 'fpga' command for programing Arria 10
SoCFPGA.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 cmd/fpga.c            |  2 +-
 drivers/fpga/altera.c | 39 +++++++++++++++++++++++++++++++--------
 drivers/fpga/fpga.c   |  8 ++++++++
 include/fpga.h        |  2 ++
 4 files changed, 42 insertions(+), 9 deletions(-)

diff --git a/cmd/fpga.c b/cmd/fpga.c
index ac6f504..3cb0bcd 100644
--- a/cmd/fpga.c
+++ b/cmd/fpga.c
@@ -363,7 +363,7 @@ U_BOOT_CMD(fpga, 6, 1, do_fpga,
 	   "(Xilinx only)\n"
 #endif
 #if defined(CONFIG_CMD_FPGA_LOADFS)
-	   "Load device from filesystem (FAT by default) (Xilinx only)\n"
+	   "Load device from filesystem (FAT by default)\n"
 	   "  loadfs [dev] [address] [image size] [blocksize] <interface>\n"
 	   "        [<dev[:part]>] <filename>\n"
 #endif
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
index 135a357..e2bee99 100644
--- a/drivers/fpga/altera.c
+++ b/drivers/fpga/altera.c
@@ -23,25 +23,31 @@ static const struct altera_fpga {
 	enum altera_family	family;
 	const char		*name;
 	int			(*load)(Altera_desc *, const void *, size_t);
+	int (*loadfs)(Altera_desc *, const void *, size_t, fpga_fs_info *);
 	int			(*dump)(Altera_desc *, const void *, size_t);
 	int			(*info)(Altera_desc *);
 } altera_fpga[] = {
 #if defined(CONFIG_FPGA_ACEX1K)
-	{ Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
-	{ Altera_CYC2,   "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
+	{ Altera_ACEX1K, "ACEX1K", ACEX1K_load, NULL, ACEX1K_dump,
+	 ACEX1K_info },
+	{ Altera_CYC2,   "ACEX1K", ACEX1K_load, NULL, ACEX1K_dump,
+	 ACEX1K_info },
 #elif defined(CONFIG_FPGA_CYCLON2)
-	{ Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
-	{ Altera_CYC2,   "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
+	{ Altera_ACEX1K, "CycloneII", CYC2_load, NULL, CYC2_dump, CYC2_info },
+	{ Altera_CYC2,   "CycloneII", CYC2_load, NULL, CYC2_dump, CYC2_info },
 #endif
 #if defined(CONFIG_FPGA_STRATIX_II)
-	{ Altera_StratixII, "StratixII", StratixII_load,
+	{ Altera_StratixII, "StratixII", StratixII_load, NULL,
 	  StratixII_dump, StratixII_info },
 #endif
 #if defined(CONFIG_FPGA_STRATIX_V)
-	{ Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
+	{ Altera_StratixV, "StratixV", stratixv_load, NULL, NULL, NULL },
 #endif
-#if defined(CONFIG_FPGA_SOCFPGA)
-	{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
+#if defined(CONFIG_FPGA_SOCFPGA) && defined(CONFIG_CMD_FPGA_LOADFS)
+	{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, socfpga_loadfs, NULL,
+	 NULL },
+#elif defined(CONFIG_FPGA_SOCFPGA)
+	{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL, NULL },
 #endif
 };
 
@@ -174,3 +180,20 @@ int altera_info(Altera_desc *desc)
 
 	return FPGA_SUCCESS;
 }
+
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+int altera_loadfs(Altera_desc *desc, const void *buf, size_t bsize,
+		   fpga_fs_info *fpga_fsinfo)
+{
+	const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
+
+	if (!fpga)
+		return FPGA_FAIL;
+
+	debug_cond(FPGA_DEBUG, "%s: Launching the %s FS Loader...\n",
+		   __func__, fpga->name);
+	if (fpga->loadfs)
+		return fpga->loadfs(desc, buf, bsize, fpga_fsinfo);
+	return 0;
+}
+#endif
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index e0fb1b4..42e901e 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -198,6 +198,14 @@ int fpga_fsload(int devnum, const void *buf, size_t size,
 			fpga_no_sup((char *)__func__, "Xilinx devices");
 #endif
 			break;
+#if defined(CONFIG_FPGA_ALTERA)
+		case fpga_altera:
+			ret_val = altera_loadfs(desc->devdesc, buf, size,
+						fpga_fsinfo);
+#else
+			fpga_no_sup((char *)__func__, "Altera devices");
+#endif
+			break;
 		default:
 			printf("%s: Invalid or unsupported device type %d\n",
 			       __func__, desc->devtype);
diff --git a/include/fpga.h b/include/fpga.h
index d768fb1..8920016 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -56,8 +56,10 @@ int fpga_count(void);
 const fpga_desc *const fpga_get_desc(int devnum);
 int fpga_load(int devnum, const void *buf, size_t bsize,
 	      bitstream_type bstype);
+#if defined(CONFIG_CMD_FPGA_LOADFS)
 int fpga_fsload(int devnum, const void *buf, size_t size,
 		fpga_fs_info *fpga_fsinfo);
+#endif
 int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
 		       bitstream_type bstype);
 int fpga_dump(int devnum, const void *buf, size_t bsize);
-- 
2.2.0

[U-Boot] [PATCH v2 05/19] arm: socfpga: Enhance FPGA program write rbf data with size >= 4 bytes

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Existing FPGA program write is always assume RBF data >= 32 bytes, so
any rbf data less than 32 bytes writing to FPGA would be failed.
This patch enhances the FPGA program write to support rbf data with
size >= 4 bytes.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 drivers/fpga/socfpga.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index 28fa16b..6e14ebd 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
  * All rights reserved.
  *
  * SPDX-License-Identifier:	BSD-3-Clause
@@ -55,18 +55,20 @@ void fpgamgr_program_write(const void *rbf_data, size_t rbf_size)
 	uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
 
 	asm volatile(
+		"	cmp	%2,	#0\n"
+		"	beq	2f\n"
 		"1:	ldmia	%0!,	{r0-r7}\n"
 		"	stmia	%1!,	{r0-r7}\n"
 		"	sub	%1,	#32\n"
 		"	subs	%2,	#1\n"
 		"	bne	1b\n"
-		"	cmp	%3,	#0\n"
-		"	beq	3f\n"
-		"2:	ldr	%2,	[%0],	#4\n"
+		"2:	cmp	%3,	#0\n"
+		"	beq	4f\n"
+		"3:	ldr	%2,	[%0],	#4\n"
 		"	str	%2,	[%1]\n"
 		"	subs	%3,	#1\n"
-		"	bne	2b\n"
-		"3:	nop\n"
+		"	bne	3b\n"
+		"4:	nop\n"
 		: "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
 		: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
 }
-- 
2.2.0

[U-Boot] [PATCH v2 06/19] dts: Enable fpga-mgr node build for Arria 10 SPL

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

fpga-mgr node is required in SPL, because SPL needs information
from the node to configure FPGA in Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/dts/socfpga_arria10.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index d4368ce..188a039 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -532,6 +532,7 @@
 		};
 
 		fpga_mgr: fpga-mgr at ffd03000 {
+			u-boot,dm-pre-reloc;
 			compatible = "altr,socfpga-a10-fpga-mgr";
 			reg = <0xffd03000 0x100
 			       0xffcfe400 0x20>;
-- 
2.2.0

[U-Boot] [PATCH v2 07/19] fdt: Add compatible strings for Arria 10

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Add compatible strings for Intel Arria 10 SoCFPGA device.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 include/fdtdec.h | 2 ++
 lib/fdtdec.c     | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 4a0947c..095ff36 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -157,6 +157,8 @@ enum fdt_compat_id {
 	COMPAT_ALTERA_SOCFPGA_F2SDR0,           /* SoCFPGA fpga2SDRAM0 bridge */
 	COMPAT_ALTERA_SOCFPGA_F2SDR1,           /* SoCFPGA fpga2SDRAM1 bridge */
 	COMPAT_ALTERA_SOCFPGA_F2SDR2,           /* SoCFPGA fpga2SDRAM2 bridge */
+	COMPAT_ALTERA_SOCFPGA_FPGA0,		/* SOCFPGA FPGA manager */
+	COMPAT_ALTERA_SOCFPGA_NOC,		/* SOCFPGA Arria 10 NOC */
 
 	COMPAT_COUNT,
 };
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 107a892..03ff75e 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -70,6 +70,8 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
 	COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
 	COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
+	COMPAT(ALTERA_SOCFPGA_FPGA0, "altr,socfpga-a10-fpga-mgr"),
+	COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
-- 
2.2.0

[U-Boot] [PATCH v2 08/19] fs: Enable generic filesystems interface support in SPL.

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Enable generic filesystem interface drivers(fs.c and fat/) build
for SPL. This would allow generic filesystem being used in SPL.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 common/spl/Kconfig | 8 ++++++++
 doc/README.SPL     | 1 +
 fs/Makefile        | 1 +
 3 files changed, 10 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 9446cd9..5f4bd92 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -304,6 +304,14 @@ config SPL_ETH_SUPPORT
 	  is required since the network stack uses a number of environment
 	  variables. See also SPL_NET_SUPPORT.
 
+config SPL_FS_GENERIC
+	bool "Support Generic filesystems interface driver"
+	help
+	  Enable support for generic filesystems interface with SPL. This
+	  permits U-Boot (or Linux in Falcon mode) to be loaded from a generic
+	  filesystem from within SPL. Support for the underlying block
+	  device (e.g. MMC or USB) must be enabled separately.
+
 config SPL_EXT_SUPPORT
 	bool "Support EXT filesystems"
 	help
diff --git a/doc/README.SPL b/doc/README.SPL
index 3ba313c..32628a4 100644
--- a/doc/README.SPL
+++ b/doc/README.SPL
@@ -55,6 +55,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT (drivers/mtd/spi/libspi_flash.o)
 CONFIG_SPL_SPI_SUPPORT (drivers/spi/libspi.o)
 CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o)
 CONFIG_SPL_EXT_SUPPORT
+CONFIG_SPL_FS_GENERIC (fs/fs.o fat/)
 CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
 CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o)
 CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
diff --git a/fs/Makefile b/fs/Makefile
index 5770f41..fdacac8 100644
--- a/fs/Makefile
+++ b/fs/Makefile
@@ -7,6 +7,7 @@
 #
 
 ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_FS_GENERIC) += fs.o fat/
 obj-$(CONFIG_SPL_FAT_SUPPORT) += fat/
 obj-$(CONFIG_SPL_EXT_SUPPORT) += ext4/
 else
-- 
2.2.0

[U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA from flash

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

These drivers handle FPGA program operation from flash loading
RBF to memory and then to program FPGA.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 .../include/mach/fpga_manager_arria10.h            |  27 ++
 drivers/fpga/socfpga_arria10.c                     | 391 ++++++++++++++++++++-
 include/altera.h                                   |   6 +
 include/configs/socfpga_common.h                   |   4 +
 4 files changed, 425 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 9cbf696..93a9122 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -8,6 +8,8 @@
 #ifndef _FPGA_MANAGER_ARRIA10_H_
 #define _FPGA_MANAGER_ARRIA10_H_
 
+#include <asm/cache.h>
+
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK		BIT(0)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK	BIT(1)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK 		BIT(2)
@@ -89,11 +91,36 @@ struct socfpga_fpga_manager {
 	u32  imgcfg_fifo_status;
 };
 
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+enum rbf_type {unknown, periph_section, core_section};
+enum rbf_security {invalid, unencrypted, encrypted};
+
+struct rbf_info {
+	enum rbf_type section;
+	enum rbf_security security;
+};
+
+struct flash_info {
+	char *interface;
+	char *dev_part;
+	char *filename;
+	int fstype;
+	u32 remaining;
+	u32 flash_offset;
+	struct rbf_info rbfinfo;
+	struct image_header header;
+};
+#endif
+
 /* Functions */
 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
 int fpgamgr_program_finish(void);
 int is_fpgamgr_user_mode(void);
 int fpgamgr_wait_early_user_mode(void);
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+const char *get_cff_filename(const void *fdt, int *len, u32 core);
+const char *get_cff_devpart(const void *fdt, int *len);
+#endif
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 5c1a68a..5fe57ef 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -13,6 +13,12 @@
 #include <altera.h>
 #include <common.h>
 #include <errno.h>
+#include <fat.h>
+#include <fs.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <part.h>
+#include <spl.h>
 #include <wait_bit.h>
 #include <watchdog.h>
 
@@ -22,6 +28,10 @@
 #define COMPRESSION_OFFSET	229
 #define FPGA_TIMEOUT_MSEC	1000  /* timeout in ms */
 #define FPGA_TIMEOUT_CNT	0x1000000
+#define RBF_UNENCRYPTED		0xa65c
+#define RBF_ENCRYPTED		0xa65d
+#define ARRIA10RBF_PERIPH	0x0001
+#define ARRIA10RBF_CORE		0x8001
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -112,13 +122,14 @@ static int wait_for_nconfig_pin_and_nstatus_pin(void)
 	unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
 				ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
 
-	/* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,
-	 * timeout at 1000ms
+	/*
+	 * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
+	 * de-asserted, timeout at 1000ms
 	 */
 	return wait_for_bit(__func__,
 			    &fpga_manager_base->imgcfg_stat,
 			    mask,
-			    false, FPGA_TIMEOUT_MSEC, false);
+			    true, FPGA_TIMEOUT_MSEC, false);
 }
 
 static int wait_for_f2s_nstatus_pin(unsigned long value)
@@ -469,6 +480,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 
 	/* Initialize the FPGA Manager */
 	status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
+
 	if (status)
 		return status;
 
@@ -477,3 +489,376 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 
 	return fpgamgr_program_finish();
 }
+
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+const char *get_cff_filename(const void *fdt, int *len, u32 core)
+{
+	const char *cff_filename = NULL;
+	const char *cell;
+	int nodeoffset;
+	nodeoffset = fdtdec_next_compatible(fdt, 0,
+			 COMPAT_ALTERA_SOCFPGA_FPGA0);
+
+	if (nodeoffset >= 0) {
+		if (core)
+			cell = fdt_getprop(fdt,
+					nodeoffset,
+					"bitstream_core",
+					len);
+		else
+			cell = fdt_getprop(fdt, nodeoffset, "bitstream_periph",
+					 len);
+
+		if (cell)
+			cff_filename = cell;
+	}
+
+	return cff_filename;
+}
+
+const char *get_cff_devpart(const void *fdt, int *len)
+{
+	const char *cff_devpart = NULL;
+	const char *cell;
+	int nodeoffset;
+	nodeoffset = fdtdec_next_compatible(fdt, 0,
+			 COMPAT_ALTERA_SOCFPGA_FPGA0);
+
+	cell = fdt_getprop(fdt, nodeoffset, "bitstream_devpart", len);
+
+	if (cell)
+		cff_devpart = cell;
+
+	return cff_devpart;
+}
+
+void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
+{
+	/*
+	 * Magic ID starting at:
+	 * -> 1st dword in periph.rbf
+	 * -> 2nd dword in core.rbf
+	 */
+	u32 word_reading_max = 2;
+	u32 i;
+
+	for (i = 0; i < word_reading_max; i++) {
+		if (RBF_UNENCRYPTED == *(buffer + i)) /* PERIPH RBF */
+			rbf->security = unencrypted;
+		else if (RBF_ENCRYPTED == *(buffer + i))
+				rbf->security = encrypted;
+		else if (RBF_UNENCRYPTED == *(buffer + i + 1)) /* CORE RBF */
+				rbf->security = unencrypted;
+		else if (RBF_ENCRYPTED == *(buffer + i + 1))
+				rbf->security = encrypted;
+		else {
+			rbf->security = invalid;
+			continue;
+		}
+
+		/* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */
+		if (ARRIA10RBF_PERIPH == *(buffer + i + 1)) {
+			rbf->section = periph_section;
+			break;
+		} else if (ARRIA10RBF_CORE == *(buffer + i + 1)) {
+			rbf->section = core_section;
+			break;
+		} else if (ARRIA10RBF_PERIPH == *(buffer + i + 2)) {
+			rbf->section = periph_section;
+			break;
+		} else if (ARRIA10RBF_CORE == *(buffer + i + 2)) {
+			rbf->section = core_section;
+			break;
+		} else {
+			rbf->section = unknown;
+			break;
+		}
+	}
+
+	return;
+}
+
+static int flash_read(struct flash_info *flashinfo,
+	u32 size_read,
+	u32 *buffer_ptr)
+{
+	size_t ret = EEXIST;
+	loff_t actread = 0;
+
+	if (fs_set_blk_dev(flashinfo->interface, flashinfo->dev_part,
+				flashinfo->fstype))
+		return FPGA_FAIL;
+
+	ret = fs_read(flashinfo->filename,
+			(u32) buffer_ptr, flashinfo->flash_offset,
+			size_read, &actread);
+
+	if (ret || actread != size_read) {
+		printf("Failed to read %s from flash %d ",
+			flashinfo->filename,
+			 ret);
+		printf("!= %d.\n", size_read);
+		return -EPERM;
+		} else
+			ret = actread;
+
+	return ret;
+}
+
+static int fs_flash_preinit(struct flash_info *flashinfo,
+	u32 *buffer, u32 *buffer_sizebytes)
+{
+	u32 *bufferptr_after_header = NULL;
+	u32 buffersize_after_header = 0;
+	u32 rbf_header_data_size = 0;
+	int ret = 0;
+
+	flashinfo->flash_offset = 0;
+
+	/* To avoid from keeping re-read the contents */
+	struct image_header *header = &(flashinfo->header);
+	size_t buffer_size = *buffer_sizebytes;
+	u32 *buffer_ptr = (u32 *)*buffer;
+
+	 /* Load mkimage header into buffer */
+	ret = flash_read(flashinfo,
+			sizeof(struct image_header), buffer_ptr);
+
+	if (0 >= ret) {
+		printf(" Failed to read mkimage header from flash.\n");
+		return -ENOENT;
+	}
+
+	WATCHDOG_RESET();
+
+	memcpy(header, (u_char *)buffer_ptr, sizeof(*header));
+
+	if (!image_check_magic(header)) {
+		printf("FPGA: Bad Magic Number.\n");
+		return -EBADF;
+	}
+
+	if (!image_check_hcrc(header)) {
+		printf("FPGA: Bad Header Checksum.\n");
+		return -EPERM;
+	}
+
+	/* Getting rbf data size */
+	flashinfo->remaining =
+		image_get_data_size(header);
+
+	/* Calculate total size of both rbf data with mkimage header */
+	rbf_header_data_size = flashinfo->remaining +
+				sizeof(struct image_header);
+
+	/* Loading to buffer chunk by chunk, normally for OCRAM buffer */
+	if (rbf_header_data_size > buffer_size) {
+		/* Calculate size of rbf data in the buffer */
+		buffersize_after_header =
+			buffer_size - sizeof(struct image_header);
+		flashinfo->remaining -= buffersize_after_header;
+	} else {
+	/* Loading whole rbf image into buffer, normally for DDR buffer */
+		buffer_size = rbf_header_data_size;
+		/* Calculate size of rbf data in the buffer */
+		buffersize_after_header =
+			buffer_size - sizeof(struct image_header);
+		flashinfo->remaining = 0;
+	}
+
+	/* Loading mkimage header and rbf data into buffer */
+	ret = flash_read(flashinfo, buffer_size, buffer_ptr);
+
+	if (0 >= ret) {
+		printf(" Failed to read mkimage header and rbf data ");
+		printf("from flash.\n");
+		return -ENOENT;
+	}
+
+	/*
+	 * Getting pointer of rbf data starting address where is it
+	 * right after mkimage header
+	 */
+	bufferptr_after_header =
+		(u32 *)((u_char *)buffer_ptr + sizeof(struct image_header));
+
+	/* Update next reading rbf data flash offset */
+	flashinfo->flash_offset += buffer_size;
+
+	/*
+	 * Update the starting addr of rbf data to init FPGA & programming
+	 * into FPGA
+	 */
+	*buffer = (u32)bufferptr_after_header;
+
+	get_rbf_image_info(&flashinfo->rbfinfo, (u16 *)bufferptr_after_header);
+
+	/* Update the size of rbf data to be programmed into FPGA */
+	*buffer_sizebytes = buffersize_after_header;
+
+#ifdef CONFIG_CHECK_FPGA_DATA_CRC
+	flashinfo->datacrc =
+		crc32(flashinfo->datacrc,
+		(u_char *)bufferptr_after_header,
+		buffersize_after_header);
+#endif
+
+if (0 == flashinfo->remaining) {
+#ifdef CONFIG_CHECK_FPGA_DATA_CRC
+	if (flashinfo->datacrc !=
+		image_get_dcrc(&(flashinfo->header))) {
+		printf("FPGA: Bad Data Checksum.\n");
+		return -EPERM;
+	}
+#endif
+}
+	return 0;
+}
+
+static int fs_flash_read(struct flash_info *flashinfo, u32 *buffer,
+	u32 *buffer_sizebytes)
+{
+	int ret = 0;
+	/* To avoid from keeping re-read the contents */
+	size_t buffer_size = *buffer_sizebytes;
+	u32 *buffer_ptr = (u32 *)*buffer;
+	u32 flash_addr = flashinfo->flash_offset;
+
+	/* Buffer allocated in OCRAM */
+	/* Read the data by small chunk by chunk. */
+	if (flashinfo->remaining > buffer_size)
+		flashinfo->remaining -= buffer_size;
+	else {
+		/*
+		 * Buffer allocated in DDR, larger than rbf data most
+		 * of the time
+		 */
+		buffer_size = flashinfo->remaining;
+		flashinfo->remaining = 0;
+	}
+
+	ret = flash_read(flashinfo, buffer_size, buffer_ptr);
+
+	if (0 >= ret) {
+		printf(" Failed to read rbf data from flash.\n");
+		return -ENOENT;
+	}
+
+#ifdef CONFIG_CHECK_FPGA_DATA_CRC
+	flashinfo->datacrc =
+		crc32(flashinfo->datacrc,
+			(unsigned char *)buffer_ptr, buffer_size);
+#endif
+
+if (0 == flashinfo->remaining) {
+#ifdef CONFIG_CHECK_FPGA_DATA_CRC
+	if (flashinfo->datacrc !=
+		image_get_dcrc(&(flashinfo->header))) {
+		printf("FPGA: Bad Data Checksum.\n");
+		return -EPERM;
+	}
+#endif
+}
+	/* Update next reading rbf data flash offset */
+	flash_addr += buffer_size;
+
+	flashinfo->flash_offset = flash_addr;
+
+	/* Update the size of rbf data to be programmed into FPGA */
+	*buffer_sizebytes = buffer_size;
+
+	return 0;
+}
+
+int socfpga_loadfs(Altera_desc *desc, const void *buf, size_t bsize,
+		   fpga_fs_info *fpga_fsinfo)
+{
+	u32 buffer = 0;
+	u32 buffer_ori = 0;
+	size_t buffer_sizebytes = 0;
+	size_t buffer_sizebytes_ori = 0;
+	struct flash_info flashinfo;
+	u32 status = 0;
+	int ret = 0;
+
+	memset(&flashinfo, 0, sizeof(flashinfo));
+
+	if (fpga_fsinfo->filename == NULL) {
+		printf("no peripheral RBF filename specified.\n");
+		return -EINVAL;
+	}
+
+	WATCHDOG_RESET();
+
+	buffer_sizebytes = buffer_sizebytes_ori = bsize;
+	buffer = buffer_ori = (u32) buf;
+	flashinfo.interface = fpga_fsinfo->interface;
+	flashinfo.dev_part = fpga_fsinfo->dev_part;
+	flashinfo.filename = fpga_fsinfo->filename;
+	flashinfo.fstype = fpga_fsinfo->fstype;
+
+	/*
+	 * Note: Both buffer and buffer_sizebytes values can be altered by
+	 * function below.
+	 */
+	ret = fs_flash_preinit(&flashinfo, &buffer, &buffer_sizebytes);
+
+	if (ret)
+		return ret;
+
+	if (periph_section == flashinfo.rbfinfo.section) {
+		/* Initialize the FPGA Manager */
+		status = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes);
+		if (status) {
+			printf("FPGA: Init with periph rbf failed with error. ");
+			printf("code %d\n", status);
+			return -EPERM;
+		}
+	}
+
+	WATCHDOG_RESET();
+
+	/* Transfer data to FPGA Manager */
+	fpgamgr_program_write((void *)buffer,
+		buffer_sizebytes);
+
+	WATCHDOG_RESET();
+
+	while (flashinfo.remaining) {
+		ret = fs_flash_read(&flashinfo, &buffer_ori,
+			&buffer_sizebytes_ori);
+
+		if (ret)
+			return ret;
+
+		/* transfer data to FPGA Manager */
+		fpgamgr_program_write((void *)buffer_ori,
+			buffer_sizebytes_ori);
+
+		WATCHDOG_RESET();
+	}
+
+	if (periph_section == flashinfo.rbfinfo.section) {
+		if (-ETIMEDOUT != fpgamgr_wait_early_user_mode())
+			printf("FPGA: Early Release Succeeded.\n");
+		else {
+			printf("FPGA: Failed to see Early Release.\n");
+			return -EIO;
+		}
+	} else if (core_section == flashinfo.rbfinfo.section) {
+		/* Ensure the FPGA entering config done */
+		status = fpgamgr_program_finish();
+		if (status)
+			return status;
+		else
+			printf("FPGA: Enter user mode.\n");
+
+	} else {
+		printf("Config Error: Unsupported FGPA raw binary type.\n");
+		return -ENOEXEC;
+	}
+
+	WATCHDOG_RESET();
+	return 1;
+}
+#endif
diff --git a/include/altera.h b/include/altera.h
index 48d3eb7..0597e8a 100644
--- a/include/altera.h
+++ b/include/altera.h
@@ -84,6 +84,10 @@ typedef struct {
 extern int altera_load(Altera_desc *desc, const void *image, size_t size);
 extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize);
 extern int altera_info(Altera_desc *desc);
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+int altera_loadfs(Altera_desc *desc, const void *buf, size_t bsize,
+		   fpga_fs_info *fpga_fsinfo);
+#endif
 
 /* Board specific implementation specific function types
  *********************************************************************/
@@ -111,6 +115,8 @@ typedef struct {
 
 #ifdef CONFIG_FPGA_SOCFPGA
 int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
+int socfpga_loadfs(Altera_desc *desc, const void *buf, size_t bsize,
+		   fpga_fs_info *fpga_fsinfo);
 #endif
 
 #ifdef CONFIG_FPGA_STRATIX_V
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 9897e11..eadce2d 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -27,7 +27,11 @@
  */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM_1			0x0
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SYS_MALLOC_LEN		(64 * 1024 * 1024)
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024 * 1024)
+#endif
 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
 #define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-- 
2.2.0

[U-Boot] [PATCH v2 10/19] arm: socfpga: Rename the gen5 sdram driver to more specific name

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Current sdram driver is only applied to gen5 device, hence it is better
to rename sdram driver to more specific name which is related to gen5
device.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/include/mach/sdram.h         | 434 +--------------------
 .../include/mach/{sdram.h => sdram_gen5.h}         |   6 +-
 drivers/ddr/altera/Makefile                        |   2 +-
 drivers/ddr/altera/{sdram.c => sdram_gen5.c}       |   0
 4 files changed, 8 insertions(+), 434 deletions(-)
 copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h} (99%)
 rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)

diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index b11228f..4a9754e 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -1,5 +1,5 @@
 /*
- * Copyright Altera Corporation (C) 2014-2015
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -8,435 +8,9 @@
 
 #ifndef __ASSEMBLY__
 
-unsigned long sdram_calculate_size(void);
-int sdram_mmr_init_full(unsigned int sdr_phy_reg);
-int sdram_calibration_full(void);
-
-const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
-
-void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
-void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
-const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
-const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
-const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
-
-#define SDR_CTRLGRP_ADDRESS	(SOCFPGA_SDR_ADDRESS | 0x5000)
-
-struct socfpga_sdr_ctrl {
-	u32	ctrl_cfg;
-	u32	dram_timing1;
-	u32	dram_timing2;
-	u32	dram_timing3;
-	u32	dram_timing4;	/* 0x10 */
-	u32	lowpwr_timing;
-	u32	dram_odt;
-	u32	extratime1;
-	u32	__padding0[3];
-	u32	dram_addrw;	/* 0x2c */
-	u32	dram_if_width;	/* 0x30 */
-	u32	dram_dev_width;
-	u32	dram_sts;
-	u32	dram_intr;
-	u32	sbe_count;	/* 0x40 */
-	u32	dbe_count;
-	u32	err_addr;
-	u32	drop_count;
-	u32	drop_addr;	/* 0x50 */
-	u32	lowpwr_eq;
-	u32	lowpwr_ack;
-	u32	static_cfg;
-	u32	ctrl_width;	/* 0x60 */
-	u32	cport_width;
-	u32	cport_wmap;
-	u32	cport_rmap;
-	u32	rfifo_cmap;	/* 0x70 */
-	u32	wfifo_cmap;
-	u32	cport_rdwr;
-	u32	port_cfg;
-	u32	fpgaport_rst;	/* 0x80 */
-	u32	__padding1;
-	u32	fifo_cfg;
-	u32	protport_default;
-	u32	prot_rule_addr;	/* 0x90 */
-	u32	prot_rule_id;
-	u32	prot_rule_data;
-	u32	prot_rule_rdwr;
-	u32	__padding2[3];
-	u32	mp_priority;	/* 0xac */
-	u32	mp_weight0;	/* 0xb0 */
-	u32	mp_weight1;
-	u32	mp_weight2;
-	u32	mp_weight3;
-	u32	mp_pacing0;	/* 0xc0 */
-	u32	mp_pacing1;
-	u32	mp_pacing2;
-	u32	mp_pacing3;
-	u32	mp_threshold0;	/* 0xd0 */
-	u32	mp_threshold1;
-	u32	mp_threshold2;
-	u32	__padding3[29];
-	u32	phy_ctrl0;	/* 0x150 */
-	u32	phy_ctrl1;
-	u32	phy_ctrl2;
-};
-
-/* SDRAM configuration structure for the SPL. */
-struct socfpga_sdram_config {
-	u32	ctrl_cfg;
-	u32	dram_timing1;
-	u32	dram_timing2;
-	u32	dram_timing3;
-	u32	dram_timing4;
-	u32	lowpwr_timing;
-	u32	dram_odt;
-	u32	extratime1;
-	u32	dram_addrw;
-	u32	dram_if_width;
-	u32	dram_dev_width;
-	u32	dram_intr;
-	u32	lowpwr_eq;
-	u32	static_cfg;
-	u32	ctrl_width;
-	u32	cport_width;
-	u32	cport_wmap;
-	u32	cport_rmap;
-	u32	rfifo_cmap;
-	u32	wfifo_cmap;
-	u32	cport_rdwr;
-	u32	port_cfg;
-	u32	fpgaport_rst;
-	u32	fifo_cfg;
-	u32	mp_priority;
-	u32	mp_weight0;
-	u32	mp_weight1;
-	u32	mp_weight2;
-	u32	mp_weight3;
-	u32	mp_pacing0;
-	u32	mp_pacing1;
-	u32	mp_pacing2;
-	u32	mp_pacing3;
-	u32	mp_threshold0;
-	u32	mp_threshold1;
-	u32	mp_threshold2;
-	u32	phy_ctrl0;
-};
-
-struct socfpga_sdram_rw_mgr_config {
-	u8	activate_0_and_1;
-	u8	activate_0_and_1_wait1;
-	u8	activate_0_and_1_wait2;
-	u8	activate_1;
-	u8	clear_dqs_enable;
-	u8	guaranteed_read;
-	u8	guaranteed_read_cont;
-	u8	guaranteed_write;
-	u8	guaranteed_write_wait0;
-	u8	guaranteed_write_wait1;
-	u8	guaranteed_write_wait2;
-	u8	guaranteed_write_wait3;
-	u8	idle;
-	u8	idle_loop1;
-	u8	idle_loop2;
-	u8	init_reset_0_cke_0;
-	u8	init_reset_1_cke_0;
-	u8	lfsr_wr_rd_bank_0;
-	u8	lfsr_wr_rd_bank_0_data;
-	u8	lfsr_wr_rd_bank_0_dqs;
-	u8	lfsr_wr_rd_bank_0_nop;
-	u8	lfsr_wr_rd_bank_0_wait;
-	u8	lfsr_wr_rd_bank_0_wl_1;
-	u8	lfsr_wr_rd_dm_bank_0;
-	u8	lfsr_wr_rd_dm_bank_0_data;
-	u8	lfsr_wr_rd_dm_bank_0_dqs;
-	u8	lfsr_wr_rd_dm_bank_0_nop;
-	u8	lfsr_wr_rd_dm_bank_0_wait;
-	u8	lfsr_wr_rd_dm_bank_0_wl_1;
-	u8	mrs0_dll_reset;
-	u8	mrs0_dll_reset_mirr;
-	u8	mrs0_user;
-	u8	mrs0_user_mirr;
-	u8	mrs1;
-	u8	mrs1_mirr;
-	u8	mrs2;
-	u8	mrs2_mirr;
-	u8	mrs3;
-	u8	mrs3_mirr;
-	u8	precharge_all;
-	u8	read_b2b;
-	u8	read_b2b_wait1;
-	u8	read_b2b_wait2;
-	u8	refresh_all;
-	u8	rreturn;
-	u8	sgle_read;
-	u8	zqcl;
-
-	u8	true_mem_data_mask_width;
-	u8	mem_address_mirroring;
-	u8	mem_data_mask_width;
-	u8	mem_data_width;
-	u8	mem_dq_per_read_dqs;
-	u8	mem_dq_per_write_dqs;
-	u8	mem_if_read_dqs_width;
-	u8	mem_if_write_dqs_width;
-	u8	mem_number_of_cs_per_dimm;
-	u8	mem_number_of_ranks;
-	u8	mem_virtual_groups_per_read_dqs;
-	u8	mem_virtual_groups_per_write_dqs;
-};
-
-struct socfpga_sdram_io_config {
-	u16	delay_per_opa_tap;
-	u8	delay_per_dchain_tap;
-	u8	delay_per_dqs_en_dchain_tap;
-	u8	dll_chain_length;
-	u8	dqdqs_out_phase_max;
-	u8	dqs_en_delay_max;
-	u8	dqs_en_delay_offset;
-	u8	dqs_en_phase_max;
-	u8	dqs_in_delay_max;
-	u8	dqs_in_reserve;
-	u8	dqs_out_reserve;
-	u8	io_in_delay_max;
-	u8	io_out1_delay_max;
-	u8	io_out2_delay_max;
-	u8	shift_dqs_en_when_shift_dqs;
-};
-
-struct socfpga_sdram_misc_config {
-	u32	reg_file_init_seq_signature;
-	u8	afi_rate_ratio;
-	u8	calib_lfifo_offset;
-	u8	calib_vfifo_offset;
-	u8	enable_super_quick_calibration;
-	u8	max_latency_count_width;
-	u8	read_valid_fifo_size;
-	u8	tinit_cntr0_val;
-	u8	tinit_cntr1_val;
-	u8	tinit_cntr2_val;
-	u8	treset_cntr0_val;
-	u8	treset_cntr1_val;
-	u8	treset_cntr2_val;
-};
-
-#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
-#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
-#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
-#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
-#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
-#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
-#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
-#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
-#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
-#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
-#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
-#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
-#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
-#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
-#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
-#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
-#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
-#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
-/* Register template: sdr::ctrlgrp::dramtiming1                            */
-#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
-#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
-#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
-#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
-#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
-#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
-#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
-#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
-#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
-#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
-#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramtiming2                            */
-#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
-#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
-#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
-#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
-#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
-#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
-#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
-#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
-#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
-/* Register template: sdr::ctrlgrp::dramtiming3                            */
-#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
-#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
-#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
-#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
-#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
-#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
-#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
-#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
-#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramtiming4                            */
-#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
-#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
-#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
-#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
-#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::lowpwrtiming                           */
-#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
-#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
-#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
-#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
-/* Register template: sdr::ctrlgrp::dramaddrw                              */
-#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
-#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
-#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
-#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
-#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
-#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
-#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
-#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
-/* Register template: sdr::ctrlgrp::dramifwidth                            */
-#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
-#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
-/* Register template: sdr::ctrlgrp::dramdevwidth                           */
-#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
-#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramintr                               */
-#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
-#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
-#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
-#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
-/* Register template: sdr::ctrlgrp::staticcfg                              */
-#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
-#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
-#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
-#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
-#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
-#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
-/* Register template: sdr::ctrlgrp::ctrlwidth                              */
-#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
-#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
-/* Register template: sdr::ctrlgrp::cportwidth                             */
-#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
-#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
-/* Register template: sdr::ctrlgrp::cportwmap                              */
-#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
-#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
-/* Register template: sdr::ctrlgrp::cportrmap                              */
-#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
-#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
-/* Register template: sdr::ctrlgrp::rfifocmap                              */
-#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
-#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
-/* Register template: sdr::ctrlgrp::wfifocmap                              */
-#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
-#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
-/* Register template: sdr::ctrlgrp::cportrdwr                              */
-#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
-#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
-/* Register template: sdr::ctrlgrp::portcfg                                */
-#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
-#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
-#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
-#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::fifocfg                                */
-#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
-#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
-#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
-#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::mppriority                             */
-#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
-#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_0                   */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_1                   */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_2                   */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_3                   */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_0                   */
-#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_1                   */
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_2                   */
-#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_3                   */
-#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0       */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
-#define  \
-SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
-0xffffffff
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1       */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
-0xffffffff
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2       */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
-0x0000ffff
-/* Register template: sdr::ctrlgrp::remappriority                          */
-#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
-#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0                     */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
- (((x) << 12) & 0xfffff000)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
- (((x) << 10) & 0x00000c00)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
- (((x) << 6) & 0x000000c0)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
- (((x) << 8) & 0x00000100)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
- (((x) << 9) & 0x00000200)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
- (((x) << 4) & 0x00000030)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
- (((x) << 2) & 0x0000000c)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
- (((x) << 0) & 0x00000003)
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1                     */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
- (((x) << 12) & 0xfffff000)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
- (((x) << 0) & 0x00000fff)
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2                     */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
- (((x) << 0) & 0x00000fff)
-/* Register template: sdr::ctrlgrp::dramodt                                */
-#define SDR_CTRLGRP_DRAMODT_READ_LSB 4
-#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
-#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
-#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
-/* Field instance: sdr::ctrlgrp::dramsts                                   */
-#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
-#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
-/* Register template: sdr::ctrlgrp::extratime1                             */
-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
-
-/* SDRAM width macro for configuration with ECC */
-#define SDRAM_WIDTH_32BIT_WITH_ECC	40
-#define SDRAM_WIDTH_16BIT_WITH_ECC	24
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/sdram_gen5.h>
+#endif
 
 #endif
 #endif /* _SDRAM_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
similarity index 99%
copy from arch/arm/mach-socfpga/include/mach/sdram.h
copy to arch/arm/mach-socfpga/include/mach/sdram_gen5.h
index b11228f..b16d776 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-#ifndef	_SDRAM_H_
-#define	_SDRAM_H_
+#ifndef	_SOCFPGA_SDRAM_GEN5_H_
+#define	_SOCFPGA_SDRAM_GEN5_H_
 
 #ifndef __ASSEMBLY__
 
@@ -439,4 +439,4 @@ SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
 #define SDRAM_WIDTH_16BIT_WITH_ECC	24
 
 #endif
-#endif /* _SDRAM_H_ */
+#endif /* _SOCFPGA_SDRAM_GEN5_H_ */
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index bdd2872..ac4ab85 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -9,5 +9,5 @@
 #
 
 ifdef CONFIG_ALTERA_SDRAM
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
 endif
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram_gen5.c
similarity index 100%
rename from drivers/ddr/altera/sdram.c
rename to drivers/ddr/altera/sdram_gen5.c
-- 
2.2.0

[U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size initialization function

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Add function for both multiple DRAM bank and single DRAM bank size
initialization. This common functionality could be used by every single
SOCFPGA board.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/board.c    | 7 +++++++
 include/configs/socfpga_common.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index a41d089..965f9dc 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -29,6 +29,13 @@ int board_init(void)
 	return 0;
 }
 
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
 #ifdef CONFIG_USB_GADGET
 struct dwc2_plat_otg_data socfpga_otg_data = {
 	.usb_gusbcfg	= 0x1417,
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index eadce2d..7549ee8 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -47,6 +47,7 @@
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_SIZE		PHYS_SDRAM_1_SIZE
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_TEXT_BASE		0x08000040
 #else
-- 
2.2.0

[U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for Arria 10

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Add DDR driver suppport for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/include/mach/sdram.h         |   2 +
 arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-
 drivers/ddr/altera/sdram_arria10.c                 | 735 +++++++++++++++++++++
 3 files changed, 839 insertions(+), 1 deletion(-)
 create mode 100644 drivers/ddr/altera/sdram_arria10.c

diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index 4a9754e..b833fc2 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -10,6 +10,8 @@
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include <asm/arch/sdram_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/sdram_arria10.h>
 #endif
 
 #endif
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
index 1d7b7c1..7af9431 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2015-2017 Intel Corporation <www.intel.com>
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
  *
  * SPDX-License-Identifier:	GPL-2.0
  */
@@ -8,6 +8,7 @@
 #define _SOCFPGA_SDRAM_ARRIA10_H_
 
 #ifndef __ASSEMBLY__
+int ddr_calibration_sequence(void);
 
 struct socfpga_ecc_hmc {
 	u32 ip_rev_id;
@@ -204,6 +205,106 @@ struct socfpga_io48_mmr {
 	u32 niosreserve1;
 	u32 niosreserve2;
 };
+
+union dramaddrw_reg {
+	struct {
+		u32 cfg_col_addr_width:5;
+		u32 cfg_row_addr_width:5;
+		u32 cfg_bank_addr_width:4;
+		u32 cfg_bank_group_addr_width:2;
+		u32 cfg_cs_addr_width:3;
+		u32 reserved:13;
+	};
+	u32 word;
+};
+
+union ctrlcfg0_reg {
+	struct {
+		u32 cfg_mem_type:4;
+		u32 cfg_dimm_type:3;
+		u32 cfg_ac_pos:2;
+		u32 cfg_ctrl_burst_len:5;
+		u32 reserved:18;  /* Other fields unused */
+	};
+	u32 word;
+};
+
+union ctrlcfg1_reg {
+	struct {
+		u32 cfg_dbc3_burst_len:5;
+		u32 cfg_addr_order:2;
+		u32 cfg_ctrl_enable_ecc:1;
+		u32 reserved:24;  /* Other fields unused */
+	};
+	u32 word;
+};
+
+union caltiming0_reg {
+	struct {
+		u32 cfg_act_to_rdwr:6;
+		u32 cfg_act_to_pch:6;
+		u32 cfg_act_to_act:6;
+		u32 cfg_act_to_act_db:6;
+		u32 reserved:8;  /* Other fields unused */
+	};
+	u32 word;
+};
+
+union caltiming1_reg {
+	struct {
+		u32 cfg_rd_to_rd:6;
+		u32 cfg_rd_to_rd_dc:6;
+		u32 cfg_rd_to_rd_db:6;
+		u32 cfg_rd_to_wr:6;
+		u32 cfg_rd_to_wr_dc:6;
+		u32 reserved:2;
+	};
+	u32 word;
+};
+
+union caltiming2_reg {
+	struct {
+		u32 cfg_rd_to_wr_db:6;
+		u32 cfg_rd_to_pch:6;
+		u32 cfg_rd_ap_to_valid:6;
+		u32 cfg_wr_to_wr:6;
+		u32 cfg_wr_to_wr_dc:6;
+		u32 reserved:2;
+	};
+	u32 word;
+};
+
+union caltiming3_reg {
+	struct {
+		u32 cfg_wr_to_wr_db:6;
+		u32 cfg_wr_to_rd:6;
+		u32 cfg_wr_to_rd_dc:6;
+		u32 cfg_wr_to_rd_db:6;
+		u32 cfg_wr_to_pch:6;
+		u32 reserved:2;
+	};
+	u32 word;
+};
+
+union caltiming4_reg {
+	struct {
+		u32 cfg_wr_ap_to_valid:6;
+		u32 cfg_pch_to_valid:6;
+		u32 cfg_pch_all_to_valid:6;
+		u32 cfg_arf_to_valid:8;
+		u32 cfg_pdn_to_valid:6;
+	};
+	u32 word;
+};
+
+union caltiming9_reg {
+	struct {
+		u32 cfg_4_act_to_act:8;
+		u32 reserved:24;
+	};
+	u32 word;
+};
+
 #endif /*__ASSEMBLY__*/
 
 #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK		0x1F000000
diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c
new file mode 100644
index 0000000..f22a726
--- /dev/null
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -0,0 +1,735 @@
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <watchdog.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/sdram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_mmr_init(void);
+static unsigned long long sdram_size_calc(void);
+
+/* FAWBANK - Number of Bank of a given device involved in the FAW period. */
+#define ARRIA10_SDR_ACTIVATE_FAWBANK	(0x1)
+
+#define ARRIA_DDR_CONFIG(A, B, C, R)	((A<<24)|(B<<16)|(C<<8)|R)
+#define DDR_CONFIG_ELEMENTS	(sizeof(ddr_config)/sizeof(u32))
+#define DDR_REG_SEQ2CORE        0xFFD0507C
+#define DDR_REG_CORE2SEQ        0xFFD05078
+#define DDR_READ_LATENCY_DELAY	40
+#define DDR_SIZE_2GB_HEX	0x80000000
+#define DDR_MAX_TRIES		0x00100000
+
+#define IO48_MMR_DRAMSTS	0xFFCFA0EC
+#define IO48_MMR_NIOS2_RESERVE0	0xFFCFA110
+#define IO48_MMR_NIOS2_RESERVE1	0xFFCFA114
+#define IO48_MMR_NIOS2_RESERVE2	0xFFCFA118
+
+#define SEQ2CORE_MASK		0xF
+#define CORE2SEQ_INT_REQ	0xF
+#define SEQ2CORE_INT_RESP_BIT	3
+
+static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
+		(void *)SOCFPGA_SDR_ADDRESS;
+static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
+		(void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
+static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
+		*socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
+		(void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
+static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
+		(void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
+static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
+		(void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
+
+/* The followring are the supported configurations */
+static u32 ddr_config[] = {
+	/* Chip - Row - Bank - Column Style */
+	/* All Types */
+	ARRIA_DDR_CONFIG(0, 3, 10, 12),
+	ARRIA_DDR_CONFIG(0, 3, 10, 13),
+	ARRIA_DDR_CONFIG(0, 3, 10, 14),
+	ARRIA_DDR_CONFIG(0, 3, 10, 15),
+	ARRIA_DDR_CONFIG(0, 3, 10, 16),
+	ARRIA_DDR_CONFIG(0, 3, 10, 17),
+	/* LPDDR x16 */
+	ARRIA_DDR_CONFIG(0, 3, 11, 14),
+	ARRIA_DDR_CONFIG(0, 3, 11, 15),
+	ARRIA_DDR_CONFIG(0, 3, 11, 16),
+	ARRIA_DDR_CONFIG(0, 3, 12, 15),
+	/* DDR4 Only */
+	ARRIA_DDR_CONFIG(0, 4, 10, 14),
+	ARRIA_DDR_CONFIG(0, 4, 10, 15),
+	ARRIA_DDR_CONFIG(0, 4, 10, 16),
+	ARRIA_DDR_CONFIG(0, 4, 10, 17),	/* 14 */
+	/* Chip - Bank - Row - Column Style */
+	ARRIA_DDR_CONFIG(1, 3, 10, 12),
+	ARRIA_DDR_CONFIG(1, 3, 10, 13),
+	ARRIA_DDR_CONFIG(1, 3, 10, 14),
+	ARRIA_DDR_CONFIG(1, 3, 10, 15),
+	ARRIA_DDR_CONFIG(1, 3, 10, 16),
+	ARRIA_DDR_CONFIG(1, 3, 10, 17),
+	ARRIA_DDR_CONFIG(1, 3, 11, 14),
+	ARRIA_DDR_CONFIG(1, 3, 11, 15),
+	ARRIA_DDR_CONFIG(1, 3, 11, 16),
+	ARRIA_DDR_CONFIG(1, 3, 12, 15),
+	/* DDR4 Only */
+	ARRIA_DDR_CONFIG(1, 4, 10, 14),
+	ARRIA_DDR_CONFIG(1, 4, 10, 15),
+	ARRIA_DDR_CONFIG(1, 4, 10, 16),
+	ARRIA_DDR_CONFIG(1, 4, 10, 17),
+};
+
+static int match_ddr_conf(u32 ddr_conf)
+{
+	int i;
+
+	for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
+		if (ddr_conf == ddr_config[i])
+			return i;
+	}
+	return 0;
+}
+
+/* Check whether SDRAM is successfully Calibrated */
+static int is_sdram_cal_success(void)
+{
+	return readl(&socfpga_ecc_hmc_base->ddrcalstat);
+}
+
+static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)
+{
+	u32 reg = readl(ereg);
+
+	return (reg & (1 << bit)) ? 1 : 0;
+}
+
+static unsigned char ddr_wait_bit(u32 ereg, u32 bit,
+			   u32 expected, u32 timeout_usec)
+{
+	u32 tmr;
+
+	for (tmr = 0; tmr < timeout_usec; tmr += 100) {
+		udelay(100);
+		WATCHDOG_RESET();
+		if (ddr_get_bit(ereg, bit) == expected)
+			return 0;
+	}
+
+	return 1;
+}
+
+static void ddr_delay(u32 delay)
+{
+	int tmr;
+
+	for (tmr = 0; tmr < delay; tmr++) {
+		udelay(1000);
+		WATCHDOG_RESET();
+	}
+}
+
+static int emif_clear(void)
+{
+	u32 s2c;
+	u32 i = DDR_MAX_TRIES;
+
+	writel(0, DDR_REG_CORE2SEQ);
+	do {
+		ddr_delay(50);
+		s2c = readl(DDR_REG_SEQ2CORE);
+	} while ((s2c & SEQ2CORE_MASK) && (--i > 0));
+
+	return !i;
+}
+
+static int emif_reset(void)
+{
+	u32 c2s, s2c;
+
+	c2s = readl(DDR_REG_CORE2SEQ);
+	s2c = readl(DDR_REG_SEQ2CORE);
+
+	debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
+		c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
+		readl(IO48_MMR_NIOS2_RESERVE1),
+		readl(IO48_MMR_NIOS2_RESERVE2),
+		readl(IO48_MMR_DRAMSTS));
+
+	if ((s2c & SEQ2CORE_MASK) && emif_clear()) {
+		printf("failed emif_clear()\n");
+		return -1;
+	}
+
+	writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
+
+	if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {
+		printf("emif_reset failed to see interrupt acknowledge\n");
+		return -2;
+	} else {
+		printf("emif_reset interrupt acknowledged\n");
+	}
+
+	if (emif_clear()) {
+		printf("emif_clear() failed\n");
+		return -3;
+	}
+	debug("emif_reset interrupt cleared\n");
+
+	debug("nr0=%08x nr1=%08x nr2=%08x\n",
+		readl(IO48_MMR_NIOS2_RESERVE0),
+		readl(IO48_MMR_NIOS2_RESERVE1),
+		readl(IO48_MMR_NIOS2_RESERVE2));
+
+	return 0;
+}
+
+static int ddr_setup(void)
+{
+	int i, j, ddr_setup_complete = 0;
+
+	/* Try 3 times to do a calibration */
+	for (i = 0; (i < 3) && !ddr_setup_complete; i++) {
+		WATCHDOG_RESET();
+
+		/* A delay to wait for calibration bit to set */
+		for (j = 0; (j < 10) && !ddr_setup_complete; j++) {
+			ddr_delay(500);
+			ddr_setup_complete = is_sdram_cal_success();
+		}
+
+		if (!ddr_setup_complete)
+			emif_reset();
+	}
+
+	if (!ddr_setup_complete) {
+		puts("Error: Could Not Calibrate SDRAM\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+/* Function to startup the SDRAM*/
+static int sdram_startup(void)
+{
+	/* Release NOC ddr scheduler from reset */
+	socfpga_reset_deassert_noc_ddr_scheduler();
+
+	/* Bringup the DDR (calibration and configuration) */
+	return ddr_setup();
+}
+
+static unsigned long long sdram_size_calc(void)
+{
+	union dramaddrw_reg dramaddrw =
+		(union dramaddrw_reg)readl(&socfpga_io48_mmr_base->dramaddrw);
+
+	unsigned long long size = (1 << (dramaddrw.cfg_cs_addr_width +
+				dramaddrw.cfg_bank_group_addr_width +
+				dramaddrw.cfg_bank_addr_width +
+				dramaddrw.cfg_row_addr_width +
+				dramaddrw.cfg_col_addr_width));
+
+	size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
+		       ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
+
+	return size;
+}
+
+/* Function to initialize SDRAM MMR and NOC DDR scheduler*/
+static void sdram_mmr_init(void)
+{
+	u32 update_value, io48_value;
+	union ctrlcfg0_reg ctrlcfg0 =
+		(union ctrlcfg0_reg)readl(&socfpga_io48_mmr_base->ctrlcfg0);
+	union ctrlcfg1_reg ctrlcfg1 =
+		(union ctrlcfg1_reg)readl(&socfpga_io48_mmr_base->ctrlcfg1);
+	union dramaddrw_reg dramaddrw =
+		(union dramaddrw_reg)readl(&socfpga_io48_mmr_base->dramaddrw);
+	union caltiming0_reg caltim0 =
+		(union caltiming0_reg)readl(&socfpga_io48_mmr_base->caltiming0);
+	union caltiming1_reg caltim1 =
+		(union caltiming1_reg)readl(&socfpga_io48_mmr_base->caltiming1);
+	union caltiming2_reg caltim2 =
+		(union caltiming2_reg)readl(&socfpga_io48_mmr_base->caltiming2);
+	union caltiming3_reg caltim3 =
+		(union caltiming3_reg)readl(&socfpga_io48_mmr_base->caltiming3);
+	union caltiming4_reg caltim4 =
+		(union caltiming4_reg)readl(&socfpga_io48_mmr_base->caltiming4);
+	union caltiming9_reg caltim9 =
+		(union caltiming9_reg)readl(&socfpga_io48_mmr_base->caltiming9);
+	u32 ddrioctl;
+
+	/*
+	 * Configure the DDR IO size [0xFFCFB008]
+	 * niosreserve0: Used to indicate DDR width &
+	 *	bit[7:0] = Number of data bits (0x20 for 32bit)
+	 *	bit[8]   = 1 if user-mode OCT is present
+	 *	bit[9]   = 1 if warm reset compiled into EMIF Cal Code
+	 *	bit[10]  = 1 if warm reset is on during generation in EMIF Cal
+	 * niosreserve1: IP ADCDS version encoded as 16 bit value
+	 *	bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
+	 *			    3=EAP, 4-6 are reserved)
+	 *	bit[5:3] = Service Pack # (e.g. 1)
+	 *	bit[9:6] = Minor Release #
+	 *	bit[14:10] = Major Release #
+	 */
+	if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) {
+		update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
+		writel(((update_value & 0xFF) >> 5),
+		       &socfpga_ecc_hmc_base->ddrioctrl);
+	}
+
+	ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
+
+	/* Set the DDR Configuration [0xFFD12400] */
+	io48_value = ARRIA_DDR_CONFIG(ctrlcfg1.cfg_addr_order,
+				      (dramaddrw.cfg_bank_addr_width +
+				      dramaddrw.cfg_bank_group_addr_width),
+				      dramaddrw.cfg_col_addr_width,
+				      dramaddrw.cfg_row_addr_width);
+
+	update_value = match_ddr_conf(io48_value);
+	if (update_value)
+		writel(update_value,
+		&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf);
+
+	/*
+	 * Configure DDR timing [0xFFD1240C]
+	 *  RDTOMISS = tRTP + tRP + tRCD - BL/2
+	 *  WRTOMISS = WL + tWR + tRP + tRCD and
+	 *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
+	 *  First part of equation is in memory clock units so divide by 2
+	 *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
+	 *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
+	 */
+	update_value = (caltim2.cfg_rd_to_pch +  caltim4.cfg_pch_to_valid +
+			caltim0.cfg_act_to_rdwr -
+			(ctrlcfg0.cfg_ctrl_burst_len >> 2));
+	io48_value = ((((socfpga_io48_mmr_base->dramtiming0 &
+		      ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
+		      (ctrlcfg0.cfg_ctrl_burst_len >> 1)) >> 1) -
+		      /* Up to here was in memory cycles so divide by 2 */
+		      caltim1.cfg_rd_to_wr + caltim0.cfg_act_to_rdwr +
+		      caltim4.cfg_pch_to_valid);
+
+	writel(((caltim0.cfg_act_to_act <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
+		(update_value <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
+		(io48_value <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
+		((ctrlcfg0.cfg_ctrl_burst_len >> 2) <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
+		(caltim1.cfg_rd_to_wr <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
+		(caltim3.cfg_wr_to_rd <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
+		(((ddrioctl == 1) ? 1 : 0) <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
+		&socfpga_noc_ddr_scheduler_base->
+			ddr_t_main_scheduler_ddrtiming);
+
+	/* Configure DDR mode [0xFFD12410] [precharge = 0] */
+	writel(((ddrioctl ? 0 : 1) <<
+		ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
+		&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
+
+	/* Configure the read latency [0xFFD12414] */
+	writel(((socfpga_io48_mmr_base->dramtiming0 &
+		ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
+		DDR_READ_LATENCY_DELAY,
+		&socfpga_noc_ddr_scheduler_base->
+			ddr_t_main_scheduler_readlatency);
+
+	/*
+	 * Configuring timing values concerning activate commands
+	 * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
+	 */
+	writel(((caltim0.cfg_act_to_act_db <<
+			ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
+		(caltim9.cfg_4_act_to_act <<
+			ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
+		(ARRIA10_SDR_ACTIVATE_FAWBANK <<
+			ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
+		&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate);
+
+	/*
+	 * Configuring timing values concerning device to device data bus
+	 * ownership change [0xFFD1243C]
+	 */
+	writel(((caltim1.cfg_rd_to_rd_dc <<
+			ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
+		(caltim1.cfg_rd_to_wr_dc <<
+			ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
+		(caltim3.cfg_wr_to_rd_dc <<
+			ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
+		&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev);
+
+	/* Enable or disable the SDRAM ECC */
+	if (ctrlcfg1.cfg_ctrl_enable_ecc) {
+		setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+			     (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
+		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+			     (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
+		setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
+			     (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
+	} else {
+		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+			     (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
+		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
+			     (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
+	}
+}
+
+struct firewall_entry {
+	const char *prop_name;
+	const u32 cfg_addr;
+	const u32 en_addr;
+	const u32 en_bit;
+};
+#define FW_MPU_FPGA_ADDRESS \
+	((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
+	SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
+const struct firewall_entry firewall_table[] = {
+	{
+		"altr,mpu0",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+		offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+			 mpuregion0addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+		offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+			 enable),
+		ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
+	},
+	{
+		"altr,mpu1",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+		offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+			 mpuregion1addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+		offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+			 enable),
+		ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
+	},
+	{
+		"altr,mpu2",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+		offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+			 mpuregion2addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+		offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+			 enable),
+		ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK
+	},
+	{
+		"altr,mpu3",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+		offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+			 mpuregion3addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+		offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+			 enable),
+		ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK
+	},
+	{
+		"altr,l3-0",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_l3, hpsregion0addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_l3, enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK
+	},
+	{
+		"altr,l3-1",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_l3, hpsregion1addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_l3, enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK
+	},
+	{
+		"altr,l3-2",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_l3, hpsregion2addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_l3, enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK
+	},
+	{
+		"altr,l3-3",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_l3, hpsregion3addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_l3, enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK
+	},
+	{
+		"altr,l3-4",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_l3, hpsregion4addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_l3, enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK
+	},
+	{
+		"altr,l3-5",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_l3, hpsregion5addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_l3, enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK
+	},
+	{
+		"altr,l3-6",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_l3, hpsregion6addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_l3, enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK
+	},
+	{
+		"altr,l3-7",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_l3, hpsregion7addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_l3, enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram0-0",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 fpga2sdram0region0addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram0-1",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 fpga2sdram0region1addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram0-2",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 fpga2sdram0region2addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram0-3",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 fpga2sdram0region3addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram1-0",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 fpga2sdram1region0addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram1-1",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 fpga2sdram1region1addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram1-2",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 fpga2sdram1region2addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram1-3",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 fpga2sdram1region3addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK
+	},	{
+		"altr,fpga2sdram2-0",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 fpga2sdram2region0addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram2-1",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 fpga2sdram2region1addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram2-2",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 fpga2sdram2region2addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram2-3",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 fpga2sdram2region3addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+			offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
+				 enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK
+	},
+
+};
+
+static int of_sdram_firewall_setup(const void *blob)
+{
+	int child, i, node;
+	u32 start_end[2];
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC);
+	if (node < 0)
+		return 2;
+
+	child = fdt_first_subnode(blob, node);
+	if (child < 0)
+		return 1;
+
+	/* set to default state */
+	writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
+	writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
+
+
+	for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
+		if (!fdtdec_get_int_array(blob, child,
+					  firewall_table[i].prop_name,
+					  start_end, 2)) {
+			writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) |
+				(start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB),
+				 firewall_table[i].cfg_addr);
+			setbits_le32(firewall_table[i].en_addr,
+				     firewall_table[i].en_bit);
+		}
+	}
+
+	return 0;
+}
+
+int ddr_calibration_sequence(void)
+{
+	WATCHDOG_RESET();
+
+	/* Check to see if SDRAM cal was success */
+	if (sdram_startup()) {
+		puts("DDRCAL: Failed\n");
+		return -1;
+	}
+
+	puts("DDRCAL: Success\n");
+
+	WATCHDOG_RESET();
+
+	/* initialize the MMR register */
+	sdram_mmr_init();
+
+	/* assigning the SDRAM size */
+	unsigned long long size = sdram_size_calc();
+
+	/* If a weird value, use default Config size */
+	/* Up to 2GB is supported, 2GB would be used if more than that */
+	if (size <= 0)
+		gd->ram_size = PHYS_SDRAM_1_SIZE;
+	else if (DDR_SIZE_2GB_HEX <= size)
+		gd->ram_size = DDR_SIZE_2GB_HEX;
+	else
+		gd->ram_size = (u32)size;
+
+	/* setup the dram info within bd */
+	dram_init_banksize();
+
+	if (of_sdram_firewall_setup(gd->fdt_blob))
+		puts("FW: Error Configuring Firewall\n");
+
+	return 0;
+}
+
+void dram_bank_mmu_setup(int bank)
+{
+	bd_t *bd = gd->bd;
+	int	i;
+
+	debug("%s: bank: %d\n", __func__, bank);
+	for (i = bd->bi_dram[bank].start >> 20;
+	     i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
+	     i++) {
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+		set_section_dcache(i, DCACHE_WRITETHROUGH);
+#else
+		set_section_dcache(i, DCACHE_WRITEBACK);
+#endif
+	}
+
+	/* same as above but just that we would want cacheable for ocram too */
+	i = CONFIG_SYS_INIT_RAM_ADDR >> 20;
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+	set_section_dcache(i, DCACHE_WRITETHROUGH);
+#else
+	set_section_dcache(i, DCACHE_WRITEBACK);
+#endif
+}
-- 
2.2.0

[U-Boot] [PATCH v2 13/19] configs: Add DDR Kconfig support for Arria 10

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

This patch enables DDR Kconfig support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/Kconfig | 1 +
 drivers/ddr/altera/Kconfig    | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 45e5379..3e7a68a 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -40,6 +40,7 @@ config TARGET_SOCFPGA_ARRIA5
 config TARGET_SOCFPGA_ARRIA10
 	bool
 	select SPL_BOARD_INIT if SPL
+	select ALTERA_SDRAM
 
 config TARGET_SOCFPGA_CYCLONE5
 	bool
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
index 021ec1d..2b28a97 100644
--- a/drivers/ddr/altera/Kconfig
+++ b/drivers/ddr/altera/Kconfig
@@ -1,5 +1,5 @@
 config ALTERA_SDRAM
 	bool "SoCFPGA DDR SDRAM driver"
-	depends on TARGET_SOCFPGA_GEN5
+	depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	help
 	  Enable DDR SDRAM controller for the SoCFPGA devices.
-- 
2.2.0

[U-Boot] [PATCH v2 14/19] arm: socfpga: Enable build for DDR Arria 10

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

This patch is for enabling the DDR support on Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 drivers/ddr/altera/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index ac4ab85..02f8b7c 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -10,4 +10,5 @@
 
 ifdef CONFIG_ALTERA_SDRAM
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
 endif
-- 
2.2.0

[U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory allocation in SPL

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Add support to memory allocation in SPL for preparation to enable FAT
in SPL. Memory allocation is needed by FAT to work properly.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 include/configs/socfpga_common.h | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 7549ee8..9b6719e 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -280,17 +280,34 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /*
  * SPL
  *
- * SRAM Memory layout:
+ * SRAM Memory layout for gen 5:
  *
  * 0xFFFF_0000 ...... Start of SRAM
  * 0xFFFF_xxxx ...... Top of stack (grows down)
  * 0xFFFF_yyyy ...... Malloc area
  * 0xFFFF_zzzz ...... Global Data
  * 0xFFFF_FF00 ...... End of SRAM
+ *
+ * SRAM Memory layout for Arria 10:
+ * 0xFFE0_0000 ...... Start of SRAM (bottom)
+ * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
+ * 0xFFEy_yyyy ...... Malloc area (grows up to top)
+ * 0xFFEz_zzzz ...... Global Data
+ * 0xFFE3_FFFF ...... End of SRAM (top)
  */
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
 #define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+/* SPL memory allocation configuration, it is required by FAT feature */
+#ifndef CONFIG_SYS_SPL_MALLOC_START
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00002000
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE - \
+					 CONFIG_SYS_SPL_MALLOC_SIZE + \
+					 CONFIG_SYS_INIT_RAM_ADDR)
+#endif
+#endif
 
 /* SPL SDMMC boot support */
 #ifdef CONFIG_SPL_MMC_SUPPORT
@@ -320,7 +337,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /*
  * Stack setup
  */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SPL_STACK		(CONFIG_SYS_SPL_MALLOC_START - 1)
+#endif
 
 /* Extra Environment */
 #ifndef CONFIG_SPL_BUILD
-- 
2.2.0

[U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Enhance preloader header with both additional program length and program
entry offset attributes, which offset is relative to the start of program
header.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/include/mach/boot0.h | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h
index 22d9e7f..33c9368 100644
--- a/arch/arm/mach-socfpga/include/mach/boot0.h
+++ b/arch/arm/mach-socfpga/include/mach/boot0.h
@@ -11,8 +11,15 @@
 	.balignl 64,0xf33db33f;
 
 	.word	0x1337c0d3;	/* SoCFPGA preloader validation word */
-	.word	0xc01df00d;	/* Version, flags, length */
-	.word	0xcafec0d3;	/* Checksum, zero-pad */
+	.word	0xc01df00d; /* Header length(2B),flags(1B),version(1B) */
+#ifndef CONFIG_TARGET_SOCFPGA_GEN5
+	.word	0xfeedface; /* Program length(4B) */
+	.word	0xf00dcafe; /*
+			     * Program entry offset(4B),relative to
+			     * the start of program header
+			     */
+#endif
+	.word	0xcafec0d3;	/* Simple checksum(2B),spare offset(2B) */
 	nop;
 
 	b reset;		/* SoCFPGA jumps here */
-- 
2.2.0

[U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency info for U-boot

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Clock frequency info is required in U-boot.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/board.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 965f9dc..a00f63b 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -8,7 +8,10 @@
 
 #include <common.h>
 #include <errno.h>
+#include <fdtdec.h>
 #include <asm/arch/reset_manager.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/misc.h>
 #include <asm/io.h>
 
 #include <usb.h>
@@ -26,6 +29,9 @@ int board_init(void)
 	/* Address of boot parameters for ATAG (if ATAG is used) */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
+	/* configuring the clock based on handoff */
+	cm_basic_init(gd->fdt_blob);
+
 	return 0;
 }
 
-- 
2.2.0

[U-Boot] [PATCH v2 18/19] arm: socfpga: Adding SoCFPGA info for both SPL and U-boot

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

SoC FPGA info is required in both SPL and U-boot.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/board.c        | 3 +++
 arch/arm/mach-socfpga/misc_arria10.c | 5 -----
 arch/arm/mach-socfpga/spl.c          | 6 ++++++
 3 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index a00f63b..0fbad67 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -32,6 +32,9 @@ int board_init(void)
 	/* configuring the clock based on handoff */
 	cm_basic_init(gd->fdt_blob);
 
+	/* Add device descriptor to FPGA device table */
+	socfpga_fpga_add();
+
 	return 0;
 }
 
diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index 9d751f6..8760ac9 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -94,11 +94,6 @@ int arch_early_init_r(void)
 	/* assert reset to all except L4WD0 and L4TIMER0 */
 	socfpga_per_reset_all();
 
-	/* configuring the clock based on handoff */
-	/* TODO: Add call to cm_basic_init() */
-
-	/* Add device descriptor to FPGA device table */
-	socfpga_fpga_add();
 	return 0;
 }
 #else
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 71bae82..aba116d 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -15,6 +15,7 @@
 #include <asm/arch/system_manager.h>
 #include <asm/arch/freeze_controller.h>
 #include <asm/arch/clock_manager.h>
+#include <asm/arch/misc.h>
 #include <asm/arch/scan_manager.h>
 #include <asm/arch/sdram.h>
 #include <asm/arch/scu.h>
@@ -208,6 +209,11 @@ void spl_board_init(void)
 
 	/* enable console uart printing */
 	preloader_console_init();
+
+	WATCHDOG_RESET();
+
+	/* Add device descriptor to FPGA device table */
+	socfpga_fpga_add();
 }
 
 void board_init_f(ulong dummy)
-- 
2.2.0

[U-Boot] [PATCH v2 19/19] arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Enable SPL loading U-boot from SDMMC to DDR and booting U-boot.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/spl.c       | 55 +++++++++++++++++++++++++++++++++++++
 common/spl/spl_mmc.c              |  2 +-
 configs/socfpga_arria10_defconfig | 57 ++++++++++++++++++++++++++++++++++-----
 include/spl.h                     |  2 ++
 4 files changed, 108 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index aba116d..9b381bb 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -15,6 +15,7 @@
 #include <asm/arch/system_manager.h>
 #include <asm/arch/freeze_controller.h>
 #include <asm/arch/clock_manager.h>
+#include <asm/arch/fpga_manager.h>
 #include <asm/arch/misc.h>
 #include <asm/arch/scan_manager.h>
 #include <asm/arch/sdram.h>
@@ -22,6 +23,10 @@
 #include <asm/arch/nic301.h>
 #include <asm/sections.h>
 #include <fdtdec.h>
+#include <fat.h>
+#include <fs.h>
+#include <linux/ctype.h>
+#include <mmc.h>
 #include <watchdog.h>
 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #include <asm/arch/pinmux.h>
@@ -29,6 +34,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define BSIZE	4096
+#define PERIPH_RBF	0
+
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
@@ -197,6 +205,12 @@ void board_init_f(ulong dummy)
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 void spl_board_init(void)
 {
+	int rval = 0;
+	int len = 0;
+	u32 buffer[BSIZE] __aligned(ARCH_DMA_MINALIGN);
+	struct spl_boot_device bootdev;
+	fpga_fs_info fpga_fsinfo;
+
 	/* configuring the clock based on handoff */
 	cm_basic_init(gd->fdt_blob);
 	WATCHDOG_RESET();
@@ -214,6 +228,47 @@ void spl_board_init(void)
 
 	/* Add device descriptor to FPGA device table */
 	socfpga_fpga_add();
+
+	bootdev.boot_device = spl_boot_device();
+
+	if (BOOT_DEVICE_MMC1 == bootdev.boot_device) {
+		struct mmc *mmc = NULL;
+		int err = 0;
+
+		spl_mmc_find_device(&mmc, bootdev.boot_device);
+
+		err = mmc_init(mmc);
+
+		if (err) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+			printf("spl: mmc init failed with error: %d\n", err);
+#endif
+		}
+
+		fpga_fsinfo.dev_part = (char *)get_cff_devpart(gd->fdt_blob,
+								 &len);
+
+		fpga_fsinfo.filename = (char *)get_cff_filename(gd->fdt_blob,
+								 &len,
+								PERIPH_RBF);
+
+		fpga_fsinfo.interface = "mmc";
+
+		fpga_fsinfo.fstype = FS_TYPE_FAT;
+	} else {
+		printf("Invalid boot device!\n");
+		return;
+	}
+
+	/* Program peripheral RBF */
+	if (fpga_fsinfo.filename && fpga_fsinfo.dev_part && (len > 0))
+		rval = fpga_fsload(0, buffer, BSIZE, &fpga_fsinfo);
+
+	if (rval > 0) {
+		config_pins(gd->fdt_blob, "shared");
+
+		ddr_calibration_sequence();
+	}
 }
 
 void board_init_f(ulong dummy)
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index b2cccc6..159443f 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -113,7 +113,7 @@ static int spl_mmc_get_device_index(u32 boot_device)
 	return -ENODEV;
 }
 
-static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
+int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
 {
 #if CONFIG_IS_ENABLED(DM_MMC)
 	struct udevice *dev;
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index 4c73d73..2ff9801 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -2,33 +2,76 @@ CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
 CONFIG_IDENT_STRING="socfpga_arria10"
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200"
 CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
+CONFIG_FIT=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SPL_FPGA_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=32768
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_CMD_PART=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
 CONFIG_DOS_PARTITION=y
-# CONFIG_SPL_DOS_PARTITION is not set
-CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SPL_DOS_PARTITION=y
+CONFIG_SPL_FS_GENERIC=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
 CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_TINY_PRINTF=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="altera"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
diff --git a/include/spl.h b/include/spl.h
index ce4cf0a..e24433d 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -10,6 +10,7 @@
 /* Platform-specific defines */
 #include <linux/compiler.h>
 #include <asm/spl.h>
+#include <mmc.h>
 
 /* Value in r0 indicates we booted from U-Boot */
 #define UBOOT_NOT_LOADED_FROM_SPL	0x13578642
@@ -68,6 +69,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
 void preloader_console_init(void);
 u32 spl_boot_device(void);
 u32 spl_boot_mode(const u32 boot_device);
+int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device);
 
 /**
  * spl_set_header_raw_uboot() - Set up a standard SPL image structure
-- 
2.2.0

[U-Boot] [PATCH v2 01/19] ARM: socfpga: add bindings doc for arria10 fpga manager

[Marek Vasut]

On 09/25/2017 10:39 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> This DT binding doc is porting from Linux DT binding doc.
> commit 1adcbea4201a6852362aa5ece573f1f169b28113
> 
> Add a device tree bindings document for the SoCFPGA Arria10
> FPGA Manager driver.
> 
> Signed-off-by: Alan Tull <atull@opensource.altera.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Acked-By: Moritz Fischer <moritz.fischer@ettus.com>
> Signed-off-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

Applied, thanks

> ---
>  .../fpga/altera-socfpga-a10-fpga-mgr.txt              | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>  create mode 100644 doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> 
> diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> new file mode 100644
> index 0000000..2fd8e7a
> --- /dev/null
> +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> @@ -0,0 +1,19 @@
> +Altera SOCFPGA Arria10 FPGA Manager
> +
> +Required properties:
> +- compatible : should contain "altr,socfpga-a10-fpga-mgr"
> +- reg        : base address and size for memory mapped io.
> +               - The first index is for FPGA manager register access.
> +               - The second index is for writing FPGA configuration data.
> +- resets     : Phandle and reset specifier for the device's reset.
> +- clocks     : Clocks used by the device.
> +
> +Example:
> +
> +	fpga_mgr: fpga-mgr at ffd03000 {
> +		compatible = "altr,socfpga-a10-fpga-mgr";
> +		reg = <0xffd03000 0x100
> +		       0xffcfe400 0x20>;
> +		clocks = <&l4_mp_clk>;
> +		resets = <&rst FPGAMGR_RESET>;
> +	};
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA RBF properties at Arria 10 FPGA manager

[Marek Vasut]

On 09/25/2017 10:39 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> This patch adds description on properties about location of FPGA RBFs are
> stored, type and functionality of RBF used to configure FPGA.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

Why does this patch have different tags than 1/19 ? Please keep things
consistent ...

> ---
>  doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> index 2fd8e7a..7abb746 100644
> --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> @@ -7,6 +7,14 @@ Required properties:
>                 - The second index is for writing FPGA configuration data.
>  - resets     : Phandle and reset specifier for the device's reset.
>  - clocks     : Clocks used by the device.
> +- bitstream_periph : FPGA peripheral raw binary file which is used to
> +                     initialize FPGA IOs, PLL, IO48 and DDR.
> +- bitstream_core : FPGA core raw binary file contains FPGA design which is used
> +                   to program FPGA CRAM and ERAM.
> +- bitstream_devpart : Partition of flash device where bitstream files are
> +		       stored.
> +                      <dev[:part]> - dev is flash device number, part is flash
> +                                     device partition.
>  
>  Example:
>  
> @@ -16,4 +24,7 @@ Example:
>  		       0xffcfe400 0x20>;
>  		clocks = <&l4_mp_clk>;
>  		resets = <&rst FPGAMGR_RESET>;
> +		bitstream_periph = "ghrd_10as066n2.periph.rbf.mkimage";
> +		bitstream_core = "ghrd_10as066n2.core.rbf.mkimage";
> +		bitstream_devpart = "0:1";
>  	};
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA RBF properties at Arria 10 FPGA manager

[Marek Vasut]

On 09/25/2017 10:39 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> This patch adds description on properties about location of FPGA RBFs are
> stored, type and functionality of RBF used to configure FPGA.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> index 2fd8e7a..7abb746 100644
> --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> @@ -7,6 +7,14 @@ Required properties:
>                 - The second index is for writing FPGA configuration data.
>  - resets     : Phandle and reset specifier for the device's reset.
>  - clocks     : Clocks used by the device.
> +- bitstream_periph : FPGA peripheral raw binary file which is used to
> +                     initialize FPGA IOs, PLL, IO48 and DDR.
> +- bitstream_core : FPGA core raw binary file contains FPGA design which is used
> +                   to program FPGA CRAM and ERAM.
> +- bitstream_devpart : Partition of flash device where bitstream files are
> +		       stored.
> +                      <dev[:part]> - dev is flash device number, part is flash
> +                                     device partition.
>  
>  Example:
>  
> @@ -16,4 +24,7 @@ Example:
>  		       0xffcfe400 0x20>;
>  		clocks = <&l4_mp_clk>;
>  		resets = <&rst FPGAMGR_RESET>;
> +		bitstream_periph = "ghrd_10as066n2.periph.rbf.mkimage";
> +		bitstream_core = "ghrd_10as066n2.core.rbf.mkimage";
> +		bitstream_devpart = "0:1";

These should probably be altr,something-something ... they are
definitely not generic bindings

>  	};
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 04/19] arm: socfpga: Add Arria 10 SoCFPGA programming interface

[Marek Vasut]

On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Add code necessary into the FPGA driver framework in U-Boot
> so it can be used via the 'fpga' command for programing Arria 10
> SoCFPGA.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---

[...]

> +#if defined(CONFIG_CMD_FPGA_LOADFS)
> +int altera_loadfs(Altera_desc *desc, const void *buf, size_t bsize,
> +		   fpga_fs_info *fpga_fsinfo)
> +{
> +	const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
> +
> +	if (!fpga)
> +		return FPGA_FAIL;
> +
> +	debug_cond(FPGA_DEBUG, "%s: Launching the %s FS Loader...\n",
> +		   __func__, fpga->name);
> +	if (fpga->loadfs)
> +		return fpga->loadfs(desc, buf, bsize, fpga_fsinfo);
> +	return 0;

return -EINVAL , since the loader could not be started ?

> +}
> +#endif
[...]

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 05/19] arm: socfpga: Enhance FPGA program write rbf data with size >= 4 bytes

[Marek Vasut]

On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Existing FPGA program write is always assume RBF data >= 32 bytes, so
> any rbf data less than 32 bytes writing to FPGA would be failed.
> This patch enhances the FPGA program write to support rbf data with
> size >= 4 bytes.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

Applied, thanks

> ---
>  drivers/fpga/socfpga.c | 14 ++++++++------
>  1 file changed, 8 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
> index 28fa16b..6e14ebd 100644
> --- a/drivers/fpga/socfpga.c
> +++ b/drivers/fpga/socfpga.c
> @@ -1,5 +1,5 @@
>  /*
> - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
>   * All rights reserved.
>   *
>   * SPDX-License-Identifier:	BSD-3-Clause
> @@ -55,18 +55,20 @@ void fpgamgr_program_write(const void *rbf_data, size_t rbf_size)
>  	uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
>  
>  	asm volatile(
> +		"	cmp	%2,	#0\n"
> +		"	beq	2f\n"
>  		"1:	ldmia	%0!,	{r0-r7}\n"
>  		"	stmia	%1!,	{r0-r7}\n"
>  		"	sub	%1,	#32\n"
>  		"	subs	%2,	#1\n"
>  		"	bne	1b\n"
> -		"	cmp	%3,	#0\n"
> -		"	beq	3f\n"
> -		"2:	ldr	%2,	[%0],	#4\n"
> +		"2:	cmp	%3,	#0\n"
> +		"	beq	4f\n"
> +		"3:	ldr	%2,	[%0],	#4\n"
>  		"	str	%2,	[%1]\n"
>  		"	subs	%3,	#1\n"
> -		"	bne	2b\n"
> -		"3:	nop\n"
> +		"	bne	3b\n"
> +		"4:	nop\n"
>  		: "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
>  		: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
>  }
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 07/19] fdt: Add compatible strings for Arria 10

[Marek Vasut]

On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Add compatible strings for Intel Arria 10 SoCFPGA device.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

Applied, thanks

> ---
>  include/fdtdec.h | 2 ++
>  lib/fdtdec.c     | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/include/fdtdec.h b/include/fdtdec.h
> index 4a0947c..095ff36 100644
> --- a/include/fdtdec.h
> +++ b/include/fdtdec.h
> @@ -157,6 +157,8 @@ enum fdt_compat_id {
>  	COMPAT_ALTERA_SOCFPGA_F2SDR0,           /* SoCFPGA fpga2SDRAM0 bridge */
>  	COMPAT_ALTERA_SOCFPGA_F2SDR1,           /* SoCFPGA fpga2SDRAM1 bridge */
>  	COMPAT_ALTERA_SOCFPGA_F2SDR2,           /* SoCFPGA fpga2SDRAM2 bridge */
> +	COMPAT_ALTERA_SOCFPGA_FPGA0,		/* SOCFPGA FPGA manager */
> +	COMPAT_ALTERA_SOCFPGA_NOC,		/* SOCFPGA Arria 10 NOC */
>  
>  	COMPAT_COUNT,
>  };
> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
> index 107a892..03ff75e 100644
> --- a/lib/fdtdec.c
> +++ b/lib/fdtdec.c
> @@ -70,6 +70,8 @@ static const char * const compat_names[COMPAT_COUNT] = {
>  	COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
>  	COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
>  	COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
> +	COMPAT(ALTERA_SOCFPGA_FPGA0, "altr,socfpga-a10-fpga-mgr"),
> +	COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"),
>  };
>  
>  const char *fdtdec_get_compatible(enum fdt_compat_id id)
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 08/19] fs: Enable generic filesystems interface support in SPL.

[Marek Vasut]

On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Enable generic filesystem interface drivers(fs.c and fat/) build
> for SPL. This would allow generic filesystem being used in SPL.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

+CC Simon, I'd like a RB on this one.

> ---
>  common/spl/Kconfig | 8 ++++++++
>  doc/README.SPL     | 1 +
>  fs/Makefile        | 1 +
>  3 files changed, 10 insertions(+)
> 
> diff --git a/common/spl/Kconfig b/common/spl/Kconfig
> index 9446cd9..5f4bd92 100644
> --- a/common/spl/Kconfig
> +++ b/common/spl/Kconfig
> @@ -304,6 +304,14 @@ config SPL_ETH_SUPPORT
>  	  is required since the network stack uses a number of environment
>  	  variables. See also SPL_NET_SUPPORT.
>  
> +config SPL_FS_GENERIC
> +	bool "Support Generic filesystems interface driver"
> +	help
> +	  Enable support for generic filesystems interface with SPL. This
> +	  permits U-Boot (or Linux in Falcon mode) to be loaded from a generic
> +	  filesystem from within SPL. Support for the underlying block
> +	  device (e.g. MMC or USB) must be enabled separately.
> +
>  config SPL_EXT_SUPPORT
>  	bool "Support EXT filesystems"
>  	help
> diff --git a/doc/README.SPL b/doc/README.SPL
> index 3ba313c..32628a4 100644
> --- a/doc/README.SPL
> +++ b/doc/README.SPL
> @@ -55,6 +55,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT (drivers/mtd/spi/libspi_flash.o)
>  CONFIG_SPL_SPI_SUPPORT (drivers/spi/libspi.o)
>  CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o)
>  CONFIG_SPL_EXT_SUPPORT
> +CONFIG_SPL_FS_GENERIC (fs/fs.o fat/)
>  CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
>  CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o)
>  CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
> diff --git a/fs/Makefile b/fs/Makefile
> index 5770f41..fdacac8 100644
> --- a/fs/Makefile
> +++ b/fs/Makefile
> @@ -7,6 +7,7 @@
>  #
>  
>  ifdef CONFIG_SPL_BUILD
> +obj-$(CONFIG_SPL_FS_GENERIC) += fs.o fat/
>  obj-$(CONFIG_SPL_FAT_SUPPORT) += fat/
>  obj-$(CONFIG_SPL_EXT_SUPPORT) += ext4/
>  else
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA from flash

[Marek Vasut]

On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> These drivers handle FPGA program operation from flash loading
> RBF to memory and then to program FPGA.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

Did you run checkpatch on this before submitting ? I presume no ...

> ---
>  .../include/mach/fpga_manager_arria10.h            |  27 ++
>  drivers/fpga/socfpga_arria10.c                     | 391 ++++++++++++++++++++-
>  include/altera.h                                   |   6 +
>  include/configs/socfpga_common.h                   |   4 +
>  4 files changed, 425 insertions(+), 3 deletions(-)
[...]

> @@ -112,13 +122,14 @@ static int wait_for_nconfig_pin_and_nstatus_pin(void)
>  	unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
>  				ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
>  
> -	/* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,
> -	 * timeout at 1000ms
> +	/*
> +	 * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
> +	 * de-asserted, timeout at 1000ms
>  	 */
>  	return wait_for_bit(__func__,
>  			    &fpga_manager_base->imgcfg_stat,
>  			    mask,
> -			    false, FPGA_TIMEOUT_MSEC, false);
> +			    true, FPGA_TIMEOUT_MSEC, false);
>  }

Seems more like a fix, split this out.

>  static int wait_for_f2s_nstatus_pin(unsigned long value)
> @@ -469,6 +480,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
>  
>  	/* Initialize the FPGA Manager */
>  	status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
> +
>  	if (status)
>  		return status;
>  
> @@ -477,3 +489,376 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
>  
>  	return fpgamgr_program_finish();
>  }
> +
> +#if defined(CONFIG_CMD_FPGA_LOADFS)
> +const char *get_cff_filename(const void *fdt, int *len, u32 core)
> +{
> +	const char *cff_filename = NULL;
> +	const char *cell;
> +	int nodeoffset;
> +	nodeoffset = fdtdec_next_compatible(fdt, 0,
> +			 COMPAT_ALTERA_SOCFPGA_FPGA0);
> +
> +	if (nodeoffset >= 0) {
> +		if (core)
> +			cell = fdt_getprop(fdt,
> +					nodeoffset,
> +					"bitstream_core",
> +					len);
> +		else
> +			cell = fdt_getprop(fdt, nodeoffset, "bitstream_periph",
> +					 len);
> +
> +		if (cell)
> +			cff_filename = cell;
> +	}
> +
> +	return cff_filename;
> +}
> +
> +const char *get_cff_devpart(const void *fdt, int *len)
> +{
> +	const char *cff_devpart = NULL;
> +	const char *cell;
> +	int nodeoffset;
> +	nodeoffset = fdtdec_next_compatible(fdt, 0,
> +			 COMPAT_ALTERA_SOCFPGA_FPGA0);
> +
> +	cell = fdt_getprop(fdt, nodeoffset, "bitstream_devpart", len);
> +
> +	if (cell)
> +		cff_devpart = cell;
> +
> +	return cff_devpart;
> +}

Take a look at splash*.c , I believe that can be reworked into generic
firmware loader , which you could then use here.

[...]

> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index 9897e11..eadce2d 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -27,7 +27,11 @@
>   */
>  #define CONFIG_NR_DRAM_BANKS		1
>  #define PHYS_SDRAM_1			0x0
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  #define CONFIG_SYS_MALLOC_LEN		(64 * 1024 * 1024)
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#define CONFIG_SYS_MALLOC_LEN		(128 * 1024 * 1024)
> +#endif

You definitely don't need 128 MiB of malloc area.

>  #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
>  #define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 10/19] arm: socfpga: Rename the gen5 sdram driver to more specific name

[Marek Vasut]

On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Current sdram driver is only applied to gen5 device, hence it is better
> to rename sdram driver to more specific name which is related to gen5
> device.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  arch/arm/mach-socfpga/include/mach/sdram.h         | 434 +--------------------
>  .../include/mach/{sdram.h => sdram_gen5.h}         |   6 +-
>  drivers/ddr/altera/Makefile                        |   2 +-
>  drivers/ddr/altera/{sdram.c => sdram_gen5.c}       |   0
>  4 files changed, 8 insertions(+), 434 deletions(-)
>  copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h} (99%)
>  rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
> index b11228f..4a9754e 100644
> --- a/arch/arm/mach-socfpga/include/mach/sdram.h
> +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
> @@ -1,5 +1,5 @@
>  /*
> - * Copyright Altera Corporation (C) 2014-2015
> + * Copyright (C) 2017 Intel Corporation <www.intel.com>

Retain the old copyright ?

>   *
>   * SPDX-License-Identifier:	GPL-2.0+
>   */
> @@ -8,435 +8,9 @@
>  
>  #ifndef __ASSEMBLY__

What's with this massive deletion here ?

> -unsigned long sdram_calculate_size(void);
> -int sdram_mmr_init_full(unsigned int sdr_phy_reg);
> -int sdram_calibration_full(void);
> -
> -const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
> -
> -void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
> -void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
> -const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
[...]

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size initialization function

[Marek Vasut]

On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Add function for both multiple DRAM bank and single DRAM bank size
> initialization. This common functionality could be used by every single
> SOCFPGA board.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

I'd like TB on Gen5.

> ---
>  arch/arm/mach-socfpga/board.c    | 7 +++++++
>  include/configs/socfpga_common.h | 1 +
>  2 files changed, 8 insertions(+)
> 
> diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
> index a41d089..965f9dc 100644
> --- a/arch/arm/mach-socfpga/board.c
> +++ b/arch/arm/mach-socfpga/board.c
> @@ -29,6 +29,13 @@ int board_init(void)
>  	return 0;
>  }
>  
> +int dram_init_banksize(void)
> +{
> +	fdtdec_setup_memory_banksize();
> +
> +	return 0;
> +}
> +
>  #ifdef CONFIG_USB_GADGET
>  struct dwc2_plat_otg_data socfpga_otg_data = {
>  	.usb_gusbcfg	= 0x1417,
> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index eadce2d..7549ee8 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -47,6 +47,7 @@
>  	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
>  
>  #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
> +#define CONFIG_SYS_SDRAM_SIZE		PHYS_SDRAM_1_SIZE
>  #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
>  #define CONFIG_SYS_TEXT_BASE		0x08000040
>  #else
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for Arria 10

[Marek Vasut]

On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Add DDR driver suppport for Arria 10.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  arch/arm/mach-socfpga/include/mach/sdram.h         |   2 +
>  arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-
>  drivers/ddr/altera/sdram_arria10.c                 | 735 +++++++++++++++++++++
>  3 files changed, 839 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/ddr/altera/sdram_arria10.c
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
> index 4a9754e..b833fc2 100644
> --- a/arch/arm/mach-socfpga/include/mach/sdram.h
> +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
> @@ -10,6 +10,8 @@
>  
>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  #include <asm/arch/sdram_gen5.h>
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#include <asm/arch/sdram_arria10.h>
>  #endif
>  
>  #endif
> diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> index 1d7b7c1..7af9431 100644
> --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> @@ -1,5 +1,5 @@
>  /*
> - * Copyright (C) 2015-2017 Intel Corporation <www.intel.com>
> + * Copyright (C) 2017 Intel Corporation <www.intel.com>
>   *
>   * SPDX-License-Identifier:	GPL-2.0
>   */
> @@ -8,6 +8,7 @@
>  #define _SOCFPGA_SDRAM_ARRIA10_H_
>  
>  #ifndef __ASSEMBLY__
> +int ddr_calibration_sequence(void);
>  
>  struct socfpga_ecc_hmc {
>  	u32 ip_rev_id;
> @@ -204,6 +205,106 @@ struct socfpga_io48_mmr {
>  	u32 niosreserve1;
>  	u32 niosreserve2;
>  };
> +
> +union dramaddrw_reg {
> +	struct {
> +		u32 cfg_col_addr_width:5;
> +		u32 cfg_row_addr_width:5;
> +		u32 cfg_bank_addr_width:4;
> +		u32 cfg_bank_group_addr_width:2;
> +		u32 cfg_cs_addr_width:3;
> +		u32 reserved:13;
> +	};

Use regular macros for bitfields, not this crap.

> +	u32 word;
> +};
> +
> +union ctrlcfg0_reg {
> +	struct {
> +		u32 cfg_mem_type:4;
> +		u32 cfg_dimm_type:3;
> +		u32 cfg_ac_pos:2;
> +		u32 cfg_ctrl_burst_len:5;
> +		u32 reserved:18;  /* Other fields unused */
> +	};
> +	u32 word;
> +};

[...]

> diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c
> new file mode 100644
> index 0000000..f22a726
> --- /dev/null
> +++ b/drivers/ddr/altera/sdram_arria10.c
> @@ -0,0 +1,735 @@
> +/*
> + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <fdtdec.h>
> +#include <malloc.h>
> +#include <mmc.h>
> +#include <nand.h>
> +#include <watchdog.h>
> +#include <ns16550.h>

Why does an SDRAM init driver need access to ns16550 UART , MMC and NAND ?

> +#include <asm/io.h>
> +#include <asm/arch/fpga_manager.h>
> +#include <asm/arch/misc.h>
> +#include <asm/arch/reset_manager.h>
> +#include <asm/arch/sdram.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static void sdram_mmr_init(void);
> +static unsigned long long sdram_size_calc(void);
> +
> +/* FAWBANK - Number of Bank of a given device involved in the FAW period. */
> +#define ARRIA10_SDR_ACTIVATE_FAWBANK	(0x1)
> +
> +#define ARRIA_DDR_CONFIG(A, B, C, R)	((A<<24)|(B<<16)|(C<<8)|R)

Missing parenthesis around (A), (B) etc. ...

> +#define DDR_CONFIG_ELEMENTS	(sizeof(ddr_config)/sizeof(u32))

So this is ARRAY_SIZE() ?

> +#define DDR_REG_SEQ2CORE        0xFFD0507C
> +#define DDR_REG_CORE2SEQ        0xFFD05078
> +#define DDR_READ_LATENCY_DELAY	40
> +#define DDR_SIZE_2GB_HEX	0x80000000
> +#define DDR_MAX_TRIES		0x00100000
> +
> +#define IO48_MMR_DRAMSTS	0xFFCFA0EC
> +#define IO48_MMR_NIOS2_RESERVE0	0xFFCFA110
> +#define IO48_MMR_NIOS2_RESERVE1	0xFFCFA114
> +#define IO48_MMR_NIOS2_RESERVE2	0xFFCFA118
> +
> +#define SEQ2CORE_MASK		0xF
> +#define CORE2SEQ_INT_REQ	0xF
> +#define SEQ2CORE_INT_RESP_BIT	3
> +
> +static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
> +		(void *)SOCFPGA_SDR_ADDRESS;
> +static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
> +		(void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
> +static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
> +		*socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
> +		(void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
> +static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
> +		(void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
> +static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
> +		(void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
> +
> +/* The followring are the supported configurations */
> +static u32 ddr_config[] = {
> +	/* Chip - Row - Bank - Column Style */
> +	/* All Types */
> +	ARRIA_DDR_CONFIG(0, 3, 10, 12),
> +	ARRIA_DDR_CONFIG(0, 3, 10, 13),
> +	ARRIA_DDR_CONFIG(0, 3, 10, 14),
> +	ARRIA_DDR_CONFIG(0, 3, 10, 15),
> +	ARRIA_DDR_CONFIG(0, 3, 10, 16),
> +	ARRIA_DDR_CONFIG(0, 3, 10, 17),
> +	/* LPDDR x16 */
> +	ARRIA_DDR_CONFIG(0, 3, 11, 14),
> +	ARRIA_DDR_CONFIG(0, 3, 11, 15),
> +	ARRIA_DDR_CONFIG(0, 3, 11, 16),
> +	ARRIA_DDR_CONFIG(0, 3, 12, 15),
> +	/* DDR4 Only */
> +	ARRIA_DDR_CONFIG(0, 4, 10, 14),
> +	ARRIA_DDR_CONFIG(0, 4, 10, 15),
> +	ARRIA_DDR_CONFIG(0, 4, 10, 16),
> +	ARRIA_DDR_CONFIG(0, 4, 10, 17),	/* 14 */
> +	/* Chip - Bank - Row - Column Style */
> +	ARRIA_DDR_CONFIG(1, 3, 10, 12),
> +	ARRIA_DDR_CONFIG(1, 3, 10, 13),
> +	ARRIA_DDR_CONFIG(1, 3, 10, 14),
> +	ARRIA_DDR_CONFIG(1, 3, 10, 15),
> +	ARRIA_DDR_CONFIG(1, 3, 10, 16),
> +	ARRIA_DDR_CONFIG(1, 3, 10, 17),
> +	ARRIA_DDR_CONFIG(1, 3, 11, 14),
> +	ARRIA_DDR_CONFIG(1, 3, 11, 15),
> +	ARRIA_DDR_CONFIG(1, 3, 11, 16),
> +	ARRIA_DDR_CONFIG(1, 3, 12, 15),
> +	/* DDR4 Only */
> +	ARRIA_DDR_CONFIG(1, 4, 10, 14),
> +	ARRIA_DDR_CONFIG(1, 4, 10, 15),
> +	ARRIA_DDR_CONFIG(1, 4, 10, 16),
> +	ARRIA_DDR_CONFIG(1, 4, 10, 17),
> +};
> +
> +static int match_ddr_conf(u32 ddr_conf)
> +{
> +	int i;
> +
> +	for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
> +		if (ddr_conf == ddr_config[i])
> +			return i;
> +	}
> +	return 0;
> +}
> +
> +/* Check whether SDRAM is successfully Calibrated */
> +static int is_sdram_cal_success(void)
> +{
> +	return readl(&socfpga_ecc_hmc_base->ddrcalstat);
> +}
> +
> +static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)
> +{
> +	u32 reg = readl(ereg);
> +
> +	return (reg & (1 << bit)) ? 1 : 0;

Urgh, BIT() and just use it inline and drop this

> +}
> +
> +static unsigned char ddr_wait_bit(u32 ereg, u32 bit,
> +			   u32 expected, u32 timeout_usec)
> +{
> +	u32 tmr;
> +
> +	for (tmr = 0; tmr < timeout_usec; tmr += 100) {
> +		udelay(100);
> +		WATCHDOG_RESET();
> +		if (ddr_get_bit(ereg, bit) == expected)
> +			return 0;
> +	}
> +
> +	return 1;
> +}
> +
> +static void ddr_delay(u32 delay)
> +{
> +	int tmr;
> +
> +	for (tmr = 0; tmr < delay; tmr++) {
> +		udelay(1000);
> +		WATCHDOG_RESET();

So this is mdelay(delay) ?

> +	}
> +}
> +
> +static int emif_clear(void)
> +{
> +	u32 s2c;
> +	u32 i = DDR_MAX_TRIES;
> +
> +	writel(0, DDR_REG_CORE2SEQ);
> +	do {
> +		ddr_delay(50);
> +		s2c = readl(DDR_REG_SEQ2CORE);
> +	} while ((s2c & SEQ2CORE_MASK) && (--i > 0));

wait_for_bit() or something ?

> +	return !i;
> +}
> +
> +static int emif_reset(void)
> +{
> +	u32 c2s, s2c;
> +
> +	c2s = readl(DDR_REG_CORE2SEQ);
> +	s2c = readl(DDR_REG_SEQ2CORE);
> +
> +	debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
> +		c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
> +		readl(IO48_MMR_NIOS2_RESERVE1),
> +		readl(IO48_MMR_NIOS2_RESERVE2),
> +		readl(IO48_MMR_DRAMSTS));
> +
> +	if ((s2c & SEQ2CORE_MASK) && emif_clear()) {
> +		printf("failed emif_clear()\n");
> +		return -1;
> +	}
> +
> +	writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
> +
> +	if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {
> +		printf("emif_reset failed to see interrupt acknowledge\n");
> +		return -2;

Use proper errno.h codes

> +	} else {
> +		printf("emif_reset interrupt acknowledged\n");
> +	}
> +
> +	if (emif_clear()) {
> +		printf("emif_clear() failed\n");
> +		return -3;
> +	}
> +	debug("emif_reset interrupt cleared\n");
> +
> +	debug("nr0=%08x nr1=%08x nr2=%08x\n",
> +		readl(IO48_MMR_NIOS2_RESERVE0),
> +		readl(IO48_MMR_NIOS2_RESERVE1),
> +		readl(IO48_MMR_NIOS2_RESERVE2));
> +
> +	return 0;
> +}
[...]

> +struct firewall_entry {
> +	const char *prop_name;
> +	const u32 cfg_addr;
> +	const u32 en_addr;
> +	const u32 en_bit;
> +};
> +#define FW_MPU_FPGA_ADDRESS \
> +	((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
> +	SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
> +const struct firewall_entry firewall_table[] = {
> +	{

This seems to be mostly copy-paste of the same stuff ... fix with macro.

> +		"altr,mpu0",
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
> +		offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
> +			 mpuregion0addr),
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
> +		offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
> +			 enable),
> +		ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
> +	},
> +	{
> +		"altr,mpu1",
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
> +		offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
> +			 mpuregion1addr),
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
> +		offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
> +			 enable),
> +		ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
> +	},
[...]


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 14/19] arm: socfpga: Enable build for DDR Arria 10

[Marek Vasut]

On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> This patch is for enabling the DDR support on Arria 10.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  drivers/ddr/altera/Makefile | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
> index ac4ab85..02f8b7c 100644
> --- a/drivers/ddr/altera/Makefile
> +++ b/drivers/ddr/altera/Makefile
> @@ -10,4 +10,5 @@
>  
>  ifdef CONFIG_ALTERA_SDRAM
>  obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
> +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
>  endif
> 
This should be part of the patch which added the sdram_arria10.c

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory allocation in SPL

[Marek Vasut]

On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Add support to memory allocation in SPL for preparation to enable FAT
> in SPL. Memory allocation is needed by FAT to work properly.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

Gen 5 does have malloc support in SPL, so what's the deal here ?

> ---
>  include/configs/socfpga_common.h | 23 ++++++++++++++++++++++-
>  1 file changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index 7549ee8..9b6719e 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -280,17 +280,34 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>  /*
>   * SPL
>   *
> - * SRAM Memory layout:
> + * SRAM Memory layout for gen 5:
>   *
>   * 0xFFFF_0000 ...... Start of SRAM
>   * 0xFFFF_xxxx ...... Top of stack (grows down)
>   * 0xFFFF_yyyy ...... Malloc area
>   * 0xFFFF_zzzz ...... Global Data
>   * 0xFFFF_FF00 ...... End of SRAM
> + *
> + * SRAM Memory layout for Arria 10:
> + * 0xFFE0_0000 ...... Start of SRAM (bottom)
> + * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
> + * 0xFFEy_yyyy ...... Malloc area (grows up to top)
> + * 0xFFEz_zzzz ...... Global Data
> + * 0xFFE3_FFFF ...... End of SRAM (top)
>   */
>  #define CONFIG_SPL_FRAMEWORK
>  #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
>  #define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE
> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +/* SPL memory allocation configuration, it is required by FAT feature */
> +#ifndef CONFIG_SYS_SPL_MALLOC_START
> +#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00002000
> +#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_INIT_RAM_SIZE - \
> +					 GENERATED_GBL_DATA_SIZE - \
> +					 CONFIG_SYS_SPL_MALLOC_SIZE + \
> +					 CONFIG_SYS_INIT_RAM_ADDR)
> +#endif
> +#endif
>  
>  /* SPL SDMMC boot support */
>  #ifdef CONFIG_SPL_MMC_SUPPORT
> @@ -320,7 +337,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>  /*
>   * Stack setup
>   */
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#define CONFIG_SPL_STACK		(CONFIG_SYS_SPL_MALLOC_START - 1)
> +#endif
>  
>  /* Extra Environment */
>  #ifndef CONFIG_SPL_BUILD
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10

[Marek Vasut]

On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Enhance preloader header with both additional program length and program
> entry offset attributes, which offset is relative to the start of program
> header.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  arch/arm/mach-socfpga/include/mach/boot0.h | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h
> index 22d9e7f..33c9368 100644
> --- a/arch/arm/mach-socfpga/include/mach/boot0.h
> +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
> @@ -11,8 +11,15 @@
>  	.balignl 64,0xf33db33f;
>  
>  	.word	0x1337c0d3;	/* SoCFPGA preloader validation word */
> -	.word	0xc01df00d;	/* Version, flags, length */
> -	.word	0xcafec0d3;	/* Checksum, zero-pad */
> +	.word	0xc01df00d; /* Header length(2B),flags(1B),version(1B) */
> +#ifndef CONFIG_TARGET_SOCFPGA_GEN5
> +	.word	0xfeedface; /* Program length(4B) */

Keep this indent intact, then it won't generate these crappy - entries.

> +	.word	0xf00dcafe; /*
> +			     * Program entry offset(4B),relative to
> +			     * the start of program header
> +			     */
> +#endif
> +	.word	0xcafec0d3;	/* Simple checksum(2B),spare offset(2B) */
>  	nop;
>  
>  	b reset;		/* SoCFPGA jumps here */
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency info for U-boot

[Marek Vasut]

On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Clock frequency info is required in U-boot.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

I want a TB on Gen 5

> ---
>  arch/arm/mach-socfpga/board.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
> index 965f9dc..a00f63b 100644
> --- a/arch/arm/mach-socfpga/board.c
> +++ b/arch/arm/mach-socfpga/board.c
> @@ -8,7 +8,10 @@
>  
>  #include <common.h>
>  #include <errno.h>
> +#include <fdtdec.h>
>  #include <asm/arch/reset_manager.h>
> +#include <asm/arch/clock_manager.h>
> +#include <asm/arch/misc.h>
>  #include <asm/io.h>
>  
>  #include <usb.h>
> @@ -26,6 +29,9 @@ int board_init(void)
>  	/* Address of boot parameters for ATAG (if ATAG is used) */
>  	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
>  
> +	/* configuring the clock based on handoff */
> +	cm_basic_init(gd->fdt_blob);
> +
>  	return 0;
>  }
>  
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 19/19] arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot

[Marek Vasut]

On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Enable SPL loading U-boot from SDMMC to DDR and booting U-boot.

This patch seems to be doing more than just one thing ...

> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  arch/arm/mach-socfpga/spl.c       | 55 +++++++++++++++++++++++++++++++++++++
>  common/spl/spl_mmc.c              |  2 +-
>  configs/socfpga_arria10_defconfig | 57 ++++++++++++++++++++++++++++++++++-----
>  include/spl.h                     |  2 ++
>  4 files changed, 108 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
> index aba116d..9b381bb 100644
> --- a/arch/arm/mach-socfpga/spl.c
> +++ b/arch/arm/mach-socfpga/spl.c
> @@ -15,6 +15,7 @@
>  #include <asm/arch/system_manager.h>
>  #include <asm/arch/freeze_controller.h>
>  #include <asm/arch/clock_manager.h>
> +#include <asm/arch/fpga_manager.h>
>  #include <asm/arch/misc.h>
>  #include <asm/arch/scan_manager.h>
>  #include <asm/arch/sdram.h>
> @@ -22,6 +23,10 @@
>  #include <asm/arch/nic301.h>
>  #include <asm/sections.h>
>  #include <fdtdec.h>
> +#include <fat.h>
> +#include <fs.h>
> +#include <linux/ctype.h>
> +#include <mmc.h>
>  #include <watchdog.h>
>  #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>  #include <asm/arch/pinmux.h>
> @@ -29,6 +34,9 @@
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> +#define BSIZE	4096
> +#define PERIPH_RBF	0
> +
>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  static struct pl310_regs *const pl310 =
>  	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> @@ -197,6 +205,12 @@ void board_init_f(ulong dummy)
>  #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>  void spl_board_init(void)
>  {
> +	int rval = 0;
> +	int len = 0;
> +	u32 buffer[BSIZE] __aligned(ARCH_DMA_MINALIGN);
> +	struct spl_boot_device bootdev;
> +	fpga_fs_info fpga_fsinfo;
> +
>  	/* configuring the clock based on handoff */
>  	cm_basic_init(gd->fdt_blob);
>  	WATCHDOG_RESET();
> @@ -214,6 +228,47 @@ void spl_board_init(void)
>  
>  	/* Add device descriptor to FPGA device table */
>  	socfpga_fpga_add();
> +
> +	bootdev.boot_device = spl_boot_device();
> +
> +	if (BOOT_DEVICE_MMC1 == bootdev.boot_device) {
> +		struct mmc *mmc = NULL;
> +		int err = 0;
> +
> +		spl_mmc_find_device(&mmc, bootdev.boot_device);
> +
> +		err = mmc_init(mmc);
> +
> +		if (err) {
> +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
> +			printf("spl: mmc init failed with error: %d\n", err);
> +#endif
> +		}
> +
> +		fpga_fsinfo.dev_part = (char *)get_cff_devpart(gd->fdt_blob,
> +								 &len);
> +
> +		fpga_fsinfo.filename = (char *)get_cff_filename(gd->fdt_blob,
> +								 &len,
> +								PERIPH_RBF);
> +
> +		fpga_fsinfo.interface = "mmc";
> +
> +		fpga_fsinfo.fstype = FS_TYPE_FAT;
> +	} else {
> +		printf("Invalid boot device!\n");
> +		return;
> +	}
> +
> +	/* Program peripheral RBF */
> +	if (fpga_fsinfo.filename && fpga_fsinfo.dev_part && (len > 0))
> +		rval = fpga_fsload(0, buffer, BSIZE, &fpga_fsinfo);
> +
> +	if (rval > 0) {
> +		config_pins(gd->fdt_blob, "shared");
> +
> +		ddr_calibration_sequence();
> +	}
>  }
>  
>  void board_init_f(ulong dummy)
> diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
> index b2cccc6..159443f 100644
> --- a/common/spl/spl_mmc.c
> +++ b/common/spl/spl_mmc.c
> @@ -113,7 +113,7 @@ static int spl_mmc_get_device_index(u32 boot_device)
>  	return -ENODEV;
>  }
>  
> -static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
> +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
>  {
>  #if CONFIG_IS_ENABLED(DM_MMC)
>  	struct udevice *dev;
> diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
> index 4c73d73..2ff9801 100644
> --- a/configs/socfpga_arria10_defconfig
> +++ b/configs/socfpga_arria10_defconfig
> @@ -2,33 +2,76 @@ CONFIG_ARM=y
>  CONFIG_ARCH_SOCFPGA=y
>  CONFIG_SYS_MALLOC_F_LEN=0x2000
>  CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
> +CONFIG_SPL_STACK_R_ADDR=0x00800000
>  CONFIG_IDENT_STRING="socfpga_arria10"
>  CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
> -CONFIG_USE_BOOTARGS=y
> -CONFIG_BOOTARGS="console=ttyS0,115200"
>  CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
> +CONFIG_FIT=y
> +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
> +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
> +CONFIG_SPL_ENV_SUPPORT=y
> +CONFIG_VERSION_VARIABLE=y
>  CONFIG_SPL=y
> +CONFIG_HUSH_PARSER=y
>  CONFIG_SPL_FPGA_SUPPORT=y
> +CONFIG_SPL_FAT_SUPPORT=y
> +CONFIG_FS_FAT_MAX_CLUSTSIZE=32768
>  CONFIG_CMD_BOOTZ=y
>  # CONFIG_CMD_IMLS is not set
>  CONFIG_CMD_ASKENV=y
>  CONFIG_CMD_GREPENV=y
>  # CONFIG_CMD_FLASH is not set
> -CONFIG_CMD_GPIO=y
> +CONFIG_SPL_LIBDISK_SUPPORT=y
> +CONFIG_CMD_PART=y
>  CONFIG_CMD_MMC=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_SPI=y
> +CONFIG_CMD_I2C=y
> +CONFIG_SYS_I2C_DW=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_DFU=y
> +CONFIG_CMD_USB_MASS_STORAGE=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_MII=y
>  CONFIG_CMD_DHCP=y
>  CONFIG_CMD_PING=y
>  CONFIG_CMD_CACHE=y
> -CONFIG_CMD_EXT4=y
> -CONFIG_CMD_EXT4_WRITE=y
>  CONFIG_DOS_PARTITION=y
> -# CONFIG_SPL_DOS_PARTITION is not set
> -CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_SPL_DOS_PARTITION=y
> +CONFIG_SPL_FS_GENERIC=y
> +CONFIG_CMD_FAT=y
> +CONFIG_CMD_FS_GENERIC=y
>  CONFIG_SPL_DM=y
>  CONFIG_SPL_DM_SEQ_ALIAS=y
> +CONFIG_DFU_MMC=y
>  CONFIG_FPGA_SOCFPGA=y
>  CONFIG_DM_GPIO=y
>  CONFIG_DWAPB_GPIO=y
>  CONFIG_DM_MMC=y
> +CONFIG_MMC_DW=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_BAR=y
> +CONFIG_SPI_FLASH_SPANSION=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_DM_ETH=y
> +CONFIG_ETH_DESIGNWARE=y
>  CONFIG_SYS_NS16550=y
>  CONFIG_USE_TINY_PRINTF=y
> +CONFIG_CMD_FPGA_LOADFS=y
> +CONFIG_CADENCE_QSPI=y
> +CONFIG_DESIGNWARE_SPI=y
> +CONFIG_USB=y
> +CONFIG_DM_USB=y
> +CONFIG_USB_STORAGE=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_DWC2_OTG=y
> +CONFIG_USB_GADGET_DOWNLOAD=y
> +CONFIG_G_DNL_MANUFACTURER="altera"
> +CONFIG_G_DNL_VENDOR_NUM=0x0525
> +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
> +CONFIG_USE_TINY_PRINTF=y
> +CONFIG_SPL_MMC_SUPPORT=y
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
> +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
> diff --git a/include/spl.h b/include/spl.h
> index ce4cf0a..e24433d 100644
> --- a/include/spl.h
> +++ b/include/spl.h
> @@ -10,6 +10,7 @@
>  /* Platform-specific defines */
>  #include <linux/compiler.h>
>  #include <asm/spl.h>
> +#include <mmc.h>
>  
>  /* Value in r0 indicates we booted from U-Boot */
>  #define UBOOT_NOT_LOADED_FROM_SPL	0x13578642
> @@ -68,6 +69,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
>  void preloader_console_init(void);
>  u32 spl_boot_device(void);
>  u32 spl_boot_mode(const u32 boot_device);
> +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device);
>  
>  /**
>   * spl_set_header_raw_uboot() - Set up a standard SPL image structure
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 19/19] arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot

[Chee, Tien Fong]

On Isn, 2017-09-25 at 11:24 +0200, Marek Vasut wrote:
> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > Enable SPL loading U-boot from SDMMC to DDR and booting U-boot.
> This patch seems to be doing more than just one thing ...
> 
I can split into two patches:
1) Enable DDR up by configuring FPGA so SPL able loading U-boot to DDR
2) Setting up configs so SPL can boot U-boot from FAT.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> >  arch/arm/mach-socfpga/spl.c       | 55
> > +++++++++++++++++++++++++++++++++++++
> >  common/spl/spl_mmc.c              |  2 +-
> >  configs/socfpga_arria10_defconfig | 57
> > ++++++++++++++++++++++++++++++++++-----
> >  include/spl.h                     |  2 ++
> >  4 files changed, 108 insertions(+), 8 deletions(-)
> > 
> > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-
> > socfpga/spl.c
> > index aba116d..9b381bb 100644
> > --- a/arch/arm/mach-socfpga/spl.c
> > +++ b/arch/arm/mach-socfpga/spl.c
> > @@ -15,6 +15,7 @@
> >  #include <asm/arch/system_manager.h>
> >  #include <asm/arch/freeze_controller.h>
> >  #include <asm/arch/clock_manager.h>
> > +#include <asm/arch/fpga_manager.h>
> >  #include <asm/arch/misc.h>
> >  #include <asm/arch/scan_manager.h>
> >  #include <asm/arch/sdram.h>
> > @@ -22,6 +23,10 @@
> >  #include <asm/arch/nic301.h>
> >  #include <asm/sections.h>
> >  #include <fdtdec.h>
> > +#include <fat.h>
> > +#include <fs.h>
> > +#include <linux/ctype.h>
> > +#include <mmc.h>
> >  #include <watchdog.h>
> >  #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> >  #include <asm/arch/pinmux.h>
> > @@ -29,6 +34,9 @@
> >  
> >  DECLARE_GLOBAL_DATA_PTR;
> >  
> > +#define BSIZE	4096
> > +#define PERIPH_RBF	0
> > +
> >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >  static struct pl310_regs *const pl310 =
> >  	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> > @@ -197,6 +205,12 @@ void board_init_f(ulong dummy)
> >  #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> >  void spl_board_init(void)
> >  {
> > +	int rval = 0;
> > +	int len = 0;
> > +	u32 buffer[BSIZE] __aligned(ARCH_DMA_MINALIGN);
> > +	struct spl_boot_device bootdev;
> > +	fpga_fs_info fpga_fsinfo;
> > +
> >  	/* configuring the clock based on handoff */
> >  	cm_basic_init(gd->fdt_blob);
> >  	WATCHDOG_RESET();
> > @@ -214,6 +228,47 @@ void spl_board_init(void)
> >  
> >  	/* Add device descriptor to FPGA device table */
> >  	socfpga_fpga_add();
> > +
> > +	bootdev.boot_device = spl_boot_device();
> > +
> > +	if (BOOT_DEVICE_MMC1 == bootdev.boot_device) {
> > +		struct mmc *mmc = NULL;
> > +		int err = 0;
> > +
> > +		spl_mmc_find_device(&mmc, bootdev.boot_device);
> > +
> > +		err = mmc_init(mmc);
> > +
> > +		if (err) {
> > +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
> > +			printf("spl: mmc init failed with error:
> > %d\n", err);
> > +#endif
> > +		}
> > +
> > +		fpga_fsinfo.dev_part = (char *)get_cff_devpart(gd-
> > >fdt_blob,
> > +								 &
> > len);
> > +
> > +		fpga_fsinfo.filename = (char
> > *)get_cff_filename(gd->fdt_blob,
> > +								 &
> > len,
> > +								PE
> > RIPH_RBF);
> > +
> > +		fpga_fsinfo.interface = "mmc";
> > +
> > +		fpga_fsinfo.fstype = FS_TYPE_FAT;
> > +	} else {
> > +		printf("Invalid boot device!\n");
> > +		return;
> > +	}
> > +
> > +	/* Program peripheral RBF */
> > +	if (fpga_fsinfo.filename && fpga_fsinfo.dev_part && (len >
> > 0))
> > +		rval = fpga_fsload(0, buffer, BSIZE,
> > &fpga_fsinfo);
> > +
> > +	if (rval > 0) {
> > +		config_pins(gd->fdt_blob, "shared");
> > +
> > +		ddr_calibration_sequence();
> > +	}
> >  }
> >  
> >  void board_init_f(ulong dummy)
> > diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
> > index b2cccc6..159443f 100644
> > --- a/common/spl/spl_mmc.c
> > +++ b/common/spl/spl_mmc.c
> > @@ -113,7 +113,7 @@ static int spl_mmc_get_device_index(u32
> > boot_device)
> >  	return -ENODEV;
> >  }
> >  
> > -static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
> > +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
> >  {
> >  #if CONFIG_IS_ENABLED(DM_MMC)
> >  	struct udevice *dev;
> > diff --git a/configs/socfpga_arria10_defconfig
> > b/configs/socfpga_arria10_defconfig
> > index 4c73d73..2ff9801 100644
> > --- a/configs/socfpga_arria10_defconfig
> > +++ b/configs/socfpga_arria10_defconfig
> > @@ -2,33 +2,76 @@ CONFIG_ARM=y
> >  CONFIG_ARCH_SOCFPGA=y
> >  CONFIG_SYS_MALLOC_F_LEN=0x2000
> >  CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
> > +CONFIG_SPL_STACK_R_ADDR=0x00800000
> >  CONFIG_IDENT_STRING="socfpga_arria10"
> >  CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
> > -CONFIG_USE_BOOTARGS=y
> > -CONFIG_BOOTARGS="console=ttyS0,115200"
> >  CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
> > +CONFIG_FIT=y
> > +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> > +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
> > +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
> > +CONFIG_SPL_ENV_SUPPORT=y
> > +CONFIG_VERSION_VARIABLE=y
> >  CONFIG_SPL=y
> > +CONFIG_HUSH_PARSER=y
> >  CONFIG_SPL_FPGA_SUPPORT=y
> > +CONFIG_SPL_FAT_SUPPORT=y
> > +CONFIG_FS_FAT_MAX_CLUSTSIZE=32768
> >  CONFIG_CMD_BOOTZ=y
> >  # CONFIG_CMD_IMLS is not set
> >  CONFIG_CMD_ASKENV=y
> >  CONFIG_CMD_GREPENV=y
> >  # CONFIG_CMD_FLASH is not set
> > -CONFIG_CMD_GPIO=y
> > +CONFIG_SPL_LIBDISK_SUPPORT=y
> > +CONFIG_CMD_PART=y
> >  CONFIG_CMD_MMC=y
> > +CONFIG_CMD_SF=y
> > +CONFIG_CMD_SPI=y
> > +CONFIG_CMD_I2C=y
> > +CONFIG_SYS_I2C_DW=y
> > +CONFIG_CMD_USB=y
> > +CONFIG_CMD_DFU=y
> > +CONFIG_CMD_USB_MASS_STORAGE=y
> > +CONFIG_CMD_GPIO=y
> > +CONFIG_CMD_MII=y
> >  CONFIG_CMD_DHCP=y
> >  CONFIG_CMD_PING=y
> >  CONFIG_CMD_CACHE=y
> > -CONFIG_CMD_EXT4=y
> > -CONFIG_CMD_EXT4_WRITE=y
> >  CONFIG_DOS_PARTITION=y
> > -# CONFIG_SPL_DOS_PARTITION is not set
> > -CONFIG_ENV_IS_IN_MMC=y
> > +CONFIG_SPL_DOS_PARTITION=y
> > +CONFIG_SPL_FS_GENERIC=y
> > +CONFIG_CMD_FAT=y
> > +CONFIG_CMD_FS_GENERIC=y
> >  CONFIG_SPL_DM=y
> >  CONFIG_SPL_DM_SEQ_ALIAS=y
> > +CONFIG_DFU_MMC=y
> >  CONFIG_FPGA_SOCFPGA=y
> >  CONFIG_DM_GPIO=y
> >  CONFIG_DWAPB_GPIO=y
> >  CONFIG_DM_MMC=y
> > +CONFIG_MMC_DW=y
> > +CONFIG_SPI_FLASH=y
> > +CONFIG_SPI_FLASH_BAR=y
> > +CONFIG_SPI_FLASH_SPANSION=y
> > +CONFIG_SPI_FLASH_STMICRO=y
> > +CONFIG_DM_ETH=y
> > +CONFIG_ETH_DESIGNWARE=y
> >  CONFIG_SYS_NS16550=y
> >  CONFIG_USE_TINY_PRINTF=y
> > +CONFIG_CMD_FPGA_LOADFS=y
> > +CONFIG_CADENCE_QSPI=y
> > +CONFIG_DESIGNWARE_SPI=y
> > +CONFIG_USB=y
> > +CONFIG_DM_USB=y
> > +CONFIG_USB_STORAGE=y
> > +CONFIG_USB_GADGET=y
> > +CONFIG_USB_GADGET_DWC2_OTG=y
> > +CONFIG_USB_GADGET_DOWNLOAD=y
> > +CONFIG_G_DNL_MANUFACTURER="altera"
> > +CONFIG_G_DNL_VENDOR_NUM=0x0525
> > +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
> > +CONFIG_USE_TINY_PRINTF=y
> > +CONFIG_SPL_MMC_SUPPORT=y
> > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
> > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
> > +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
> > diff --git a/include/spl.h b/include/spl.h
> > index ce4cf0a..e24433d 100644
> > --- a/include/spl.h
> > +++ b/include/spl.h
> > @@ -10,6 +10,7 @@
> >  /* Platform-specific defines */
> >  #include <linux/compiler.h>
> >  #include <asm/spl.h>
> > +#include <mmc.h>
> >  
> >  /* Value in r0 indicates we booted from U-Boot */
> >  #define UBOOT_NOT_LOADED_FROM_SPL	0x13578642
> > @@ -68,6 +69,7 @@ int spl_load_simple_fit(struct spl_image_info
> > *spl_image,
> >  void preloader_console_init(void);
> >  u32 spl_boot_device(void);
> >  u32 spl_boot_mode(const u32 boot_device);
> > +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device);
> >  
> >  /**
> >   * spl_set_header_raw_uboot() - Set up a standard SPL image
> > structure
> > 
> 

[U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency info for U-boot

[Chee, Tien Fong]

On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:
> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > Clock frequency info is required in U-boot.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> I want a TB on Gen 5
> 
What is TB?
> > 
> > ---
> >  arch/arm/mach-socfpga/board.c | 6 ++++++
> >  1 file changed, 6 insertions(+)
> > 
> > diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-
> > socfpga/board.c
> > index 965f9dc..a00f63b 100644
> > --- a/arch/arm/mach-socfpga/board.c
> > +++ b/arch/arm/mach-socfpga/board.c
> > @@ -8,7 +8,10 @@
> >  
> >  #include <common.h>
> >  #include <errno.h>
> > +#include <fdtdec.h>
> >  #include <asm/arch/reset_manager.h>
> > +#include <asm/arch/clock_manager.h>
> > +#include <asm/arch/misc.h>
> >  #include <asm/io.h>
> >  
> >  #include <usb.h>
> > @@ -26,6 +29,9 @@ int board_init(void)
> >  	/* Address of boot parameters for ATAG (if ATAG is used)
> > */
> >  	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> >  
> > +	/* configuring the clock based on handoff */
> > +	cm_basic_init(gd->fdt_blob);
> > +
> >  	return 0;
> >  }
> >  
> > 
> 

[U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10

[Chee, Tien Fong]

On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:
> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > Enhance preloader header with both additional program length and
> > program
> > entry offset attributes, which offset is relative to the start of
> > program
> > header.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> >  arch/arm/mach-socfpga/include/mach/boot0.h | 11 +++++++++--
> >  1 file changed, 9 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h
> > b/arch/arm/mach-socfpga/include/mach/boot0.h
> > index 22d9e7f..33c9368 100644
> > --- a/arch/arm/mach-socfpga/include/mach/boot0.h
> > +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
> > @@ -11,8 +11,15 @@
> >  	.balignl 64,0xf33db33f;
> >  
> >  	.word	0x1337c0d3;	/* SoCFPGA preloader
> > validation word */
> > -	.word	0xc01df00d;	/* Version, flags, length
> > */
> > -	.word	0xcafec0d3;	/* Checksum, zero-pad */
> > +	.word	0xc01df00d; /* Header
> > length(2B),flags(1B),version(1B) */
> > +#ifndef CONFIG_TARGET_SOCFPGA_GEN5
> > +	.word	0xfeedface; /* Program length(4B) */
> Keep this indent intact, then it won't generate these crappy -
> entries.
> 
Are you saying to keep the comment indent intact, and allign with 1st
comment  /* SoCFPGA preloader validation word */ ?
> > 
> > +	.word	0xf00dcafe; /*
> > +			     * Program entry offset(4B),relative
> > to
> > +			     * the start of program header
> > +			     */
> > +#endif
> > +	.word	0xcafec0d3;	/* Simple
> > checksum(2B),spare offset(2B) */
> >  	nop;
> >  
> >  	b reset;		/* SoCFPGA jumps here */
> > 
> 

[U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory allocation in SPL

[Chee, Tien Fong]

On Isn, 2017-09-25 at 11:21 +0200, Marek Vasut wrote:
> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > Add support to memory allocation in SPL for preparation to enable
> > FAT
> > in SPL. Memory allocation is needed by FAT to work properly.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> Gen 5 does have malloc support in SPL, so what's the deal here ?
> 
For FAT to work properly in Arria 10 SPL, SPL malloc need to be
enabled, and the min of SPL malloc size is 0x2000. FAT needed in Arria
10 SPL, because u-boot.img is stored in FAT partition.
> > 
> > ---
> >  include/configs/socfpga_common.h | 23 ++++++++++++++++++++++-
> >  1 file changed, 22 insertions(+), 1 deletion(-)
> > 
> > diff --git a/include/configs/socfpga_common.h
> > b/include/configs/socfpga_common.h
> > index 7549ee8..9b6719e 100644
> > --- a/include/configs/socfpga_common.h
> > +++ b/include/configs/socfpga_common.h
> > @@ -280,17 +280,34 @@ unsigned int
> > cm_get_qspi_controller_clk_hz(void);
> >  /*
> >   * SPL
> >   *
> > - * SRAM Memory layout:
> > + * SRAM Memory layout for gen 5:
> >   *
> >   * 0xFFFF_0000 ...... Start of SRAM
> >   * 0xFFFF_xxxx ...... Top of stack (grows down)
> >   * 0xFFFF_yyyy ...... Malloc area
> >   * 0xFFFF_zzzz ...... Global Data
> >   * 0xFFFF_FF00 ...... End of SRAM
> > + *
> > + * SRAM Memory layout for Arria 10:
> > + * 0xFFE0_0000 ...... Start of SRAM (bottom)
> > + * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
> > + * 0xFFEy_yyyy ...... Malloc area (grows up to top)
> > + * 0xFFEz_zzzz ...... Global Data
> > + * 0xFFE3_FFFF ...... End of SRAM (top)
> >   */
> >  #define CONFIG_SPL_FRAMEWORK
> >  #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_AD
> > DR
> >  #define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZ
> > E
> > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +/* SPL memory allocation configuration, it is required by FAT
> > feature */
> > +#ifndef CONFIG_SYS_SPL_MALLOC_START
> > +#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00002000
> > +#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_INIT_RAM_SI
> > ZE - \
> > +					 GENERATED_GBL_DATA_SIZE -
> > \
> > +					 CONFIG_SYS_SPL_MALLOC_SIZ
> > E + \
> > +					 CONFIG_SYS_INIT_RAM_ADDR)
> > +#endif
> > +#endif
> >  
> >  /* SPL SDMMC boot support */
> >  #ifdef CONFIG_SPL_MMC_SUPPORT
> > @@ -320,7 +337,11 @@ unsigned int
> > cm_get_qspi_controller_clk_hz(void);
> >  /*
> >   * Stack setup
> >   */
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >  #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +#define CONFIG_SPL_STACK		(CONFIG_SYS_SPL_MALLOC_STA
> > RT - 1)
> > +#endif
> >  
> >  /* Extra Environment */
> >  #ifndef CONFIG_SPL_BUILD
> > 
> 

[U-Boot] [PATCH v2 14/19] arm: socfpga: Enable build for DDR Arria 10

[Chee, Tien Fong]

On Isn, 2017-09-25 at 11:20 +0200, Marek Vasut wrote:
> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > This patch is for enabling the DDR support on Arria 10.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> >  drivers/ddr/altera/Makefile | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/ddr/altera/Makefile
> > b/drivers/ddr/altera/Makefile
> > index ac4ab85..02f8b7c 100644
> > --- a/drivers/ddr/altera/Makefile
> > +++ b/drivers/ddr/altera/Makefile
> > @@ -10,4 +10,5 @@
> >  
> >  ifdef CONFIG_ALTERA_SDRAM
> >  obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
> > +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
> >  endif
> > 
> This should be part of the patch which added the sdram_arria10.c
> 
Okay.

[U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for Arria 10

[Chee, Tien Fong]

On Isn, 2017-09-25 at 11:19 +0200, Marek Vasut wrote:
> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > Add DDR driver suppport for Arria 10.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> >  arch/arm/mach-socfpga/include/mach/sdram.h         |   2 +
> >  arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-
> >  drivers/ddr/altera/sdram_arria10.c                 | 735
> > +++++++++++++++++++++
> >  3 files changed, 839 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/ddr/altera/sdram_arria10.c
> > 
> > diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
> > b/arch/arm/mach-socfpga/include/mach/sdram.h
> > index 4a9754e..b833fc2 100644
> > --- a/arch/arm/mach-socfpga/include/mach/sdram.h
> > +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
> > @@ -10,6 +10,8 @@
> >  
> >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >  #include <asm/arch/sdram_gen5.h>
> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +#include <asm/arch/sdram_arria10.h>
> >  #endif
> >  
> >  #endif
> > diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > index 1d7b7c1..7af9431 100644
> > --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > @@ -1,5 +1,5 @@
> >  /*
> > - * Copyright (C) 2015-2017 Intel Corporation <www.intel.com>
> > + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> >   *
> >   * SPDX-License-Identifier:	GPL-2.0
> >   */
> > @@ -8,6 +8,7 @@
> >  #define _SOCFPGA_SDRAM_ARRIA10_H_
> >  
> >  #ifndef __ASSEMBLY__
> > +int ddr_calibration_sequence(void);
> >  
> >  struct socfpga_ecc_hmc {
> >  	u32 ip_rev_id;
> > @@ -204,6 +205,106 @@ struct socfpga_io48_mmr {
> >  	u32 niosreserve1;
> >  	u32 niosreserve2;
> >  };
> > +
> > +union dramaddrw_reg {
> > +	struct {
> > +		u32 cfg_col_addr_width:5;
> > +		u32 cfg_row_addr_width:5;
> > +		u32 cfg_bank_addr_width:4;
> > +		u32 cfg_bank_group_addr_width:2;
> > +		u32 cfg_cs_addr_width:3;
> > +		u32 reserved:13;
> > +	};
> Use regular macros for bitfields, not this crap.
> 
Why regular macros is prefered? Above implementation improve
readability, simplify the implementation and saving memory.
> > 
> > +	u32 word;
> > +};
> > +
> > +union ctrlcfg0_reg {
> > +	struct {
> > +		u32 cfg_mem_type:4;
> > +		u32 cfg_dimm_type:3;
> > +		u32 cfg_ac_pos:2;
> > +		u32 cfg_ctrl_burst_len:5;
> > +		u32 reserved:18;  /* Other fields unused */
> > +	};
> > +	u32 word;
> > +};
> [...]
> 
> > 
> > diff --git a/drivers/ddr/altera/sdram_arria10.c
> > b/drivers/ddr/altera/sdram_arria10.c
> > new file mode 100644
> > index 0000000..f22a726
> > --- /dev/null
> > +++ b/drivers/ddr/altera/sdram_arria10.c
> > @@ -0,0 +1,735 @@
> > +/*
> > + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> > + *
> > + * SPDX-License-Identifier:    GPL-2.0
> > + */
> > +
> > +#include <common.h>
> > +#include <fdtdec.h>
> > +#include <malloc.h>
> > +#include <mmc.h>
> > +#include <nand.h>
> > +#include <watchdog.h>
> > +#include <ns16550.h>
> Why does an SDRAM init driver need access to ns16550 UART , MMC and
> NAND ?
> 
I will remove them.
> > 
> > +#include <asm/io.h>
> > +#include <asm/arch/fpga_manager.h>
> > +#include <asm/arch/misc.h>
> > +#include <asm/arch/reset_manager.h>
> > +#include <asm/arch/sdram.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +static void sdram_mmr_init(void);
> > +static unsigned long long sdram_size_calc(void);
> > +
> > +/* FAWBANK - Number of Bank of a given device involved in the FAW
> > period. */
> > +#define ARRIA10_SDR_ACTIVATE_FAWBANK	(0x1)
> > +
> > +#define ARRIA_DDR_CONFIG(A, B, C, R)	((A<<24)|(B<<16)|(C<<8
> > )|R)
> Missing parenthesis around (A), (B) etc. ...
> 
Okay.
> > 
> > +#define DDR_CONFIG_ELEMENTS	(sizeof(ddr_config)/sizeof(u32)
> > )
> So this is ARRAY_SIZE() ?
> 
Yes. i will use ARRAY_SIZE().
> > 
> > +#define DDR_REG_SEQ2CORE        0xFFD0507C
> > +#define DDR_REG_CORE2SEQ        0xFFD05078
> > +#define DDR_READ_LATENCY_DELAY	40
> > +#define DDR_SIZE_2GB_HEX	0x80000000
> > +#define DDR_MAX_TRIES		0x00100000
> > +
> > +#define IO48_MMR_DRAMSTS	0xFFCFA0EC
> > +#define IO48_MMR_NIOS2_RESERVE0	0xFFCFA110
> > +#define IO48_MMR_NIOS2_RESERVE1	0xFFCFA114
> > +#define IO48_MMR_NIOS2_RESERVE2	0xFFCFA118
> > +
> > +#define SEQ2CORE_MASK		0xF
> > +#define CORE2SEQ_INT_REQ	0xF
> > +#define SEQ2CORE_INT_RESP_BIT	3
> > +
> > +static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
> > +		(void *)SOCFPGA_SDR_ADDRESS;
> > +static const struct socfpga_noc_ddr_scheduler
> > *socfpga_noc_ddr_scheduler_base =
> > +		(void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
> > +static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
> > +		*socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
> > +		(void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
> > +static const struct socfpga_noc_fw_ddr_l3
> > *socfpga_noc_fw_ddr_l3_base =
> > +		(void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
> > +static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
> > +		(void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
> > +
> > +/* The followring are the supported configurations */
> > +static u32 ddr_config[] = {
> > +	/* Chip - Row - Bank - Column Style */
> > +	/* All Types */
> > +	ARRIA_DDR_CONFIG(0, 3, 10, 12),
> > +	ARRIA_DDR_CONFIG(0, 3, 10, 13),
> > +	ARRIA_DDR_CONFIG(0, 3, 10, 14),
> > +	ARRIA_DDR_CONFIG(0, 3, 10, 15),
> > +	ARRIA_DDR_CONFIG(0, 3, 10, 16),
> > +	ARRIA_DDR_CONFIG(0, 3, 10, 17),
> > +	/* LPDDR x16 */
> > +	ARRIA_DDR_CONFIG(0, 3, 11, 14),
> > +	ARRIA_DDR_CONFIG(0, 3, 11, 15),
> > +	ARRIA_DDR_CONFIG(0, 3, 11, 16),
> > +	ARRIA_DDR_CONFIG(0, 3, 12, 15),
> > +	/* DDR4 Only */
> > +	ARRIA_DDR_CONFIG(0, 4, 10, 14),
> > +	ARRIA_DDR_CONFIG(0, 4, 10, 15),
> > +	ARRIA_DDR_CONFIG(0, 4, 10, 16),
> > +	ARRIA_DDR_CONFIG(0, 4, 10, 17),	/* 14 */
> > +	/* Chip - Bank - Row - Column Style */
> > +	ARRIA_DDR_CONFIG(1, 3, 10, 12),
> > +	ARRIA_DDR_CONFIG(1, 3, 10, 13),
> > +	ARRIA_DDR_CONFIG(1, 3, 10, 14),
> > +	ARRIA_DDR_CONFIG(1, 3, 10, 15),
> > +	ARRIA_DDR_CONFIG(1, 3, 10, 16),
> > +	ARRIA_DDR_CONFIG(1, 3, 10, 17),
> > +	ARRIA_DDR_CONFIG(1, 3, 11, 14),
> > +	ARRIA_DDR_CONFIG(1, 3, 11, 15),
> > +	ARRIA_DDR_CONFIG(1, 3, 11, 16),
> > +	ARRIA_DDR_CONFIG(1, 3, 12, 15),
> > +	/* DDR4 Only */
> > +	ARRIA_DDR_CONFIG(1, 4, 10, 14),
> > +	ARRIA_DDR_CONFIG(1, 4, 10, 15),
> > +	ARRIA_DDR_CONFIG(1, 4, 10, 16),
> > +	ARRIA_DDR_CONFIG(1, 4, 10, 17),
> > +};
> > +
> > +static int match_ddr_conf(u32 ddr_conf)
> > +{
> > +	int i;
> > +
> > +	for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
> > +		if (ddr_conf == ddr_config[i])
> > +			return i;
> > +	}
> > +	return 0;
> > +}
> > +
> > +/* Check whether SDRAM is successfully Calibrated */
> > +static int is_sdram_cal_success(void)
> > +{
> > +	return readl(&socfpga_ecc_hmc_base->ddrcalstat);
> > +}
> > +
> > +static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)
> > +{
> > +	u32 reg = readl(ereg);
> > +
> > +	return (reg & (1 << bit)) ? 1 : 0;
> Urgh, BIT() and just use it inline and drop this
> 
Okay.
> > 
> > +}
> > +
> > +static unsigned char ddr_wait_bit(u32 ereg, u32 bit,
> > +			   u32 expected, u32 timeout_usec)
> > +{
> > +	u32 tmr;
> > +
> > +	for (tmr = 0; tmr < timeout_usec; tmr += 100) {
> > +		udelay(100);
> > +		WATCHDOG_RESET();
> > +		if (ddr_get_bit(ereg, bit) == expected)
> > +			return 0;
> > +	}
> > +
> > +	return 1;
> > +}
> > +
> > +static void ddr_delay(u32 delay)
> > +{
> > +	int tmr;
> > +
> > +	for (tmr = 0; tmr < delay; tmr++) {
> > +		udelay(1000);
> > +		WATCHDOG_RESET();
> So this is mdelay(delay) ?
> 
Yes, i can use mdelay.
> > 
> > +	}
> > +}
> > +
> > +static int emif_clear(void)
> > +{
> > +	u32 s2c;
> > +	u32 i = DDR_MAX_TRIES;
> > +
> > +	writel(0, DDR_REG_CORE2SEQ);
> > +	do {
> > +		ddr_delay(50);
> > +		s2c = readl(DDR_REG_SEQ2CORE);
> > +	} while ((s2c & SEQ2CORE_MASK) && (--i > 0));
> wait_for_bit() or something ?
> 
Okay.
> > 
> > +	return !i;
> > +}
> > +
> > +static int emif_reset(void)
> > +{
> > +	u32 c2s, s2c;
> > +
> > +	c2s = readl(DDR_REG_CORE2SEQ);
> > +	s2c = readl(DDR_REG_SEQ2CORE);
> > +
> > +	debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x
> > dst=%08x\n",
> > +		c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
> > +		readl(IO48_MMR_NIOS2_RESERVE1),
> > +		readl(IO48_MMR_NIOS2_RESERVE2),
> > +		readl(IO48_MMR_DRAMSTS));
> > +
> > +	if ((s2c & SEQ2CORE_MASK) && emif_clear()) {
> > +		printf("failed emif_clear()\n");
> > +		return -1;
> > +	}
> > +
> > +	writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
> > +
> > +	if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT,
> > 0, 1000000)) {
> > +		printf("emif_reset failed to see interrupt
> > acknowledge\n");
> > +		return -2;
> Use proper errno.h codes
> 
Okay.
> > 
> > +	} else {
> > +		printf("emif_reset interrupt acknowledged\n");
> > +	}
> > +
> > +	if (emif_clear()) {
> > +		printf("emif_clear() failed\n");
> > +		return -3;
> > +	}
> > +	debug("emif_reset interrupt cleared\n");
> > +
> > +	debug("nr0=%08x nr1=%08x nr2=%08x\n",
> > +		readl(IO48_MMR_NIOS2_RESERVE0),
> > +		readl(IO48_MMR_NIOS2_RESERVE1),
> > +		readl(IO48_MMR_NIOS2_RESERVE2));
> > +
> > +	return 0;
> > +}
> [...]
> 
> > 
> > +struct firewall_entry {
> > +	const char *prop_name;
> > +	const u32 cfg_addr;
> > +	const u32 en_addr;
> > +	const u32 en_bit;
> > +};
> > +#define FW_MPU_FPGA_ADDRESS \
> > +	((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
> > +	SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
> > +const struct firewall_entry firewall_table[] = {
> > +	{
> This seems to be mostly copy-paste of the same stuff ... fix with
> macro.
> 
Okay.
> > 
> > +		"altr,mpu0",
> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
> > +		offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
> > +			 mpuregion0addr),
> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
> > +		offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
> > +			 enable),
> > +		ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
> > +	},
> > +	{
> > +		"altr,mpu1",
> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
> > +		offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
> > +			 mpuregion1addr),
> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
> > +		offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,
> > +			 enable),
> > +		ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
> > +	},
> [...]
> 
> 

[U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size initialization function

[Chee, Tien Fong]

On Isn, 2017-09-25 at 11:15 +0200, Marek Vasut wrote:
> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > Add function for both multiple DRAM bank and single DRAM bank size
> > initialization. This common functionality could be used by every
> > single
> > SOCFPGA board.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> I'd like TB on Gen5.
> 
What is TB?
> > 
> > ---
> >  arch/arm/mach-socfpga/board.c    | 7 +++++++
> >  include/configs/socfpga_common.h | 1 +
> >  2 files changed, 8 insertions(+)
> > 
> > diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-
> > socfpga/board.c
> > index a41d089..965f9dc 100644
> > --- a/arch/arm/mach-socfpga/board.c
> > +++ b/arch/arm/mach-socfpga/board.c
> > @@ -29,6 +29,13 @@ int board_init(void)
> >  	return 0;
> >  }
> >  
> > +int dram_init_banksize(void)
> > +{
> > +	fdtdec_setup_memory_banksize();
> > +
> > +	return 0;
> > +}
> > +
> >  #ifdef CONFIG_USB_GADGET
> >  struct dwc2_plat_otg_data socfpga_otg_data = {
> >  	.usb_gusbcfg	= 0x1417,
> > diff --git a/include/configs/socfpga_common.h
> > b/include/configs/socfpga_common.h
> > index eadce2d..7549ee8 100644
> > --- a/include/configs/socfpga_common.h
> > +++ b/include/configs/socfpga_common.h
> > @@ -47,6 +47,7 @@
> >  	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> >  
> >  #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
> > +#define CONFIG_SYS_SDRAM_SIZE		PHYS_SDRAM_1_SIZE
> >  #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
> >  #define CONFIG_SYS_TEXT_BASE		0x08000040
> >  #else
> > 
> 

[U-Boot] [PATCH v2 10/19] arm: socfpga: Rename the gen5 sdram driver to more specific name

[Chee, Tien Fong]

On Isn, 2017-09-25 at 11:15 +0200, Marek Vasut wrote:
> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > Current sdram driver is only applied to gen5 device, hence it is
> > better
> > to rename sdram driver to more specific name which is related to
> > gen5
> > device.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> >  arch/arm/mach-socfpga/include/mach/sdram.h         | 434 +------
> > --------------
> >  .../include/mach/{sdram.h => sdram_gen5.h}         |   6 +-
> >  drivers/ddr/altera/Makefile                        |   2 +-
> >  drivers/ddr/altera/{sdram.c => sdram_gen5.c}       |   0
> >  4 files changed, 8 insertions(+), 434 deletions(-)
> >  copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h}
> > (99%)
> >  rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)
> > 
> > diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
> > b/arch/arm/mach-socfpga/include/mach/sdram.h
> > index b11228f..4a9754e 100644
> > --- a/arch/arm/mach-socfpga/include/mach/sdram.h
> > +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
> > @@ -1,5 +1,5 @@
> >  /*
> > - * Copyright Altera Corporation (C) 2014-2015
> > + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> Retain the old copyright ?
> 
Okay.
> > 
> >   *
> >   * SPDX-License-Identifier:	GPL-2.0+
> >   */
> > @@ -8,435 +8,9 @@
> >  
> >  #ifndef __ASSEMBLY__
> What's with this massive deletion here ?
> 
Move to sdram_gen5.h . This header should contain common stuff.
> > 
> > -unsigned long sdram_calculate_size(void);
> > -int sdram_mmr_init_full(unsigned int sdr_phy_reg);
> > -int sdram_calibration_full(void);
> > -
> > -const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
> > -
> > -void socfpga_get_seq_ac_init(const u32 **init, unsigned int
> > *nelem);
> > -void socfpga_get_seq_inst_init(const u32 **init, unsigned int
> > *nelem);
> > -const struct socfpga_sdram_rw_mgr_config
> > *socfpga_get_sdram_rwmgr_config(void);
> [...]
> 

[U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA from flash

[Chee, Tien Fong]

On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:
> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > These drivers handle FPGA program operation from flash loading
> > RBF to memory and then to program FPGA.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> Did you run checkpatch on this before submitting ? I presume no ...
> 
Yeah, i run checkpatch for all patches. What's the issue here?
> > 
> > ---
> >  .../include/mach/fpga_manager_arria10.h            |  27 ++
> >  drivers/fpga/socfpga_arria10.c                     | 391
> > ++++++++++++++++++++-
> >  include/altera.h                                   |   6 +
> >  include/configs/socfpga_common.h                   |   4 +
> >  4 files changed, 425 insertions(+), 3 deletions(-)
> [...]
> 
> > 
> > @@ -112,13 +122,14 @@ static int
> > wait_for_nconfig_pin_and_nstatus_pin(void)
> >  	unsigned long mask =
> > ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
> >  				ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATU
> > S_PIN_SET_MSK;
> >  
> > -	/* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop
> > until de-asserted,
> > -	 * timeout at 1000ms
> > +	/*
> > +	 * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop
> > until
> > +	 * de-asserted, timeout at 1000ms
> >  	 */
> >  	return wait_for_bit(__func__,
> >  			    &fpga_manager_base->imgcfg_stat,
> >  			    mask,
> > -			    false, FPGA_TIMEOUT_MSEC, false);
> > +			    true, FPGA_TIMEOUT_MSEC, false);
> >  }
> Seems more like a fix, split this out.
> 
Okay.
> > 
> >  static int wait_for_f2s_nstatus_pin(unsigned long value)
> > @@ -469,6 +480,7 @@ int socfpga_load(Altera_desc *desc, const void
> > *rbf_data, size_t rbf_size)
> >  
> >  	/* Initialize the FPGA Manager */
> >  	status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
> > +
> >  	if (status)
> >  		return status;
> >  
> > @@ -477,3 +489,376 @@ int socfpga_load(Altera_desc *desc, const
> > void *rbf_data, size_t rbf_size)
> >  
> >  	return fpgamgr_program_finish();
> >  }
> > +
> > +#if defined(CONFIG_CMD_FPGA_LOADFS)
> > +const char *get_cff_filename(const void *fdt, int *len, u32 core)
> > +{
> > +	const char *cff_filename = NULL;
> > +	const char *cell;
> > +	int nodeoffset;
> > +	nodeoffset = fdtdec_next_compatible(fdt, 0,
> > +			 COMPAT_ALTERA_SOCFPGA_FPGA0);
> > +
> > +	if (nodeoffset >= 0) {
> > +		if (core)
> > +			cell = fdt_getprop(fdt,
> > +					nodeoffset,
> > +					"bitstream_core",
> > +					len);
> > +		else
> > +			cell = fdt_getprop(fdt, nodeoffset,
> > "bitstream_periph",
> > +					 len);
> > +
> > +		if (cell)
> > +			cff_filename = cell;
> > +	}
> > +
> > +	return cff_filename;
> > +}
> > +
> > +const char *get_cff_devpart(const void *fdt, int *len)
> > +{
> > +	const char *cff_devpart = NULL;
> > +	const char *cell;
> > +	int nodeoffset;
> > +	nodeoffset = fdtdec_next_compatible(fdt, 0,
> > +			 COMPAT_ALTERA_SOCFPGA_FPGA0);
> > +
> > +	cell = fdt_getprop(fdt, nodeoffset, "bitstream_devpart",
> > len);
> > +
> > +	if (cell)
> > +		cff_devpart = cell;
> > +
> > +	return cff_devpart;
> > +}
> Take a look at splash*.c , I believe that can be reworked into
> generic
> firmware loader , which you could then use here.
> 
> [...]
> 
> > 
> > diff --git a/include/configs/socfpga_common.h
> > b/include/configs/socfpga_common.h
> > index 9897e11..eadce2d 100644
> > --- a/include/configs/socfpga_common.h
> > +++ b/include/configs/socfpga_common.h
> > @@ -27,7 +27,11 @@
> >   */
> >  #define CONFIG_NR_DRAM_BANKS		1
> >  #define PHYS_SDRAM_1			0x0
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >  #define CONFIG_SYS_MALLOC_LEN		(64 * 1024 * 1024)
> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +#define CONFIG_SYS_MALLOC_LEN		(128 * 1024 * 1024)
> > +#endif
> You definitely don't need 128 MiB of malloc area.
> 
Okay, i will try out with smaller size.
> > 
> >  #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
> >  #define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
> >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > 
> 

[U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA RBF properties at Arria 10 FPGA manager

[Chee, Tien Fong]

On Isn, 2017-09-25 at 11:01 +0200, Marek Vasut wrote:
> On 09/25/2017 10:39 AM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > This patch adds description on properties about location of FPGA
> > RBFs are
> > stored, type and functionality of RBF used to configure FPGA.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> >  doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11
> > +++++++++++
> >  1 file changed, 11 insertions(+)
> > 
> > diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
> > mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
> > mgr.txt
> > index 2fd8e7a..7abb746 100644
> > --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> > +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> > @@ -7,6 +7,14 @@ Required properties:
> >                 - The second index is for writing FPGA
> > configuration data.
> >  - resets     : Phandle and reset specifier for the device's reset.
> >  - clocks     : Clocks used by the device.
> > +- bitstream_periph : FPGA peripheral raw binary file which is used
> > to
> > +                     initialize FPGA IOs, PLL, IO48 and DDR.
> > +- bitstream_core : FPGA core raw binary file contains FPGA design
> > which is used
> > +                   to program FPGA CRAM and ERAM.
> > +- bitstream_devpart : Partition of flash device where bitstream
> > files are
> > +		       stored.
> > +                      <dev[:part]> - dev is flash device number,
> > part is flash
> > +                                     device partition.
> >  
> >  Example:
> >  
> > @@ -16,4 +24,7 @@ Example:
> >  		       0xffcfe400 0x20>;
> >  		clocks = <&l4_mp_clk>;
> >  		resets = <&rst FPGAMGR_RESET>;
> > +		bitstream_periph =
> > "ghrd_10as066n2.periph.rbf.mkimage";
> > +		bitstream_core =
> > "ghrd_10as066n2.core.rbf.mkimage";
> > +		bitstream_devpart = "0:1";
> These should probably be altr,something-something ... they are
> definitely not generic bindings
> 
Okay.
> > 
> >  	};
> > 
> 

[U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA RBF properties at Arria 10 FPGA manager

[Chee, Tien Fong]

On Isn, 2017-09-25 at 11:00 +0200, Marek Vasut wrote:
> On 09/25/2017 10:39 AM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > This patch adds description on properties about location of FPGA
> > RBFs are
> > stored, type and functionality of RBF used to configure FPGA.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> Why does this patch have different tags than 1/19 ? Please keep
> things
> consistent ...
> 
Not get you. What's you means for tags?
> > 
> > ---
> >  doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11
> > +++++++++++
> >  1 file changed, 11 insertions(+)
> > 
> > diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
> > mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
> > mgr.txt
> > index 2fd8e7a..7abb746 100644
> > --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> > +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> > @@ -7,6 +7,14 @@ Required properties:
> >                 - The second index is for writing FPGA
> > configuration data.
> >  - resets     : Phandle and reset specifier for the device's reset.
> >  - clocks     : Clocks used by the device.
> > +- bitstream_periph : FPGA peripheral raw binary file which is used
> > to
> > +                     initialize FPGA IOs, PLL, IO48 and DDR.
> > +- bitstream_core : FPGA core raw binary file contains FPGA design
> > which is used
> > +                   to program FPGA CRAM and ERAM.
> > +- bitstream_devpart : Partition of flash device where bitstream
> > files are
> > +		       stored.
> > +                      <dev[:part]> - dev is flash device number,
> > part is flash
> > +                                     device partition.
> >  
> >  Example:
> >  
> > @@ -16,4 +24,7 @@ Example:
> >  		       0xffcfe400 0x20>;
> >  		clocks = <&l4_mp_clk>;
> >  		resets = <&rst FPGAMGR_RESET>;
> > +		bitstream_periph =
> > "ghrd_10as066n2.periph.rbf.mkimage";
> > +		bitstream_core =
> > "ghrd_10as066n2.core.rbf.mkimage";
> > +		bitstream_devpart = "0:1";
> >  	};
> > 
> 

[U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA from flash

[Chee, Tien Fong]

On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:
> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > These drivers handle FPGA program operation from flash loading
> > RBF to memory and then to program FPGA.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> Did you run checkpatch on this before submitting ? I presume no ...
> 
> > 
> > ---
> >  .../include/mach/fpga_manager_arria10.h            |  27 ++
> >  drivers/fpga/socfpga_arria10.c                     | 391
> > ++++++++++++++++++++-
> >  include/altera.h                                   |   6 +
> >  include/configs/socfpga_common.h                   |   4 +
> >  4 files changed, 425 insertions(+), 3 deletions(-)
> [...]
> 
> > 
> > @@ -112,13 +122,14 @@ static int
> > wait_for_nconfig_pin_and_nstatus_pin(void)
> >  	unsigned long mask =
> > ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
> >  				ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATU
> > S_PIN_SET_MSK;
> >  
> > -	/* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop
> > until de-asserted,
> > -	 * timeout at 1000ms
> > +	/*
> > +	 * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop
> > until
> > +	 * de-asserted, timeout at 1000ms
> >  	 */
> >  	return wait_for_bit(__func__,
> >  			    &fpga_manager_base->imgcfg_stat,
> >  			    mask,
> > -			    false, FPGA_TIMEOUT_MSEC, false);
> > +			    true, FPGA_TIMEOUT_MSEC, false);
> >  }
> Seems more like a fix, split this out.
> 
> > 
> >  static int wait_for_f2s_nstatus_pin(unsigned long value)
> > @@ -469,6 +480,7 @@ int socfpga_load(Altera_desc *desc, const void
> > *rbf_data, size_t rbf_size)
> >  
> >  	/* Initialize the FPGA Manager */
> >  	status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
> > +
> >  	if (status)
> >  		return status;
> >  
> > @@ -477,3 +489,376 @@ int socfpga_load(Altera_desc *desc, const
> > void *rbf_data, size_t rbf_size)
> >  
> >  	return fpgamgr_program_finish();
> >  }
> > +
> > +#if defined(CONFIG_CMD_FPGA_LOADFS)
> > +const char *get_cff_filename(const void *fdt, int *len, u32 core)
> > +{
> > +	const char *cff_filename = NULL;
> > +	const char *cell;
> > +	int nodeoffset;
> > +	nodeoffset = fdtdec_next_compatible(fdt, 0,
> > +			 COMPAT_ALTERA_SOCFPGA_FPGA0);
> > +
> > +	if (nodeoffset >= 0) {
> > +		if (core)
> > +			cell = fdt_getprop(fdt,
> > +					nodeoffset,
> > +					"bitstream_core",
> > +					len);
> > +		else
> > +			cell = fdt_getprop(fdt, nodeoffset,
> > "bitstream_periph",
> > +					 len);
> > +
> > +		if (cell)
> > +			cff_filename = cell;
> > +	}
> > +
> > +	return cff_filename;
> > +}
> > +
> > +const char *get_cff_devpart(const void *fdt, int *len)
> > +{
> > +	const char *cff_devpart = NULL;
> > +	const char *cell;
> > +	int nodeoffset;
> > +	nodeoffset = fdtdec_next_compatible(fdt, 0,
> > +			 COMPAT_ALTERA_SOCFPGA_FPGA0);
> > +
> > +	cell = fdt_getprop(fdt, nodeoffset, "bitstream_devpart",
> > len);
> > +
> > +	if (cell)
> > +		cff_devpart = cell;
> > +
> > +	return cff_devpart;
> > +}
> Take a look at splash*.c , I believe that can be reworked into
> generic
> firmware loader , which you could then use here.
> 
the devpart is hard coded in splash*.c. The function here is getting
devpart info from DTS. So, is there any similar function in splash*.c?
May be you can share more about your idea.
> [...]
> 
> > 
> > diff --git a/include/configs/socfpga_common.h
> > b/include/configs/socfpga_common.h
> > index 9897e11..eadce2d 100644
> > --- a/include/configs/socfpga_common.h
> > +++ b/include/configs/socfpga_common.h
> > @@ -27,7 +27,11 @@
> >   */
> >  #define CONFIG_NR_DRAM_BANKS		1
> >  #define PHYS_SDRAM_1			0x0
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >  #define CONFIG_SYS_MALLOC_LEN		(64 * 1024 * 1024)
> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +#define CONFIG_SYS_MALLOC_LEN		(128 * 1024 * 1024)
> > +#endif
> You definitely don't need 128 MiB of malloc area.
> 
> > 
> >  #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
> >  #define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
> >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > 
> 

[U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA RBF properties at Arria 10 FPGA manager

[Marek Vasut]

On 09/26/2017 10:54 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:00 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:39 AM, tien.fong.chee at intel.com wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>
>>> This patch adds description on properties about location of FPGA
>>> RBFs are
>>> stored, type and functionality of RBF used to configure FPGA.
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>> Why does this patch have different tags than 1/19 ? Please keep
>> things
>> consistent ...
>>
> Not get you. What's you means for tags?

ARM: socfpga: , not the random doc: dtbinding: .
Heck, the first and second patch change the same file, yet have
different tags, why ?

>>> ---
>>>  doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11
>>> +++++++++++
>>>  1 file changed, 11 insertions(+)
>>>
>>> diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
>>> mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
>>> mgr.txt
>>> index 2fd8e7a..7abb746 100644
>>> --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
>>> +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
>>> @@ -7,6 +7,14 @@ Required properties:
>>>                 - The second index is for writing FPGA
>>> configuration data.
>>>  - resets     : Phandle and reset specifier for the device's reset.
>>>  - clocks     : Clocks used by the device.
>>> +- bitstream_periph : FPGA peripheral raw binary file which is used
>>> to
>>> +                     initialize FPGA IOs, PLL, IO48 and DDR.
>>> +- bitstream_core : FPGA core raw binary file contains FPGA design
>>> which is used
>>> +                   to program FPGA CRAM and ERAM.
>>> +- bitstream_devpart : Partition of flash device where bitstream
>>> files are
>>> +		       stored.
>>> +                      <dev[:part]> - dev is flash device number,
>>> part is flash
>>> +                                     device partition.
>>>  
>>>  Example:
>>>  
>>> @@ -16,4 +24,7 @@ Example:
>>>  		       0xffcfe400 0x20>;
>>>  		clocks = <&l4_mp_clk>;
>>>  		resets = <&rst FPGAMGR_RESET>;
>>> +		bitstream_periph =
>>> "ghrd_10as066n2.periph.rbf.mkimage";
>>> +		bitstream_core =
>>> "ghrd_10as066n2.core.rbf.mkimage";
>>> +		bitstream_devpart = "0:1";
>>>  	};
>>>


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA from flash

[Marek Vasut]

On 09/26/2017 10:30 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>
>>> These drivers handle FPGA program operation from flash loading
>>> RBF to memory and then to program FPGA.
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>> Did you run checkpatch on this before submitting ? I presume no ...
>>
> Yeah, i run checkpatch for all patches. What's the issue here?

It should definitely indicate problem with ie. yoda-notation
+if (0 == flashinfo->remaining) {
and indent ...

>>>
>>> ---
>>>  .../include/mach/fpga_manager_arria10.h            |  27 ++
>>>  drivers/fpga/socfpga_arria10.c                     | 391
>>> ++++++++++++++++++++-
>>>  include/altera.h                                   |   6 +
>>>  include/configs/socfpga_common.h                   |   4 +
>>>  4 files changed, 425 insertions(+), 3 deletions(-)
>> [...]
>>
>>>
>>> @@ -112,13 +122,14 @@ static int
>>> wait_for_nconfig_pin_and_nstatus_pin(void)
>>>  	unsigned long mask =
>>> ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
>>>  				ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATU
>>> S_PIN_SET_MSK;
>>>  
>>> -	/* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop
>>> until de-asserted,
>>> -	 * timeout at 1000ms
>>> +	/*
>>> +	 * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop
>>> until
>>> +	 * de-asserted, timeout at 1000ms
>>>  	 */
>>>  	return wait_for_bit(__func__,
>>>  			    &fpga_manager_base->imgcfg_stat,
>>>  			    mask,
>>> -			    false, FPGA_TIMEOUT_MSEC, false);
>>> +			    true, FPGA_TIMEOUT_MSEC, false);
>>>  }
>> Seems more like a fix, split this out.
>>
> Okay.
>>>
>>>  static int wait_for_f2s_nstatus_pin(unsigned long value)
>>> @@ -469,6 +480,7 @@ int socfpga_load(Altera_desc *desc, const void
>>> *rbf_data, size_t rbf_size)
>>>  
>>>  	/* Initialize the FPGA Manager */
>>>  	status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
>>> +
>>>  	if (status)
>>>  		return status;
>>>  
>>> @@ -477,3 +489,376 @@ int socfpga_load(Altera_desc *desc, const
>>> void *rbf_data, size_t rbf_size)
>>>  
>>>  	return fpgamgr_program_finish();
>>>  }
>>> +
>>> +#if defined(CONFIG_CMD_FPGA_LOADFS)
>>> +const char *get_cff_filename(const void *fdt, int *len, u32 core)
>>> +{
>>> +	const char *cff_filename = NULL;
>>> +	const char *cell;
>>> +	int nodeoffset;
>>> +	nodeoffset = fdtdec_next_compatible(fdt, 0,
>>> +			 COMPAT_ALTERA_SOCFPGA_FPGA0);
>>> +
>>> +	if (nodeoffset >= 0) {
>>> +		if (core)
>>> +			cell = fdt_getprop(fdt,
>>> +					nodeoffset,
>>> +					"bitstream_core",
>>> +					len);
>>> +		else
>>> +			cell = fdt_getprop(fdt, nodeoffset,
>>> "bitstream_periph",
>>> +					 len);
>>> +
>>> +		if (cell)
>>> +			cff_filename = cell;
>>> +	}
>>> +
>>> +	return cff_filename;
>>> +}
>>> +
>>> +const char *get_cff_devpart(const void *fdt, int *len)
>>> +{
>>> +	const char *cff_devpart = NULL;
>>> +	const char *cell;
>>> +	int nodeoffset;
>>> +	nodeoffset = fdtdec_next_compatible(fdt, 0,
>>> +			 COMPAT_ALTERA_SOCFPGA_FPGA0);
>>> +
>>> +	cell = fdt_getprop(fdt, nodeoffset, "bitstream_devpart",
>>> len);
>>> +
>>> +	if (cell)
>>> +		cff_devpart = cell;
>>> +
>>> +	return cff_devpart;
>>> +}
>> Take a look at splash*.c , I believe that can be reworked into
>> generic
>> firmware loader , which you could then use here.

This is important here, I don't want yet another ad-hoc loader ...

>> [...]
>>
>>>
>>> diff --git a/include/configs/socfpga_common.h
>>> b/include/configs/socfpga_common.h
>>> index 9897e11..eadce2d 100644
>>> --- a/include/configs/socfpga_common.h
>>> +++ b/include/configs/socfpga_common.h
>>> @@ -27,7 +27,11 @@
>>>   */
>>>  #define CONFIG_NR_DRAM_BANKS		1
>>>  #define PHYS_SDRAM_1			0x0
>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>  #define CONFIG_SYS_MALLOC_LEN		(64 * 1024 * 1024)
>>> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>> +#define CONFIG_SYS_MALLOC_LEN		(128 * 1024 * 1024)
>>> +#endif
>> You definitely don't need 128 MiB of malloc area.
>>
> Okay, i will try out with smaller size.

Why do you need such massive area ? It's not a matter of "try out", you
should know why this change was needed for your use-case.

>>>
>>>  #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
>>>  #define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
>>>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 10/19] arm: socfpga: Rename the gen5 sdram driver to more specific name

[Marek Vasut]

On 09/26/2017 10:23 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:15 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>
>>> Current sdram driver is only applied to gen5 device, hence it is
>>> better
>>> to rename sdram driver to more specific name which is related to
>>> gen5
>>> device.
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>> ---
>>>  arch/arm/mach-socfpga/include/mach/sdram.h         | 434 +------
>>> --------------
>>>  .../include/mach/{sdram.h => sdram_gen5.h}         |   6 +-
>>>  drivers/ddr/altera/Makefile                        |   2 +-
>>>  drivers/ddr/altera/{sdram.c => sdram_gen5.c}       |   0
>>>  4 files changed, 8 insertions(+), 434 deletions(-)
>>>  copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h}
>>> (99%)
>>>  rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)
>>>
>>> diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
>>> b/arch/arm/mach-socfpga/include/mach/sdram.h
>>> index b11228f..4a9754e 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/sdram.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
>>> @@ -1,5 +1,5 @@
>>>  /*
>>> - * Copyright Altera Corporation (C) 2014-2015
>>> + * Copyright (C) 2017 Intel Corporation <www.intel.com>
>> Retain the old copyright ?
>>
> Okay.
>>>
>>>   *
>>>   * SPDX-License-Identifier:	GPL-2.0+
>>>   */
>>> @@ -8,435 +8,9 @@
>>>  
>>>  #ifndef __ASSEMBLY__
>> What's with this massive deletion here ?
>>
> Move to sdram_gen5.h . This header should contain common stuff.

Then where did the + part go ?

>>>
>>> -unsigned long sdram_calculate_size(void);
>>> -int sdram_mmr_init_full(unsigned int sdr_phy_reg);
>>> -int sdram_calibration_full(void);
>>> -
>>> -const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
>>> -
>>> -void socfpga_get_seq_ac_init(const u32 **init, unsigned int
>>> *nelem);
>>> -void socfpga_get_seq_inst_init(const u32 **init, unsigned int
>>> *nelem);
>>> -const struct socfpga_sdram_rw_mgr_config
>>> *socfpga_get_sdram_rwmgr_config(void);
>> [...]


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size initialization function

[Marek Vasut]

On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:15 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>
>>> Add function for both multiple DRAM bank and single DRAM bank size
>>> initialization. This common functionality could be used by every
>>> single
>>> SOCFPGA board.
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>> I'd like TB on Gen5.
>>
> What is TB?

Tested-by

>>>
>>> ---
>>>  arch/arm/mach-socfpga/board.c    | 7 +++++++
>>>  include/configs/socfpga_common.h | 1 +
>>>  2 files changed, 8 insertions(+)
>>>
>>> diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-
>>> socfpga/board.c
>>> index a41d089..965f9dc 100644
>>> --- a/arch/arm/mach-socfpga/board.c
>>> +++ b/arch/arm/mach-socfpga/board.c
>>> @@ -29,6 +29,13 @@ int board_init(void)
>>>  	return 0;
>>>  }
>>>  
>>> +int dram_init_banksize(void)
>>> +{
>>> +	fdtdec_setup_memory_banksize();
>>> +
>>> +	return 0;
>>> +}
>>> +
>>>  #ifdef CONFIG_USB_GADGET
>>>  struct dwc2_plat_otg_data socfpga_otg_data = {
>>>  	.usb_gusbcfg	= 0x1417,
>>> diff --git a/include/configs/socfpga_common.h
>>> b/include/configs/socfpga_common.h
>>> index eadce2d..7549ee8 100644
>>> --- a/include/configs/socfpga_common.h
>>> +++ b/include/configs/socfpga_common.h
>>> @@ -47,6 +47,7 @@
>>>  	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
>>>  
>>>  #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
>>> +#define CONFIG_SYS_SDRAM_SIZE		PHYS_SDRAM_1_SIZE
>>>  #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
>>>  #define CONFIG_SYS_TEXT_BASE		0x08000040
>>>  #else
>>>


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for Arria 10

[Marek Vasut]

On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:19 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>
>>> Add DDR driver suppport for Arria 10.
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>> ---
>>>  arch/arm/mach-socfpga/include/mach/sdram.h         |   2 +
>>>  arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-
>>>  drivers/ddr/altera/sdram_arria10.c                 | 735
>>> +++++++++++++++++++++
>>>  3 files changed, 839 insertions(+), 1 deletion(-)
>>>  create mode 100644 drivers/ddr/altera/sdram_arria10.c
>>>
>>> diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
>>> b/arch/arm/mach-socfpga/include/mach/sdram.h
>>> index 4a9754e..b833fc2 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/sdram.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
>>> @@ -10,6 +10,8 @@
>>>  
>>>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>  #include <asm/arch/sdram_gen5.h>
>>> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>> +#include <asm/arch/sdram_arria10.h>
>>>  #endif
>>>  
>>>  #endif
>>> diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
>>> b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
>>> index 1d7b7c1..7af9431 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
>>> @@ -1,5 +1,5 @@
>>>  /*
>>> - * Copyright (C) 2015-2017 Intel Corporation <www.intel.com>
>>> + * Copyright (C) 2017 Intel Corporation <www.intel.com>
>>>   *
>>>   * SPDX-License-Identifier:	GPL-2.0
>>>   */
>>> @@ -8,6 +8,7 @@
>>>  #define _SOCFPGA_SDRAM_ARRIA10_H_
>>>  
>>>  #ifndef __ASSEMBLY__
>>> +int ddr_calibration_sequence(void);
>>>  
>>>  struct socfpga_ecc_hmc {
>>>  	u32 ip_rev_id;
>>> @@ -204,6 +205,106 @@ struct socfpga_io48_mmr {
>>>  	u32 niosreserve1;
>>>  	u32 niosreserve2;
>>>  };
>>> +
>>> +union dramaddrw_reg {
>>> +	struct {
>>> +		u32 cfg_col_addr_width:5;
>>> +		u32 cfg_row_addr_width:5;
>>> +		u32 cfg_bank_addr_width:4;
>>> +		u32 cfg_bank_group_addr_width:2;
>>> +		u32 cfg_cs_addr_width:3;
>>> +		u32 reserved:13;
>>> +	};
>> Use regular macros for bitfields, not this crap.
>>
> Why regular macros is prefered? Above implementation improve
> readability, simplify the implementation and saving memory.

Because that's how U-Boot does it (and the above afair breaks on
different endianness).

>>>
>>> +	u32 word;
>>> +};
>>> +
>>> +union ctrlcfg0_reg {
>>> +	struct {
>>> +		u32 cfg_mem_type:4;
>>> +		u32 cfg_dimm_type:3;
>>> +		u32 cfg_ac_pos:2;
>>> +		u32 cfg_ctrl_burst_len:5;
>>> +		u32 reserved:18;  /* Other fields unused */
>>> +	};
>>> +	u32 word;
>>> +};
>> [...]

[...]

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory allocation in SPL

[Marek Vasut]

On 09/26/2017 07:06 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:21 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>
>>> Add support to memory allocation in SPL for preparation to enable
>>> FAT
>>> in SPL. Memory allocation is needed by FAT to work properly.
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>> Gen 5 does have malloc support in SPL, so what's the deal here ?
>>
> For FAT to work properly in Arria 10 SPL, SPL malloc need to be
> enabled,

It is already enabled on Gen 5

> and the min of SPL malloc size is 0x2000.

Where did you find about this minimum ? That can be configured ...

> FAT needed in Arria
> 10 SPL, because u-boot.img is stored in FAT partition.

It can also be stored on ext partition (which is preferred, patent-wise)

>>>
>>> ---
>>>  include/configs/socfpga_common.h | 23 ++++++++++++++++++++++-
>>>  1 file changed, 22 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/include/configs/socfpga_common.h
>>> b/include/configs/socfpga_common.h
>>> index 7549ee8..9b6719e 100644
>>> --- a/include/configs/socfpga_common.h
>>> +++ b/include/configs/socfpga_common.h
>>> @@ -280,17 +280,34 @@ unsigned int
>>> cm_get_qspi_controller_clk_hz(void);
>>>  /*
>>>   * SPL
>>>   *
>>> - * SRAM Memory layout:
>>> + * SRAM Memory layout for gen 5:
>>>   *
>>>   * 0xFFFF_0000 ...... Start of SRAM
>>>   * 0xFFFF_xxxx ...... Top of stack (grows down)
>>>   * 0xFFFF_yyyy ...... Malloc area
>>>   * 0xFFFF_zzzz ...... Global Data
>>>   * 0xFFFF_FF00 ...... End of SRAM
>>> + *
>>> + * SRAM Memory layout for Arria 10:
>>> + * 0xFFE0_0000 ...... Start of SRAM (bottom)
>>> + * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
>>> + * 0xFFEy_yyyy ...... Malloc area (grows up to top)
>>> + * 0xFFEz_zzzz ...... Global Data
>>> + * 0xFFE3_FFFF ...... End of SRAM (top)
>>>   */
>>>  #define CONFIG_SPL_FRAMEWORK
>>>  #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_AD
>>> DR
>>>  #define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZ
>>> E
>>> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>> +/* SPL memory allocation configuration, it is required by FAT
>>> feature */
>>> +#ifndef CONFIG_SYS_SPL_MALLOC_START
>>> +#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00002000
>>> +#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_INIT_RAM_SI
>>> ZE - \
>>> +					 GENERATED_GBL_DATA_SIZE -
>>> \
>>> +					 CONFIG_SYS_SPL_MALLOC_SIZ
>>> E + \
>>> +					 CONFIG_SYS_INIT_RAM_ADDR)
>>> +#endif
>>> +#endif
>>>  
>>>  /* SPL SDMMC boot support */
>>>  #ifdef CONFIG_SPL_MMC_SUPPORT
>>> @@ -320,7 +337,11 @@ unsigned int
>>> cm_get_qspi_controller_clk_hz(void);
>>>  /*
>>>   * Stack setup
>>>   */
>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>  #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
>>> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>> +#define CONFIG_SPL_STACK		(CONFIG_SYS_SPL_MALLOC_STA
>>> RT - 1)
>>> +#endif
>>>  
>>>  /* Extra Environment */
>>>  #ifndef CONFIG_SPL_BUILD
>>>


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10

[Marek Vasut]

On 09/26/2017 06:42 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>
>>> Enhance preloader header with both additional program length and
>>> program
>>> entry offset attributes, which offset is relative to the start of
>>> program
>>> header.
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>> ---
>>>  arch/arm/mach-socfpga/include/mach/boot0.h | 11 +++++++++--
>>>  1 file changed, 9 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h
>>> b/arch/arm/mach-socfpga/include/mach/boot0.h
>>> index 22d9e7f..33c9368 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/boot0.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
>>> @@ -11,8 +11,15 @@
>>>  	.balignl 64,0xf33db33f;
>>>  
>>>  	.word	0x1337c0d3;	/* SoCFPGA preloader
>>> validation word */
>>> -	.word	0xc01df00d;	/* Version, flags, length
>>> */
>>> -	.word	0xcafec0d3;	/* Checksum, zero-pad */
>>> +	.word	0xc01df00d; /* Header
>>> length(2B),flags(1B),version(1B) */
>>> +#ifndef CONFIG_TARGET_SOCFPGA_GEN5
>>> +	.word	0xfeedface; /* Program length(4B) */
>> Keep this indent intact, then it won't generate these crappy -
>> entries.
>>
> Are you saying to keep the comment indent intact, and allign with 1st
> comment  /* SoCFPGA preloader validation word */ ?

Just look at the diff and make sure that it only changes the relevant
parts, not extras due to indent changes.

>>>
>>> +	.word	0xf00dcafe; /*
>>> +			     * Program entry offset(4B),relative
>>> to
>>> +			     * the start of program header
>>> +			     */
>>> +#endif
>>> +	.word	0xcafec0d3;	/* Simple
>>> checksum(2B),spare offset(2B) */
>>>  	nop;
>>>  
>>>  	b reset;		/* SoCFPGA jumps here */
>>>


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 19/19] arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot

[Marek Vasut]

On 09/26/2017 06:31 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:24 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>
>>> Enable SPL loading U-boot from SDMMC to DDR and booting U-boot.
>> This patch seems to be doing more than just one thing ...
>>
> I can split into two patches:
> 1) Enable DDR up by configuring FPGA so SPL able loading U-boot to DDR
> 2) Setting up configs so SPL can boot U-boot from FAT.

Split it so that one patch does one thing.

>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>> ---
>>>  arch/arm/mach-socfpga/spl.c       | 55
>>> +++++++++++++++++++++++++++++++++++++
>>>  common/spl/spl_mmc.c              |  2 +-
>>>  configs/socfpga_arria10_defconfig | 57
>>> ++++++++++++++++++++++++++++++++++-----
>>>  include/spl.h                     |  2 ++
>>>  4 files changed, 108 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-
>>> socfpga/spl.c
>>> index aba116d..9b381bb 100644
>>> --- a/arch/arm/mach-socfpga/spl.c
>>> +++ b/arch/arm/mach-socfpga/spl.c
>>> @@ -15,6 +15,7 @@
>>>  #include <asm/arch/system_manager.h>
>>>  #include <asm/arch/freeze_controller.h>
>>>  #include <asm/arch/clock_manager.h>
>>> +#include <asm/arch/fpga_manager.h>
>>>  #include <asm/arch/misc.h>
>>>  #include <asm/arch/scan_manager.h>
>>>  #include <asm/arch/sdram.h>
>>> @@ -22,6 +23,10 @@
>>>  #include <asm/arch/nic301.h>
>>>  #include <asm/sections.h>
>>>  #include <fdtdec.h>
>>> +#include <fat.h>
>>> +#include <fs.h>
>>> +#include <linux/ctype.h>
>>> +#include <mmc.h>
>>>  #include <watchdog.h>
>>>  #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>>  #include <asm/arch/pinmux.h>
>>> @@ -29,6 +34,9 @@
>>>  
>>>  DECLARE_GLOBAL_DATA_PTR;
>>>  
>>> +#define BSIZE	4096
>>> +#define PERIPH_RBF	0
>>> +
>>>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>  static struct pl310_regs *const pl310 =
>>>  	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
>>> @@ -197,6 +205,12 @@ void board_init_f(ulong dummy)
>>>  #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>>  void spl_board_init(void)
>>>  {
>>> +	int rval = 0;
>>> +	int len = 0;
>>> +	u32 buffer[BSIZE] __aligned(ARCH_DMA_MINALIGN);
>>> +	struct spl_boot_device bootdev;
>>> +	fpga_fs_info fpga_fsinfo;
>>> +
>>>  	/* configuring the clock based on handoff */
>>>  	cm_basic_init(gd->fdt_blob);
>>>  	WATCHDOG_RESET();
>>> @@ -214,6 +228,47 @@ void spl_board_init(void)
>>>  
>>>  	/* Add device descriptor to FPGA device table */
>>>  	socfpga_fpga_add();
>>> +
>>> +	bootdev.boot_device = spl_boot_device();
>>> +
>>> +	if (BOOT_DEVICE_MMC1 == bootdev.boot_device) {
>>> +		struct mmc *mmc = NULL;
>>> +		int err = 0;
>>> +
>>> +		spl_mmc_find_device(&mmc, bootdev.boot_device);
>>> +
>>> +		err = mmc_init(mmc);
>>> +
>>> +		if (err) {
>>> +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
>>> +			printf("spl: mmc init failed with error:
>>> %d\n", err);
>>> +#endif
>>> +		}
>>> +
>>> +		fpga_fsinfo.dev_part = (char *)get_cff_devpart(gd-
>>>> fdt_blob,
>>> +								 &
>>> len);
>>> +
>>> +		fpga_fsinfo.filename = (char
>>> *)get_cff_filename(gd->fdt_blob,
>>> +								 &
>>> len,
>>> +								PE
>>> RIPH_RBF);
>>> +
>>> +		fpga_fsinfo.interface = "mmc";
>>> +
>>> +		fpga_fsinfo.fstype = FS_TYPE_FAT;
>>> +	} else {
>>> +		printf("Invalid boot device!\n");
>>> +		return;
>>> +	}
>>> +
>>> +	/* Program peripheral RBF */
>>> +	if (fpga_fsinfo.filename && fpga_fsinfo.dev_part && (len >
>>> 0))
>>> +		rval = fpga_fsload(0, buffer, BSIZE,
>>> &fpga_fsinfo);
>>> +
>>> +	if (rval > 0) {
>>> +		config_pins(gd->fdt_blob, "shared");
>>> +
>>> +		ddr_calibration_sequence();
>>> +	}
>>>  }
>>>  
>>>  void board_init_f(ulong dummy)
>>> diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
>>> index b2cccc6..159443f 100644
>>> --- a/common/spl/spl_mmc.c
>>> +++ b/common/spl/spl_mmc.c
>>> @@ -113,7 +113,7 @@ static int spl_mmc_get_device_index(u32
>>> boot_device)
>>>  	return -ENODEV;
>>>  }
>>>  
>>> -static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
>>> +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
>>>  {
>>>  #if CONFIG_IS_ENABLED(DM_MMC)
>>>  	struct udevice *dev;
>>> diff --git a/configs/socfpga_arria10_defconfig
>>> b/configs/socfpga_arria10_defconfig
>>> index 4c73d73..2ff9801 100644
>>> --- a/configs/socfpga_arria10_defconfig
>>> +++ b/configs/socfpga_arria10_defconfig
>>> @@ -2,33 +2,76 @@ CONFIG_ARM=y
>>>  CONFIG_ARCH_SOCFPGA=y
>>>  CONFIG_SYS_MALLOC_F_LEN=0x2000
>>>  CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
>>> +CONFIG_SPL_STACK_R_ADDR=0x00800000
>>>  CONFIG_IDENT_STRING="socfpga_arria10"
>>>  CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
>>> -CONFIG_USE_BOOTARGS=y
>>> -CONFIG_BOOTARGS="console=ttyS0,115200"
>>>  CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
>>> +CONFIG_FIT=y
>>> +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
>>> +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
>>> +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
>>> +CONFIG_SPL_ENV_SUPPORT=y
>>> +CONFIG_VERSION_VARIABLE=y
>>>  CONFIG_SPL=y
>>> +CONFIG_HUSH_PARSER=y
>>>  CONFIG_SPL_FPGA_SUPPORT=y
>>> +CONFIG_SPL_FAT_SUPPORT=y
>>> +CONFIG_FS_FAT_MAX_CLUSTSIZE=32768
>>>  CONFIG_CMD_BOOTZ=y
>>>  # CONFIG_CMD_IMLS is not set
>>>  CONFIG_CMD_ASKENV=y
>>>  CONFIG_CMD_GREPENV=y
>>>  # CONFIG_CMD_FLASH is not set
>>> -CONFIG_CMD_GPIO=y
>>> +CONFIG_SPL_LIBDISK_SUPPORT=y
>>> +CONFIG_CMD_PART=y
>>>  CONFIG_CMD_MMC=y
>>> +CONFIG_CMD_SF=y
>>> +CONFIG_CMD_SPI=y
>>> +CONFIG_CMD_I2C=y
>>> +CONFIG_SYS_I2C_DW=y
>>> +CONFIG_CMD_USB=y
>>> +CONFIG_CMD_DFU=y
>>> +CONFIG_CMD_USB_MASS_STORAGE=y
>>> +CONFIG_CMD_GPIO=y
>>> +CONFIG_CMD_MII=y
>>>  CONFIG_CMD_DHCP=y
>>>  CONFIG_CMD_PING=y
>>>  CONFIG_CMD_CACHE=y
>>> -CONFIG_CMD_EXT4=y
>>> -CONFIG_CMD_EXT4_WRITE=y
>>>  CONFIG_DOS_PARTITION=y
>>> -# CONFIG_SPL_DOS_PARTITION is not set
>>> -CONFIG_ENV_IS_IN_MMC=y
>>> +CONFIG_SPL_DOS_PARTITION=y
>>> +CONFIG_SPL_FS_GENERIC=y
>>> +CONFIG_CMD_FAT=y
>>> +CONFIG_CMD_FS_GENERIC=y
>>>  CONFIG_SPL_DM=y
>>>  CONFIG_SPL_DM_SEQ_ALIAS=y
>>> +CONFIG_DFU_MMC=y
>>>  CONFIG_FPGA_SOCFPGA=y
>>>  CONFIG_DM_GPIO=y
>>>  CONFIG_DWAPB_GPIO=y
>>>  CONFIG_DM_MMC=y
>>> +CONFIG_MMC_DW=y
>>> +CONFIG_SPI_FLASH=y
>>> +CONFIG_SPI_FLASH_BAR=y
>>> +CONFIG_SPI_FLASH_SPANSION=y
>>> +CONFIG_SPI_FLASH_STMICRO=y
>>> +CONFIG_DM_ETH=y
>>> +CONFIG_ETH_DESIGNWARE=y
>>>  CONFIG_SYS_NS16550=y
>>>  CONFIG_USE_TINY_PRINTF=y
>>> +CONFIG_CMD_FPGA_LOADFS=y
>>> +CONFIG_CADENCE_QSPI=y
>>> +CONFIG_DESIGNWARE_SPI=y
>>> +CONFIG_USB=y
>>> +CONFIG_DM_USB=y
>>> +CONFIG_USB_STORAGE=y
>>> +CONFIG_USB_GADGET=y
>>> +CONFIG_USB_GADGET_DWC2_OTG=y
>>> +CONFIG_USB_GADGET_DOWNLOAD=y
>>> +CONFIG_G_DNL_MANUFACTURER="altera"
>>> +CONFIG_G_DNL_VENDOR_NUM=0x0525
>>> +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
>>> +CONFIG_USE_TINY_PRINTF=y
>>> +CONFIG_SPL_MMC_SUPPORT=y
>>> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
>>> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
>>> +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
>>> diff --git a/include/spl.h b/include/spl.h
>>> index ce4cf0a..e24433d 100644
>>> --- a/include/spl.h
>>> +++ b/include/spl.h
>>> @@ -10,6 +10,7 @@
>>>  /* Platform-specific defines */
>>>  #include <linux/compiler.h>
>>>  #include <asm/spl.h>
>>> +#include <mmc.h>
>>>  
>>>  /* Value in r0 indicates we booted from U-Boot */
>>>  #define UBOOT_NOT_LOADED_FROM_SPL	0x13578642
>>> @@ -68,6 +69,7 @@ int spl_load_simple_fit(struct spl_image_info
>>> *spl_image,
>>>  void preloader_console_init(void);
>>>  u32 spl_boot_device(void);
>>>  u32 spl_boot_mode(const u32 boot_device);
>>> +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device);
>>>  
>>>  /**
>>>   * spl_set_header_raw_uboot() - Set up a standard SPL image
>>> structure
>>>


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA from flash

[Marek Vasut]

On 09/26/2017 11:52 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>
>>> These drivers handle FPGA program operation from flash loading
>>> RBF to memory and then to program FPGA.
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

[...]

>>> +const char *get_cff_devpart(const void *fdt, int *len)
>>> +{
>>> +	const char *cff_devpart = NULL;
>>> +	const char *cell;
>>> +	int nodeoffset;
>>> +	nodeoffset = fdtdec_next_compatible(fdt, 0,
>>> +			 COMPAT_ALTERA_SOCFPGA_FPGA0);
>>> +
>>> +	cell = fdt_getprop(fdt, nodeoffset, "bitstream_devpart",
>>> len);
>>> +
>>> +	if (cell)
>>> +		cff_devpart = cell;
>>> +
>>> +	return cff_devpart;
>>> +}
>> Take a look at splash*.c , I believe that can be reworked into
>> generic
>> firmware loader , which you could then use here.
>>
> the devpart is hard coded in splash*.c. The function here is getting
> devpart info from DTS. So, is there any similar function in splash*.c?
> May be you can share more about your idea.

The generic loader could use some work of course ...

[...]

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA RBF properties at Arria 10 FPGA manager

[Chee, Tien Fong]

On Sel, 2017-09-26 at 12:30 +0200, Marek Vasut wrote:
> On 09/26/2017 10:54 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2017-09-25 at 11:00 +0200, Marek Vasut wrote:
> > > 
> > > On 09/25/2017 10:39 AM, tien.fong.chee at intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > 
> > > > This patch adds description on properties about location of
> > > > FPGA
> > > > RBFs are
> > > > stored, type and functionality of RBF used to configure FPGA.
> > > > 
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > Why does this patch have different tags than 1/19 ? Please keep
> > > things
> > > consistent ...
> > > 
> > Not get you. What's you means for tags?
> ARM: socfpga: , not the random doc: dtbinding: .
> Heck, the first and second patch change the same file, yet have
> different tags, why ?
> 
I ported patch 01 from Linux, so i keep everything intact. For patch
02, i put doc:dtbinding because i think that is more descriptive to the
file i changed.
I can change to ARM:socfpga .
> > 
> > > 
> > > > 
> > > > ---
> > > >  doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> > > > | 11
> > > > +++++++++++
> > > >  1 file changed, 11 insertions(+)
> > > > 
> > > > diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-
> > > > fpga-
> > > > mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-
> > > > fpga-
> > > > mgr.txt
> > > > index 2fd8e7a..7abb746 100644
> > > > --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
> > > > mgr.txt
> > > > +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
> > > > mgr.txt
> > > > @@ -7,6 +7,14 @@ Required properties:
> > > >                 - The second index is for writing FPGA
> > > > configuration data.
> > > >  - resets     : Phandle and reset specifier for the device's
> > > > reset.
> > > >  - clocks     : Clocks used by the device.
> > > > +- bitstream_periph : FPGA peripheral raw binary file which is
> > > > used
> > > > to
> > > > +                     initialize FPGA IOs, PLL, IO48 and DDR.
> > > > +- bitstream_core : FPGA core raw binary file contains FPGA
> > > > design
> > > > which is used
> > > > +                   to program FPGA CRAM and ERAM.
> > > > +- bitstream_devpart : Partition of flash device where
> > > > bitstream
> > > > files are
> > > > +		       stored.
> > > > +                      <dev[:part]> - dev is flash device
> > > > number,
> > > > part is flash
> > > > +                                     device partition.
> > > >  
> > > >  Example:
> > > >  
> > > > @@ -16,4 +24,7 @@ Example:
> > > >  		       0xffcfe400 0x20>;
> > > >  		clocks = <&l4_mp_clk>;
> > > >  		resets = <&rst FPGAMGR_RESET>;
> > > > +		bitstream_periph =
> > > > "ghrd_10as066n2.periph.rbf.mkimage";
> > > > +		bitstream_core =
> > > > "ghrd_10as066n2.core.rbf.mkimage";
> > > > +		bitstream_devpart = "0:1";
> > > >  	};
> > > > 
> 

[U-Boot] [PATCH v2 19/19] arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot

[Chee, Tien Fong]

On Sel, 2017-09-26 at 12:38 +0200, Marek Vasut wrote:
> On 09/26/2017 06:31 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2017-09-25 at 11:24 +0200, Marek Vasut wrote:
> > > 
> > > On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > 
> > > > Enable SPL loading U-boot from SDMMC to DDR and booting U-boot.
> > > This patch seems to be doing more than just one thing ...
> > > 
> > I can split into two patches:
> > 1) Enable DDR up by configuring FPGA so SPL able loading U-boot to
> > DDR
> > 2) Setting up configs so SPL can boot U-boot from FAT.
> Split it so that one patch does one thing.
> 
Okay.
> > 
> > > 
> > > > 
> > > > 
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > ---
> > > >  arch/arm/mach-socfpga/spl.c       | 55
> > > > +++++++++++++++++++++++++++++++++++++
> > > >  common/spl/spl_mmc.c              |  2 +-
> > > >  configs/socfpga_arria10_defconfig | 57
> > > > ++++++++++++++++++++++++++++++++++-----
> > > >  include/spl.h                     |  2 ++
> > > >  4 files changed, 108 insertions(+), 8 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-
> > > > socfpga/spl.c
> > > > index aba116d..9b381bb 100644
> > > > --- a/arch/arm/mach-socfpga/spl.c
> > > > +++ b/arch/arm/mach-socfpga/spl.c
> > > > @@ -15,6 +15,7 @@
> > > >  #include <asm/arch/system_manager.h>
> > > >  #include <asm/arch/freeze_controller.h>
> > > >  #include <asm/arch/clock_manager.h>
> > > > +#include <asm/arch/fpga_manager.h>
> > > >  #include <asm/arch/misc.h>
> > > >  #include <asm/arch/scan_manager.h>
> > > >  #include <asm/arch/sdram.h>
> > > > @@ -22,6 +23,10 @@
> > > >  #include <asm/arch/nic301.h>
> > > >  #include <asm/sections.h>
> > > >  #include <fdtdec.h>
> > > > +#include <fat.h>
> > > > +#include <fs.h>
> > > > +#include <linux/ctype.h>
> > > > +#include <mmc.h>
> > > >  #include <watchdog.h>
> > > >  #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > >  #include <asm/arch/pinmux.h>
> > > > @@ -29,6 +34,9 @@
> > > >  
> > > >  DECLARE_GLOBAL_DATA_PTR;
> > > >  
> > > > +#define BSIZE	4096
> > > > +#define PERIPH_RBF	0
> > > > +
> > > >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > >  static struct pl310_regs *const pl310 =
> > > >  	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> > > > @@ -197,6 +205,12 @@ void board_init_f(ulong dummy)
> > > >  #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > >  void spl_board_init(void)
> > > >  {
> > > > +	int rval = 0;
> > > > +	int len = 0;
> > > > +	u32 buffer[BSIZE] __aligned(ARCH_DMA_MINALIGN);
> > > > +	struct spl_boot_device bootdev;
> > > > +	fpga_fs_info fpga_fsinfo;
> > > > +
> > > >  	/* configuring the clock based on handoff */
> > > >  	cm_basic_init(gd->fdt_blob);
> > > >  	WATCHDOG_RESET();
> > > > @@ -214,6 +228,47 @@ void spl_board_init(void)
> > > >  
> > > >  	/* Add device descriptor to FPGA device table */
> > > >  	socfpga_fpga_add();
> > > > +
> > > > +	bootdev.boot_device = spl_boot_device();
> > > > +
> > > > +	if (BOOT_DEVICE_MMC1 == bootdev.boot_device) {
> > > > +		struct mmc *mmc = NULL;
> > > > +		int err = 0;
> > > > +
> > > > +		spl_mmc_find_device(&mmc,
> > > > bootdev.boot_device);
> > > > +
> > > > +		err = mmc_init(mmc);
> > > > +
> > > > +		if (err) {
> > > > +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
> > > > +			printf("spl: mmc init failed with
> > > > error:
> > > > %d\n", err);
> > > > +#endif
> > > > +		}
> > > > +
> > > > +		fpga_fsinfo.dev_part = (char
> > > > *)get_cff_devpart(gd-
> > > > > 
> > > > > fdt_blob,
> > > > +								
> > > >  &
> > > > len);
> > > > +
> > > > +		fpga_fsinfo.filename = (char
> > > > *)get_cff_filename(gd->fdt_blob,
> > > > +								
> > > >  &
> > > > len,
> > > > +								
> > > > PE
> > > > RIPH_RBF);
> > > > +
> > > > +		fpga_fsinfo.interface = "mmc";
> > > > +
> > > > +		fpga_fsinfo.fstype = FS_TYPE_FAT;
> > > > +	} else {
> > > > +		printf("Invalid boot device!\n");
> > > > +		return;
> > > > +	}
> > > > +
> > > > +	/* Program peripheral RBF */
> > > > +	if (fpga_fsinfo.filename && fpga_fsinfo.dev_part &&
> > > > (len >
> > > > 0))
> > > > +		rval = fpga_fsload(0, buffer, BSIZE,
> > > > &fpga_fsinfo);
> > > > +
> > > > +	if (rval > 0) {
> > > > +		config_pins(gd->fdt_blob, "shared");
> > > > +
> > > > +		ddr_calibration_sequence();
> > > > +	}
> > > >  }
> > > >  
> > > >  void board_init_f(ulong dummy)
> > > > diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
> > > > index b2cccc6..159443f 100644
> > > > --- a/common/spl/spl_mmc.c
> > > > +++ b/common/spl/spl_mmc.c
> > > > @@ -113,7 +113,7 @@ static int spl_mmc_get_device_index(u32
> > > > boot_device)
> > > >  	return -ENODEV;
> > > >  }
> > > >  
> > > > -static int spl_mmc_find_device(struct mmc **mmcp, u32
> > > > boot_device)
> > > > +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
> > > >  {
> > > >  #if CONFIG_IS_ENABLED(DM_MMC)
> > > >  	struct udevice *dev;
> > > > diff --git a/configs/socfpga_arria10_defconfig
> > > > b/configs/socfpga_arria10_defconfig
> > > > index 4c73d73..2ff9801 100644
> > > > --- a/configs/socfpga_arria10_defconfig
> > > > +++ b/configs/socfpga_arria10_defconfig
> > > > @@ -2,33 +2,76 @@ CONFIG_ARM=y
> > > >  CONFIG_ARCH_SOCFPGA=y
> > > >  CONFIG_SYS_MALLOC_F_LEN=0x2000
> > > >  CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
> > > > +CONFIG_SPL_STACK_R_ADDR=0x00800000
> > > >  CONFIG_IDENT_STRING="socfpga_arria10"
> > > >  CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
> > > > -CONFIG_USE_BOOTARGS=y
> > > > -CONFIG_BOOTARGS="console=ttyS0,115200"
> > > >  CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
> > > > +CONFIG_FIT=y
> > > > +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> > > > +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
> > > > +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
> > > > +CONFIG_SPL_ENV_SUPPORT=y
> > > > +CONFIG_VERSION_VARIABLE=y
> > > >  CONFIG_SPL=y
> > > > +CONFIG_HUSH_PARSER=y
> > > >  CONFIG_SPL_FPGA_SUPPORT=y
> > > > +CONFIG_SPL_FAT_SUPPORT=y
> > > > +CONFIG_FS_FAT_MAX_CLUSTSIZE=32768
> > > >  CONFIG_CMD_BOOTZ=y
> > > >  # CONFIG_CMD_IMLS is not set
> > > >  CONFIG_CMD_ASKENV=y
> > > >  CONFIG_CMD_GREPENV=y
> > > >  # CONFIG_CMD_FLASH is not set
> > > > -CONFIG_CMD_GPIO=y
> > > > +CONFIG_SPL_LIBDISK_SUPPORT=y
> > > > +CONFIG_CMD_PART=y
> > > >  CONFIG_CMD_MMC=y
> > > > +CONFIG_CMD_SF=y
> > > > +CONFIG_CMD_SPI=y
> > > > +CONFIG_CMD_I2C=y
> > > > +CONFIG_SYS_I2C_DW=y
> > > > +CONFIG_CMD_USB=y
> > > > +CONFIG_CMD_DFU=y
> > > > +CONFIG_CMD_USB_MASS_STORAGE=y
> > > > +CONFIG_CMD_GPIO=y
> > > > +CONFIG_CMD_MII=y
> > > >  CONFIG_CMD_DHCP=y
> > > >  CONFIG_CMD_PING=y
> > > >  CONFIG_CMD_CACHE=y
> > > > -CONFIG_CMD_EXT4=y
> > > > -CONFIG_CMD_EXT4_WRITE=y
> > > >  CONFIG_DOS_PARTITION=y
> > > > -# CONFIG_SPL_DOS_PARTITION is not set
> > > > -CONFIG_ENV_IS_IN_MMC=y
> > > > +CONFIG_SPL_DOS_PARTITION=y
> > > > +CONFIG_SPL_FS_GENERIC=y
> > > > +CONFIG_CMD_FAT=y
> > > > +CONFIG_CMD_FS_GENERIC=y
> > > >  CONFIG_SPL_DM=y
> > > >  CONFIG_SPL_DM_SEQ_ALIAS=y
> > > > +CONFIG_DFU_MMC=y
> > > >  CONFIG_FPGA_SOCFPGA=y
> > > >  CONFIG_DM_GPIO=y
> > > >  CONFIG_DWAPB_GPIO=y
> > > >  CONFIG_DM_MMC=y
> > > > +CONFIG_MMC_DW=y
> > > > +CONFIG_SPI_FLASH=y
> > > > +CONFIG_SPI_FLASH_BAR=y
> > > > +CONFIG_SPI_FLASH_SPANSION=y
> > > > +CONFIG_SPI_FLASH_STMICRO=y
> > > > +CONFIG_DM_ETH=y
> > > > +CONFIG_ETH_DESIGNWARE=y
> > > >  CONFIG_SYS_NS16550=y
> > > >  CONFIG_USE_TINY_PRINTF=y
> > > > +CONFIG_CMD_FPGA_LOADFS=y
> > > > +CONFIG_CADENCE_QSPI=y
> > > > +CONFIG_DESIGNWARE_SPI=y
> > > > +CONFIG_USB=y
> > > > +CONFIG_DM_USB=y
> > > > +CONFIG_USB_STORAGE=y
> > > > +CONFIG_USB_GADGET=y
> > > > +CONFIG_USB_GADGET_DWC2_OTG=y
> > > > +CONFIG_USB_GADGET_DOWNLOAD=y
> > > > +CONFIG_G_DNL_MANUFACTURER="altera"
> > > > +CONFIG_G_DNL_VENDOR_NUM=0x0525
> > > > +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
> > > > +CONFIG_USE_TINY_PRINTF=y
> > > > +CONFIG_SPL_MMC_SUPPORT=y
> > > > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
> > > > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
> > > > +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
> > > > diff --git a/include/spl.h b/include/spl.h
> > > > index ce4cf0a..e24433d 100644
> > > > --- a/include/spl.h
> > > > +++ b/include/spl.h
> > > > @@ -10,6 +10,7 @@
> > > >  /* Platform-specific defines */
> > > >  #include <linux/compiler.h>
> > > >  #include <asm/spl.h>
> > > > +#include <mmc.h>
> > > >  
> > > >  /* Value in r0 indicates we booted from U-Boot */
> > > >  #define UBOOT_NOT_LOADED_FROM_SPL	0x13578642
> > > > @@ -68,6 +69,7 @@ int spl_load_simple_fit(struct spl_image_info
> > > > *spl_image,
> > > >  void preloader_console_init(void);
> > > >  u32 spl_boot_device(void);
> > > >  u32 spl_boot_mode(const u32 boot_device);
> > > > +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device);
> > > >  
> > > >  /**
> > > >   * spl_set_header_raw_uboot() - Set up a standard SPL image
> > > > structure
> > > > 
> 

[U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency info for U-boot

[Chee, Tien Fong]

On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:
> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > Clock frequency info is required in U-boot.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> I want a TB on Gen 5
> 
Okay.
> > 
> > ---
> >  arch/arm/mach-socfpga/board.c | 6 ++++++
> >  1 file changed, 6 insertions(+)
> > 
> > diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-
> > socfpga/board.c
> > index 965f9dc..a00f63b 100644
> > --- a/arch/arm/mach-socfpga/board.c
> > +++ b/arch/arm/mach-socfpga/board.c
> > @@ -8,7 +8,10 @@
> >  
> >  #include <common.h>
> >  #include <errno.h>
> > +#include <fdtdec.h>
> >  #include <asm/arch/reset_manager.h>
> > +#include <asm/arch/clock_manager.h>
> > +#include <asm/arch/misc.h>
> >  #include <asm/io.h>
> >  
> >  #include <usb.h>
> > @@ -26,6 +29,9 @@ int board_init(void)
> >  	/* Address of boot parameters for ATAG (if ATAG is used)
> > */
> >  	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> >  
> > +	/* configuring the clock based on handoff */
> > +	cm_basic_init(gd->fdt_blob);
> > +
> >  	return 0;
> >  }
> >  
> > 
> 

[U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10

[Chee, Tien Fong]

On Sel, 2017-09-26 at 12:37 +0200, Marek Vasut wrote:
> On 09/26/2017 06:42 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:
> > > 
> > > On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > 
> > > > Enhance preloader header with both additional program length
> > > > and
> > > > program
> > > > entry offset attributes, which offset is relative to the start
> > > > of
> > > > program
> > > > header.
> > > > 
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > ---
> > > >  arch/arm/mach-socfpga/include/mach/boot0.h | 11 +++++++++--
> > > >  1 file changed, 9 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h
> > > > b/arch/arm/mach-socfpga/include/mach/boot0.h
> > > > index 22d9e7f..33c9368 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/boot0.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
> > > > @@ -11,8 +11,15 @@
> > > >  	.balignl 64,0xf33db33f;
> > > >  
> > > >  	.word	0x1337c0d3;	/* SoCFPGA preloader
> > > > validation word */
> > > > -	.word	0xc01df00d;	/* Version, flags,
> > > > length
> > > > */
> > > > -	.word	0xcafec0d3;	/* Checksum, zero-pad
> > > > */
> > > > +	.word	0xc01df00d; /* Header
> > > > length(2B),flags(1B),version(1B) */
> > > > +#ifndef CONFIG_TARGET_SOCFPGA_GEN5
> > > > +	.word	0xfeedface; /* Program length(4B) */
> > > Keep this indent intact, then it won't generate these crappy -
> > > entries.
> > > 
> > Are you saying to keep the comment indent intact, and allign with
> > 1st
> > comment  /* SoCFPGA preloader validation word */ ?
> Just look at the diff and make sure that it only changes the relevant
> parts, not extras due to indent changes.
> 
Not get you, which particular change is due to indent changes only?
Some changes are for re-writing more descriptive comment. And some new
adding header attributes to support Arria 10.
> > 
> > > 
> > > > 
> > > > 
> > > > +	.word	0xf00dcafe; /*
> > > > +			     * Program entry
> > > > offset(4B),relative
> > > > to
> > > > +			     * the start of program header
> > > > +			     */
> > > > +#endif
> > > > +	.word	0xcafec0d3;	/* Simple
> > > > checksum(2B),spare offset(2B) */
> > > >  	nop;
> > > >  
> > > >  	b reset;		/* SoCFPGA jumps here */
> > > > 
> 

[U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for Arria 10

[Chee, Tien Fong]

On Sel, 2017-09-26 at 12:35 +0200, Marek Vasut wrote:
> On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2017-09-25 at 11:19 +0200, Marek Vasut wrote:
> > > 
> > > On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > 
> > > > Add DDR driver suppport for Arria 10.
> > > > 
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > ---
> > > >  arch/arm/mach-socfpga/include/mach/sdram.h         |   2 +
> > > >  arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-
> > > >  drivers/ddr/altera/sdram_arria10.c                 | 735
> > > > +++++++++++++++++++++
> > > >  3 files changed, 839 insertions(+), 1 deletion(-)
> > > >  create mode 100644 drivers/ddr/altera/sdram_arria10.c
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > b/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > index 4a9754e..b833fc2 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > @@ -10,6 +10,8 @@
> > > >  
> > > >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > >  #include <asm/arch/sdram_gen5.h>
> > > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > +#include <asm/arch/sdram_arria10.h>
> > > >  #endif
> > > >  
> > > >  #endif
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > > > b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > > > index 1d7b7c1..7af9431 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > > > @@ -1,5 +1,5 @@
> > > >  /*
> > > > - * Copyright (C) 2015-2017 Intel Corporation <www.intel.com>
> > > > + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> > > >   *
> > > >   * SPDX-License-Identifier:	GPL-2.0
> > > >   */
> > > > @@ -8,6 +8,7 @@
> > > >  #define _SOCFPGA_SDRAM_ARRIA10_H_
> > > >  
> > > >  #ifndef __ASSEMBLY__
> > > > +int ddr_calibration_sequence(void);
> > > >  
> > > >  struct socfpga_ecc_hmc {
> > > >  	u32 ip_rev_id;
> > > > @@ -204,6 +205,106 @@ struct socfpga_io48_mmr {
> > > >  	u32 niosreserve1;
> > > >  	u32 niosreserve2;
> > > >  };
> > > > +
> > > > +union dramaddrw_reg {
> > > > +	struct {
> > > > +		u32 cfg_col_addr_width:5;
> > > > +		u32 cfg_row_addr_width:5;
> > > > +		u32 cfg_bank_addr_width:4;
> > > > +		u32 cfg_bank_group_addr_width:2;
> > > > +		u32 cfg_cs_addr_width:3;
> > > > +		u32 reserved:13;
> > > > +	};
> > > Use regular macros for bitfields, not this crap.
> > > 
> > Why regular macros is prefered? Above implementation improve
> > readability, simplify the implementation and saving memory.
> Because that's how U-Boot does it (and the above afair breaks on
> different endianness).
> 
Okay.
> > 
> > > 
> > > > 
> > > > 
> > > > +	u32 word;
> > > > +};
> > > > +
> > > > +union ctrlcfg0_reg {
> > > > +	struct {
> > > > +		u32 cfg_mem_type:4;
> > > > +		u32 cfg_dimm_type:3;
> > > > +		u32 cfg_ac_pos:2;
> > > > +		u32 cfg_ctrl_burst_len:5;
> > > > +		u32 reserved:18;  /* Other fields unused */
> > > > +	};
> > > > +	u32 word;
> > > > +};
> > > [...]
> [...]
> 

[U-Boot] [PATCH v2 10/19] arm: socfpga: Rename the gen5 sdram driver to more specific name

[Chee, Tien Fong]

On Sel, 2017-09-26 at 12:33 +0200, Marek Vasut wrote:
> On 09/26/2017 10:23 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2017-09-25 at 11:15 +0200, Marek Vasut wrote:
> > > 
> > > On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > 
> > > > Current sdram driver is only applied to gen5 device, hence it
> > > > is
> > > > better
> > > > to rename sdram driver to more specific name which is related
> > > > to
> > > > gen5
> > > > device.
> > > > 
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > ---
> > > >  arch/arm/mach-socfpga/include/mach/sdram.h         | 434 +--
> > > > ----
> > > > --------------
> > > >  .../include/mach/{sdram.h => sdram_gen5.h}         |   6 +-
> > > >  drivers/ddr/altera/Makefile                        |   2 +-
> > > >  drivers/ddr/altera/{sdram.c => sdram_gen5.c}       |   0
> > > >  4 files changed, 8 insertions(+), 434 deletions(-)
> > > >  copy arch/arm/mach-socfpga/include/mach/{sdram.h =>
> > > > sdram_gen5.h}
> > > > (99%)
> > > >  rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > b/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > index b11228f..4a9754e 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > @@ -1,5 +1,5 @@
> > > >  /*
> > > > - * Copyright Altera Corporation (C) 2014-2015
> > > > + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> > > Retain the old copyright ?
> > > 
> > Okay.
> > > 
> > > > 
> > > > 
> > > >   *
> > > >   * SPDX-License-Identifier:	GPL-2.0+
> > > >   */
> > > > @@ -8,435 +8,9 @@
> > > >  
> > > >  #ifndef __ASSEMBLY__
> > > What's with this massive deletion here ?
> > > 
> > Move to sdram_gen5.h . This header should contain common stuff.
> Then where did the + part go ?
> 
I'm not sure why the patch didn't showing "+" portion, i suspect the
patch use below instead of "+".
 copy arch/arm/mach-socfpga/include/mach/{sdram.h =>
> > > > sdram_gen5.h}> > > > (99%)> > > >  rename
drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)
> > 
> > > 
> > > > 
> > > > 
> > > > -unsigned long sdram_calculate_size(void);
> > > > -int sdram_mmr_init_full(unsigned int sdr_phy_reg);
> > > > -int sdram_calibration_full(void);
> > > > -
> > > > -const struct socfpga_sdram_config
> > > > *socfpga_get_sdram_config(void);
> > > > -
> > > > -void socfpga_get_seq_ac_init(const u32 **init, unsigned int
> > > > *nelem);
> > > > -void socfpga_get_seq_inst_init(const u32 **init, unsigned int
> > > > *nelem);
> > > > -const struct socfpga_sdram_rw_mgr_config
> > > > *socfpga_get_sdram_rwmgr_config(void);
> > > [...]
> 

[U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory allocation in SPL

[Chee, Tien Fong]

On Sel, 2017-09-26 at 12:37 +0200, Marek Vasut wrote:
> On 09/26/2017 07:06 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2017-09-25 at 11:21 +0200, Marek Vasut wrote:
> > > 
> > > On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > 
> > > > Add support to memory allocation in SPL for preparation to
> > > > enable
> > > > FAT
> > > > in SPL. Memory allocation is needed by FAT to work properly.
> > > > 
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > Gen 5 does have malloc support in SPL, so what's the deal here ?
> > > 
> > For FAT to work properly in Arria 10 SPL, SPL malloc need to be
> > enabled,
> It is already enabled on Gen 5
> 
I think i have confused you, this patch is for getting the malloc area
mapping to Arria 10 SRAM memory correctly. I will improve the commit
message.
> > 
> > and the min of SPL malloc size is 0x2000.
> Where did you find about this minimum ? That can be configured ...
> 
I having issue to boot u-boot successful(Hung or reset), after debuging
through debugger, just found that 0x2000 is min required.
> > 
> > FAT needed in Arria
> > 10 SPL, because u-boot.img is stored in FAT partition.
> It can also be stored on ext partition (which is preferred, patent-
> wise)
> 
> > 
> > > 
> > > > 
> > > > 
> > > > ---
> > > >  include/configs/socfpga_common.h | 23 ++++++++++++++++++++++-
> > > >  1 file changed, 22 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/include/configs/socfpga_common.h
> > > > b/include/configs/socfpga_common.h
> > > > index 7549ee8..9b6719e 100644
> > > > --- a/include/configs/socfpga_common.h
> > > > +++ b/include/configs/socfpga_common.h
> > > > @@ -280,17 +280,34 @@ unsigned int
> > > > cm_get_qspi_controller_clk_hz(void);
> > > >  /*
> > > >   * SPL
> > > >   *
> > > > - * SRAM Memory layout:
> > > > + * SRAM Memory layout for gen 5:
> > > >   *
> > > >   * 0xFFFF_0000 ...... Start of SRAM
> > > >   * 0xFFFF_xxxx ...... Top of stack (grows down)
> > > >   * 0xFFFF_yyyy ...... Malloc area
> > > >   * 0xFFFF_zzzz ...... Global Data
> > > >   * 0xFFFF_FF00 ...... End of SRAM
> > > > + *
> > > > + * SRAM Memory layout for Arria 10:
> > > > + * 0xFFE0_0000 ...... Start of SRAM (bottom)
> > > > + * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
> > > > + * 0xFFEy_yyyy ...... Malloc area (grows up to top)
> > > > + * 0xFFEz_zzzz ...... Global Data
> > > > + * 0xFFE3_FFFF ...... End of SRAM (top)
> > > >   */
> > > >  #define CONFIG_SPL_FRAMEWORK
> > > >  #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RA
> > > > M_AD
> > > > DR
> > > >  #define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM
> > > > _SIZ
> > > > E
> > > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > +/* SPL memory allocation configuration, it is required by FAT
> > > > feature */
> > > > +#ifndef CONFIG_SYS_SPL_MALLOC_START
> > > > +#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00002000
> > > > +#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_INIT_RA
> > > > M_SI
> > > > ZE - \
> > > > +					 GENERATED_GBL_DATA_SI
> > > > ZE -
> > > > \
> > > > +					 CONFIG_SYS_SPL_MALLOC
> > > > _SIZ
> > > > E + \
> > > > +					 CONFIG_SYS_INIT_RAM_A
> > > > DDR)
> > > > +#endif
> > > > +#endif
> > > >  
> > > >  /* SPL SDMMC boot support */
> > > >  #ifdef CONFIG_SPL_MMC_SUPPORT
> > > > @@ -320,7 +337,11 @@ unsigned int
> > > > cm_get_qspi_controller_clk_hz(void);
> > > >  /*
> > > >   * Stack setup
> > > >   */
> > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > >  #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADD
> > > > R
> > > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > +#define CONFIG_SPL_STACK		(CONFIG_SYS_SPL_MALLOC
> > > > _STA
> > > > RT - 1)
> > > > +#endif
> > > >  
> > > >  /* Extra Environment */
> > > >  #ifndef CONFIG_SPL_BUILD
> > > > 
> 

[U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA from flash

[Chee, Tien Fong]

On Sel, 2017-09-26 at 12:32 +0200, Marek Vasut wrote:
> On 09/26/2017 10:30 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:
> > > 
> > > On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > 
> > > > These drivers handle FPGA program operation from flash loading
> > > > RBF to memory and then to program FPGA.
> > > > 
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > Did you run checkpatch on this before submitting ? I presume no
> > > ...
> > > 
> > Yeah, i run checkpatch for all patches. What's the issue here?
> It should definitely indicate problem with ie. yoda-notation
> +if (0 == flashinfo->remaining) {
> and indent ...
> 
No complaint from checkpath. I know someone saying bad for readbility,
but yoda-notation at this simple implementation doesn't impact the
readbility, and having benefit to leverage detection of compiler on
missing "=". Overall, this can help to improve coding quality. I can
remove it if this doesn't favored in U-boot.
> > 
> > > 
> > > > 
> > > > 
> > > > ---
> > > >  .../include/mach/fpga_manager_arria10.h            |  27 ++
> > > >  drivers/fpga/socfpga_arria10.c                     | 391
> > > > ++++++++++++++++++++-
> > > >  include/altera.h                                   |   6 +
> > > >  include/configs/socfpga_common.h                   |   4 +
> > > >  4 files changed, 425 insertions(+), 3 deletions(-)
> > > [...]
> > > 
> > > > 
> > > > 
> > > > @@ -112,13 +122,14 @@ static int
> > > > wait_for_nconfig_pin_and_nstatus_pin(void)
> > > >  	unsigned long mask =
> > > > ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
> > > >  				ALT_FPGAMGR_IMGCFG_STAT_F2S_NS
> > > > TATU
> > > > S_PIN_SET_MSK;
> > > >  
> > > > -	/* Poll until f2s_nconfig_pin and f2s_nstatus_pin;
> > > > loop
> > > > until de-asserted,
> > > > -	 * timeout at 1000ms
> > > > +	/*
> > > > +	 * Poll until f2s_nconfig_pin and f2s_nstatus_pin;
> > > > loop
> > > > until
> > > > +	 * de-asserted, timeout at 1000ms
> > > >  	 */
> > > >  	return wait_for_bit(__func__,
> > > >  			    &fpga_manager_base->imgcfg_stat,
> > > >  			    mask,
> > > > -			    false, FPGA_TIMEOUT_MSEC, false);
> > > > +			    true, FPGA_TIMEOUT_MSEC, false);
> > > >  }
> > > Seems more like a fix, split this out.
> > > 
> > Okay.
> > > 
> > > > 
> > > > 
> > > >  static int wait_for_f2s_nstatus_pin(unsigned long value)
> > > > @@ -469,6 +480,7 @@ int socfpga_load(Altera_desc *desc, const
> > > > void
> > > > *rbf_data, size_t rbf_size)
> > > >  
> > > >  	/* Initialize the FPGA Manager */
> > > >  	status = fpgamgr_program_init((u32 *)rbf_data,
> > > > rbf_size);
> > > > +
> > > >  	if (status)
> > > >  		return status;
> > > >  
> > > > @@ -477,3 +489,376 @@ int socfpga_load(Altera_desc *desc, const
> > > > void *rbf_data, size_t rbf_size)
> > > >  
> > > >  	return fpgamgr_program_finish();
> > > >  }
> > > > +
> > > > +#if defined(CONFIG_CMD_FPGA_LOADFS)
> > > > +const char *get_cff_filename(const void *fdt, int *len, u32
> > > > core)
> > > > +{
> > > > +	const char *cff_filename = NULL;
> > > > +	const char *cell;
> > > > +	int nodeoffset;
> > > > +	nodeoffset = fdtdec_next_compatible(fdt, 0,
> > > > +			 COMPAT_ALTERA_SOCFPGA_FPGA0);
> > > > +
> > > > +	if (nodeoffset >= 0) {
> > > > +		if (core)
> > > > +			cell = fdt_getprop(fdt,
> > > > +					nodeoffset,
> > > > +					"bitstream_core",
> > > > +					len);
> > > > +		else
> > > > +			cell = fdt_getprop(fdt, nodeoffset,
> > > > "bitstream_periph",
> > > > +					 len);
> > > > +
> > > > +		if (cell)
> > > > +			cff_filename = cell;
> > > > +	}
> > > > +
> > > > +	return cff_filename;
> > > > +}
> > > > +
> > > > +const char *get_cff_devpart(const void *fdt, int *len)
> > > > +{
> > > > +	const char *cff_devpart = NULL;
> > > > +	const char *cell;
> > > > +	int nodeoffset;
> > > > +	nodeoffset = fdtdec_next_compatible(fdt, 0,
> > > > +			 COMPAT_ALTERA_SOCFPGA_FPGA0);
> > > > +
> > > > +	cell = fdt_getprop(fdt, nodeoffset,
> > > > "bitstream_devpart",
> > > > len);
> > > > +
> > > > +	if (cell)
> > > > +		cff_devpart = cell;
> > > > +
> > > > +	return cff_devpart;
> > > > +}
> > > Take a look at splash*.c , I believe that can be reworked into
> > > generic
> > > firmware loader , which you could then use here.
> This is important here, I don't want yet another ad-hoc loader ...
> 
Disucss in another email reply separately. I need time to think.
> > 
> > > 
> > > [...]
> > > 
> > > > 
> > > > 
> > > > diff --git a/include/configs/socfpga_common.h
> > > > b/include/configs/socfpga_common.h
> > > > index 9897e11..eadce2d 100644
> > > > --- a/include/configs/socfpga_common.h
> > > > +++ b/include/configs/socfpga_common.h
> > > > @@ -27,7 +27,11 @@
> > > >   */
> > > >  #define CONFIG_NR_DRAM_BANKS		1
> > > >  #define PHYS_SDRAM_1			0x0
> > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > >  #define CONFIG_SYS_MALLOC_LEN		(64 * 1024 *
> > > > 1024)
> > > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > +#define CONFIG_SYS_MALLOC_LEN		(128 * 1024 *
> > > > 1024)
> > > > +#endif
> > > You definitely don't need 128 MiB of malloc area.
> > > 
> > Okay, i will try out with smaller size.
> Why do you need such massive area ? It's not a matter of "try out",
> you
> should know why this change was needed for your use-case.
> 
I forgot what reason i put this value. I need to find out.
> > 
> > > 
> > > > 
> > > > 
> > > >  #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
> > > >  #define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZ
> > > > E
> > > >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > 
> 

[U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA RBF properties at Arria 10 FPGA manager

[Marek Vasut]

On 09/27/2017 05:12 AM, Chee, Tien Fong wrote:
> On Sel, 2017-09-26 at 12:30 +0200, Marek Vasut wrote:
>> On 09/26/2017 10:54 AM, Chee, Tien Fong wrote:
>>>
>>> On Isn, 2017-09-25 at 11:00 +0200, Marek Vasut wrote:
>>>>
>>>> On 09/25/2017 10:39 AM, tien.fong.chee at intel.com wrote:
>>>>>
>>>>>
>>>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>>
>>>>> This patch adds description on properties about location of
>>>>> FPGA
>>>>> RBFs are
>>>>> stored, type and functionality of RBF used to configure FPGA.
>>>>>
>>>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>>> Why does this patch have different tags than 1/19 ? Please keep
>>>> things
>>>> consistent ...
>>>>
>>> Not get you. What's you means for tags?
>> ARM: socfpga: , not the random doc: dtbinding: .
>> Heck, the first and second patch change the same file, yet have
>> different tags, why ?
>>
> I ported patch 01 from Linux, so i keep everything intact. For patch
> 02, i put doc:dtbinding because i think that is more descriptive to the
> file i changed.
> I can change to ARM:socfpga .

The tags are standardized ... inventing new random ones only messes
things up.

>>>
>>>>
>>>>>
>>>>> ---
>>>>>  doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
>>>>> | 11
>>>>> +++++++++++
>>>>>  1 file changed, 11 insertions(+)
>>>>>
>>>>> diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-
>>>>> fpga-
>>>>> mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-
>>>>> fpga-
>>>>> mgr.txt
>>>>> index 2fd8e7a..7abb746 100644
>>>>> --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
>>>>> mgr.txt
>>>>> +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
>>>>> mgr.txt
>>>>> @@ -7,6 +7,14 @@ Required properties:
>>>>>                 - The second index is for writing FPGA
>>>>> configuration data.
>>>>>  - resets     : Phandle and reset specifier for the device's
>>>>> reset.
>>>>>  - clocks     : Clocks used by the device.
>>>>> +- bitstream_periph : FPGA peripheral raw binary file which is
>>>>> used
>>>>> to
>>>>> +                     initialize FPGA IOs, PLL, IO48 and DDR.
>>>>> +- bitstream_core : FPGA core raw binary file contains FPGA
>>>>> design
>>>>> which is used
>>>>> +                   to program FPGA CRAM and ERAM.
>>>>> +- bitstream_devpart : Partition of flash device where
>>>>> bitstream
>>>>> files are
>>>>> +		       stored.
>>>>> +                      <dev[:part]> - dev is flash device
>>>>> number,
>>>>> part is flash
>>>>> +                                     device partition.
>>>>>  
>>>>>  Example:
>>>>>  
>>>>> @@ -16,4 +24,7 @@ Example:
>>>>>  		       0xffcfe400 0x20>;
>>>>>  		clocks = <&l4_mp_clk>;
>>>>>  		resets = <&rst FPGAMGR_RESET>;
>>>>> +		bitstream_periph =
>>>>> "ghrd_10as066n2.periph.rbf.mkimage";
>>>>> +		bitstream_core =
>>>>> "ghrd_10as066n2.core.rbf.mkimage";
>>>>> +		bitstream_devpart = "0:1";
>>>>>  	};
>>>>>


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA from flash

[Marek Vasut]

On 09/27/2017 08:05 AM, Chee, Tien Fong wrote:
> On Sel, 2017-09-26 at 12:32 +0200, Marek Vasut wrote:
>> On 09/26/2017 10:30 AM, Chee, Tien Fong wrote:
>>>
>>> On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:
>>>>
>>>> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
>>>>>
>>>>>
>>>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>>
>>>>> These drivers handle FPGA program operation from flash loading
>>>>> RBF to memory and then to program FPGA.
>>>>>
>>>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>>> Did you run checkpatch on this before submitting ? I presume no
>>>> ...
>>>>
>>> Yeah, i run checkpatch for all patches. What's the issue here?
>> It should definitely indicate problem with ie. yoda-notation
>> +if (0 == flashinfo->remaining) {
>> and indent ...
>>
> No complaint from checkpath. I know someone saying bad for readbility,
> but yoda-notation at this simple implementation doesn't impact the
> readbility, and having benefit to leverage detection of compiler on
> missing "=". Overall, this can help to improve coding quality. I can
> remove it if this doesn't favored in U-boot.

It is not welcome and modern gcc warns you about such things .

>>>
>>>>
>>>>>
>>>>>
>>>>> ---
>>>>>  .../include/mach/fpga_manager_arria10.h            |  27 ++
>>>>>  drivers/fpga/socfpga_arria10.c                     | 391
>>>>> ++++++++++++++++++++-
>>>>>  include/altera.h                                   |   6 +
>>>>>  include/configs/socfpga_common.h                   |   4 +
>>>>>  4 files changed, 425 insertions(+), 3 deletions(-)
>>>> [...]
>>>>
>>>>>
>>>>>
>>>>> @@ -112,13 +122,14 @@ static int
>>>>> wait_for_nconfig_pin_and_nstatus_pin(void)
>>>>>  	unsigned long mask =
>>>>> ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
>>>>>  				ALT_FPGAMGR_IMGCFG_STAT_F2S_NS
>>>>> TATU
>>>>> S_PIN_SET_MSK;
>>>>>  
>>>>> -	/* Poll until f2s_nconfig_pin and f2s_nstatus_pin;
>>>>> loop
>>>>> until de-asserted,
>>>>> -	 * timeout at 1000ms
>>>>> +	/*
>>>>> +	 * Poll until f2s_nconfig_pin and f2s_nstatus_pin;
>>>>> loop
>>>>> until
>>>>> +	 * de-asserted, timeout at 1000ms
>>>>>  	 */
>>>>>  	return wait_for_bit(__func__,
>>>>>  			    &fpga_manager_base->imgcfg_stat,
>>>>>  			    mask,
>>>>> -			    false, FPGA_TIMEOUT_MSEC, false);
>>>>> +			    true, FPGA_TIMEOUT_MSEC, false);
>>>>>  }
>>>> Seems more like a fix, split this out.
>>>>
>>> Okay.
>>>>
>>>>>
>>>>>
>>>>>  static int wait_for_f2s_nstatus_pin(unsigned long value)
>>>>> @@ -469,6 +480,7 @@ int socfpga_load(Altera_desc *desc, const
>>>>> void
>>>>> *rbf_data, size_t rbf_size)
>>>>>  
>>>>>  	/* Initialize the FPGA Manager */
>>>>>  	status = fpgamgr_program_init((u32 *)rbf_data,
>>>>> rbf_size);
>>>>> +
>>>>>  	if (status)
>>>>>  		return status;
>>>>>  
>>>>> @@ -477,3 +489,376 @@ int socfpga_load(Altera_desc *desc, const
>>>>> void *rbf_data, size_t rbf_size)
>>>>>  
>>>>>  	return fpgamgr_program_finish();
>>>>>  }
>>>>> +
>>>>> +#if defined(CONFIG_CMD_FPGA_LOADFS)
>>>>> +const char *get_cff_filename(const void *fdt, int *len, u32
>>>>> core)
>>>>> +{
>>>>> +	const char *cff_filename = NULL;
>>>>> +	const char *cell;
>>>>> +	int nodeoffset;
>>>>> +	nodeoffset = fdtdec_next_compatible(fdt, 0,
>>>>> +			 COMPAT_ALTERA_SOCFPGA_FPGA0);
>>>>> +
>>>>> +	if (nodeoffset >= 0) {
>>>>> +		if (core)
>>>>> +			cell = fdt_getprop(fdt,
>>>>> +					nodeoffset,
>>>>> +					"bitstream_core",
>>>>> +					len);
>>>>> +		else
>>>>> +			cell = fdt_getprop(fdt, nodeoffset,
>>>>> "bitstream_periph",
>>>>> +					 len);
>>>>> +
>>>>> +		if (cell)
>>>>> +			cff_filename = cell;
>>>>> +	}
>>>>> +
>>>>> +	return cff_filename;
>>>>> +}
>>>>> +
>>>>> +const char *get_cff_devpart(const void *fdt, int *len)
>>>>> +{
>>>>> +	const char *cff_devpart = NULL;
>>>>> +	const char *cell;
>>>>> +	int nodeoffset;
>>>>> +	nodeoffset = fdtdec_next_compatible(fdt, 0,
>>>>> +			 COMPAT_ALTERA_SOCFPGA_FPGA0);
>>>>> +
>>>>> +	cell = fdt_getprop(fdt, nodeoffset,
>>>>> "bitstream_devpart",
>>>>> len);
>>>>> +
>>>>> +	if (cell)
>>>>> +		cff_devpart = cell;
>>>>> +
>>>>> +	return cff_devpart;
>>>>> +}
>>>> Take a look at splash*.c , I believe that can be reworked into
>>>> generic
>>>> firmware loader , which you could then use here.
>> This is important here, I don't want yet another ad-hoc loader ...
>>
> Disucss in another email reply separately. I need time to think.
>>>
>>>>
>>>> [...]
>>>>
>>>>>
>>>>>
>>>>> diff --git a/include/configs/socfpga_common.h
>>>>> b/include/configs/socfpga_common.h
>>>>> index 9897e11..eadce2d 100644
>>>>> --- a/include/configs/socfpga_common.h
>>>>> +++ b/include/configs/socfpga_common.h
>>>>> @@ -27,7 +27,11 @@
>>>>>   */
>>>>>  #define CONFIG_NR_DRAM_BANKS		1
>>>>>  #define PHYS_SDRAM_1			0x0
>>>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>>>  #define CONFIG_SYS_MALLOC_LEN		(64 * 1024 *
>>>>> 1024)
>>>>> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>>>> +#define CONFIG_SYS_MALLOC_LEN		(128 * 1024 *
>>>>> 1024)
>>>>> +#endif
>>>> You definitely don't need 128 MiB of malloc area.
>>>>
>>> Okay, i will try out with smaller size.
>> Why do you need such massive area ? It's not a matter of "try out",
>> you
>> should know why this change was needed for your use-case.
>>
> I forgot what reason i put this value. I need to find out.

If this was properly documented in the commit message, you would not
have to ...

>>>
>>>>
>>>>>
>>>>>
>>>>>  #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
>>>>>  #define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZ
>>>>> E
>>>>>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>>>


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory allocation in SPL

[Marek Vasut]

On 09/27/2017 07:43 AM, Chee, Tien Fong wrote:
> On Sel, 2017-09-26 at 12:37 +0200, Marek Vasut wrote:
>> On 09/26/2017 07:06 AM, Chee, Tien Fong wrote:
>>>
>>> On Isn, 2017-09-25 at 11:21 +0200, Marek Vasut wrote:
>>>>
>>>> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
>>>>>
>>>>>
>>>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>>
>>>>> Add support to memory allocation in SPL for preparation to
>>>>> enable
>>>>> FAT
>>>>> in SPL. Memory allocation is needed by FAT to work properly.
>>>>>
>>>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>>> Gen 5 does have malloc support in SPL, so what's the deal here ?
>>>>
>>> For FAT to work properly in Arria 10 SPL, SPL malloc need to be
>>> enabled,
>> It is already enabled on Gen 5
>>
> I think i have confused you, this patch is for getting the malloc area
> mapping to Arria 10 SRAM memory correctly. I will improve the commit
> message.
>>>
>>> and the min of SPL malloc size is 0x2000.
>> Where did you find about this minimum ? That can be configured ...
>>
> I having issue to boot u-boot successful(Hung or reset), after debuging
> through debugger, just found that 0x2000 is min required.

You can set the value much lower and depending on the requirements, it
will work, so the problem must be elsewhere ...

>>>
>>> FAT needed in Arria
>>> 10 SPL, because u-boot.img is stored in FAT partition.
>> It can also be stored on ext partition (which is preferred, patent-
>> wise)
>>
>>>
>>>>
>>>>>
>>>>>
>>>>> ---
>>>>>  include/configs/socfpga_common.h | 23 ++++++++++++++++++++++-
>>>>>  1 file changed, 22 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/include/configs/socfpga_common.h
>>>>> b/include/configs/socfpga_common.h
>>>>> index 7549ee8..9b6719e 100644
>>>>> --- a/include/configs/socfpga_common.h
>>>>> +++ b/include/configs/socfpga_common.h
>>>>> @@ -280,17 +280,34 @@ unsigned int
>>>>> cm_get_qspi_controller_clk_hz(void);
>>>>>  /*
>>>>>   * SPL
>>>>>   *
>>>>> - * SRAM Memory layout:
>>>>> + * SRAM Memory layout for gen 5:
>>>>>   *
>>>>>   * 0xFFFF_0000 ...... Start of SRAM
>>>>>   * 0xFFFF_xxxx ...... Top of stack (grows down)
>>>>>   * 0xFFFF_yyyy ...... Malloc area
>>>>>   * 0xFFFF_zzzz ...... Global Data
>>>>>   * 0xFFFF_FF00 ...... End of SRAM
>>>>> + *
>>>>> + * SRAM Memory layout for Arria 10:
>>>>> + * 0xFFE0_0000 ...... Start of SRAM (bottom)
>>>>> + * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
>>>>> + * 0xFFEy_yyyy ...... Malloc area (grows up to top)
>>>>> + * 0xFFEz_zzzz ...... Global Data
>>>>> + * 0xFFE3_FFFF ...... End of SRAM (top)
>>>>>   */
>>>>>  #define CONFIG_SPL_FRAMEWORK
>>>>>  #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RA
>>>>> M_AD
>>>>> DR
>>>>>  #define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM
>>>>> _SIZ
>>>>> E
>>>>> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>>>> +/* SPL memory allocation configuration, it is required by FAT
>>>>> feature */
>>>>> +#ifndef CONFIG_SYS_SPL_MALLOC_START
>>>>> +#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00002000
>>>>> +#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_INIT_RA
>>>>> M_SI
>>>>> ZE - \
>>>>> +					 GENERATED_GBL_DATA_SI
>>>>> ZE -
>>>>> \
>>>>> +					 CONFIG_SYS_SPL_MALLOC
>>>>> _SIZ
>>>>> E + \
>>>>> +					 CONFIG_SYS_INIT_RAM_A
>>>>> DDR)
>>>>> +#endif
>>>>> +#endif
>>>>>  
>>>>>  /* SPL SDMMC boot support */
>>>>>  #ifdef CONFIG_SPL_MMC_SUPPORT
>>>>> @@ -320,7 +337,11 @@ unsigned int
>>>>> cm_get_qspi_controller_clk_hz(void);
>>>>>  /*
>>>>>   * Stack setup
>>>>>   */
>>>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>>>  #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADD
>>>>> R
>>>>> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>>>> +#define CONFIG_SPL_STACK		(CONFIG_SYS_SPL_MALLOC
>>>>> _STA
>>>>> RT - 1)
>>>>> +#endif
>>>>>  
>>>>>  /* Extra Environment */
>>>>>  #ifndef CONFIG_SPL_BUILD
>>>>>


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10

[Marek Vasut]

On 09/27/2017 05:30 AM, Chee, Tien Fong wrote:
> On Sel, 2017-09-26 at 12:37 +0200, Marek Vasut wrote:
>> On 09/26/2017 06:42 AM, Chee, Tien Fong wrote:
>>>
>>> On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:
>>>>
>>>> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
>>>>>
>>>>>
>>>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>>
>>>>> Enhance preloader header with both additional program length
>>>>> and
>>>>> program
>>>>> entry offset attributes, which offset is relative to the start
>>>>> of
>>>>> program
>>>>> header.
>>>>>
>>>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>> ---
>>>>>  arch/arm/mach-socfpga/include/mach/boot0.h | 11 +++++++++--
>>>>>  1 file changed, 9 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h
>>>>> b/arch/arm/mach-socfpga/include/mach/boot0.h
>>>>> index 22d9e7f..33c9368 100644
>>>>> --- a/arch/arm/mach-socfpga/include/mach/boot0.h
>>>>> +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
>>>>> @@ -11,8 +11,15 @@
>>>>>  	.balignl 64,0xf33db33f;
>>>>>  
>>>>>  	.word	0x1337c0d3;	/* SoCFPGA preloader
>>>>> validation word */
>>>>> -	.word	0xc01df00d;	/* Version, flags,
>>>>> length
>>>>> */
>>>>> -	.word	0xcafec0d3;	/* Checksum, zero-pad
>>>>> */
>>>>> +	.word	0xc01df00d; /* Header
>>>>> length(2B),flags(1B),version(1B) */
>>>>> +#ifndef CONFIG_TARGET_SOCFPGA_GEN5
>>>>> +	.word	0xfeedface; /* Program length(4B) */
>>>> Keep this indent intact, then it won't generate these crappy -
>>>> entries.
>>>>
>>> Are you saying to keep the comment indent intact, and allign with
>>> 1st
>>> comment  /* SoCFPGA preloader validation word */ ?
>> Just look at the diff and make sure that it only changes the relevant
>> parts, not extras due to indent changes.
>>
> Not get you, which particular change is due to indent changes only?
> Some changes are for re-writing more descriptive comment. And some new
> adding header attributes to support Arria 10.

Aaargh, then don't do two things in one patch.

>>>
>>>>
>>>>>
>>>>>
>>>>> +	.word	0xf00dcafe; /*
>>>>> +			     * Program entry
>>>>> offset(4B),relative
>>>>> to
>>>>> +			     * the start of program header
>>>>> +			     */
>>>>> +#endif
>>>>> +	.word	0xcafec0d3;	/* Simple
>>>>> checksum(2B),spare offset(2B) */
>>>>>  	nop;
>>>>>  
>>>>>  	b reset;		/* SoCFPGA jumps here */
>>>>>


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA from flash

[Chee, Tien Fong]

On Sel, 2017-09-26 at 12:39 +0200, Marek Vasut wrote:
> On 09/26/2017 11:52 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:
> > > 
> > > On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > 
> > > > These drivers handle FPGA program operation from flash loading
> > > > RBF to memory and then to program FPGA.
> > > > 
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> [...]
> 
> > 
> > > 
> > > > 
> > > > +const char *get_cff_devpart(const void *fdt, int *len)
> > > > +{
> > > > +	const char *cff_devpart = NULL;
> > > > +	const char *cell;
> > > > +	int nodeoffset;
> > > > +	nodeoffset = fdtdec_next_compatible(fdt, 0,
> > > > +			 COMPAT_ALTERA_SOCFPGA_FPGA0);
> > > > +
> > > > +	cell = fdt_getprop(fdt, nodeoffset,
> > > > "bitstream_devpart",
> > > > len);
> > > > +
> > > > +	if (cell)
> > > > +		cff_devpart = cell;
> > > > +
> > > > +	return cff_devpart;
> > > > +}
> > > Take a look at splash*.c , I believe that can be reworked into
> > > generic
> > > firmware loader , which you could then use here.
> > > 
> > the devpart is hard coded in splash*.c. The function here is
> > getting
> > devpart info from DTS. So, is there any similar function in
> > splash*.c?
> > May be you can share more about your idea.
> The generic loader could use some work of course ...
> 
Sorry, i am still confusing. Allow me to ask you more:
1. Is the generic firmware loader already exists in splash*.c?
2. Are you talking about get_cff_devpart or whole fpga laodfs?
3. You want me integrate get_cff_devpart function into splash*.c?
4. Are you means to hard code the devpart instead providing dynamic
devpart described in DTS?

Current implementation are located in spl_board_init func
(arcg/arm/mach-socfpga/spl.c). Based on boot device such as mmc, nand
and QSPI, then reading some info from DTS, setting dev and partition
with generic fs functions, and reading with generic fs function before
programming RBF into FPGA. All these are in patch 19.

Thanks.
> [...]
> 

[U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA from flash

[Marek Vasut]

On 09/27/2017 11:13 AM, Chee, Tien Fong wrote:
> On Sel, 2017-09-26 at 12:39 +0200, Marek Vasut wrote:
>> On 09/26/2017 11:52 AM, Chee, Tien Fong wrote:
>>>
>>> On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:
>>>>
>>>> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
>>>>>
>>>>>
>>>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>>
>>>>> These drivers handle FPGA program operation from flash loading
>>>>> RBF to memory and then to program FPGA.
>>>>>
>>>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>> [...]
>>
>>>
>>>>
>>>>>
>>>>> +const char *get_cff_devpart(const void *fdt, int *len)
>>>>> +{
>>>>> +	const char *cff_devpart = NULL;
>>>>> +	const char *cell;
>>>>> +	int nodeoffset;
>>>>> +	nodeoffset = fdtdec_next_compatible(fdt, 0,
>>>>> +			 COMPAT_ALTERA_SOCFPGA_FPGA0);
>>>>> +
>>>>> +	cell = fdt_getprop(fdt, nodeoffset,
>>>>> "bitstream_devpart",
>>>>> len);
>>>>> +
>>>>> +	if (cell)
>>>>> +		cff_devpart = cell;
>>>>> +
>>>>> +	return cff_devpart;
>>>>> +}
>>>> Take a look at splash*.c , I believe that can be reworked into
>>>> generic
>>>> firmware loader , which you could then use here.
>>>>
>>> the devpart is hard coded in splash*.c. The function here is
>>> getting
>>> devpart info from DTS. So, is there any similar function in
>>> splash*.c?
>>> May be you can share more about your idea.
>> The generic loader could use some work of course ...
>>
> Sorry, i am still confusing. Allow me to ask you more:
> 1. Is the generic firmware loader already exists in splash*.c?

No

> 2. Are you talking about get_cff_devpart or whole fpga laodfs?
> 3. You want me integrate get_cff_devpart function into splash*.c?
> 4. Are you means to hard code the devpart instead providing dynamic
> devpart described in DTS?

I am talking about factoring out generic firmware loader from splash*c ,
since it already contains most of the parts for such a thing.

> Current implementation are located in spl_board_init func
> (arcg/arm/mach-socfpga/spl.c). Based on boot device such as mmc, nand
> and QSPI, then reading some info from DTS, setting dev and partition
> with generic fs functions, and reading with generic fs function before
> programming RBF into FPGA. All these are in patch 19.

That's what splash*c also does, so adding separate parallel
implementation of the same functionality is a no-no.

> Thanks.
>> [...]


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA from flash

[Chee, Tien Fong]

On Rab, 2017-09-27 at 10:30 +0200, Marek Vasut wrote:
> On 09/27/2017 08:05 AM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2017-09-26 at 12:32 +0200, Marek Vasut wrote:
> > > 
> > > On 09/26/2017 10:30 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > 
> > > > > > These drivers handle FPGA program operation from flash
> > > > > > loading
> > > > > > RBF to memory and then to program FPGA.
> > > > > > 
> > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > Did you run checkpatch on this before submitting ? I presume
> > > > > no
> > > > > ...
> > > > > 
> > > > Yeah, i run checkpatch for all patches. What's the issue here?
> > > It should definitely indicate problem with ie. yoda-notation
> > > +if (0 == flashinfo->remaining) {
> > > and indent ...
> > > 
> > No complaint from checkpath. I know someone saying bad for
> > readbility,
> > but yoda-notation at this simple implementation doesn't impact the
> > readbility, and having benefit to leverage detection of compiler on
> > missing "=". Overall, this can help to improve coding quality. I
> > can
> > remove it if this doesn't favored in U-boot.
> It is not welcome and modern gcc warns you about such things .
> 
Okay.
> > 
> > > 
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > ---
> > > > > >  .../include/mach/fpga_manager_arria10.h            |  27
> > > > > > ++
> > > > > >  drivers/fpga/socfpga_arria10.c                     | 391
> > > > > > ++++++++++++++++++++-
> > > > > >  include/altera.h                                   |   6 +
> > > > > >  include/configs/socfpga_common.h                   |   4 +
> > > > > >  4 files changed, 425 insertions(+), 3 deletions(-)
> > > > > [...]
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > @@ -112,13 +122,14 @@ static int
> > > > > > wait_for_nconfig_pin_and_nstatus_pin(void)
> > > > > >  	unsigned long mask =
> > > > > > ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
> > > > > >  				ALT_FPGAMGR_IMGCFG_STAT_F2
> > > > > > S_NS
> > > > > > TATU
> > > > > > S_PIN_SET_MSK;
> > > > > >  
> > > > > > -	/* Poll until f2s_nconfig_pin and f2s_nstatus_pin;
> > > > > > loop
> > > > > > until de-asserted,
> > > > > > -	 * timeout at 1000ms
> > > > > > +	/*
> > > > > > +	 * Poll until f2s_nconfig_pin and f2s_nstatus_pin;
> > > > > > loop
> > > > > > until
> > > > > > +	 * de-asserted, timeout at 1000ms
> > > > > >  	 */
> > > > > >  	return wait_for_bit(__func__,
> > > > > >  			    &fpga_manager_base-
> > > > > > >imgcfg_stat,
> > > > > >  			    mask,
> > > > > > -			    false, FPGA_TIMEOUT_MSEC,
> > > > > > false);
> > > > > > +			    true, FPGA_TIMEOUT_MSEC,
> > > > > > false);
> > > > > >  }
> > > > > Seems more like a fix, split this out.
> > > > > 
> > > > Okay.
> > > > > 
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > >  static int wait_for_f2s_nstatus_pin(unsigned long value)
> > > > > > @@ -469,6 +480,7 @@ int socfpga_load(Altera_desc *desc,
> > > > > > const
> > > > > > void
> > > > > > *rbf_data, size_t rbf_size)
> > > > > >  
> > > > > >  	/* Initialize the FPGA Manager */
> > > > > >  	status = fpgamgr_program_init((u32 *)rbf_data,
> > > > > > rbf_size);
> > > > > > +
> > > > > >  	if (status)
> > > > > >  		return status;
> > > > > >  
> > > > > > @@ -477,3 +489,376 @@ int socfpga_load(Altera_desc *desc,
> > > > > > const
> > > > > > void *rbf_data, size_t rbf_size)
> > > > > >  
> > > > > >  	return fpgamgr_program_finish();
> > > > > >  }
> > > > > > +
> > > > > > +#if defined(CONFIG_CMD_FPGA_LOADFS)
> > > > > > +const char *get_cff_filename(const void *fdt, int *len,
> > > > > > u32
> > > > > > core)
> > > > > > +{
> > > > > > +	const char *cff_filename = NULL;
> > > > > > +	const char *cell;
> > > > > > +	int nodeoffset;
> > > > > > +	nodeoffset = fdtdec_next_compatible(fdt, 0,
> > > > > > +			 COMPAT_ALTERA_SOCFPGA_FPGA0);
> > > > > > +
> > > > > > +	if (nodeoffset >= 0) {
> > > > > > +		if (core)
> > > > > > +			cell = fdt_getprop(fdt,
> > > > > > +					nodeoffset,
> > > > > > +					"bitstream_core",
> > > > > > +					len);
> > > > > > +		else
> > > > > > +			cell = fdt_getprop(fdt,
> > > > > > nodeoffset,
> > > > > > "bitstream_periph",
> > > > > > +					 len);
> > > > > > +
> > > > > > +		if (cell)
> > > > > > +			cff_filename = cell;
> > > > > > +	}
> > > > > > +
> > > > > > +	return cff_filename;
> > > > > > +}
> > > > > > +
> > > > > > +const char *get_cff_devpart(const void *fdt, int *len)
> > > > > > +{
> > > > > > +	const char *cff_devpart = NULL;
> > > > > > +	const char *cell;
> > > > > > +	int nodeoffset;
> > > > > > +	nodeoffset = fdtdec_next_compatible(fdt, 0,
> > > > > > +			 COMPAT_ALTERA_SOCFPGA_FPGA0);
> > > > > > +
> > > > > > +	cell = fdt_getprop(fdt, nodeoffset,
> > > > > > "bitstream_devpart",
> > > > > > len);
> > > > > > +
> > > > > > +	if (cell)
> > > > > > +		cff_devpart = cell;
> > > > > > +
> > > > > > +	return cff_devpart;
> > > > > > +}
> > > > > Take a look at splash*.c , I believe that can be reworked
> > > > > into
> > > > > generic
> > > > > firmware loader , which you could then use here.
> > > This is important here, I don't want yet another ad-hoc loader
> > > ...
> > > 
> > Disucss in another email reply separately. I need time to think.
> > > 
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > [...]
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > diff --git a/include/configs/socfpga_common.h
> > > > > > b/include/configs/socfpga_common.h
> > > > > > index 9897e11..eadce2d 100644
> > > > > > --- a/include/configs/socfpga_common.h
> > > > > > +++ b/include/configs/socfpga_common.h
> > > > > > @@ -27,7 +27,11 @@
> > > > > >   */
> > > > > >  #define CONFIG_NR_DRAM_BANKS		1
> > > > > >  #define PHYS_SDRAM_1			0x0
> > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > > >  #define CONFIG_SYS_MALLOC_LEN		(64 * 1024 *
> > > > > > 1024)
> > > > > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > > > +#define CONFIG_SYS_MALLOC_LEN		(128 * 1024 *
> > > > > > 1024)
> > > > > > +#endif
> > > > > You definitely don't need 128 MiB of malloc area.
> > > > > 
> > > > Okay, i will try out with smaller size.
> > > Why do you need such massive area ? It's not a matter of "try
> > > out",
> > > you
> > > should know why this change was needed for your use-case.
> > > 
> > I forgot what reason i put this value. I need to find out.
> If this was properly documented in the commit message, you would not
> have to ...
> 
Okay.
> > 
> > > 
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > >  #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
> > > > > >  #define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1
> > > > > > _SIZ
> > > > > > E
> > > > > >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > > > 
> 

[U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10

[Chee, Tien Fong]

On Rab, 2017-09-27 at 10:33 +0200, Marek Vasut wrote:
> On 09/27/2017 05:30 AM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2017-09-26 at 12:37 +0200, Marek Vasut wrote:
> > > 
> > > On 09/26/2017 06:42 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > 
> > > > > > Enhance preloader header with both additional program
> > > > > > length
> > > > > > and
> > > > > > program
> > > > > > entry offset attributes, which offset is relative to the
> > > > > > start
> > > > > > of
> > > > > > program
> > > > > > header.
> > > > > > 
> > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > ---
> > > > > >  arch/arm/mach-socfpga/include/mach/boot0.h | 11 +++++++++-
> > > > > > -
> > > > > >  1 file changed, 9 insertions(+), 2 deletions(-)
> > > > > > 
> > > > > > diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h
> > > > > > b/arch/arm/mach-socfpga/include/mach/boot0.h
> > > > > > index 22d9e7f..33c9368 100644
> > > > > > --- a/arch/arm/mach-socfpga/include/mach/boot0.h
> > > > > > +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
> > > > > > @@ -11,8 +11,15 @@
> > > > > >  	.balignl 64,0xf33db33f;
> > > > > >  
> > > > > >  	.word	0x1337c0d3;	/* SoCFPGA
> > > > > > preloader
> > > > > > validation word */
> > > > > > -	.word	0xc01df00d;	/* Version, flags,
> > > > > > length
> > > > > > */
> > > > > > -	.word	0xcafec0d3;	/* Checksum, zero-
> > > > > > pad
> > > > > > */
> > > > > > +	.word	0xc01df00d; /* Header
> > > > > > length(2B),flags(1B),version(1B) */
> > > > > > +#ifndef CONFIG_TARGET_SOCFPGA_GEN5
> > > > > > +	.word	0xfeedface; /* Program length(4B) */
> > > > > Keep this indent intact, then it won't generate these crappy
> > > > > -
> > > > > entries.
> > > > > 
> > > > Are you saying to keep the comment indent intact, and allign
> > > > with
> > > > 1st
> > > > comment  /* SoCFPGA preloader validation word */ ?
> > > Just look at the diff and make sure that it only changes the
> > > relevant
> > > parts, not extras due to indent changes.
> > > 
> > Not get you, which particular change is due to indent changes only?
> > Some changes are for re-writing more descriptive comment. And some
> > new
> > adding header attributes to support Arria 10.
> Aaargh, then don't do two things in one patch.
> 
I can split them.
> > 
> > > 
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > +	.word	0xf00dcafe; /*
> > > > > > +			     * Program entry
> > > > > > offset(4B),relative
> > > > > > to
> > > > > > +			     * the start of program header
> > > > > > +			     */
> > > > > > +#endif
> > > > > > +	.word	0xcafec0d3;	/* Simple
> > > > > > checksum(2B),spare offset(2B) */
> > > > > >  	nop;
> > > > > >  
> > > > > >  	b reset;		/* SoCFPGA jumps here */
> > > > > > 
> 

[U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory allocation in SPL

[Chee, Tien Fong]

On Rab, 2017-09-27 at 10:32 +0200, Marek Vasut wrote:
> On 09/27/2017 07:43 AM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2017-09-26 at 12:37 +0200, Marek Vasut wrote:
> > > 
> > > On 09/26/2017 07:06 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Isn, 2017-09-25 at 11:21 +0200, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > 
> > > > > > Add support to memory allocation in SPL for preparation to
> > > > > > enable
> > > > > > FAT
> > > > > > in SPL. Memory allocation is needed by FAT to work
> > > > > > properly.
> > > > > > 
> > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > Gen 5 does have malloc support in SPL, so what's the deal
> > > > > here ?
> > > > > 
> > > > For FAT to work properly in Arria 10 SPL, SPL malloc need to be
> > > > enabled,
> > > It is already enabled on Gen 5
> > > 
> > I think i have confused you, this patch is for getting the malloc
> > area
> > mapping to Arria 10 SRAM memory correctly. I will improve the
> > commit
> > message.
> > > 
> > > > 
> > > > 
> > > > and the min of SPL malloc size is 0x2000.
> > > Where did you find about this minimum ? That can be configured
> > > ...
> > > 
> > I having issue to boot u-boot successful(Hung or reset), after
> > debuging
> > through debugger, just found that 0x2000 is min required.
> You can set the value much lower and depending on the requirements,
> it
> will work, so the problem must be elsewhere ...
> 
Okay, i will test it out.
> > 
> > > 
> > > > 
> > > > 
> > > > FAT needed in Arria
> > > > 10 SPL, because u-boot.img is stored in FAT partition.
> > > It can also be stored on ext partition (which is preferred,
> > > patent-
> > > wise)
> > > 
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > ---
> > > > > >  include/configs/socfpga_common.h | 23
> > > > > > ++++++++++++++++++++++-
> > > > > >  1 file changed, 22 insertions(+), 1 deletion(-)
> > > > > > 
> > > > > > diff --git a/include/configs/socfpga_common.h
> > > > > > b/include/configs/socfpga_common.h
> > > > > > index 7549ee8..9b6719e 100644
> > > > > > --- a/include/configs/socfpga_common.h
> > > > > > +++ b/include/configs/socfpga_common.h
> > > > > > @@ -280,17 +280,34 @@ unsigned int
> > > > > > cm_get_qspi_controller_clk_hz(void);
> > > > > >  /*
> > > > > >   * SPL
> > > > > >   *
> > > > > > - * SRAM Memory layout:
> > > > > > + * SRAM Memory layout for gen 5:
> > > > > >   *
> > > > > >   * 0xFFFF_0000 ...... Start of SRAM
> > > > > >   * 0xFFFF_xxxx ...... Top of stack (grows down)
> > > > > >   * 0xFFFF_yyyy ...... Malloc area
> > > > > >   * 0xFFFF_zzzz ...... Global Data
> > > > > >   * 0xFFFF_FF00 ...... End of SRAM
> > > > > > + *
> > > > > > + * SRAM Memory layout for Arria 10:
> > > > > > + * 0xFFE0_0000 ...... Start of SRAM (bottom)
> > > > > > + * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
> > > > > > + * 0xFFEy_yyyy ...... Malloc area (grows up to top)
> > > > > > + * 0xFFEz_zzzz ...... Global Data
> > > > > > + * 0xFFE3_FFFF ...... End of SRAM (top)
> > > > > >   */
> > > > > >  #define CONFIG_SPL_FRAMEWORK
> > > > > >  #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INI
> > > > > > T_RA
> > > > > > M_AD
> > > > > > DR
> > > > > >  #define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT
> > > > > > _RAM
> > > > > > _SIZ
> > > > > > E
> > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > > > +/* SPL memory allocation configuration, it is required by
> > > > > > FAT
> > > > > > feature */
> > > > > > +#ifndef CONFIG_SYS_SPL_MALLOC_START
> > > > > > +#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00002000
> > > > > > +#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_INI
> > > > > > T_RA
> > > > > > M_SI
> > > > > > ZE - \
> > > > > > +					 GENERATED_GBL_DAT
> > > > > > A_SI
> > > > > > ZE -
> > > > > > \
> > > > > > +					 CONFIG_SYS_SPL_MA
> > > > > > LLOC
> > > > > > _SIZ
> > > > > > E + \
> > > > > > +					 CONFIG_SYS_INIT_R
> > > > > > AM_A
> > > > > > DDR)
> > > > > > +#endif
> > > > > > +#endif
> > > > > >  
> > > > > >  /* SPL SDMMC boot support */
> > > > > >  #ifdef CONFIG_SPL_MMC_SUPPORT
> > > > > > @@ -320,7 +337,11 @@ unsigned int
> > > > > > cm_get_qspi_controller_clk_hz(void);
> > > > > >  /*
> > > > > >   * Stack setup
> > > > > >   */
> > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > > >  #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP
> > > > > > _ADD
> > > > > > R
> > > > > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > > > +#define CONFIG_SPL_STACK		(CONFIG_SYS_SPL_MA
> > > > > > LLOC
> > > > > > _STA
> > > > > > RT - 1)
> > > > > > +#endif
> > > > > >  
> > > > > >  /* Extra Environment */
> > > > > >  #ifndef CONFIG_SPL_BUILD
> > > > > > 
> 

[U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA RBF properties at Arria 10 FPGA manager

[Chee, Tien Fong]

On Rab, 2017-09-27 at 10:29 +0200, Marek Vasut wrote:
> On 09/27/2017 05:12 AM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2017-09-26 at 12:30 +0200, Marek Vasut wrote:
> > > 
> > > On 09/26/2017 10:54 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Isn, 2017-09-25 at 11:00 +0200, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 09/25/2017 10:39 AM, tien.fong.chee at intel.com wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > 
> > > > > > This patch adds description on properties about location of
> > > > > > FPGA
> > > > > > RBFs are
> > > > > > stored, type and functionality of RBF used to configure
> > > > > > FPGA.
> > > > > > 
> > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > Why does this patch have different tags than 1/19 ? Please
> > > > > keep
> > > > > things
> > > > > consistent ...
> > > > > 
> > > > Not get you. What's you means for tags?
> > > ARM: socfpga: , not the random doc: dtbinding: .
> > > Heck, the first and second patch change the same file, yet have
> > > different tags, why ?
> > > 
> > I ported patch 01 from Linux, so i keep everything intact. For
> > patch
> > 02, i put doc:dtbinding because i think that is more descriptive to
> > the
> > file i changed.
> > I can change to ARM:socfpga .
> The tags are standardized ... inventing new random ones only messes
> things up.
> 
Okay.
> > 
> > > 
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > ---
> > > > > >  doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
> > > > > > mgr.txt
> > > > > > > 
> > > > > > > 11
> > > > > > +++++++++++
> > > > > >  1 file changed, 11 insertions(+)
> > > > > > 
> > > > > > diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-
> > > > > > a10-
> > > > > > fpga-
> > > > > > mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-
> > > > > > fpga-
> > > > > > mgr.txt
> > > > > > index 2fd8e7a..7abb746 100644
> > > > > > --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-
> > > > > > fpga-
> > > > > > mgr.txt
> > > > > > +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-
> > > > > > fpga-
> > > > > > mgr.txt
> > > > > > @@ -7,6 +7,14 @@ Required properties:
> > > > > >                 - The second index is for writing FPGA
> > > > > > configuration data.
> > > > > >  - resets     : Phandle and reset specifier for the
> > > > > > device's
> > > > > > reset.
> > > > > >  - clocks     : Clocks used by the device.
> > > > > > +- bitstream_periph : FPGA peripheral raw binary file which
> > > > > > is
> > > > > > used
> > > > > > to
> > > > > > +                     initialize FPGA IOs, PLL, IO48 and
> > > > > > DDR.
> > > > > > +- bitstream_core : FPGA core raw binary file contains FPGA
> > > > > > design
> > > > > > which is used
> > > > > > +                   to program FPGA CRAM and ERAM.
> > > > > > +- bitstream_devpart : Partition of flash device where
> > > > > > bitstream
> > > > > > files are
> > > > > > +		       stored.
> > > > > > +                      <dev[:part]> - dev is flash device
> > > > > > number,
> > > > > > part is flash
> > > > > > +                                     device partition.
> > > > > >  
> > > > > >  Example:
> > > > > >  
> > > > > > @@ -16,4 +24,7 @@ Example:
> > > > > >  		       0xffcfe400 0x20>;
> > > > > >  		clocks = <&l4_mp_clk>;
> > > > > >  		resets = <&rst FPGAMGR_RESET>;
> > > > > > +		bitstream_periph =
> > > > > > "ghrd_10as066n2.periph.rbf.mkimage";
> > > > > > +		bitstream_core =
> > > > > > "ghrd_10as066n2.core.rbf.mkimage";
> > > > > > +		bitstream_devpart = "0:1";
> > > > > >  	};
> > > > > > 
> 

[U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA from flash

[Chee, Tien Fong]

On Rab, 2017-09-27 at 11:23 +0200, Marek Vasut wrote:
> On 09/27/2017 11:13 AM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2017-09-26 at 12:39 +0200, Marek Vasut wrote:
> > > 
> > > On 09/26/2017 11:52 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > 
> > > > > > These drivers handle FPGA program operation from flash
> > > > > > loading
> > > > > > RBF to memory and then to program FPGA.
> > > > > > 
> > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > [...]
> > > 
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > +const char *get_cff_devpart(const void *fdt, int *len)
> > > > > > +{
> > > > > > +	const char *cff_devpart = NULL;
> > > > > > +	const char *cell;
> > > > > > +	int nodeoffset;
> > > > > > +	nodeoffset = fdtdec_next_compatible(fdt, 0,
> > > > > > +			 COMPAT_ALTERA_SOCFPGA_FPGA0);
> > > > > > +
> > > > > > +	cell = fdt_getprop(fdt, nodeoffset,
> > > > > > "bitstream_devpart",
> > > > > > len);
> > > > > > +
> > > > > > +	if (cell)
> > > > > > +		cff_devpart = cell;
> > > > > > +
> > > > > > +	return cff_devpart;
> > > > > > +}
> > > > > Take a look at splash*.c , I believe that can be reworked
> > > > > into
> > > > > generic
> > > > > firmware loader , which you could then use here.
> > > > > 
> > > > the devpart is hard coded in splash*.c. The function here is
> > > > getting
> > > > devpart info from DTS. So, is there any similar function in
> > > > splash*.c?
> > > > May be you can share more about your idea.
> > > The generic loader could use some work of course ...
> > > 
> > Sorry, i am still confusing. Allow me to ask you more:
> > 1. Is the generic firmware loader already exists in splash*.c?
> No
> 
> > 
> > 2. Are you talking about get_cff_devpart or whole fpga laodfs?
> > 3. You want me integrate get_cff_devpart function into splash*.c?
> > 4. Are you means to hard code the devpart instead providing dynamic
> > devpart described in DTS?
> I am talking about factoring out generic firmware loader from
> splash*c ,
> since it already contains most of the parts for such a thing.
> 
> > 
> > Current implementation are located in spl_board_init func
> > (arcg/arm/mach-socfpga/spl.c). Based on boot device such as mmc,
> > nand
> > and QSPI, then reading some info from DTS, setting dev and
> > partition
> > with generic fs functions, and reading with generic fs function
> > before
> > programming RBF into FPGA. All these are in patch 19.
> That's what splash*c also does, so adding separate parallel
> implementation of the same functionality is a no-no.
> 
After reading through splash*c, i found there are two functions bear a
close similarity to.
1st function -->
In /common/splash.c : 
static struct splash_location default_splash_locations[] = {
	{
		.name = "sf",
		.storage = SPLASH_STORAGE_SF,
		.flags = SPLASH_STORAGE_RAW,
		.offset = 0x0,
	},
	{
		.name = "mmc_fs",
		.storage = SPLASH_STORAGE_MMC,
		.flags = SPLASH_STORAGE_FS,
		.devpart = "0:1",
	},
	{
		.name = "usb_fs",
		.storage = SPLASH_STORAGE_USB,
		.flags = SPLASH_STORAGE_FS,
		.devpart = "0:1",
	},
	{
		.name = "sata_fs",
		.storage = SPLASH_STORAGE_SATA,
		.flags = SPLASH_STORAGE_FS,
		.devpart = "0:1",
	},
};

In my /arch/arm/mach-socfpga/spl.c (spl_board_init(void))
bootdev.boot_device = spl_boot_device();

	if (BOOT_DEVICE_MMC1 == bootdev.boot_device) {
		struct mmc *mmc = NULL;
		int err = 0;

		spl_mmc_find_device(&mmc, bootdev.boot_device);

		err = mmc_init(mmc);

		if (err) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
			printf("spl: mmc init failed with error: %d\n",
err);
#endif
		}

		fpga_fsinfo.dev_part = (char *)get_cff_devpart(gd-
>fdt_blob,
								 &len);

		fpga_fsinfo.filename = (char *)get_cff_filename(gd-
>fdt_blob,
								 &len,
								PERIPH_
RBF);

		fpga_fsinfo.interface = "mmc";

		fpga_fsinfo.fstype = FS_TYPE_FAT;
	} else {
		printf("Invalid boot device!\n");
		return;
	}

	/* Program peripheral RBF */
	if (fpga_fsinfo.filename && fpga_fsinfo.dev_part && (len > 0))
		rval = fpga_fsload(0, buffer, BSIZE, &fpga_fsinfo);

In /common/splash.c, dev_Part and flash type everything are hard coded
in struct splash_location. In my spl.c, flash type are determined on
run time and dev_part are retrived from DTS, and then assigned to
struct fpga_fsinfo. Please note that this is in SPL, mmc need to be
initialized 1st before loading raw file into memory. In SPL, raw file
are coppied to OCRAM chunk by chunk, but In u-boot it would normally
done in one big chunk to DRAM. This would be handled by fpga loadfs.

So, you want me hard code everthing like in splash.c?

2nd function -->
In /common/splash_source.c
static int splash_select_fs_dev(struct splash_location *location)
{
	int res;

	switch (location->storage) {
	case SPLASH_STORAGE_MMC:
		res = fs_set_blk_dev("mmc", location->devpart,
FS_TYPE_ANY);
		break;
	case SPLASH_STORAGE_USB:
		res = fs_set_blk_dev("usb", location->devpart,
FS_TYPE_ANY);
		break;
	case SPLASH_STORAGE_SATA:
		res = fs_set_blk_dev("sata", location->devpart,
FS_TYPE_ANY);
		break;
	case SPLASH_STORAGE_NAND:
		if (location->ubivol != NULL)
			res = fs_set_blk_dev("ubi", NULL,
FS_TYPE_UBIFS);
		else
			res = -ENODEV;
		break;
	default:
		printf("Error: unsupported location storage.\n");
		return -ENODEV;
	}

	if (res)
		printf("Error: could not access storage.\n");

	return res;
}

In my /drivers/fpga/socfpga_arria10.c
static int flash_read(struct flash_info *flashinfo,
	u32 size_read,
	u32 *buffer_ptr)
{
	size_t ret = EEXIST;
	loff_t actread = 0;

	if (fs_set_blk_dev(flashinfo->interface, flashinfo->dev_part,
				flashinfo->fstype))
		return FPGA_FAIL;

	ret = fs_read(flashinfo->filename,
			(u32) buffer_ptr, flashinfo->flash_offset,
			size_read, &actread);

	if (ret || actread != size_read) {
		printf("Failed to read %s from flash %d ",
			flashinfo->filename,
			 ret);
		printf("!= %d.\n", size_read);
		return -EPERM;
		} else
			ret = actread;

	return ret;
}

Some attributes like flash type is determined on run time and and
dev_part is retrieved from DTS, so every infos driver need to know are
assinged into struct flashinfo and passed to fs_set_blk_dev as
arguments. I found that function in splash_source.c some like flash
type are getting from env variable, but we are still in SPL phase,
those env variable is not set up yet. So, i think that is very
ineffcient to factor out them as common.

If you want me create a generic firmware loader which is generic enough
loading content for all components like flashes, FPGA, splash ....etc,
i don't think that is effient enough, as fpga loadfs has different
handling in both SPL and U-boot like copying raw into memory.

It would be good you can direct point me out which functions have
similirity and how to factor them out as common.

Thanks a lot.
> > 
> > Thanks.
> > > 
> > > [...]
> 

[U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA from flash

[Marek Vasut]

On 09/28/2017 05:14 PM, Chee, Tien Fong wrote:
> On Rab, 2017-09-27 at 11:23 +0200, Marek Vasut wrote:
>> On 09/27/2017 11:13 AM, Chee, Tien Fong wrote:
>>>
>>> On Sel, 2017-09-26 at 12:39 +0200, Marek Vasut wrote:
>>>>
>>>> On 09/26/2017 11:52 AM, Chee, Tien Fong wrote:
>>>>>
>>>>>
>>>>> On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:
>>>>>>
>>>>>>
>>>>>> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>>>>
>>>>>>> These drivers handle FPGA program operation from flash
>>>>>>> loading
>>>>>>> RBF to memory and then to program FPGA.
>>>>>>>
>>>>>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>>> [...]
>>>>
>>>>>
>>>>>
>>>>>>
>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> +const char *get_cff_devpart(const void *fdt, int *len)
>>>>>>> +{
>>>>>>> +	const char *cff_devpart = NULL;
>>>>>>> +	const char *cell;
>>>>>>> +	int nodeoffset;
>>>>>>> +	nodeoffset = fdtdec_next_compatible(fdt, 0,
>>>>>>> +			 COMPAT_ALTERA_SOCFPGA_FPGA0);
>>>>>>> +
>>>>>>> +	cell = fdt_getprop(fdt, nodeoffset,
>>>>>>> "bitstream_devpart",
>>>>>>> len);
>>>>>>> +
>>>>>>> +	if (cell)
>>>>>>> +		cff_devpart = cell;
>>>>>>> +
>>>>>>> +	return cff_devpart;
>>>>>>> +}
>>>>>> Take a look at splash*.c , I believe that can be reworked
>>>>>> into
>>>>>> generic
>>>>>> firmware loader , which you could then use here.
>>>>>>
>>>>> the devpart is hard coded in splash*.c. The function here is
>>>>> getting
>>>>> devpart info from DTS. So, is there any similar function in
>>>>> splash*.c?
>>>>> May be you can share more about your idea.
>>>> The generic loader could use some work of course ...
>>>>
>>> Sorry, i am still confusing. Allow me to ask you more:
>>> 1. Is the generic firmware loader already exists in splash*.c?
>> No
>>
>>>
>>> 2. Are you talking about get_cff_devpart or whole fpga laodfs?
>>> 3. You want me integrate get_cff_devpart function into splash*.c?
>>> 4. Are you means to hard code the devpart instead providing dynamic
>>> devpart described in DTS?
>> I am talking about factoring out generic firmware loader from
>> splash*c ,
>> since it already contains most of the parts for such a thing.
>>
>>>
>>> Current implementation are located in spl_board_init func
>>> (arcg/arm/mach-socfpga/spl.c). Based on boot device such as mmc,
>>> nand
>>> and QSPI, then reading some info from DTS, setting dev and
>>> partition
>>> with generic fs functions, and reading with generic fs function
>>> before
>>> programming RBF into FPGA. All these are in patch 19.
>> That's what splash*c also does, so adding separate parallel
>> implementation of the same functionality is a no-no.
>>
> After reading through splash*c, i found there are two functions bear a
> close similarity to.
> 1st function -->
> In /common/splash.c : 
> static struct splash_location default_splash_locations[] = {
> 	{
> 		.name = "sf",
> 		.storage = SPLASH_STORAGE_SF,
> 		.flags = SPLASH_STORAGE_RAW,
> 		.offset = 0x0,
> 	},
> 	{
> 		.name = "mmc_fs",
> 		.storage = SPLASH_STORAGE_MMC,
> 		.flags = SPLASH_STORAGE_FS,
> 		.devpart = "0:1",
> 	},
> 	{
> 		.name = "usb_fs",
> 		.storage = SPLASH_STORAGE_USB,
> 		.flags = SPLASH_STORAGE_FS,
> 		.devpart = "0:1",
> 	},
> 	{
> 		.name = "sata_fs",
> 		.storage = SPLASH_STORAGE_SATA,
> 		.flags = SPLASH_STORAGE_FS,
> 		.devpart = "0:1",
> 	},
> };
> 
> In my /arch/arm/mach-socfpga/spl.c (spl_board_init(void))
> bootdev.boot_device = spl_boot_device();
> 
> 	if (BOOT_DEVICE_MMC1 == bootdev.boot_device) {
> 		struct mmc *mmc = NULL;
> 		int err = 0;
> 
> 		spl_mmc_find_device(&mmc, bootdev.boot_device);
> 
> 		err = mmc_init(mmc);
> 
> 		if (err) {
> #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
> 			printf("spl: mmc init failed with error: %d\n",
> err);
> #endif
> 		}
> 
> 		fpga_fsinfo.dev_part = (char *)get_cff_devpart(gd-
>> fdt_blob,
> 								 &len);
> 
> 		fpga_fsinfo.filename = (char *)get_cff_filename(gd-
>> fdt_blob,
> 								 &len,
> 								PERIPH_
> RBF);
> 
> 		fpga_fsinfo.interface = "mmc";
> 
> 		fpga_fsinfo.fstype = FS_TYPE_FAT;
> 	} else {
> 		printf("Invalid boot device!\n");
> 		return;
> 	}
> 
> 	/* Program peripheral RBF */
> 	if (fpga_fsinfo.filename && fpga_fsinfo.dev_part && (len > 0))
> 		rval = fpga_fsload(0, buffer, BSIZE, &fpga_fsinfo);
> 
> In /common/splash.c, dev_Part and flash type everything are hard coded
> in struct splash_location. In my spl.c, flash type are determined on
> run time and dev_part are retrived from DTS, and then assigned to
> struct fpga_fsinfo. Please note that this is in SPL, mmc need to be
> initialized 1st before loading raw file into memory. In SPL, raw file
> are coppied to OCRAM chunk by chunk, but In u-boot it would normally
> done in one big chunk to DRAM. This would be handled by fpga loadfs.
> 
> So, you want me hard code everthing like in splash.c?

No, I need you to play around with this and come up with generic
firmware loader that's flexible enough.

> 2nd function -->
> In /common/splash_source.c
> static int splash_select_fs_dev(struct splash_location *location)
> {
> 	int res;
> 
> 	switch (location->storage) {
> 	case SPLASH_STORAGE_MMC:
> 		res = fs_set_blk_dev("mmc", location->devpart,
> FS_TYPE_ANY);
> 		break;
> 	case SPLASH_STORAGE_USB:
> 		res = fs_set_blk_dev("usb", location->devpart,
> FS_TYPE_ANY);
> 		break;
> 	case SPLASH_STORAGE_SATA:
> 		res = fs_set_blk_dev("sata", location->devpart,
> FS_TYPE_ANY);
> 		break;
> 	case SPLASH_STORAGE_NAND:
> 		if (location->ubivol != NULL)
> 			res = fs_set_blk_dev("ubi", NULL,
> FS_TYPE_UBIFS);
> 		else
> 			res = -ENODEV;
> 		break;
> 	default:
> 		printf("Error: unsupported location storage.\n");
> 		return -ENODEV;
> 	}
> 
> 	if (res)
> 		printf("Error: could not access storage.\n");
> 
> 	return res;
> }
> 
> In my /drivers/fpga/socfpga_arria10.c
> static int flash_read(struct flash_info *flashinfo,
> 	u32 size_read,
> 	u32 *buffer_ptr)
> {
> 	size_t ret = EEXIST;
> 	loff_t actread = 0;
> 
> 	if (fs_set_blk_dev(flashinfo->interface, flashinfo->dev_part,
> 				flashinfo->fstype))
> 		return FPGA_FAIL;
> 
> 	ret = fs_read(flashinfo->filename,
> 			(u32) buffer_ptr, flashinfo->flash_offset,
> 			size_read, &actread);
> 
> 	if (ret || actread != size_read) {
> 		printf("Failed to read %s from flash %d ",
> 			flashinfo->filename,
> 			 ret);
> 		printf("!= %d.\n", size_read);
> 		return -EPERM;
> 		} else
> 			ret = actread;
> 
> 	return ret;
> }
> 
> Some attributes like flash type is determined on run time and and
> dev_part is retrieved from DTS, so every infos driver need to know are
> assinged into struct flashinfo and passed to fs_set_blk_dev as
> arguments. I found that function in splash_source.c some like flash
> type are getting from env variable, but we are still in SPL phase,
> those env variable is not set up yet. So, i think that is very
> ineffcient to factor out them as common.
> 
> If you want me create a generic firmware loader which is generic enough
> loading content for all components like flashes, FPGA, splash ....etc,
> i don't think that is effient enough, as fpga loadfs has different
> handling in both SPL and U-boot like copying raw into memory.

Duplicating code is nonsense and I believe generic firmware loader would
be the way to go here.

> It would be good you can direct point me out which functions have
> similirity and how to factor them out as common.
> 
> Thanks a lot.
>>>
>>> Thanks.
>>>>
>>>> [...]


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 04/19] arm: socfpga: Add Arria 10 SoCFPGA programming interface

[Chee, Tien Fong]

On Isn, 2017-09-25 at 11:03 +0200, Marek Vasut wrote:
> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > Add code necessary into the FPGA driver framework in U-Boot
> > so it can be used via the 'fpga' command for programing Arria 10
> > SoCFPGA.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> [...]
> 
> > 
> > +#if defined(CONFIG_CMD_FPGA_LOADFS)
> > +int altera_loadfs(Altera_desc *desc, const void *buf, size_t
> > bsize,
> > +		   fpga_fs_info *fpga_fsinfo)
> > +{
> > +	const struct altera_fpga *fpga = altera_desc_to_fpga(desc,
> > __func__);
> > +
> > +	if (!fpga)
> > +		return FPGA_FAIL;
> > +
> > +	debug_cond(FPGA_DEBUG, "%s: Launching the %s FS
> > Loader...\n",
> > +		   __func__, fpga->name);
> > +	if (fpga->loadfs)
> > +		return fpga->loadfs(desc, buf, bsize,
> > fpga_fsinfo);
> > +	return 0;
> return -EINVAL , since the loader could not be started ?
> 
Okay.
> > 
> > +}
> > +#endif
> [...]
> 

[U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size initialization function

[Chee, Tien Fong]

On Sel, 2017-09-26 at 12:33 +0200, Marek Vasut wrote:
> On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2017-09-25 at 11:15 +0200, Marek Vasut wrote:
> > > 
> > > On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > 
> > > > Add function for both multiple DRAM bank and single DRAM bank
> > > > size
> > > > initialization. This common functionality could be used by
> > > > every
> > > > single
> > > > SOCFPGA board.
> > > > 
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > I'd like TB on Gen5.
> > > 
> > What is TB?
> Tested-by
> Tested-by: Tien Fong Chee <tien.fong.chee@intel.com>

You want me resend the patch with Tested-by?
> > 
> > > 
> > > > 
> > > > 
> > > > ---
> > > >  arch/arm/mach-socfpga/board.c    | 7 +++++++
> > > >  include/configs/socfpga_common.h | 1 +
> > > >  2 files changed, 8 insertions(+)
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-
> > > > socfpga/board.c
> > > > index a41d089..965f9dc 100644
> > > > --- a/arch/arm/mach-socfpga/board.c
> > > > +++ b/arch/arm/mach-socfpga/board.c
> > > > @@ -29,6 +29,13 @@ int board_init(void)
> > > >  	return 0;
> > > >  }
> > > >  
> > > > +int dram_init_banksize(void)
> > > > +{
> > > > +	fdtdec_setup_memory_banksize();
> > > > +
> > > > +	return 0;
> > > > +}
> > > > +
> > > >  #ifdef CONFIG_USB_GADGET
> > > >  struct dwc2_plat_otg_data socfpga_otg_data = {
> > > >  	.usb_gusbcfg	= 0x1417,
> > > > diff --git a/include/configs/socfpga_common.h
> > > > b/include/configs/socfpga_common.h
> > > > index eadce2d..7549ee8 100644
> > > > --- a/include/configs/socfpga_common.h
> > > > +++ b/include/configs/socfpga_common.h
> > > > @@ -47,6 +47,7 @@
> > > >  	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> > > >  
> > > >  #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
> > > > +#define CONFIG_SYS_SDRAM_SIZE		PHYS_SDRAM_1_SIZE
> > > >  #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
> > > >  #define CONFIG_SYS_TEXT_BASE		0x08000040
> > > >  #else
> > > > 
> 

[U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size initialization function

[Marek Vasut]

On 10/02/2017 12:01 PM, Chee, Tien Fong wrote:
> On Sel, 2017-09-26 at 12:33 +0200, Marek Vasut wrote:
>> On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:
>>>
>>> On Isn, 2017-09-25 at 11:15 +0200, Marek Vasut wrote:
>>>>
>>>> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
>>>>>
>>>>>
>>>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>>
>>>>> Add function for both multiple DRAM bank and single DRAM bank
>>>>> size
>>>>> initialization. This common functionality could be used by
>>>>> every
>>>>> single
>>>>> SOCFPGA board.
>>>>>
>>>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>>> I'd like TB on Gen5.
>>>>
>>> What is TB?
>> Tested-by
>> Tested-by: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> You want me resend the patch with Tested-by?

Uh no, that's not how TB works. You should get TB on your patches from
someone else , not yourself .

>>>
>>>>
>>>>>
>>>>>
>>>>> ---
>>>>>  arch/arm/mach-socfpga/board.c    | 7 +++++++
>>>>>  include/configs/socfpga_common.h | 1 +
>>>>>  2 files changed, 8 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-
>>>>> socfpga/board.c
>>>>> index a41d089..965f9dc 100644
>>>>> --- a/arch/arm/mach-socfpga/board.c
>>>>> +++ b/arch/arm/mach-socfpga/board.c
>>>>> @@ -29,6 +29,13 @@ int board_init(void)
>>>>>  	return 0;
>>>>>  }
>>>>>  
>>>>> +int dram_init_banksize(void)
>>>>> +{
>>>>> +	fdtdec_setup_memory_banksize();
>>>>> +
>>>>> +	return 0;
>>>>> +}
>>>>> +
>>>>>  #ifdef CONFIG_USB_GADGET
>>>>>  struct dwc2_plat_otg_data socfpga_otg_data = {
>>>>>  	.usb_gusbcfg	= 0x1417,
>>>>> diff --git a/include/configs/socfpga_common.h
>>>>> b/include/configs/socfpga_common.h
>>>>> index eadce2d..7549ee8 100644
>>>>> --- a/include/configs/socfpga_common.h
>>>>> +++ b/include/configs/socfpga_common.h
>>>>> @@ -47,6 +47,7 @@
>>>>>  	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
>>>>>  
>>>>>  #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
>>>>> +#define CONFIG_SYS_SDRAM_SIZE		PHYS_SDRAM_1_SIZE
>>>>>  #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
>>>>>  #define CONFIG_SYS_TEXT_BASE		0x08000040
>>>>>  #else
>>>>>


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency info for U-boot

[Chee, Tien Fong]

On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:
> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > Clock frequency info is required in U-boot.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> I want a TB on Gen 5
> 
This patch break the gen5, because cm_basic_init is exclusive for Arria
10. #ifdef is required.
> > 
> > ---
> >  arch/arm/mach-socfpga/board.c | 6 ++++++
> >  1 file changed, 6 insertions(+)
> > 
> > diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-
> > socfpga/board.c
> > index 965f9dc..a00f63b 100644
> > --- a/arch/arm/mach-socfpga/board.c
> > +++ b/arch/arm/mach-socfpga/board.c
> > @@ -8,7 +8,10 @@
> >  
> >  #include <common.h>
> >  #include <errno.h>
> > +#include <fdtdec.h>
> >  #include <asm/arch/reset_manager.h>
> > +#include <asm/arch/clock_manager.h>
> > +#include <asm/arch/misc.h>
> >  #include <asm/io.h>
> >  
> >  #include <usb.h>
> > @@ -26,6 +29,9 @@ int board_init(void)
> >  	/* Address of boot parameters for ATAG (if ATAG is used)
> > */
> >  	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> >  
> > +	/* configuring the clock based on handoff */
> > +	cm_basic_init(gd->fdt_blob);
> > +
> >  	return 0;
> >  }
> >  
> > 
> 

[U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size initialization function

[Chee, Tien Fong]

On Isn, 2017-10-02 at 12:04 +0200, Marek Vasut wrote:
> On 10/02/2017 12:01 PM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2017-09-26 at 12:33 +0200, Marek Vasut wrote:
> > > 
> > > On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Isn, 2017-09-25 at 11:15 +0200, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > 
> > > > > > Add function for both multiple DRAM bank and single DRAM
> > > > > > bank
> > > > > > size
> > > > > > initialization. This common functionality could be used by
> > > > > > every
> > > > > > single
> > > > > > SOCFPGA board.
> > > > > > 
> > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > I'd like TB on Gen5.
> > > > > 
> > > > What is TB?
> > > Tested-by
> > > Tested-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > You want me resend the patch with Tested-by?
> Uh no, that's not how TB works. You should get TB on your patches
> from
> someone else , not yourself .
> 
oo...okay, i will ask ley foon help to verify.
> > 
> > > 
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > ---
> > > > > >  arch/arm/mach-socfpga/board.c    | 7 +++++++
> > > > > >  include/configs/socfpga_common.h | 1 +
> > > > > >  2 files changed, 8 insertions(+)
> > > > > > 
> > > > > > diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-
> > > > > > socfpga/board.c
> > > > > > index a41d089..965f9dc 100644
> > > > > > --- a/arch/arm/mach-socfpga/board.c
> > > > > > +++ b/arch/arm/mach-socfpga/board.c
> > > > > > @@ -29,6 +29,13 @@ int board_init(void)
> > > > > >  	return 0;
> > > > > >  }
> > > > > >  
> > > > > > +int dram_init_banksize(void)
> > > > > > +{
> > > > > > +	fdtdec_setup_memory_banksize();
> > > > > > +
> > > > > > +	return 0;
> > > > > > +}
> > > > > > +
> > > > > >  #ifdef CONFIG_USB_GADGET
> > > > > >  struct dwc2_plat_otg_data socfpga_otg_data = {
> > > > > >  	.usb_gusbcfg	= 0x1417,
> > > > > > diff --git a/include/configs/socfpga_common.h
> > > > > > b/include/configs/socfpga_common.h
> > > > > > index eadce2d..7549ee8 100644
> > > > > > --- a/include/configs/socfpga_common.h
> > > > > > +++ b/include/configs/socfpga_common.h
> > > > > > @@ -47,6 +47,7 @@
> > > > > >  	(CONFIG_SYS_INIT_RAM_ADDR +
> > > > > > CONFIG_SYS_INIT_SP_OFFSET)
> > > > > >  
> > > > > >  #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
> > > > > > +#define CONFIG_SYS_SDRAM_SIZE		PHYS_SDRAM_1_
> > > > > > SIZE
> > > > > >  #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
> > > > > >  #define CONFIG_SYS_TEXT_BASE		0x08000040
> > > > > >  #else
> > > > > > 
> 

[U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency info for U-boot

[Marek Vasut]

On 10/02/2017 12:04 PM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>
>>> Clock frequency info is required in U-boot.
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>> I want a TB on Gen 5
>>
> This patch break the gen5, because cm_basic_init is exclusive for Arria
> 10. #ifdef is required.

Can you at least build-test your patches before submitting ?
Heck, you can also set up the travisci [1] to do all that stuff for you.

[1] https://travis-ci.org/marex/u-boot-socfpga/branches

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency info for U-boot

[Chee, Tien Fong]

On Isn, 2017-10-02 at 12:10 +0200, Marek Vasut wrote:
> On 10/02/2017 12:04 PM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:
> > > 
> > > On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > 
> > > > Clock frequency info is required in U-boot.
> > > > 
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > I want a TB on Gen 5
> > > 
> > This patch break the gen5, because cm_basic_init is exclusive for
> > Arria
> > 10. #ifdef is required.
> Can you at least build-test your patches before submitting ?
> Heck, you can also set up the travisci [1] to do all that stuff for
> you.
> 
> [1] https://travis-ci.org/marex/u-boot-socfpga/branches
> 
Okay.

[U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size initialization function

[Ley Foon Tan]

On Mon, Oct 2, 2017 at 6:06 PM, Chee, Tien Fong
<tien.fong.chee@intel.com> wrote:
> On Isn, 2017-10-02 at 12:04 +0200, Marek Vasut wrote:
>> On 10/02/2017 12:01 PM, Chee, Tien Fong wrote:
>> >
>> > On Sel, 2017-09-26 at 12:33 +0200, Marek Vasut wrote:
>> > >
>> > > On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:
>> > > >
>> > > >
>> > > > On Isn, 2017-09-25 at 11:15 +0200, Marek Vasut wrote:
>> > > > >
>> > > > >
>> > > > > On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
>> > > > > >
>> > > > > >
>> > > > > >
>> > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
>> > > > > >
>> > > > > > Add function for both multiple DRAM bank and single DRAM
>> > > > > > bank
>> > > > > > size
>> > > > > > initialization. This common functionality could be used by
>> > > > > > every
>> > > > > > single
>> > > > > > SOCFPGA board.
>> > > > > >
>> > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>> > > > > I'd like TB on Gen5.
>> > > > >
>> > > > What is TB?
>> > > Tested-by
>> > > Tested-by: Tien Fong Chee <tien.fong.chee@intel.com>
>> > You want me resend the patch with Tested-by?
>> Uh no, that's not how TB works. You should get TB on your patches
>> from
>> someone else , not yourself .
>>
> oo...okay, i will ask ley foon help to verify.
>> >
Tested-by: Ley Foon Tan <ley.foon.tan@intel.com>

[U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA from flash

[Simon Glass]

Hi,

On 25 September 2017 at 02:40,  <tien.fong.chee@intel.com> wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> These drivers handle FPGA program operation from flash loading
> RBF to memory and then to program FPGA.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  .../include/mach/fpga_manager_arria10.h            |  27 ++
>  drivers/fpga/socfpga_arria10.c                     | 391 ++++++++++++++++++++-
>  include/altera.h                                   |   6 +
>  include/configs/socfpga_common.h                   |   4 +
>  4 files changed, 425 insertions(+), 3 deletions(-)

Agreed on the generic loader, but also, can you please use driver
model? Am I missing something?

Regards,
Simon

[U-Boot] [PATCH v2 08/19] fs: Enable generic filesystems interface support in SPL.

[Simon Glass]

On 25 September 2017 at 02:40,  <tien.fong.chee@intel.com> wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> Enable generic filesystem interface drivers(fs.c and fat/) build
> for SPL. This would allow generic filesystem being used in SPL.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  common/spl/Kconfig | 8 ++++++++
>  doc/README.SPL     | 1 +
>  fs/Makefile        | 1 +
>  3 files changed, 10 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 07/19] fdt: Add compatible strings for Arria 10

[Simon Glass]

Hi,

On 25 September 2017 at 03:08, Marek Vasut <marex@denx.de> wrote:
> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>
>> Add compatible strings for Intel Arria 10 SoCFPGA device.
>>
>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>
> Applied, thanks
>
>> ---
>>  include/fdtdec.h | 2 ++
>>  lib/fdtdec.c     | 2 ++
>>  2 files changed, 4 insertions(+)
>>
>> diff --git a/include/fdtdec.h b/include/fdtdec.h
>> index 4a0947c..095ff36 100644
>> --- a/include/fdtdec.h
>> +++ b/include/fdtdec.h
>> @@ -157,6 +157,8 @@ enum fdt_compat_id {
>>       COMPAT_ALTERA_SOCFPGA_F2SDR0,           /* SoCFPGA fpga2SDRAM0 bridge */
>>       COMPAT_ALTERA_SOCFPGA_F2SDR1,           /* SoCFPGA fpga2SDRAM1 bridge */
>>       COMPAT_ALTERA_SOCFPGA_F2SDR2,           /* SoCFPGA fpga2SDRAM2 bridge */
>> +     COMPAT_ALTERA_SOCFPGA_FPGA0,            /* SOCFPGA FPGA manager */
>> +     COMPAT_ALTERA_SOCFPGA_NOC,              /* SOCFPGA Arria 10 NOC */

We should not be adding new things here. There is a clear message at the top:

 * NOTE: This list is basically a TODO list for things that need to be
 * converted to driver model. So don't add new things here unless there is a
 * good reason why driver-model conversion is infeasible. Examples include
 * things which are used before driver model is available.

Can this be converted to driver model please? I'll see if I can remove
this array.

>>
>>       COMPAT_COUNT,
>>  };
>> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
>> index 107a892..03ff75e 100644
>> --- a/lib/fdtdec.c
>> +++ b/lib/fdtdec.c
>> @@ -70,6 +70,8 @@ static const char * const compat_names[COMPAT_COUNT] = {
>>       COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
>>       COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
>>       COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
>> +     COMPAT(ALTERA_SOCFPGA_FPGA0, "altr,socfpga-a10-fpga-mgr"),
>> +     COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"),
>>  };
>>
>>  const char *fdtdec_get_compatible(enum fdt_compat_id id)
>>
>
>
> --
> Best regards,
> Marek Vasut


Regards,
Simon