From: Cyrille Pitchen <cyrille.pitchen@atmel.com> To: Yunhui Cui <B56489@freescale.com>, <dwmw2@infradead.org>, <computersforpeace@gmail.com>, <han.xu@freescale.com>, <jagannadh.teki@gmail.com> Cc: Yunhui Cui <yunhui.cui@nxp.com>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <yao.yuan@nxp.com> Subject: Re: [PATCH v3 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR Date: Fri, 30 Sep 2016 12:04:46 +0200 [thread overview] Message-ID: <22010794-652a-4f1e-21ec-4f0025073a82@atmel.com> (raw) In-Reply-To: <1471505884-33996-1-git-send-email-B56489@freescale.com> Hi Yunhui, Indeed it's a really good thing to update the Freescale QSPI controller driver so it relies more on the settings chosen in spi-nor.c: it avoids duplicating the code. spi-nor.c is supposed to select all the instruction codes and memory settings according to both the (Q)SPI memory and the controller capabilities. The controller driver should only be responsible for sending the SPI commands but should neither modify those commands nor be aware of the actual memory connected to it. So the idea of this patch is great :) Best regards, Cyrille Le 18/08/2016 à 09:37, Yunhui Cui a écrit : > We can get the read/write/erase opcode from the spi nor framework > directly. This patch uses the information stored in the SPI-NOR to > remove the hardcode in the fsl_qspi_init_lut(). > > Signed-off-by: Yunhui Cui <B56489@freescale.com> > Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> > --- > drivers/mtd/spi-nor/fsl-quadspi.c | 40 ++++++++++++--------------------------- > 1 file changed, 12 insertions(+), 28 deletions(-) > > diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c > index 5c82e4e..5ad6402 100644 > --- a/drivers/mtd/spi-nor/fsl-quadspi.c > +++ b/drivers/mtd/spi-nor/fsl-quadspi.c > @@ -373,9 +373,13 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > void __iomem *base = q->iobase; > int rxfifo = q->devtype_data->rxfifo; > u32 lut_base; > - u8 cmd, addrlen, dummy; > int i; > > + struct spi_nor *nor = &q->nor[0]; > + u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT; > + u8 read_op = nor->read_opcode; > + u8 read_dm = nor->read_dummy; > + > fsl_qspi_unlock_lut(q); > > /* Clear all the LUT table */ > @@ -385,20 +389,10 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > /* Quad Read */ > lut_base = SEQID_QUAD_READ * 4; > > - if (q->nor_size <= SZ_16M) { > - cmd = SPINOR_OP_READ_1_1_4; > - addrlen = ADDR24BIT; > - dummy = 8; > - } else { > - /* use the 4-byte address */ > - cmd = SPINOR_OP_READ_1_1_4; > - addrlen = ADDR32BIT; > - dummy = 8; > - } > - > - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), > + qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen), > base + QUADSPI_LUT(lut_base)); > - qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo), > + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | > + LUT1(FSL_READ, PAD4, rxfifo), > base + QUADSPI_LUT(lut_base + 1)); > > /* Write enable */ > @@ -409,16 +403,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > /* Page Program */ > lut_base = SEQID_PP * 4; > > - if (q->nor_size <= SZ_16M) { > - cmd = SPINOR_OP_PP; > - addrlen = ADDR24BIT; > - } else { > - /* use the 4-byte address */ > - cmd = SPINOR_OP_PP; > - addrlen = ADDR32BIT; > - } > - > - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), > + qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) | > + LUT1(ADDR, PAD1, addrlen), > base + QUADSPI_LUT(lut_base)); > qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0), > base + QUADSPI_LUT(lut_base + 1)); > @@ -432,10 +418,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > /* Erase a sector */ > lut_base = SEQID_SE * 4; > > - cmd = q->nor[0].erase_opcode; > - addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT; > - > - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), > + qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) | > + LUT1(ADDR, PAD1, addrlen), > base + QUADSPI_LUT(lut_base)); > > /* Erase the whole chip */ >
WARNING: multiple messages have this Message-ID (diff)
From: cyrille.pitchen@atmel.com (Cyrille Pitchen) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR Date: Fri, 30 Sep 2016 12:04:46 +0200 [thread overview] Message-ID: <22010794-652a-4f1e-21ec-4f0025073a82@atmel.com> (raw) In-Reply-To: <1471505884-33996-1-git-send-email-B56489@freescale.com> Hi Yunhui, Indeed it's a really good thing to update the Freescale QSPI controller driver so it relies more on the settings chosen in spi-nor.c: it avoids duplicating the code. spi-nor.c is supposed to select all the instruction codes and memory settings according to both the (Q)SPI memory and the controller capabilities. The controller driver should only be responsible for sending the SPI commands but should neither modify those commands nor be aware of the actual memory connected to it. So the idea of this patch is great :) Best regards, Cyrille Le 18/08/2016 ? 09:37, Yunhui Cui a ?crit : > We can get the read/write/erase opcode from the spi nor framework > directly. This patch uses the information stored in the SPI-NOR to > remove the hardcode in the fsl_qspi_init_lut(). > > Signed-off-by: Yunhui Cui <B56489@freescale.com> > Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> > --- > drivers/mtd/spi-nor/fsl-quadspi.c | 40 ++++++++++++--------------------------- > 1 file changed, 12 insertions(+), 28 deletions(-) > > diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c > index 5c82e4e..5ad6402 100644 > --- a/drivers/mtd/spi-nor/fsl-quadspi.c > +++ b/drivers/mtd/spi-nor/fsl-quadspi.c > @@ -373,9 +373,13 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > void __iomem *base = q->iobase; > int rxfifo = q->devtype_data->rxfifo; > u32 lut_base; > - u8 cmd, addrlen, dummy; > int i; > > + struct spi_nor *nor = &q->nor[0]; > + u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT; > + u8 read_op = nor->read_opcode; > + u8 read_dm = nor->read_dummy; > + > fsl_qspi_unlock_lut(q); > > /* Clear all the LUT table */ > @@ -385,20 +389,10 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > /* Quad Read */ > lut_base = SEQID_QUAD_READ * 4; > > - if (q->nor_size <= SZ_16M) { > - cmd = SPINOR_OP_READ_1_1_4; > - addrlen = ADDR24BIT; > - dummy = 8; > - } else { > - /* use the 4-byte address */ > - cmd = SPINOR_OP_READ_1_1_4; > - addrlen = ADDR32BIT; > - dummy = 8; > - } > - > - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), > + qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen), > base + QUADSPI_LUT(lut_base)); > - qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo), > + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | > + LUT1(FSL_READ, PAD4, rxfifo), > base + QUADSPI_LUT(lut_base + 1)); > > /* Write enable */ > @@ -409,16 +403,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > /* Page Program */ > lut_base = SEQID_PP * 4; > > - if (q->nor_size <= SZ_16M) { > - cmd = SPINOR_OP_PP; > - addrlen = ADDR24BIT; > - } else { > - /* use the 4-byte address */ > - cmd = SPINOR_OP_PP; > - addrlen = ADDR32BIT; > - } > - > - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), > + qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) | > + LUT1(ADDR, PAD1, addrlen), > base + QUADSPI_LUT(lut_base)); > qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0), > base + QUADSPI_LUT(lut_base + 1)); > @@ -432,10 +418,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > /* Erase a sector */ > lut_base = SEQID_SE * 4; > > - cmd = q->nor[0].erase_opcode; > - addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT; > - > - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), > + qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) | > + LUT1(ADDR, PAD1, addrlen), > base + QUADSPI_LUT(lut_base)); > > /* Erase the whole chip */ >
next prev parent reply other threads:[~2016-09-30 10:04 UTC|newest] Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-08-18 7:37 [PATCH v3 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR Yunhui Cui 2016-08-18 7:37 ` Yunhui Cui 2016-08-18 7:37 ` [PATCH v3 2/9] mtd: fsl-quadspi: Rename SEQID_QUAD_READ to SEQID_READ Yunhui Cui 2016-08-18 7:37 ` Yunhui Cui 2016-09-14 19:44 ` Han Xu 2016-09-14 19:44 ` Han Xu 2017-01-27 10:35 ` Cyrille Pitchen 2017-01-27 10:35 ` Cyrille Pitchen 2016-08-18 7:37 ` [PATCH v3 3/9] mtd: spi-nor: fsl-quadspi: add fast-read mode support Yunhui Cui 2016-08-18 7:37 ` Yunhui Cui 2016-09-14 19:45 ` Han Xu 2016-09-14 19:45 ` Han Xu 2016-08-18 7:37 ` [PATCH v3 4/9] mtd: spi-nor: fsl-quadspi: extend support for some special requerment Yunhui Cui 2016-08-18 7:37 ` Yunhui Cui 2016-09-14 19:45 ` Han Xu 2016-09-14 19:45 ` Han Xu 2016-08-18 7:38 ` [PATCH v3 5/9] mtd: spi-nor: fsl-quadspi:Support qspi for ls2080a Yunhui Cui 2016-08-18 7:38 ` Yunhui Cui 2016-09-14 19:46 ` Han Xu 2016-09-14 19:46 ` Han Xu 2016-08-18 7:38 ` [PATCH v3 6/9] mtd: spi-nor: Support R/W for S25FS-S family flash Yunhui Cui 2016-08-18 7:38 ` Yunhui Cui 2016-09-14 19:48 ` Han Xu 2016-09-14 19:48 ` Han Xu 2016-09-15 6:50 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-09-15 6:50 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-09-15 6:50 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-16 17:10 ` Han Xu 2016-11-16 17:10 ` Han Xu 2016-11-16 17:10 ` Han Xu 2016-11-17 7:42 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-17 7:42 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-17 7:42 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-17 9:14 ` Yao Yuan 2016-11-17 9:14 ` Yao Yuan 2016-11-17 9:14 ` Yao Yuan 2016-11-17 9:20 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-17 9:20 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-17 9:20 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-18 4:19 ` Yao Yuan 2016-11-18 4:19 ` Yao Yuan 2016-11-18 4:19 ` Yao Yuan 2016-11-18 10:59 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-18 10:59 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-18 10:59 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-21 6:27 ` Yao Yuan 2016-11-21 6:27 ` Yao Yuan 2016-11-21 6:27 ` Yao Yuan 2016-11-21 7:14 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-21 7:14 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-21 7:14 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-21 9:18 ` Yao Yuan 2016-11-21 9:18 ` Yao Yuan 2016-11-21 9:18 ` Yao Yuan 2016-11-18 4:30 ` Han Xu 2016-11-18 4:30 ` Han Xu 2016-11-18 4:30 ` Han Xu 2016-11-21 6:30 ` Yao Yuan 2016-11-21 6:30 ` Yao Yuan 2016-11-21 6:30 ` Yao Yuan 2016-11-16 17:44 ` Jagan Teki 2016-11-16 17:44 ` Jagan Teki 2016-11-16 17:44 ` Jagan Teki 2016-08-18 7:38 ` [PATCH v3 7/9] mtd: fsl-quadspi: Solve Micron Spansion flash command conflict Yunhui Cui 2016-08-18 7:38 ` Yunhui Cui 2016-09-14 19:48 ` Han Xu 2016-09-14 19:48 ` Han Xu 2016-08-18 7:38 ` [PATCH v3 8/9] mtd: fsl-quadspi: disable AHB buffer prefetch Yunhui Cui 2016-08-18 7:38 ` Yunhui Cui 2016-09-14 19:49 ` Han Xu 2016-09-14 19:49 ` Han Xu 2016-08-18 7:38 ` [PATCH v3 9/9] mtd: fsl-quadspi: add multi flash chip R/W on ls2080a Yunhui Cui 2016-08-18 7:38 ` Yunhui Cui 2016-09-14 19:49 ` Han Xu 2016-09-14 19:49 ` Han Xu 2016-09-14 19:44 ` [PATCH v3 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR Han Xu 2016-09-14 19:44 ` Han Xu 2016-09-30 10:04 ` Cyrille Pitchen [this message] 2016-09-30 10:04 ` Cyrille Pitchen 2017-01-27 10:27 ` Cyrille Pitchen 2017-01-27 10:27 ` Cyrille Pitchen
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