From: Han Xu <xhnjupt@gmail.com> To: Yunhui Cui <B56489@freescale.com> Cc: David Woodhouse <dwmw2@infradead.org>, Brian Norris <computersforpeace@gmail.com>, "han.xu@freescale.com" <han.xu@freescale.com>, jagannadh.teki@gmail.com, Yunhui Cui <yunhui.cui@nxp.com>, "linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Yao Yuan <yao.yuan@nxp.com> Subject: Re: [PATCH v3 8/9] mtd: fsl-quadspi: disable AHB buffer prefetch Date: Wed, 14 Sep 2016 14:49:10 -0500 [thread overview] Message-ID: <CA+EcR20qsH0bix7d8Z7pBkuksnMo5-G70TcrX60SC8NYge=+=Q@mail.gmail.com> (raw) In-Reply-To: <1471505884-33996-8-git-send-email-B56489@freescale.com> On Thu, Aug 18, 2016 at 2:38 AM, Yunhui Cui <B56489@freescale.com> wrote: > From: Yunhui Cui <yunhui.cui@nxp.com> > > A-009282: QuadSPI: QuadSPI data pre-fetch can result in incorrect data > Affects: QuadSPI > Description: With AHB buffer prefetch enabled, the QuadSPI may return > incorrect data on the AHB > interface. The buffer pre-fetch is enabled if the fetch size as > configured either in the LUT or in > the BUFxCR register is greater than 8 bytes. > Impact: Only 64 bit read allowed. > Workaround: Keep the read data size to 64 bits (8 Bytes), which disables > the prefetch on the AHB buffer, > and prevents this issue from occurring. > > Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> > --- > drivers/mtd/spi-nor/fsl-quadspi.c | 33 ++++++++++++++++++++++++--------- > 1 file changed, 24 insertions(+), 9 deletions(-) > > diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c > index f9a7d4b..193e81b 100644 > --- a/drivers/mtd/spi-nor/fsl-quadspi.c > +++ b/drivers/mtd/spi-nor/fsl-quadspi.c > @@ -41,6 +41,8 @@ > #define QUADSPI_QUIRK_TKT253890 (1 << 2) > /* Controller cannot wake up from wait mode, TKT245618 */ > #define QUADSPI_QUIRK_TKT245618 (1 << 3) > +/*Errata A-009282: disable the AHB buffer prefetch */ > +#define QUADSPI_QUIRK_ADASZ_8BYTE_LIMIT (1 << 4) > /* QSPI_AMBA_BASE is internally added by SOC design */ > #define QUADSPI_AMBA_BASE_INTERNAL (0x10000) > > @@ -270,7 +272,7 @@ static struct fsl_qspi_devtype_data ls1021a_data = { > .rxfifo = 128, > .txfifo = 64, > .ahb_buf_size = 1024, > - .driver_data = 0, > + .driver_data = QUADSPI_QUIRK_ADASZ_8BYTE_LIMIT, > }; > > static struct fsl_qspi_devtype_data ls2080a_data = { > @@ -278,7 +280,8 @@ static struct fsl_qspi_devtype_data ls2080a_data = { > .rxfifo = 128, > .txfifo = 64, > .ahb_buf_size = 1024, > - .driver_data = QUADSPI_AMBA_BASE_INTERNAL, > + .driver_data = QUADSPI_AMBA_BASE_INTERNAL > + | QUADSPI_QUIRK_ADASZ_8BYTE_LIMIT, > }; > > #define FSL_QSPI_MAX_CHIP 4 > @@ -328,6 +331,11 @@ static inline int has_added_amba_base_internal(struct fsl_qspi *q) > return q->devtype_data->driver_data & QUADSPI_AMBA_BASE_INTERNAL; > } > > +static inline int needs_disable_ahb_prefetch(struct fsl_qspi *q) > +{ > + return q->devtype_data->driver_data & QUADSPI_QUIRK_ADASZ_8BYTE_LIMIT; > +} > + > /* > * R/W functions for big- or little-endian registers: > * The qSPI controller's endian is independent of the CPU core's endian. > @@ -757,14 +765,21 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q) > qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR); > qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR); > qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR); > - /* > - * Set ADATSZ with the maximum AHB buffer size to improve the > - * read performance. > - */ > - qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | > - ((q->devtype_data->ahb_buf_size / 8) > - << QUADSPI_BUF3CR_ADATSZ_SHIFT), > + > + if (needs_disable_ahb_prefetch(q)) { > + qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | > + (1 << QUADSPI_BUF3CR_ADATSZ_SHIFT), > base + QUADSPI_BUF3CR); > + } else { > + /* > + * Set ADATSZ with the maximum AHB buffer size to improve the > + * read performance. > + */ > + qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | > + ((q->devtype_data->ahb_buf_size / 8) > + << QUADSPI_BUF3CR_ADATSZ_SHIFT), > + base + QUADSPI_BUF3CR); > + } > > /* We only use the buffer3 */ > qspi_writel(q, 0, base + QUADSPI_BUF0IND); > -- > 2.1.0.27.g96db324 > > Acked-by: Han xu <han.xu@nxp.com> > ______________________________________________________ > Linux MTD discussion mailing list > http://lists.infradead.org/mailman/listinfo/linux-mtd/ -- Sincerely, Han XU
WARNING: multiple messages have this Message-ID (diff)
From: xhnjupt@gmail.com (Han Xu) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 8/9] mtd: fsl-quadspi: disable AHB buffer prefetch Date: Wed, 14 Sep 2016 14:49:10 -0500 [thread overview] Message-ID: <CA+EcR20qsH0bix7d8Z7pBkuksnMo5-G70TcrX60SC8NYge=+=Q@mail.gmail.com> (raw) In-Reply-To: <1471505884-33996-8-git-send-email-B56489@freescale.com> On Thu, Aug 18, 2016 at 2:38 AM, Yunhui Cui <B56489@freescale.com> wrote: > From: Yunhui Cui <yunhui.cui@nxp.com> > > A-009282: QuadSPI: QuadSPI data pre-fetch can result in incorrect data > Affects: QuadSPI > Description: With AHB buffer prefetch enabled, the QuadSPI may return > incorrect data on the AHB > interface. The buffer pre-fetch is enabled if the fetch size as > configured either in the LUT or in > the BUFxCR register is greater than 8 bytes. > Impact: Only 64 bit read allowed. > Workaround: Keep the read data size to 64 bits (8 Bytes), which disables > the prefetch on the AHB buffer, > and prevents this issue from occurring. > > Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> > --- > drivers/mtd/spi-nor/fsl-quadspi.c | 33 ++++++++++++++++++++++++--------- > 1 file changed, 24 insertions(+), 9 deletions(-) > > diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c > index f9a7d4b..193e81b 100644 > --- a/drivers/mtd/spi-nor/fsl-quadspi.c > +++ b/drivers/mtd/spi-nor/fsl-quadspi.c > @@ -41,6 +41,8 @@ > #define QUADSPI_QUIRK_TKT253890 (1 << 2) > /* Controller cannot wake up from wait mode, TKT245618 */ > #define QUADSPI_QUIRK_TKT245618 (1 << 3) > +/*Errata A-009282: disable the AHB buffer prefetch */ > +#define QUADSPI_QUIRK_ADASZ_8BYTE_LIMIT (1 << 4) > /* QSPI_AMBA_BASE is internally added by SOC design */ > #define QUADSPI_AMBA_BASE_INTERNAL (0x10000) > > @@ -270,7 +272,7 @@ static struct fsl_qspi_devtype_data ls1021a_data = { > .rxfifo = 128, > .txfifo = 64, > .ahb_buf_size = 1024, > - .driver_data = 0, > + .driver_data = QUADSPI_QUIRK_ADASZ_8BYTE_LIMIT, > }; > > static struct fsl_qspi_devtype_data ls2080a_data = { > @@ -278,7 +280,8 @@ static struct fsl_qspi_devtype_data ls2080a_data = { > .rxfifo = 128, > .txfifo = 64, > .ahb_buf_size = 1024, > - .driver_data = QUADSPI_AMBA_BASE_INTERNAL, > + .driver_data = QUADSPI_AMBA_BASE_INTERNAL > + | QUADSPI_QUIRK_ADASZ_8BYTE_LIMIT, > }; > > #define FSL_QSPI_MAX_CHIP 4 > @@ -328,6 +331,11 @@ static inline int has_added_amba_base_internal(struct fsl_qspi *q) > return q->devtype_data->driver_data & QUADSPI_AMBA_BASE_INTERNAL; > } > > +static inline int needs_disable_ahb_prefetch(struct fsl_qspi *q) > +{ > + return q->devtype_data->driver_data & QUADSPI_QUIRK_ADASZ_8BYTE_LIMIT; > +} > + > /* > * R/W functions for big- or little-endian registers: > * The qSPI controller's endian is independent of the CPU core's endian. > @@ -757,14 +765,21 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q) > qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR); > qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR); > qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR); > - /* > - * Set ADATSZ with the maximum AHB buffer size to improve the > - * read performance. > - */ > - qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | > - ((q->devtype_data->ahb_buf_size / 8) > - << QUADSPI_BUF3CR_ADATSZ_SHIFT), > + > + if (needs_disable_ahb_prefetch(q)) { > + qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | > + (1 << QUADSPI_BUF3CR_ADATSZ_SHIFT), > base + QUADSPI_BUF3CR); > + } else { > + /* > + * Set ADATSZ with the maximum AHB buffer size to improve the > + * read performance. > + */ > + qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | > + ((q->devtype_data->ahb_buf_size / 8) > + << QUADSPI_BUF3CR_ADATSZ_SHIFT), > + base + QUADSPI_BUF3CR); > + } > > /* We only use the buffer3 */ > qspi_writel(q, 0, base + QUADSPI_BUF0IND); > -- > 2.1.0.27.g96db324 > > Acked-by: Han xu <han.xu@nxp.com> > ______________________________________________________ > Linux MTD discussion mailing list > http://lists.infradead.org/mailman/listinfo/linux-mtd/ -- Sincerely, Han XU
next prev parent reply other threads:[~2016-09-14 19:49 UTC|newest] Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-08-18 7:37 [PATCH v3 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR Yunhui Cui 2016-08-18 7:37 ` Yunhui Cui 2016-08-18 7:37 ` [PATCH v3 2/9] mtd: fsl-quadspi: Rename SEQID_QUAD_READ to SEQID_READ Yunhui Cui 2016-08-18 7:37 ` Yunhui Cui 2016-09-14 19:44 ` Han Xu 2016-09-14 19:44 ` Han Xu 2017-01-27 10:35 ` Cyrille Pitchen 2017-01-27 10:35 ` Cyrille Pitchen 2016-08-18 7:37 ` [PATCH v3 3/9] mtd: spi-nor: fsl-quadspi: add fast-read mode support Yunhui Cui 2016-08-18 7:37 ` Yunhui Cui 2016-09-14 19:45 ` Han Xu 2016-09-14 19:45 ` Han Xu 2016-08-18 7:37 ` [PATCH v3 4/9] mtd: spi-nor: fsl-quadspi: extend support for some special requerment Yunhui Cui 2016-08-18 7:37 ` Yunhui Cui 2016-09-14 19:45 ` Han Xu 2016-09-14 19:45 ` Han Xu 2016-08-18 7:38 ` [PATCH v3 5/9] mtd: spi-nor: fsl-quadspi:Support qspi for ls2080a Yunhui Cui 2016-08-18 7:38 ` Yunhui Cui 2016-09-14 19:46 ` Han Xu 2016-09-14 19:46 ` Han Xu 2016-08-18 7:38 ` [PATCH v3 6/9] mtd: spi-nor: Support R/W for S25FS-S family flash Yunhui Cui 2016-08-18 7:38 ` Yunhui Cui 2016-09-14 19:48 ` Han Xu 2016-09-14 19:48 ` Han Xu 2016-09-15 6:50 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-09-15 6:50 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-09-15 6:50 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-16 17:10 ` Han Xu 2016-11-16 17:10 ` Han Xu 2016-11-16 17:10 ` Han Xu 2016-11-17 7:42 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-17 7:42 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-17 7:42 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-17 9:14 ` Yao Yuan 2016-11-17 9:14 ` Yao Yuan 2016-11-17 9:14 ` Yao Yuan 2016-11-17 9:20 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-17 9:20 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-17 9:20 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-18 4:19 ` Yao Yuan 2016-11-18 4:19 ` Yao Yuan 2016-11-18 4:19 ` Yao Yuan 2016-11-18 10:59 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-18 10:59 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-18 10:59 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-21 6:27 ` Yao Yuan 2016-11-21 6:27 ` Yao Yuan 2016-11-21 6:27 ` Yao Yuan 2016-11-21 7:14 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-21 7:14 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-21 7:14 ` Krzeminski, Marcin (Nokia - PL/Wroclaw) 2016-11-21 9:18 ` Yao Yuan 2016-11-21 9:18 ` Yao Yuan 2016-11-21 9:18 ` Yao Yuan 2016-11-18 4:30 ` Han Xu 2016-11-18 4:30 ` Han Xu 2016-11-18 4:30 ` Han Xu 2016-11-21 6:30 ` Yao Yuan 2016-11-21 6:30 ` Yao Yuan 2016-11-21 6:30 ` Yao Yuan 2016-11-16 17:44 ` Jagan Teki 2016-11-16 17:44 ` Jagan Teki 2016-11-16 17:44 ` Jagan Teki 2016-08-18 7:38 ` [PATCH v3 7/9] mtd: fsl-quadspi: Solve Micron Spansion flash command conflict Yunhui Cui 2016-08-18 7:38 ` Yunhui Cui 2016-09-14 19:48 ` Han Xu 2016-09-14 19:48 ` Han Xu 2016-08-18 7:38 ` [PATCH v3 8/9] mtd: fsl-quadspi: disable AHB buffer prefetch Yunhui Cui 2016-08-18 7:38 ` Yunhui Cui 2016-09-14 19:49 ` Han Xu [this message] 2016-09-14 19:49 ` Han Xu 2016-08-18 7:38 ` [PATCH v3 9/9] mtd: fsl-quadspi: add multi flash chip R/W on ls2080a Yunhui Cui 2016-08-18 7:38 ` Yunhui Cui 2016-09-14 19:49 ` Han Xu 2016-09-14 19:49 ` Han Xu 2016-09-14 19:44 ` [PATCH v3 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR Han Xu 2016-09-14 19:44 ` Han Xu 2016-09-30 10:04 ` Cyrille Pitchen 2016-09-30 10:04 ` Cyrille Pitchen 2017-01-27 10:27 ` Cyrille Pitchen 2017-01-27 10:27 ` Cyrille Pitchen
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