From: Julien Thierry <julien.thierry@arm.com> To: "liwei (GF)" <liwei391@huawei.com>, linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org, joel@joelfernandes.org, marc.zyngier@arm.com, christoffer.dall@arm.com, james.morse@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, mark.rutland@arm.com, Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net> Subject: Re: [PATCH v9 22/26] irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI Date: Mon, 28 Jan 2019 08:57:43 +0000 [thread overview] Message-ID: <315b0845-441d-4e02-d0a8-03769b63caee@arm.com> (raw) In-Reply-To: <8c0efe3f-1fc7-cbc7-0086-bd9c379cf0fc@huawei.com> Hi, On 26/01/2019 10:19, liwei (GF) wrote: > > > On 2019/1/21 23:33, Julien Thierry wrote: >> Implement NMI callbacks for GICv3 irqchip. Install NMI safe handlers >> when setting up interrupt line as NMI. >> >> Only SPIs and PPIs are allowed to be set up as NMI. >> >> Signed-off-by: Julien Thierry <julien.thierry@arm.com> >> Cc: Thomas Gleixner <tglx@linutronix.de> >> Cc: Jason Cooper <jason@lakedaemon.net> >> Cc: Marc Zyngier <marc.zyngier@arm.com> >> --- >> drivers/irqchip/irq-gic-v3.c | 84 ++++++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 84 insertions(+) >> >> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c >> index 4df1e94..447d8ab 100644 >> --- a/drivers/irqchip/irq-gic-v3.c >> +++ b/drivers/irqchip/irq-gic-v3.c > (snip) >> >> +static int gic_irq_nmi_setup(struct irq_data *d) >> +{ >> + struct irq_desc *desc = irq_to_desc(d->irq); >> + >> + if (!gic_supports_nmi()) >> + return -EINVAL; >> + >> + if (gic_peek_irq(d, GICD_ISENABLER)) { >> + pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); >> + return -EINVAL; >> + } >> + >> + /* >> + * A secondary irq_chip should be in charge of LPI request, >> + * it should not be possible to get there >> + */ >> + if (WARN_ON(gic_irq(d) >= 8192)) >> + return -EINVAL; >> + >> + /* desc lock should already be held */ >> + if (gic_irq(d) < 32) { >> + /* Setting up PPI as NMI, only switch handler for first NMI */ >> + if (!refcount_inc_not_zero(&ppi_nmi_refs[gic_irq(d) - 16])) { >> + refcount_set(&ppi_nmi_refs[gic_irq(d) - 16], 1); >> + desc->handle_irq = handle_percpu_devid_fasteoi_nmi; >> + } >> + } else { >> + desc->handle_irq = handle_fasteoi_nmi; >> + } >> + >> + gic_set_irq_prio(gic_irq(d), gic_dist_base(d), GICD_INT_NMI_PRI); >> + >> + return 0; >> +} >> + >> +static void gic_irq_nmi_teardown(struct irq_data *d) >> +{ >> + struct irq_desc *desc = irq_to_desc(d->irq); >> + >> + if (WARN_ON(!gic_supports_nmi())) >> + return; >> + >> + if (gic_peek_irq(d, GICD_ISENABLER)) { >> + pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); >> + return; >> + } >> + >> + /* >> + * A secondary irq_chip should be in charge of LPI request, >> + * it should not be possible to get there >> + */ >> + if (WARN_ON(gic_irq(d) >= 8192)) >> + return; >> + >> + /* desc lock should already be held */ >> + if (gic_irq(d) < 32) { >> + /* Tearing down NMI, only switch handler for last NMI */ >> + if (refcount_dec_and_test(&ppi_nmi_refs[gic_irq(d) - 16])) >> + desc->handle_irq = handle_percpu_devid_irq; >> + } else { >> + desc->handle_irq = handle_fasteoi_irq; >> + } >> + >> + gic_set_irq_prio(gic_irq(d), gic_dist_base(d), GICD_INT_DEF_PRI); >> +} >> + > > Hello Julien, > I am afraid the setting of priority is not correct here. If the irq is in redistributor(gic_irq(d) < 32), > we should set the priority on each cpu, while we just set the priority on the current cpu here. As Marc stated, to work with PPIs, the core IRQ API provides a set of *_percpu_irq functions (request, enable, disable...). The current idea is that the driver is in charge of calling ready_percpu_nmi() before enabling on the correct CPU, in a similar manner that the driver is in charge of calling enable_percpu_irq() and disable_percpu_irq() on the correct CPU. > static inline void __iomem *gic_dist_base(struct irq_data *d) > { > if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ > return gic_data_rdist_sgi_base(); > > if (d->hwirq <= 1023) /* SPI -> dist_base */ > return gic_data.dist_base; > > return NULL; > } > > I tried to add a smp_call_function here, but the kernel reported a warning as we have disabled irq > when calling raw_spin_lock_irqsave in request_nmi or ready_percpu_nmi. > [ 2.137262] Call trace: > [ 2.137265] smp_call_function_many+0xf8/0x3a0 > [ 2.137267] smp_call_function+0x40/0x58 > [ 2.137271] gic_irq_nmi_setup+0xe8/0x118 > [ 2.137275] ready_percpu_nmi+0x6c/0xf0> [ 2.137279] armpmu_request_irq+0x228/0x250 Your issue lies here, if your PMU IRQ is a PPI, you shouldn't be calling ready_percpu_nmi() at the time you request but probably somewhere like arm_perf_starting_cpu(). And you wouldn't need the smp_call to set the priority. Hope this helps. > [ 2.137281] arm_pmu_acpi_init+0x150/0x2f0 > [ 2.137284] do_one_initcall+0x54/0x218 > [ 2.137289] kernel_init_freeable+0x230/0x354 > [ 2.137293] kernel_init+0x18/0x118 > [ 2.137295] ret_from_fork+0x10/0x18 > Thanks, -- Julien Thierry
WARNING: multiple messages have this Message-ID (diff)
From: Julien Thierry <julien.thierry@arm.com> To: "liwei (GF)" <liwei391@huawei.com>, linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com, daniel.thompson@linaro.org, Jason Cooper <jason@lakedaemon.net>, marc.zyngier@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, christoffer.dall@arm.com, james.morse@arm.com, joel@joelfernandes.org, Thomas Gleixner <tglx@linutronix.de> Subject: Re: [PATCH v9 22/26] irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI Date: Mon, 28 Jan 2019 08:57:43 +0000 [thread overview] Message-ID: <315b0845-441d-4e02-d0a8-03769b63caee@arm.com> (raw) In-Reply-To: <8c0efe3f-1fc7-cbc7-0086-bd9c379cf0fc@huawei.com> Hi, On 26/01/2019 10:19, liwei (GF) wrote: > > > On 2019/1/21 23:33, Julien Thierry wrote: >> Implement NMI callbacks for GICv3 irqchip. Install NMI safe handlers >> when setting up interrupt line as NMI. >> >> Only SPIs and PPIs are allowed to be set up as NMI. >> >> Signed-off-by: Julien Thierry <julien.thierry@arm.com> >> Cc: Thomas Gleixner <tglx@linutronix.de> >> Cc: Jason Cooper <jason@lakedaemon.net> >> Cc: Marc Zyngier <marc.zyngier@arm.com> >> --- >> drivers/irqchip/irq-gic-v3.c | 84 ++++++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 84 insertions(+) >> >> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c >> index 4df1e94..447d8ab 100644 >> --- a/drivers/irqchip/irq-gic-v3.c >> +++ b/drivers/irqchip/irq-gic-v3.c > (snip) >> >> +static int gic_irq_nmi_setup(struct irq_data *d) >> +{ >> + struct irq_desc *desc = irq_to_desc(d->irq); >> + >> + if (!gic_supports_nmi()) >> + return -EINVAL; >> + >> + if (gic_peek_irq(d, GICD_ISENABLER)) { >> + pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); >> + return -EINVAL; >> + } >> + >> + /* >> + * A secondary irq_chip should be in charge of LPI request, >> + * it should not be possible to get there >> + */ >> + if (WARN_ON(gic_irq(d) >= 8192)) >> + return -EINVAL; >> + >> + /* desc lock should already be held */ >> + if (gic_irq(d) < 32) { >> + /* Setting up PPI as NMI, only switch handler for first NMI */ >> + if (!refcount_inc_not_zero(&ppi_nmi_refs[gic_irq(d) - 16])) { >> + refcount_set(&ppi_nmi_refs[gic_irq(d) - 16], 1); >> + desc->handle_irq = handle_percpu_devid_fasteoi_nmi; >> + } >> + } else { >> + desc->handle_irq = handle_fasteoi_nmi; >> + } >> + >> + gic_set_irq_prio(gic_irq(d), gic_dist_base(d), GICD_INT_NMI_PRI); >> + >> + return 0; >> +} >> + >> +static void gic_irq_nmi_teardown(struct irq_data *d) >> +{ >> + struct irq_desc *desc = irq_to_desc(d->irq); >> + >> + if (WARN_ON(!gic_supports_nmi())) >> + return; >> + >> + if (gic_peek_irq(d, GICD_ISENABLER)) { >> + pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); >> + return; >> + } >> + >> + /* >> + * A secondary irq_chip should be in charge of LPI request, >> + * it should not be possible to get there >> + */ >> + if (WARN_ON(gic_irq(d) >= 8192)) >> + return; >> + >> + /* desc lock should already be held */ >> + if (gic_irq(d) < 32) { >> + /* Tearing down NMI, only switch handler for last NMI */ >> + if (refcount_dec_and_test(&ppi_nmi_refs[gic_irq(d) - 16])) >> + desc->handle_irq = handle_percpu_devid_irq; >> + } else { >> + desc->handle_irq = handle_fasteoi_irq; >> + } >> + >> + gic_set_irq_prio(gic_irq(d), gic_dist_base(d), GICD_INT_DEF_PRI); >> +} >> + > > Hello Julien, > I am afraid the setting of priority is not correct here. If the irq is in redistributor(gic_irq(d) < 32), > we should set the priority on each cpu, while we just set the priority on the current cpu here. As Marc stated, to work with PPIs, the core IRQ API provides a set of *_percpu_irq functions (request, enable, disable...). The current idea is that the driver is in charge of calling ready_percpu_nmi() before enabling on the correct CPU, in a similar manner that the driver is in charge of calling enable_percpu_irq() and disable_percpu_irq() on the correct CPU. > static inline void __iomem *gic_dist_base(struct irq_data *d) > { > if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ > return gic_data_rdist_sgi_base(); > > if (d->hwirq <= 1023) /* SPI -> dist_base */ > return gic_data.dist_base; > > return NULL; > } > > I tried to add a smp_call_function here, but the kernel reported a warning as we have disabled irq > when calling raw_spin_lock_irqsave in request_nmi or ready_percpu_nmi. > [ 2.137262] Call trace: > [ 2.137265] smp_call_function_many+0xf8/0x3a0 > [ 2.137267] smp_call_function+0x40/0x58 > [ 2.137271] gic_irq_nmi_setup+0xe8/0x118 > [ 2.137275] ready_percpu_nmi+0x6c/0xf0> [ 2.137279] armpmu_request_irq+0x228/0x250 Your issue lies here, if your PMU IRQ is a PPI, you shouldn't be calling ready_percpu_nmi() at the time you request but probably somewhere like arm_perf_starting_cpu(). And you wouldn't need the smp_call to set the priority. Hope this helps. > [ 2.137281] arm_pmu_acpi_init+0x150/0x2f0 > [ 2.137284] do_one_initcall+0x54/0x218 > [ 2.137289] kernel_init_freeable+0x230/0x354 > [ 2.137293] kernel_init+0x18/0x118 > [ 2.137295] ret_from_fork+0x10/0x18 > Thanks, -- Julien Thierry _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-01-28 8:57 UTC|newest] Thread overview: 166+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-01-21 15:33 [PATCH v9 00/26] arm64: provide pseudo NMI with GICv3 Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-21 15:33 ` [PATCH v9 01/26] arm64: Fix HCR.TGE status for NMI contexts Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-23 22:57 ` Sasha Levin 2019-01-23 22:57 ` Sasha Levin 2019-01-28 11:48 ` James Morse 2019-01-28 11:48 ` James Morse 2019-01-28 15:42 ` Julien Thierry 2019-01-28 15:42 ` Julien Thierry 2019-01-31 8:19 ` Christoffer Dall 2019-01-31 8:19 ` Christoffer Dall 2019-01-31 8:56 ` Julien Thierry 2019-01-31 8:56 ` Julien Thierry 2019-01-31 9:27 ` Christoffer Dall 2019-01-31 9:27 ` Christoffer Dall 2019-01-31 9:40 ` Julien Thierry 2019-01-31 9:40 ` Julien Thierry 2019-01-31 9:48 ` Christoffer Dall 2019-01-31 9:48 ` Christoffer Dall 2019-01-31 9:53 ` Marc Zyngier 2019-01-31 9:53 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 02/26] arm64: Remove unused daif related functions/macros Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 9:21 ` Marc Zyngier 2019-01-28 9:21 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 03/26] arm64: cpufeature: Set SYSREG_GIC_CPUIF as a boot system feature Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 9:22 ` Marc Zyngier 2019-01-28 9:22 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 04/26] arm64: cpufeature: Add cpufeature for IRQ priority masking Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 9:24 ` Marc Zyngier 2019-01-28 9:24 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 05/26] arm/arm64: gic-v3: Add PMR and RPR accessors Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 9:25 ` Marc Zyngier 2019-01-28 9:25 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 06/26] irqchip/gic-v3: Switch to PMR masking before calling IRQ handler Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 9:30 ` Marc Zyngier 2019-01-28 9:30 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 07/26] arm64: ptrace: Provide definitions for PMR values Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 9:37 ` Marc Zyngier 2019-01-28 9:37 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 08/26] arm64: Make PMR part of task context Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 9:42 ` Marc Zyngier 2019-01-28 9:42 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 09/26] arm64: Unmask PMR before going idle Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-22 15:23 ` Catalin Marinas 2019-01-22 15:23 ` Catalin Marinas 2019-01-22 20:18 ` Ard Biesheuvel 2019-01-22 20:18 ` Ard Biesheuvel 2019-01-23 8:56 ` Julien Thierry 2019-01-23 8:56 ` Julien Thierry 2019-01-23 9:38 ` Ard Biesheuvel 2019-01-23 9:38 ` Ard Biesheuvel 2019-01-28 9:44 ` Marc Zyngier 2019-01-28 9:44 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 10/26] arm64: kvm: Unmask PMR before entering guest Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 9:58 ` Marc Zyngier 2019-01-28 9:58 ` Marc Zyngier 2019-01-28 9:58 ` Marc Zyngier 2019-01-30 12:07 ` Christoffer Dall 2019-01-30 12:07 ` Christoffer Dall 2019-01-30 14:58 ` Julien Thierry 2019-01-30 14:58 ` Julien Thierry 2019-01-21 15:33 ` [PATCH v9 11/26] efi: Let architectures decide the flags that should be saved/restored Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-21 15:42 ` Ard Biesheuvel 2019-01-21 15:42 ` Ard Biesheuvel 2019-01-23 9:04 ` Julien Thierry 2019-01-23 9:04 ` Julien Thierry 2019-01-28 10:00 ` Marc Zyngier 2019-01-28 10:00 ` Marc Zyngier 2019-01-28 10:00 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 12/26] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-21 15:45 ` Ard Biesheuvel 2019-01-21 15:45 ` Ard Biesheuvel 2019-01-21 18:05 ` Julien Thierry 2019-01-21 18:05 ` Julien Thierry 2019-01-22 15:21 ` Catalin Marinas 2019-01-22 15:21 ` Catalin Marinas 2019-01-23 10:44 ` Julien Thierry 2019-01-23 10:44 ` Julien Thierry 2019-01-30 11:52 ` Julien Thierry 2019-01-30 11:52 ` Julien Thierry 2019-01-21 15:33 ` [PATCH v9 13/26] arm64: daifflags: Include PMR in daifflags restore operations Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 10:37 ` Marc Zyngier 2019-01-28 10:37 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 14/26] arm64: alternative: Allow alternative status checking per cpufeature Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 11:00 ` Marc Zyngier 2019-01-28 11:00 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 15/26] arm64: alternative: Apply alternatives early in boot process Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 11:17 ` Marc Zyngier 2019-01-28 11:17 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 16/26] irqchip/gic-v3: Factor group0 detection into functions Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 11:19 ` Marc Zyngier 2019-01-28 11:19 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 17/26] arm64: Switch to PMR masking when starting CPUs Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 11:21 ` Marc Zyngier 2019-01-28 11:21 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 18/26] arm64: gic-v3: Implement arch support for priority masking Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 11:23 ` Marc Zyngier 2019-01-28 11:23 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 19/26] irqchip/gic-v3: Detect if GIC can support pseudo-NMIs Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 11:39 ` Marc Zyngier 2019-01-28 11:39 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 20/26] irqchip/gic-v3: Handle pseudo-NMIs Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 11:59 ` Marc Zyngier 2019-01-28 11:59 ` Marc Zyngier 2019-01-29 11:33 ` Julien Thierry 2019-01-29 11:33 ` Julien Thierry 2019-01-29 12:31 ` Marc Zyngier 2019-01-29 12:31 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 21/26] irqchip/gic: Add functions to access irq priorities Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 12:04 ` Marc Zyngier 2019-01-28 12:04 ` Marc Zyngier 2019-01-29 11:36 ` Julien Thierry 2019-01-29 11:36 ` Julien Thierry 2019-01-21 15:33 ` [PATCH v9 22/26] irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-26 10:19 ` liwei (GF) 2019-01-26 10:19 ` liwei (GF) 2019-01-26 10:41 ` Marc Zyngier 2019-01-26 10:41 ` Marc Zyngier 2019-01-28 8:57 ` Julien Thierry [this message] 2019-01-28 8:57 ` Julien Thierry 2019-01-28 13:59 ` liwei (GF) 2019-01-28 13:59 ` liwei (GF) 2019-01-28 14:49 ` Julien Thierry 2019-01-28 14:49 ` Julien Thierry 2019-01-28 12:08 ` Marc Zyngier 2019-01-28 12:08 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 23/26] arm64: Handle serror in NMI context Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 12:26 ` Marc Zyngier 2019-01-28 12:26 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 24/26] arm64: Skip preemption when exiting an NMI Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 12:34 ` Marc Zyngier 2019-01-28 12:34 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 25/26] arm64: Skip irqflags tracing for NMI in IRQs disabled context Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 12:40 ` Marc Zyngier 2019-01-28 12:40 ` Marc Zyngier 2019-01-21 15:33 ` [PATCH v9 26/26] arm64: Enable the support of pseudo-NMIs Julien Thierry 2019-01-21 15:33 ` Julien Thierry 2019-01-28 12:47 ` Marc Zyngier 2019-01-28 12:47 ` Marc Zyngier 2019-01-30 13:46 ` Julien Thierry 2019-01-30 13:46 ` Julien Thierry
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