* [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup
@ 2021-12-01 15:25 Ville Syrjala
2021-12-01 15:25 ` [Intel-gfx] [PATCH 01/14] drm/i915: Get rid of the 64bit PLANE_CC_VAL mmio Ville Syrjala
` (17 more replies)
0 siblings, 18 replies; 48+ messages in thread
From: Ville Syrjala @ 2021-12-01 15:25 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Bunch of cleanup around plane registers, and a bit of
reshuffling in the skl+ universal plane code.
Ville Syrjälä (14):
drm/i915: Get rid of the 64bit PLANE_CC_VAL mmio
drm/i915: Rename plane YUV order bits
drm/i915: Get rid of the "sizes are 0 based" stuff
drm/i915: Sipmplify PLANE_STRIDE masking
drm/i915: Rename PLANE_CUS_CTL Y plane bits
drm/i915: Use REG_BIT() & co. for universal plane bits
drm/i915: Clean up pre-skl primary plane registers
drm/i915: Clean up ivb+ sprite plane registers
drm/i915: Clean up vlv/chv sprite plane registers
drm/i915: Clean up g4x+ sprite plane registers
drm/i915: Clean up cursor registers
drm/i915: Extract skl_plane_aux_dist()
drm/i915: Declutter color key register stuff
drm/i915: Nuke pointless middle men for skl+ plane programming
drivers/gpu/drm/i915/display/i9xx_plane.c | 99 ++-
drivers/gpu/drm/i915/display/intel_cursor.c | 25 +-
drivers/gpu/drm/i915/display/intel_display.c | 25 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 57 +-
.../drm/i915/display/skl_universal_plane.c | 191 +++---
drivers/gpu/drm/i915/gvt/reg.h | 1 -
drivers/gpu/drm/i915/i915_reg.h | 646 ++++++++++--------
drivers/gpu/drm/i915/intel_pm.c | 14 +-
8 files changed, 581 insertions(+), 477 deletions(-)
--
2.32.0
^ permalink raw reply [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 01/14] drm/i915: Get rid of the 64bit PLANE_CC_VAL mmio
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
@ 2021-12-01 15:25 ` Ville Syrjala
2021-12-01 17:13 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 02/14] drm/i915: Rename plane YUV order bits Ville Syrjala
` (16 subsequent siblings)
17 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2021-12-01 15:25 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's just stick to 32bit mmio accesses so we can get rid
of the bare "uncore" reg access in display code. The register
are defined as 32bit in the spec anyway.
We could define a 64bit "de" variant I suppose, but doesn't
really make much sense just for this one case, and when we
start to use the DSB for this stuff we'd also need another
64bit variant for that. Just easier to do 32bit always.
While at it we can reorder stuff a bit so that we write the
registers in order of increasing offset (more or less).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 11 +++++++----
drivers/gpu/drm/i915/i915_reg.h | 12 ++++++------
2 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 28890876bdeb..845b99844ec6 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1047,6 +1047,13 @@ skl_program_plane_noarm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
(src_h << 16) | src_w);
+ if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
+ intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
+ lower_32_bits(plane_state->ccval));
+ intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 1),
+ upper_32_bits(plane_state->ccval));
+ }
+
if (icl_is_hdr_plane(dev_priv, plane_id))
intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
plane_state->cus_ctl);
@@ -1054,10 +1061,6 @@ skl_program_plane_noarm(struct intel_plane *plane,
if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
icl_program_input_csc(plane, crtc_state, plane_state);
- if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier))
- intel_uncore_write64_fw(&dev_priv->uncore,
- PLANE_CC_VAL(pipe, plane_id), plane_state->ccval);
-
skl_write_plane_wm(plane, crtc_state);
intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3450818802c2..3c0471f20e53 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7363,12 +7363,12 @@ enum {
#define _PLANE_NV12_BUF_CFG_1_A 0x70278
#define _PLANE_NV12_BUF_CFG_2_A 0x70378
-#define _PLANE_CC_VAL_1_B 0x711b4
-#define _PLANE_CC_VAL_2_B 0x712b4
-#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
-#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
-#define PLANE_CC_VAL(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
+#define _PLANE_CC_VAL_1_B 0x711b4
+#define _PLANE_CC_VAL_2_B 0x712b4
+#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
+#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
+#define PLANE_CC_VAL(pipe, plane, dw) \
+ _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
/* Input CSC Register Definitions */
#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
--
2.32.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 02/14] drm/i915: Rename plane YUV order bits
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
2021-12-01 15:25 ` [Intel-gfx] [PATCH 01/14] drm/i915: Get rid of the 64bit PLANE_CC_VAL mmio Ville Syrjala
@ 2021-12-01 15:25 ` Ville Syrjala
2021-12-01 17:14 ` Souza, Jose
2021-12-06 13:13 ` kernel test robot
2021-12-01 15:25 ` [Intel-gfx] [PATCH 03/14] drm/i915: Get rid of the "sizes are 0 based" stuff Ville Syrjala
` (15 subsequent siblings)
17 siblings, 2 replies; 48+ messages in thread
From: Ville Syrjala @ 2021-12-01 15:25 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename the YUV byte order bits to be a bit more consistent.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 8 ++++----
drivers/gpu/drm/i915/i915_reg.h | 14 +++++++-------
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 845b99844ec6..9ff24a0e79b4 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -672,13 +672,13 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
case DRM_FORMAT_XYUV8888:
return PLANE_CTL_FORMAT_XYUV;
case DRM_FORMAT_YUYV:
- return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
+ return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YUYV;
case DRM_FORMAT_YVYU:
- return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
+ return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YVYU;
case DRM_FORMAT_UYVY:
- return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
+ return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_UYVY;
case DRM_FORMAT_VYUY:
- return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+ return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_VYUY;
case DRM_FORMAT_NV12:
return PLANE_CTL_FORMAT_NV12;
case DRM_FORMAT_P010:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3c0471f20e53..02d8db03c0bf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6966,7 +6966,7 @@ enum {
#define DVS_SOURCE_KEY (1 << 22)
#define DVS_RGB_ORDER_XBGR (1 << 20)
#define DVS_YUV_FORMAT_BT709 (1 << 18)
-#define DVS_YUV_BYTE_ORDER_MASK (3 << 16)
+#define DVS_YUV_ORDER_MASK (3 << 16)
#define DVS_YUV_ORDER_YUYV (0 << 16)
#define DVS_YUV_ORDER_UYVY (1 << 16)
#define DVS_YUV_ORDER_YVYU (2 << 16)
@@ -7045,7 +7045,7 @@ enum {
#define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and 161616 */
#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)
#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */
-#define SPRITE_YUV_BYTE_ORDER_MASK (3 << 16)
+#define SPRITE_YUV_ORDER_MASK (3 << 16)
#define SPRITE_YUV_ORDER_YUYV (0 << 16)
#define SPRITE_YUV_ORDER_UYVY (1 << 16)
#define SPRITE_YUV_ORDER_YVYU (2 << 16)
@@ -7130,7 +7130,7 @@ enum {
#define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
#define SP_SOURCE_KEY (1 << 22)
#define SP_YUV_FORMAT_BT709 (1 << 18)
-#define SP_YUV_BYTE_ORDER_MASK (3 << 16)
+#define SP_YUV_ORDER_MASK (3 << 16)
#define SP_YUV_ORDER_YUYV (0 << 16)
#define SP_YUV_ORDER_UYVY (1 << 16)
#define SP_YUV_ORDER_YVYU (2 << 16)
@@ -7271,10 +7271,10 @@ enum {
#define PLANE_CTL_YUV420_Y_PLANE (1 << 19)
#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
-#define PLANE_CTL_YUV422_YUYV (0 << 16)
-#define PLANE_CTL_YUV422_UYVY (1 << 16)
-#define PLANE_CTL_YUV422_YVYU (2 << 16)
-#define PLANE_CTL_YUV422_VYUY (3 << 16)
+#define PLANE_CTL_YUV422_ORDER_YUYV (0 << 16)
+#define PLANE_CTL_YUV422_ORDER_UYVY (1 << 16)
+#define PLANE_CTL_YUV422_ORDER_YVYU (2 << 16)
+#define PLANE_CTL_YUV422_ORDER_VYUY (3 << 16)
#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
#define PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13) /* TGL+ */
--
2.32.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 03/14] drm/i915: Get rid of the "sizes are 0 based" stuff
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
2021-12-01 15:25 ` [Intel-gfx] [PATCH 01/14] drm/i915: Get rid of the 64bit PLANE_CC_VAL mmio Ville Syrjala
2021-12-01 15:25 ` [Intel-gfx] [PATCH 02/14] drm/i915: Rename plane YUV order bits Ville Syrjala
@ 2021-12-01 15:25 ` Ville Syrjala
2021-12-01 17:18 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 04/14] drm/i915: Sipmplify PLANE_STRIDE masking Ville Syrjala
` (14 subsequent siblings)
17 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2021-12-01 15:25 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Replace the "sizes are 0 based" stuff with just straight
up -1 where needed. Less confusing all around.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 26 ++++---------------
.../drm/i915/display/skl_universal_plane.c | 6 +----
2 files changed, 6 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 1b99a9501a45..2067a7bca4a8 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -431,10 +431,6 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
unsigned long irqflags;
- /* Sizes are 0 based */
- crtc_w--;
- crtc_h--;
-
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
@@ -442,7 +438,7 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),
(crtc_y << 16) | crtc_x);
intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
- (crtc_h << 16) | crtc_w);
+ ((crtc_h - 1) << 16) | (crtc_w - 1));
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
@@ -866,21 +862,15 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
u32 sprscale = 0;
unsigned long irqflags;
- /* Sizes are 0 based */
- src_w--;
- src_h--;
- crtc_w--;
- crtc_h--;
-
if (crtc_w != src_w || crtc_h != src_h)
- sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
+ sprscale = SPRITE_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
plane_state->view.color_plane[0].mapping_stride);
intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x);
- intel_de_write_fw(dev_priv, SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
+ intel_de_write_fw(dev_priv, SPRSIZE(pipe), ((crtc_h - 1) << 16) | (crtc_w - 1));
if (IS_IVYBRIDGE(dev_priv))
intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
@@ -1208,21 +1198,15 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
u32 dvsscale = 0;
unsigned long irqflags;
- /* Sizes are 0 based */
- src_w--;
- src_h--;
- crtc_w--;
- crtc_h--;
-
if (crtc_w != src_w || crtc_h != src_h)
- dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
+ dvsscale = DVS_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
plane_state->view.color_plane[0].mapping_stride);
intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x);
- intel_de_write_fw(dev_priv, DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
+ intel_de_write_fw(dev_priv, DVSSIZE(pipe), ((crtc_h - 1) << 16) | (crtc_w - 1));
intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 9ff24a0e79b4..09948922016b 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1022,10 +1022,6 @@ skl_program_plane_noarm(struct intel_plane *plane,
u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
unsigned long irqflags;
- /* Sizes are 0 based */
- src_w--;
- src_h--;
-
/* The scaler will handle the output position */
if (plane_state->scaler_id >= 0) {
crtc_x = 0;
@@ -1045,7 +1041,7 @@ skl_program_plane_noarm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
(crtc_y << 16) | crtc_x);
intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
- (src_h << 16) | src_w);
+ ((src_h - 1) << 16) | (src_w - 1));
if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
--
2.32.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 04/14] drm/i915: Sipmplify PLANE_STRIDE masking
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
` (2 preceding siblings ...)
2021-12-01 15:25 ` [Intel-gfx] [PATCH 03/14] drm/i915: Get rid of the "sizes are 0 based" stuff Ville Syrjala
@ 2021-12-01 15:25 ` Ville Syrjala
2022-01-12 19:50 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 05/14] drm/i915: Rename PLANE_CUS_CTL Y plane bits Ville Syrjala
` (13 subsequent siblings)
17 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2021-12-01 15:25 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
There's no need to have separate masks for the stride bitfield
in PLANE_STRIDE for different platforms. All the extra bits
are hardcoded to zero anyway.
Also the masks we're using now don't even match the actual hardware
since the bitfield was only 10 bits on skl/derivatives, only getting
bumped to 11 bits on glk.
So let's just use a 12 bit mask for everything.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 +----
drivers/gpu/drm/i915/i915_reg.h | 3 +--
2 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 09948922016b..984bb35ecf06 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2347,10 +2347,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
- if (DISPLAY_VER(dev_priv) >= 13)
- fb->pitches[0] = (val & PLANE_STRIDE_MASK_XELPD) * stride_mult;
- else
- fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
+ fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
aligned_height = intel_fb_align_height(fb, 0, fb->height);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 02d8db03c0bf..6066b1e2763c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7440,8 +7440,7 @@ enum {
_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
#define PLANE_STRIDE(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
-#define PLANE_STRIDE_MASK REG_GENMASK(10, 0)
-#define PLANE_STRIDE_MASK_XELPD REG_GENMASK(11, 0)
+#define PLANE_STRIDE_MASK REG_GENMASK(11, 0)
#define _PLANE_POS_1_B 0x7118c
#define _PLANE_POS_2_B 0x7128c
--
2.32.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 05/14] drm/i915: Rename PLANE_CUS_CTL Y plane bits
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
` (3 preceding siblings ...)
2021-12-01 15:25 ` [Intel-gfx] [PATCH 04/14] drm/i915: Sipmplify PLANE_STRIDE masking Ville Syrjala
@ 2021-12-01 15:25 ` Ville Syrjala
2021-12-01 17:17 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 06/14] drm/i915: Use REG_BIT() & co. for universal " Ville Syrjala
` (12 subsequent siblings)
17 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2021-12-01 15:25 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename the PLANE_CUS_CTL Y plane selection bits to actually
say "Y plane".
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 8 ++++----
drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index badf035efaeb..726c1552c9bf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5159,13 +5159,13 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
if (icl_is_hdr_plane(dev_priv, plane->id)) {
if (linked->id == PLANE_SPRITE5)
- plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
+ plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
else if (linked->id == PLANE_SPRITE4)
- plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
+ plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
else if (linked->id == PLANE_SPRITE3)
- plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
+ plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
else if (linked->id == PLANE_SPRITE2)
- plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
+ plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
else
MISSING_CASE(linked->id);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6066b1e2763c..4b2bc17d0235 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7328,10 +7328,10 @@ enum {
#define _PLANE_CUS_CTL_1_A 0x701c8
#define _PLANE_CUS_CTL_2_A 0x702c8
#define PLANE_CUS_ENABLE (1 << 31)
-#define PLANE_CUS_PLANE_4_RKL (0 << 30)
-#define PLANE_CUS_PLANE_5_RKL (1 << 30)
-#define PLANE_CUS_PLANE_6 (0 << 30)
-#define PLANE_CUS_PLANE_7 (1 << 30)
+#define PLANE_CUS_Y_PLANE_4_RKL (0 << 30)
+#define PLANE_CUS_Y_PLANE_5_RKL (1 << 30)
+#define PLANE_CUS_Y_PLANE_6_ICL (0 << 30)
+#define PLANE_CUS_Y_PLANE_7_ICL (1 << 30)
#define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19)
#define PLANE_CUS_HPHASE_0 (0 << 16)
#define PLANE_CUS_HPHASE_0_25 (1 << 16)
--
2.32.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 06/14] drm/i915: Use REG_BIT() & co. for universal plane bits
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
` (4 preceding siblings ...)
2021-12-01 15:25 ` [Intel-gfx] [PATCH 05/14] drm/i915: Rename PLANE_CUS_CTL Y plane bits Ville Syrjala
@ 2021-12-01 15:25 ` Ville Syrjala
2021-12-01 17:26 ` Souza, Jose
2021-12-06 15:57 ` kernel test robot
2021-12-01 15:25 ` [Intel-gfx] [PATCH 07/14] drm/i915: Clean up pre-skl primary plane registers Ville Syrjala
` (11 subsequent siblings)
17 siblings, 2 replies; 48+ messages in thread
From: Ville Syrjala @ 2021-12-01 15:25 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Polish the skl+ universal plane register defines by
using REG_BIT() & co.
The defines are also currently spread around in some
semi-random fashion. Collect them up into one place.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/skl_universal_plane.c | 36 ++--
drivers/gpu/drm/i915/gvt/reg.h | 1 -
drivers/gpu/drm/i915/i915_reg.h | 197 ++++++++++--------
drivers/gpu/drm/i915/intel_pm.c | 12 +-
4 files changed, 135 insertions(+), 111 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 984bb35ecf06..79998eb67280 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1037,11 +1037,12 @@ skl_program_plane_noarm(struct intel_plane *plane,
if (plane_state->force_black)
icl_plane_csc_load_black(plane);
- intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), stride);
+ intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
+ PLANE_STRIDE_(stride));
intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
- (crtc_y << 16) | crtc_x);
+ PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
- ((src_h - 1) << 16) | (src_w - 1));
+ PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
@@ -1100,7 +1101,7 @@ skl_program_plane_arm(struct intel_plane *plane,
skl_surf_address(plane_state, color_plane);
if (DISPLAY_VER(dev_priv) < 12)
- aux_dist |= skl_plane_stride(plane_state, aux_plane);
+ aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));
}
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
@@ -1111,14 +1112,14 @@ skl_program_plane_arm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), keymax);
intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
- (y << 16) | x);
+ PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
if (DISPLAY_VER(dev_priv) < 11)
intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
- (plane_state->view.color_plane[1].y << 16) |
- plane_state->view.color_plane[1].x);
+ PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) |
+ PLANE_OFFSET_X(plane_state->view.color_plane[1].x));
if (DISPLAY_VER(dev_priv) >= 10)
intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
@@ -2262,16 +2263,17 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
if (DISPLAY_VER(dev_priv) >= 11)
- pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
+ pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL;
else
- pixel_format = val & PLANE_CTL_FORMAT_MASK;
+ pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL;
if (DISPLAY_VER(dev_priv) >= 10) {
- alpha = intel_de_read(dev_priv,
- PLANE_COLOR_CTL(pipe, plane_id));
- alpha &= PLANE_COLOR_ALPHA_MASK;
+ u32 color_ctl;
+
+ color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe, plane_id));
+ alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl);
} else {
- alpha = val & PLANE_CTL_ALPHA_MASK;
+ alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val);
}
fourcc = skl_format_to_fourcc(pixel_format,
@@ -2335,19 +2337,19 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
if (drm_rotation_90_or_270(plane_config->rotation))
goto error;
- base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
+ base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK;
plane_config->base = base;
offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
- fb->height = ((val >> 16) & 0xffff) + 1;
- fb->width = ((val >> 0) & 0xffff) + 1;
+ fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1;
+ fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1;
val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
- fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
+ fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult;
aligned_height = intel_fb_align_height(fb, 0, fb->height);
diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
index 244cc7320b54..7d666d34f9ff 100644
--- a/drivers/gpu/drm/i915/gvt/reg.h
+++ b/drivers/gpu/drm/i915/gvt/reg.h
@@ -62,7 +62,6 @@
#define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe))
-#define PLANE_CTL_ASYNC_FLIP (1 << 9)
#define REG50080_FLIP_TYPE_MASK 0x3
#define REG50080_FLIP_TYPE_ASYNC 0x1
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4b2bc17d0235..9fffa2392bbf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7233,84 +7233,99 @@ enum {
#define _PLANE_CTL_1_A 0x70180
#define _PLANE_CTL_2_A 0x70280
#define _PLANE_CTL_3_A 0x70380
-#define PLANE_CTL_ENABLE (1 << 31)
+#define PLANE_CTL_ENABLE REG_BIT(31)
#define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
#define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
-#define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
-#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
+#define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
+#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
/*
* ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
* expanded to include bit 23 as well. However, the shift-24 based values
* correctly map to the same formats in ICL, as long as bit 23 is set to 0
*/
-#define PLANE_CTL_FORMAT_MASK (0xf << 24)
-#define PLANE_CTL_FORMAT_YUV422 (0 << 24)
-#define PLANE_CTL_FORMAT_NV12 (1 << 24)
-#define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
-#define PLANE_CTL_FORMAT_P010 (3 << 24)
-#define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24)
-#define PLANE_CTL_FORMAT_P012 (5 << 24)
-#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
-#define PLANE_CTL_FORMAT_P016 (7 << 24)
-#define PLANE_CTL_FORMAT_XYUV (8 << 24)
-#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
-#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
-#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
-#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
-#define PLANE_CTL_FORMAT_Y210 (1 << 23)
-#define PLANE_CTL_FORMAT_Y212 (3 << 23)
-#define PLANE_CTL_FORMAT_Y216 (5 << 23)
-#define PLANE_CTL_FORMAT_Y410 (7 << 23)
-#define PLANE_CTL_FORMAT_Y412 (9 << 23)
-#define PLANE_CTL_FORMAT_Y416 (0xb << 23)
-#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
-#define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
-#define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
-#define PLANE_CTL_ORDER_BGRX (0 << 20)
-#define PLANE_CTL_ORDER_RGBX (1 << 20)
-#define PLANE_CTL_YUV420_Y_PLANE (1 << 19)
-#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
-#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
-#define PLANE_CTL_YUV422_ORDER_YUYV (0 << 16)
-#define PLANE_CTL_YUV422_ORDER_UYVY (1 << 16)
-#define PLANE_CTL_YUV422_ORDER_YVYU (2 << 16)
-#define PLANE_CTL_YUV422_ORDER_VYUY (3 << 16)
-#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
-#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
-#define PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13) /* TGL+ */
-#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
-#define PLANE_CTL_TILED_MASK (0x7 << 10)
-#define PLANE_CTL_TILED_LINEAR (0 << 10)
-#define PLANE_CTL_TILED_X (1 << 10)
-#define PLANE_CTL_TILED_Y (4 << 10)
-#define PLANE_CTL_TILED_YF (5 << 10)
-#define PLANE_CTL_ASYNC_FLIP (1 << 9)
-#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
-#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
-#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
-#define PLANE_CTL_ALPHA_DISABLE (0 << 4)
-#define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
-#define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4)
-#define PLANE_CTL_ROTATE_MASK 0x3
-#define PLANE_CTL_ROTATE_0 0x0
-#define PLANE_CTL_ROTATE_90 0x1
-#define PLANE_CTL_ROTATE_180 0x2
-#define PLANE_CTL_ROTATE_270 0x3
+#define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */
+#define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */
+#define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
+#define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1)
+#define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2)
+#define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3)
+#define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4)
+#define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5)
+#define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6)
+#define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7)
+#define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8)
+#define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12)
+#define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14)
+#define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1)
+#define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3)
+#define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5)
+#define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7)
+#define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9)
+#define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11)
+#define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
+#define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21)
+#define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1)
+#define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2)
+#define PLANE_CTL_ORDER_RGBX REG_BIT(20)
+#define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19)
+#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18)
+#define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16)
+#define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)
+#define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1)
+#define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2)
+#define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3)
+#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15)
+#define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14)
+#define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
+#define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
+#define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10)
+#define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0)
+#define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1)
+#define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4)
+#define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
+#define PLANE_CTL_ASYNC_FLIP REG_BIT(9)
+#define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8)
+#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
+#define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
+#define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0)
+#define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2)
+#define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3)
+#define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0)
+#define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0)
+#define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
+#define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
+#define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
#define _PLANE_STRIDE_1_A 0x70188
#define _PLANE_STRIDE_2_A 0x70288
#define _PLANE_STRIDE_3_A 0x70388
+#define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
+#define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
#define _PLANE_POS_1_A 0x7018c
#define _PLANE_POS_2_A 0x7028c
#define _PLANE_POS_3_A 0x7038c
+#define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
+#define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
+#define PLANE_POS_X_MASK REG_GENMASK(15, 0)
+#define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
#define _PLANE_SIZE_1_A 0x70190
#define _PLANE_SIZE_2_A 0x70290
#define _PLANE_SIZE_3_A 0x70390
+#define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
+#define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
+#define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
+#define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
#define _PLANE_SURF_1_A 0x7019c
#define _PLANE_SURF_2_A 0x7029c
#define _PLANE_SURF_3_A 0x7039c
+#define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
+#define PLANE_SURF_DECRYPT REG_BIT(2)
#define _PLANE_OFFSET_1_A 0x701a4
#define _PLANE_OFFSET_2_A 0x702a4
#define _PLANE_OFFSET_3_A 0x703a4
+#define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
+#define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
+#define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
+#define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))
#define _PLANE_KEYVAL_1_A 0x70194
#define _PLANE_KEYVAL_2_A 0x70294
#define _PLANE_KEYMSK_1_A 0x70198
@@ -7322,42 +7337,49 @@ enum {
#define _PLANE_CC_VAL_1_A 0x701b4
#define _PLANE_CC_VAL_2_A 0x702b4
#define _PLANE_AUX_DIST_1_A 0x701c0
+#define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
+#define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
+#define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
#define _PLANE_AUX_DIST_2_A 0x702c0
#define _PLANE_AUX_OFFSET_1_A 0x701c4
#define _PLANE_AUX_OFFSET_2_A 0x702c4
#define _PLANE_CUS_CTL_1_A 0x701c8
#define _PLANE_CUS_CTL_2_A 0x702c8
-#define PLANE_CUS_ENABLE (1 << 31)
-#define PLANE_CUS_Y_PLANE_4_RKL (0 << 30)
-#define PLANE_CUS_Y_PLANE_5_RKL (1 << 30)
-#define PLANE_CUS_Y_PLANE_6_ICL (0 << 30)
-#define PLANE_CUS_Y_PLANE_7_ICL (1 << 30)
-#define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19)
-#define PLANE_CUS_HPHASE_0 (0 << 16)
-#define PLANE_CUS_HPHASE_0_25 (1 << 16)
-#define PLANE_CUS_HPHASE_0_5 (2 << 16)
-#define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15)
-#define PLANE_CUS_VPHASE_0 (0 << 12)
-#define PLANE_CUS_VPHASE_0_25 (1 << 12)
-#define PLANE_CUS_VPHASE_0_5 (2 << 12)
+#define PLANE_CUS_ENABLE REG_BIT(31)
+#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
+#define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
+#define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
+#define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
+#define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
+#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
+#define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16)
+#define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
+#define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
+#define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
+#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
+#define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12)
+#define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
+#define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
+#define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
-#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
-#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
+#define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
+#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
+#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
#define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
-#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
-#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
-#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
-#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 (1 << 17)
-#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
-#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
-#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
-#define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
-#define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
-#define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
-#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
-#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
+#define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
+#define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17)
+#define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
+#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)
+#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2)
+#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3)
+#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4)
+#define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13)
+#define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4)
+#define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
+#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
+#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
#define _PLANE_BUF_CFG_1_A 0x7027c
#define _PLANE_BUF_CFG_2_A 0x7037c
#define _PLANE_NV12_BUF_CFG_1_A 0x70278
@@ -7440,7 +7462,6 @@ enum {
_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
#define PLANE_STRIDE(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
-#define PLANE_STRIDE_MASK REG_GENMASK(11, 0)
#define _PLANE_POS_1_B 0x7118c
#define _PLANE_POS_2_B 0x7128c
@@ -7468,7 +7489,6 @@ enum {
#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
-#define PLANE_SURF_DECRYPT REG_BIT(2)
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
@@ -7500,8 +7520,11 @@ enum {
#define _PLANE_BUF_CFG_1_B 0x7127c
#define _PLANE_BUF_CFG_2_B 0x7137c
-#define DDB_ENTRY_MASK 0xFFF /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
-#define DDB_ENTRY_END_SHIFT 16
+/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
+#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
+#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
+#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
+#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
#define _PLANE_BUF_CFG_1(pipe) \
_PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
#define _PLANE_BUF_CFG_2(pipe) \
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cff0f32bedc9..7f00fd2f62a0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4283,11 +4283,10 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
struct skl_ddb_entry *entry, u32 reg)
{
- entry->start = reg & DDB_ENTRY_MASK;
- entry->end = (reg >> DDB_ENTRY_END_SHIFT) & DDB_ENTRY_MASK;
-
+ entry->start = REG_FIELD_GET(PLANE_BUF_START_MASK, reg);
+ entry->end = REG_FIELD_GET(PLANE_BUF_END_MASK, reg);
if (entry->end)
- entry->end += 1;
+ entry->end++;
}
static void
@@ -4311,7 +4310,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
/* No DDB allocated for disabled planes */
if (val & PLANE_CTL_ENABLE)
- fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK,
+ fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK_SKL,
val & PLANE_CTL_ORDER_RGBX,
val & PLANE_CTL_ALPHA_MASK);
@@ -5882,7 +5881,8 @@ static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
{
if (entry->end)
intel_de_write_fw(dev_priv, reg,
- (entry->end - 1) << 16 | entry->start);
+ PLANE_BUF_END(entry->end - 1) |
+ PLANE_BUF_START(entry->start));
else
intel_de_write_fw(dev_priv, reg, 0);
}
--
2.32.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 07/14] drm/i915: Clean up pre-skl primary plane registers
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
` (5 preceding siblings ...)
2021-12-01 15:25 ` [Intel-gfx] [PATCH 06/14] drm/i915: Use REG_BIT() & co. for universal " Ville Syrjala
@ 2021-12-01 15:25 ` Ville Syrjala
2021-12-06 19:22 ` kernel test robot
2022-01-12 20:12 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 08/14] drm/i915: Clean up ivb+ sprite " Ville Syrjala
` (10 subsequent siblings)
17 siblings, 2 replies; 48+ messages in thread
From: Ville Syrjala @ 2021-12-01 15:25 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use REG_BIT() & co. for the pre-skl primary plane registers.
Also give everything a consistent namespace.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 99 +++++++++--------
drivers/gpu/drm/i915/display/intel_display.c | 13 +--
drivers/gpu/drm/i915/i915_reg.h | 108 +++++++++++--------
drivers/gpu/drm/i915/intel_pm.c | 2 +-
4 files changed, 117 insertions(+), 105 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 2194f74101ae..00cc8b4bd6bc 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -145,51 +145,51 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
unsigned int rotation = plane_state->hw.rotation;
u32 dspcntr;
- dspcntr = DISPLAY_PLANE_ENABLE;
+ dspcntr = DSP_ENABLE;
if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) ||
IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
- dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
+ dspcntr |= DSP_TRICKLE_FEED_DISABLE;
switch (fb->format->format) {
case DRM_FORMAT_C8:
- dspcntr |= DISPPLANE_8BPP;
+ dspcntr |= DSP_FORMAT_8BPP;
break;
case DRM_FORMAT_XRGB1555:
- dspcntr |= DISPPLANE_BGRX555;
+ dspcntr |= DSP_FORMAT_BGRX555;
break;
case DRM_FORMAT_ARGB1555:
- dspcntr |= DISPPLANE_BGRA555;
+ dspcntr |= DSP_FORMAT_BGRA555;
break;
case DRM_FORMAT_RGB565:
- dspcntr |= DISPPLANE_BGRX565;
+ dspcntr |= DSP_FORMAT_BGRX565;
break;
case DRM_FORMAT_XRGB8888:
- dspcntr |= DISPPLANE_BGRX888;
+ dspcntr |= DSP_FORMAT_BGRX888;
break;
case DRM_FORMAT_XBGR8888:
- dspcntr |= DISPPLANE_RGBX888;
+ dspcntr |= DSP_FORMAT_RGBX888;
break;
case DRM_FORMAT_ARGB8888:
- dspcntr |= DISPPLANE_BGRA888;
+ dspcntr |= DSP_FORMAT_BGRA888;
break;
case DRM_FORMAT_ABGR8888:
- dspcntr |= DISPPLANE_RGBA888;
+ dspcntr |= DSP_FORMAT_RGBA888;
break;
case DRM_FORMAT_XRGB2101010:
- dspcntr |= DISPPLANE_BGRX101010;
+ dspcntr |= DSP_FORMAT_BGRX101010;
break;
case DRM_FORMAT_XBGR2101010:
- dspcntr |= DISPPLANE_RGBX101010;
+ dspcntr |= DSP_FORMAT_RGBX101010;
break;
case DRM_FORMAT_ARGB2101010:
- dspcntr |= DISPPLANE_BGRA101010;
+ dspcntr |= DSP_FORMAT_BGRA101010;
break;
case DRM_FORMAT_ABGR2101010:
- dspcntr |= DISPPLANE_RGBA101010;
+ dspcntr |= DSP_FORMAT_RGBA101010;
break;
case DRM_FORMAT_XBGR16161616F:
- dspcntr |= DISPPLANE_RGBX161616;
+ dspcntr |= DSP_FORMAT_RGBX161616;
break;
default:
MISSING_CASE(fb->format->format);
@@ -198,13 +198,13 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
if (DISPLAY_VER(dev_priv) >= 4 &&
fb->modifier == I915_FORMAT_MOD_X_TILED)
- dspcntr |= DISPPLANE_TILED;
+ dspcntr |= DSP_TILED;
if (rotation & DRM_MODE_ROTATE_180)
- dspcntr |= DISPPLANE_ROTATE_180;
+ dspcntr |= DSP_ROTATE_180;
if (rotation & DRM_MODE_REFLECT_X)
- dspcntr |= DISPPLANE_MIRROR;
+ dspcntr |= DSP_MIRROR;
return dspcntr;
}
@@ -344,13 +344,13 @@ static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
u32 dspcntr = 0;
if (crtc_state->gamma_enable)
- dspcntr |= DISPPLANE_GAMMA_ENABLE;
+ dspcntr |= DSP_PIPE_GAMMA_ENABLE;
if (crtc_state->csc_enable)
- dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
+ dspcntr |= DSP_PIPE_CSC_ENABLE;
if (DISPLAY_VER(dev_priv) < 5)
- dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
+ dspcntr |= DSP_PIPE_SEL(crtc->pipe);
return dspcntr;
}
@@ -427,9 +427,9 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane,
* program whatever is there.
*/
intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
- (crtc_y << 16) | crtc_x);
+ DSP_POS_Y(crtc_y) | DSP_POS_X(crtc_x));
intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
- ((crtc_h - 1) << 16) | (crtc_w - 1));
+ DSP_HEIGHT(crtc_h - 1) | DSP_POS_X(crtc_w - 1));
}
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
@@ -464,20 +464,20 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
int crtc_h = drm_rect_height(&plane_state->uapi.dst);
intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
- (crtc_y << 16) | crtc_x);
+ PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x));
intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
- ((crtc_h - 1) << 16) | (crtc_w - 1));
+ PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1));
intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
}
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
- (y << 16) | x);
+ DSP_OFFSET_Y(y) | DSP_OFFSET_X(x));
} else if (DISPLAY_VER(dev_priv) >= 4) {
intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
linear_offset);
intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
- (y << 16) | x);
+ DSP_OFFSET_Y(y) | DSP_OFFSET_X(x));
}
/*
@@ -554,7 +554,7 @@ g4x_primary_async_flip(struct intel_plane *plane,
unsigned long irqflags;
if (async_flip)
- dspcntr |= DISPPLANE_ASYNC_FLIP;
+ dspcntr |= DSP_ASYNC_FLIP;
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
@@ -686,13 +686,12 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
- ret = val & DISPLAY_PLANE_ENABLE;
+ ret = val & DSP_ENABLE;
if (DISPLAY_VER(dev_priv) >= 5)
*pipe = plane->pipe;
else
- *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
- DISPPLANE_SEL_PIPE_SHIFT;
+ *pipe = REG_FIELD_GET(DSP_PIPE_SEL_MASK, val);
intel_display_power_put(dev_priv, power_domain, wakeref);
@@ -951,32 +950,32 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
static int i9xx_format_to_fourcc(int format)
{
switch (format) {
- case DISPPLANE_8BPP:
+ case DSP_FORMAT_8BPP:
return DRM_FORMAT_C8;
- case DISPPLANE_BGRA555:
+ case DSP_FORMAT_BGRA555:
return DRM_FORMAT_ARGB1555;
- case DISPPLANE_BGRX555:
+ case DSP_FORMAT_BGRX555:
return DRM_FORMAT_XRGB1555;
- case DISPPLANE_BGRX565:
+ case DSP_FORMAT_BGRX565:
return DRM_FORMAT_RGB565;
default:
- case DISPPLANE_BGRX888:
+ case DSP_FORMAT_BGRX888:
return DRM_FORMAT_XRGB8888;
- case DISPPLANE_RGBX888:
+ case DSP_FORMAT_RGBX888:
return DRM_FORMAT_XBGR8888;
- case DISPPLANE_BGRA888:
+ case DSP_FORMAT_BGRA888:
return DRM_FORMAT_ARGB8888;
- case DISPPLANE_RGBA888:
+ case DSP_FORMAT_RGBA888:
return DRM_FORMAT_ABGR8888;
- case DISPPLANE_BGRX101010:
+ case DSP_FORMAT_BGRX101010:
return DRM_FORMAT_XRGB2101010;
- case DISPPLANE_RGBX101010:
+ case DSP_FORMAT_RGBX101010:
return DRM_FORMAT_XBGR2101010;
- case DISPPLANE_BGRA101010:
+ case DSP_FORMAT_BGRA101010:
return DRM_FORMAT_ARGB2101010;
- case DISPPLANE_RGBA101010:
+ case DSP_FORMAT_RGBA101010:
return DRM_FORMAT_ABGR2101010;
- case DISPPLANE_RGBX161616:
+ case DSP_FORMAT_RGBX161616:
return DRM_FORMAT_XBGR16161616F;
}
}
@@ -1014,26 +1013,26 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
if (DISPLAY_VER(dev_priv) >= 4) {
- if (val & DISPPLANE_TILED) {
+ if (val & DSP_TILED) {
plane_config->tiling = I915_TILING_X;
fb->modifier = I915_FORMAT_MOD_X_TILED;
}
- if (val & DISPPLANE_ROTATE_180)
+ if (val & DSP_ROTATE_180)
plane_config->rotation = DRM_MODE_ROTATE_180;
}
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
- val & DISPPLANE_MIRROR)
+ val & DSP_MIRROR)
plane_config->rotation |= DRM_MODE_REFLECT_X;
- pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
+ pixel_format = val & DSP_FORMAT_MASK;
fourcc = i9xx_format_to_fourcc(pixel_format);
fb->format = drm_format_info(fourcc);
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
- base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
+ base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DSP_ADDR_MASK;
} else if (DISPLAY_VER(dev_priv) >= 4) {
if (plane_config->tiling)
offset = intel_de_read(dev_priv,
@@ -1041,7 +1040,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
else
offset = intel_de_read(dev_priv,
DSPLINOFF(i9xx_plane));
- base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
+ base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DSP_ADDR_MASK;
} else {
base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 726c1552c9bf..00a2c9915780 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3534,11 +3534,11 @@ static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
- if (tmp & DISPPLANE_GAMMA_ENABLE)
+ if (tmp & DSP_PIPE_GAMMA_ENABLE)
crtc_state->gamma_enable = true;
if (!HAS_GMCH(dev_priv) &&
- tmp & DISPPLANE_PIPE_CSC_ENABLE)
+ tmp & DSP_PIPE_CSC_ENABLE)
crtc_state->csc_enable = true;
}
@@ -10035,14 +10035,11 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
pipe_name(pipe));
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
- DISPLAY_PLANE_ENABLE);
+ intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DSP_ENABLE);
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
- DISPLAY_PLANE_ENABLE);
+ intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DSP_ENABLE);
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
- DISPLAY_PLANE_ENABLE);
+ intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DSP_ENABLE);
drm_WARN_ON(&dev_priv->drm,
intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
drm_WARN_ON(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9fffa2392bbf..8678cbab1d33 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6824,49 +6824,54 @@ enum {
/* Display A control */
#define _DSPAADDR_VLV 0x7017C /* vlv/chv */
#define _DSPACNTR 0x70180
-#define DISPLAY_PLANE_ENABLE (1 << 31)
-#define DISPLAY_PLANE_DISABLE 0
-#define DISPPLANE_GAMMA_ENABLE (1 << 30)
-#define DISPPLANE_GAMMA_DISABLE 0
-#define DISPPLANE_PIXFORMAT_MASK (0xf << 26)
-#define DISPPLANE_YUV422 (0x0 << 26)
-#define DISPPLANE_8BPP (0x2 << 26)
-#define DISPPLANE_BGRA555 (0x3 << 26)
-#define DISPPLANE_BGRX555 (0x4 << 26)
-#define DISPPLANE_BGRX565 (0x5 << 26)
-#define DISPPLANE_BGRX888 (0x6 << 26)
-#define DISPPLANE_BGRA888 (0x7 << 26)
-#define DISPPLANE_RGBX101010 (0x8 << 26)
-#define DISPPLANE_RGBA101010 (0x9 << 26)
-#define DISPPLANE_BGRX101010 (0xa << 26)
-#define DISPPLANE_BGRA101010 (0xb << 26)
-#define DISPPLANE_RGBX161616 (0xc << 26)
-#define DISPPLANE_RGBX888 (0xe << 26)
-#define DISPPLANE_RGBA888 (0xf << 26)
-#define DISPPLANE_STEREO_ENABLE (1 << 25)
-#define DISPPLANE_STEREO_DISABLE 0
-#define DISPPLANE_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
-#define DISPPLANE_SEL_PIPE_SHIFT 24
-#define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT)
-#define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
-#define DISPPLANE_SRC_KEY_ENABLE (1 << 22)
-#define DISPPLANE_SRC_KEY_DISABLE 0
-#define DISPPLANE_LINE_DOUBLE (1 << 20)
-#define DISPPLANE_NO_LINE_DOUBLE 0
-#define DISPPLANE_STEREO_POLARITY_FIRST 0
-#define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)
-#define DISPPLANE_ALPHA_PREMULTIPLY (1 << 16) /* CHV pipe B */
-#define DISPPLANE_ROTATE_180 (1 << 15)
-#define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14) /* Ironlake */
-#define DISPPLANE_TILED (1 << 10)
-#define DISPPLANE_ASYNC_FLIP (1 << 9) /* g4x+ */
-#define DISPPLANE_MIRROR (1 << 8) /* CHV pipe B */
+#define DSP_ENABLE REG_BIT(31)
+#define DSP_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define DSP_FORMAT_MASK REG_GENMASK(29, 26)
+#define DSP_FORMAT_8BPP REG_FIELD_PREP(DSP_FORMAT_MASK, 2)
+#define DSP_FORMAT_BGRA555 REG_FIELD_PREP(DSP_FORMAT_MASK, 3)
+#define DSP_FORMAT_BGRX555 REG_FIELD_PREP(DSP_FORMAT_MASK, 4)
+#define DSP_FORMAT_BGRX565 REG_FIELD_PREP(DSP_FORMAT_MASK, 5)
+#define DSP_FORMAT_BGRX888 REG_FIELD_PREP(DSP_FORMAT_MASK, 6)
+#define DSP_FORMAT_BGRA888 REG_FIELD_PREP(DSP_FORMAT_MASK, 7)
+#define DSP_FORMAT_RGBX101010 REG_FIELD_PREP(DSP_FORMAT_MASK, 8)
+#define DSP_FORMAT_RGBA101010 REG_FIELD_PREP(DSP_FORMAT_MASK, 9)
+#define DSP_FORMAT_BGRX101010 REG_FIELD_PREP(DSP_FORMAT_MASK, 10)
+#define DSP_FORMAT_BGRA101010 REG_FIELD_PREP(DSP_FORMAT_MASK, 11)
+#define DSP_FORMAT_RGBX161616 REG_FIELD_PREP(DSP_FORMAT_MASK, 12)
+#define DSP_FORMAT_RGBX888 REG_FIELD_PREP(DSP_FORMAT_MASK, 14)
+#define DSP_FORMAT_RGBA888 REG_FIELD_PREP(DSP_FORMAT_MASK, 15)
+#define DSP_STEREO_ENABLE REG_BIT(25)
+#define DSP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
+#define DSP_PIPE_SEL_MASK REG_GENMASK(25, 24)
+#define DSP_PIPE_SEL(pipe) REG_FIELD_PREP(DSP_PIPE_SEL_MASK, (pipe))
+#define DSP_SRC_KEY_ENABLE REG_BIT(22)
+#define DSP_LINE_DOUBLE REG_BIT(20)
+#define DSP_STEREO_POLARITY_SECOND REG_BIT(18)
+#define DSP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
+#define DSP_ROTATE_180 REG_BIT(15)
+#define DSP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */
+#define DSP_TILED REG_BIT(10)
+#define DSP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
+#define DSP_MIRROR REG_BIT(8) /* CHV pipe B */
#define _DSPAADDR 0x70184
#define _DSPASTRIDE 0x70188
#define _DSPAPOS 0x7018C /* reserved */
+#define DSP_POS_Y_MASK REG_GENMASK(31, 0)
+#define DSP_POS_Y(y) REG_FIELD_PREP(DSP_POS_Y_MASK, (y))
+#define DSP_POS_X_MASK REG_GENMASK(15, 0)
+#define DSP_POS_X(x) REG_FIELD_PREP(DSP_POS_X_MASK, (x))
#define _DSPASIZE 0x70190
+#define DSP_HEIGHT_MASK REG_GENMASK(31, 0)
+#define DSP_HEIGHT(h) REG_FIELD_PREP(DSP_HEIGHT_MASK, (h))
+#define DSP_WIDTH_MASK REG_GENMASK(15, 0)
+#define DSP_WIDTH(w) REG_FIELD_PREP(DSP_WIDTH_MASK, (w))
#define _DSPASURF 0x7019C /* 965+ only */
+#define DSP_ADDR_MASK REG_GENMASK(31, 12)
#define _DSPATILEOFF 0x701A4 /* 965+ only */
+#define DSP_OFFSET_Y_MASK REG_GENMASK(31, 16)
+#define DSP_OFFSET_Y(y) REG_FIELD_PREP(DSP_OFFSET_Y_MASK, (y))
+#define DSP_OFFSET_X_MASK REG_GENMASK(15, 0)
+#define DSP_OFFSET_X(x) REG_FIELD_PREP(DSP_OFFSET_X_MASK, (x))
#define _DSPAOFFSET 0x701A4 /* HSW */
#define _DSPASURFLIVE 0x701AC
#define _DSPAGAMC 0x701E0
@@ -6886,15 +6891,28 @@ enum {
/* CHV pipe B blender and primary plane */
#define _CHV_BLEND_A 0x60a00
-#define CHV_BLEND_LEGACY (0 << 30)
-#define CHV_BLEND_ANDROID (1 << 30)
-#define CHV_BLEND_MPO (2 << 30)
-#define CHV_BLEND_MASK (3 << 30)
+#define CHV_BLEND_MASK REG_GENMASK(31, 30)
+#define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
+#define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1)
+#define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2)
#define _CHV_CANVAS_A 0x60a04
+#define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
+#define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
+#define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
#define _PRIMPOS_A 0x60a08
+#define PRIM_POS_Y_MASK REG_GENMASK(31, 16)
+#define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
+#define PRIM_POS_X_MASK REG_GENMASK(15, 0)
+#define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x))
#define _PRIMSIZE_A 0x60a0c
+#define PRIM_HEIGHT_MASK REG_GENMASK(31, 16)
+#define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))
+#define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
+#define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
#define _PRIMCNSTALPHA_A 0x60a10
-#define PRIM_CONST_ALPHA_ENABLE (1 << 31)
+#define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
+#define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0)
+#define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))
#define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
#define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
@@ -6935,10 +6953,8 @@ enum {
/* Display B control */
#define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
-#define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
-#define DISPPLANE_ALPHA_TRANS_DISABLE 0
-#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
-#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
+#define DSP_ALPHA_TRANS_ENABLE REG_BIT(15)
+#define DSP_SPRITE_ABOVE_OVERLAY REG_BIT(0)
#define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
#define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
#define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7f00fd2f62a0..2941c2cd1708 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7211,7 +7211,7 @@ static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
for_each_pipe(dev_priv, pipe) {
intel_uncore_write(&dev_priv->uncore, DSPCNTR(pipe),
intel_uncore_read(&dev_priv->uncore, DSPCNTR(pipe)) |
- DISPPLANE_TRICKLE_FEED_DISABLE);
+ DSP_TRICKLE_FEED_DISABLE);
intel_uncore_write(&dev_priv->uncore, DSPSURF(pipe), intel_uncore_read(&dev_priv->uncore, DSPSURF(pipe)));
intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe));
--
2.32.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 08/14] drm/i915: Clean up ivb+ sprite plane registers
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
` (6 preceding siblings ...)
2021-12-01 15:25 ` [Intel-gfx] [PATCH 07/14] drm/i915: Clean up pre-skl primary plane registers Ville Syrjala
@ 2021-12-01 15:25 ` Ville Syrjala
2022-01-14 16:26 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 09/14] drm/i915: Clean up vlv/chv " Ville Syrjala
` (9 subsequent siblings)
17 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2021-12-01 15:25 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use REG_BIT() & co. to polish the ivb+ sprite plane registers.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 20 +++--
drivers/gpu/drm/i915/i915_reg.h | 81 +++++++++++++--------
2 files changed, 62 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 2067a7bca4a8..70083d04a9fd 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -700,7 +700,7 @@ static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
u32 sprctl = 0;
if (crtc_state->gamma_enable)
- sprctl |= SPRITE_GAMMA_ENABLE;
+ sprctl |= SPRITE_PIPE_GAMMA_ENABLE;
if (crtc_state->csc_enable)
sprctl |= SPRITE_PIPE_CSC_ENABLE;
@@ -770,7 +770,7 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
}
if (!ivb_need_sprite_gamma(plane_state))
- sprctl |= SPRITE_INT_GAMMA_DISABLE;
+ sprctl |= SPRITE_PLANE_GAMMA_DISABLE;
if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
@@ -863,14 +863,18 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
unsigned long irqflags;
if (crtc_w != src_w || crtc_h != src_h)
- sprscale = SPRITE_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
+ sprscale = SPRITE_SCALE_ENABLE |
+ SPRITE_SRC_WIDTH(src_w - 1) |
+ SPRITE_SRC_HEIGHT(src_h - 1);
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
plane_state->view.color_plane[0].mapping_stride);
- intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x);
- intel_de_write_fw(dev_priv, SPRSIZE(pipe), ((crtc_h - 1) << 16) | (crtc_w - 1));
+ intel_de_write_fw(dev_priv, SPRPOS(pipe),
+ SPRITE_POS_Y(crtc_y) | SPRITE_POS_X(crtc_x));
+ intel_de_write_fw(dev_priv, SPRSIZE(pipe),
+ SPRITE_HEIGHT(crtc_h - 1) | SPRITE_WIDTH(crtc_w - 1));
if (IS_IVYBRIDGE(dev_priv))
intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
@@ -907,10 +911,12 @@ ivb_sprite_update_arm(struct intel_plane *plane,
/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
* register */
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
- intel_de_write_fw(dev_priv, SPROFFSET(pipe), (y << 16) | x);
+ intel_de_write_fw(dev_priv, SPROFFSET(pipe),
+ SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x));
} else {
intel_de_write_fw(dev_priv, SPRLINOFF(pipe), linear_offset);
- intel_de_write_fw(dev_priv, SPRTILEOFF(pipe), (y << 16) | x);
+ intel_de_write_fw(dev_priv, SPRTILEOFF(pipe),
+ SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x));
}
/*
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8678cbab1d33..0bd47a929f5d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7046,50 +7046,67 @@ enum {
#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
#define _SPRA_CTL 0x70280
-#define SPRITE_ENABLE (1 << 31)
-#define SPRITE_GAMMA_ENABLE (1 << 30)
-#define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
-#define SPRITE_PIXFORMAT_MASK (7 << 25)
-#define SPRITE_FORMAT_YUV422 (0 << 25)
-#define SPRITE_FORMAT_RGBX101010 (1 << 25)
-#define SPRITE_FORMAT_RGBX888 (2 << 25)
-#define SPRITE_FORMAT_RGBX161616 (3 << 25)
-#define SPRITE_FORMAT_YUV444 (4 << 25)
-#define SPRITE_FORMAT_XR_BGR101010 (5 << 25) /* Extended range */
-#define SPRITE_PIPE_CSC_ENABLE (1 << 24)
-#define SPRITE_SOURCE_KEY (1 << 22)
-#define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and 161616 */
-#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)
-#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */
-#define SPRITE_YUV_ORDER_MASK (3 << 16)
-#define SPRITE_YUV_ORDER_YUYV (0 << 16)
-#define SPRITE_YUV_ORDER_UYVY (1 << 16)
-#define SPRITE_YUV_ORDER_YVYU (2 << 16)
-#define SPRITE_YUV_ORDER_VYUY (3 << 16)
-#define SPRITE_ROTATE_180 (1 << 15)
-#define SPRITE_TRICKLE_FEED_DISABLE (1 << 14)
-#define SPRITE_INT_GAMMA_DISABLE (1 << 13)
-#define SPRITE_TILED (1 << 10)
-#define SPRITE_DEST_KEY (1 << 2)
+#define SPRITE_ENABLE REG_BIT(31)
+#define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
+#define SPRITE_FORMAT_MASK REG_GENMASK(27, 25)
+#define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0)
+#define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1)
+#define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2)
+#define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3)
+#define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4)
+#define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */
+#define SPRITE_PIPE_CSC_ENABLE REG_BIT(24)
+#define SPRITE_SOURCE_KEY REG_BIT(22)
+#define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */
+#define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19)
+#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */
+#define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16)
+#define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)
+#define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1)
+#define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2)
+#define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3)
+#define SPRITE_ROTATE_180 REG_BIT(15)
+#define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14)
+#define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13)
+#define SPRITE_TILED REG_BIT(10)
+#define SPRITE_DEST_KEY REG_BIT(2)
#define _SPRA_LINOFF 0x70284
#define _SPRA_STRIDE 0x70288
#define _SPRA_POS 0x7028c
+#define SPRITE_POS_Y_MASK REG_GENMASK(31, 16)
+#define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))
+#define SPRITE_POS_X_MASK REG_GENMASK(15, 0)
+#define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))
#define _SPRA_SIZE 0x70290
+#define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16)
+#define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))
+#define SPRITE_WIDTH_MASK REG_GENMASK(15, 0)
+#define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))
#define _SPRA_KEYVAL 0x70294
#define _SPRA_KEYMSK 0x70298
#define _SPRA_SURF 0x7029c
+#define SPRITE_ADDR_MASK REG_GENMASK(31, 12)
#define _SPRA_KEYMAX 0x702a0
#define _SPRA_TILEOFF 0x702a4
+#define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
+#define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
+#define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
+#define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
#define _SPRA_OFFSET 0x702a4
#define _SPRA_SURFLIVE 0x702ac
#define _SPRA_SCALE 0x70304
-#define SPRITE_SCALE_ENABLE (1 << 31)
-#define SPRITE_FILTER_MASK (3 << 29)
-#define SPRITE_FILTER_MEDIUM (0 << 29)
-#define SPRITE_FILTER_ENHANCING (1 << 29)
-#define SPRITE_FILTER_SOFTENING (2 << 29)
-#define SPRITE_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
-#define SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27)
+#define SPRITE_SCALE_ENABLE REG_BIT(31)
+#define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
+#define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
+#define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1)
+#define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2)
+#define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
+#define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27)
+#define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16)
+#define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))
+#define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
+#define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))
#define _SPRA_GAMC 0x70400
#define _SPRA_GAMC16 0x70440
#define _SPRA_GAMC17 0x7044c
--
2.32.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 09/14] drm/i915: Clean up vlv/chv sprite plane registers
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
` (7 preceding siblings ...)
2021-12-01 15:25 ` [Intel-gfx] [PATCH 08/14] drm/i915: Clean up ivb+ sprite " Ville Syrjala
@ 2021-12-01 15:25 ` Ville Syrjala
2022-01-14 16:34 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 10/14] drm/i915: Clean up g4x+ " Ville Syrjala
` (8 subsequent siblings)
17 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2021-12-01 15:25 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use REG_BIT() & co. to polish the vlv/chv sprite plane registers.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 9 +-
drivers/gpu/drm/i915/i915_reg.h | 103 ++++++++++++--------
2 files changed, 70 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 70083d04a9fd..eb9ce96c030f 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -313,7 +313,7 @@ static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
u32 sprctl = 0;
if (crtc_state->gamma_enable)
- sprctl |= SP_GAMMA_ENABLE;
+ sprctl |= SP_PIPE_GAMMA_ENABLE;
return sprctl;
}
@@ -436,9 +436,9 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
plane_state->view.color_plane[0].mapping_stride);
intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),
- (crtc_y << 16) | crtc_x);
+ SP_POS_Y(crtc_y) | SP_POS_X(crtc_x));
intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
- ((crtc_h - 1) << 16) | (crtc_w - 1));
+ SP_HEIGHT(crtc_h - 1) | SP_WIDTH(crtc_w - 1));
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
@@ -479,7 +479,8 @@ vlv_sprite_update_arm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0);
intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset);
- intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id), (y << 16) | x);
+ intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id),
+ SP_OFFSET_Y(y) | SP_OFFSET_X(x));
/*
* The control register self-arms if the plane was previously
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0bd47a929f5d..4d61e7f2ee7c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7146,48 +7146,67 @@ enum {
#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
-#define SP_ENABLE (1 << 31)
-#define SP_GAMMA_ENABLE (1 << 30)
-#define SP_PIXFORMAT_MASK (0xf << 26)
-#define SP_FORMAT_YUV422 (0x0 << 26)
-#define SP_FORMAT_8BPP (0x2 << 26)
-#define SP_FORMAT_BGR565 (0x5 << 26)
-#define SP_FORMAT_BGRX8888 (0x6 << 26)
-#define SP_FORMAT_BGRA8888 (0x7 << 26)
-#define SP_FORMAT_RGBX1010102 (0x8 << 26)
-#define SP_FORMAT_RGBA1010102 (0x9 << 26)
-#define SP_FORMAT_BGRX1010102 (0xa << 26) /* CHV pipe B */
-#define SP_FORMAT_BGRA1010102 (0xb << 26) /* CHV pipe B */
-#define SP_FORMAT_RGBX8888 (0xe << 26)
-#define SP_FORMAT_RGBA8888 (0xf << 26)
-#define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
-#define SP_SOURCE_KEY (1 << 22)
-#define SP_YUV_FORMAT_BT709 (1 << 18)
-#define SP_YUV_ORDER_MASK (3 << 16)
-#define SP_YUV_ORDER_YUYV (0 << 16)
-#define SP_YUV_ORDER_UYVY (1 << 16)
-#define SP_YUV_ORDER_YVYU (2 << 16)
-#define SP_YUV_ORDER_VYUY (3 << 16)
-#define SP_ROTATE_180 (1 << 15)
-#define SP_TILED (1 << 10)
-#define SP_MIRROR (1 << 8) /* CHV pipe B */
+#define SP_ENABLE REG_BIT(31)
+#define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define SP_FORMAT_MASK REG_GENMASK(29, 26)
+#define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0)
+#define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2)
+#define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5)
+#define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6)
+#define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7)
+#define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8)
+#define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9)
+#define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */
+#define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */
+#define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14)
+#define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15)
+#define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */
+#define SP_SOURCE_KEY REG_BIT(22)
+#define SP_YUV_FORMAT_BT709 REG_BIT(18)
+#define SP_YUV_ORDER_MASK REG_GENMASK(17, 16)
+#define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0)
+#define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1)
+#define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2)
+#define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3)
+#define SP_ROTATE_180 REG_BIT(15)
+#define SP_TILED REG_BIT(10)
+#define SP_MIRROR REG_BIT(8) /* CHV pipe B */
#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
+#define SP_POS_Y_MASK REG_GENMASK(31, 16)
+#define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y))
+#define SP_POS_X_MASK REG_GENMASK(15, 0)
+#define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x))
#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
+#define SP_HEIGHT_MASK REG_GENMASK(31, 16)
+#define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h))
+#define SP_WIDTH_MASK REG_GENMASK(15, 0)
+#define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w))
#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
+#define SP_ADDR_MASK REG_GENMASK(31, 12)
#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
+#define SP_OFFSET_Y_MASK REG_GENMASK(31, 16)
+#define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))
+#define SP_OFFSET_X_MASK REG_GENMASK(15, 0)
+#define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))
#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
-#define SP_CONST_ALPHA_ENABLE (1 << 31)
+#define SP_CONST_ALPHA_ENABLE REG_BIT(31)
+#define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
+#define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
-#define SP_CONTRAST(x) ((x) << 18) /* u3.6 */
-#define SP_BRIGHTNESS(x) ((x) & 0xff) /* s8 */
+#define SP_CONTRAST_MASK REG_GENMASK(26, 18)
+#define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
+#define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0)
+#define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */
#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
-#define SP_SH_SIN(x) (((x) & 0x7ff) << 16) /* s4.7 */
-#define SP_SH_COS(x) (x) /* u3.7 */
+#define SP_SH_SIN_MASK REG_GENMASK(26, 16)
+#define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */
+#define SP_SH_COS_MASK REG_GENMASK(9, 0)
+#define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */
#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
@@ -7238,28 +7257,36 @@ enum {
#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
-#define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
-#define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
+#define SPCSC_OOFF_MASK REG_GENMASK(26, 16)
+#define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
+#define SPCSC_IOFF_MASK REG_GENMASK(10, 0)
+#define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */
#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
-#define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
-#define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
+#define SPCSC_C1_MASK REG_GENMASK(30, 16)
+#define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */
+#define SPCSC_C0_MASK REG_GENMASK(14, 0)
+#define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */
#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
-#define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
-#define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
+#define SPCSC_IMAX_MASK REG_GENMASK(26, 16)
+#define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */
+#define SPCSC_IMIN_MASK REG_GENMASK(10, 0)
+#define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */
#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
-#define SPCSC_OMAX(x) ((x) << 16) /* u10 */
-#define SPCSC_OMIN(x) ((x) << 0) /* u10 */
+#define SPCSC_OMAX_MASK REG_GENMASK(25, 16)
+#define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */
+#define SPCSC_OMIN_MASK REG_GENMASK(9, 0)
+#define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */
/* Skylake plane registers */
--
2.32.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 10/14] drm/i915: Clean up g4x+ sprite plane registers
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
` (8 preceding siblings ...)
2021-12-01 15:25 ` [Intel-gfx] [PATCH 09/14] drm/i915: Clean up vlv/chv " Ville Syrjala
@ 2021-12-01 15:25 ` Ville Syrjala
2022-01-14 16:38 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 11/14] drm/i915: Clean up cursor registers Ville Syrjala
` (7 subsequent siblings)
17 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2021-12-01 15:25 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use REG_BIT() & co. to polish the g4x+ sprite plane registers.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 12 ++--
drivers/gpu/drm/i915/i915_reg.h | 73 +++++++++++++--------
2 files changed, 53 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index eb9ce96c030f..6f2a560700ce 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1054,7 +1054,7 @@ static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
u32 dvscntr = 0;
if (crtc_state->gamma_enable)
- dvscntr |= DVS_GAMMA_ENABLE;
+ dvscntr |= DVS_PIPE_GAMMA_ENABLE;
if (crtc_state->csc_enable)
dvscntr |= DVS_PIPE_CSC_ENABLE;
@@ -1206,14 +1206,18 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
unsigned long irqflags;
if (crtc_w != src_w || crtc_h != src_h)
- dvsscale = DVS_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
+ dvsscale = DVS_SCALE_ENABLE |
+ DVS_SRC_WIDTH(src_w - 1) |
+ DVS_SRC_HEIGHT(src_h - 1);
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
plane_state->view.color_plane[0].mapping_stride);
- intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x);
- intel_de_write_fw(dev_priv, DVSSIZE(pipe), ((crtc_h - 1) << 16) | (crtc_w - 1));
+ intel_de_write_fw(dev_priv, DVSPOS(pipe),
+ DVS_POS_Y(crtc_y) | DVS_POS_X(crtc_x));
+ intel_de_write_fw(dev_priv, DVSSIZE(pipe),
+ DVS_HEIGHT(crtc_h - 1) | DVS_WIDTH(crtc_w - 1));
intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4d61e7f2ee7c..d215cad95fe8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6970,46 +6970,63 @@ enum {
/* Sprite A control */
#define _DVSACNTR 0x72180
-#define DVS_ENABLE (1 << 31)
-#define DVS_GAMMA_ENABLE (1 << 30)
-#define DVS_YUV_RANGE_CORRECTION_DISABLE (1 << 27)
-#define DVS_PIXFORMAT_MASK (3 << 25)
-#define DVS_FORMAT_YUV422 (0 << 25)
-#define DVS_FORMAT_RGBX101010 (1 << 25)
-#define DVS_FORMAT_RGBX888 (2 << 25)
-#define DVS_FORMAT_RGBX161616 (3 << 25)
-#define DVS_PIPE_CSC_ENABLE (1 << 24)
-#define DVS_SOURCE_KEY (1 << 22)
-#define DVS_RGB_ORDER_XBGR (1 << 20)
-#define DVS_YUV_FORMAT_BT709 (1 << 18)
-#define DVS_YUV_ORDER_MASK (3 << 16)
-#define DVS_YUV_ORDER_YUYV (0 << 16)
-#define DVS_YUV_ORDER_UYVY (1 << 16)
-#define DVS_YUV_ORDER_YVYU (2 << 16)
-#define DVS_YUV_ORDER_VYUY (3 << 16)
-#define DVS_ROTATE_180 (1 << 15)
-#define DVS_DEST_KEY (1 << 2)
-#define DVS_TRICKLE_FEED_DISABLE (1 << 14)
-#define DVS_TILED (1 << 10)
+#define DVS_ENABLE REG_BIT(31)
+#define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
+#define DVS_FORMAT_MASK REG_GENMASK(26, 25)
+#define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
+#define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1)
+#define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
+#define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3)
+#define DVS_PIPE_CSC_ENABLE REG_BIT(24)
+#define DVS_SOURCE_KEY REG_BIT(22)
+#define DVS_RGB_ORDER_XBGR REG_BIT(20)
+#define DVS_YUV_FORMAT_BT709 REG_BIT(18)
+#define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16)
+#define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
+#define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
+#define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
+#define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
+#define DVS_ROTATE_180 REG_BIT(15)
+#define DVS_DEST_KEY REG_BIT(2)
+#define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
+#define DVS_TILED REG_BIT(10)
#define _DVSALINOFF 0x72184
#define _DVSASTRIDE 0x72188
#define _DVSAPOS 0x7218c
+#define DVS_POS_Y_MASK REG_GENMASK(31, 16)
+#define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
+#define DVS_POS_X_MASK REG_GENMASK(15, 0)
+#define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))
#define _DVSASIZE 0x72190
+#define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
+#define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
+#define DVS_WIDTH_MASK REG_GENMASK(15, 0)
+#define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
#define _DVSAKEYVAL 0x72194
#define _DVSAKEYMSK 0x72198
#define _DVSASURF 0x7219c
+#define DVS_ADDR_MASK REG_GENMASK(31, 12)
#define _DVSAKEYMAXVAL 0x721a0
#define _DVSATILEOFF 0x721a4
+#define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16)
+#define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
+#define DVS_OFFSET_X_MASK REG_GENMASK(15, 0)
+#define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
#define _DVSASURFLIVE 0x721ac
#define _DVSAGAMC_G4X 0x721e0 /* g4x */
#define _DVSASCALE 0x72204
-#define DVS_SCALE_ENABLE (1 << 31)
-#define DVS_FILTER_MASK (3 << 29)
-#define DVS_FILTER_MEDIUM (0 << 29)
-#define DVS_FILTER_ENHANCING (1 << 29)
-#define DVS_FILTER_SOFTENING (2 << 29)
-#define DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
-#define DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
+#define DVS_SCALE_ENABLE REG_BIT(31)
+#define DVS_FILTER_MASK REG_GENMASK(30, 29)
+#define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0)
+#define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1)
+#define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2)
+#define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
+#define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27)
+#define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16)
+#define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
+#define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
+#define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
#define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
--
2.32.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 11/14] drm/i915: Clean up cursor registers
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
` (9 preceding siblings ...)
2021-12-01 15:25 ` [Intel-gfx] [PATCH 10/14] drm/i915: Clean up g4x+ " Ville Syrjala
@ 2021-12-01 15:25 ` Ville Syrjala
2022-01-14 16:45 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 12/14] drm/i915: Extract skl_plane_aux_dist() Ville Syrjala
` (6 subsequent siblings)
17 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2021-12-01 15:25 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use REG_BIT() & co. to polish the cursor plane registers.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cursor.c | 25 ++++---
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 71 +++++++++++---------
3 files changed, 53 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 16d34685d83f..2ade8fdd9bdd 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -51,16 +51,16 @@ static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
u32 pos = 0;
if (x < 0) {
- pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
+ pos |= CURSOR_POS_X_SIGN;
x = -x;
}
- pos |= x << CURSOR_X_SHIFT;
+ pos |= CURSOR_POS_X(x);
if (y < 0) {
- pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
+ pos |= CURSOR_POS_Y_SIGN;
y = -y;
}
- pos |= y << CURSOR_Y_SHIFT;
+ pos |= CURSOR_POS_Y(y);
return pos;
}
@@ -180,7 +180,7 @@ static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
u32 cntl = 0;
if (crtc_state->gamma_enable)
- cntl |= CURSOR_GAMMA_ENABLE;
+ cntl |= CURSOR_PIPE_GAMMA_ENABLE;
return cntl;
}
@@ -264,7 +264,7 @@ static void i845_cursor_update_arm(struct intel_plane *plane,
cntl = plane_state->ctl |
i845_cursor_ctl_crtc(crtc_state);
- size = (height << 12) | width;
+ size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width);
base = intel_cursor_base(plane_state);
pos = intel_cursor_position(plane_state);
@@ -280,7 +280,7 @@ static void i845_cursor_update_arm(struct intel_plane *plane,
plane->cursor.cntl != cntl) {
intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
- intel_de_write_fw(dev_priv, CURSIZE, size);
+ intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
@@ -340,13 +340,13 @@ static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
return cntl;
if (crtc_state->gamma_enable)
- cntl = MCURSOR_GAMMA_ENABLE;
+ cntl = MCURSOR_PIPE_GAMMA_ENABLE;
if (crtc_state->csc_enable)
cntl |= MCURSOR_PIPE_CSC_ENABLE;
if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
- cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
+ cntl |= MCURSOR_PIPE_SEL(crtc->pipe);
return cntl;
}
@@ -502,7 +502,7 @@ static void i9xx_cursor_update_arm(struct intel_plane *plane,
i9xx_cursor_ctl_crtc(crtc_state);
if (width != height)
- fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
+ fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1);
base = intel_cursor_base(plane_state);
pos = intel_cursor_position(plane_state);
@@ -586,13 +586,12 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
- ret = val & MCURSOR_MODE;
+ ret = val & MCURSOR_MODE_MASK;
if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
*pipe = plane->pipe;
else
- *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
- MCURSOR_PIPE_SELECT_SHIFT;
+ *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);
intel_display_power_put(dev_priv, power_domain, wakeref);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 00a2c9915780..34c1463e2ef9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10041,9 +10041,9 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
drm_WARN_ON(&dev_priv->drm,
intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DSP_ENABLE);
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
+ intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
+ intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
intel_de_write(dev_priv, PIPECONF(pipe), 0);
intel_de_posting_read(dev_priv, PIPECONF(pipe));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d215cad95fe8..e010add5574a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6761,44 +6761,50 @@ enum {
/* Cursor A & B regs */
#define _CURACNTR 0x70080
/* Old style CUR*CNTR flags (desktop 8xx) */
-#define CURSOR_ENABLE 0x80000000
-#define CURSOR_GAMMA_ENABLE 0x40000000
-#define CURSOR_STRIDE_SHIFT 28
-#define CURSOR_STRIDE(x) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
-#define CURSOR_FORMAT_SHIFT 24
-#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
-#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
-#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
-#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
-#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
-#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
+#define CURSOR_ENABLE REG_BIT(31)
+#define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define CURSOR_STRIDE_MASK REG_GENMASK(29, 28)
+#define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */
+#define CURSOR_FORMAT_MASK REG_GENMASK(26, 24)
+#define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0)
+#define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1)
+#define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2)
+#define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4)
+#define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5)
/* New style CUR*CNTR flags */
-#define MCURSOR_MODE 0x27
-#define MCURSOR_MODE_DISABLE 0x00
-#define MCURSOR_MODE_128_32B_AX 0x02
-#define MCURSOR_MODE_256_32B_AX 0x03
-#define MCURSOR_MODE_64_32B_AX 0x07
-#define MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
-#define MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
-#define MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
#define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
#define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */
-#define MCURSOR_PIPE_SELECT_MASK (0x3 << 28)
-#define MCURSOR_PIPE_SELECT_SHIFT 28
-#define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)
-#define MCURSOR_GAMMA_ENABLE (1 << 26)
-#define MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
-#define MCURSOR_ROTATE_180 (1 << 15)
-#define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14)
+#define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28)
+#define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe))
+#define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26)
+#define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
+#define MCURSOR_ROTATE_180 REG_BIT(15)
+#define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14)
+#define MCURSOR_MODE_MASK 0x27
+#define MCURSOR_MODE_DISABLE 0x00
+#define MCURSOR_MODE_128_32B_AX 0x02
+#define MCURSOR_MODE_256_32B_AX 0x03
+#define MCURSOR_MODE_64_32B_AX 0x07
+#define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX)
+#define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX)
+#define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX)
#define _CURABASE 0x70084
#define _CURAPOS 0x70088
-#define CURSOR_POS_MASK 0x007FF
-#define CURSOR_POS_SIGN 0x8000
-#define CURSOR_X_SHIFT 0
-#define CURSOR_Y_SHIFT 16
-#define CURSIZE _MMIO(0x700a0) /* 845/865 */
+#define CURSOR_POS_Y_SIGN REG_BIT(31)
+#define CURSOR_POS_Y_MASK REG_GENMASK(30, 16)
+#define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))
+#define CURSOR_POS_X_SIGN REG_BIT(15)
+#define CURSOR_POS_X_MASK REG_GENMASK(14, 0)
+#define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))
+#define _CURASIZE 0x700a0 /* 845/865 */
+#define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12)
+#define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))
+#define CURSOR_WIDTH_MASK REG_GENMASK(9, 0)
+#define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))
#define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
-#define CUR_FBC_CTL_EN (1 << 31)
+#define CUR_FBC_EN REG_BIT(31)
+#define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0)
+#define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))
#define _CURASURFLIVE 0x700ac /* g4x+ */
#define _CURBCNTR 0x700c0
#define _CURBBASE 0x700c4
@@ -6811,6 +6817,7 @@ enum {
#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
+#define CURSIZE(pipe) _CURSOR2(pipe, _CURASIZE)
#define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
#define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
--
2.32.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 12/14] drm/i915: Extract skl_plane_aux_dist()
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
` (10 preceding siblings ...)
2021-12-01 15:25 ` [Intel-gfx] [PATCH 11/14] drm/i915: Clean up cursor registers Ville Syrjala
@ 2021-12-01 15:25 ` Ville Syrjala
2021-12-01 17:28 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 13/14] drm/i915: Declutter color key register stuff Ville Syrjala
` (5 subsequent siblings)
17 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2021-12-01 15:25 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Extract the PLANE_AUX_DIST stuff into a small helper to
dclutter skl_program_plane_arm() a bit.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/skl_universal_plane.c | 35 ++++++++++++-------
1 file changed, 23 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 79998eb67280..c7de643d16dd 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -981,6 +981,26 @@ static u32 skl_plane_surf(const struct intel_plane_state *plane_state,
return plane_surf;
}
+static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state,
+ int color_plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ int aux_plane = skl_main_to_aux_plane(fb, color_plane);
+ u32 aux_dist;
+
+ if (!aux_plane)
+ return 0;
+
+ aux_dist = skl_surf_address(plane_state, aux_plane) -
+ skl_surf_address(plane_state, color_plane);
+
+ if (DISPLAY_VER(i915) < 12)
+ aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));
+
+ return aux_dist;
+}
+
static void icl_plane_csc_load_black(struct intel_plane *plane)
{
struct drm_i915_private *i915 = to_i915(plane->base.dev);
@@ -1075,11 +1095,9 @@ skl_program_plane_arm(struct intel_plane *plane,
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
- const struct drm_framebuffer *fb = plane_state->hw.fb;
- int aux_plane = skl_main_to_aux_plane(fb, color_plane);
u32 x = plane_state->view.color_plane[color_plane].x;
u32 y = plane_state->view.color_plane[color_plane].y;
- u32 keymsk, keymax, aux_dist = 0, plane_color_ctl = 0;
+ u32 keymsk, keymax, plane_color_ctl = 0;
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_ctl = plane_state->ctl;
unsigned long irqflags;
@@ -1096,14 +1114,6 @@ skl_program_plane_arm(struct intel_plane *plane,
if (alpha < 0xff)
keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
- if (aux_plane) {
- aux_dist = skl_surf_address(plane_state, aux_plane) -
- skl_surf_address(plane_state, color_plane);
-
- if (DISPLAY_VER(dev_priv) < 12)
- aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));
- }
-
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
@@ -1114,7 +1124,8 @@ skl_program_plane_arm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
- intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
+ intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
+ skl_plane_aux_dist(plane_state, color_plane));
if (DISPLAY_VER(dev_priv) < 11)
intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
--
2.32.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 13/14] drm/i915: Declutter color key register stuff
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
` (11 preceding siblings ...)
2021-12-01 15:25 ` [Intel-gfx] [PATCH 12/14] drm/i915: Extract skl_plane_aux_dist() Ville Syrjala
@ 2021-12-01 15:25 ` Ville Syrjala
2021-12-01 17:31 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 14/14] drm/i915: Nuke pointless middle men for skl+ plane programming Ville Syrjala
` (4 subsequent siblings)
17 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2021-12-01 15:25 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add a few small helpers to calculate the color key register
values. Cleans up skl_program_plane_arm() a bit.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/skl_universal_plane.c | 45 +++++++++++++------
1 file changed, 32 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index c7de643d16dd..92270679a99c 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1001,6 +1001,34 @@ static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state,
return aux_dist;
}
+static u32 skl_plane_keyval(const struct intel_plane_state *plane_state)
+{
+ const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
+
+ return key->min_value;
+}
+
+static u32 skl_plane_keymax(const struct intel_plane_state *plane_state)
+{
+ const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
+ u8 alpha = plane_state->hw.alpha >> 8;
+
+ return (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
+}
+
+static u32 skl_plane_keymsk(const struct intel_plane_state *plane_state)
+{
+ const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
+ u8 alpha = plane_state->hw.alpha >> 8;
+ u32 keymsk;
+
+ keymsk = key->channel_mask & 0x7ffffff;
+ if (alpha < 0xff)
+ keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
+
+ return keymsk;
+}
+
static void icl_plane_csc_load_black(struct intel_plane *plane)
{
struct drm_i915_private *i915 = to_i915(plane->base.dev);
@@ -1094,11 +1122,9 @@ skl_program_plane_arm(struct intel_plane *plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
- const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
u32 x = plane_state->view.color_plane[color_plane].x;
u32 y = plane_state->view.color_plane[color_plane].y;
- u32 keymsk, keymax, plane_color_ctl = 0;
- u8 alpha = plane_state->hw.alpha >> 8;
+ u32 plane_color_ctl = 0;
u32 plane_ctl = plane_state->ctl;
unsigned long irqflags;
@@ -1108,18 +1134,11 @@ skl_program_plane_arm(struct intel_plane *plane,
plane_color_ctl = plane_state->color_ctl |
glk_plane_color_ctl_crtc(crtc_state);
- keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
-
- keymsk = key->channel_mask & 0x7ffffff;
- if (alpha < 0xff)
- keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
-
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
- intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
- key->min_value);
- intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk);
- intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), keymax);
+ intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state));
+ intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state));
+ intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state));
intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
--
2.32.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] [PATCH 14/14] drm/i915: Nuke pointless middle men for skl+ plane programming
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
` (12 preceding siblings ...)
2021-12-01 15:25 ` [Intel-gfx] [PATCH 13/14] drm/i915: Declutter color key register stuff Ville Syrjala
@ 2021-12-01 15:25 ` Ville Syrjala
2021-12-01 17:32 ` Souza, Jose
2021-12-01 18:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanup Patchwork
` (3 subsequent siblings)
17 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2021-12-01 15:25 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
There is no real point in having this two stage
skl_program_plane*() vs. skl_plane_update*() wrapper stuff.
All we need to do is determine the correct color plane and
we're done.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/skl_universal_plane.c | 53 ++++++-------------
1 file changed, 17 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 92270679a99c..de2708ac1802 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1053,15 +1053,24 @@ static void icl_plane_csc_load_black(struct intel_plane *plane)
intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);
}
+static int skl_plane_color_plane(const struct intel_plane_state *plane_state)
+{
+ /* Program the UV plane on planar master */
+ if (plane_state->planar_linked_plane && !plane_state->planar_slave)
+ return 1;
+ else
+ return 0;
+}
+
static void
-skl_program_plane_noarm(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state,
- int color_plane)
+skl_plane_update_noarm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
+ int color_plane = skl_plane_color_plane(plane_state);
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
int crtc_x = plane_state->uapi.dst.x1;
@@ -1114,14 +1123,14 @@ skl_program_plane_noarm(struct intel_plane *plane,
}
static void
-skl_program_plane_arm(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state,
- int color_plane)
+skl_plane_update_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
+ int color_plane = skl_plane_color_plane(plane_state);
u32 x = plane_state->view.color_plane[color_plane].x;
u32 y = plane_state->view.color_plane[color_plane].y;
u32 plane_color_ctl = 0;
@@ -1202,34 +1211,6 @@ skl_plane_async_flip(struct intel_plane *plane,
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
-static void
-skl_plane_update_noarm(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
-{
- int color_plane = 0;
-
- if (plane_state->planar_linked_plane && !plane_state->planar_slave)
- /* Program the UV plane on planar master */
- color_plane = 1;
-
- skl_program_plane_noarm(plane, crtc_state, plane_state, color_plane);
-}
-
-static void
-skl_plane_update_arm(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
-{
- int color_plane = 0;
-
- if (plane_state->planar_linked_plane && !plane_state->planar_slave)
- /* Program the UV plane on planar master */
- color_plane = 1;
-
- skl_program_plane_arm(plane, crtc_state, plane_state, color_plane);
-}
-
static bool intel_format_is_p01x(u32 format)
{
switch (format) {
--
2.32.0
^ permalink raw reply related [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 01/14] drm/i915: Get rid of the 64bit PLANE_CC_VAL mmio
2021-12-01 15:25 ` [Intel-gfx] [PATCH 01/14] drm/i915: Get rid of the 64bit PLANE_CC_VAL mmio Ville Syrjala
@ 2021-12-01 17:13 ` Souza, Jose
0 siblings, 0 replies; 48+ messages in thread
From: Souza, Jose @ 2021-12-01 17:13 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Let's just stick to 32bit mmio accesses so we can get rid
> of the bare "uncore" reg access in display code. The register
> are defined as 32bit in the spec anyway.
>
> We could define a 64bit "de" variant I suppose, but doesn't
> really make much sense just for this one case, and when we
> start to use the DSB for this stuff we'd also need another
> 64bit variant for that. Just easier to do 32bit always.
>
> While at it we can reorder stuff a bit so that we write the
> registers in order of increasing offset (more or less).
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 11 +++++++----
> drivers/gpu/drm/i915/i915_reg.h | 12 ++++++------
> 2 files changed, 13 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 28890876bdeb..845b99844ec6 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1047,6 +1047,13 @@ skl_program_plane_noarm(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
> (src_h << 16) | src_w);
>
> + if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
> + intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
> + lower_32_bits(plane_state->ccval));
> + intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 1),
> + upper_32_bits(plane_state->ccval));
> + }
> +
> if (icl_is_hdr_plane(dev_priv, plane_id))
> intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
> plane_state->cus_ctl);
> @@ -1054,10 +1061,6 @@ skl_program_plane_noarm(struct intel_plane *plane,
> if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
> icl_program_input_csc(plane, crtc_state, plane_state);
>
> - if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier))
> - intel_uncore_write64_fw(&dev_priv->uncore,
> - PLANE_CC_VAL(pipe, plane_id), plane_state->ccval);
> -
> skl_write_plane_wm(plane, crtc_state);
>
> intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3450818802c2..3c0471f20e53 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7363,12 +7363,12 @@ enum {
> #define _PLANE_NV12_BUF_CFG_1_A 0x70278
> #define _PLANE_NV12_BUF_CFG_2_A 0x70378
>
> -#define _PLANE_CC_VAL_1_B 0x711b4
> -#define _PLANE_CC_VAL_2_B 0x712b4
> -#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
> -#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
> -#define PLANE_CC_VAL(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
> +#define _PLANE_CC_VAL_1_B 0x711b4
> +#define _PLANE_CC_VAL_2_B 0x712b4
> +#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
> +#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
> +#define PLANE_CC_VAL(pipe, plane, dw) \
> + _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
>
> /* Input CSC Register Definitions */
> #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 02/14] drm/i915: Rename plane YUV order bits
2021-12-01 15:25 ` [Intel-gfx] [PATCH 02/14] drm/i915: Rename plane YUV order bits Ville Syrjala
@ 2021-12-01 17:14 ` Souza, Jose
2021-12-02 11:53 ` Ville Syrjälä
2021-12-06 13:13 ` kernel test robot
1 sibling, 1 reply; 48+ messages in thread
From: Souza, Jose @ 2021-12-01 17:14 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename the YUV byte order bits to be a bit more consistent.
Why rename bits not used? Would be better already nuke it.
Anyways up to you.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 8 ++++----
> drivers/gpu/drm/i915/i915_reg.h | 14 +++++++-------
> 2 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 845b99844ec6..9ff24a0e79b4 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -672,13 +672,13 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
> case DRM_FORMAT_XYUV8888:
> return PLANE_CTL_FORMAT_XYUV;
> case DRM_FORMAT_YUYV:
> - return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
> + return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YUYV;
> case DRM_FORMAT_YVYU:
> - return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
> + return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YVYU;
> case DRM_FORMAT_UYVY:
> - return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
> + return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_UYVY;
> case DRM_FORMAT_VYUY:
> - return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
> + return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_VYUY;
> case DRM_FORMAT_NV12:
> return PLANE_CTL_FORMAT_NV12;
> case DRM_FORMAT_P010:
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3c0471f20e53..02d8db03c0bf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6966,7 +6966,7 @@ enum {
> #define DVS_SOURCE_KEY (1 << 22)
> #define DVS_RGB_ORDER_XBGR (1 << 20)
> #define DVS_YUV_FORMAT_BT709 (1 << 18)
> -#define DVS_YUV_BYTE_ORDER_MASK (3 << 16)
> +#define DVS_YUV_ORDER_MASK (3 << 16)
> #define DVS_YUV_ORDER_YUYV (0 << 16)
> #define DVS_YUV_ORDER_UYVY (1 << 16)
> #define DVS_YUV_ORDER_YVYU (2 << 16)
> @@ -7045,7 +7045,7 @@ enum {
> #define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and 161616 */
> #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)
> #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */
> -#define SPRITE_YUV_BYTE_ORDER_MASK (3 << 16)
> +#define SPRITE_YUV_ORDER_MASK (3 << 16)
> #define SPRITE_YUV_ORDER_YUYV (0 << 16)
> #define SPRITE_YUV_ORDER_UYVY (1 << 16)
> #define SPRITE_YUV_ORDER_YVYU (2 << 16)
> @@ -7130,7 +7130,7 @@ enum {
> #define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
> #define SP_SOURCE_KEY (1 << 22)
> #define SP_YUV_FORMAT_BT709 (1 << 18)
> -#define SP_YUV_BYTE_ORDER_MASK (3 << 16)
> +#define SP_YUV_ORDER_MASK (3 << 16)
> #define SP_YUV_ORDER_YUYV (0 << 16)
> #define SP_YUV_ORDER_UYVY (1 << 16)
> #define SP_YUV_ORDER_YVYU (2 << 16)
> @@ -7271,10 +7271,10 @@ enum {
> #define PLANE_CTL_YUV420_Y_PLANE (1 << 19)
> #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
> #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
> -#define PLANE_CTL_YUV422_YUYV (0 << 16)
> -#define PLANE_CTL_YUV422_UYVY (1 << 16)
> -#define PLANE_CTL_YUV422_YVYU (2 << 16)
> -#define PLANE_CTL_YUV422_VYUY (3 << 16)
> +#define PLANE_CTL_YUV422_ORDER_YUYV (0 << 16)
> +#define PLANE_CTL_YUV422_ORDER_UYVY (1 << 16)
> +#define PLANE_CTL_YUV422_ORDER_YVYU (2 << 16)
> +#define PLANE_CTL_YUV422_ORDER_VYUY (3 << 16)
> #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
> #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
> #define PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13) /* TGL+ */
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 05/14] drm/i915: Rename PLANE_CUS_CTL Y plane bits
2021-12-01 15:25 ` [Intel-gfx] [PATCH 05/14] drm/i915: Rename PLANE_CUS_CTL Y plane bits Ville Syrjala
@ 2021-12-01 17:17 ` Souza, Jose
0 siblings, 0 replies; 48+ messages in thread
From: Souza, Jose @ 2021-12-01 17:17 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename the PLANE_CUS_CTL Y plane selection bits to actually
> say "Y plane".
>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 8 ++++----
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index badf035efaeb..726c1552c9bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5159,13 +5159,13 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
>
> if (icl_is_hdr_plane(dev_priv, plane->id)) {
> if (linked->id == PLANE_SPRITE5)
> - plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
> + plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
> else if (linked->id == PLANE_SPRITE4)
> - plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
> + plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
> else if (linked->id == PLANE_SPRITE3)
> - plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
> + plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
> else if (linked->id == PLANE_SPRITE2)
> - plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
> + plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
> else
> MISSING_CASE(linked->id);
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6066b1e2763c..4b2bc17d0235 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7328,10 +7328,10 @@ enum {
> #define _PLANE_CUS_CTL_1_A 0x701c8
> #define _PLANE_CUS_CTL_2_A 0x702c8
> #define PLANE_CUS_ENABLE (1 << 31)
> -#define PLANE_CUS_PLANE_4_RKL (0 << 30)
> -#define PLANE_CUS_PLANE_5_RKL (1 << 30)
> -#define PLANE_CUS_PLANE_6 (0 << 30)
> -#define PLANE_CUS_PLANE_7 (1 << 30)
> +#define PLANE_CUS_Y_PLANE_4_RKL (0 << 30)
> +#define PLANE_CUS_Y_PLANE_5_RKL (1 << 30)
> +#define PLANE_CUS_Y_PLANE_6_ICL (0 << 30)
> +#define PLANE_CUS_Y_PLANE_7_ICL (1 << 30)
> #define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19)
> #define PLANE_CUS_HPHASE_0 (0 << 16)
> #define PLANE_CUS_HPHASE_0_25 (1 << 16)
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 03/14] drm/i915: Get rid of the "sizes are 0 based" stuff
2021-12-01 15:25 ` [Intel-gfx] [PATCH 03/14] drm/i915: Get rid of the "sizes are 0 based" stuff Ville Syrjala
@ 2021-12-01 17:18 ` Souza, Jose
2021-12-02 11:56 ` Ville Syrjälä
0 siblings, 1 reply; 48+ messages in thread
From: Souza, Jose @ 2021-12-01 17:18 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Replace the "sizes are 0 based" stuff with just straight
> up -1 where needed. Less confusing all around.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 26 ++++---------------
> .../drm/i915/display/skl_universal_plane.c | 6 +----
> 2 files changed, 6 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 1b99a9501a45..2067a7bca4a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -431,10 +431,6 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
> u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
> unsigned long irqflags;
>
> - /* Sizes are 0 based */
In my opinion at least this comment should stay, helps understand why the -1.
> - crtc_w--;
> - crtc_h--;
> -
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
> @@ -442,7 +438,7 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),
> (crtc_y << 16) | crtc_x);
> intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
> - (crtc_h << 16) | crtc_w);
> + ((crtc_h - 1) << 16) | (crtc_w - 1));
>
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
> @@ -866,21 +862,15 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
> u32 sprscale = 0;
> unsigned long irqflags;
>
> - /* Sizes are 0 based */
> - src_w--;
> - src_h--;
> - crtc_w--;
> - crtc_h--;
> -
> if (crtc_w != src_w || crtc_h != src_h)
> - sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
> + sprscale = SPRITE_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
>
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
> plane_state->view.color_plane[0].mapping_stride);
> intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x);
> - intel_de_write_fw(dev_priv, SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
> + intel_de_write_fw(dev_priv, SPRSIZE(pipe), ((crtc_h - 1) << 16) | (crtc_w - 1));
> if (IS_IVYBRIDGE(dev_priv))
> intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
>
> @@ -1208,21 +1198,15 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
> u32 dvsscale = 0;
> unsigned long irqflags;
>
> - /* Sizes are 0 based */
> - src_w--;
> - src_h--;
> - crtc_w--;
> - crtc_h--;
> -
> if (crtc_w != src_w || crtc_h != src_h)
> - dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
> + dvsscale = DVS_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
>
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
> plane_state->view.color_plane[0].mapping_stride);
> intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x);
> - intel_de_write_fw(dev_priv, DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
> + intel_de_write_fw(dev_priv, DVSSIZE(pipe), ((crtc_h - 1) << 16) | (crtc_w - 1));
> intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
>
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 9ff24a0e79b4..09948922016b 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1022,10 +1022,6 @@ skl_program_plane_noarm(struct intel_plane *plane,
> u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> unsigned long irqflags;
>
> - /* Sizes are 0 based */
> - src_w--;
> - src_h--;
> -
> /* The scaler will handle the output position */
> if (plane_state->scaler_id >= 0) {
> crtc_x = 0;
> @@ -1045,7 +1041,7 @@ skl_program_plane_noarm(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
> (crtc_y << 16) | crtc_x);
> intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
> - (src_h << 16) | src_w);
> + ((src_h - 1) << 16) | (src_w - 1));
>
> if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
> intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 06/14] drm/i915: Use REG_BIT() & co. for universal plane bits
2021-12-01 15:25 ` [Intel-gfx] [PATCH 06/14] drm/i915: Use REG_BIT() & co. for universal " Ville Syrjala
@ 2021-12-01 17:26 ` Souza, Jose
2021-12-02 11:57 ` Ville Syrjälä
2021-12-06 15:57 ` kernel test robot
1 sibling, 1 reply; 48+ messages in thread
From: Souza, Jose @ 2021-12-01 17:26 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Polish the skl+ universal plane register defines by
> using REG_BIT() & co.
>
> The defines are also currently spread around in some
> semi-random fashion. Collect them up into one place.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> .../drm/i915/display/skl_universal_plane.c | 36 ++--
> drivers/gpu/drm/i915/gvt/reg.h | 1 -
> drivers/gpu/drm/i915/i915_reg.h | 197 ++++++++++--------
> drivers/gpu/drm/i915/intel_pm.c | 12 +-
> 4 files changed, 135 insertions(+), 111 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 984bb35ecf06..79998eb67280 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1037,11 +1037,12 @@ skl_program_plane_noarm(struct intel_plane *plane,
> if (plane_state->force_black)
> icl_plane_csc_load_black(plane);
>
> - intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), stride);
> + intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
> + PLANE_STRIDE_(stride));
> intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
> - (crtc_y << 16) | crtc_x);
> + PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
> intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
> - ((src_h - 1) << 16) | (src_w - 1));
> + PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
>
> if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
> intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
> @@ -1100,7 +1101,7 @@ skl_program_plane_arm(struct intel_plane *plane,
> skl_surf_address(plane_state, color_plane);
>
> if (DISPLAY_VER(dev_priv) < 12)
> - aux_dist |= skl_plane_stride(plane_state, aux_plane);
> + aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));
> }
>
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> @@ -1111,14 +1112,14 @@ skl_program_plane_arm(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), keymax);
>
> intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
> - (y << 16) | x);
> + PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
>
> intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
>
> if (DISPLAY_VER(dev_priv) < 11)
> intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
> - (plane_state->view.color_plane[1].y << 16) |
> - plane_state->view.color_plane[1].x);
> + PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) |
> + PLANE_OFFSET_X(plane_state->view.color_plane[1].x));
>
> if (DISPLAY_VER(dev_priv) >= 10)
> intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
> @@ -2262,16 +2263,17 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
>
> if (DISPLAY_VER(dev_priv) >= 11)
> - pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
> + pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL;
Most of our platform bits definition follows <platform or display ver>_<register name>.
Other than that the idea looks good to me.
> else
> - pixel_format = val & PLANE_CTL_FORMAT_MASK;
> + pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL;
>
> if (DISPLAY_VER(dev_priv) >= 10) {
> - alpha = intel_de_read(dev_priv,
> - PLANE_COLOR_CTL(pipe, plane_id));
> - alpha &= PLANE_COLOR_ALPHA_MASK;
> + u32 color_ctl;
> +
> + color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe, plane_id));
> + alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl);
> } else {
> - alpha = val & PLANE_CTL_ALPHA_MASK;
> + alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val);
> }
>
> fourcc = skl_format_to_fourcc(pixel_format,
> @@ -2335,19 +2337,19 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> if (drm_rotation_90_or_270(plane_config->rotation))
> goto error;
>
> - base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
> + base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK;
> plane_config->base = base;
>
> offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
>
> val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
> - fb->height = ((val >> 16) & 0xffff) + 1;
> - fb->width = ((val >> 0) & 0xffff) + 1;
> + fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1;
> + fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1;
>
> val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
> stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
>
> - fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
> + fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult;
>
> aligned_height = intel_fb_align_height(fb, 0, fb->height);
>
> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
> index 244cc7320b54..7d666d34f9ff 100644
> --- a/drivers/gpu/drm/i915/gvt/reg.h
> +++ b/drivers/gpu/drm/i915/gvt/reg.h
> @@ -62,7 +62,6 @@
>
> #define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe))
>
> -#define PLANE_CTL_ASYNC_FLIP (1 << 9)
> #define REG50080_FLIP_TYPE_MASK 0x3
> #define REG50080_FLIP_TYPE_ASYNC 0x1
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4b2bc17d0235..9fffa2392bbf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7233,84 +7233,99 @@ enum {
> #define _PLANE_CTL_1_A 0x70180
> #define _PLANE_CTL_2_A 0x70280
> #define _PLANE_CTL_3_A 0x70380
> -#define PLANE_CTL_ENABLE (1 << 31)
> +#define PLANE_CTL_ENABLE REG_BIT(31)
> #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
> #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
> -#define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
> -#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
> +#define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
> +#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
> /*
> * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
> * expanded to include bit 23 as well. However, the shift-24 based values
> * correctly map to the same formats in ICL, as long as bit 23 is set to 0
> */
> -#define PLANE_CTL_FORMAT_MASK (0xf << 24)
> -#define PLANE_CTL_FORMAT_YUV422 (0 << 24)
> -#define PLANE_CTL_FORMAT_NV12 (1 << 24)
> -#define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
> -#define PLANE_CTL_FORMAT_P010 (3 << 24)
> -#define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24)
> -#define PLANE_CTL_FORMAT_P012 (5 << 24)
> -#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
> -#define PLANE_CTL_FORMAT_P016 (7 << 24)
> -#define PLANE_CTL_FORMAT_XYUV (8 << 24)
> -#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
> -#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
> -#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
> -#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
> -#define PLANE_CTL_FORMAT_Y210 (1 << 23)
> -#define PLANE_CTL_FORMAT_Y212 (3 << 23)
> -#define PLANE_CTL_FORMAT_Y216 (5 << 23)
> -#define PLANE_CTL_FORMAT_Y410 (7 << 23)
> -#define PLANE_CTL_FORMAT_Y412 (9 << 23)
> -#define PLANE_CTL_FORMAT_Y416 (0xb << 23)
> -#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
> -#define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
> -#define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
> -#define PLANE_CTL_ORDER_BGRX (0 << 20)
> -#define PLANE_CTL_ORDER_RGBX (1 << 20)
> -#define PLANE_CTL_YUV420_Y_PLANE (1 << 19)
> -#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
> -#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
> -#define PLANE_CTL_YUV422_ORDER_YUYV (0 << 16)
> -#define PLANE_CTL_YUV422_ORDER_UYVY (1 << 16)
> -#define PLANE_CTL_YUV422_ORDER_YVYU (2 << 16)
> -#define PLANE_CTL_YUV422_ORDER_VYUY (3 << 16)
> -#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
> -#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
> -#define PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13) /* TGL+ */
> -#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
> -#define PLANE_CTL_TILED_MASK (0x7 << 10)
> -#define PLANE_CTL_TILED_LINEAR (0 << 10)
> -#define PLANE_CTL_TILED_X (1 << 10)
> -#define PLANE_CTL_TILED_Y (4 << 10)
> -#define PLANE_CTL_TILED_YF (5 << 10)
> -#define PLANE_CTL_ASYNC_FLIP (1 << 9)
> -#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> -#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> -#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
> -#define PLANE_CTL_ALPHA_DISABLE (0 << 4)
> -#define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
> -#define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4)
> -#define PLANE_CTL_ROTATE_MASK 0x3
> -#define PLANE_CTL_ROTATE_0 0x0
> -#define PLANE_CTL_ROTATE_90 0x1
> -#define PLANE_CTL_ROTATE_180 0x2
> -#define PLANE_CTL_ROTATE_270 0x3
> +#define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */
> +#define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */
> +#define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
> +#define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1)
> +#define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2)
> +#define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3)
> +#define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4)
> +#define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5)
> +#define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6)
> +#define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7)
> +#define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8)
> +#define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12)
> +#define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14)
> +#define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1)
> +#define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3)
> +#define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5)
> +#define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7)
> +#define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9)
> +#define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11)
> +#define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
> +#define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21)
> +#define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1)
> +#define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2)
> +#define PLANE_CTL_ORDER_RGBX REG_BIT(20)
> +#define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19)
> +#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18)
> +#define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16)
> +#define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)
> +#define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1)
> +#define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2)
> +#define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3)
> +#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15)
> +#define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14)
> +#define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
> +#define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
> +#define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10)
> +#define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0)
> +#define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1)
> +#define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4)
> +#define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
> +#define PLANE_CTL_ASYNC_FLIP REG_BIT(9)
> +#define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8)
> +#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
> +#define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
> +#define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0)
> +#define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2)
> +#define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3)
> +#define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0)
> +#define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0)
> +#define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
> +#define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
> +#define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
> #define _PLANE_STRIDE_1_A 0x70188
> #define _PLANE_STRIDE_2_A 0x70288
> #define _PLANE_STRIDE_3_A 0x70388
> +#define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
> +#define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
> #define _PLANE_POS_1_A 0x7018c
> #define _PLANE_POS_2_A 0x7028c
> #define _PLANE_POS_3_A 0x7038c
> +#define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
> +#define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
> +#define PLANE_POS_X_MASK REG_GENMASK(15, 0)
> +#define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
> #define _PLANE_SIZE_1_A 0x70190
> #define _PLANE_SIZE_2_A 0x70290
> #define _PLANE_SIZE_3_A 0x70390
> +#define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
> +#define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
> +#define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
> +#define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
> #define _PLANE_SURF_1_A 0x7019c
> #define _PLANE_SURF_2_A 0x7029c
> #define _PLANE_SURF_3_A 0x7039c
> +#define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
> +#define PLANE_SURF_DECRYPT REG_BIT(2)
> #define _PLANE_OFFSET_1_A 0x701a4
> #define _PLANE_OFFSET_2_A 0x702a4
> #define _PLANE_OFFSET_3_A 0x703a4
> +#define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
> +#define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
> +#define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
> +#define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))
> #define _PLANE_KEYVAL_1_A 0x70194
> #define _PLANE_KEYVAL_2_A 0x70294
> #define _PLANE_KEYMSK_1_A 0x70198
> @@ -7322,42 +7337,49 @@ enum {
> #define _PLANE_CC_VAL_1_A 0x701b4
> #define _PLANE_CC_VAL_2_A 0x702b4
> #define _PLANE_AUX_DIST_1_A 0x701c0
> +#define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
> +#define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
> +#define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
> #define _PLANE_AUX_DIST_2_A 0x702c0
> #define _PLANE_AUX_OFFSET_1_A 0x701c4
> #define _PLANE_AUX_OFFSET_2_A 0x702c4
> #define _PLANE_CUS_CTL_1_A 0x701c8
> #define _PLANE_CUS_CTL_2_A 0x702c8
> -#define PLANE_CUS_ENABLE (1 << 31)
> -#define PLANE_CUS_Y_PLANE_4_RKL (0 << 30)
> -#define PLANE_CUS_Y_PLANE_5_RKL (1 << 30)
> -#define PLANE_CUS_Y_PLANE_6_ICL (0 << 30)
> -#define PLANE_CUS_Y_PLANE_7_ICL (1 << 30)
> -#define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19)
> -#define PLANE_CUS_HPHASE_0 (0 << 16)
> -#define PLANE_CUS_HPHASE_0_25 (1 << 16)
> -#define PLANE_CUS_HPHASE_0_5 (2 << 16)
> -#define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15)
> -#define PLANE_CUS_VPHASE_0 (0 << 12)
> -#define PLANE_CUS_VPHASE_0_25 (1 << 12)
> -#define PLANE_CUS_VPHASE_0_5 (2 << 12)
> +#define PLANE_CUS_ENABLE REG_BIT(31)
> +#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
> +#define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
> +#define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
> +#define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
> +#define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
> +#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
> +#define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16)
> +#define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
> +#define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
> +#define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
> +#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
> +#define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12)
> +#define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
> +#define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
> +#define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
> #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
> #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
> #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
> -#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
> -#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
> +#define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
> +#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
> +#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
> #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
> -#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
> -#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
> -#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
> -#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 (1 << 17)
> -#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
> -#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
> -#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
> -#define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
> -#define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
> -#define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
> -#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
> -#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
> +#define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
> +#define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17)
> +#define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
> +#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)
> +#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2)
> +#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3)
> +#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4)
> +#define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13)
> +#define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4)
> +#define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
> +#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
> +#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
> #define _PLANE_BUF_CFG_1_A 0x7027c
> #define _PLANE_BUF_CFG_2_A 0x7037c
> #define _PLANE_NV12_BUF_CFG_1_A 0x70278
> @@ -7440,7 +7462,6 @@ enum {
> _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
> #define PLANE_STRIDE(pipe, plane) \
> _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
> -#define PLANE_STRIDE_MASK REG_GENMASK(11, 0)
>
> #define _PLANE_POS_1_B 0x7118c
> #define _PLANE_POS_2_B 0x7128c
> @@ -7468,7 +7489,6 @@ enum {
> #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
> #define PLANE_SURF(pipe, plane) \
> _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
> -#define PLANE_SURF_DECRYPT REG_BIT(2)
>
> #define _PLANE_OFFSET_1_B 0x711a4
> #define _PLANE_OFFSET_2_B 0x712a4
> @@ -7500,8 +7520,11 @@ enum {
>
> #define _PLANE_BUF_CFG_1_B 0x7127c
> #define _PLANE_BUF_CFG_2_B 0x7137c
> -#define DDB_ENTRY_MASK 0xFFF /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
> -#define DDB_ENTRY_END_SHIFT 16
> +/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
> +#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
> +#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
> +#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
> +#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
> #define _PLANE_BUF_CFG_1(pipe) \
> _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
> #define _PLANE_BUF_CFG_2(pipe) \
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index cff0f32bedc9..7f00fd2f62a0 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4283,11 +4283,10 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
> static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
> struct skl_ddb_entry *entry, u32 reg)
> {
> - entry->start = reg & DDB_ENTRY_MASK;
> - entry->end = (reg >> DDB_ENTRY_END_SHIFT) & DDB_ENTRY_MASK;
> -
> + entry->start = REG_FIELD_GET(PLANE_BUF_START_MASK, reg);
> + entry->end = REG_FIELD_GET(PLANE_BUF_END_MASK, reg);
> if (entry->end)
> - entry->end += 1;
> + entry->end++;
> }
>
> static void
> @@ -4311,7 +4310,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
>
> /* No DDB allocated for disabled planes */
> if (val & PLANE_CTL_ENABLE)
> - fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK,
> + fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK_SKL,
> val & PLANE_CTL_ORDER_RGBX,
> val & PLANE_CTL_ALPHA_MASK);
>
> @@ -5882,7 +5881,8 @@ static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
> {
> if (entry->end)
> intel_de_write_fw(dev_priv, reg,
> - (entry->end - 1) << 16 | entry->start);
> + PLANE_BUF_END(entry->end - 1) |
> + PLANE_BUF_START(entry->start));
> else
> intel_de_write_fw(dev_priv, reg, 0);
> }
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 12/14] drm/i915: Extract skl_plane_aux_dist()
2021-12-01 15:25 ` [Intel-gfx] [PATCH 12/14] drm/i915: Extract skl_plane_aux_dist() Ville Syrjala
@ 2021-12-01 17:28 ` Souza, Jose
0 siblings, 0 replies; 48+ messages in thread
From: Souza, Jose @ 2021-12-01 17:28 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract the PLANE_AUX_DIST stuff into a small helper to
> dclutter skl_program_plane_arm() a bit.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> .../drm/i915/display/skl_universal_plane.c | 35 ++++++++++++-------
> 1 file changed, 23 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 79998eb67280..c7de643d16dd 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -981,6 +981,26 @@ static u32 skl_plane_surf(const struct intel_plane_state *plane_state,
> return plane_surf;
> }
>
> +static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state,
> + int color_plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
> + const struct drm_framebuffer *fb = plane_state->hw.fb;
> + int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> + u32 aux_dist;
> +
> + if (!aux_plane)
> + return 0;
> +
> + aux_dist = skl_surf_address(plane_state, aux_plane) -
> + skl_surf_address(plane_state, color_plane);
> +
> + if (DISPLAY_VER(i915) < 12)
> + aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));
> +
> + return aux_dist;
> +}
> +
> static void icl_plane_csc_load_black(struct intel_plane *plane)
> {
> struct drm_i915_private *i915 = to_i915(plane->base.dev);
> @@ -1075,11 +1095,9 @@ skl_program_plane_arm(struct intel_plane *plane,
> enum plane_id plane_id = plane->id;
> enum pipe pipe = plane->pipe;
> const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> - const struct drm_framebuffer *fb = plane_state->hw.fb;
> - int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> u32 x = plane_state->view.color_plane[color_plane].x;
> u32 y = plane_state->view.color_plane[color_plane].y;
> - u32 keymsk, keymax, aux_dist = 0, plane_color_ctl = 0;
> + u32 keymsk, keymax, plane_color_ctl = 0;
> u8 alpha = plane_state->hw.alpha >> 8;
> u32 plane_ctl = plane_state->ctl;
> unsigned long irqflags;
> @@ -1096,14 +1114,6 @@ skl_program_plane_arm(struct intel_plane *plane,
> if (alpha < 0xff)
> keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
>
> - if (aux_plane) {
> - aux_dist = skl_surf_address(plane_state, aux_plane) -
> - skl_surf_address(plane_state, color_plane);
> -
> - if (DISPLAY_VER(dev_priv) < 12)
> - aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));
> - }
> -
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
> @@ -1114,7 +1124,8 @@ skl_program_plane_arm(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
> PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
>
> - intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
> + intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
> + skl_plane_aux_dist(plane_state, color_plane));
>
> if (DISPLAY_VER(dev_priv) < 11)
> intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 13/14] drm/i915: Declutter color key register stuff
2021-12-01 15:25 ` [Intel-gfx] [PATCH 13/14] drm/i915: Declutter color key register stuff Ville Syrjala
@ 2021-12-01 17:31 ` Souza, Jose
0 siblings, 0 replies; 48+ messages in thread
From: Souza, Jose @ 2021-12-01 17:31 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add a few small helpers to calculate the color key register
> values. Cleans up skl_program_plane_arm() a bit.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> .../drm/i915/display/skl_universal_plane.c | 45 +++++++++++++------
> 1 file changed, 32 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index c7de643d16dd..92270679a99c 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1001,6 +1001,34 @@ static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state,
> return aux_dist;
> }
>
> +static u32 skl_plane_keyval(const struct intel_plane_state *plane_state)
> +{
> + const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> +
> + return key->min_value;
> +}
> +
> +static u32 skl_plane_keymax(const struct intel_plane_state *plane_state)
> +{
> + const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> + u8 alpha = plane_state->hw.alpha >> 8;
> +
> + return (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
> +}
> +
> +static u32 skl_plane_keymsk(const struct intel_plane_state *plane_state)
> +{
> + const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> + u8 alpha = plane_state->hw.alpha >> 8;
> + u32 keymsk;
> +
> + keymsk = key->channel_mask & 0x7ffffff;
> + if (alpha < 0xff)
> + keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
> +
> + return keymsk;
> +}
> +
> static void icl_plane_csc_load_black(struct intel_plane *plane)
> {
> struct drm_i915_private *i915 = to_i915(plane->base.dev);
> @@ -1094,11 +1122,9 @@ skl_program_plane_arm(struct intel_plane *plane,
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum plane_id plane_id = plane->id;
> enum pipe pipe = plane->pipe;
> - const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> u32 x = plane_state->view.color_plane[color_plane].x;
> u32 y = plane_state->view.color_plane[color_plane].y;
> - u32 keymsk, keymax, plane_color_ctl = 0;
> - u8 alpha = plane_state->hw.alpha >> 8;
> + u32 plane_color_ctl = 0;
> u32 plane_ctl = plane_state->ctl;
> unsigned long irqflags;
>
> @@ -1108,18 +1134,11 @@ skl_program_plane_arm(struct intel_plane *plane,
> plane_color_ctl = plane_state->color_ctl |
> glk_plane_color_ctl_crtc(crtc_state);
>
> - keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
> -
> - keymsk = key->channel_mask & 0x7ffffff;
> - if (alpha < 0xff)
> - keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
> -
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> - intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
> - key->min_value);
> - intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk);
> - intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), keymax);
> + intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state));
> + intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state));
> + intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state));
>
> intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
> PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 14/14] drm/i915: Nuke pointless middle men for skl+ plane programming
2021-12-01 15:25 ` [Intel-gfx] [PATCH 14/14] drm/i915: Nuke pointless middle men for skl+ plane programming Ville Syrjala
@ 2021-12-01 17:32 ` Souza, Jose
0 siblings, 0 replies; 48+ messages in thread
From: Souza, Jose @ 2021-12-01 17:32 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> There is no real point in having this two stage
> skl_program_plane*() vs. skl_plane_update*() wrapper stuff.
> All we need to do is determine the correct color plane and
> we're done.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> .../drm/i915/display/skl_universal_plane.c | 53 ++++++-------------
> 1 file changed, 17 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 92270679a99c..de2708ac1802 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1053,15 +1053,24 @@ static void icl_plane_csc_load_black(struct intel_plane *plane)
> intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);
> }
>
> +static int skl_plane_color_plane(const struct intel_plane_state *plane_state)
> +{
> + /* Program the UV plane on planar master */
> + if (plane_state->planar_linked_plane && !plane_state->planar_slave)
> + return 1;
> + else
> + return 0;
> +}
> +
> static void
> -skl_program_plane_noarm(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state,
> - int color_plane)
> +skl_plane_update_noarm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum plane_id plane_id = plane->id;
> enum pipe pipe = plane->pipe;
> + int color_plane = skl_plane_color_plane(plane_state);
> u32 stride = skl_plane_stride(plane_state, color_plane);
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> int crtc_x = plane_state->uapi.dst.x1;
> @@ -1114,14 +1123,14 @@ skl_program_plane_noarm(struct intel_plane *plane,
> }
>
> static void
> -skl_program_plane_arm(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state,
> - int color_plane)
> +skl_plane_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum plane_id plane_id = plane->id;
> enum pipe pipe = plane->pipe;
> + int color_plane = skl_plane_color_plane(plane_state);
> u32 x = plane_state->view.color_plane[color_plane].x;
> u32 y = plane_state->view.color_plane[color_plane].y;
> u32 plane_color_ctl = 0;
> @@ -1202,34 +1211,6 @@ skl_plane_async_flip(struct intel_plane *plane,
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> -static void
> -skl_plane_update_noarm(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> -{
> - int color_plane = 0;
> -
> - if (plane_state->planar_linked_plane && !plane_state->planar_slave)
> - /* Program the UV plane on planar master */
> - color_plane = 1;
> -
> - skl_program_plane_noarm(plane, crtc_state, plane_state, color_plane);
> -}
> -
> -static void
> -skl_plane_update_arm(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> -{
> - int color_plane = 0;
> -
> - if (plane_state->planar_linked_plane && !plane_state->planar_slave)
> - /* Program the UV plane on planar master */
> - color_plane = 1;
> -
> - skl_program_plane_arm(plane, crtc_state, plane_state, color_plane);
> -}
> -
> static bool intel_format_is_p01x(u32 format)
> {
> switch (format) {
^ permalink raw reply [flat|nested] 48+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanup
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
` (13 preceding siblings ...)
2021-12-01 15:25 ` [Intel-gfx] [PATCH 14/14] drm/i915: Nuke pointless middle men for skl+ plane programming Ville Syrjala
@ 2021-12-01 18:47 ` Patchwork
2021-12-01 18:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
17 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2021-12-01 18:47 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Plane register cleanup
URL : https://patchwork.freedesktop.org/series/97467/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2a489c8cf0ae drm/i915: Get rid of the 64bit PLANE_CC_VAL mmio
-:69: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#69: FILE: drivers/gpu/drm/i915/i915_reg.h:7368:
+#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
-:70: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#70: FILE: drivers/gpu/drm/i915/i915_reg.h:7369:
+#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
-:71: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#71: FILE: drivers/gpu/drm/i915/i915_reg.h:7370:
+#define PLANE_CC_VAL(pipe, plane, dw) \
+ _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
-:71: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dw' - possible side-effects?
#71: FILE: drivers/gpu/drm/i915/i915_reg.h:7370:
+#define PLANE_CC_VAL(pipe, plane, dw) \
+ _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
total: 0 errors, 2 warnings, 2 checks, 41 lines checked
cace02264ed4 drm/i915: Rename plane YUV order bits
fd4e986084c5 drm/i915: Get rid of the "sizes are 0 based" stuff
fb774f7bdbf7 drm/i915: Sipmplify PLANE_STRIDE masking
0ae6611ab3f7 drm/i915: Rename PLANE_CUS_CTL Y plane bits
f2f7a1963976 drm/i915: Use REG_BIT() & co. for universal plane bits
08836e799b35 drm/i915: Clean up pre-skl primary plane registers
b7bd2fa19c5d drm/i915: Clean up ivb+ sprite plane registers
-:114: WARNING:LONG_LINE_COMMENT: line length of 106 exceeds 100 columns
#114: FILE: drivers/gpu/drm/i915/i915_reg.h:7058:
+#define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */
total: 0 errors, 1 warnings, 0 checks, 150 lines checked
b2a43d32eb81 drm/i915: Clean up vlv/chv sprite plane registers
e86cd1d175b5 drm/i915: Clean up g4x+ sprite plane registers
f5a56e525f98 drm/i915: Clean up cursor registers
-:144: WARNING:LONG_LINE_COMMENT: line length of 103 exceeds 100 columns
#144: FILE: drivers/gpu/drm/i915/i915_reg.h:6767:
+#define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */
total: 0 errors, 1 warnings, 0 checks, 182 lines checked
0008f4a39e22 drm/i915: Extract skl_plane_aux_dist()
79283225eb38 drm/i915: Declutter color key register stuff
7f07412a683b drm/i915: Nuke pointless middle men for skl+ plane programming
^ permalink raw reply [flat|nested] 48+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Plane register cleanup
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
` (14 preceding siblings ...)
2021-12-01 18:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanup Patchwork
@ 2021-12-01 18:48 ` Patchwork
2021-12-01 19:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-12-02 1:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
17 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2021-12-01 18:48 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Plane register cleanup
URL : https://patchwork.freedesktop.org/series/97467/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 48+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Plane register cleanup
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
` (15 preceding siblings ...)
2021-12-01 18:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-12-01 19:14 ` Patchwork
2021-12-02 1:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
17 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2021-12-01 19:14 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7685 bytes --]
== Series Details ==
Series: drm/i915: Plane register cleanup
URL : https://patchwork.freedesktop.org/series/97467/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10950 -> Patchwork_21718
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/index.html
Participating hosts (40 -> 33)
------------------------------
Additional (1): fi-icl-u2
Missing (8): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-pnv-d510 bat-jsl-2 bat-jsl-1
Known issues
------------
Here are the changes found in Patchwork_21718 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-gfx:
- fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-rkl-guc/igt@amdgpu/amd_basic@cs-gfx.html
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][3] ([i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [PASS][5] -> [INCOMPLETE][6] ([i915#2940])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_pm:
- fi-tgl-1115g4: [PASS][7] -> [DMESG-FAIL][8] ([i915#3987])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: NOTRUN -> [SKIP][10] ([fdo#109278]) +2 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2: NOTRUN -> [SKIP][11] ([fdo#109285])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@primary_page_flip:
- fi-skl-6600u: [PASS][12] -> [FAIL][13] ([i915#4547])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
* igt@prime_vgem@basic-userptr:
- fi-icl-u2: NOTRUN -> [SKIP][14] ([i915#3301])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-icl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-skl-6600u: NOTRUN -> [FAIL][15] ([i915#3363] / [i915#4312])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-skl-6600u/igt@runner@aborted.html
- fi-bsw-n3050: NOTRUN -> [FAIL][16] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-bsw-n3050/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_engines:
- fi-rkl-guc: [INCOMPLETE][17] ([i915#4432]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-bdw-5557u: [DMESG-FAIL][19] ([i915#541]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][21] ([i915#4269]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4432]: https://gitlab.freedesktop.org/drm/intel/issues/4432
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Build changes
-------------
* Linux: CI_DRM_10950 -> Patchwork_21718
CI-20190529: 20190529
CI_DRM_10950: 8088766e298d5a8504c59be3a3812adfb8655fb7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6298: f062f4ae60ecf47af4b037c8f9952a1360662579 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21718: 7f07412a683b700784caac18ef30c6da29a840d0 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7f07412a683b drm/i915: Nuke pointless middle men for skl+ plane programming
79283225eb38 drm/i915: Declutter color key register stuff
0008f4a39e22 drm/i915: Extract skl_plane_aux_dist()
f5a56e525f98 drm/i915: Clean up cursor registers
e86cd1d175b5 drm/i915: Clean up g4x+ sprite plane registers
b2a43d32eb81 drm/i915: Clean up vlv/chv sprite plane registers
b7bd2fa19c5d drm/i915: Clean up ivb+ sprite plane registers
08836e799b35 drm/i915: Clean up pre-skl primary plane registers
f2f7a1963976 drm/i915: Use REG_BIT() & co. for universal plane bits
0ae6611ab3f7 drm/i915: Rename PLANE_CUS_CTL Y plane bits
fb774f7bdbf7 drm/i915: Sipmplify PLANE_STRIDE masking
fd4e986084c5 drm/i915: Get rid of the "sizes are 0 based" stuff
cace02264ed4 drm/i915: Rename plane YUV order bits
2a489c8cf0ae drm/i915: Get rid of the 64bit PLANE_CC_VAL mmio
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/index.html
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^ permalink raw reply [flat|nested] 48+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Plane register cleanup
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
` (16 preceding siblings ...)
2021-12-01 19:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-12-02 1:57 ` Patchwork
17 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2021-12-02 1:57 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30255 bytes --]
== Series Details ==
Series: drm/i915: Plane register cleanup
URL : https://patchwork.freedesktop.org/series/97467/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10950_full -> Patchwork_21718_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21718_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_psr2_su@page_flip-xrgb8888}:
- shard-iclb: [FAIL][1] -> [SKIP][2] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-iclb2/igt@kms_psr2_su@page_flip-xrgb8888.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-iclb5/igt@kms_psr2_su@page_flip-xrgb8888.html
Known issues
------------
Here are the changes found in Patchwork_21718_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#658])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-iclb2/igt@feature_discovery@psr2.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-iclb4/igt@feature_discovery@psr2.html
* igt@gem_eio@in-flight-suspend:
- shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#198]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-skl6/igt@gem_eio@in-flight-suspend.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl1/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_capture@pi@bcs0:
- shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#4547])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-skl4/igt@gem_exec_capture@pi@bcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl10/igt@gem_exec_capture@pi@bcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-kbl2/igt@gem_exec_fair@basic-none@vcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-tglb8/igt@gem_exec_fair@basic-pace@bcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-tglb2/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-apl4/igt@gem_lmem_swapping@parallel-random-engines.html
- shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl7/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@random:
- shard-tglb: NOTRUN -> [SKIP][15] ([i915#4613])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-tglb5/igt@gem_lmem_swapping@random.html
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#4613])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-iclb2/igt@gem_lmem_swapping@random.html
* igt@gem_lmem_swapping@verify-random:
- shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +3 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl1/igt@gem_lmem_swapping@verify-random.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [PASS][18] -> [FAIL][19] ([i915#644])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-glk9/igt@gem_ppgtt@flink-and-close-vma-leak.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-glk6/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271]) +148 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl7/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_userptr_blits@input-checking:
- shard-skl: NOTRUN -> [DMESG-WARN][21] ([i915#3002])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl6/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][22] ([i915#3318])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-apl2/igt@gem_userptr_blits@vma-merge.html
* igt@gem_workarounds@suspend-resume-context:
- shard-skl: NOTRUN -> [INCOMPLETE][23] ([i915#198])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl4/igt@gem_workarounds@suspend-resume-context.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [PASS][24] -> [DMESG-WARN][25] ([i915#180]) +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-kbl1/igt@gem_workarounds@suspend-resume-fd.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][26] -> [FAIL][27] ([i915#454])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-iclb5/igt@i915_pm_dc@dc6-dpms.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
- shard-skl: NOTRUN -> [FAIL][28] ([i915#454])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl9/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [PASS][29] -> [SKIP][30] ([i915#4281])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-iclb7/igt@i915_pm_dc@dc9-dpms.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3777]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl2/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][32] ([i915#3743])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl9/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-skl: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3777]) +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][34] ([i915#3763])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl9/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3886]) +4 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-apl4/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3886]) +6 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl6/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3886]) +8 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl7/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@hdmi-hpd-fast:
- shard-iclb: NOTRUN -> [SKIP][38] ([fdo#109284] / [fdo#111827])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-iclb2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-kbl: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +14 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl2/igt@kms_chamelium@hdmi-hpd-storm.html
- shard-tglb: NOTRUN -> [SKIP][40] ([fdo#109284] / [fdo#111827]) +2 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-tglb5/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_color_chamelium@pipe-a-ctm-limited-range:
- shard-apl: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +11 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-apl4/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-b-ctm-max:
- shard-skl: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +17 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl7/igt@kms_color_chamelium@pipe-b-ctm-max.html
* igt@kms_content_protection@lic:
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109300] / [fdo#111066])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-iclb2/igt@kms_content_protection@lic.html
- shard-tglb: NOTRUN -> [SKIP][44] ([fdo#111828])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-tglb5/igt@kms_content_protection@lic.html
* igt@kms_content_protection@srm:
- shard-apl: NOTRUN -> [TIMEOUT][45] ([i915#1319])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-apl2/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent:
- shard-kbl: NOTRUN -> [FAIL][46] ([i915#2105])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl6/igt@kms_content_protection@uevent.html
- shard-apl: NOTRUN -> [FAIL][47] ([i915#2105])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-apl6/igt@kms_content_protection@uevent.html
* igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][48] -> [FAIL][49] ([i915#79])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank@a-dp1:
- shard-kbl: [PASS][50] -> [FAIL][51] ([i915#79])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-kbl3/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl4/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: NOTRUN -> [DMESG-WARN][52] ([i915#180]) +3 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1:
- shard-skl: [PASS][53] -> [FAIL][54] ([i915#2122])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl10/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-apl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#2672])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-apl2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-apl: NOTRUN -> [SKIP][56] ([fdo#109271]) +124 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-apl4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][57] -> [DMESG-WARN][58] ([i915#180]) +3 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-apl8/igt@kms_frontbuffer_tracking@fbc-suspend.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-skl: NOTRUN -> [SKIP][59] ([fdo#109271]) +203 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#533]) +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][61] ([fdo#108145] / [i915#265]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-skl: NOTRUN -> [FAIL][62] ([fdo#108145] / [i915#265]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][63] ([i915#265])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl3/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][64] ([i915#265]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-kbl: NOTRUN -> [FAIL][65] ([fdo#108145] / [i915#265])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-skl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#2733])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl9/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
- shard-kbl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#658]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
- shard-apl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#658]) +2 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-apl6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
- shard-skl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#658]) +5 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl9/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
* igt@kms_selftest@all@check_plane_state:
- shard-skl: NOTRUN -> [INCOMPLETE][70] ([i915#4663])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl4/igt@kms_selftest@all@check_plane_state.html
- shard-kbl: NOTRUN -> [INCOMPLETE][71] ([i915#4663])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl2/igt@kms_selftest@all@check_plane_state.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#533])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-apl2/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-kbl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#2437])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl7/igt@kms_writeback@writeback-invalid-parameters.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-skl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#2437])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl7/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@blocking:
- shard-skl: [PASS][75] -> [FAIL][76] ([i915#1542])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-skl6/igt@perf@blocking.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl5/igt@perf@blocking.html
* igt@sysfs_clients@sema-10:
- shard-skl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#2994]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl7/igt@sysfs_clients@sema-10.html
* igt@sysfs_clients@sema-50:
- shard-kbl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2994])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl3/igt@sysfs_clients@sema-50.html
#### Possible fixes ####
* igt@fbdev@eof:
- {shard-rkl}: [SKIP][79] ([i915#2582]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-1/igt@fbdev@eof.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-rkl-6/igt@fbdev@eof.html
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl: [DMESG-WARN][81] ([i915#165]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][83] ([i915#3063] / [i915#3648]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-tglb1/igt@gem_eio@unwedge-stress.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-tglb8/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][85] ([i915#2846]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-glk4/igt@gem_exec_fair@basic-deadline.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-glk2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][87] ([i915#2842]) -> [PASS][88] +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][89] ([i915#2842]) -> [PASS][90] +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html
- shard-apl: [SKIP][91] ([fdo#109271]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-apl7/igt@gem_exec_fair@basic-none-share@rcs0.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-apl4/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: [FAIL][93] ([i915#2842]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-kbl2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][95] ([i915#2842]) -> [PASS][96] +1 similar issue
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-glk3/igt@gem_exec_fair@basic-throttle@rcs0.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-glk6/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- shard-glk: [DMESG-WARN][97] ([i915#118]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-glk3/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-glk6/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0:
- {shard-rkl}: ([SKIP][99], [SKIP][100]) ([i915#1845]) -> [PASS][101]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-rkl-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_color@pipe-a-ctm-red-to-blue:
- {shard-rkl}: ([SKIP][102], [PASS][103]) ([i915#1149] / [i915#4098]) -> [PASS][104]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-4/igt@kms_color@pipe-a-ctm-red-to-blue.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-6/igt@kms_color@pipe-a-ctm-red-to-blue.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-rkl-6/igt@kms_color@pipe-a-ctm-red-to-blue.html
* igt@kms_color@pipe-b-ctm-0-25:
- {shard-rkl}: ([SKIP][105], [SKIP][106]) ([i915#1149] / [i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][107] +1 similar issue
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-1/igt@kms_color@pipe-b-ctm-0-25.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-4/igt@kms_color@pipe-b-ctm-0-25.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-rkl-6/igt@kms_color@pipe-b-ctm-0-25.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen:
- {shard-rkl}: [SKIP][108] ([fdo#112022] / [i915#4070]) -> [PASS][109] +3 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-1/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [FAIL][110] ([i915#2346]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
- {shard-rkl}: [SKIP][112] ([fdo#111825] / [i915#4070]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-1/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled:
- {shard-rkl}: [SKIP][114] ([fdo#111314]) -> [PASS][115] +3 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-1/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-rkl-6/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile:
- shard-iclb: [SKIP][116] ([i915#3701]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt:
- {shard-rkl}: ([SKIP][118], [SKIP][119]) ([i915#1849] / [i915#4098]) -> [PASS][120] +2 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc:
- {shard-rkl}: ([PASS][121], [SKIP][122]) ([i915#4098]) -> [PASS][123]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render:
- {shard-rkl}: [SKIP][124] ([i915#1849]) -> [PASS][125] +5 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite:
- {shard-rkl}: [SKIP][126] ([i915#4098]) -> [PASS][127] +1 similar issue
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][128] ([i915#1188]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl5/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: [DMESG-WARN][130] ([i915#180]) -> [PASS][131] +4 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-kbl4/igt@kms_hdr@bpc-switch-suspend.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl6/igt@kms_hdr@bpc-switch-suspend.html
- shard-apl: [DMESG-WARN][132] ([i915#180]) -> [PASS][133] +1 similar issue
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-apl1/igt@kms_hdr@bpc-switch-suspend.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-apl6/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_lease@lease_revoke:
- {shard-rkl}: [SKIP][134] ([i915#1845] / [i915#4098]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-4/igt@kms_lease@lease_revoke.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-rkl-6/igt@kms_lease@lease_revoke.html
* igt@kms_lease@lease_unleased_crtc:
- {shard-rkl}: ([SKIP][136], [SKIP][137]) ([i915#1845] / [i915#4098]) -> [PASS][138]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-4/igt@kms_lease@lease_unleased_crtc.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-1/igt@kms_lease@lease_unleased_crtc.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-rkl-6/igt@kms_lease@lease_unleased_crtc.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-skl: [INCOMPLETE][139] ([i915#198]) -> [PASS][140]
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane@plane-position-covered@pipe-b-planes:
- {shard-rkl}: [SKIP][141] ([i915#3558]) -> [PASS][142] +1 similar issue
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-1/igt@kms_plane@plane-position-covered@pipe-b-planes.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-rkl-6/igt@kms_plane@plane-position-covered@pipe-b-planes.html
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- {shard-rkl}: [SKIP][143] ([i915#3558] / [i915#4070]) -> [PASS][144]
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-rkl-1/igt@kms_plane_multiple@atomic-pipe-b-tiling-none.html
[144]: https://intel-gfx-ci.01.o
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/index.html
[-- Attachment #2: Type: text/html, Size: 33305 bytes --]
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 02/14] drm/i915: Rename plane YUV order bits
2021-12-01 17:14 ` Souza, Jose
@ 2021-12-02 11:53 ` Ville Syrjälä
0 siblings, 0 replies; 48+ messages in thread
From: Ville Syrjälä @ 2021-12-02 11:53 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Wed, Dec 01, 2021 at 05:14:39PM +0000, Souza, Jose wrote:
> On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Rename the YUV byte order bits to be a bit more consistent.
>
> Why rename bits not used? Would be better already nuke it.
> Anyways up to you.
We'll need the masks for the REG_FIELD_PREP() stuff later.
>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/skl_universal_plane.c | 8 ++++----
> > drivers/gpu/drm/i915/i915_reg.h | 14 +++++++-------
> > 2 files changed, 11 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 845b99844ec6..9ff24a0e79b4 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -672,13 +672,13 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
> > case DRM_FORMAT_XYUV8888:
> > return PLANE_CTL_FORMAT_XYUV;
> > case DRM_FORMAT_YUYV:
> > - return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
> > + return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YUYV;
> > case DRM_FORMAT_YVYU:
> > - return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
> > + return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YVYU;
> > case DRM_FORMAT_UYVY:
> > - return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
> > + return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_UYVY;
> > case DRM_FORMAT_VYUY:
> > - return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
> > + return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_VYUY;
> > case DRM_FORMAT_NV12:
> > return PLANE_CTL_FORMAT_NV12;
> > case DRM_FORMAT_P010:
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 3c0471f20e53..02d8db03c0bf 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6966,7 +6966,7 @@ enum {
> > #define DVS_SOURCE_KEY (1 << 22)
> > #define DVS_RGB_ORDER_XBGR (1 << 20)
> > #define DVS_YUV_FORMAT_BT709 (1 << 18)
> > -#define DVS_YUV_BYTE_ORDER_MASK (3 << 16)
> > +#define DVS_YUV_ORDER_MASK (3 << 16)
> > #define DVS_YUV_ORDER_YUYV (0 << 16)
> > #define DVS_YUV_ORDER_UYVY (1 << 16)
> > #define DVS_YUV_ORDER_YVYU (2 << 16)
> > @@ -7045,7 +7045,7 @@ enum {
> > #define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and 161616 */
> > #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)
> > #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */
> > -#define SPRITE_YUV_BYTE_ORDER_MASK (3 << 16)
> > +#define SPRITE_YUV_ORDER_MASK (3 << 16)
> > #define SPRITE_YUV_ORDER_YUYV (0 << 16)
> > #define SPRITE_YUV_ORDER_UYVY (1 << 16)
> > #define SPRITE_YUV_ORDER_YVYU (2 << 16)
> > @@ -7130,7 +7130,7 @@ enum {
> > #define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
> > #define SP_SOURCE_KEY (1 << 22)
> > #define SP_YUV_FORMAT_BT709 (1 << 18)
> > -#define SP_YUV_BYTE_ORDER_MASK (3 << 16)
> > +#define SP_YUV_ORDER_MASK (3 << 16)
> > #define SP_YUV_ORDER_YUYV (0 << 16)
> > #define SP_YUV_ORDER_UYVY (1 << 16)
> > #define SP_YUV_ORDER_YVYU (2 << 16)
> > @@ -7271,10 +7271,10 @@ enum {
> > #define PLANE_CTL_YUV420_Y_PLANE (1 << 19)
> > #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
> > #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
> > -#define PLANE_CTL_YUV422_YUYV (0 << 16)
> > -#define PLANE_CTL_YUV422_UYVY (1 << 16)
> > -#define PLANE_CTL_YUV422_YVYU (2 << 16)
> > -#define PLANE_CTL_YUV422_VYUY (3 << 16)
> > +#define PLANE_CTL_YUV422_ORDER_YUYV (0 << 16)
> > +#define PLANE_CTL_YUV422_ORDER_UYVY (1 << 16)
> > +#define PLANE_CTL_YUV422_ORDER_YVYU (2 << 16)
> > +#define PLANE_CTL_YUV422_ORDER_VYUY (3 << 16)
> > #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
> > #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
> > #define PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13) /* TGL+ */
>
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 03/14] drm/i915: Get rid of the "sizes are 0 based" stuff
2021-12-01 17:18 ` Souza, Jose
@ 2021-12-02 11:56 ` Ville Syrjälä
2021-12-03 13:40 ` Souza, Jose
0 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjälä @ 2021-12-02 11:56 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Wed, Dec 01, 2021 at 05:18:54PM +0000, Souza, Jose wrote:
> On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Replace the "sizes are 0 based" stuff with just straight
> > up -1 where needed. Less confusing all around.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_sprite.c | 26 ++++---------------
> > .../drm/i915/display/skl_universal_plane.c | 6 +----
> > 2 files changed, 6 insertions(+), 26 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index 1b99a9501a45..2067a7bca4a8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -431,10 +431,6 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
> > u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
> > unsigned long irqflags;
> >
> > - /* Sizes are 0 based */
>
> In my opinion at least this comment should stay, helps understand why the -1.
It's just normal practice for almost all such registers.
We don't have similar comments elsewhere either. Also if
the code already says "foo-1" then I don't see what extra
the comment gets you.
>
> > - crtc_w--;
> > - crtc_h--;
> > -
> > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> >
> > intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
> > @@ -442,7 +438,7 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
> > intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),
> > (crtc_y << 16) | crtc_x);
> > intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
> > - (crtc_h << 16) | crtc_w);
> > + ((crtc_h - 1) << 16) | (crtc_w - 1));
> >
> > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> > }
> > @@ -866,21 +862,15 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
> > u32 sprscale = 0;
> > unsigned long irqflags;
> >
> > - /* Sizes are 0 based */
> > - src_w--;
> > - src_h--;
> > - crtc_w--;
> > - crtc_h--;
> > -
> > if (crtc_w != src_w || crtc_h != src_h)
> > - sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
> > + sprscale = SPRITE_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
> >
> > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> >
> > intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
> > plane_state->view.color_plane[0].mapping_stride);
> > intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x);
> > - intel_de_write_fw(dev_priv, SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
> > + intel_de_write_fw(dev_priv, SPRSIZE(pipe), ((crtc_h - 1) << 16) | (crtc_w - 1));
> > if (IS_IVYBRIDGE(dev_priv))
> > intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
> >
> > @@ -1208,21 +1198,15 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
> > u32 dvsscale = 0;
> > unsigned long irqflags;
> >
> > - /* Sizes are 0 based */
> > - src_w--;
> > - src_h--;
> > - crtc_w--;
> > - crtc_h--;
> > -
> > if (crtc_w != src_w || crtc_h != src_h)
> > - dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
> > + dvsscale = DVS_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
> >
> > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> >
> > intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
> > plane_state->view.color_plane[0].mapping_stride);
> > intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x);
> > - intel_de_write_fw(dev_priv, DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
> > + intel_de_write_fw(dev_priv, DVSSIZE(pipe), ((crtc_h - 1) << 16) | (crtc_w - 1));
> > intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
> >
> > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 9ff24a0e79b4..09948922016b 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -1022,10 +1022,6 @@ skl_program_plane_noarm(struct intel_plane *plane,
> > u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> > unsigned long irqflags;
> >
> > - /* Sizes are 0 based */
> > - src_w--;
> > - src_h--;
> > -
> > /* The scaler will handle the output position */
> > if (plane_state->scaler_id >= 0) {
> > crtc_x = 0;
> > @@ -1045,7 +1041,7 @@ skl_program_plane_noarm(struct intel_plane *plane,
> > intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
> > (crtc_y << 16) | crtc_x);
> > intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
> > - (src_h << 16) | src_w);
> > + ((src_h - 1) << 16) | (src_w - 1));
> >
> > if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
> > intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
>
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 06/14] drm/i915: Use REG_BIT() & co. for universal plane bits
2021-12-01 17:26 ` Souza, Jose
@ 2021-12-02 11:57 ` Ville Syrjälä
2022-01-12 19:52 ` Souza, Jose
0 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjälä @ 2021-12-02 11:57 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Wed, Dec 01, 2021 at 05:26:50PM +0000, Souza, Jose wrote:
> On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Polish the skl+ universal plane register defines by
> > using REG_BIT() & co.
> >
> > The defines are also currently spread around in some
> > semi-random fashion. Collect them up into one place.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > .../drm/i915/display/skl_universal_plane.c | 36 ++--
> > drivers/gpu/drm/i915/gvt/reg.h | 1 -
> > drivers/gpu/drm/i915/i915_reg.h | 197 ++++++++++--------
> > drivers/gpu/drm/i915/intel_pm.c | 12 +-
> > 4 files changed, 135 insertions(+), 111 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 984bb35ecf06..79998eb67280 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -1037,11 +1037,12 @@ skl_program_plane_noarm(struct intel_plane *plane,
> > if (plane_state->force_black)
> > icl_plane_csc_load_black(plane);
> >
> > - intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), stride);
> > + intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
> > + PLANE_STRIDE_(stride));
> > intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
> > - (crtc_y << 16) | crtc_x);
> > + PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
> > intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
> > - ((src_h - 1) << 16) | (src_w - 1));
> > + PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
> >
> > if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
> > intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
> > @@ -1100,7 +1101,7 @@ skl_program_plane_arm(struct intel_plane *plane,
> > skl_surf_address(plane_state, color_plane);
> >
> > if (DISPLAY_VER(dev_priv) < 12)
> > - aux_dist |= skl_plane_stride(plane_state, aux_plane);
> > + aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));
> > }
> >
> > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> > @@ -1111,14 +1112,14 @@ skl_program_plane_arm(struct intel_plane *plane,
> > intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), keymax);
> >
> > intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
> > - (y << 16) | x);
> > + PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
> >
> > intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
> >
> > if (DISPLAY_VER(dev_priv) < 11)
> > intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
> > - (plane_state->view.color_plane[1].y << 16) |
> > - plane_state->view.color_plane[1].x);
> > + PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) |
> > + PLANE_OFFSET_X(plane_state->view.color_plane[1].x));
> >
> > if (DISPLAY_VER(dev_priv) >= 10)
> > intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
> > @@ -2262,16 +2263,17 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
> >
> > if (DISPLAY_VER(dev_priv) >= 11)
> > - pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
> > + pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL;
>
> Most of our platform bits definition follows <platform or display ver>_<register name>.
s/most/some/
I want it exactly the other way around so that the namespace for
each register is consistent.
>
> Other than that the idea looks good to me.
>
> > else
> > - pixel_format = val & PLANE_CTL_FORMAT_MASK;
> > + pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL;
> >
> > if (DISPLAY_VER(dev_priv) >= 10) {
> > - alpha = intel_de_read(dev_priv,
> > - PLANE_COLOR_CTL(pipe, plane_id));
> > - alpha &= PLANE_COLOR_ALPHA_MASK;
> > + u32 color_ctl;
> > +
> > + color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe, plane_id));
> > + alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl);
> > } else {
> > - alpha = val & PLANE_CTL_ALPHA_MASK;
> > + alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val);
> > }
> >
> > fourcc = skl_format_to_fourcc(pixel_format,
> > @@ -2335,19 +2337,19 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > if (drm_rotation_90_or_270(plane_config->rotation))
> > goto error;
> >
> > - base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
> > + base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK;
> > plane_config->base = base;
> >
> > offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
> >
> > val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
> > - fb->height = ((val >> 16) & 0xffff) + 1;
> > - fb->width = ((val >> 0) & 0xffff) + 1;
> > + fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1;
> > + fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1;
> >
> > val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
> > stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
> >
> > - fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
> > + fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult;
> >
> > aligned_height = intel_fb_align_height(fb, 0, fb->height);
> >
> > diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
> > index 244cc7320b54..7d666d34f9ff 100644
> > --- a/drivers/gpu/drm/i915/gvt/reg.h
> > +++ b/drivers/gpu/drm/i915/gvt/reg.h
> > @@ -62,7 +62,6 @@
> >
> > #define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe))
> >
> > -#define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > #define REG50080_FLIP_TYPE_MASK 0x3
> > #define REG50080_FLIP_TYPE_ASYNC 0x1
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 4b2bc17d0235..9fffa2392bbf 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7233,84 +7233,99 @@ enum {
> > #define _PLANE_CTL_1_A 0x70180
> > #define _PLANE_CTL_2_A 0x70280
> > #define _PLANE_CTL_3_A 0x70380
> > -#define PLANE_CTL_ENABLE (1 << 31)
> > +#define PLANE_CTL_ENABLE REG_BIT(31)
> > #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
> > #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
> > -#define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
> > -#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
> > +#define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
> > +#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
> > /*
> > * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
> > * expanded to include bit 23 as well. However, the shift-24 based values
> > * correctly map to the same formats in ICL, as long as bit 23 is set to 0
> > */
> > -#define PLANE_CTL_FORMAT_MASK (0xf << 24)
> > -#define PLANE_CTL_FORMAT_YUV422 (0 << 24)
> > -#define PLANE_CTL_FORMAT_NV12 (1 << 24)
> > -#define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
> > -#define PLANE_CTL_FORMAT_P010 (3 << 24)
> > -#define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24)
> > -#define PLANE_CTL_FORMAT_P012 (5 << 24)
> > -#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
> > -#define PLANE_CTL_FORMAT_P016 (7 << 24)
> > -#define PLANE_CTL_FORMAT_XYUV (8 << 24)
> > -#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
> > -#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
> > -#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
> > -#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
> > -#define PLANE_CTL_FORMAT_Y210 (1 << 23)
> > -#define PLANE_CTL_FORMAT_Y212 (3 << 23)
> > -#define PLANE_CTL_FORMAT_Y216 (5 << 23)
> > -#define PLANE_CTL_FORMAT_Y410 (7 << 23)
> > -#define PLANE_CTL_FORMAT_Y412 (9 << 23)
> > -#define PLANE_CTL_FORMAT_Y416 (0xb << 23)
> > -#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
> > -#define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
> > -#define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
> > -#define PLANE_CTL_ORDER_BGRX (0 << 20)
> > -#define PLANE_CTL_ORDER_RGBX (1 << 20)
> > -#define PLANE_CTL_YUV420_Y_PLANE (1 << 19)
> > -#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
> > -#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
> > -#define PLANE_CTL_YUV422_ORDER_YUYV (0 << 16)
> > -#define PLANE_CTL_YUV422_ORDER_UYVY (1 << 16)
> > -#define PLANE_CTL_YUV422_ORDER_YVYU (2 << 16)
> > -#define PLANE_CTL_YUV422_ORDER_VYUY (3 << 16)
> > -#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
> > -#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
> > -#define PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13) /* TGL+ */
> > -#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
> > -#define PLANE_CTL_TILED_MASK (0x7 << 10)
> > -#define PLANE_CTL_TILED_LINEAR (0 << 10)
> > -#define PLANE_CTL_TILED_X (1 << 10)
> > -#define PLANE_CTL_TILED_Y (4 << 10)
> > -#define PLANE_CTL_TILED_YF (5 << 10)
> > -#define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > -#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > -#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> > -#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
> > -#define PLANE_CTL_ALPHA_DISABLE (0 << 4)
> > -#define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
> > -#define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4)
> > -#define PLANE_CTL_ROTATE_MASK 0x3
> > -#define PLANE_CTL_ROTATE_0 0x0
> > -#define PLANE_CTL_ROTATE_90 0x1
> > -#define PLANE_CTL_ROTATE_180 0x2
> > -#define PLANE_CTL_ROTATE_270 0x3
> > +#define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */
> > +#define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */
> > +#define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
> > +#define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1)
> > +#define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2)
> > +#define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3)
> > +#define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4)
> > +#define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5)
> > +#define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6)
> > +#define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7)
> > +#define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8)
> > +#define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12)
> > +#define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14)
> > +#define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1)
> > +#define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3)
> > +#define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5)
> > +#define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7)
> > +#define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9)
> > +#define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11)
> > +#define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
> > +#define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21)
> > +#define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1)
> > +#define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2)
> > +#define PLANE_CTL_ORDER_RGBX REG_BIT(20)
> > +#define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19)
> > +#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18)
> > +#define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16)
> > +#define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)
> > +#define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1)
> > +#define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2)
> > +#define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3)
> > +#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15)
> > +#define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14)
> > +#define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
> > +#define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
> > +#define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10)
> > +#define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0)
> > +#define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1)
> > +#define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4)
> > +#define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
> > +#define PLANE_CTL_ASYNC_FLIP REG_BIT(9)
> > +#define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8)
> > +#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
> > +#define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
> > +#define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0)
> > +#define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2)
> > +#define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3)
> > +#define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0)
> > +#define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0)
> > +#define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
> > +#define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
> > +#define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
> > #define _PLANE_STRIDE_1_A 0x70188
> > #define _PLANE_STRIDE_2_A 0x70288
> > #define _PLANE_STRIDE_3_A 0x70388
> > +#define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
> > +#define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
> > #define _PLANE_POS_1_A 0x7018c
> > #define _PLANE_POS_2_A 0x7028c
> > #define _PLANE_POS_3_A 0x7038c
> > +#define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
> > +#define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
> > +#define PLANE_POS_X_MASK REG_GENMASK(15, 0)
> > +#define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
> > #define _PLANE_SIZE_1_A 0x70190
> > #define _PLANE_SIZE_2_A 0x70290
> > #define _PLANE_SIZE_3_A 0x70390
> > +#define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
> > +#define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
> > +#define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
> > +#define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
> > #define _PLANE_SURF_1_A 0x7019c
> > #define _PLANE_SURF_2_A 0x7029c
> > #define _PLANE_SURF_3_A 0x7039c
> > +#define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
> > +#define PLANE_SURF_DECRYPT REG_BIT(2)
> > #define _PLANE_OFFSET_1_A 0x701a4
> > #define _PLANE_OFFSET_2_A 0x702a4
> > #define _PLANE_OFFSET_3_A 0x703a4
> > +#define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
> > +#define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
> > +#define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
> > +#define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))
> > #define _PLANE_KEYVAL_1_A 0x70194
> > #define _PLANE_KEYVAL_2_A 0x70294
> > #define _PLANE_KEYMSK_1_A 0x70198
> > @@ -7322,42 +7337,49 @@ enum {
> > #define _PLANE_CC_VAL_1_A 0x701b4
> > #define _PLANE_CC_VAL_2_A 0x702b4
> > #define _PLANE_AUX_DIST_1_A 0x701c0
> > +#define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
> > +#define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
> > +#define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
> > #define _PLANE_AUX_DIST_2_A 0x702c0
> > #define _PLANE_AUX_OFFSET_1_A 0x701c4
> > #define _PLANE_AUX_OFFSET_2_A 0x702c4
> > #define _PLANE_CUS_CTL_1_A 0x701c8
> > #define _PLANE_CUS_CTL_2_A 0x702c8
> > -#define PLANE_CUS_ENABLE (1 << 31)
> > -#define PLANE_CUS_Y_PLANE_4_RKL (0 << 30)
> > -#define PLANE_CUS_Y_PLANE_5_RKL (1 << 30)
> > -#define PLANE_CUS_Y_PLANE_6_ICL (0 << 30)
> > -#define PLANE_CUS_Y_PLANE_7_ICL (1 << 30)
> > -#define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19)
> > -#define PLANE_CUS_HPHASE_0 (0 << 16)
> > -#define PLANE_CUS_HPHASE_0_25 (1 << 16)
> > -#define PLANE_CUS_HPHASE_0_5 (2 << 16)
> > -#define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15)
> > -#define PLANE_CUS_VPHASE_0 (0 << 12)
> > -#define PLANE_CUS_VPHASE_0_25 (1 << 12)
> > -#define PLANE_CUS_VPHASE_0_5 (2 << 12)
> > +#define PLANE_CUS_ENABLE REG_BIT(31)
> > +#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
> > +#define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
> > +#define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
> > +#define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
> > +#define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
> > +#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
> > +#define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16)
> > +#define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
> > +#define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
> > +#define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
> > +#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
> > +#define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12)
> > +#define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
> > +#define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
> > +#define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
> > #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
> > #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
> > #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
> > -#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
> > -#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
> > +#define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
> > +#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
> > +#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
> > #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
> > -#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
> > -#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
> > -#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
> > -#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 (1 << 17)
> > -#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
> > -#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
> > -#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
> > -#define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
> > -#define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
> > -#define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
> > -#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
> > -#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
> > +#define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
> > +#define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17)
> > +#define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
> > +#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)
> > +#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2)
> > +#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3)
> > +#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4)
> > +#define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13)
> > +#define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4)
> > +#define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
> > +#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
> > +#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
> > #define _PLANE_BUF_CFG_1_A 0x7027c
> > #define _PLANE_BUF_CFG_2_A 0x7037c
> > #define _PLANE_NV12_BUF_CFG_1_A 0x70278
> > @@ -7440,7 +7462,6 @@ enum {
> > _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
> > #define PLANE_STRIDE(pipe, plane) \
> > _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
> > -#define PLANE_STRIDE_MASK REG_GENMASK(11, 0)
> >
> > #define _PLANE_POS_1_B 0x7118c
> > #define _PLANE_POS_2_B 0x7128c
> > @@ -7468,7 +7489,6 @@ enum {
> > #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
> > #define PLANE_SURF(pipe, plane) \
> > _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
> > -#define PLANE_SURF_DECRYPT REG_BIT(2)
> >
> > #define _PLANE_OFFSET_1_B 0x711a4
> > #define _PLANE_OFFSET_2_B 0x712a4
> > @@ -7500,8 +7520,11 @@ enum {
> >
> > #define _PLANE_BUF_CFG_1_B 0x7127c
> > #define _PLANE_BUF_CFG_2_B 0x7137c
> > -#define DDB_ENTRY_MASK 0xFFF /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
> > -#define DDB_ENTRY_END_SHIFT 16
> > +/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
> > +#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
> > +#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
> > +#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
> > +#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
> > #define _PLANE_BUF_CFG_1(pipe) \
> > _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
> > #define _PLANE_BUF_CFG_2(pipe) \
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index cff0f32bedc9..7f00fd2f62a0 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4283,11 +4283,10 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
> > static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
> > struct skl_ddb_entry *entry, u32 reg)
> > {
> > - entry->start = reg & DDB_ENTRY_MASK;
> > - entry->end = (reg >> DDB_ENTRY_END_SHIFT) & DDB_ENTRY_MASK;
> > -
> > + entry->start = REG_FIELD_GET(PLANE_BUF_START_MASK, reg);
> > + entry->end = REG_FIELD_GET(PLANE_BUF_END_MASK, reg);
> > if (entry->end)
> > - entry->end += 1;
> > + entry->end++;
> > }
> >
> > static void
> > @@ -4311,7 +4310,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
> >
> > /* No DDB allocated for disabled planes */
> > if (val & PLANE_CTL_ENABLE)
> > - fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK,
> > + fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK_SKL,
> > val & PLANE_CTL_ORDER_RGBX,
> > val & PLANE_CTL_ALPHA_MASK);
> >
> > @@ -5882,7 +5881,8 @@ static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
> > {
> > if (entry->end)
> > intel_de_write_fw(dev_priv, reg,
> > - (entry->end - 1) << 16 | entry->start);
> > + PLANE_BUF_END(entry->end - 1) |
> > + PLANE_BUF_START(entry->start));
> > else
> > intel_de_write_fw(dev_priv, reg, 0);
> > }
>
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 03/14] drm/i915: Get rid of the "sizes are 0 based" stuff
2021-12-02 11:56 ` Ville Syrjälä
@ 2021-12-03 13:40 ` Souza, Jose
0 siblings, 0 replies; 48+ messages in thread
From: Souza, Jose @ 2021-12-03 13:40 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Thu, 2021-12-02 at 13:56 +0200, Ville Syrjälä wrote:
> On Wed, Dec 01, 2021 at 05:18:54PM +0000, Souza, Jose wrote:
> > On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Replace the "sizes are 0 based" stuff with just straight
> > > up -1 where needed. Less confusing all around.
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_sprite.c | 26 ++++---------------
> > > .../drm/i915/display/skl_universal_plane.c | 6 +----
> > > 2 files changed, 6 insertions(+), 26 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > index 1b99a9501a45..2067a7bca4a8 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > @@ -431,10 +431,6 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
> > > u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
> > > unsigned long irqflags;
> > >
> > > - /* Sizes are 0 based */
> >
> > In my opinion at least this comment should stay, helps understand why the -1.
>
> It's just normal practice for almost all such registers.
> We don't have similar comments elsewhere either. Also if
> the code already says "foo-1" then I don't see what extra
> the comment gets you.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> >
> > > - crtc_w--;
> > > - crtc_h--;
> > > -
> > > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> > >
> > > intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
> > > @@ -442,7 +438,7 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
> > > intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),
> > > (crtc_y << 16) | crtc_x);
> > > intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
> > > - (crtc_h << 16) | crtc_w);
> > > + ((crtc_h - 1) << 16) | (crtc_w - 1));
> > >
> > > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> > > }
> > > @@ -866,21 +862,15 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
> > > u32 sprscale = 0;
> > > unsigned long irqflags;
> > >
> > > - /* Sizes are 0 based */
> > > - src_w--;
> > > - src_h--;
> > > - crtc_w--;
> > > - crtc_h--;
> > > -
> > > if (crtc_w != src_w || crtc_h != src_h)
> > > - sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
> > > + sprscale = SPRITE_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
> > >
> > > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> > >
> > > intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
> > > plane_state->view.color_plane[0].mapping_stride);
> > > intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x);
> > > - intel_de_write_fw(dev_priv, SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
> > > + intel_de_write_fw(dev_priv, SPRSIZE(pipe), ((crtc_h - 1) << 16) | (crtc_w - 1));
> > > if (IS_IVYBRIDGE(dev_priv))
> > > intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
> > >
> > > @@ -1208,21 +1198,15 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
> > > u32 dvsscale = 0;
> > > unsigned long irqflags;
> > >
> > > - /* Sizes are 0 based */
> > > - src_w--;
> > > - src_h--;
> > > - crtc_w--;
> > > - crtc_h--;
> > > -
> > > if (crtc_w != src_w || crtc_h != src_h)
> > > - dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
> > > + dvsscale = DVS_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
> > >
> > > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> > >
> > > intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
> > > plane_state->view.color_plane[0].mapping_stride);
> > > intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x);
> > > - intel_de_write_fw(dev_priv, DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
> > > + intel_de_write_fw(dev_priv, DVSSIZE(pipe), ((crtc_h - 1) << 16) | (crtc_w - 1));
> > > intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
> > >
> > > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > index 9ff24a0e79b4..09948922016b 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > @@ -1022,10 +1022,6 @@ skl_program_plane_noarm(struct intel_plane *plane,
> > > u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> > > unsigned long irqflags;
> > >
> > > - /* Sizes are 0 based */
> > > - src_w--;
> > > - src_h--;
> > > -
> > > /* The scaler will handle the output position */
> > > if (plane_state->scaler_id >= 0) {
> > > crtc_x = 0;
> > > @@ -1045,7 +1041,7 @@ skl_program_plane_noarm(struct intel_plane *plane,
> > > intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
> > > (crtc_y << 16) | crtc_x);
> > > intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
> > > - (src_h << 16) | src_w);
> > > + ((src_h - 1) << 16) | (src_w - 1));
> > >
> > > if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
> > > intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
> >
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 02/14] drm/i915: Rename plane YUV order bits
2021-12-01 15:25 ` [Intel-gfx] [PATCH 02/14] drm/i915: Rename plane YUV order bits Ville Syrjala
@ 2021-12-06 13:13 ` kernel test robot
2021-12-06 13:13 ` kernel test robot
1 sibling, 0 replies; 48+ messages in thread
From: kernel test robot @ 2021-12-06 13:13 UTC (permalink / raw)
To: Ville Syrjala; +Cc: llvm, kbuild-all
Hi Ville,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to drm-tip/drm-tip v5.16-rc4 next-20211206]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Plane-register-cleanup/20211202-010520
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a012-20211130 (https://download.01.org/0day-ci/archive/20211206/202112062144.pndb6yAj-lkp@intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 4b553297ef3ee4dc2119d5429adf3072e90fac38)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/9e3683729de554eb265e6f4d8ec9cfc6eb591e52
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Plane-register-cleanup/20211202-010520
git checkout 9e3683729de554eb265e6f4d8ec9cfc6eb591e52
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:430:21: error: use of undeclared identifier 'SPRITE_YUV_BYTE_ORDER_MASK'
yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >>
^
1 error generated.
vim +/SPRITE_YUV_BYTE_ORDER_MASK +430 drivers/gpu/drm/i915/gvt/fb_decoder.c
9f31d1063b434c Tina Zhang 2017-11-23 401
9f31d1063b434c Tina Zhang 2017-11-23 402 /**
9f31d1063b434c Tina Zhang 2017-11-23 403 * intel_vgpu_decode_sprite_plane - Decode sprite plane
9f31d1063b434c Tina Zhang 2017-11-23 404 * @vgpu: input vgpu
9f31d1063b434c Tina Zhang 2017-11-23 405 * @plane: sprite plane to save decoded info
9f31d1063b434c Tina Zhang 2017-11-23 406 * This function is called for decoding plane
9f31d1063b434c Tina Zhang 2017-11-23 407 *
9f31d1063b434c Tina Zhang 2017-11-23 408 * Returns:
9f31d1063b434c Tina Zhang 2017-11-23 409 * 0 on success, non-zero if failed.
9f31d1063b434c Tina Zhang 2017-11-23 410 */
9f31d1063b434c Tina Zhang 2017-11-23 411 int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,
9f31d1063b434c Tina Zhang 2017-11-23 412 struct intel_vgpu_sprite_plane_format *plane)
9f31d1063b434c Tina Zhang 2017-11-23 413 {
9f31d1063b434c Tina Zhang 2017-11-23 414 u32 val, fmt;
9f31d1063b434c Tina Zhang 2017-11-23 415 u32 color_order, yuv_order;
9f31d1063b434c Tina Zhang 2017-11-23 416 int drm_format;
9f31d1063b434c Tina Zhang 2017-11-23 417 int pipe;
9f31d1063b434c Tina Zhang 2017-11-23 418
9f31d1063b434c Tina Zhang 2017-11-23 419 pipe = get_active_pipe(vgpu);
9f31d1063b434c Tina Zhang 2017-11-23 420 if (pipe >= I915_MAX_PIPES)
9f31d1063b434c Tina Zhang 2017-11-23 421 return -ENODEV;
9f31d1063b434c Tina Zhang 2017-11-23 422
90551a1296d4db Zhenyu Wang 2017-12-19 423 val = vgpu_vreg_t(vgpu, SPRCTL(pipe));
9f31d1063b434c Tina Zhang 2017-11-23 424 plane->enabled = !!(val & SPRITE_ENABLE);
9f31d1063b434c Tina Zhang 2017-11-23 425 if (!plane->enabled)
9f31d1063b434c Tina Zhang 2017-11-23 426 return -ENODEV;
9f31d1063b434c Tina Zhang 2017-11-23 427
9f31d1063b434c Tina Zhang 2017-11-23 428 plane->tiled = !!(val & SPRITE_TILED);
9f31d1063b434c Tina Zhang 2017-11-23 429 color_order = !!(val & SPRITE_RGB_ORDER_RGBX);
9f31d1063b434c Tina Zhang 2017-11-23 @430 yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 02/14] drm/i915: Rename plane YUV order bits
@ 2021-12-06 13:13 ` kernel test robot
0 siblings, 0 replies; 48+ messages in thread
From: kernel test robot @ 2021-12-06 13:13 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 4195 bytes --]
Hi Ville,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to drm-tip/drm-tip v5.16-rc4 next-20211206]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Plane-register-cleanup/20211202-010520
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a012-20211130 (https://download.01.org/0day-ci/archive/20211206/202112062144.pndb6yAj-lkp(a)intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 4b553297ef3ee4dc2119d5429adf3072e90fac38)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/9e3683729de554eb265e6f4d8ec9cfc6eb591e52
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Plane-register-cleanup/20211202-010520
git checkout 9e3683729de554eb265e6f4d8ec9cfc6eb591e52
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:430:21: error: use of undeclared identifier 'SPRITE_YUV_BYTE_ORDER_MASK'
yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >>
^
1 error generated.
vim +/SPRITE_YUV_BYTE_ORDER_MASK +430 drivers/gpu/drm/i915/gvt/fb_decoder.c
9f31d1063b434c Tina Zhang 2017-11-23 401
9f31d1063b434c Tina Zhang 2017-11-23 402 /**
9f31d1063b434c Tina Zhang 2017-11-23 403 * intel_vgpu_decode_sprite_plane - Decode sprite plane
9f31d1063b434c Tina Zhang 2017-11-23 404 * @vgpu: input vgpu
9f31d1063b434c Tina Zhang 2017-11-23 405 * @plane: sprite plane to save decoded info
9f31d1063b434c Tina Zhang 2017-11-23 406 * This function is called for decoding plane
9f31d1063b434c Tina Zhang 2017-11-23 407 *
9f31d1063b434c Tina Zhang 2017-11-23 408 * Returns:
9f31d1063b434c Tina Zhang 2017-11-23 409 * 0 on success, non-zero if failed.
9f31d1063b434c Tina Zhang 2017-11-23 410 */
9f31d1063b434c Tina Zhang 2017-11-23 411 int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,
9f31d1063b434c Tina Zhang 2017-11-23 412 struct intel_vgpu_sprite_plane_format *plane)
9f31d1063b434c Tina Zhang 2017-11-23 413 {
9f31d1063b434c Tina Zhang 2017-11-23 414 u32 val, fmt;
9f31d1063b434c Tina Zhang 2017-11-23 415 u32 color_order, yuv_order;
9f31d1063b434c Tina Zhang 2017-11-23 416 int drm_format;
9f31d1063b434c Tina Zhang 2017-11-23 417 int pipe;
9f31d1063b434c Tina Zhang 2017-11-23 418
9f31d1063b434c Tina Zhang 2017-11-23 419 pipe = get_active_pipe(vgpu);
9f31d1063b434c Tina Zhang 2017-11-23 420 if (pipe >= I915_MAX_PIPES)
9f31d1063b434c Tina Zhang 2017-11-23 421 return -ENODEV;
9f31d1063b434c Tina Zhang 2017-11-23 422
90551a1296d4db Zhenyu Wang 2017-12-19 423 val = vgpu_vreg_t(vgpu, SPRCTL(pipe));
9f31d1063b434c Tina Zhang 2017-11-23 424 plane->enabled = !!(val & SPRITE_ENABLE);
9f31d1063b434c Tina Zhang 2017-11-23 425 if (!plane->enabled)
9f31d1063b434c Tina Zhang 2017-11-23 426 return -ENODEV;
9f31d1063b434c Tina Zhang 2017-11-23 427
9f31d1063b434c Tina Zhang 2017-11-23 428 plane->tiled = !!(val & SPRITE_TILED);
9f31d1063b434c Tina Zhang 2017-11-23 429 color_order = !!(val & SPRITE_RGB_ORDER_RGBX);
9f31d1063b434c Tina Zhang 2017-11-23 @430 yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 06/14] drm/i915: Use REG_BIT() & co. for universal plane bits
2021-12-01 15:25 ` [Intel-gfx] [PATCH 06/14] drm/i915: Use REG_BIT() & co. for universal " Ville Syrjala
@ 2021-12-06 15:57 ` kernel test robot
2021-12-06 15:57 ` kernel test robot
1 sibling, 0 replies; 48+ messages in thread
From: kernel test robot @ 2021-12-06 15:57 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: llvm, kbuild-all
Hi Ville,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to drm-tip/drm-tip v5.16-rc4 next-20211206]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Plane-register-cleanup/20211202-010520
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a012-20211130 (https://download.01.org/0day-ci/archive/20211206/202112062346.Pub0KCZK-lkp@intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 4b553297ef3ee4dc2119d5429adf3072e90fac38)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/50180d495a061c64528e2348a684037f5dc26e2e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Plane-register-cleanup/20211202-010520
git checkout 50180d495a061c64528e2348a684037f5dc26e2e
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:221:10: error: use of undeclared identifier 'PLANE_CTL_FORMAT_MASK'
val & PLANE_CTL_FORMAT_MASK,
^
drivers/gpu/drm/i915/gvt/fb_decoder.c:430:21: error: use of undeclared identifier 'SPRITE_YUV_BYTE_ORDER_MASK'
yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >>
^
2 errors generated.
vim +/PLANE_CTL_FORMAT_MASK +221 drivers/gpu/drm/i915/gvt/fb_decoder.c
9f31d1063b434c Tina Zhang 2017-11-23 192
9f31d1063b434c Tina Zhang 2017-11-23 193 /**
9f31d1063b434c Tina Zhang 2017-11-23 194 * intel_vgpu_decode_primary_plane - Decode primary plane
9f31d1063b434c Tina Zhang 2017-11-23 195 * @vgpu: input vgpu
9f31d1063b434c Tina Zhang 2017-11-23 196 * @plane: primary plane to save decoded info
9f31d1063b434c Tina Zhang 2017-11-23 197 * This function is called for decoding plane
9f31d1063b434c Tina Zhang 2017-11-23 198 *
9f31d1063b434c Tina Zhang 2017-11-23 199 * Returns:
9f31d1063b434c Tina Zhang 2017-11-23 200 * 0 on success, non-zero if failed.
9f31d1063b434c Tina Zhang 2017-11-23 201 */
9f31d1063b434c Tina Zhang 2017-11-23 202 int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
9f31d1063b434c Tina Zhang 2017-11-23 203 struct intel_vgpu_primary_plane_format *plane)
9f31d1063b434c Tina Zhang 2017-11-23 204 {
a61ac1e75105a0 Chris Wilson 2020-03-06 205 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
9f31d1063b434c Tina Zhang 2017-11-23 206 u32 val, fmt;
9f31d1063b434c Tina Zhang 2017-11-23 207 int pipe;
9f31d1063b434c Tina Zhang 2017-11-23 208
9f31d1063b434c Tina Zhang 2017-11-23 209 pipe = get_active_pipe(vgpu);
9f31d1063b434c Tina Zhang 2017-11-23 210 if (pipe >= I915_MAX_PIPES)
9f31d1063b434c Tina Zhang 2017-11-23 211 return -ENODEV;
9f31d1063b434c Tina Zhang 2017-11-23 212
90551a1296d4db Zhenyu Wang 2017-12-19 213 val = vgpu_vreg_t(vgpu, DSPCNTR(pipe));
9f31d1063b434c Tina Zhang 2017-11-23 214 plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
9f31d1063b434c Tina Zhang 2017-11-23 215 if (!plane->enabled)
9f31d1063b434c Tina Zhang 2017-11-23 216 return -ENODEV;
9f31d1063b434c Tina Zhang 2017-11-23 217
d8d123128c4872 Lucas De Marchi 2021-06-03 218 if (GRAPHICS_VER(dev_priv) >= 9) {
b244ffa15c8b1a Zhenyu Wang 2018-08-30 219 plane->tiled = val & PLANE_CTL_TILED_MASK;
9f31d1063b434c Tina Zhang 2017-11-23 220 fmt = skl_format_to_drm(
9f31d1063b434c Tina Zhang 2017-11-23 @221 val & PLANE_CTL_FORMAT_MASK,
9f31d1063b434c Tina Zhang 2017-11-23 222 val & PLANE_CTL_ORDER_RGBX,
9f31d1063b434c Tina Zhang 2017-11-23 223 val & PLANE_CTL_ALPHA_MASK,
9f31d1063b434c Tina Zhang 2017-11-23 224 val & PLANE_CTL_YUV422_ORDER_MASK);
461bd6227ede27 Gustavo A. R. Silva 2017-12-09 225
461bd6227ede27 Gustavo A. R. Silva 2017-12-09 226 if (fmt >= ARRAY_SIZE(skl_pixel_formats)) {
461bd6227ede27 Gustavo A. R. Silva 2017-12-09 227 gvt_vgpu_err("Out-of-bounds pixel format index\n");
461bd6227ede27 Gustavo A. R. Silva 2017-12-09 228 return -EINVAL;
461bd6227ede27 Gustavo A. R. Silva 2017-12-09 229 }
461bd6227ede27 Gustavo A. R. Silva 2017-12-09 230
9f31d1063b434c Tina Zhang 2017-11-23 231 plane->bpp = skl_pixel_formats[fmt].bpp;
9f31d1063b434c Tina Zhang 2017-11-23 232 plane->drm_format = skl_pixel_formats[fmt].drm_format;
9f31d1063b434c Tina Zhang 2017-11-23 233 } else {
a40fa231bb64b3 Tina Zhang 2018-12-03 234 plane->tiled = val & DISPPLANE_TILED;
9f31d1063b434c Tina Zhang 2017-11-23 235 fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK);
9f31d1063b434c Tina Zhang 2017-11-23 236 plane->bpp = bdw_pixel_formats[fmt].bpp;
9f31d1063b434c Tina Zhang 2017-11-23 237 plane->drm_format = bdw_pixel_formats[fmt].drm_format;
9f31d1063b434c Tina Zhang 2017-11-23 238 }
9f31d1063b434c Tina Zhang 2017-11-23 239
9f31d1063b434c Tina Zhang 2017-11-23 240 if (!plane->bpp) {
9f31d1063b434c Tina Zhang 2017-11-23 241 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
9f31d1063b434c Tina Zhang 2017-11-23 242 return -EINVAL;
9f31d1063b434c Tina Zhang 2017-11-23 243 }
9f31d1063b434c Tina Zhang 2017-11-23 244
9f31d1063b434c Tina Zhang 2017-11-23 245 plane->hw_format = fmt;
9f31d1063b434c Tina Zhang 2017-11-23 246
90551a1296d4db Zhenyu Wang 2017-12-19 247 plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK;
c25144098bee19 Xiong Zhang 2019-05-27 248 if (!vgpu_gmadr_is_valid(vgpu, plane->base))
9f31d1063b434c Tina Zhang 2017-11-23 249 return -EINVAL;
9f31d1063b434c Tina Zhang 2017-11-23 250
9f31d1063b434c Tina Zhang 2017-11-23 251 plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
9f31d1063b434c Tina Zhang 2017-11-23 252 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
a733390f9a7987 Xiong Zhang 2018-03-28 253 gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n",
a733390f9a7987 Xiong Zhang 2018-03-28 254 plane->base);
9f31d1063b434c Tina Zhang 2017-11-23 255 return -EINVAL;
9f31d1063b434c Tina Zhang 2017-11-23 256 }
9f31d1063b434c Tina Zhang 2017-11-23 257
b244ffa15c8b1a Zhenyu Wang 2018-08-30 258 plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,
d8d123128c4872 Lucas De Marchi 2021-06-03 259 (GRAPHICS_VER(dev_priv) >= 9) ?
4a136d590bd4c5 Tina Zhang 2017-11-28 260 (_PRI_PLANE_STRIDE_MASK >> 6) :
9f31d1063b434c Tina Zhang 2017-11-23 261 _PRI_PLANE_STRIDE_MASK, plane->bpp);
9f31d1063b434c Tina Zhang 2017-11-23 262
90551a1296d4db Zhenyu Wang 2017-12-19 263 plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>
9f31d1063b434c Tina Zhang 2017-11-23 264 _PIPE_H_SRCSZ_SHIFT;
9f31d1063b434c Tina Zhang 2017-11-23 265 plane->width += 1;
90551a1296d4db Zhenyu Wang 2017-12-19 266 plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) &
9f31d1063b434c Tina Zhang 2017-11-23 267 _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
9f31d1063b434c Tina Zhang 2017-11-23 268 plane->height += 1; /* raw height is one minus the real value */
9f31d1063b434c Tina Zhang 2017-11-23 269
90551a1296d4db Zhenyu Wang 2017-12-19 270 val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe));
9f31d1063b434c Tina Zhang 2017-11-23 271 plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
9f31d1063b434c Tina Zhang 2017-11-23 272 _PRI_PLANE_X_OFF_SHIFT;
9f31d1063b434c Tina Zhang 2017-11-23 273 plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
9f31d1063b434c Tina Zhang 2017-11-23 274 _PRI_PLANE_Y_OFF_SHIFT;
9f31d1063b434c Tina Zhang 2017-11-23 275
9f31d1063b434c Tina Zhang 2017-11-23 276 return 0;
9f31d1063b434c Tina Zhang 2017-11-23 277 }
9f31d1063b434c Tina Zhang 2017-11-23 278
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 06/14] drm/i915: Use REG_BIT() & co. for universal plane bits
@ 2021-12-06 15:57 ` kernel test robot
0 siblings, 0 replies; 48+ messages in thread
From: kernel test robot @ 2021-12-06 15:57 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 9388 bytes --]
Hi Ville,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to drm-tip/drm-tip v5.16-rc4 next-20211206]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Plane-register-cleanup/20211202-010520
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a012-20211130 (https://download.01.org/0day-ci/archive/20211206/202112062346.Pub0KCZK-lkp(a)intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 4b553297ef3ee4dc2119d5429adf3072e90fac38)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/50180d495a061c64528e2348a684037f5dc26e2e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Plane-register-cleanup/20211202-010520
git checkout 50180d495a061c64528e2348a684037f5dc26e2e
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:221:10: error: use of undeclared identifier 'PLANE_CTL_FORMAT_MASK'
val & PLANE_CTL_FORMAT_MASK,
^
drivers/gpu/drm/i915/gvt/fb_decoder.c:430:21: error: use of undeclared identifier 'SPRITE_YUV_BYTE_ORDER_MASK'
yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >>
^
2 errors generated.
vim +/PLANE_CTL_FORMAT_MASK +221 drivers/gpu/drm/i915/gvt/fb_decoder.c
9f31d1063b434c Tina Zhang 2017-11-23 192
9f31d1063b434c Tina Zhang 2017-11-23 193 /**
9f31d1063b434c Tina Zhang 2017-11-23 194 * intel_vgpu_decode_primary_plane - Decode primary plane
9f31d1063b434c Tina Zhang 2017-11-23 195 * @vgpu: input vgpu
9f31d1063b434c Tina Zhang 2017-11-23 196 * @plane: primary plane to save decoded info
9f31d1063b434c Tina Zhang 2017-11-23 197 * This function is called for decoding plane
9f31d1063b434c Tina Zhang 2017-11-23 198 *
9f31d1063b434c Tina Zhang 2017-11-23 199 * Returns:
9f31d1063b434c Tina Zhang 2017-11-23 200 * 0 on success, non-zero if failed.
9f31d1063b434c Tina Zhang 2017-11-23 201 */
9f31d1063b434c Tina Zhang 2017-11-23 202 int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
9f31d1063b434c Tina Zhang 2017-11-23 203 struct intel_vgpu_primary_plane_format *plane)
9f31d1063b434c Tina Zhang 2017-11-23 204 {
a61ac1e75105a0 Chris Wilson 2020-03-06 205 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
9f31d1063b434c Tina Zhang 2017-11-23 206 u32 val, fmt;
9f31d1063b434c Tina Zhang 2017-11-23 207 int pipe;
9f31d1063b434c Tina Zhang 2017-11-23 208
9f31d1063b434c Tina Zhang 2017-11-23 209 pipe = get_active_pipe(vgpu);
9f31d1063b434c Tina Zhang 2017-11-23 210 if (pipe >= I915_MAX_PIPES)
9f31d1063b434c Tina Zhang 2017-11-23 211 return -ENODEV;
9f31d1063b434c Tina Zhang 2017-11-23 212
90551a1296d4db Zhenyu Wang 2017-12-19 213 val = vgpu_vreg_t(vgpu, DSPCNTR(pipe));
9f31d1063b434c Tina Zhang 2017-11-23 214 plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
9f31d1063b434c Tina Zhang 2017-11-23 215 if (!plane->enabled)
9f31d1063b434c Tina Zhang 2017-11-23 216 return -ENODEV;
9f31d1063b434c Tina Zhang 2017-11-23 217
d8d123128c4872 Lucas De Marchi 2021-06-03 218 if (GRAPHICS_VER(dev_priv) >= 9) {
b244ffa15c8b1a Zhenyu Wang 2018-08-30 219 plane->tiled = val & PLANE_CTL_TILED_MASK;
9f31d1063b434c Tina Zhang 2017-11-23 220 fmt = skl_format_to_drm(
9f31d1063b434c Tina Zhang 2017-11-23 @221 val & PLANE_CTL_FORMAT_MASK,
9f31d1063b434c Tina Zhang 2017-11-23 222 val & PLANE_CTL_ORDER_RGBX,
9f31d1063b434c Tina Zhang 2017-11-23 223 val & PLANE_CTL_ALPHA_MASK,
9f31d1063b434c Tina Zhang 2017-11-23 224 val & PLANE_CTL_YUV422_ORDER_MASK);
461bd6227ede27 Gustavo A. R. Silva 2017-12-09 225
461bd6227ede27 Gustavo A. R. Silva 2017-12-09 226 if (fmt >= ARRAY_SIZE(skl_pixel_formats)) {
461bd6227ede27 Gustavo A. R. Silva 2017-12-09 227 gvt_vgpu_err("Out-of-bounds pixel format index\n");
461bd6227ede27 Gustavo A. R. Silva 2017-12-09 228 return -EINVAL;
461bd6227ede27 Gustavo A. R. Silva 2017-12-09 229 }
461bd6227ede27 Gustavo A. R. Silva 2017-12-09 230
9f31d1063b434c Tina Zhang 2017-11-23 231 plane->bpp = skl_pixel_formats[fmt].bpp;
9f31d1063b434c Tina Zhang 2017-11-23 232 plane->drm_format = skl_pixel_formats[fmt].drm_format;
9f31d1063b434c Tina Zhang 2017-11-23 233 } else {
a40fa231bb64b3 Tina Zhang 2018-12-03 234 plane->tiled = val & DISPPLANE_TILED;
9f31d1063b434c Tina Zhang 2017-11-23 235 fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK);
9f31d1063b434c Tina Zhang 2017-11-23 236 plane->bpp = bdw_pixel_formats[fmt].bpp;
9f31d1063b434c Tina Zhang 2017-11-23 237 plane->drm_format = bdw_pixel_formats[fmt].drm_format;
9f31d1063b434c Tina Zhang 2017-11-23 238 }
9f31d1063b434c Tina Zhang 2017-11-23 239
9f31d1063b434c Tina Zhang 2017-11-23 240 if (!plane->bpp) {
9f31d1063b434c Tina Zhang 2017-11-23 241 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
9f31d1063b434c Tina Zhang 2017-11-23 242 return -EINVAL;
9f31d1063b434c Tina Zhang 2017-11-23 243 }
9f31d1063b434c Tina Zhang 2017-11-23 244
9f31d1063b434c Tina Zhang 2017-11-23 245 plane->hw_format = fmt;
9f31d1063b434c Tina Zhang 2017-11-23 246
90551a1296d4db Zhenyu Wang 2017-12-19 247 plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK;
c25144098bee19 Xiong Zhang 2019-05-27 248 if (!vgpu_gmadr_is_valid(vgpu, plane->base))
9f31d1063b434c Tina Zhang 2017-11-23 249 return -EINVAL;
9f31d1063b434c Tina Zhang 2017-11-23 250
9f31d1063b434c Tina Zhang 2017-11-23 251 plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
9f31d1063b434c Tina Zhang 2017-11-23 252 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
a733390f9a7987 Xiong Zhang 2018-03-28 253 gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n",
a733390f9a7987 Xiong Zhang 2018-03-28 254 plane->base);
9f31d1063b434c Tina Zhang 2017-11-23 255 return -EINVAL;
9f31d1063b434c Tina Zhang 2017-11-23 256 }
9f31d1063b434c Tina Zhang 2017-11-23 257
b244ffa15c8b1a Zhenyu Wang 2018-08-30 258 plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,
d8d123128c4872 Lucas De Marchi 2021-06-03 259 (GRAPHICS_VER(dev_priv) >= 9) ?
4a136d590bd4c5 Tina Zhang 2017-11-28 260 (_PRI_PLANE_STRIDE_MASK >> 6) :
9f31d1063b434c Tina Zhang 2017-11-23 261 _PRI_PLANE_STRIDE_MASK, plane->bpp);
9f31d1063b434c Tina Zhang 2017-11-23 262
90551a1296d4db Zhenyu Wang 2017-12-19 263 plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>
9f31d1063b434c Tina Zhang 2017-11-23 264 _PIPE_H_SRCSZ_SHIFT;
9f31d1063b434c Tina Zhang 2017-11-23 265 plane->width += 1;
90551a1296d4db Zhenyu Wang 2017-12-19 266 plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) &
9f31d1063b434c Tina Zhang 2017-11-23 267 _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
9f31d1063b434c Tina Zhang 2017-11-23 268 plane->height += 1; /* raw height is one minus the real value */
9f31d1063b434c Tina Zhang 2017-11-23 269
90551a1296d4db Zhenyu Wang 2017-12-19 270 val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe));
9f31d1063b434c Tina Zhang 2017-11-23 271 plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
9f31d1063b434c Tina Zhang 2017-11-23 272 _PRI_PLANE_X_OFF_SHIFT;
9f31d1063b434c Tina Zhang 2017-11-23 273 plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
9f31d1063b434c Tina Zhang 2017-11-23 274 _PRI_PLANE_Y_OFF_SHIFT;
9f31d1063b434c Tina Zhang 2017-11-23 275
9f31d1063b434c Tina Zhang 2017-11-23 276 return 0;
9f31d1063b434c Tina Zhang 2017-11-23 277 }
9f31d1063b434c Tina Zhang 2017-11-23 278
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 07/14] drm/i915: Clean up pre-skl primary plane registers
2021-12-01 15:25 ` [Intel-gfx] [PATCH 07/14] drm/i915: Clean up pre-skl primary plane registers Ville Syrjala
@ 2021-12-06 19:22 ` kernel test robot
2022-01-12 20:12 ` Souza, Jose
1 sibling, 0 replies; 48+ messages in thread
From: kernel test robot @ 2021-12-06 19:22 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: llvm, kbuild-all
Hi Ville,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to drm-tip/drm-tip v5.16-rc4 next-20211206]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Plane-register-cleanup/20211202-010520
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a012-20211130 (https://download.01.org/0day-ci/archive/20211207/202112070356.mQALTRgQ-lkp@intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 4b553297ef3ee4dc2119d5429adf3072e90fac38)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/ec767426b169205cc023d38ea477e9bd38b93284
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Plane-register-cleanup/20211202-010520
git checkout ec767426b169205cc023d38ea477e9bd38b93284
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gvt/display.c:188:41: error: use of undeclared identifier 'DISPLAY_PLANE_ENABLE'
vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
^
drivers/gpu/drm/i915/gvt/display.c:499:40: error: use of undeclared identifier 'DISPLAY_PLANE_ENABLE'
vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
^
2 errors generated.
--
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:86:7: error: use of undeclared identifier 'DISPPLANE_8BPP'
case DISPPLANE_8BPP:
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:89:7: error: use of undeclared identifier 'DISPPLANE_BGRX565'
case DISPPLANE_BGRX565:
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:92:7: error: use of undeclared identifier 'DISPPLANE_BGRX888'
case DISPPLANE_BGRX888:
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:95:7: error: use of undeclared identifier 'DISPPLANE_RGBX101010'
case DISPPLANE_RGBX101010:
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:98:7: error: use of undeclared identifier 'DISPPLANE_BGRX101010'
case DISPPLANE_BGRX101010:
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:101:7: error: use of undeclared identifier 'DISPPLANE_RGBX888'
case DISPPLANE_RGBX888:
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:214:28: error: use of undeclared identifier 'DISPLAY_PLANE_ENABLE'
plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
^
drivers/gpu/drm/i915/gvt/fb_decoder.c:221:10: error: use of undeclared identifier 'PLANE_CTL_FORMAT_MASK'
val & PLANE_CTL_FORMAT_MASK,
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:234:24: error: use of undeclared identifier 'DISPPLANE_TILED'
plane->tiled = val & DISPPLANE_TILED;
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:235:33: error: use of undeclared identifier 'DISPPLANE_PIXFORMAT_MASK'
fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK);
^
drivers/gpu/drm/i915/gvt/fb_decoder.c:430:21: error: use of undeclared identifier 'SPRITE_YUV_BYTE_ORDER_MASK'
yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >>
^
11 errors generated.
vim +/DISPLAY_PLANE_ENABLE +188 drivers/gpu/drm/i915/gvt/display.c
04d348ae3f0aea Zhi Wang 2016-04-25 169
04d348ae3f0aea Zhi Wang 2016-04-25 170 static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
04d348ae3f0aea Zhi Wang 2016-04-25 171 {
a61ac1e75105a0 Chris Wilson 2020-03-06 172 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
65eff272330c72 Xiong Zhang 2018-03-28 173 int pipe;
65eff272330c72 Xiong Zhang 2018-03-28 174
72bad997287693 Colin Xu 2018-06-11 175 if (IS_BROXTON(dev_priv)) {
a5a8ef937cfa79 Colin Xu 2020-11-09 176 enum transcoder trans;
a5a8ef937cfa79 Colin Xu 2020-11-09 177 enum port port;
72bad997287693 Colin Xu 2018-06-11 178
a5a8ef937cfa79 Colin Xu 2020-11-09 179 /* Clear PIPE, DDI, PHY, HPD before setting new */
8625b221f307ef Ville Syrjälä 2020-10-28 180 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
e5abaab30eca51 Ville Syrjälä 2020-10-28 181 ~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) |
e5abaab30eca51 Ville Syrjälä 2020-10-28 182 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) |
e5abaab30eca51 Ville Syrjälä 2020-10-28 183 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));
72bad997287693 Colin Xu 2018-06-11 184
a5a8ef937cfa79 Colin Xu 2020-11-09 185 for_each_pipe(dev_priv, pipe) {
a5a8ef937cfa79 Colin Xu 2020-11-09 186 vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 187 ~(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE);
a5a8ef937cfa79 Colin Xu 2020-11-09 @188 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
a5a8ef937cfa79 Colin Xu 2020-11-09 189 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
a5a8ef937cfa79 Colin Xu 2020-11-09 190 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
a5a8ef937cfa79 Colin Xu 2020-11-09 191 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
a5a8ef937cfa79 Colin Xu 2020-11-09 192 }
a5a8ef937cfa79 Colin Xu 2020-11-09 193
a5a8ef937cfa79 Colin Xu 2020-11-09 194 for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) {
a5a8ef937cfa79 Colin Xu 2020-11-09 195 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 196 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
a5a8ef937cfa79 Colin Xu 2020-11-09 197 TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE);
a5a8ef937cfa79 Colin Xu 2020-11-09 198 }
a5a8ef937cfa79 Colin Xu 2020-11-09 199 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 200 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
a5a8ef937cfa79 Colin Xu 2020-11-09 201 TRANS_DDI_PORT_MASK);
a5a8ef937cfa79 Colin Xu 2020-11-09 202
a5a8ef937cfa79 Colin Xu 2020-11-09 203 for (port = PORT_A; port <= PORT_C; port++) {
a5a8ef937cfa79 Colin Xu 2020-11-09 204 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 205 ~BXT_PHY_LANE_ENABLED;
a5a8ef937cfa79 Colin Xu 2020-11-09 206 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 207 (BXT_PHY_CMNLANE_POWERDOWN_ACK |
a5a8ef937cfa79 Colin Xu 2020-11-09 208 BXT_PHY_LANE_POWERDOWN_ACK);
a5a8ef937cfa79 Colin Xu 2020-11-09 209
a5a8ef937cfa79 Colin Xu 2020-11-09 210 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 211 ~(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
a5a8ef937cfa79 Colin Xu 2020-11-09 212 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
a5a8ef937cfa79 Colin Xu 2020-11-09 213 PORT_PLL_ENABLE);
a5a8ef937cfa79 Colin Xu 2020-11-09 214
a5a8ef937cfa79 Colin Xu 2020-11-09 215 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 216 ~(DDI_INIT_DISPLAY_DETECTED |
a5a8ef937cfa79 Colin Xu 2020-11-09 217 DDI_BUF_CTL_ENABLE);
a5a8ef937cfa79 Colin Xu 2020-11-09 218 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;
a5a8ef937cfa79 Colin Xu 2020-11-09 219 }
4ceb06e7c336f4 Colin Xu 2020-12-01 220 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
4ceb06e7c336f4 Colin Xu 2020-12-01 221 ~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK);
4ceb06e7c336f4 Colin Xu 2020-12-01 222 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
4ceb06e7c336f4 Colin Xu 2020-12-01 223 ~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK);
4ceb06e7c336f4 Colin Xu 2020-12-01 224 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
4ceb06e7c336f4 Colin Xu 2020-12-01 225 ~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK);
4ceb06e7c336f4 Colin Xu 2020-12-01 226 /* No hpd_invert set in vgpu vbt, need to clear invert mask */
4ceb06e7c336f4 Colin Xu 2020-12-01 227 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;
4ceb06e7c336f4 Colin Xu 2020-12-01 228 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;
a5a8ef937cfa79 Colin Xu 2020-11-09 229
a5a8ef937cfa79 Colin Xu 2020-11-09 230 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));
a5a8ef937cfa79 Colin Xu 2020-11-09 231 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 232 ~PHY_POWER_GOOD;
a5a8ef937cfa79 Colin Xu 2020-11-09 233 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 234 ~PHY_POWER_GOOD;
a5a8ef937cfa79 Colin Xu 2020-11-09 235 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30);
a5a8ef937cfa79 Colin Xu 2020-11-09 236 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30);
a5a8ef937cfa79 Colin Xu 2020-11-09 237
a5a8ef937cfa79 Colin Xu 2020-11-09 238 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED;
a5a8ef937cfa79 Colin Xu 2020-11-09 239 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED;
a5a8ef937cfa79 Colin Xu 2020-11-09 240
a5a8ef937cfa79 Colin Xu 2020-11-09 241 /*
a5a8ef937cfa79 Colin Xu 2020-11-09 242 * Only 1 PIPE enabled in current vGPU display and PIPE_A is
a5a8ef937cfa79 Colin Xu 2020-11-09 243 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
a5a8ef937cfa79 Colin Xu 2020-11-09 244 * TRANSCODER_A can be enabled. PORT_x depends on the input of
a5a8ef937cfa79 Colin Xu 2020-11-09 245 * setup_virtual_dp_monitor.
a5a8ef937cfa79 Colin Xu 2020-11-09 246 */
a5a8ef937cfa79 Colin Xu 2020-11-09 247 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
a5a8ef937cfa79 Colin Xu 2020-11-09 248 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE;
a5a8ef937cfa79 Colin Xu 2020-11-09 249
a5a8ef937cfa79 Colin Xu 2020-11-09 250 /*
a5a8ef937cfa79 Colin Xu 2020-11-09 251 * Golden M/N are calculated based on:
a5a8ef937cfa79 Colin Xu 2020-11-09 252 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
a5a8ef937cfa79 Colin Xu 2020-11-09 253 * DP link clk 1620 MHz and non-constant_n.
a5a8ef937cfa79 Colin Xu 2020-11-09 254 * TODO: calculate DP link symbol clk and stream clk m/n.
a5a8ef937cfa79 Colin Xu 2020-11-09 255 */
a5a8ef937cfa79 Colin Xu 2020-11-09 256 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
a5a8ef937cfa79 Colin Xu 2020-11-09 257 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
a5a8ef937cfa79 Colin Xu 2020-11-09 258 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
a5a8ef937cfa79 Colin Xu 2020-11-09 259 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
a5a8ef937cfa79 Colin Xu 2020-11-09 260 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
a5a8ef937cfa79 Colin Xu 2020-11-09 261
a5a8ef937cfa79 Colin Xu 2020-11-09 262 /* Enable per-DDI/PORT vreg */
72bad997287693 Colin Xu 2018-06-11 263 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
a5a8ef937cfa79 Colin Xu 2020-11-09 264 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1);
a5a8ef937cfa79 Colin Xu 2020-11-09 265 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 266 PHY_POWER_GOOD;
a5a8ef937cfa79 Colin Xu 2020-11-09 267 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 268 BIT(30);
a5a8ef937cfa79 Colin Xu 2020-11-09 269 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 270 BXT_PHY_LANE_ENABLED;
a5a8ef937cfa79 Colin Xu 2020-11-09 271 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 272 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
a5a8ef937cfa79 Colin Xu 2020-11-09 273 BXT_PHY_LANE_POWERDOWN_ACK);
a5a8ef937cfa79 Colin Xu 2020-11-09 274 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 275 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
a5a8ef937cfa79 Colin Xu 2020-11-09 276 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
a5a8ef937cfa79 Colin Xu 2020-11-09 277 PORT_PLL_ENABLE);
a5a8ef937cfa79 Colin Xu 2020-11-09 278 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 279 (DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED);
a5a8ef937cfa79 Colin Xu 2020-11-09 280 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 281 ~DDI_BUF_IS_IDLE;
a5a8ef937cfa79 Colin Xu 2020-11-09 282 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 283 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
a5a8ef937cfa79 Colin Xu 2020-11-09 284 TRANS_DDI_FUNC_ENABLE);
4ceb06e7c336f4 Colin Xu 2020-12-01 285 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
4ceb06e7c336f4 Colin Xu 2020-12-01 286 PORTA_HOTPLUG_ENABLE;
72bad997287693 Colin Xu 2018-06-11 287 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
e5abaab30eca51 Ville Syrjälä 2020-10-28 288 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
72bad997287693 Colin Xu 2018-06-11 289 }
72bad997287693 Colin Xu 2018-06-11 290
72bad997287693 Colin Xu 2018-06-11 291 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
a5a8ef937cfa79 Colin Xu 2020-11-09 292 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
a5a8ef937cfa79 Colin Xu 2020-11-09 293 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
a5a8ef937cfa79 Colin Xu 2020-11-09 294 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 295 PHY_POWER_GOOD;
a5a8ef937cfa79 Colin Xu 2020-11-09 296 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 297 BIT(30);
a5a8ef937cfa79 Colin Xu 2020-11-09 298 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 299 BXT_PHY_LANE_ENABLED;
a5a8ef937cfa79 Colin Xu 2020-11-09 300 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 301 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
a5a8ef937cfa79 Colin Xu 2020-11-09 302 BXT_PHY_LANE_POWERDOWN_ACK);
a5a8ef937cfa79 Colin Xu 2020-11-09 303 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 304 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
a5a8ef937cfa79 Colin Xu 2020-11-09 305 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
a5a8ef937cfa79 Colin Xu 2020-11-09 306 PORT_PLL_ENABLE);
a5a8ef937cfa79 Colin Xu 2020-11-09 307 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 308 DDI_BUF_CTL_ENABLE;
a5a8ef937cfa79 Colin Xu 2020-11-09 309 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 310 ~DDI_BUF_IS_IDLE;
a5a8ef937cfa79 Colin Xu 2020-11-09 311 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 312 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
a5a8ef937cfa79 Colin Xu 2020-11-09 313 (PORT_B << TRANS_DDI_PORT_SHIFT) |
a5a8ef937cfa79 Colin Xu 2020-11-09 314 TRANS_DDI_FUNC_ENABLE);
4ceb06e7c336f4 Colin Xu 2020-12-01 315 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
4ceb06e7c336f4 Colin Xu 2020-12-01 316 PORTB_HOTPLUG_ENABLE;
72bad997287693 Colin Xu 2018-06-11 317 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
e5abaab30eca51 Ville Syrjälä 2020-10-28 318 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
72bad997287693 Colin Xu 2018-06-11 319 }
72bad997287693 Colin Xu 2018-06-11 320
72bad997287693 Colin Xu 2018-06-11 321 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
a5a8ef937cfa79 Colin Xu 2020-11-09 322 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
a5a8ef937cfa79 Colin Xu 2020-11-09 323 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
a5a8ef937cfa79 Colin Xu 2020-11-09 324 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 325 PHY_POWER_GOOD;
a5a8ef937cfa79 Colin Xu 2020-11-09 326 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 327 BIT(30);
a5a8ef937cfa79 Colin Xu 2020-11-09 328 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 329 BXT_PHY_LANE_ENABLED;
a5a8ef937cfa79 Colin Xu 2020-11-09 330 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 331 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
a5a8ef937cfa79 Colin Xu 2020-11-09 332 BXT_PHY_LANE_POWERDOWN_ACK);
a5a8ef937cfa79 Colin Xu 2020-11-09 333 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 334 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
a5a8ef937cfa79 Colin Xu 2020-11-09 335 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
a5a8ef937cfa79 Colin Xu 2020-11-09 336 PORT_PLL_ENABLE);
a5a8ef937cfa79 Colin Xu 2020-11-09 337 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 338 DDI_BUF_CTL_ENABLE;
a5a8ef937cfa79 Colin Xu 2020-11-09 339 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 340 ~DDI_BUF_IS_IDLE;
a5a8ef937cfa79 Colin Xu 2020-11-09 341 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 342 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
a5a8ef937cfa79 Colin Xu 2020-11-09 343 (PORT_B << TRANS_DDI_PORT_SHIFT) |
a5a8ef937cfa79 Colin Xu 2020-11-09 344 TRANS_DDI_FUNC_ENABLE);
4ceb06e7c336f4 Colin Xu 2020-12-01 345 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
4ceb06e7c336f4 Colin Xu 2020-12-01 346 PORTC_HOTPLUG_ENABLE;
72bad997287693 Colin Xu 2018-06-11 347 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
e5abaab30eca51 Ville Syrjälä 2020-10-28 348 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
72bad997287693 Colin Xu 2018-06-11 349 }
72bad997287693 Colin Xu 2018-06-11 350
72bad997287693 Colin Xu 2018-06-11 351 return;
72bad997287693 Colin Xu 2018-06-11 352 }
72bad997287693 Colin Xu 2018-06-11 353
90551a1296d4db Zhenyu Wang 2017-12-19 354 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
04d348ae3f0aea Zhi Wang 2016-04-25 355 SDE_PORTC_HOTPLUG_CPT |
04d348ae3f0aea Zhi Wang 2016-04-25 356 SDE_PORTD_HOTPLUG_CPT);
04d348ae3f0aea Zhi Wang 2016-04-25 357
5f4ae2704d59ee Chris Wilson 2020-06-02 358 if (IS_SKYLAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson 2020-06-02 359 IS_KABYLAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson 2020-06-02 360 IS_COFFEELAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson 2020-06-02 361 IS_COMETLAKE(dev_priv)) {
90551a1296d4db Zhenyu Wang 2017-12-19 362 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
04d348ae3f0aea Zhi Wang 2016-04-25 363 SDE_PORTE_HOTPLUG_SPT);
90551a1296d4db Zhenyu Wang 2017-12-19 364 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
88a16b64c3f48d Weinan Li 2017-03-17 365 SKL_FUSE_DOWNLOAD_STATUS |
b2891eb2531e5e Imre Deak 2017-07-11 366 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
b2891eb2531e5e Imre Deak 2017-07-11 367 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
b2891eb2531e5e Imre Deak 2017-07-11 368 SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
f965b68188ab59 Colin Xu 2020-05-08 369 /*
f965b68188ab59 Colin Xu 2020-05-08 370 * Only 1 PIPE enabled in current vGPU display and PIPE_A is
f965b68188ab59 Colin Xu 2020-05-08 371 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
f965b68188ab59 Colin Xu 2020-05-08 372 * TRANSCODER_A can be enabled. PORT_x depends on the input of
f965b68188ab59 Colin Xu 2020-05-08 373 * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x
f965b68188ab59 Colin Xu 2020-05-08 374 * so we fixed to DPLL0 here.
f965b68188ab59 Colin Xu 2020-05-08 375 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode
f965b68188ab59 Colin Xu 2020-05-08 376 */
f965b68188ab59 Colin Xu 2020-05-08 377 vgpu_vreg_t(vgpu, DPLL_CTRL1) =
f965b68188ab59 Colin Xu 2020-05-08 378 DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0);
f965b68188ab59 Colin Xu 2020-05-08 379 vgpu_vreg_t(vgpu, DPLL_CTRL1) |=
f965b68188ab59 Colin Xu 2020-05-08 380 DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0);
f965b68188ab59 Colin Xu 2020-05-08 381 vgpu_vreg_t(vgpu, LCPLL1_CTL) =
f965b68188ab59 Colin Xu 2020-05-08 382 LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK;
f965b68188ab59 Colin Xu 2020-05-08 383 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);
f965b68188ab59 Colin Xu 2020-05-08 384 /*
f965b68188ab59 Colin Xu 2020-05-08 385 * Golden M/N are calculated based on:
f965b68188ab59 Colin Xu 2020-05-08 386 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
f965b68188ab59 Colin Xu 2020-05-08 387 * DP link clk 1620 MHz and non-constant_n.
f965b68188ab59 Colin Xu 2020-05-08 388 * TODO: calculate DP link symbol clk and stream clk m/n.
f965b68188ab59 Colin Xu 2020-05-08 389 */
f965b68188ab59 Colin Xu 2020-05-08 390 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
f965b68188ab59 Colin Xu 2020-05-08 391 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
f965b68188ab59 Colin Xu 2020-05-08 392 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
f965b68188ab59 Colin Xu 2020-05-08 393 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
f965b68188ab59 Colin Xu 2020-05-08 394 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
88a16b64c3f48d Weinan Li 2017-03-17 395 }
04d348ae3f0aea Zhi Wang 2016-04-25 396
858b0f571d3091 Bing Niu 2017-02-28 397 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
f965b68188ab59 Colin Xu 2020-05-08 398 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
f965b68188ab59 Colin Xu 2020-05-08 399 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B);
f965b68188ab59 Colin Xu 2020-05-08 400 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu 2020-05-08 401 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B);
f965b68188ab59 Colin Xu 2020-05-08 402 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu 2020-05-08 403 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B);
90551a1296d4db Zhenyu Wang 2017-12-19 404 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
90551a1296d4db Zhenyu Wang 2017-12-19 405 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
efa69d734adbf8 Pei Zhang 2017-04-07 406 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
efa69d734adbf8 Pei Zhang 2017-04-07 407 TRANS_DDI_PORT_MASK);
90551a1296d4db Zhenyu Wang 2017-12-19 408 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
75db1a5b2aea2a Tina Zhang 2020-03-17 409 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
efa69d734adbf8 Pei Zhang 2017-04-07 410 (PORT_B << TRANS_DDI_PORT_SHIFT) |
efa69d734adbf8 Pei Zhang 2017-04-07 411 TRANS_DDI_FUNC_ENABLE);
295a0d0b55269f Xiong Zhang 2017-06-20 412 if (IS_BROADWELL(dev_priv)) {
90551a1296d4db Zhenyu Wang 2017-12-19 413 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
295a0d0b55269f Xiong Zhang 2017-06-20 414 ~PORT_CLK_SEL_MASK;
90551a1296d4db Zhenyu Wang 2017-12-19 415 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
295a0d0b55269f Xiong Zhang 2017-06-20 416 PORT_CLK_SEL_LCPLL_810;
295a0d0b55269f Xiong Zhang 2017-06-20 417 }
90551a1296d4db Zhenyu Wang 2017-12-19 418 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
90551a1296d4db Zhenyu Wang 2017-12-19 419 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
90551a1296d4db Zhenyu Wang 2017-12-19 420 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
858b0f571d3091 Bing Niu 2017-02-28 421 }
04d348ae3f0aea Zhi Wang 2016-04-25 422
858b0f571d3091 Bing Niu 2017-02-28 423 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
f965b68188ab59 Colin Xu 2020-05-08 424 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
f965b68188ab59 Colin Xu 2020-05-08 425 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C);
f965b68188ab59 Colin Xu 2020-05-08 426 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu 2020-05-08 427 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C);
f965b68188ab59 Colin Xu 2020-05-08 428 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu 2020-05-08 429 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C);
90551a1296d4db Zhenyu Wang 2017-12-19 430 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
90551a1296d4db Zhenyu Wang 2017-12-19 431 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
efa69d734adbf8 Pei Zhang 2017-04-07 432 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
efa69d734adbf8 Pei Zhang 2017-04-07 433 TRANS_DDI_PORT_MASK);
90551a1296d4db Zhenyu Wang 2017-12-19 434 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
75db1a5b2aea2a Tina Zhang 2020-03-17 435 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
efa69d734adbf8 Pei Zhang 2017-04-07 436 (PORT_C << TRANS_DDI_PORT_SHIFT) |
efa69d734adbf8 Pei Zhang 2017-04-07 437 TRANS_DDI_FUNC_ENABLE);
295a0d0b55269f Xiong Zhang 2017-06-20 438 if (IS_BROADWELL(dev_priv)) {
90551a1296d4db Zhenyu Wang 2017-12-19 439 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
295a0d0b55269f Xiong Zhang 2017-06-20 440 ~PORT_CLK_SEL_MASK;
90551a1296d4db Zhenyu Wang 2017-12-19 441 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
295a0d0b55269f Xiong Zhang 2017-06-20 442 PORT_CLK_SEL_LCPLL_810;
295a0d0b55269f Xiong Zhang 2017-06-20 443 }
90551a1296d4db Zhenyu Wang 2017-12-19 444 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
90551a1296d4db Zhenyu Wang 2017-12-19 445 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
90551a1296d4db Zhenyu Wang 2017-12-19 446 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
858b0f571d3091 Bing Niu 2017-02-28 447 }
04d348ae3f0aea Zhi Wang 2016-04-25 448
858b0f571d3091 Bing Niu 2017-02-28 449 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
f965b68188ab59 Colin Xu 2020-05-08 450 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
f965b68188ab59 Colin Xu 2020-05-08 451 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D);
f965b68188ab59 Colin Xu 2020-05-08 452 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu 2020-05-08 453 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D);
f965b68188ab59 Colin Xu 2020-05-08 454 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu 2020-05-08 455 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D);
90551a1296d4db Zhenyu Wang 2017-12-19 456 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
90551a1296d4db Zhenyu Wang 2017-12-19 457 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
efa69d734adbf8 Pei Zhang 2017-04-07 458 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
efa69d734adbf8 Pei Zhang 2017-04-07 459 TRANS_DDI_PORT_MASK);
90551a1296d4db Zhenyu Wang 2017-12-19 460 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
75db1a5b2aea2a Tina Zhang 2020-03-17 461 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
efa69d734adbf8 Pei Zhang 2017-04-07 462 (PORT_D << TRANS_DDI_PORT_SHIFT) |
efa69d734adbf8 Pei Zhang 2017-04-07 463 TRANS_DDI_FUNC_ENABLE);
295a0d0b55269f Xiong Zhang 2017-06-20 464 if (IS_BROADWELL(dev_priv)) {
90551a1296d4db Zhenyu Wang 2017-12-19 465 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
295a0d0b55269f Xiong Zhang 2017-06-20 466 ~PORT_CLK_SEL_MASK;
90551a1296d4db Zhenyu Wang 2017-12-19 467 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
295a0d0b55269f Xiong Zhang 2017-06-20 468 PORT_CLK_SEL_LCPLL_810;
295a0d0b55269f Xiong Zhang 2017-06-20 469 }
90551a1296d4db Zhenyu Wang 2017-12-19 470 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
90551a1296d4db Zhenyu Wang 2017-12-19 471 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
90551a1296d4db Zhenyu Wang 2017-12-19 472 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
858b0f571d3091 Bing Niu 2017-02-28 473 }
04d348ae3f0aea Zhi Wang 2016-04-25 474
5f4ae2704d59ee Chris Wilson 2020-06-02 475 if ((IS_SKYLAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson 2020-06-02 476 IS_KABYLAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson 2020-06-02 477 IS_COFFEELAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson 2020-06-02 478 IS_COMETLAKE(dev_priv)) &&
04d348ae3f0aea Zhi Wang 2016-04-25 479 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
90551a1296d4db Zhenyu Wang 2017-12-19 480 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
04d348ae3f0aea Zhi Wang 2016-04-25 481 }
04d348ae3f0aea Zhi Wang 2016-04-25 482
04d348ae3f0aea Zhi Wang 2016-04-25 483 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
04d348ae3f0aea Zhi Wang 2016-04-25 484 if (IS_BROADWELL(dev_priv))
90551a1296d4db Zhenyu Wang 2017-12-19 485 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
e5abaab30eca51 Ville Syrjälä 2020-10-28 486 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
04d348ae3f0aea Zhi Wang 2016-04-25 487 else
90551a1296d4db Zhenyu Wang 2017-12-19 488 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
858b0f571d3091 Bing Niu 2017-02-28 489
90551a1296d4db Zhenyu Wang 2017-12-19 490 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
04d348ae3f0aea Zhi Wang 2016-04-25 491 }
75e64ff2c2f5ce Xiong Zhang 2017-06-28 492
75e64ff2c2f5ce Xiong Zhang 2017-06-28 493 /* Clear host CRT status, so guest couldn't detect this host CRT. */
75e64ff2c2f5ce Xiong Zhang 2017-06-28 494 if (IS_BROADWELL(dev_priv))
90551a1296d4db Zhenyu Wang 2017-12-19 495 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
4e889d62b89d00 Xiaolin Zhang 2017-12-05 496
65eff272330c72 Xiong Zhang 2018-03-28 497 /* Disable Primary/Sprite/Cursor plane */
65eff272330c72 Xiong Zhang 2018-03-28 498 for_each_pipe(dev_priv, pipe) {
65eff272330c72 Xiong Zhang 2018-03-28 499 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
65eff272330c72 Xiong Zhang 2018-03-28 500 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
b99b9ec1d374fd Ville Syrjälä 2018-01-31 501 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
b99b9ec1d374fd Ville Syrjälä 2018-01-31 502 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
65eff272330c72 Xiong Zhang 2018-03-28 503 }
65eff272330c72 Xiong Zhang 2018-03-28 504
90551a1296d4db Zhenyu Wang 2017-12-19 505 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
04d348ae3f0aea Zhi Wang 2016-04-25 506 }
04d348ae3f0aea Zhi Wang 2016-04-25 507
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 07/14] drm/i915: Clean up pre-skl primary plane registers
@ 2021-12-06 19:22 ` kernel test robot
0 siblings, 0 replies; 48+ messages in thread
From: kernel test robot @ 2021-12-06 19:22 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 33252 bytes --]
Hi Ville,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to drm-tip/drm-tip v5.16-rc4 next-20211206]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Plane-register-cleanup/20211202-010520
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a012-20211130 (https://download.01.org/0day-ci/archive/20211207/202112070356.mQALTRgQ-lkp(a)intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 4b553297ef3ee4dc2119d5429adf3072e90fac38)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/ec767426b169205cc023d38ea477e9bd38b93284
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Plane-register-cleanup/20211202-010520
git checkout ec767426b169205cc023d38ea477e9bd38b93284
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gvt/display.c:188:41: error: use of undeclared identifier 'DISPLAY_PLANE_ENABLE'
vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
^
drivers/gpu/drm/i915/gvt/display.c:499:40: error: use of undeclared identifier 'DISPLAY_PLANE_ENABLE'
vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
^
2 errors generated.
--
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:86:7: error: use of undeclared identifier 'DISPPLANE_8BPP'
case DISPPLANE_8BPP:
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:89:7: error: use of undeclared identifier 'DISPPLANE_BGRX565'
case DISPPLANE_BGRX565:
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:92:7: error: use of undeclared identifier 'DISPPLANE_BGRX888'
case DISPPLANE_BGRX888:
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:95:7: error: use of undeclared identifier 'DISPPLANE_RGBX101010'
case DISPPLANE_RGBX101010:
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:98:7: error: use of undeclared identifier 'DISPPLANE_BGRX101010'
case DISPPLANE_BGRX101010:
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:101:7: error: use of undeclared identifier 'DISPPLANE_RGBX888'
case DISPPLANE_RGBX888:
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:214:28: error: use of undeclared identifier 'DISPLAY_PLANE_ENABLE'
plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
^
drivers/gpu/drm/i915/gvt/fb_decoder.c:221:10: error: use of undeclared identifier 'PLANE_CTL_FORMAT_MASK'
val & PLANE_CTL_FORMAT_MASK,
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:234:24: error: use of undeclared identifier 'DISPPLANE_TILED'
plane->tiled = val & DISPPLANE_TILED;
^
>> drivers/gpu/drm/i915/gvt/fb_decoder.c:235:33: error: use of undeclared identifier 'DISPPLANE_PIXFORMAT_MASK'
fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK);
^
drivers/gpu/drm/i915/gvt/fb_decoder.c:430:21: error: use of undeclared identifier 'SPRITE_YUV_BYTE_ORDER_MASK'
yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >>
^
11 errors generated.
vim +/DISPLAY_PLANE_ENABLE +188 drivers/gpu/drm/i915/gvt/display.c
04d348ae3f0aea Zhi Wang 2016-04-25 169
04d348ae3f0aea Zhi Wang 2016-04-25 170 static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
04d348ae3f0aea Zhi Wang 2016-04-25 171 {
a61ac1e75105a0 Chris Wilson 2020-03-06 172 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
65eff272330c72 Xiong Zhang 2018-03-28 173 int pipe;
65eff272330c72 Xiong Zhang 2018-03-28 174
72bad997287693 Colin Xu 2018-06-11 175 if (IS_BROXTON(dev_priv)) {
a5a8ef937cfa79 Colin Xu 2020-11-09 176 enum transcoder trans;
a5a8ef937cfa79 Colin Xu 2020-11-09 177 enum port port;
72bad997287693 Colin Xu 2018-06-11 178
a5a8ef937cfa79 Colin Xu 2020-11-09 179 /* Clear PIPE, DDI, PHY, HPD before setting new */
8625b221f307ef Ville Syrjälä 2020-10-28 180 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
e5abaab30eca51 Ville Syrjälä 2020-10-28 181 ~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) |
e5abaab30eca51 Ville Syrjälä 2020-10-28 182 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) |
e5abaab30eca51 Ville Syrjälä 2020-10-28 183 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));
72bad997287693 Colin Xu 2018-06-11 184
a5a8ef937cfa79 Colin Xu 2020-11-09 185 for_each_pipe(dev_priv, pipe) {
a5a8ef937cfa79 Colin Xu 2020-11-09 186 vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 187 ~(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE);
a5a8ef937cfa79 Colin Xu 2020-11-09 @188 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
a5a8ef937cfa79 Colin Xu 2020-11-09 189 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
a5a8ef937cfa79 Colin Xu 2020-11-09 190 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
a5a8ef937cfa79 Colin Xu 2020-11-09 191 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
a5a8ef937cfa79 Colin Xu 2020-11-09 192 }
a5a8ef937cfa79 Colin Xu 2020-11-09 193
a5a8ef937cfa79 Colin Xu 2020-11-09 194 for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) {
a5a8ef937cfa79 Colin Xu 2020-11-09 195 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 196 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
a5a8ef937cfa79 Colin Xu 2020-11-09 197 TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE);
a5a8ef937cfa79 Colin Xu 2020-11-09 198 }
a5a8ef937cfa79 Colin Xu 2020-11-09 199 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 200 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
a5a8ef937cfa79 Colin Xu 2020-11-09 201 TRANS_DDI_PORT_MASK);
a5a8ef937cfa79 Colin Xu 2020-11-09 202
a5a8ef937cfa79 Colin Xu 2020-11-09 203 for (port = PORT_A; port <= PORT_C; port++) {
a5a8ef937cfa79 Colin Xu 2020-11-09 204 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 205 ~BXT_PHY_LANE_ENABLED;
a5a8ef937cfa79 Colin Xu 2020-11-09 206 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 207 (BXT_PHY_CMNLANE_POWERDOWN_ACK |
a5a8ef937cfa79 Colin Xu 2020-11-09 208 BXT_PHY_LANE_POWERDOWN_ACK);
a5a8ef937cfa79 Colin Xu 2020-11-09 209
a5a8ef937cfa79 Colin Xu 2020-11-09 210 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 211 ~(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
a5a8ef937cfa79 Colin Xu 2020-11-09 212 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
a5a8ef937cfa79 Colin Xu 2020-11-09 213 PORT_PLL_ENABLE);
a5a8ef937cfa79 Colin Xu 2020-11-09 214
a5a8ef937cfa79 Colin Xu 2020-11-09 215 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 216 ~(DDI_INIT_DISPLAY_DETECTED |
a5a8ef937cfa79 Colin Xu 2020-11-09 217 DDI_BUF_CTL_ENABLE);
a5a8ef937cfa79 Colin Xu 2020-11-09 218 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;
a5a8ef937cfa79 Colin Xu 2020-11-09 219 }
4ceb06e7c336f4 Colin Xu 2020-12-01 220 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
4ceb06e7c336f4 Colin Xu 2020-12-01 221 ~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK);
4ceb06e7c336f4 Colin Xu 2020-12-01 222 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
4ceb06e7c336f4 Colin Xu 2020-12-01 223 ~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK);
4ceb06e7c336f4 Colin Xu 2020-12-01 224 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
4ceb06e7c336f4 Colin Xu 2020-12-01 225 ~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK);
4ceb06e7c336f4 Colin Xu 2020-12-01 226 /* No hpd_invert set in vgpu vbt, need to clear invert mask */
4ceb06e7c336f4 Colin Xu 2020-12-01 227 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;
4ceb06e7c336f4 Colin Xu 2020-12-01 228 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;
a5a8ef937cfa79 Colin Xu 2020-11-09 229
a5a8ef937cfa79 Colin Xu 2020-11-09 230 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));
a5a8ef937cfa79 Colin Xu 2020-11-09 231 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 232 ~PHY_POWER_GOOD;
a5a8ef937cfa79 Colin Xu 2020-11-09 233 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 234 ~PHY_POWER_GOOD;
a5a8ef937cfa79 Colin Xu 2020-11-09 235 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30);
a5a8ef937cfa79 Colin Xu 2020-11-09 236 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30);
a5a8ef937cfa79 Colin Xu 2020-11-09 237
a5a8ef937cfa79 Colin Xu 2020-11-09 238 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED;
a5a8ef937cfa79 Colin Xu 2020-11-09 239 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED;
a5a8ef937cfa79 Colin Xu 2020-11-09 240
a5a8ef937cfa79 Colin Xu 2020-11-09 241 /*
a5a8ef937cfa79 Colin Xu 2020-11-09 242 * Only 1 PIPE enabled in current vGPU display and PIPE_A is
a5a8ef937cfa79 Colin Xu 2020-11-09 243 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
a5a8ef937cfa79 Colin Xu 2020-11-09 244 * TRANSCODER_A can be enabled. PORT_x depends on the input of
a5a8ef937cfa79 Colin Xu 2020-11-09 245 * setup_virtual_dp_monitor.
a5a8ef937cfa79 Colin Xu 2020-11-09 246 */
a5a8ef937cfa79 Colin Xu 2020-11-09 247 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
a5a8ef937cfa79 Colin Xu 2020-11-09 248 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE;
a5a8ef937cfa79 Colin Xu 2020-11-09 249
a5a8ef937cfa79 Colin Xu 2020-11-09 250 /*
a5a8ef937cfa79 Colin Xu 2020-11-09 251 * Golden M/N are calculated based on:
a5a8ef937cfa79 Colin Xu 2020-11-09 252 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
a5a8ef937cfa79 Colin Xu 2020-11-09 253 * DP link clk 1620 MHz and non-constant_n.
a5a8ef937cfa79 Colin Xu 2020-11-09 254 * TODO: calculate DP link symbol clk and stream clk m/n.
a5a8ef937cfa79 Colin Xu 2020-11-09 255 */
a5a8ef937cfa79 Colin Xu 2020-11-09 256 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
a5a8ef937cfa79 Colin Xu 2020-11-09 257 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
a5a8ef937cfa79 Colin Xu 2020-11-09 258 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
a5a8ef937cfa79 Colin Xu 2020-11-09 259 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
a5a8ef937cfa79 Colin Xu 2020-11-09 260 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
a5a8ef937cfa79 Colin Xu 2020-11-09 261
a5a8ef937cfa79 Colin Xu 2020-11-09 262 /* Enable per-DDI/PORT vreg */
72bad997287693 Colin Xu 2018-06-11 263 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
a5a8ef937cfa79 Colin Xu 2020-11-09 264 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1);
a5a8ef937cfa79 Colin Xu 2020-11-09 265 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 266 PHY_POWER_GOOD;
a5a8ef937cfa79 Colin Xu 2020-11-09 267 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 268 BIT(30);
a5a8ef937cfa79 Colin Xu 2020-11-09 269 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 270 BXT_PHY_LANE_ENABLED;
a5a8ef937cfa79 Colin Xu 2020-11-09 271 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 272 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
a5a8ef937cfa79 Colin Xu 2020-11-09 273 BXT_PHY_LANE_POWERDOWN_ACK);
a5a8ef937cfa79 Colin Xu 2020-11-09 274 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 275 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
a5a8ef937cfa79 Colin Xu 2020-11-09 276 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
a5a8ef937cfa79 Colin Xu 2020-11-09 277 PORT_PLL_ENABLE);
a5a8ef937cfa79 Colin Xu 2020-11-09 278 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 279 (DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED);
a5a8ef937cfa79 Colin Xu 2020-11-09 280 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 281 ~DDI_BUF_IS_IDLE;
a5a8ef937cfa79 Colin Xu 2020-11-09 282 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 283 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
a5a8ef937cfa79 Colin Xu 2020-11-09 284 TRANS_DDI_FUNC_ENABLE);
4ceb06e7c336f4 Colin Xu 2020-12-01 285 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
4ceb06e7c336f4 Colin Xu 2020-12-01 286 PORTA_HOTPLUG_ENABLE;
72bad997287693 Colin Xu 2018-06-11 287 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
e5abaab30eca51 Ville Syrjälä 2020-10-28 288 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
72bad997287693 Colin Xu 2018-06-11 289 }
72bad997287693 Colin Xu 2018-06-11 290
72bad997287693 Colin Xu 2018-06-11 291 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
a5a8ef937cfa79 Colin Xu 2020-11-09 292 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
a5a8ef937cfa79 Colin Xu 2020-11-09 293 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
a5a8ef937cfa79 Colin Xu 2020-11-09 294 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 295 PHY_POWER_GOOD;
a5a8ef937cfa79 Colin Xu 2020-11-09 296 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 297 BIT(30);
a5a8ef937cfa79 Colin Xu 2020-11-09 298 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 299 BXT_PHY_LANE_ENABLED;
a5a8ef937cfa79 Colin Xu 2020-11-09 300 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 301 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
a5a8ef937cfa79 Colin Xu 2020-11-09 302 BXT_PHY_LANE_POWERDOWN_ACK);
a5a8ef937cfa79 Colin Xu 2020-11-09 303 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 304 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
a5a8ef937cfa79 Colin Xu 2020-11-09 305 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
a5a8ef937cfa79 Colin Xu 2020-11-09 306 PORT_PLL_ENABLE);
a5a8ef937cfa79 Colin Xu 2020-11-09 307 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 308 DDI_BUF_CTL_ENABLE;
a5a8ef937cfa79 Colin Xu 2020-11-09 309 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 310 ~DDI_BUF_IS_IDLE;
a5a8ef937cfa79 Colin Xu 2020-11-09 311 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 312 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
a5a8ef937cfa79 Colin Xu 2020-11-09 313 (PORT_B << TRANS_DDI_PORT_SHIFT) |
a5a8ef937cfa79 Colin Xu 2020-11-09 314 TRANS_DDI_FUNC_ENABLE);
4ceb06e7c336f4 Colin Xu 2020-12-01 315 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
4ceb06e7c336f4 Colin Xu 2020-12-01 316 PORTB_HOTPLUG_ENABLE;
72bad997287693 Colin Xu 2018-06-11 317 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
e5abaab30eca51 Ville Syrjälä 2020-10-28 318 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
72bad997287693 Colin Xu 2018-06-11 319 }
72bad997287693 Colin Xu 2018-06-11 320
72bad997287693 Colin Xu 2018-06-11 321 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
a5a8ef937cfa79 Colin Xu 2020-11-09 322 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
a5a8ef937cfa79 Colin Xu 2020-11-09 323 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
a5a8ef937cfa79 Colin Xu 2020-11-09 324 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 325 PHY_POWER_GOOD;
a5a8ef937cfa79 Colin Xu 2020-11-09 326 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 327 BIT(30);
a5a8ef937cfa79 Colin Xu 2020-11-09 328 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 329 BXT_PHY_LANE_ENABLED;
a5a8ef937cfa79 Colin Xu 2020-11-09 330 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 331 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
a5a8ef937cfa79 Colin Xu 2020-11-09 332 BXT_PHY_LANE_POWERDOWN_ACK);
a5a8ef937cfa79 Colin Xu 2020-11-09 333 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 334 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
a5a8ef937cfa79 Colin Xu 2020-11-09 335 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
a5a8ef937cfa79 Colin Xu 2020-11-09 336 PORT_PLL_ENABLE);
a5a8ef937cfa79 Colin Xu 2020-11-09 337 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 338 DDI_BUF_CTL_ENABLE;
a5a8ef937cfa79 Colin Xu 2020-11-09 339 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=
a5a8ef937cfa79 Colin Xu 2020-11-09 340 ~DDI_BUF_IS_IDLE;
a5a8ef937cfa79 Colin Xu 2020-11-09 341 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
a5a8ef937cfa79 Colin Xu 2020-11-09 342 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
a5a8ef937cfa79 Colin Xu 2020-11-09 343 (PORT_B << TRANS_DDI_PORT_SHIFT) |
a5a8ef937cfa79 Colin Xu 2020-11-09 344 TRANS_DDI_FUNC_ENABLE);
4ceb06e7c336f4 Colin Xu 2020-12-01 345 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
4ceb06e7c336f4 Colin Xu 2020-12-01 346 PORTC_HOTPLUG_ENABLE;
72bad997287693 Colin Xu 2018-06-11 347 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
e5abaab30eca51 Ville Syrjälä 2020-10-28 348 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
72bad997287693 Colin Xu 2018-06-11 349 }
72bad997287693 Colin Xu 2018-06-11 350
72bad997287693 Colin Xu 2018-06-11 351 return;
72bad997287693 Colin Xu 2018-06-11 352 }
72bad997287693 Colin Xu 2018-06-11 353
90551a1296d4db Zhenyu Wang 2017-12-19 354 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
04d348ae3f0aea Zhi Wang 2016-04-25 355 SDE_PORTC_HOTPLUG_CPT |
04d348ae3f0aea Zhi Wang 2016-04-25 356 SDE_PORTD_HOTPLUG_CPT);
04d348ae3f0aea Zhi Wang 2016-04-25 357
5f4ae2704d59ee Chris Wilson 2020-06-02 358 if (IS_SKYLAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson 2020-06-02 359 IS_KABYLAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson 2020-06-02 360 IS_COFFEELAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson 2020-06-02 361 IS_COMETLAKE(dev_priv)) {
90551a1296d4db Zhenyu Wang 2017-12-19 362 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
04d348ae3f0aea Zhi Wang 2016-04-25 363 SDE_PORTE_HOTPLUG_SPT);
90551a1296d4db Zhenyu Wang 2017-12-19 364 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
88a16b64c3f48d Weinan Li 2017-03-17 365 SKL_FUSE_DOWNLOAD_STATUS |
b2891eb2531e5e Imre Deak 2017-07-11 366 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
b2891eb2531e5e Imre Deak 2017-07-11 367 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
b2891eb2531e5e Imre Deak 2017-07-11 368 SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
f965b68188ab59 Colin Xu 2020-05-08 369 /*
f965b68188ab59 Colin Xu 2020-05-08 370 * Only 1 PIPE enabled in current vGPU display and PIPE_A is
f965b68188ab59 Colin Xu 2020-05-08 371 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
f965b68188ab59 Colin Xu 2020-05-08 372 * TRANSCODER_A can be enabled. PORT_x depends on the input of
f965b68188ab59 Colin Xu 2020-05-08 373 * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x
f965b68188ab59 Colin Xu 2020-05-08 374 * so we fixed to DPLL0 here.
f965b68188ab59 Colin Xu 2020-05-08 375 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode
f965b68188ab59 Colin Xu 2020-05-08 376 */
f965b68188ab59 Colin Xu 2020-05-08 377 vgpu_vreg_t(vgpu, DPLL_CTRL1) =
f965b68188ab59 Colin Xu 2020-05-08 378 DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0);
f965b68188ab59 Colin Xu 2020-05-08 379 vgpu_vreg_t(vgpu, DPLL_CTRL1) |=
f965b68188ab59 Colin Xu 2020-05-08 380 DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0);
f965b68188ab59 Colin Xu 2020-05-08 381 vgpu_vreg_t(vgpu, LCPLL1_CTL) =
f965b68188ab59 Colin Xu 2020-05-08 382 LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK;
f965b68188ab59 Colin Xu 2020-05-08 383 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);
f965b68188ab59 Colin Xu 2020-05-08 384 /*
f965b68188ab59 Colin Xu 2020-05-08 385 * Golden M/N are calculated based on:
f965b68188ab59 Colin Xu 2020-05-08 386 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
f965b68188ab59 Colin Xu 2020-05-08 387 * DP link clk 1620 MHz and non-constant_n.
f965b68188ab59 Colin Xu 2020-05-08 388 * TODO: calculate DP link symbol clk and stream clk m/n.
f965b68188ab59 Colin Xu 2020-05-08 389 */
f965b68188ab59 Colin Xu 2020-05-08 390 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
f965b68188ab59 Colin Xu 2020-05-08 391 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
f965b68188ab59 Colin Xu 2020-05-08 392 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
f965b68188ab59 Colin Xu 2020-05-08 393 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
f965b68188ab59 Colin Xu 2020-05-08 394 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
88a16b64c3f48d Weinan Li 2017-03-17 395 }
04d348ae3f0aea Zhi Wang 2016-04-25 396
858b0f571d3091 Bing Niu 2017-02-28 397 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
f965b68188ab59 Colin Xu 2020-05-08 398 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
f965b68188ab59 Colin Xu 2020-05-08 399 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B);
f965b68188ab59 Colin Xu 2020-05-08 400 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu 2020-05-08 401 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B);
f965b68188ab59 Colin Xu 2020-05-08 402 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu 2020-05-08 403 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B);
90551a1296d4db Zhenyu Wang 2017-12-19 404 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
90551a1296d4db Zhenyu Wang 2017-12-19 405 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
efa69d734adbf8 Pei Zhang 2017-04-07 406 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
efa69d734adbf8 Pei Zhang 2017-04-07 407 TRANS_DDI_PORT_MASK);
90551a1296d4db Zhenyu Wang 2017-12-19 408 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
75db1a5b2aea2a Tina Zhang 2020-03-17 409 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
efa69d734adbf8 Pei Zhang 2017-04-07 410 (PORT_B << TRANS_DDI_PORT_SHIFT) |
efa69d734adbf8 Pei Zhang 2017-04-07 411 TRANS_DDI_FUNC_ENABLE);
295a0d0b55269f Xiong Zhang 2017-06-20 412 if (IS_BROADWELL(dev_priv)) {
90551a1296d4db Zhenyu Wang 2017-12-19 413 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
295a0d0b55269f Xiong Zhang 2017-06-20 414 ~PORT_CLK_SEL_MASK;
90551a1296d4db Zhenyu Wang 2017-12-19 415 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
295a0d0b55269f Xiong Zhang 2017-06-20 416 PORT_CLK_SEL_LCPLL_810;
295a0d0b55269f Xiong Zhang 2017-06-20 417 }
90551a1296d4db Zhenyu Wang 2017-12-19 418 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
90551a1296d4db Zhenyu Wang 2017-12-19 419 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
90551a1296d4db Zhenyu Wang 2017-12-19 420 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
858b0f571d3091 Bing Niu 2017-02-28 421 }
04d348ae3f0aea Zhi Wang 2016-04-25 422
858b0f571d3091 Bing Niu 2017-02-28 423 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
f965b68188ab59 Colin Xu 2020-05-08 424 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
f965b68188ab59 Colin Xu 2020-05-08 425 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C);
f965b68188ab59 Colin Xu 2020-05-08 426 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu 2020-05-08 427 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C);
f965b68188ab59 Colin Xu 2020-05-08 428 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu 2020-05-08 429 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C);
90551a1296d4db Zhenyu Wang 2017-12-19 430 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
90551a1296d4db Zhenyu Wang 2017-12-19 431 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
efa69d734adbf8 Pei Zhang 2017-04-07 432 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
efa69d734adbf8 Pei Zhang 2017-04-07 433 TRANS_DDI_PORT_MASK);
90551a1296d4db Zhenyu Wang 2017-12-19 434 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
75db1a5b2aea2a Tina Zhang 2020-03-17 435 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
efa69d734adbf8 Pei Zhang 2017-04-07 436 (PORT_C << TRANS_DDI_PORT_SHIFT) |
efa69d734adbf8 Pei Zhang 2017-04-07 437 TRANS_DDI_FUNC_ENABLE);
295a0d0b55269f Xiong Zhang 2017-06-20 438 if (IS_BROADWELL(dev_priv)) {
90551a1296d4db Zhenyu Wang 2017-12-19 439 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
295a0d0b55269f Xiong Zhang 2017-06-20 440 ~PORT_CLK_SEL_MASK;
90551a1296d4db Zhenyu Wang 2017-12-19 441 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
295a0d0b55269f Xiong Zhang 2017-06-20 442 PORT_CLK_SEL_LCPLL_810;
295a0d0b55269f Xiong Zhang 2017-06-20 443 }
90551a1296d4db Zhenyu Wang 2017-12-19 444 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
90551a1296d4db Zhenyu Wang 2017-12-19 445 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
90551a1296d4db Zhenyu Wang 2017-12-19 446 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
858b0f571d3091 Bing Niu 2017-02-28 447 }
04d348ae3f0aea Zhi Wang 2016-04-25 448
858b0f571d3091 Bing Niu 2017-02-28 449 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
f965b68188ab59 Colin Xu 2020-05-08 450 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
f965b68188ab59 Colin Xu 2020-05-08 451 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D);
f965b68188ab59 Colin Xu 2020-05-08 452 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu 2020-05-08 453 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D);
f965b68188ab59 Colin Xu 2020-05-08 454 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu 2020-05-08 455 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D);
90551a1296d4db Zhenyu Wang 2017-12-19 456 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
90551a1296d4db Zhenyu Wang 2017-12-19 457 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
efa69d734adbf8 Pei Zhang 2017-04-07 458 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
efa69d734adbf8 Pei Zhang 2017-04-07 459 TRANS_DDI_PORT_MASK);
90551a1296d4db Zhenyu Wang 2017-12-19 460 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
75db1a5b2aea2a Tina Zhang 2020-03-17 461 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
efa69d734adbf8 Pei Zhang 2017-04-07 462 (PORT_D << TRANS_DDI_PORT_SHIFT) |
efa69d734adbf8 Pei Zhang 2017-04-07 463 TRANS_DDI_FUNC_ENABLE);
295a0d0b55269f Xiong Zhang 2017-06-20 464 if (IS_BROADWELL(dev_priv)) {
90551a1296d4db Zhenyu Wang 2017-12-19 465 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
295a0d0b55269f Xiong Zhang 2017-06-20 466 ~PORT_CLK_SEL_MASK;
90551a1296d4db Zhenyu Wang 2017-12-19 467 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
295a0d0b55269f Xiong Zhang 2017-06-20 468 PORT_CLK_SEL_LCPLL_810;
295a0d0b55269f Xiong Zhang 2017-06-20 469 }
90551a1296d4db Zhenyu Wang 2017-12-19 470 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
90551a1296d4db Zhenyu Wang 2017-12-19 471 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
90551a1296d4db Zhenyu Wang 2017-12-19 472 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
858b0f571d3091 Bing Niu 2017-02-28 473 }
04d348ae3f0aea Zhi Wang 2016-04-25 474
5f4ae2704d59ee Chris Wilson 2020-06-02 475 if ((IS_SKYLAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson 2020-06-02 476 IS_KABYLAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson 2020-06-02 477 IS_COFFEELAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson 2020-06-02 478 IS_COMETLAKE(dev_priv)) &&
04d348ae3f0aea Zhi Wang 2016-04-25 479 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
90551a1296d4db Zhenyu Wang 2017-12-19 480 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
04d348ae3f0aea Zhi Wang 2016-04-25 481 }
04d348ae3f0aea Zhi Wang 2016-04-25 482
04d348ae3f0aea Zhi Wang 2016-04-25 483 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
04d348ae3f0aea Zhi Wang 2016-04-25 484 if (IS_BROADWELL(dev_priv))
90551a1296d4db Zhenyu Wang 2017-12-19 485 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
e5abaab30eca51 Ville Syrjälä 2020-10-28 486 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
04d348ae3f0aea Zhi Wang 2016-04-25 487 else
90551a1296d4db Zhenyu Wang 2017-12-19 488 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
858b0f571d3091 Bing Niu 2017-02-28 489
90551a1296d4db Zhenyu Wang 2017-12-19 490 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
04d348ae3f0aea Zhi Wang 2016-04-25 491 }
75e64ff2c2f5ce Xiong Zhang 2017-06-28 492
75e64ff2c2f5ce Xiong Zhang 2017-06-28 493 /* Clear host CRT status, so guest couldn't detect this host CRT. */
75e64ff2c2f5ce Xiong Zhang 2017-06-28 494 if (IS_BROADWELL(dev_priv))
90551a1296d4db Zhenyu Wang 2017-12-19 495 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
4e889d62b89d00 Xiaolin Zhang 2017-12-05 496
65eff272330c72 Xiong Zhang 2018-03-28 497 /* Disable Primary/Sprite/Cursor plane */
65eff272330c72 Xiong Zhang 2018-03-28 498 for_each_pipe(dev_priv, pipe) {
65eff272330c72 Xiong Zhang 2018-03-28 499 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
65eff272330c72 Xiong Zhang 2018-03-28 500 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
b99b9ec1d374fd Ville Syrjälä 2018-01-31 501 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
b99b9ec1d374fd Ville Syrjälä 2018-01-31 502 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
65eff272330c72 Xiong Zhang 2018-03-28 503 }
65eff272330c72 Xiong Zhang 2018-03-28 504
90551a1296d4db Zhenyu Wang 2017-12-19 505 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
04d348ae3f0aea Zhi Wang 2016-04-25 506 }
04d348ae3f0aea Zhi Wang 2016-04-25 507
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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* Re: [Intel-gfx] [PATCH 04/14] drm/i915: Sipmplify PLANE_STRIDE masking
2021-12-01 15:25 ` [Intel-gfx] [PATCH 04/14] drm/i915: Sipmplify PLANE_STRIDE masking Ville Syrjala
@ 2022-01-12 19:50 ` Souza, Jose
0 siblings, 0 replies; 48+ messages in thread
From: Souza, Jose @ 2022-01-12 19:50 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> There's no need to have separate masks for the stride bitfield
> in PLANE_STRIDE for different platforms. All the extra bits
> are hardcoded to zero anyway.
>
> Also the masks we're using now don't even match the actual hardware
> since the bitfield was only 10 bits on skl/derivatives, only getting
> bumped to 11 bits on glk.
>
> So let's just use a 12 bit mask for everything.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 +----
> drivers/gpu/drm/i915/i915_reg.h | 3 +--
> 2 files changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 09948922016b..984bb35ecf06 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2347,10 +2347,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
> stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
>
> - if (DISPLAY_VER(dev_priv) >= 13)
> - fb->pitches[0] = (val & PLANE_STRIDE_MASK_XELPD) * stride_mult;
> - else
> - fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
> + fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
>
> aligned_height = intel_fb_align_height(fb, 0, fb->height);
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 02d8db03c0bf..6066b1e2763c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7440,8 +7440,7 @@ enum {
> _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
> #define PLANE_STRIDE(pipe, plane) \
> _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
> -#define PLANE_STRIDE_MASK REG_GENMASK(10, 0)
> -#define PLANE_STRIDE_MASK_XELPD REG_GENMASK(11, 0)
> +#define PLANE_STRIDE_MASK REG_GENMASK(11, 0)
>
> #define _PLANE_POS_1_B 0x7118c
> #define _PLANE_POS_2_B 0x7128c
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 06/14] drm/i915: Use REG_BIT() & co. for universal plane bits
2021-12-02 11:57 ` Ville Syrjälä
@ 2022-01-12 19:52 ` Souza, Jose
0 siblings, 0 replies; 48+ messages in thread
From: Souza, Jose @ 2022-01-12 19:52 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Thu, 2021-12-02 at 13:57 +0200, Ville Syrjälä wrote:
> On Wed, Dec 01, 2021 at 05:26:50PM +0000, Souza, Jose wrote:
> > On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Polish the skl+ universal plane register defines by
> > > using REG_BIT() & co.
> > >
> > > The defines are also currently spread around in some
> > > semi-random fashion. Collect them up into one place.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > .../drm/i915/display/skl_universal_plane.c | 36 ++--
> > > drivers/gpu/drm/i915/gvt/reg.h | 1 -
> > > drivers/gpu/drm/i915/i915_reg.h | 197 ++++++++++--------
> > > drivers/gpu/drm/i915/intel_pm.c | 12 +-
> > > 4 files changed, 135 insertions(+), 111 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > index 984bb35ecf06..79998eb67280 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > @@ -1037,11 +1037,12 @@ skl_program_plane_noarm(struct intel_plane *plane,
> > > if (plane_state->force_black)
> > > icl_plane_csc_load_black(plane);
> > >
> > > - intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), stride);
> > > + intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
> > > + PLANE_STRIDE_(stride));
> > > intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
> > > - (crtc_y << 16) | crtc_x);
> > > + PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
> > > intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
> > > - ((src_h - 1) << 16) | (src_w - 1));
> > > + PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
> > >
> > > if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
> > > intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
> > > @@ -1100,7 +1101,7 @@ skl_program_plane_arm(struct intel_plane *plane,
> > > skl_surf_address(plane_state, color_plane);
> > >
> > > if (DISPLAY_VER(dev_priv) < 12)
> > > - aux_dist |= skl_plane_stride(plane_state, aux_plane);
> > > + aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));
> > > }
> > >
> > > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> > > @@ -1111,14 +1112,14 @@ skl_program_plane_arm(struct intel_plane *plane,
> > > intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), keymax);
> > >
> > > intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
> > > - (y << 16) | x);
> > > + PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
> > >
> > > intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
> > >
> > > if (DISPLAY_VER(dev_priv) < 11)
> > > intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
> > > - (plane_state->view.color_plane[1].y << 16) |
> > > - plane_state->view.color_plane[1].x);
> > > + PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) |
> > > + PLANE_OFFSET_X(plane_state->view.color_plane[1].x));
> > >
> > > if (DISPLAY_VER(dev_priv) >= 10)
> > > intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
> > > @@ -2262,16 +2263,17 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > > val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
> > >
> > > if (DISPLAY_VER(dev_priv) >= 11)
> > > - pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
> > > + pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL;
> >
> > Most of our platform bits definition follows <platform or display ver>_<register name>.
>
> s/most/some/
>
> I want it exactly the other way around so that the namespace for
> each register is consistent.
>
> >
> > Other than that the idea looks good to me.
> >
> > > else
> > > - pixel_format = val & PLANE_CTL_FORMAT_MASK;
> > > + pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL;
> > >
> > > if (DISPLAY_VER(dev_priv) >= 10) {
> > > - alpha = intel_de_read(dev_priv,
> > > - PLANE_COLOR_CTL(pipe, plane_id));
> > > - alpha &= PLANE_COLOR_ALPHA_MASK;
> > > + u32 color_ctl;
> > > +
> > > + color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe, plane_id));
> > > + alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl);
> > > } else {
> > > - alpha = val & PLANE_CTL_ALPHA_MASK;
> > > + alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val);
> > > }
> > >
> > > fourcc = skl_format_to_fourcc(pixel_format,
> > > @@ -2335,19 +2337,19 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > > if (drm_rotation_90_or_270(plane_config->rotation))
> > > goto error;
> > >
> > > - base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
> > > + base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK;
> > > plane_config->base = base;
> > >
> > > offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
> > >
> > > val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
> > > - fb->height = ((val >> 16) & 0xffff) + 1;
> > > - fb->width = ((val >> 0) & 0xffff) + 1;
> > > + fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1;
> > > + fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1;
> > >
> > > val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
> > > stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
> > >
> > > - fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
> > > + fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult;
> > >
> > > aligned_height = intel_fb_align_height(fb, 0, fb->height);
> > >
> > > diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
> > > index 244cc7320b54..7d666d34f9ff 100644
> > > --- a/drivers/gpu/drm/i915/gvt/reg.h
> > > +++ b/drivers/gpu/drm/i915/gvt/reg.h
> > > @@ -62,7 +62,6 @@
> > >
> > > #define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe))
> > >
> > > -#define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > > #define REG50080_FLIP_TYPE_MASK 0x3
> > > #define REG50080_FLIP_TYPE_ASYNC 0x1
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 4b2bc17d0235..9fffa2392bbf 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7233,84 +7233,99 @@ enum {
> > > #define _PLANE_CTL_1_A 0x70180
> > > #define _PLANE_CTL_2_A 0x70280
> > > #define _PLANE_CTL_3_A 0x70380
> > > -#define PLANE_CTL_ENABLE (1 << 31)
> > > +#define PLANE_CTL_ENABLE REG_BIT(31)
> > > #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
> > > #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
> > > -#define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
> > > -#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
> > > +#define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
> > > +#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
> > > /*
> > > * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
> > > * expanded to include bit 23 as well. However, the shift-24 based values
> > > * correctly map to the same formats in ICL, as long as bit 23 is set to 0
> > > */
> > > -#define PLANE_CTL_FORMAT_MASK (0xf << 24)
> > > -#define PLANE_CTL_FORMAT_YUV422 (0 << 24)
> > > -#define PLANE_CTL_FORMAT_NV12 (1 << 24)
> > > -#define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
> > > -#define PLANE_CTL_FORMAT_P010 (3 << 24)
> > > -#define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24)
> > > -#define PLANE_CTL_FORMAT_P012 (5 << 24)
> > > -#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
> > > -#define PLANE_CTL_FORMAT_P016 (7 << 24)
> > > -#define PLANE_CTL_FORMAT_XYUV (8 << 24)
> > > -#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
> > > -#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
> > > -#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
> > > -#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
> > > -#define PLANE_CTL_FORMAT_Y210 (1 << 23)
> > > -#define PLANE_CTL_FORMAT_Y212 (3 << 23)
> > > -#define PLANE_CTL_FORMAT_Y216 (5 << 23)
> > > -#define PLANE_CTL_FORMAT_Y410 (7 << 23)
> > > -#define PLANE_CTL_FORMAT_Y412 (9 << 23)
> > > -#define PLANE_CTL_FORMAT_Y416 (0xb << 23)
> > > -#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
> > > -#define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
> > > -#define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
> > > -#define PLANE_CTL_ORDER_BGRX (0 << 20)
> > > -#define PLANE_CTL_ORDER_RGBX (1 << 20)
> > > -#define PLANE_CTL_YUV420_Y_PLANE (1 << 19)
> > > -#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
> > > -#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
> > > -#define PLANE_CTL_YUV422_ORDER_YUYV (0 << 16)
> > > -#define PLANE_CTL_YUV422_ORDER_UYVY (1 << 16)
> > > -#define PLANE_CTL_YUV422_ORDER_YVYU (2 << 16)
> > > -#define PLANE_CTL_YUV422_ORDER_VYUY (3 << 16)
> > > -#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
> > > -#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
> > > -#define PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13) /* TGL+ */
> > > -#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
> > > -#define PLANE_CTL_TILED_MASK (0x7 << 10)
> > > -#define PLANE_CTL_TILED_LINEAR (0 << 10)
> > > -#define PLANE_CTL_TILED_X (1 << 10)
> > > -#define PLANE_CTL_TILED_Y (4 << 10)
> > > -#define PLANE_CTL_TILED_YF (5 << 10)
> > > -#define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > > -#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > > -#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> > > -#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
> > > -#define PLANE_CTL_ALPHA_DISABLE (0 << 4)
> > > -#define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
> > > -#define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4)
> > > -#define PLANE_CTL_ROTATE_MASK 0x3
> > > -#define PLANE_CTL_ROTATE_0 0x0
> > > -#define PLANE_CTL_ROTATE_90 0x1
> > > -#define PLANE_CTL_ROTATE_180 0x2
> > > -#define PLANE_CTL_ROTATE_270 0x3
> > > +#define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */
> > > +#define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */
> > > +#define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
> > > +#define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1)
> > > +#define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2)
> > > +#define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3)
> > > +#define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4)
> > > +#define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5)
> > > +#define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6)
> > > +#define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7)
> > > +#define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8)
> > > +#define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12)
> > > +#define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14)
> > > +#define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1)
> > > +#define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3)
> > > +#define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5)
> > > +#define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7)
> > > +#define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9)
> > > +#define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11)
> > > +#define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
> > > +#define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21)
> > > +#define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1)
> > > +#define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2)
> > > +#define PLANE_CTL_ORDER_RGBX REG_BIT(20)
> > > +#define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19)
> > > +#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18)
> > > +#define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16)
> > > +#define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)
> > > +#define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1)
> > > +#define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2)
> > > +#define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3)
> > > +#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15)
> > > +#define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14)
> > > +#define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
> > > +#define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
> > > +#define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10)
> > > +#define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0)
> > > +#define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1)
> > > +#define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4)
> > > +#define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
> > > +#define PLANE_CTL_ASYNC_FLIP REG_BIT(9)
> > > +#define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8)
> > > +#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
> > > +#define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
> > > +#define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0)
> > > +#define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2)
> > > +#define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3)
> > > +#define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0)
> > > +#define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0)
> > > +#define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
> > > +#define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
> > > +#define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
> > > #define _PLANE_STRIDE_1_A 0x70188
> > > #define _PLANE_STRIDE_2_A 0x70288
> > > #define _PLANE_STRIDE_3_A 0x70388
> > > +#define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
> > > +#define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
> > > #define _PLANE_POS_1_A 0x7018c
> > > #define _PLANE_POS_2_A 0x7028c
> > > #define _PLANE_POS_3_A 0x7038c
> > > +#define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
> > > +#define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
> > > +#define PLANE_POS_X_MASK REG_GENMASK(15, 0)
> > > +#define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
> > > #define _PLANE_SIZE_1_A 0x70190
> > > #define _PLANE_SIZE_2_A 0x70290
> > > #define _PLANE_SIZE_3_A 0x70390
> > > +#define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
> > > +#define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
> > > +#define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
> > > +#define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
> > > #define _PLANE_SURF_1_A 0x7019c
> > > #define _PLANE_SURF_2_A 0x7029c
> > > #define _PLANE_SURF_3_A 0x7039c
> > > +#define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
> > > +#define PLANE_SURF_DECRYPT REG_BIT(2)
> > > #define _PLANE_OFFSET_1_A 0x701a4
> > > #define _PLANE_OFFSET_2_A 0x702a4
> > > #define _PLANE_OFFSET_3_A 0x703a4
> > > +#define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
> > > +#define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
> > > +#define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
> > > +#define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))
> > > #define _PLANE_KEYVAL_1_A 0x70194
> > > #define _PLANE_KEYVAL_2_A 0x70294
> > > #define _PLANE_KEYMSK_1_A 0x70198
> > > @@ -7322,42 +7337,49 @@ enum {
> > > #define _PLANE_CC_VAL_1_A 0x701b4
> > > #define _PLANE_CC_VAL_2_A 0x702b4
> > > #define _PLANE_AUX_DIST_1_A 0x701c0
> > > +#define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
> > > +#define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
> > > +#define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
> > > #define _PLANE_AUX_DIST_2_A 0x702c0
> > > #define _PLANE_AUX_OFFSET_1_A 0x701c4
> > > #define _PLANE_AUX_OFFSET_2_A 0x702c4
> > > #define _PLANE_CUS_CTL_1_A 0x701c8
> > > #define _PLANE_CUS_CTL_2_A 0x702c8
> > > -#define PLANE_CUS_ENABLE (1 << 31)
> > > -#define PLANE_CUS_Y_PLANE_4_RKL (0 << 30)
> > > -#define PLANE_CUS_Y_PLANE_5_RKL (1 << 30)
> > > -#define PLANE_CUS_Y_PLANE_6_ICL (0 << 30)
> > > -#define PLANE_CUS_Y_PLANE_7_ICL (1 << 30)
> > > -#define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19)
> > > -#define PLANE_CUS_HPHASE_0 (0 << 16)
> > > -#define PLANE_CUS_HPHASE_0_25 (1 << 16)
> > > -#define PLANE_CUS_HPHASE_0_5 (2 << 16)
> > > -#define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15)
> > > -#define PLANE_CUS_VPHASE_0 (0 << 12)
> > > -#define PLANE_CUS_VPHASE_0_25 (1 << 12)
> > > -#define PLANE_CUS_VPHASE_0_5 (2 << 12)
> > > +#define PLANE_CUS_ENABLE REG_BIT(31)
> > > +#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
> > > +#define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
> > > +#define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
> > > +#define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
> > > +#define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
> > > +#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
> > > +#define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16)
> > > +#define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
> > > +#define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
> > > +#define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
> > > +#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
> > > +#define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12)
> > > +#define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
> > > +#define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
> > > +#define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
> > > #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
> > > #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
> > > #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
> > > -#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
> > > -#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
> > > +#define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
> > > +#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
> > > +#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
> > > #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
> > > -#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
> > > -#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
> > > -#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
> > > -#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 (1 << 17)
> > > -#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
> > > -#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
> > > -#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
> > > -#define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
> > > -#define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
> > > -#define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
> > > -#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
> > > -#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
> > > +#define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
> > > +#define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17)
> > > +#define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
> > > +#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)
> > > +#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2)
> > > +#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3)
> > > +#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4)
> > > +#define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13)
> > > +#define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4)
> > > +#define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
> > > +#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
> > > +#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
> > > #define _PLANE_BUF_CFG_1_A 0x7027c
> > > #define _PLANE_BUF_CFG_2_A 0x7037c
> > > #define _PLANE_NV12_BUF_CFG_1_A 0x70278
> > > @@ -7440,7 +7462,6 @@ enum {
> > > _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
> > > #define PLANE_STRIDE(pipe, plane) \
> > > _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
> > > -#define PLANE_STRIDE_MASK REG_GENMASK(11, 0)
> > >
> > > #define _PLANE_POS_1_B 0x7118c
> > > #define _PLANE_POS_2_B 0x7128c
> > > @@ -7468,7 +7489,6 @@ enum {
> > > #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
> > > #define PLANE_SURF(pipe, plane) \
> > > _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
> > > -#define PLANE_SURF_DECRYPT REG_BIT(2)
> > >
> > > #define _PLANE_OFFSET_1_B 0x711a4
> > > #define _PLANE_OFFSET_2_B 0x712a4
> > > @@ -7500,8 +7520,11 @@ enum {
> > >
> > > #define _PLANE_BUF_CFG_1_B 0x7127c
> > > #define _PLANE_BUF_CFG_2_B 0x7137c
> > > -#define DDB_ENTRY_MASK 0xFFF /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
> > > -#define DDB_ENTRY_END_SHIFT 16
> > > +/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
> > > +#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
> > > +#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
> > > +#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
> > > +#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
> > > #define _PLANE_BUF_CFG_1(pipe) \
> > > _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
> > > #define _PLANE_BUF_CFG_2(pipe) \
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index cff0f32bedc9..7f00fd2f62a0 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -4283,11 +4283,10 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
> > > static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
> > > struct skl_ddb_entry *entry, u32 reg)
> > > {
> > > - entry->start = reg & DDB_ENTRY_MASK;
> > > - entry->end = (reg >> DDB_ENTRY_END_SHIFT) & DDB_ENTRY_MASK;
> > > -
> > > + entry->start = REG_FIELD_GET(PLANE_BUF_START_MASK, reg);
> > > + entry->end = REG_FIELD_GET(PLANE_BUF_END_MASK, reg);
> > > if (entry->end)
> > > - entry->end += 1;
> > > + entry->end++;
> > > }
> > >
> > > static void
> > > @@ -4311,7 +4310,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
> > >
> > > /* No DDB allocated for disabled planes */
> > > if (val & PLANE_CTL_ENABLE)
> > > - fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK,
> > > + fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK_SKL,
> > > val & PLANE_CTL_ORDER_RGBX,
> > > val & PLANE_CTL_ALPHA_MASK);
> > >
> > > @@ -5882,7 +5881,8 @@ static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
> > > {
> > > if (entry->end)
> > > intel_de_write_fw(dev_priv, reg,
> > > - (entry->end - 1) << 16 | entry->start);
> > > + PLANE_BUF_END(entry->end - 1) |
> > > + PLANE_BUF_START(entry->start));
> > > else
> > > intel_de_write_fw(dev_priv, reg, 0);
> > > }
> >
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 07/14] drm/i915: Clean up pre-skl primary plane registers
2021-12-01 15:25 ` [Intel-gfx] [PATCH 07/14] drm/i915: Clean up pre-skl primary plane registers Ville Syrjala
2021-12-06 19:22 ` kernel test robot
@ 2022-01-12 20:12 ` Souza, Jose
2022-01-18 0:55 ` Ville Syrjälä
1 sibling, 1 reply; 48+ messages in thread
From: Souza, Jose @ 2022-01-12 20:12 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use REG_BIT() & co. for the pre-skl primary plane registers.
> Also give everything a consistent namespace.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 99 +++++++++--------
> drivers/gpu/drm/i915/display/intel_display.c | 13 +--
> drivers/gpu/drm/i915/i915_reg.h | 108 +++++++++++--------
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 4 files changed, 117 insertions(+), 105 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 2194f74101ae..00cc8b4bd6bc 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -145,51 +145,51 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
> unsigned int rotation = plane_state->hw.rotation;
> u32 dspcntr;
>
> - dspcntr = DISPLAY_PLANE_ENABLE;
> + dspcntr = DSP_ENABLE;
>
> if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) ||
> IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
> - dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
> + dspcntr |= DSP_TRICKLE_FEED_DISABLE;
>
> switch (fb->format->format) {
> case DRM_FORMAT_C8:
> - dspcntr |= DISPPLANE_8BPP;
> + dspcntr |= DSP_FORMAT_8BPP;
> break;
> case DRM_FORMAT_XRGB1555:
> - dspcntr |= DISPPLANE_BGRX555;
> + dspcntr |= DSP_FORMAT_BGRX555;
> break;
> case DRM_FORMAT_ARGB1555:
> - dspcntr |= DISPPLANE_BGRA555;
> + dspcntr |= DSP_FORMAT_BGRA555;
> break;
> case DRM_FORMAT_RGB565:
> - dspcntr |= DISPPLANE_BGRX565;
> + dspcntr |= DSP_FORMAT_BGRX565;
> break;
> case DRM_FORMAT_XRGB8888:
> - dspcntr |= DISPPLANE_BGRX888;
> + dspcntr |= DSP_FORMAT_BGRX888;
> break;
> case DRM_FORMAT_XBGR8888:
> - dspcntr |= DISPPLANE_RGBX888;
> + dspcntr |= DSP_FORMAT_RGBX888;
> break;
> case DRM_FORMAT_ARGB8888:
> - dspcntr |= DISPPLANE_BGRA888;
> + dspcntr |= DSP_FORMAT_BGRA888;
> break;
> case DRM_FORMAT_ABGR8888:
> - dspcntr |= DISPPLANE_RGBA888;
> + dspcntr |= DSP_FORMAT_RGBA888;
> break;
> case DRM_FORMAT_XRGB2101010:
> - dspcntr |= DISPPLANE_BGRX101010;
> + dspcntr |= DSP_FORMAT_BGRX101010;
> break;
> case DRM_FORMAT_XBGR2101010:
> - dspcntr |= DISPPLANE_RGBX101010;
> + dspcntr |= DSP_FORMAT_RGBX101010;
> break;
> case DRM_FORMAT_ARGB2101010:
> - dspcntr |= DISPPLANE_BGRA101010;
> + dspcntr |= DSP_FORMAT_BGRA101010;
> break;
> case DRM_FORMAT_ABGR2101010:
> - dspcntr |= DISPPLANE_RGBA101010;
> + dspcntr |= DSP_FORMAT_RGBA101010;
> break;
> case DRM_FORMAT_XBGR16161616F:
> - dspcntr |= DISPPLANE_RGBX161616;
> + dspcntr |= DSP_FORMAT_RGBX161616;
> break;
> default:
> MISSING_CASE(fb->format->format);
> @@ -198,13 +198,13 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
>
> if (DISPLAY_VER(dev_priv) >= 4 &&
> fb->modifier == I915_FORMAT_MOD_X_TILED)
> - dspcntr |= DISPPLANE_TILED;
> + dspcntr |= DSP_TILED;
>
> if (rotation & DRM_MODE_ROTATE_180)
> - dspcntr |= DISPPLANE_ROTATE_180;
> + dspcntr |= DSP_ROTATE_180;
>
> if (rotation & DRM_MODE_REFLECT_X)
> - dspcntr |= DISPPLANE_MIRROR;
> + dspcntr |= DSP_MIRROR;
>
> return dspcntr;
> }
> @@ -344,13 +344,13 @@ static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
> u32 dspcntr = 0;
>
> if (crtc_state->gamma_enable)
> - dspcntr |= DISPPLANE_GAMMA_ENABLE;
> + dspcntr |= DSP_PIPE_GAMMA_ENABLE;
>
> if (crtc_state->csc_enable)
> - dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> + dspcntr |= DSP_PIPE_CSC_ENABLE;
>
> if (DISPLAY_VER(dev_priv) < 5)
> - dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
> + dspcntr |= DSP_PIPE_SEL(crtc->pipe);
>
> return dspcntr;
> }
> @@ -427,9 +427,9 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane,
> * program whatever is there.
> */
> intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
> - (crtc_y << 16) | crtc_x);
> + DSP_POS_Y(crtc_y) | DSP_POS_X(crtc_x));
> intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
> - ((crtc_h - 1) << 16) | (crtc_w - 1));
> + DSP_HEIGHT(crtc_h - 1) | DSP_POS_X(crtc_w - 1));
DSP_HEIGHT(crtc_h - 1) | DSP_WIDTH(crtc_w - 1));
> }
>
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> @@ -464,20 +464,20 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
> int crtc_h = drm_rect_height(&plane_state->uapi.dst);
>
> intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
> - (crtc_y << 16) | crtc_x);
> + PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x));
> intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
> - ((crtc_h - 1) << 16) | (crtc_w - 1));
> + PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1));
> intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
> }
>
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
> - (y << 16) | x);
> + DSP_OFFSET_Y(y) | DSP_OFFSET_X(x));
> } else if (DISPLAY_VER(dev_priv) >= 4) {
> intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
> linear_offset);
> intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
> - (y << 16) | x);
> + DSP_OFFSET_Y(y) | DSP_OFFSET_X(x));
> }
>
> /*
> @@ -554,7 +554,7 @@ g4x_primary_async_flip(struct intel_plane *plane,
> unsigned long irqflags;
>
> if (async_flip)
> - dspcntr |= DISPPLANE_ASYNC_FLIP;
> + dspcntr |= DSP_ASYNC_FLIP;
>
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
> @@ -686,13 +686,12 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
>
> val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
>
> - ret = val & DISPLAY_PLANE_ENABLE;
> + ret = val & DSP_ENABLE;
>
> if (DISPLAY_VER(dev_priv) >= 5)
> *pipe = plane->pipe;
> else
> - *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
> - DISPPLANE_SEL_PIPE_SHIFT;
> + *pipe = REG_FIELD_GET(DSP_PIPE_SEL_MASK, val);
>
> intel_display_power_put(dev_priv, power_domain, wakeref);
>
> @@ -951,32 +950,32 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> static int i9xx_format_to_fourcc(int format)
> {
> switch (format) {
> - case DISPPLANE_8BPP:
> + case DSP_FORMAT_8BPP:
> return DRM_FORMAT_C8;
> - case DISPPLANE_BGRA555:
> + case DSP_FORMAT_BGRA555:
> return DRM_FORMAT_ARGB1555;
> - case DISPPLANE_BGRX555:
> + case DSP_FORMAT_BGRX555:
> return DRM_FORMAT_XRGB1555;
> - case DISPPLANE_BGRX565:
> + case DSP_FORMAT_BGRX565:
> return DRM_FORMAT_RGB565;
> default:
> - case DISPPLANE_BGRX888:
> + case DSP_FORMAT_BGRX888:
> return DRM_FORMAT_XRGB8888;
> - case DISPPLANE_RGBX888:
> + case DSP_FORMAT_RGBX888:
> return DRM_FORMAT_XBGR8888;
> - case DISPPLANE_BGRA888:
> + case DSP_FORMAT_BGRA888:
> return DRM_FORMAT_ARGB8888;
> - case DISPPLANE_RGBA888:
> + case DSP_FORMAT_RGBA888:
> return DRM_FORMAT_ABGR8888;
> - case DISPPLANE_BGRX101010:
> + case DSP_FORMAT_BGRX101010:
> return DRM_FORMAT_XRGB2101010;
> - case DISPPLANE_RGBX101010:
> + case DSP_FORMAT_RGBX101010:
> return DRM_FORMAT_XBGR2101010;
> - case DISPPLANE_BGRA101010:
> + case DSP_FORMAT_BGRA101010:
> return DRM_FORMAT_ARGB2101010;
> - case DISPPLANE_RGBA101010:
> + case DSP_FORMAT_RGBA101010:
> return DRM_FORMAT_ABGR2101010;
> - case DISPPLANE_RGBX161616:
> + case DSP_FORMAT_RGBX161616:
> return DRM_FORMAT_XBGR16161616F;
> }
> }
> @@ -1014,26 +1013,26 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
> val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
>
> if (DISPLAY_VER(dev_priv) >= 4) {
> - if (val & DISPPLANE_TILED) {
> + if (val & DSP_TILED) {
> plane_config->tiling = I915_TILING_X;
> fb->modifier = I915_FORMAT_MOD_X_TILED;
> }
>
> - if (val & DISPPLANE_ROTATE_180)
> + if (val & DSP_ROTATE_180)
> plane_config->rotation = DRM_MODE_ROTATE_180;
> }
>
> if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
> - val & DISPPLANE_MIRROR)
> + val & DSP_MIRROR)
> plane_config->rotation |= DRM_MODE_REFLECT_X;
>
> - pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
> + pixel_format = val & DSP_FORMAT_MASK;
> fourcc = i9xx_format_to_fourcc(pixel_format);
> fb->format = drm_format_info(fourcc);
>
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
> - base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
> + base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DSP_ADDR_MASK;
> } else if (DISPLAY_VER(dev_priv) >= 4) {
> if (plane_config->tiling)
> offset = intel_de_read(dev_priv,
> @@ -1041,7 +1040,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
> else
> offset = intel_de_read(dev_priv,
> DSPLINOFF(i9xx_plane));
> - base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
> + base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DSP_ADDR_MASK;
> } else {
> base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 726c1552c9bf..00a2c9915780 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3534,11 +3534,11 @@ static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
>
> tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
>
> - if (tmp & DISPPLANE_GAMMA_ENABLE)
> + if (tmp & DSP_PIPE_GAMMA_ENABLE)
> crtc_state->gamma_enable = true;
>
> if (!HAS_GMCH(dev_priv) &&
> - tmp & DISPPLANE_PIPE_CSC_ENABLE)
> + tmp & DSP_PIPE_CSC_ENABLE)
> crtc_state->csc_enable = true;
> }
>
> @@ -10035,14 +10035,11 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> pipe_name(pipe));
>
> drm_WARN_ON(&dev_priv->drm,
> - intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
> - DISPLAY_PLANE_ENABLE);
> + intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DSP_ENABLE);
> drm_WARN_ON(&dev_priv->drm,
> - intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
> - DISPLAY_PLANE_ENABLE);
> + intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DSP_ENABLE);
> drm_WARN_ON(&dev_priv->drm,
> - intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
> - DISPLAY_PLANE_ENABLE);
> + intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DSP_ENABLE);
> drm_WARN_ON(&dev_priv->drm,
> intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
> drm_WARN_ON(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9fffa2392bbf..8678cbab1d33 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6824,49 +6824,54 @@ enum {
> /* Display A control */
> #define _DSPAADDR_VLV 0x7017C /* vlv/chv */
> #define _DSPACNTR 0x70180
> -#define DISPLAY_PLANE_ENABLE (1 << 31)
> -#define DISPLAY_PLANE_DISABLE 0
> -#define DISPPLANE_GAMMA_ENABLE (1 << 30)
> -#define DISPPLANE_GAMMA_DISABLE 0
> -#define DISPPLANE_PIXFORMAT_MASK (0xf << 26)
> -#define DISPPLANE_YUV422 (0x0 << 26)
> -#define DISPPLANE_8BPP (0x2 << 26)
> -#define DISPPLANE_BGRA555 (0x3 << 26)
> -#define DISPPLANE_BGRX555 (0x4 << 26)
> -#define DISPPLANE_BGRX565 (0x5 << 26)
> -#define DISPPLANE_BGRX888 (0x6 << 26)
> -#define DISPPLANE_BGRA888 (0x7 << 26)
> -#define DISPPLANE_RGBX101010 (0x8 << 26)
> -#define DISPPLANE_RGBA101010 (0x9 << 26)
> -#define DISPPLANE_BGRX101010 (0xa << 26)
> -#define DISPPLANE_BGRA101010 (0xb << 26)
> -#define DISPPLANE_RGBX161616 (0xc << 26)
> -#define DISPPLANE_RGBX888 (0xe << 26)
> -#define DISPPLANE_RGBA888 (0xf << 26)
> -#define DISPPLANE_STEREO_ENABLE (1 << 25)
> -#define DISPPLANE_STEREO_DISABLE 0
> -#define DISPPLANE_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
> -#define DISPPLANE_SEL_PIPE_SHIFT 24
> -#define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT)
> -#define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
> -#define DISPPLANE_SRC_KEY_ENABLE (1 << 22)
> -#define DISPPLANE_SRC_KEY_DISABLE 0
> -#define DISPPLANE_LINE_DOUBLE (1 << 20)
> -#define DISPPLANE_NO_LINE_DOUBLE 0
> -#define DISPPLANE_STEREO_POLARITY_FIRST 0
> -#define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)
> -#define DISPPLANE_ALPHA_PREMULTIPLY (1 << 16) /* CHV pipe B */
> -#define DISPPLANE_ROTATE_180 (1 << 15)
> -#define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14) /* Ironlake */
> -#define DISPPLANE_TILED (1 << 10)
> -#define DISPPLANE_ASYNC_FLIP (1 << 9) /* g4x+ */
> -#define DISPPLANE_MIRROR (1 << 8) /* CHV pipe B */
> +#define DSP_ENABLE REG_BIT(31)
I really don't like DSP, it is broadly used acronym to Digital Signal Processors.
Would prefer to have DISPLAY or DISP.
Anyways, DSP_ENABLE should have also have plane on it.
Other than above and a minor typo reported in general looks good to me but it also broke build because it missed GVT renames.
> +#define DSP_PIPE_GAMMA_ENABLE REG_BIT(30)
> +#define DSP_FORMAT_MASK REG_GENMASK(29, 26)
> +#define DSP_FORMAT_8BPP REG_FIELD_PREP(DSP_FORMAT_MASK, 2)
> +#define DSP_FORMAT_BGRA555 REG_FIELD_PREP(DSP_FORMAT_MASK, 3)
> +#define DSP_FORMAT_BGRX555 REG_FIELD_PREP(DSP_FORMAT_MASK, 4)
> +#define DSP_FORMAT_BGRX565 REG_FIELD_PREP(DSP_FORMAT_MASK, 5)
> +#define DSP_FORMAT_BGRX888 REG_FIELD_PREP(DSP_FORMAT_MASK, 6)
> +#define DSP_FORMAT_BGRA888 REG_FIELD_PREP(DSP_FORMAT_MASK, 7)
> +#define DSP_FORMAT_RGBX101010 REG_FIELD_PREP(DSP_FORMAT_MASK, 8)
> +#define DSP_FORMAT_RGBA101010 REG_FIELD_PREP(DSP_FORMAT_MASK, 9)
> +#define DSP_FORMAT_BGRX101010 REG_FIELD_PREP(DSP_FORMAT_MASK, 10)
> +#define DSP_FORMAT_BGRA101010 REG_FIELD_PREP(DSP_FORMAT_MASK, 11)
> +#define DSP_FORMAT_RGBX161616 REG_FIELD_PREP(DSP_FORMAT_MASK, 12)
> +#define DSP_FORMAT_RGBX888 REG_FIELD_PREP(DSP_FORMAT_MASK, 14)
> +#define DSP_FORMAT_RGBA888 REG_FIELD_PREP(DSP_FORMAT_MASK, 15)
> +#define DSP_STEREO_ENABLE REG_BIT(25)
> +#define DSP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
> +#define DSP_PIPE_SEL_MASK REG_GENMASK(25, 24)
> +#define DSP_PIPE_SEL(pipe) REG_FIELD_PREP(DSP_PIPE_SEL_MASK, (pipe))
> +#define DSP_SRC_KEY_ENABLE REG_BIT(22)
> +#define DSP_LINE_DOUBLE REG_BIT(20)
> +#define DSP_STEREO_POLARITY_SECOND REG_BIT(18)
> +#define DSP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
> +#define DSP_ROTATE_180 REG_BIT(15)
> +#define DSP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */
> +#define DSP_TILED REG_BIT(10)
> +#define DSP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
> +#define DSP_MIRROR REG_BIT(8) /* CHV pipe B */
> #define _DSPAADDR 0x70184
> #define _DSPASTRIDE 0x70188
> #define _DSPAPOS 0x7018C /* reserved */
> +#define DSP_POS_Y_MASK REG_GENMASK(31, 0)
> +#define DSP_POS_Y(y) REG_FIELD_PREP(DSP_POS_Y_MASK, (y))
> +#define DSP_POS_X_MASK REG_GENMASK(15, 0)
> +#define DSP_POS_X(x) REG_FIELD_PREP(DSP_POS_X_MASK, (x))
> #define _DSPASIZE 0x70190
> +#define DSP_HEIGHT_MASK REG_GENMASK(31, 0)
> +#define DSP_HEIGHT(h) REG_FIELD_PREP(DSP_HEIGHT_MASK, (h))
> +#define DSP_WIDTH_MASK REG_GENMASK(15, 0)
> +#define DSP_WIDTH(w) REG_FIELD_PREP(DSP_WIDTH_MASK, (w))
> #define _DSPASURF 0x7019C /* 965+ only */
> +#define DSP_ADDR_MASK REG_GENMASK(31, 12)
> #define _DSPATILEOFF 0x701A4 /* 965+ only */
> +#define DSP_OFFSET_Y_MASK REG_GENMASK(31, 16)
> +#define DSP_OFFSET_Y(y) REG_FIELD_PREP(DSP_OFFSET_Y_MASK, (y))
> +#define DSP_OFFSET_X_MASK REG_GENMASK(15, 0)
> +#define DSP_OFFSET_X(x) REG_FIELD_PREP(DSP_OFFSET_X_MASK, (x))
> #define _DSPAOFFSET 0x701A4 /* HSW */
> #define _DSPASURFLIVE 0x701AC
> #define _DSPAGAMC 0x701E0
> @@ -6886,15 +6891,28 @@ enum {
>
> /* CHV pipe B blender and primary plane */
> #define _CHV_BLEND_A 0x60a00
> -#define CHV_BLEND_LEGACY (0 << 30)
> -#define CHV_BLEND_ANDROID (1 << 30)
> -#define CHV_BLEND_MPO (2 << 30)
> -#define CHV_BLEND_MASK (3 << 30)
> +#define CHV_BLEND_MASK REG_GENMASK(31, 30)
> +#define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
> +#define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1)
> +#define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2)
> #define _CHV_CANVAS_A 0x60a04
> +#define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
> +#define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
> +#define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
> #define _PRIMPOS_A 0x60a08
> +#define PRIM_POS_Y_MASK REG_GENMASK(31, 16)
> +#define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
> +#define PRIM_POS_X_MASK REG_GENMASK(15, 0)
> +#define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x))
> #define _PRIMSIZE_A 0x60a0c
> +#define PRIM_HEIGHT_MASK REG_GENMASK(31, 16)
> +#define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))
> +#define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
> +#define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
> #define _PRIMCNSTALPHA_A 0x60a10
> -#define PRIM_CONST_ALPHA_ENABLE (1 << 31)
> +#define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
> +#define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0)
> +#define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))
>
> #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
> #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
> @@ -6935,10 +6953,8 @@ enum {
>
> /* Display B control */
> #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
> -#define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
> -#define DISPPLANE_ALPHA_TRANS_DISABLE 0
> -#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
> -#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
> +#define DSP_ALPHA_TRANS_ENABLE REG_BIT(15)
> +#define DSP_SPRITE_ABOVE_OVERLAY REG_BIT(0)
> #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
> #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
> #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7f00fd2f62a0..2941c2cd1708 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7211,7 +7211,7 @@ static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
> for_each_pipe(dev_priv, pipe) {
> intel_uncore_write(&dev_priv->uncore, DSPCNTR(pipe),
> intel_uncore_read(&dev_priv->uncore, DSPCNTR(pipe)) |
> - DISPPLANE_TRICKLE_FEED_DISABLE);
> + DSP_TRICKLE_FEED_DISABLE);
>
> intel_uncore_write(&dev_priv->uncore, DSPSURF(pipe), intel_uncore_read(&dev_priv->uncore, DSPSURF(pipe)));
> intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe));
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 08/14] drm/i915: Clean up ivb+ sprite plane registers
2021-12-01 15:25 ` [Intel-gfx] [PATCH 08/14] drm/i915: Clean up ivb+ sprite " Ville Syrjala
@ 2022-01-14 16:26 ` Souza, Jose
0 siblings, 0 replies; 48+ messages in thread
From: Souza, Jose @ 2022-01-14 16:26 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use REG_BIT() & co. to polish the ivb+ sprite plane registers.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 20 +++--
> drivers/gpu/drm/i915/i915_reg.h | 81 +++++++++++++--------
> 2 files changed, 62 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 2067a7bca4a8..70083d04a9fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -700,7 +700,7 @@ static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
> u32 sprctl = 0;
>
> if (crtc_state->gamma_enable)
> - sprctl |= SPRITE_GAMMA_ENABLE;
> + sprctl |= SPRITE_PIPE_GAMMA_ENABLE;
>
> if (crtc_state->csc_enable)
> sprctl |= SPRITE_PIPE_CSC_ENABLE;
> @@ -770,7 +770,7 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
> }
>
> if (!ivb_need_sprite_gamma(plane_state))
> - sprctl |= SPRITE_INT_GAMMA_DISABLE;
> + sprctl |= SPRITE_PLANE_GAMMA_DISABLE;
>
> if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
> sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
> @@ -863,14 +863,18 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
> unsigned long irqflags;
>
> if (crtc_w != src_w || crtc_h != src_h)
> - sprscale = SPRITE_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
> + sprscale = SPRITE_SCALE_ENABLE |
> + SPRITE_SRC_WIDTH(src_w - 1) |
> + SPRITE_SRC_HEIGHT(src_h - 1);
>
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
> plane_state->view.color_plane[0].mapping_stride);
> - intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x);
> - intel_de_write_fw(dev_priv, SPRSIZE(pipe), ((crtc_h - 1) << 16) | (crtc_w - 1));
> + intel_de_write_fw(dev_priv, SPRPOS(pipe),
> + SPRITE_POS_Y(crtc_y) | SPRITE_POS_X(crtc_x));
> + intel_de_write_fw(dev_priv, SPRSIZE(pipe),
> + SPRITE_HEIGHT(crtc_h - 1) | SPRITE_WIDTH(crtc_w - 1));
> if (IS_IVYBRIDGE(dev_priv))
> intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
>
> @@ -907,10 +911,12 @@ ivb_sprite_update_arm(struct intel_plane *plane,
> /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
> * register */
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> - intel_de_write_fw(dev_priv, SPROFFSET(pipe), (y << 16) | x);
> + intel_de_write_fw(dev_priv, SPROFFSET(pipe),
> + SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x));
> } else {
> intel_de_write_fw(dev_priv, SPRLINOFF(pipe), linear_offset);
> - intel_de_write_fw(dev_priv, SPRTILEOFF(pipe), (y << 16) | x);
> + intel_de_write_fw(dev_priv, SPRTILEOFF(pipe),
> + SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x));
> }
>
> /*
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8678cbab1d33..0bd47a929f5d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7046,50 +7046,67 @@ enum {
> #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
>
> #define _SPRA_CTL 0x70280
> -#define SPRITE_ENABLE (1 << 31)
> -#define SPRITE_GAMMA_ENABLE (1 << 30)
> -#define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
> -#define SPRITE_PIXFORMAT_MASK (7 << 25)
> -#define SPRITE_FORMAT_YUV422 (0 << 25)
> -#define SPRITE_FORMAT_RGBX101010 (1 << 25)
> -#define SPRITE_FORMAT_RGBX888 (2 << 25)
> -#define SPRITE_FORMAT_RGBX161616 (3 << 25)
> -#define SPRITE_FORMAT_YUV444 (4 << 25)
> -#define SPRITE_FORMAT_XR_BGR101010 (5 << 25) /* Extended range */
> -#define SPRITE_PIPE_CSC_ENABLE (1 << 24)
> -#define SPRITE_SOURCE_KEY (1 << 22)
> -#define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and 161616 */
> -#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)
> -#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */
> -#define SPRITE_YUV_ORDER_MASK (3 << 16)
> -#define SPRITE_YUV_ORDER_YUYV (0 << 16)
> -#define SPRITE_YUV_ORDER_UYVY (1 << 16)
> -#define SPRITE_YUV_ORDER_YVYU (2 << 16)
> -#define SPRITE_YUV_ORDER_VYUY (3 << 16)
> -#define SPRITE_ROTATE_180 (1 << 15)
> -#define SPRITE_TRICKLE_FEED_DISABLE (1 << 14)
> -#define SPRITE_INT_GAMMA_DISABLE (1 << 13)
> -#define SPRITE_TILED (1 << 10)
> -#define SPRITE_DEST_KEY (1 << 2)
> +#define SPRITE_ENABLE REG_BIT(31)
> +#define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30)
> +#define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
> +#define SPRITE_FORMAT_MASK REG_GENMASK(27, 25)
> +#define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0)
> +#define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1)
> +#define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2)
> +#define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3)
> +#define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4)
> +#define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */
> +#define SPRITE_PIPE_CSC_ENABLE REG_BIT(24)
> +#define SPRITE_SOURCE_KEY REG_BIT(22)
> +#define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */
> +#define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19)
> +#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */
> +#define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16)
> +#define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)
> +#define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1)
> +#define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2)
> +#define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3)
> +#define SPRITE_ROTATE_180 REG_BIT(15)
> +#define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14)
> +#define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13)
> +#define SPRITE_TILED REG_BIT(10)
> +#define SPRITE_DEST_KEY REG_BIT(2)
> #define _SPRA_LINOFF 0x70284
> #define _SPRA_STRIDE 0x70288
> #define _SPRA_POS 0x7028c
> +#define SPRITE_POS_Y_MASK REG_GENMASK(31, 16)
> +#define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))
> +#define SPRITE_POS_X_MASK REG_GENMASK(15, 0)
> +#define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))
> #define _SPRA_SIZE 0x70290
> +#define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16)
> +#define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))
> +#define SPRITE_WIDTH_MASK REG_GENMASK(15, 0)
> +#define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))
> #define _SPRA_KEYVAL 0x70294
> #define _SPRA_KEYMSK 0x70298
> #define _SPRA_SURF 0x7029c
> +#define SPRITE_ADDR_MASK REG_GENMASK(31, 12)
> #define _SPRA_KEYMAX 0x702a0
> #define _SPRA_TILEOFF 0x702a4
> +#define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
> +#define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
> +#define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
> +#define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
> #define _SPRA_OFFSET 0x702a4
> #define _SPRA_SURFLIVE 0x702ac
> #define _SPRA_SCALE 0x70304
> -#define SPRITE_SCALE_ENABLE (1 << 31)
> -#define SPRITE_FILTER_MASK (3 << 29)
> -#define SPRITE_FILTER_MEDIUM (0 << 29)
> -#define SPRITE_FILTER_ENHANCING (1 << 29)
> -#define SPRITE_FILTER_SOFTENING (2 << 29)
> -#define SPRITE_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
> -#define SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27)
> +#define SPRITE_SCALE_ENABLE REG_BIT(31)
> +#define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
> +#define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
> +#define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1)
> +#define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2)
> +#define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
> +#define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27)
> +#define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16)
> +#define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))
> +#define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
> +#define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))
> #define _SPRA_GAMC 0x70400
> #define _SPRA_GAMC16 0x70440
> #define _SPRA_GAMC17 0x7044c
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 09/14] drm/i915: Clean up vlv/chv sprite plane registers
2021-12-01 15:25 ` [Intel-gfx] [PATCH 09/14] drm/i915: Clean up vlv/chv " Ville Syrjala
@ 2022-01-14 16:34 ` Souza, Jose
2022-01-18 1:11 ` Ville Syrjälä
0 siblings, 1 reply; 48+ messages in thread
From: Souza, Jose @ 2022-01-14 16:34 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use REG_BIT() & co. to polish the vlv/chv sprite plane registers.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 9 +-
> drivers/gpu/drm/i915/i915_reg.h | 103 ++++++++++++--------
> 2 files changed, 70 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 70083d04a9fd..eb9ce96c030f 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -313,7 +313,7 @@ static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
> u32 sprctl = 0;
>
> if (crtc_state->gamma_enable)
> - sprctl |= SP_GAMMA_ENABLE;
> + sprctl |= SP_PIPE_GAMMA_ENABLE;
>
> return sprctl;
> }
> @@ -436,9 +436,9 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
> plane_state->view.color_plane[0].mapping_stride);
> intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),
> - (crtc_y << 16) | crtc_x);
> + SP_POS_Y(crtc_y) | SP_POS_X(crtc_x));
> intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
> - ((crtc_h - 1) << 16) | (crtc_w - 1));
> + SP_HEIGHT(crtc_h - 1) | SP_WIDTH(crtc_w - 1));
>
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
> @@ -479,7 +479,8 @@ vlv_sprite_update_arm(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0);
>
> intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset);
> - intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id), (y << 16) | x);
> + intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id),
> + SP_OFFSET_Y(y) | SP_OFFSET_X(x));
>
> /*
> * The control register self-arms if the plane was previously
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0bd47a929f5d..4d61e7f2ee7c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7146,48 +7146,67 @@ enum {
> #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
>
> #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
> -#define SP_ENABLE (1 << 31)
> -#define SP_GAMMA_ENABLE (1 << 30)
> -#define SP_PIXFORMAT_MASK (0xf << 26)
> -#define SP_FORMAT_YUV422 (0x0 << 26)
> -#define SP_FORMAT_8BPP (0x2 << 26)
> -#define SP_FORMAT_BGR565 (0x5 << 26)
> -#define SP_FORMAT_BGRX8888 (0x6 << 26)
> -#define SP_FORMAT_BGRA8888 (0x7 << 26)
> -#define SP_FORMAT_RGBX1010102 (0x8 << 26)
> -#define SP_FORMAT_RGBA1010102 (0x9 << 26)
> -#define SP_FORMAT_BGRX1010102 (0xa << 26) /* CHV pipe B */
> -#define SP_FORMAT_BGRA1010102 (0xb << 26) /* CHV pipe B */
> -#define SP_FORMAT_RGBX8888 (0xe << 26)
> -#define SP_FORMAT_RGBA8888 (0xf << 26)
> -#define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
> -#define SP_SOURCE_KEY (1 << 22)
> -#define SP_YUV_FORMAT_BT709 (1 << 18)
> -#define SP_YUV_ORDER_MASK (3 << 16)
> -#define SP_YUV_ORDER_YUYV (0 << 16)
> -#define SP_YUV_ORDER_UYVY (1 << 16)
> -#define SP_YUV_ORDER_YVYU (2 << 16)
> -#define SP_YUV_ORDER_VYUY (3 << 16)
> -#define SP_ROTATE_180 (1 << 15)
> -#define SP_TILED (1 << 10)
> -#define SP_MIRROR (1 << 8) /* CHV pipe B */
> +#define SP_ENABLE REG_BIT(31)
> +#define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
> +#define SP_FORMAT_MASK REG_GENMASK(29, 26)
> +#define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0)
> +#define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2)
> +#define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5)
> +#define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6)
> +#define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7)
> +#define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8)
> +#define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9)
> +#define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */
> +#define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */
> +#define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14)
> +#define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15)
> +#define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */
> +#define SP_SOURCE_KEY REG_BIT(22)
> +#define SP_YUV_FORMAT_BT709 REG_BIT(18)
> +#define SP_YUV_ORDER_MASK REG_GENMASK(17, 16)
> +#define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0)
> +#define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1)
> +#define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2)
> +#define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3)
> +#define SP_ROTATE_180 REG_BIT(15)
> +#define SP_TILED REG_BIT(10)
> +#define SP_MIRROR REG_BIT(8) /* CHV pipe B */
> #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
> #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
> #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
> +#define SP_POS_Y_MASK REG_GENMASK(31, 16)
> +#define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y))
> +#define SP_POS_X_MASK REG_GENMASK(15, 0)
> +#define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x))
> #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
> +#define SP_HEIGHT_MASK REG_GENMASK(31, 16)
> +#define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h))
> +#define SP_WIDTH_MASK REG_GENMASK(15, 0)
> +#define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w))
> #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
> #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
> #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
> +#define SP_ADDR_MASK REG_GENMASK(31, 12)
> #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
> #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
> +#define SP_OFFSET_Y_MASK REG_GENMASK(31, 16)
> +#define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))
> +#define SP_OFFSET_X_MASK REG_GENMASK(15, 0)
> +#define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))
> #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
> -#define SP_CONST_ALPHA_ENABLE (1 << 31)
> +#define SP_CONST_ALPHA_ENABLE REG_BIT(31)
> +#define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
> +#define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
> #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
> -#define SP_CONTRAST(x) ((x) << 18) /* u3.6 */
> -#define SP_BRIGHTNESS(x) ((x) & 0xff) /* s8 */
> +#define SP_CONTRAST_MASK REG_GENMASK(26, 18)
> +#define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
> +#define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0)
> +#define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */
> #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
> -#define SP_SH_SIN(x) (((x) & 0x7ff) << 16) /* s4.7 */
> -#define SP_SH_COS(x) (x) /* u3.7 */
> +#define SP_SH_SIN_MASK REG_GENMASK(26, 16)
> +#define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */
> +#define SP_SH_COS_MASK REG_GENMASK(9, 0)
> +#define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */
> #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
>
> #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
> @@ -7238,28 +7257,36 @@ enum {
> #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
> #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
> #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
> -#define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
> -#define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
> +#define SPCSC_OOFF_MASK REG_GENMASK(26, 16)
> +#define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
With REG_FIELD_PREP you don't need to do (x) & 0x7ff.
With all of similar cases fixed:
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> +#define SPCSC_IOFF_MASK REG_GENMASK(10, 0)
> +#define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */
>
> #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
> #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
> #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
> #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
> #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
> -#define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
> -#define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
> +#define SPCSC_C1_MASK REG_GENMASK(30, 16)
> +#define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */
> +#define SPCSC_C0_MASK REG_GENMASK(14, 0)
> +#define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */
>
> #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
> #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
> #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
> -#define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
> -#define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
> +#define SPCSC_IMAX_MASK REG_GENMASK(26, 16)
> +#define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */
> +#define SPCSC_IMIN_MASK REG_GENMASK(10, 0)
> +#define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */
>
> #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
> #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
> #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
> -#define SPCSC_OMAX(x) ((x) << 16) /* u10 */
> -#define SPCSC_OMIN(x) ((x) << 0) /* u10 */
> +#define SPCSC_OMAX_MASK REG_GENMASK(25, 16)
> +#define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */
> +#define SPCSC_OMIN_MASK REG_GENMASK(9, 0)
> +#define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */
>
> /* Skylake plane registers */
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 10/14] drm/i915: Clean up g4x+ sprite plane registers
2021-12-01 15:25 ` [Intel-gfx] [PATCH 10/14] drm/i915: Clean up g4x+ " Ville Syrjala
@ 2022-01-14 16:38 ` Souza, Jose
0 siblings, 0 replies; 48+ messages in thread
From: Souza, Jose @ 2022-01-14 16:38 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use REG_BIT() & co. to polish the g4x+ sprite plane registers.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 12 ++--
> drivers/gpu/drm/i915/i915_reg.h | 73 +++++++++++++--------
> 2 files changed, 53 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index eb9ce96c030f..6f2a560700ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -1054,7 +1054,7 @@ static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
> u32 dvscntr = 0;
>
> if (crtc_state->gamma_enable)
> - dvscntr |= DVS_GAMMA_ENABLE;
> + dvscntr |= DVS_PIPE_GAMMA_ENABLE;
>
> if (crtc_state->csc_enable)
> dvscntr |= DVS_PIPE_CSC_ENABLE;
> @@ -1206,14 +1206,18 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
> unsigned long irqflags;
>
> if (crtc_w != src_w || crtc_h != src_h)
> - dvsscale = DVS_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
> + dvsscale = DVS_SCALE_ENABLE |
> + DVS_SRC_WIDTH(src_w - 1) |
> + DVS_SRC_HEIGHT(src_h - 1);
>
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
> plane_state->view.color_plane[0].mapping_stride);
> - intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x);
> - intel_de_write_fw(dev_priv, DVSSIZE(pipe), ((crtc_h - 1) << 16) | (crtc_w - 1));
> + intel_de_write_fw(dev_priv, DVSPOS(pipe),
> + DVS_POS_Y(crtc_y) | DVS_POS_X(crtc_x));
> + intel_de_write_fw(dev_priv, DVSSIZE(pipe),
> + DVS_HEIGHT(crtc_h - 1) | DVS_WIDTH(crtc_w - 1));
> intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
>
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4d61e7f2ee7c..d215cad95fe8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6970,46 +6970,63 @@ enum {
>
> /* Sprite A control */
> #define _DVSACNTR 0x72180
> -#define DVS_ENABLE (1 << 31)
> -#define DVS_GAMMA_ENABLE (1 << 30)
> -#define DVS_YUV_RANGE_CORRECTION_DISABLE (1 << 27)
> -#define DVS_PIXFORMAT_MASK (3 << 25)
> -#define DVS_FORMAT_YUV422 (0 << 25)
> -#define DVS_FORMAT_RGBX101010 (1 << 25)
> -#define DVS_FORMAT_RGBX888 (2 << 25)
> -#define DVS_FORMAT_RGBX161616 (3 << 25)
> -#define DVS_PIPE_CSC_ENABLE (1 << 24)
> -#define DVS_SOURCE_KEY (1 << 22)
> -#define DVS_RGB_ORDER_XBGR (1 << 20)
> -#define DVS_YUV_FORMAT_BT709 (1 << 18)
> -#define DVS_YUV_ORDER_MASK (3 << 16)
> -#define DVS_YUV_ORDER_YUYV (0 << 16)
> -#define DVS_YUV_ORDER_UYVY (1 << 16)
> -#define DVS_YUV_ORDER_YVYU (2 << 16)
> -#define DVS_YUV_ORDER_VYUY (3 << 16)
> -#define DVS_ROTATE_180 (1 << 15)
> -#define DVS_DEST_KEY (1 << 2)
> -#define DVS_TRICKLE_FEED_DISABLE (1 << 14)
> -#define DVS_TILED (1 << 10)
> +#define DVS_ENABLE REG_BIT(31)
> +#define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
> +#define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
> +#define DVS_FORMAT_MASK REG_GENMASK(26, 25)
> +#define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
> +#define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1)
> +#define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
> +#define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3)
> +#define DVS_PIPE_CSC_ENABLE REG_BIT(24)
> +#define DVS_SOURCE_KEY REG_BIT(22)
> +#define DVS_RGB_ORDER_XBGR REG_BIT(20)
> +#define DVS_YUV_FORMAT_BT709 REG_BIT(18)
> +#define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16)
> +#define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
> +#define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
> +#define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
> +#define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
> +#define DVS_ROTATE_180 REG_BIT(15)
> +#define DVS_DEST_KEY REG_BIT(2)
> +#define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
> +#define DVS_TILED REG_BIT(10)
> #define _DVSALINOFF 0x72184
> #define _DVSASTRIDE 0x72188
> #define _DVSAPOS 0x7218c
> +#define DVS_POS_Y_MASK REG_GENMASK(31, 16)
> +#define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
> +#define DVS_POS_X_MASK REG_GENMASK(15, 0)
> +#define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))
> #define _DVSASIZE 0x72190
> +#define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
> +#define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
> +#define DVS_WIDTH_MASK REG_GENMASK(15, 0)
> +#define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
> #define _DVSAKEYVAL 0x72194
> #define _DVSAKEYMSK 0x72198
> #define _DVSASURF 0x7219c
> +#define DVS_ADDR_MASK REG_GENMASK(31, 12)
> #define _DVSAKEYMAXVAL 0x721a0
> #define _DVSATILEOFF 0x721a4
> +#define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16)
> +#define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
> +#define DVS_OFFSET_X_MASK REG_GENMASK(15, 0)
> +#define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
> #define _DVSASURFLIVE 0x721ac
> #define _DVSAGAMC_G4X 0x721e0 /* g4x */
> #define _DVSASCALE 0x72204
> -#define DVS_SCALE_ENABLE (1 << 31)
> -#define DVS_FILTER_MASK (3 << 29)
> -#define DVS_FILTER_MEDIUM (0 << 29)
> -#define DVS_FILTER_ENHANCING (1 << 29)
> -#define DVS_FILTER_SOFTENING (2 << 29)
> -#define DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
> -#define DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
> +#define DVS_SCALE_ENABLE REG_BIT(31)
> +#define DVS_FILTER_MASK REG_GENMASK(30, 29)
> +#define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0)
> +#define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1)
> +#define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2)
> +#define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
> +#define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27)
> +#define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16)
> +#define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
> +#define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
> +#define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
> #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
> #define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 11/14] drm/i915: Clean up cursor registers
2021-12-01 15:25 ` [Intel-gfx] [PATCH 11/14] drm/i915: Clean up cursor registers Ville Syrjala
@ 2022-01-14 16:45 ` Souza, Jose
0 siblings, 0 replies; 48+ messages in thread
From: Souza, Jose @ 2022-01-14 16:45 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use REG_BIT() & co. to polish the cursor plane registers.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cursor.c | 25 ++++---
> drivers/gpu/drm/i915/display/intel_display.c | 4 +-
> drivers/gpu/drm/i915/i915_reg.h | 71 +++++++++++---------
> 3 files changed, 53 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index 16d34685d83f..2ade8fdd9bdd 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -51,16 +51,16 @@ static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
> u32 pos = 0;
>
> if (x < 0) {
> - pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
> + pos |= CURSOR_POS_X_SIGN;
> x = -x;
> }
> - pos |= x << CURSOR_X_SHIFT;
> + pos |= CURSOR_POS_X(x);
>
> if (y < 0) {
> - pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
> + pos |= CURSOR_POS_Y_SIGN;
> y = -y;
> }
> - pos |= y << CURSOR_Y_SHIFT;
> + pos |= CURSOR_POS_Y(y);
>
> return pos;
> }
> @@ -180,7 +180,7 @@ static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
> u32 cntl = 0;
>
> if (crtc_state->gamma_enable)
> - cntl |= CURSOR_GAMMA_ENABLE;
> + cntl |= CURSOR_PIPE_GAMMA_ENABLE;
>
> return cntl;
> }
> @@ -264,7 +264,7 @@ static void i845_cursor_update_arm(struct intel_plane *plane,
> cntl = plane_state->ctl |
> i845_cursor_ctl_crtc(crtc_state);
>
> - size = (height << 12) | width;
> + size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width);
>
> base = intel_cursor_base(plane_state);
> pos = intel_cursor_position(plane_state);
> @@ -280,7 +280,7 @@ static void i845_cursor_update_arm(struct intel_plane *plane,
> plane->cursor.cntl != cntl) {
> intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
> intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
> - intel_de_write_fw(dev_priv, CURSIZE, size);
> + intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
> intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
> intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
>
> @@ -340,13 +340,13 @@ static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
> return cntl;
>
> if (crtc_state->gamma_enable)
> - cntl = MCURSOR_GAMMA_ENABLE;
> + cntl = MCURSOR_PIPE_GAMMA_ENABLE;
>
> if (crtc_state->csc_enable)
> cntl |= MCURSOR_PIPE_CSC_ENABLE;
>
> if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
> - cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
> + cntl |= MCURSOR_PIPE_SEL(crtc->pipe);
>
> return cntl;
> }
> @@ -502,7 +502,7 @@ static void i9xx_cursor_update_arm(struct intel_plane *plane,
> i9xx_cursor_ctl_crtc(crtc_state);
>
> if (width != height)
> - fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
> + fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1);
>
> base = intel_cursor_base(plane_state);
> pos = intel_cursor_position(plane_state);
> @@ -586,13 +586,12 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
>
> val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
>
> - ret = val & MCURSOR_MODE;
> + ret = val & MCURSOR_MODE_MASK;
>
> if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
> *pipe = plane->pipe;
> else
> - *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
> - MCURSOR_PIPE_SELECT_SHIFT;
> + *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);
>
> intel_display_power_put(dev_priv, power_domain, wakeref);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 00a2c9915780..34c1463e2ef9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -10041,9 +10041,9 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> drm_WARN_ON(&dev_priv->drm,
> intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DSP_ENABLE);
> drm_WARN_ON(&dev_priv->drm,
> - intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
> + intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
> drm_WARN_ON(&dev_priv->drm,
> - intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
> + intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
>
> intel_de_write(dev_priv, PIPECONF(pipe), 0);
> intel_de_posting_read(dev_priv, PIPECONF(pipe));
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d215cad95fe8..e010add5574a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6761,44 +6761,50 @@ enum {
> /* Cursor A & B regs */
> #define _CURACNTR 0x70080
> /* Old style CUR*CNTR flags (desktop 8xx) */
> -#define CURSOR_ENABLE 0x80000000
> -#define CURSOR_GAMMA_ENABLE 0x40000000
> -#define CURSOR_STRIDE_SHIFT 28
> -#define CURSOR_STRIDE(x) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
> -#define CURSOR_FORMAT_SHIFT 24
> -#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
> -#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
> -#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
> -#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
> -#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
> -#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
> +#define CURSOR_ENABLE REG_BIT(31)
> +#define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
> +#define CURSOR_STRIDE_MASK REG_GENMASK(29, 28)
> +#define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */
> +#define CURSOR_FORMAT_MASK REG_GENMASK(26, 24)
> +#define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0)
> +#define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1)
> +#define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2)
> +#define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4)
> +#define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5)
> /* New style CUR*CNTR flags */
> -#define MCURSOR_MODE 0x27
> -#define MCURSOR_MODE_DISABLE 0x00
> -#define MCURSOR_MODE_128_32B_AX 0x02
> -#define MCURSOR_MODE_256_32B_AX 0x03
> -#define MCURSOR_MODE_64_32B_AX 0x07
> -#define MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
> -#define MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
> -#define MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
> #define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
> #define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */
> -#define MCURSOR_PIPE_SELECT_MASK (0x3 << 28)
> -#define MCURSOR_PIPE_SELECT_SHIFT 28
> -#define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)
> -#define MCURSOR_GAMMA_ENABLE (1 << 26)
> -#define MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
> -#define MCURSOR_ROTATE_180 (1 << 15)
> -#define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14)
> +#define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28)
> +#define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe))
> +#define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26)
> +#define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
> +#define MCURSOR_ROTATE_180 REG_BIT(15)
> +#define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14)
> +#define MCURSOR_MODE_MASK 0x27
> +#define MCURSOR_MODE_DISABLE 0x00
> +#define MCURSOR_MODE_128_32B_AX 0x02
> +#define MCURSOR_MODE_256_32B_AX 0x03
> +#define MCURSOR_MODE_64_32B_AX 0x07
> +#define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX)
> +#define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX)
> +#define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX)
> #define _CURABASE 0x70084
> #define _CURAPOS 0x70088
> -#define CURSOR_POS_MASK 0x007FF
> -#define CURSOR_POS_SIGN 0x8000
> -#define CURSOR_X_SHIFT 0
> -#define CURSOR_Y_SHIFT 16
> -#define CURSIZE _MMIO(0x700a0) /* 845/865 */
> +#define CURSOR_POS_Y_SIGN REG_BIT(31)
> +#define CURSOR_POS_Y_MASK REG_GENMASK(30, 16)
> +#define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))
> +#define CURSOR_POS_X_SIGN REG_BIT(15)
> +#define CURSOR_POS_X_MASK REG_GENMASK(14, 0)
> +#define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))
> +#define _CURASIZE 0x700a0 /* 845/865 */
> +#define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12)
> +#define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))
> +#define CURSOR_WIDTH_MASK REG_GENMASK(9, 0)
> +#define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))
> #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
> -#define CUR_FBC_CTL_EN (1 << 31)
> +#define CUR_FBC_EN REG_BIT(31)
> +#define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0)
> +#define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))
> #define _CURASURFLIVE 0x700ac /* g4x+ */
> #define _CURBCNTR 0x700c0
> #define _CURBBASE 0x700c4
> @@ -6811,6 +6817,7 @@ enum {
> #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
> #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
> #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
> +#define CURSIZE(pipe) _CURSOR2(pipe, _CURASIZE)
> #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
> #define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 07/14] drm/i915: Clean up pre-skl primary plane registers
2022-01-12 20:12 ` Souza, Jose
@ 2022-01-18 0:55 ` Ville Syrjälä
2022-01-18 13:40 ` Souza, Jose
0 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjälä @ 2022-01-18 0:55 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Wed, Jan 12, 2022 at 08:12:31PM +0000, Souza, Jose wrote:
> On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> > @@ -427,9 +427,9 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane,
> > * program whatever is there.
> > */
> > intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
> > - (crtc_y << 16) | crtc_x);
> > + DSP_POS_Y(crtc_y) | DSP_POS_X(crtc_x));
> > intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
> > - ((crtc_h - 1) << 16) | (crtc_w - 1));
> > + DSP_HEIGHT(crtc_h - 1) | DSP_POS_X(crtc_w - 1));
>
> DSP_HEIGHT(crtc_h - 1) | DSP_WIDTH(crtc_w - 1));
Whoops. Thanks for cathcing that.
<snip>
> > +#define DSP_ENABLE REG_BIT(31)
>
> I really don't like DSP, it is broadly used acronym to Digital Signal Processors.
> Would prefer to have DISPLAY or DISP.
The registers are called DSP<foo>, so the spec makes the case for DSP_.
The problem with DISP_/etc. is that the namespace then makes it a bit
hard to figure out what register the defines belong to.
>
> Anyways, DSP_ENABLE should have also have plane on it.
DSP==display plane. Any more would be redundant.
>
> Other than above and a minor typo reported in general looks good to me but it also broke build because it missed GVT renames.
Always happens to me :/
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 09/14] drm/i915: Clean up vlv/chv sprite plane registers
2022-01-14 16:34 ` Souza, Jose
@ 2022-01-18 1:11 ` Ville Syrjälä
0 siblings, 0 replies; 48+ messages in thread
From: Ville Syrjälä @ 2022-01-18 1:11 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Fri, Jan 14, 2022 at 04:34:14PM +0000, Souza, Jose wrote:
> On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> > @@ -7238,28 +7257,36 @@ enum {
> > #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
> > #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
> > #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
> > -#define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
> > -#define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
> > +#define SPCSC_OOFF_MASK REG_GENMASK(26, 16)
> > +#define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
>
> With REG_FIELD_PREP you don't need to do (x) & 0x7ff.
Actually we do. These are two's complemnt so if we pass in a wider
negative value we need to mask off a bunch of the the sign bits.
Yes, REG_FIELD_PREP() does that in the end but it also BUILD_BUG()s
if you pass in a constant value that exceeds the bitmask. And for
these registers we do pass in negative constants.
I'm not entirely sure how much magic we should have in these macros
tbh, vs. just forcing the caller to handle it. If we had readout for
these then the caller would anyway have take care to sign extend the
result. So by that argument maybe these macros shouldn't have anything
like this. Not sure.
I've also occasioanlly pondered about extending that BUILD_BUG_ON()
behaviour to do runtime checks as well, hidden behind a suitable
debug kconfig knob. But haven't actually written the patch for it.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 07/14] drm/i915: Clean up pre-skl primary plane registers
2022-01-18 0:55 ` Ville Syrjälä
@ 2022-01-18 13:40 ` Souza, Jose
2022-01-18 16:27 ` Ville Syrjälä
0 siblings, 1 reply; 48+ messages in thread
From: Souza, Jose @ 2022-01-18 13:40 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Tue, 2022-01-18 at 02:55 +0200, Ville Syrjälä wrote:
> On Wed, Jan 12, 2022 at 08:12:31PM +0000, Souza, Jose wrote:
> > On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> > > @@ -427,9 +427,9 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane,
> > > * program whatever is there.
> > > */
> > > intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
> > > - (crtc_y << 16) | crtc_x);
> > > + DSP_POS_Y(crtc_y) | DSP_POS_X(crtc_x));
> > > intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
> > > - ((crtc_h - 1) << 16) | (crtc_w - 1));
> > > + DSP_HEIGHT(crtc_h - 1) | DSP_POS_X(crtc_w - 1));
> >
> > DSP_HEIGHT(crtc_h - 1) | DSP_WIDTH(crtc_w - 1));
>
> Whoops. Thanks for cathcing that.
>
> <snip>
> > > +#define DSP_ENABLE REG_BIT(31)
> >
> > I really don't like DSP, it is broadly used acronym to Digital Signal Processors.
> > Would prefer to have DISPLAY or DISP.
>
> The registers are called DSP<foo>, so the spec makes the case for DSP_.
> The problem with DISP_/etc. is that the namespace then makes it a bit
> hard to figure out what register the defines belong to.
>
> >
> > Anyways, DSP_ENABLE should have also have plane on it.
>
> DSP==display plane. Any more would be redundant.
Damn, even worst, thought it was DiSPlay.
But if this is the BSpec name, go ahead with it.
>
> >
> > Other than above and a minor typo reported in general looks good to me but it also broke build because it missed GVT renames.
>
> Always happens to me :/
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 07/14] drm/i915: Clean up pre-skl primary plane registers
2022-01-18 13:40 ` Souza, Jose
@ 2022-01-18 16:27 ` Ville Syrjälä
0 siblings, 0 replies; 48+ messages in thread
From: Ville Syrjälä @ 2022-01-18 16:27 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Tue, Jan 18, 2022 at 01:40:41PM +0000, Souza, Jose wrote:
> On Tue, 2022-01-18 at 02:55 +0200, Ville Syrjälä wrote:
> > On Wed, Jan 12, 2022 at 08:12:31PM +0000, Souza, Jose wrote:
> > > On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> > > > @@ -427,9 +427,9 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane,
> > > > * program whatever is there.
> > > > */
> > > > intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
> > > > - (crtc_y << 16) | crtc_x);
> > > > + DSP_POS_Y(crtc_y) | DSP_POS_X(crtc_x));
> > > > intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
> > > > - ((crtc_h - 1) << 16) | (crtc_w - 1));
> > > > + DSP_HEIGHT(crtc_h - 1) | DSP_POS_X(crtc_w - 1));
> > >
> > > DSP_HEIGHT(crtc_h - 1) | DSP_WIDTH(crtc_w - 1));
> >
> > Whoops. Thanks for cathcing that.
> >
> > <snip>
> > > > +#define DSP_ENABLE REG_BIT(31)
> > >
> > > I really don't like DSP, it is broadly used acronym to Digital Signal Processors.
> > > Would prefer to have DISPLAY or DISP.
> >
> > The registers are called DSP<foo>, so the spec makes the case for DSP_.
> > The problem with DISP_/etc. is that the namespace then makes it a bit
> > hard to figure out what register the defines belong to.
> >
> > >
> > > Anyways, DSP_ENABLE should have also have plane on it.
> >
> > DSP==display plane. Any more would be redundant.
>
> Damn, even worst, thought it was DiSPlay.
Well I guess it might be that too. I think the old docs tend to use
"display A" vs. "display plane A" etc. interchangeably when talking
about planes.
> But if this is the BSpec name, go ahead with it.
I guess I could be convinced to use DISP_ just to raise a few less
eyebrows. Just a bit sad that the namespace won't match the register
name then. But I suppose we have that sort of thing going on in other
places too.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
end of thread, other threads:[~2022-01-18 16:27 UTC | newest]
Thread overview: 48+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-01 15:25 [Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup Ville Syrjala
2021-12-01 15:25 ` [Intel-gfx] [PATCH 01/14] drm/i915: Get rid of the 64bit PLANE_CC_VAL mmio Ville Syrjala
2021-12-01 17:13 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 02/14] drm/i915: Rename plane YUV order bits Ville Syrjala
2021-12-01 17:14 ` Souza, Jose
2021-12-02 11:53 ` Ville Syrjälä
2021-12-06 13:13 ` kernel test robot
2021-12-06 13:13 ` kernel test robot
2021-12-01 15:25 ` [Intel-gfx] [PATCH 03/14] drm/i915: Get rid of the "sizes are 0 based" stuff Ville Syrjala
2021-12-01 17:18 ` Souza, Jose
2021-12-02 11:56 ` Ville Syrjälä
2021-12-03 13:40 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 04/14] drm/i915: Sipmplify PLANE_STRIDE masking Ville Syrjala
2022-01-12 19:50 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 05/14] drm/i915: Rename PLANE_CUS_CTL Y plane bits Ville Syrjala
2021-12-01 17:17 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 06/14] drm/i915: Use REG_BIT() & co. for universal " Ville Syrjala
2021-12-01 17:26 ` Souza, Jose
2021-12-02 11:57 ` Ville Syrjälä
2022-01-12 19:52 ` Souza, Jose
2021-12-06 15:57 ` kernel test robot
2021-12-06 15:57 ` kernel test robot
2021-12-01 15:25 ` [Intel-gfx] [PATCH 07/14] drm/i915: Clean up pre-skl primary plane registers Ville Syrjala
2021-12-06 19:22 ` kernel test robot
2021-12-06 19:22 ` kernel test robot
2022-01-12 20:12 ` Souza, Jose
2022-01-18 0:55 ` Ville Syrjälä
2022-01-18 13:40 ` Souza, Jose
2022-01-18 16:27 ` Ville Syrjälä
2021-12-01 15:25 ` [Intel-gfx] [PATCH 08/14] drm/i915: Clean up ivb+ sprite " Ville Syrjala
2022-01-14 16:26 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 09/14] drm/i915: Clean up vlv/chv " Ville Syrjala
2022-01-14 16:34 ` Souza, Jose
2022-01-18 1:11 ` Ville Syrjälä
2021-12-01 15:25 ` [Intel-gfx] [PATCH 10/14] drm/i915: Clean up g4x+ " Ville Syrjala
2022-01-14 16:38 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 11/14] drm/i915: Clean up cursor registers Ville Syrjala
2022-01-14 16:45 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 12/14] drm/i915: Extract skl_plane_aux_dist() Ville Syrjala
2021-12-01 17:28 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 13/14] drm/i915: Declutter color key register stuff Ville Syrjala
2021-12-01 17:31 ` Souza, Jose
2021-12-01 15:25 ` [Intel-gfx] [PATCH 14/14] drm/i915: Nuke pointless middle men for skl+ plane programming Ville Syrjala
2021-12-01 17:32 ` Souza, Jose
2021-12-01 18:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanup Patchwork
2021-12-01 18:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-12-01 19:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-12-02 1:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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