[PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

This series implements a common reset framework driver for Tegra, and
updates all relevant Tegra drivers to use it. It also removes the custom
DMA bindings and replaced them with the standard DMA DT bindings.

Historically, the Tegra clock driver has exported a custom API for module
reset. This series removes that API, and transitions DT and drivers to
the new reset framework.

The custom API used a "struct clk" to identify which module to reset, and
consequently some DT bindings and drivers required clocks to be provided
where they really needed just a reset identifier instead. Due to this
known deficiency, I have always considered most Tegra bindings to be
unstable. This series removes this excuse for instability, although I
still consider some Tegra bindings unstable due to the need to convert to
the common DMA bindings.

Historically, Tegra DMA channels have been represented in DT using a
custom nvidia,dma-request-selector property. Now that standard DMA DT
bindings exist, convert all Tegra bindings, DTs, and drivers to use the
standard instead.

This series makes a DT-ABI-incompatible change to:
- Require reset specifiers in DT where relevant.
- Require standard DMA specifiers.
- Remove clock specifiers from DT where they were only needed for reset.
- Remove legacy DMA specifier properties.

I anticipate merging this whole series into the Tegra and arm-soc trees
as its own branch, due to internal dependencies. This branch will be
stable and can then be merged into any other subsystem trees should any
conflicts arise.

This series depends on Peter's Tegra clock driver rework, available at
git://nv-tegra.nvidia.com/user/pdeschrijver/linux tegra-clk-tegra124-0
(or whatever version of that gets included in 3.14)

Cc: ac100@lists.launchpad.net
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: alsa-devel@alsa-project.org
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: David Airlie <airlied@linux.ie>
Cc: devel@driverdev.osuosl.org
Cc: devicetree@vger.kernel.org
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Dmitry Torokhov <dtor@mail.ru>
Cc: dri-devel@lists.freedesktop.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Julian Andres Klode <jak@jak-linux.org>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-i2c@vger.kernel.org
Cc: linux-input@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-serial@vger.kernel.org
Cc: linux-spi@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: linux-usb@vger.kernel.org
Cc: Marc Dietrich <marvin24@gmx.de>
Cc: Mark Brown <broonie@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: pdeschrijver@nvidia.com
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Terje Bergström <tbergstrom@nvidia.com>
Cc: treding@nvidia.com
Cc: Wolfram Sang <wsa@the-dreams.de>

Stephen Warren (31):
  ARM: tegra: add missing clock documentation to DT bindings
  ARM: tegra: document reset properties in DT bindings
  ARM: tegra: document use of standard DMA DT bindings
  ARM: tegra: update DT files to add reset properties
  ARM: tegra: update DT files to add DMA properties
  ARM: tegra: select the reset framework
  clk: tegra: implement a reset driver
  pci: tegra: use reset framework
  drm/tegra: use reset framework
  ARM: tegra: pass reset to tegra_powergate_sequence_power_up()
  dma: add channel request API that supports deferred probe
  dma: tegra: use reset framework
  dma: tegra: register as an OF DMA controller
  ASoC: dmaengine: support deferred probe for DMA channels
  ASoC: dmaengine: add custom DMA config to snd_dmaengine_pcm_config
  ASoC: tegra: use reset framework
  ASoC: tegra: call pm_runtime APIs around register accesses
  ASoC: tegra: allocate AHUB FIFO during probe() not startup()
  ASoC: tegra: convert to standard DMA DT bindings
  i2c: tegra: use reset framework
  staging: nvec: use reset framework
  spi: tegra: use reset framework
  spi: tegra: convert to standard DMA DT bindings
  serial: tegra: use reset framework
  serial: tegra: convert to standard DMA DT bindings
  Input: tegra-kbc - use reset framework
  USB: EHCI: tegra: use reset framework
  ARM: tegra: remove legacy clock entries from DT
  ARM: tegra: remove legacy DMA entries from DT
  clk: tegra: remove legacy reset APIs
  clk: tegra: remove bogus PCIE_XCLK

 .../bindings/arm/tegra/nvidia,tegra20-pmc.txt      |   1 +
 .../bindings/clock/nvidia,tegra114-car.txt         |   4 +
 .../bindings/clock/nvidia,tegra124-car.txt         |   4 +
 .../bindings/clock/nvidia,tegra20-car.txt          |   4 +
 .../bindings/clock/nvidia,tegra30-car.txt          |   4 +
 .../devicetree/bindings/dma/tegra20-apbdma.txt     |   9 ++
 .../bindings/gpu/nvidia,tegra20-host1x.txt         | 124 +++++++++++++++
 .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt |  27 +++-
 .../bindings/input/nvidia,tegra20-kbc.txt          |   9 ++
 .../bindings/mmc/nvidia,tegra20-sdhci.txt          |   9 ++
 .../devicetree/bindings/nvec/nvidia,nvec.txt       |  12 ++
 .../bindings/pci/nvidia,tegra20-pcie.txt           |  28 ++--
 .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt |   9 ++
 .../devicetree/bindings/rtc/nvidia,tegra20-rtc.txt |   3 +
 .../bindings/serial/nvidia,tegra20-hsuart.txt      |  19 ++-
 .../bindings/sound/nvidia,tegra-audio-alc5632.txt  |   7 +-
 .../bindings/sound/nvidia,tegra-audio-rt5640.txt   |   7 +-
 .../bindings/sound/nvidia,tegra-audio-wm8753.txt   |   7 +-
 .../bindings/sound/nvidia,tegra-audio-wm8903.txt   |   7 +-
 .../bindings/sound/nvidia,tegra-audio-wm9712.txt   |   7 +-
 .../bindings/sound/nvidia,tegra20-ac97.txt         |  20 ++-
 .../bindings/sound/nvidia,tegra20-i2s.txt          |  19 ++-
 .../bindings/sound/nvidia,tegra30-ahub.txt         |  54 +++++--
 .../bindings/sound/nvidia,tegra30-i2s.txt          |  11 +-
 .../bindings/spi/nvidia,tegra114-spi.txt           |  24 ++-
 .../bindings/spi/nvidia,tegra20-sflash.txt         |  20 ++-
 .../bindings/spi/nvidia,tegra20-slink.txt          |  20 ++-
 .../bindings/timer/nvidia,tegra20-timer.txt        |   3 +
 .../bindings/timer/nvidia,tegra30-timer.txt        |   3 +
 .../bindings/usb/nvidia,tegra20-ehci.txt           |   7 +-
 arch/arm/boot/dts/tegra114.dtsi                    | 142 ++++++++++++++---
 arch/arm/boot/dts/tegra20-paz00.dts                |   2 +
 arch/arm/boot/dts/tegra20.dtsi                     | 132 ++++++++++++++--
 arch/arm/boot/dts/tegra30.dtsi                     | 171 +++++++++++++++++----
 arch/arm/mach-tegra/Kconfig                        |   2 +
 arch/arm/mach-tegra/powergate.c                    |   8 +-
 drivers/clk/tegra/clk-periph-gate.c                |  22 ---
 drivers/clk/tegra/clk-periph.c                     |  40 -----
 drivers/clk/tegra/clk-tegra114.c                   |   3 +-
 drivers/clk/tegra/clk-tegra124.c                   |   2 +-
 drivers/clk/tegra/clk-tegra20.c                    |   9 +-
 drivers/clk/tegra/clk-tegra30.c                    |  10 +-
 drivers/clk/tegra/clk.c                            |  55 ++++++-
 drivers/clk/tegra/clk.h                            |   3 +-
 drivers/dma/acpi-dma.c                             |  12 +-
 drivers/dma/dmaengine.c                            |  44 +++++-
 drivers/dma/of-dma.c                               |  12 +-
 drivers/dma/tegra20-apb-dma.c                      |  49 +++++-
 drivers/gpu/drm/tegra/Kconfig                      |   1 +
 drivers/gpu/drm/tegra/dc.c                         |   9 +-
 drivers/gpu/drm/tegra/drm.h                        |   3 +
 drivers/gpu/drm/tegra/gr3d.c                       |  22 ++-
 drivers/gpu/drm/tegra/hdmi.c                       |  14 +-
 drivers/i2c/busses/i2c-tegra.c                     |  13 +-
 drivers/input/keyboard/tegra-kbc.c                 |  13 +-
 drivers/pci/host/pci-tegra.c                       |  52 +++++--
 drivers/spi/Kconfig                                |   3 +
 drivers/spi/spi-tegra114.c                         |  66 ++++----
 drivers/spi/spi-tegra20-sflash.c                   |  18 ++-
 drivers/spi/spi-tegra20-slink.c                    |  66 ++++----
 drivers/staging/nvec/nvec.c                        |  11 +-
 drivers/staging/nvec/nvec.h                        |   5 +-
 drivers/tty/serial/serial-tegra.c                  |  86 +++++------
 drivers/usb/host/ehci-tegra.c                      |  14 +-
 include/dt-bindings/clock/tegra20-car.h            |   2 +-
 include/dt-bindings/clock/tegra30-car.h            |   2 +-
 include/linux/clk/tegra.h                          |   7 -
 include/linux/dmaengine.h                          |   7 +
 include/linux/of_dma.h                             |   9 +-
 include/linux/tegra-powergate.h                    |   4 +-
 include/sound/dmaengine_pcm.h                      |   6 +
 sound/soc/soc-generic-dmaengine-pcm.c              |  82 +++++++---
 sound/soc/tegra/Kconfig                            |   2 +
 sound/soc/tegra/tegra20_ac97.c                     |  11 --
 sound/soc/tegra/tegra20_i2s.c                      |  20 +--
 sound/soc/tegra/tegra30_ahub.c                     | 125 +++++++++------
 sound/soc/tegra/tegra30_ahub.h                     |  11 +-
 sound/soc/tegra/tegra30_i2s.c                      |  97 ++++++------
 sound/soc/tegra/tegra30_i2s.h                      |   3 +
 sound/soc/tegra/tegra_pcm.c                        |  17 +-
 sound/soc/tegra/tegra_pcm.h                        |   5 +
 81 files changed, 1448 insertions(+), 558 deletions(-)

-- 
1.8.1.5


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

This series implements a common reset framework driver for Tegra, and
updates all relevant Tegra drivers to use it. It also removes the custom
DMA bindings and replaced them with the standard DMA DT bindings.

Historically, the Tegra clock driver has exported a custom API for module
reset. This series removes that API, and transitions DT and drivers to
the new reset framework.

The custom API used a "struct clk" to identify which module to reset, and
consequently some DT bindings and drivers required clocks to be provided
where they really needed just a reset identifier instead. Due to this
known deficiency, I have always considered most Tegra bindings to be
unstable. This series removes this excuse for instability, although I
still consider some Tegra bindings unstable due to the need to convert to
the common DMA bindings.

Historically, Tegra DMA channels have been represented in DT using a
custom nvidia,dma-request-selector property. Now that standard DMA DT
bindings exist, convert all Tegra bindings, DTs, and drivers to use the
standard instead.

This series makes a DT-ABI-incompatible change to:
- Require reset specifiers in DT where relevant.
- Require standard DMA specifiers.
- Remove clock specifiers from DT where they were only needed for reset.
- Remove legacy DMA specifier properties.

I anticipate merging this whole series into the Tegra and arm-soc trees
as its own branch, due to internal dependencies. This branch will be
stable and can then be merged into any other subsystem trees should any
conflicts arise.

This series depends on Peter's Tegra clock driver rework, available at
git://nv-tegra.nvidia.com/user/pdeschrijver/linux tegra-clk-tegra124-0
(or whatever version of that gets included in 3.14)

Cc: ac100 at lists.launchpad.net
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: alsa-devel at alsa-project.org
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: David Airlie <airlied@linux.ie>
Cc: devel at driverdev.osuosl.org
Cc: devicetree at vger.kernel.org
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Dmitry Torokhov <dtor@mail.ru>
Cc: dri-devel at lists.freedesktop.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Julian Andres Klode <jak@jak-linux.org>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-i2c at vger.kernel.org
Cc: linux-input at vger.kernel.org
Cc: linux-pci at vger.kernel.org
Cc: linux-serial at vger.kernel.org
Cc: linux-spi at vger.kernel.org
Cc: linux-tegra at vger.kernel.org
Cc: linux-usb at vger.kernel.org
Cc: Marc Dietrich <marvin24@gmx.de>
Cc: Mark Brown <broonie@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: pdeschrijver at nvidia.com
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Terje Bergstr?m <tbergstrom@nvidia.com>
Cc: treding at nvidia.com
Cc: Wolfram Sang <wsa@the-dreams.de>

Stephen Warren (31):
  ARM: tegra: add missing clock documentation to DT bindings
  ARM: tegra: document reset properties in DT bindings
  ARM: tegra: document use of standard DMA DT bindings
  ARM: tegra: update DT files to add reset properties
  ARM: tegra: update DT files to add DMA properties
  ARM: tegra: select the reset framework
  clk: tegra: implement a reset driver
  pci: tegra: use reset framework
  drm/tegra: use reset framework
  ARM: tegra: pass reset to tegra_powergate_sequence_power_up()
  dma: add channel request API that supports deferred probe
  dma: tegra: use reset framework
  dma: tegra: register as an OF DMA controller
  ASoC: dmaengine: support deferred probe for DMA channels
  ASoC: dmaengine: add custom DMA config to snd_dmaengine_pcm_config
  ASoC: tegra: use reset framework
  ASoC: tegra: call pm_runtime APIs around register accesses
  ASoC: tegra: allocate AHUB FIFO during probe() not startup()
  ASoC: tegra: convert to standard DMA DT bindings
  i2c: tegra: use reset framework
  staging: nvec: use reset framework
  spi: tegra: use reset framework
  spi: tegra: convert to standard DMA DT bindings
  serial: tegra: use reset framework
  serial: tegra: convert to standard DMA DT bindings
  Input: tegra-kbc - use reset framework
  USB: EHCI: tegra: use reset framework
  ARM: tegra: remove legacy clock entries from DT
  ARM: tegra: remove legacy DMA entries from DT
  clk: tegra: remove legacy reset APIs
  clk: tegra: remove bogus PCIE_XCLK

 .../bindings/arm/tegra/nvidia,tegra20-pmc.txt      |   1 +
 .../bindings/clock/nvidia,tegra114-car.txt         |   4 +
 .../bindings/clock/nvidia,tegra124-car.txt         |   4 +
 .../bindings/clock/nvidia,tegra20-car.txt          |   4 +
 .../bindings/clock/nvidia,tegra30-car.txt          |   4 +
 .../devicetree/bindings/dma/tegra20-apbdma.txt     |   9 ++
 .../bindings/gpu/nvidia,tegra20-host1x.txt         | 124 +++++++++++++++
 .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt |  27 +++-
 .../bindings/input/nvidia,tegra20-kbc.txt          |   9 ++
 .../bindings/mmc/nvidia,tegra20-sdhci.txt          |   9 ++
 .../devicetree/bindings/nvec/nvidia,nvec.txt       |  12 ++
 .../bindings/pci/nvidia,tegra20-pcie.txt           |  28 ++--
 .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt |   9 ++
 .../devicetree/bindings/rtc/nvidia,tegra20-rtc.txt |   3 +
 .../bindings/serial/nvidia,tegra20-hsuart.txt      |  19 ++-
 .../bindings/sound/nvidia,tegra-audio-alc5632.txt  |   7 +-
 .../bindings/sound/nvidia,tegra-audio-rt5640.txt   |   7 +-
 .../bindings/sound/nvidia,tegra-audio-wm8753.txt   |   7 +-
 .../bindings/sound/nvidia,tegra-audio-wm8903.txt   |   7 +-
 .../bindings/sound/nvidia,tegra-audio-wm9712.txt   |   7 +-
 .../bindings/sound/nvidia,tegra20-ac97.txt         |  20 ++-
 .../bindings/sound/nvidia,tegra20-i2s.txt          |  19 ++-
 .../bindings/sound/nvidia,tegra30-ahub.txt         |  54 +++++--
 .../bindings/sound/nvidia,tegra30-i2s.txt          |  11 +-
 .../bindings/spi/nvidia,tegra114-spi.txt           |  24 ++-
 .../bindings/spi/nvidia,tegra20-sflash.txt         |  20 ++-
 .../bindings/spi/nvidia,tegra20-slink.txt          |  20 ++-
 .../bindings/timer/nvidia,tegra20-timer.txt        |   3 +
 .../bindings/timer/nvidia,tegra30-timer.txt        |   3 +
 .../bindings/usb/nvidia,tegra20-ehci.txt           |   7 +-
 arch/arm/boot/dts/tegra114.dtsi                    | 142 ++++++++++++++---
 arch/arm/boot/dts/tegra20-paz00.dts                |   2 +
 arch/arm/boot/dts/tegra20.dtsi                     | 132 ++++++++++++++--
 arch/arm/boot/dts/tegra30.dtsi                     | 171 +++++++++++++++++----
 arch/arm/mach-tegra/Kconfig                        |   2 +
 arch/arm/mach-tegra/powergate.c                    |   8 +-
 drivers/clk/tegra/clk-periph-gate.c                |  22 ---
 drivers/clk/tegra/clk-periph.c                     |  40 -----
 drivers/clk/tegra/clk-tegra114.c                   |   3 +-
 drivers/clk/tegra/clk-tegra124.c                   |   2 +-
 drivers/clk/tegra/clk-tegra20.c                    |   9 +-
 drivers/clk/tegra/clk-tegra30.c                    |  10 +-
 drivers/clk/tegra/clk.c                            |  55 ++++++-
 drivers/clk/tegra/clk.h                            |   3 +-
 drivers/dma/acpi-dma.c                             |  12 +-
 drivers/dma/dmaengine.c                            |  44 +++++-
 drivers/dma/of-dma.c                               |  12 +-
 drivers/dma/tegra20-apb-dma.c                      |  49 +++++-
 drivers/gpu/drm/tegra/Kconfig                      |   1 +
 drivers/gpu/drm/tegra/dc.c                         |   9 +-
 drivers/gpu/drm/tegra/drm.h                        |   3 +
 drivers/gpu/drm/tegra/gr3d.c                       |  22 ++-
 drivers/gpu/drm/tegra/hdmi.c                       |  14 +-
 drivers/i2c/busses/i2c-tegra.c                     |  13 +-
 drivers/input/keyboard/tegra-kbc.c                 |  13 +-
 drivers/pci/host/pci-tegra.c                       |  52 +++++--
 drivers/spi/Kconfig                                |   3 +
 drivers/spi/spi-tegra114.c                         |  66 ++++----
 drivers/spi/spi-tegra20-sflash.c                   |  18 ++-
 drivers/spi/spi-tegra20-slink.c                    |  66 ++++----
 drivers/staging/nvec/nvec.c                        |  11 +-
 drivers/staging/nvec/nvec.h                        |   5 +-
 drivers/tty/serial/serial-tegra.c                  |  86 +++++------
 drivers/usb/host/ehci-tegra.c                      |  14 +-
 include/dt-bindings/clock/tegra20-car.h            |   2 +-
 include/dt-bindings/clock/tegra30-car.h            |   2 +-
 include/linux/clk/tegra.h                          |   7 -
 include/linux/dmaengine.h                          |   7 +
 include/linux/of_dma.h                             |   9 +-
 include/linux/tegra-powergate.h                    |   4 +-
 include/sound/dmaengine_pcm.h                      |   6 +
 sound/soc/soc-generic-dmaengine-pcm.c              |  82 +++++++---
 sound/soc/tegra/Kconfig                            |   2 +
 sound/soc/tegra/tegra20_ac97.c                     |  11 --
 sound/soc/tegra/tegra20_i2s.c                      |  20 +--
 sound/soc/tegra/tegra30_ahub.c                     | 125 +++++++++------
 sound/soc/tegra/tegra30_ahub.h                     |  11 +-
 sound/soc/tegra/tegra30_i2s.c                      |  97 ++++++------
 sound/soc/tegra/tegra30_i2s.h                      |   3 +
 sound/soc/tegra/tegra_pcm.c                        |  17 +-
 sound/soc/tegra/tegra_pcm.h                        |   5 +
 81 files changed, 1448 insertions(+), 558 deletions(-)

-- 
1.8.1.5

[PATCH 08/31] pci: tegra: use reset framework

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

The old Tegra-specific API used a struct clock to represent the module
to reset. Some of the clocks retrieved during probe() were only used for
reset purposes, and indeed aren't even true clocks. So, there's no need
to get() them any more.

Cc: treding@nvidia.com
Cc: pdeschrijver@nvidia.com
Cc: linux-tegra@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/pci/host/pci-tegra.c | 49 ++++++++++++++++++++++++++++++++------------
 1 file changed, 36 insertions(+), 13 deletions(-)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 0afbbbc55c81..174a5bc2d993 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -39,6 +39,7 @@
 #include <linux/of_platform.h>
 #include <linux/pci.h>
 #include <linux/platform_device.h>
+#include <linux/reset.h>
 #include <linux/sizes.h>
 #include <linux/slab.h>
 #include <linux/tegra-cpuidle.h>
@@ -259,10 +260,13 @@ struct tegra_pcie {
 
 	struct clk *pex_clk;
 	struct clk *afi_clk;
-	struct clk *pcie_xclk;
 	struct clk *pll_e;
 	struct clk *cml_clk;
 
+	struct reset_control *pex_rst;
+	struct reset_control *afi_rst;
+	struct reset_control *pcie_xrst;
+
 	struct tegra_msi msi;
 
 	struct list_head ports;
@@ -858,7 +862,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
 	pads_writel(pcie, value, PADS_CTL);
 
 	/* take the PCIe interface module out of reset */
-	tegra_periph_reset_deassert(pcie->pcie_xclk);
+	reset_control_deassert(pcie->pcie_xrst);
 
 	/* finally enable PCIe */
 	value = afi_readl(pcie, AFI_CONFIGURATION);
@@ -891,9 +895,9 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie)
 
 	/* TODO: disable and unprepare clocks? */
 
-	tegra_periph_reset_assert(pcie->pcie_xclk);
-	tegra_periph_reset_assert(pcie->afi_clk);
-	tegra_periph_reset_assert(pcie->pex_clk);
+	reset_control_assert(pcie->pcie_xrst);
+	reset_control_assert(pcie->afi_rst);
+	reset_control_assert(pcie->pex_rst);
 
 	tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
 
@@ -921,9 +925,9 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
 	const struct tegra_pcie_soc_data *soc = pcie->soc_data;
 	int err;
 
-	tegra_periph_reset_assert(pcie->pcie_xclk);
-	tegra_periph_reset_assert(pcie->afi_clk);
-	tegra_periph_reset_assert(pcie->pex_clk);
+	reset_control_assert(pcie->pcie_xrst);
+	reset_control_assert(pcie->afi_rst);
+	reset_control_assert(pcie->pex_rst);
 
 	tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
 
@@ -958,7 +962,7 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
 		return err;
 	}
 
-	tegra_periph_reset_deassert(pcie->afi_clk);
+	reset_control_deassert(pcie->afi_rst);
 
 	err = clk_prepare_enable(pcie->afi_clk);
 	if (err < 0) {
@@ -996,10 +1000,6 @@ static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
 	if (IS_ERR(pcie->afi_clk))
 		return PTR_ERR(pcie->afi_clk);
 
-	pcie->pcie_xclk = devm_clk_get(pcie->dev, "pcie_xclk");
-	if (IS_ERR(pcie->pcie_xclk))
-		return PTR_ERR(pcie->pcie_xclk);
-
 	pcie->pll_e = devm_clk_get(pcie->dev, "pll_e");
 	if (IS_ERR(pcie->pll_e))
 		return PTR_ERR(pcie->pll_e);
@@ -1013,6 +1013,23 @@ static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
 	return 0;
 }
 
+static int tegra_pcie_resets_get(struct tegra_pcie *pcie)
+{
+	pcie->pex_rst = devm_reset_control_get(pcie->dev, "pex");
+	if (IS_ERR(pcie->pex_rst))
+		return PTR_ERR(pcie->pex_rst);
+
+	pcie->afi_rst = devm_reset_control_get(pcie->dev, "afi");
+	if (IS_ERR(pcie->afi_rst))
+		return PTR_ERR(pcie->afi_rst);
+
+	pcie->pcie_xrst = devm_reset_control_get(pcie->dev, "pcie_x");
+	if (IS_ERR(pcie->pcie_xrst))
+		return PTR_ERR(pcie->pcie_xrst);
+
+	return 0;
+}
+
 static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
 {
 	struct platform_device *pdev = to_platform_device(pcie->dev);
@@ -1025,6 +1042,12 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
 		return err;
 	}
 
+	err = tegra_pcie_resets_get(pcie);
+	if (err) {
+		dev_err(&pdev->dev, "failed to get resets: %d\n", err);
+		return err;
+	}
+
 	err = tegra_pcie_power_on(pcie);
 	if (err) {
 		dev_err(&pdev->dev, "failed to power up: %d\n", err);
-- 
1.8.1.5

[PATCH 08/31] pci: tegra: use reset framework

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

The old Tegra-specific API used a struct clock to represent the module
to reset. Some of the clocks retrieved during probe() were only used for
reset purposes, and indeed aren't even true clocks. So, there's no need
to get() them any more.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci at vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/pci/host/pci-tegra.c | 49 ++++++++++++++++++++++++++++++++------------
 1 file changed, 36 insertions(+), 13 deletions(-)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 0afbbbc55c81..174a5bc2d993 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -39,6 +39,7 @@
 #include <linux/of_platform.h>
 #include <linux/pci.h>
 #include <linux/platform_device.h>
+#include <linux/reset.h>
 #include <linux/sizes.h>
 #include <linux/slab.h>
 #include <linux/tegra-cpuidle.h>
@@ -259,10 +260,13 @@ struct tegra_pcie {
 
 	struct clk *pex_clk;
 	struct clk *afi_clk;
-	struct clk *pcie_xclk;
 	struct clk *pll_e;
 	struct clk *cml_clk;
 
+	struct reset_control *pex_rst;
+	struct reset_control *afi_rst;
+	struct reset_control *pcie_xrst;
+
 	struct tegra_msi msi;
 
 	struct list_head ports;
@@ -858,7 +862,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
 	pads_writel(pcie, value, PADS_CTL);
 
 	/* take the PCIe interface module out of reset */
-	tegra_periph_reset_deassert(pcie->pcie_xclk);
+	reset_control_deassert(pcie->pcie_xrst);
 
 	/* finally enable PCIe */
 	value = afi_readl(pcie, AFI_CONFIGURATION);
@@ -891,9 +895,9 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie)
 
 	/* TODO: disable and unprepare clocks? */
 
-	tegra_periph_reset_assert(pcie->pcie_xclk);
-	tegra_periph_reset_assert(pcie->afi_clk);
-	tegra_periph_reset_assert(pcie->pex_clk);
+	reset_control_assert(pcie->pcie_xrst);
+	reset_control_assert(pcie->afi_rst);
+	reset_control_assert(pcie->pex_rst);
 
 	tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
 
@@ -921,9 +925,9 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
 	const struct tegra_pcie_soc_data *soc = pcie->soc_data;
 	int err;
 
-	tegra_periph_reset_assert(pcie->pcie_xclk);
-	tegra_periph_reset_assert(pcie->afi_clk);
-	tegra_periph_reset_assert(pcie->pex_clk);
+	reset_control_assert(pcie->pcie_xrst);
+	reset_control_assert(pcie->afi_rst);
+	reset_control_assert(pcie->pex_rst);
 
 	tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
 
@@ -958,7 +962,7 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
 		return err;
 	}
 
-	tegra_periph_reset_deassert(pcie->afi_clk);
+	reset_control_deassert(pcie->afi_rst);
 
 	err = clk_prepare_enable(pcie->afi_clk);
 	if (err < 0) {
@@ -996,10 +1000,6 @@ static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
 	if (IS_ERR(pcie->afi_clk))
 		return PTR_ERR(pcie->afi_clk);
 
-	pcie->pcie_xclk = devm_clk_get(pcie->dev, "pcie_xclk");
-	if (IS_ERR(pcie->pcie_xclk))
-		return PTR_ERR(pcie->pcie_xclk);
-
 	pcie->pll_e = devm_clk_get(pcie->dev, "pll_e");
 	if (IS_ERR(pcie->pll_e))
 		return PTR_ERR(pcie->pll_e);
@@ -1013,6 +1013,23 @@ static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
 	return 0;
 }
 
+static int tegra_pcie_resets_get(struct tegra_pcie *pcie)
+{
+	pcie->pex_rst = devm_reset_control_get(pcie->dev, "pex");
+	if (IS_ERR(pcie->pex_rst))
+		return PTR_ERR(pcie->pex_rst);
+
+	pcie->afi_rst = devm_reset_control_get(pcie->dev, "afi");
+	if (IS_ERR(pcie->afi_rst))
+		return PTR_ERR(pcie->afi_rst);
+
+	pcie->pcie_xrst = devm_reset_control_get(pcie->dev, "pcie_x");
+	if (IS_ERR(pcie->pcie_xrst))
+		return PTR_ERR(pcie->pcie_xrst);
+
+	return 0;
+}
+
 static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
 {
 	struct platform_device *pdev = to_platform_device(pcie->dev);
@@ -1025,6 +1042,12 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
 		return err;
 	}
 
+	err = tegra_pcie_resets_get(pcie);
+	if (err) {
+		dev_err(&pdev->dev, "failed to get resets: %d\n", err);
+		return err;
+	}
+
 	err = tegra_pcie_power_on(pcie);
 	if (err) {
 		dev_err(&pdev->dev, "failed to power up: %d\n", err);
-- 
1.8.1.5

Re: [PATCH 08/31] pci: tegra: use reset framework

[Bjorn Helgaas]

On Fri, Nov 15, 2013 at 1:54 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
>
> The old Tegra-specific API used a struct clock to represent the module
> to reset. Some of the clocks retrieved during probe() were only used for
> reset purposes, and indeed aren't even true clocks. So, there's no need
> to get() them any more.
>
> Cc: treding@nvidia.com
> Cc: pdeschrijver@nvidia.com
> Cc: linux-tegra@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: linux-pci@vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>

Acked-by: Bjorn Helgaas <bhelgaas@google.com>

Feel free to merge this through whatever tree is appropriate.  If I
were applying this, I would be looking for an ack from Thierry in
addition to mine.

> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/pci/host/pci-tegra.c | 49 ++++++++++++++++++++++++++++++++------------
>  1 file changed, 36 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index 0afbbbc55c81..174a5bc2d993 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -39,6 +39,7 @@
>  #include <linux/of_platform.h>
>  #include <linux/pci.h>
>  #include <linux/platform_device.h>
> +#include <linux/reset.h>
>  #include <linux/sizes.h>
>  #include <linux/slab.h>
>  #include <linux/tegra-cpuidle.h>
> @@ -259,10 +260,13 @@ struct tegra_pcie {
>
>         struct clk *pex_clk;
>         struct clk *afi_clk;
> -       struct clk *pcie_xclk;
>         struct clk *pll_e;
>         struct clk *cml_clk;
>
> +       struct reset_control *pex_rst;
> +       struct reset_control *afi_rst;
> +       struct reset_control *pcie_xrst;
> +
>         struct tegra_msi msi;
>
>         struct list_head ports;
> @@ -858,7 +862,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
>         pads_writel(pcie, value, PADS_CTL);
>
>         /* take the PCIe interface module out of reset */
> -       tegra_periph_reset_deassert(pcie->pcie_xclk);
> +       reset_control_deassert(pcie->pcie_xrst);
>
>         /* finally enable PCIe */
>         value = afi_readl(pcie, AFI_CONFIGURATION);
> @@ -891,9 +895,9 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie)
>
>         /* TODO: disable and unprepare clocks? */
>
> -       tegra_periph_reset_assert(pcie->pcie_xclk);
> -       tegra_periph_reset_assert(pcie->afi_clk);
> -       tegra_periph_reset_assert(pcie->pex_clk);
> +       reset_control_assert(pcie->pcie_xrst);
> +       reset_control_assert(pcie->afi_rst);
> +       reset_control_assert(pcie->pex_rst);
>
>         tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
>
> @@ -921,9 +925,9 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
>         const struct tegra_pcie_soc_data *soc = pcie->soc_data;
>         int err;
>
> -       tegra_periph_reset_assert(pcie->pcie_xclk);
> -       tegra_periph_reset_assert(pcie->afi_clk);
> -       tegra_periph_reset_assert(pcie->pex_clk);
> +       reset_control_assert(pcie->pcie_xrst);
> +       reset_control_assert(pcie->afi_rst);
> +       reset_control_assert(pcie->pex_rst);
>
>         tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
>
> @@ -958,7 +962,7 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
>                 return err;
>         }
>
> -       tegra_periph_reset_deassert(pcie->afi_clk);
> +       reset_control_deassert(pcie->afi_rst);
>
>         err = clk_prepare_enable(pcie->afi_clk);
>         if (err < 0) {
> @@ -996,10 +1000,6 @@ static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
>         if (IS_ERR(pcie->afi_clk))
>                 return PTR_ERR(pcie->afi_clk);
>
> -       pcie->pcie_xclk = devm_clk_get(pcie->dev, "pcie_xclk");
> -       if (IS_ERR(pcie->pcie_xclk))
> -               return PTR_ERR(pcie->pcie_xclk);
> -
>         pcie->pll_e = devm_clk_get(pcie->dev, "pll_e");
>         if (IS_ERR(pcie->pll_e))
>                 return PTR_ERR(pcie->pll_e);
> @@ -1013,6 +1013,23 @@ static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
>         return 0;
>  }
>
> +static int tegra_pcie_resets_get(struct tegra_pcie *pcie)
> +{
> +       pcie->pex_rst = devm_reset_control_get(pcie->dev, "pex");
> +       if (IS_ERR(pcie->pex_rst))
> +               return PTR_ERR(pcie->pex_rst);
> +
> +       pcie->afi_rst = devm_reset_control_get(pcie->dev, "afi");
> +       if (IS_ERR(pcie->afi_rst))
> +               return PTR_ERR(pcie->afi_rst);
> +
> +       pcie->pcie_xrst = devm_reset_control_get(pcie->dev, "pcie_x");
> +       if (IS_ERR(pcie->pcie_xrst))
> +               return PTR_ERR(pcie->pcie_xrst);
> +
> +       return 0;
> +}
> +
>  static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
>  {
>         struct platform_device *pdev = to_platform_device(pcie->dev);
> @@ -1025,6 +1042,12 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
>                 return err;
>         }
>
> +       err = tegra_pcie_resets_get(pcie);
> +       if (err) {
> +               dev_err(&pdev->dev, "failed to get resets: %d\n", err);
> +               return err;
> +       }
> +
>         err = tegra_pcie_power_on(pcie);
>         if (err) {
>                 dev_err(&pdev->dev, "failed to power up: %d\n", err);
> --
> 1.8.1.5
>

[PATCH 08/31] pci: tegra: use reset framework

[Bjorn Helgaas]

On Fri, Nov 15, 2013 at 1:54 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
>
> The old Tegra-specific API used a struct clock to represent the module
> to reset. Some of the clocks retrieved during probe() were only used for
> reset purposes, and indeed aren't even true clocks. So, there's no need
> to get() them any more.
>
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: linux-pci at vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>

Acked-by: Bjorn Helgaas <bhelgaas@google.com>

Feel free to merge this through whatever tree is appropriate.  If I
were applying this, I would be looking for an ack from Thierry in
addition to mine.

> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/pci/host/pci-tegra.c | 49 ++++++++++++++++++++++++++++++++------------
>  1 file changed, 36 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index 0afbbbc55c81..174a5bc2d993 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -39,6 +39,7 @@
>  #include <linux/of_platform.h>
>  #include <linux/pci.h>
>  #include <linux/platform_device.h>
> +#include <linux/reset.h>
>  #include <linux/sizes.h>
>  #include <linux/slab.h>
>  #include <linux/tegra-cpuidle.h>
> @@ -259,10 +260,13 @@ struct tegra_pcie {
>
>         struct clk *pex_clk;
>         struct clk *afi_clk;
> -       struct clk *pcie_xclk;
>         struct clk *pll_e;
>         struct clk *cml_clk;
>
> +       struct reset_control *pex_rst;
> +       struct reset_control *afi_rst;
> +       struct reset_control *pcie_xrst;
> +
>         struct tegra_msi msi;
>
>         struct list_head ports;
> @@ -858,7 +862,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
>         pads_writel(pcie, value, PADS_CTL);
>
>         /* take the PCIe interface module out of reset */
> -       tegra_periph_reset_deassert(pcie->pcie_xclk);
> +       reset_control_deassert(pcie->pcie_xrst);
>
>         /* finally enable PCIe */
>         value = afi_readl(pcie, AFI_CONFIGURATION);
> @@ -891,9 +895,9 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie)
>
>         /* TODO: disable and unprepare clocks? */
>
> -       tegra_periph_reset_assert(pcie->pcie_xclk);
> -       tegra_periph_reset_assert(pcie->afi_clk);
> -       tegra_periph_reset_assert(pcie->pex_clk);
> +       reset_control_assert(pcie->pcie_xrst);
> +       reset_control_assert(pcie->afi_rst);
> +       reset_control_assert(pcie->pex_rst);
>
>         tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
>
> @@ -921,9 +925,9 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
>         const struct tegra_pcie_soc_data *soc = pcie->soc_data;
>         int err;
>
> -       tegra_periph_reset_assert(pcie->pcie_xclk);
> -       tegra_periph_reset_assert(pcie->afi_clk);
> -       tegra_periph_reset_assert(pcie->pex_clk);
> +       reset_control_assert(pcie->pcie_xrst);
> +       reset_control_assert(pcie->afi_rst);
> +       reset_control_assert(pcie->pex_rst);
>
>         tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
>
> @@ -958,7 +962,7 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
>                 return err;
>         }
>
> -       tegra_periph_reset_deassert(pcie->afi_clk);
> +       reset_control_deassert(pcie->afi_rst);
>
>         err = clk_prepare_enable(pcie->afi_clk);
>         if (err < 0) {
> @@ -996,10 +1000,6 @@ static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
>         if (IS_ERR(pcie->afi_clk))
>                 return PTR_ERR(pcie->afi_clk);
>
> -       pcie->pcie_xclk = devm_clk_get(pcie->dev, "pcie_xclk");
> -       if (IS_ERR(pcie->pcie_xclk))
> -               return PTR_ERR(pcie->pcie_xclk);
> -
>         pcie->pll_e = devm_clk_get(pcie->dev, "pll_e");
>         if (IS_ERR(pcie->pll_e))
>                 return PTR_ERR(pcie->pll_e);
> @@ -1013,6 +1013,23 @@ static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
>         return 0;
>  }
>
> +static int tegra_pcie_resets_get(struct tegra_pcie *pcie)
> +{
> +       pcie->pex_rst = devm_reset_control_get(pcie->dev, "pex");
> +       if (IS_ERR(pcie->pex_rst))
> +               return PTR_ERR(pcie->pex_rst);
> +
> +       pcie->afi_rst = devm_reset_control_get(pcie->dev, "afi");
> +       if (IS_ERR(pcie->afi_rst))
> +               return PTR_ERR(pcie->afi_rst);
> +
> +       pcie->pcie_xrst = devm_reset_control_get(pcie->dev, "pcie_x");
> +       if (IS_ERR(pcie->pcie_xrst))
> +               return PTR_ERR(pcie->pcie_xrst);
> +
> +       return 0;
> +}
> +
>  static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
>  {
>         struct platform_device *pdev = to_platform_device(pcie->dev);
> @@ -1025,6 +1042,12 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
>                 return err;
>         }
>
> +       err = tegra_pcie_resets_get(pcie);
> +       if (err) {
> +               dev_err(&pdev->dev, "failed to get resets: %d\n", err);
> +               return err;
> +       }
> +
>         err = tegra_pcie_power_on(pcie);
>         if (err) {
>                 dev_err(&pdev->dev, "failed to power up: %d\n", err);
> --
> 1.8.1.5
>

Re: [PATCH 08/31] pci: tegra: use reset framework

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 629 bytes --]

On Fri, Nov 15, 2013 at 01:54:03PM -0700, Stephen Warren wrote:
[...]
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index 0afbbbc55c81..174a5bc2d993 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -39,6 +39,7 @@
>  #include <linux/of_platform.h>
>  #include <linux/pci.h>
>  #include <linux/platform_device.h>
> +#include <linux/reset.h>

Can't you also remove the linux/clk/tegra.h include now that none of the
functions it declares are used anymore?

Otherwise looks good to me:

Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

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[PATCH 08/31] pci: tegra: use reset framework

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:54:03PM -0700, Stephen Warren wrote:
[...]
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index 0afbbbc55c81..174a5bc2d993 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -39,6 +39,7 @@
>  #include <linux/of_platform.h>
>  #include <linux/pci.h>
>  #include <linux/platform_device.h>
> +#include <linux/reset.h>

Can't you also remove the linux/clk/tegra.h include now that none of the
functions it declares are used anymore?

Otherwise looks good to me:

Reviewed-by: Thierry Reding <treding@nvidia.com>
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Re: [PATCH 08/31] pci: tegra: use reset framework

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 600 bytes --]

On Fri, Nov 15, 2013 at 01:54:03PM -0700, Stephen Warren wrote:
[...]
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index 0afbbbc55c81..174a5bc2d993 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -39,6 +39,7 @@
>  #include <linux/of_platform.h>
>  #include <linux/pci.h>
>  #include <linux/platform_device.h>
> +#include <linux/reset.h>

Can't you also remove the linux/clk/tegra.h include now that none of the
functions it declares are used anymore?

Otherwise looks good to me:

Reviewed-by: Thierry Reding <treding@nvidia.com>

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Re: [PATCH 08/31] pci: tegra: use reset framework

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 847 bytes --]

On Fri, Nov 29, 2013 at 02:29:58PM +0100, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:54:03PM -0700, Stephen Warren wrote:
> [...]
> > diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> > index 0afbbbc55c81..174a5bc2d993 100644
> > --- a/drivers/pci/host/pci-tegra.c
> > +++ b/drivers/pci/host/pci-tegra.c
> > @@ -39,6 +39,7 @@
> >  #include <linux/of_platform.h>
> >  #include <linux/pci.h>
> >  #include <linux/platform_device.h>
> > +#include <linux/reset.h>
> 
> Can't you also remove the linux/clk/tegra.h include now that none of the
> functions it declares are used anymore?
> 
> Otherwise looks good to me:
> 
> Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

And I guess also:

Acked-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

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[PATCH 08/31] pci: tegra: use reset framework

[Thierry Reding]

On Fri, Nov 29, 2013 at 02:29:58PM +0100, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:54:03PM -0700, Stephen Warren wrote:
> [...]
> > diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> > index 0afbbbc55c81..174a5bc2d993 100644
> > --- a/drivers/pci/host/pci-tegra.c
> > +++ b/drivers/pci/host/pci-tegra.c
> > @@ -39,6 +39,7 @@
> >  #include <linux/of_platform.h>
> >  #include <linux/pci.h>
> >  #include <linux/platform_device.h>
> > +#include <linux/reset.h>
> 
> Can't you also remove the linux/clk/tegra.h include now that none of the
> functions it declares are used anymore?
> 
> Otherwise looks good to me:
> 
> Reviewed-by: Thierry Reding <treding@nvidia.com>

And I guess also:

Acked-by: Thierry Reding <treding@nvidia.com>
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Re: [PATCH 08/31] pci: tegra: use reset framework

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 789 bytes --]

On Fri, Nov 29, 2013 at 02:29:58PM +0100, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:54:03PM -0700, Stephen Warren wrote:
> [...]
> > diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> > index 0afbbbc55c81..174a5bc2d993 100644
> > --- a/drivers/pci/host/pci-tegra.c
> > +++ b/drivers/pci/host/pci-tegra.c
> > @@ -39,6 +39,7 @@
> >  #include <linux/of_platform.h>
> >  #include <linux/pci.h>
> >  #include <linux/platform_device.h>
> > +#include <linux/reset.h>
> 
> Can't you also remove the linux/clk/tegra.h include now that none of the
> functions it declares are used anymore?
> 
> Otherwise looks good to me:
> 
> Reviewed-by: Thierry Reding <treding@nvidia.com>

And I guess also:

Acked-by: Thierry Reding <treding@nvidia.com>

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[PATCH 09/31] drm/tegra: use reset framework

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

Cc: treding@nvidia.com
Cc: pdeschrijver@nvidia.com
Cc: linux-tegra@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: Terje Bergström <tbergstrom@nvidia.com>
Cc: David Airlie <airlied@linux.ie>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/gpu/drm/tegra/Kconfig |  1 +
 drivers/gpu/drm/tegra/dc.c    |  9 ++++++++-
 drivers/gpu/drm/tegra/drm.h   |  3 +++
 drivers/gpu/drm/tegra/gr3d.c  | 16 ++++++++++++++++
 drivers/gpu/drm/tegra/hdmi.c  | 14 +++++++++++---
 5 files changed, 39 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/tegra/Kconfig b/drivers/gpu/drm/tegra/Kconfig
index 8961ba6a34b8..8db9b3bce001 100644
--- a/drivers/gpu/drm/tegra/Kconfig
+++ b/drivers/gpu/drm/tegra/Kconfig
@@ -2,6 +2,7 @@ config DRM_TEGRA
 	bool "NVIDIA Tegra DRM"
 	depends on ARCH_TEGRA || ARCH_MULTIPLATFORM
 	depends on DRM
+	depends on RESET_CONTROLLER
 	select TEGRA_HOST1X
 	select DRM_KMS_HELPER
 	select DRM_KMS_FB_HELPER
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index ae1cb31ead7e..c3be92879bea 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -10,6 +10,7 @@
 #include <linux/clk.h>
 #include <linux/clk/tegra.h>
 #include <linux/debugfs.h>
+#include <linux/reset.h>
 
 #include "dc.h"
 #include "drm.h"
@@ -712,7 +713,7 @@ static void tegra_crtc_prepare(struct drm_crtc *crtc)
 	unsigned long value;
 
 	/* hardware initialization */
-	tegra_periph_reset_deassert(dc->clk);
+	reset_control_deassert(dc->rst);
 	usleep_range(10000, 20000);
 
 	if (dc->pipe)
@@ -1187,6 +1188,12 @@ static int tegra_dc_probe(struct platform_device *pdev)
 		return PTR_ERR(dc->clk);
 	}
 
+	dc->rst = devm_reset_control_get(&pdev->dev, "dc");
+	if (IS_ERR(dc->rst)) {
+		dev_err(&pdev->dev, "failed to get reset\n");
+		return PTR_ERR(dc->rst);
+	}
+
 	err = clk_prepare_enable(dc->clk);
 	if (err < 0)
 		return err;
diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index fdfe259ed7f8..f717c18b28c2 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -19,6 +19,8 @@
 #include <drm/drm_fb_helper.h>
 #include <drm/drm_fixed.h>
 
+struct reset_control;
+
 struct tegra_fb {
 	struct drm_framebuffer base;
 	struct tegra_bo **planes;
@@ -93,6 +95,7 @@ struct tegra_dc {
 	int pipe;
 
 	struct clk *clk;
+	struct reset_control *rst;
 	void __iomem *regs;
 	int irq;
 
diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c
index 4cec8f526af7..f629e38b00e4 100644
--- a/drivers/gpu/drm/tegra/gr3d.c
+++ b/drivers/gpu/drm/tegra/gr3d.c
@@ -11,6 +11,7 @@
 #include <linux/host1x.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/reset.h>
 #include <linux/tegra-powergate.h>
 
 #include "drm.h"
@@ -22,6 +23,8 @@ struct gr3d {
 	struct host1x_channel *channel;
 	struct clk *clk_secondary;
 	struct clk *clk;
+	struct reset_control *rst_secondary;
+	struct reset_control *rst;
 
 	DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS);
 };
@@ -255,12 +258,25 @@ static int gr3d_probe(struct platform_device *pdev)
 		return PTR_ERR(gr3d->clk);
 	}
 
+	gr3d->rst = devm_reset_control_get(&pdev->dev, "3d");
+	if (IS_ERR(gr3d->rst)) {
+		dev_err(&pdev->dev, "cannot get reset\n");
+		return PTR_ERR(gr3d->rst);
+	}
+
 	if (of_device_is_compatible(np, "nvidia,tegra30-gr3d")) {
 		gr3d->clk_secondary = devm_clk_get(&pdev->dev, "3d2");
 		if (IS_ERR(gr3d->clk)) {
 			dev_err(&pdev->dev, "cannot get secondary clock\n");
 			return PTR_ERR(gr3d->clk);
 		}
+
+		gr3d->rst_secondary = devm_reset_control_get(&pdev->dev,
+								"3d2");
+		if (IS_ERR(gr3d->rst_secondary)) {
+			dev_err(&pdev->dev, "cannot get secondary reset\n");
+			return PTR_ERR(gr3d->rst_secondary);
+		}
 	}
 
 	err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk);
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index 0cd9bc2056e8..f3aad49633d6 100644
--- a/drivers/gpu/drm/tegra/hdmi.c
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -12,6 +12,7 @@
 #include <linux/debugfs.h>
 #include <linux/hdmi.h>
 #include <linux/regulator/consumer.h>
+#include <linux/reset.h>
 
 #include "hdmi.h"
 #include "drm.h"
@@ -49,6 +50,7 @@ struct tegra_hdmi {
 
 	struct clk *clk_parent;
 	struct clk *clk;
+	struct reset_control *rst;
 
 	const struct tegra_hdmi_config *config;
 
@@ -731,9 +733,9 @@ static int tegra_output_hdmi_enable(struct tegra_output *output)
 		return err;
 	}
 
-	tegra_periph_reset_assert(hdmi->clk);
+	reset_control_assert(hdmi->rst);
 	usleep_range(1000, 2000);
-	tegra_periph_reset_deassert(hdmi->clk);
+	reset_control_deassert(hdmi->rst);
 
 	tegra_dc_writel(dc, VSYNC_H_POSITION(1),
 			DC_DISP_DISP_TIMING_OPTIONS);
@@ -912,7 +914,7 @@ static int tegra_output_hdmi_disable(struct tegra_output *output)
 {
 	struct tegra_hdmi *hdmi = to_hdmi(output);
 
-	tegra_periph_reset_assert(hdmi->clk);
+	reset_control_assert(hdmi->rst);
 	clk_disable(hdmi->clk);
 	regulator_disable(hdmi->pll);
 
@@ -1338,6 +1340,12 @@ static int tegra_hdmi_probe(struct platform_device *pdev)
 		return PTR_ERR(hdmi->clk);
 	}
 
+	hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
+	if (IS_ERR(hdmi->rst)) {
+		dev_err(&pdev->dev, "failed to get reset\n");
+		return PTR_ERR(hdmi->rst);
+	}
+
 	err = clk_prepare(hdmi->clk);
 	if (err < 0)
 		return err;
-- 
1.8.1.5

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH 09/31] drm/tegra: use reset framework

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Terje Bergstr?m <tbergstrom@nvidia.com>
Cc: David Airlie <airlied@linux.ie>
Cc: dri-devel at lists.freedesktop.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/gpu/drm/tegra/Kconfig |  1 +
 drivers/gpu/drm/tegra/dc.c    |  9 ++++++++-
 drivers/gpu/drm/tegra/drm.h   |  3 +++
 drivers/gpu/drm/tegra/gr3d.c  | 16 ++++++++++++++++
 drivers/gpu/drm/tegra/hdmi.c  | 14 +++++++++++---
 5 files changed, 39 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/tegra/Kconfig b/drivers/gpu/drm/tegra/Kconfig
index 8961ba6a34b8..8db9b3bce001 100644
--- a/drivers/gpu/drm/tegra/Kconfig
+++ b/drivers/gpu/drm/tegra/Kconfig
@@ -2,6 +2,7 @@ config DRM_TEGRA
 	bool "NVIDIA Tegra DRM"
 	depends on ARCH_TEGRA || ARCH_MULTIPLATFORM
 	depends on DRM
+	depends on RESET_CONTROLLER
 	select TEGRA_HOST1X
 	select DRM_KMS_HELPER
 	select DRM_KMS_FB_HELPER
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index ae1cb31ead7e..c3be92879bea 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -10,6 +10,7 @@
 #include <linux/clk.h>
 #include <linux/clk/tegra.h>
 #include <linux/debugfs.h>
+#include <linux/reset.h>
 
 #include "dc.h"
 #include "drm.h"
@@ -712,7 +713,7 @@ static void tegra_crtc_prepare(struct drm_crtc *crtc)
 	unsigned long value;
 
 	/* hardware initialization */
-	tegra_periph_reset_deassert(dc->clk);
+	reset_control_deassert(dc->rst);
 	usleep_range(10000, 20000);
 
 	if (dc->pipe)
@@ -1187,6 +1188,12 @@ static int tegra_dc_probe(struct platform_device *pdev)
 		return PTR_ERR(dc->clk);
 	}
 
+	dc->rst = devm_reset_control_get(&pdev->dev, "dc");
+	if (IS_ERR(dc->rst)) {
+		dev_err(&pdev->dev, "failed to get reset\n");
+		return PTR_ERR(dc->rst);
+	}
+
 	err = clk_prepare_enable(dc->clk);
 	if (err < 0)
 		return err;
diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index fdfe259ed7f8..f717c18b28c2 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -19,6 +19,8 @@
 #include <drm/drm_fb_helper.h>
 #include <drm/drm_fixed.h>
 
+struct reset_control;
+
 struct tegra_fb {
 	struct drm_framebuffer base;
 	struct tegra_bo **planes;
@@ -93,6 +95,7 @@ struct tegra_dc {
 	int pipe;
 
 	struct clk *clk;
+	struct reset_control *rst;
 	void __iomem *regs;
 	int irq;
 
diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c
index 4cec8f526af7..f629e38b00e4 100644
--- a/drivers/gpu/drm/tegra/gr3d.c
+++ b/drivers/gpu/drm/tegra/gr3d.c
@@ -11,6 +11,7 @@
 #include <linux/host1x.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/reset.h>
 #include <linux/tegra-powergate.h>
 
 #include "drm.h"
@@ -22,6 +23,8 @@ struct gr3d {
 	struct host1x_channel *channel;
 	struct clk *clk_secondary;
 	struct clk *clk;
+	struct reset_control *rst_secondary;
+	struct reset_control *rst;
 
 	DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS);
 };
@@ -255,12 +258,25 @@ static int gr3d_probe(struct platform_device *pdev)
 		return PTR_ERR(gr3d->clk);
 	}
 
+	gr3d->rst = devm_reset_control_get(&pdev->dev, "3d");
+	if (IS_ERR(gr3d->rst)) {
+		dev_err(&pdev->dev, "cannot get reset\n");
+		return PTR_ERR(gr3d->rst);
+	}
+
 	if (of_device_is_compatible(np, "nvidia,tegra30-gr3d")) {
 		gr3d->clk_secondary = devm_clk_get(&pdev->dev, "3d2");
 		if (IS_ERR(gr3d->clk)) {
 			dev_err(&pdev->dev, "cannot get secondary clock\n");
 			return PTR_ERR(gr3d->clk);
 		}
+
+		gr3d->rst_secondary = devm_reset_control_get(&pdev->dev,
+								"3d2");
+		if (IS_ERR(gr3d->rst_secondary)) {
+			dev_err(&pdev->dev, "cannot get secondary reset\n");
+			return PTR_ERR(gr3d->rst_secondary);
+		}
 	}
 
 	err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk);
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index 0cd9bc2056e8..f3aad49633d6 100644
--- a/drivers/gpu/drm/tegra/hdmi.c
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -12,6 +12,7 @@
 #include <linux/debugfs.h>
 #include <linux/hdmi.h>
 #include <linux/regulator/consumer.h>
+#include <linux/reset.h>
 
 #include "hdmi.h"
 #include "drm.h"
@@ -49,6 +50,7 @@ struct tegra_hdmi {
 
 	struct clk *clk_parent;
 	struct clk *clk;
+	struct reset_control *rst;
 
 	const struct tegra_hdmi_config *config;
 
@@ -731,9 +733,9 @@ static int tegra_output_hdmi_enable(struct tegra_output *output)
 		return err;
 	}
 
-	tegra_periph_reset_assert(hdmi->clk);
+	reset_control_assert(hdmi->rst);
 	usleep_range(1000, 2000);
-	tegra_periph_reset_deassert(hdmi->clk);
+	reset_control_deassert(hdmi->rst);
 
 	tegra_dc_writel(dc, VSYNC_H_POSITION(1),
 			DC_DISP_DISP_TIMING_OPTIONS);
@@ -912,7 +914,7 @@ static int tegra_output_hdmi_disable(struct tegra_output *output)
 {
 	struct tegra_hdmi *hdmi = to_hdmi(output);
 
-	tegra_periph_reset_assert(hdmi->clk);
+	reset_control_assert(hdmi->rst);
 	clk_disable(hdmi->clk);
 	regulator_disable(hdmi->pll);
 
@@ -1338,6 +1340,12 @@ static int tegra_hdmi_probe(struct platform_device *pdev)
 		return PTR_ERR(hdmi->clk);
 	}
 
+	hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
+	if (IS_ERR(hdmi->rst)) {
+		dev_err(&pdev->dev, "failed to get reset\n");
+		return PTR_ERR(hdmi->rst);
+	}
+
 	err = clk_prepare(hdmi->clk);
 	if (err < 0)
 		return err;
-- 
1.8.1.5

Re: [PATCH 09/31] drm/tegra: use reset framework

[Thierry Reding]

[-- Attachment #1.1: Type: text/plain, Size: 3482 bytes --]

On Fri, Nov 15, 2013 at 01:54:04PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding@nvidia.com
> Cc: pdeschrijver@nvidia.com
> Cc: linux-tegra@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: Terje Bergström <tbergstrom@nvidia.com>
> Cc: David Airlie <airlied@linux.ie>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/gpu/drm/tegra/Kconfig |  1 +
>  drivers/gpu/drm/tegra/dc.c    |  9 ++++++++-
>  drivers/gpu/drm/tegra/drm.h   |  3 +++
>  drivers/gpu/drm/tegra/gr3d.c  | 16 ++++++++++++++++
>  drivers/gpu/drm/tegra/hdmi.c  | 14 +++++++++++---
>  5 files changed, 39 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/tegra/Kconfig b/drivers/gpu/drm/tegra/Kconfig
> index 8961ba6a34b8..8db9b3bce001 100644
> --- a/drivers/gpu/drm/tegra/Kconfig
> +++ b/drivers/gpu/drm/tegra/Kconfig
> @@ -2,6 +2,7 @@ config DRM_TEGRA
>  	bool "NVIDIA Tegra DRM"
>  	depends on ARCH_TEGRA || ARCH_MULTIPLATFORM
>  	depends on DRM
> +	depends on RESET_CONTROLLER

Is this really needed? ARCH_TEGRA already selects RESET_CONTROLLER and
we depend on ARCH_TEGRA. Or perhaps you need this because it might also
be that ARCH_MULTIPLATFORM is selected without ARCH_TEGRA support? In
either case I guess a good thing would be to add dummies for the reset
API so that we don't have this additional compile-time dependency.

>  	select TEGRA_HOST1X
>  	select DRM_KMS_HELPER
>  	select DRM_KMS_FB_HELPER
> diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
> index ae1cb31ead7e..c3be92879bea 100644
> --- a/drivers/gpu/drm/tegra/dc.c
> +++ b/drivers/gpu/drm/tegra/dc.c
> @@ -10,6 +10,7 @@
>  #include <linux/clk.h>
>  #include <linux/clk/tegra.h>
>  #include <linux/debugfs.h>
> +#include <linux/reset.h>

You should be able to drop linux/clk/tegra.h now.

> diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c
> index 4cec8f526af7..f629e38b00e4 100644
> --- a/drivers/gpu/drm/tegra/gr3d.c
> +++ b/drivers/gpu/drm/tegra/gr3d.c
> @@ -11,6 +11,7 @@
>  #include <linux/host1x.h>
>  #include <linux/module.h>
>  #include <linux/platform_device.h>
> +#include <linux/reset.h>

I was going to say "Same here", but interestingly this driver doesn't
use the old Tegra-specific reset API. It's actually handled internally
by the tegra_powergate_sequence_power_up() function and I think that'll
be handled by a separate patch in your series if I recall correctly.

> diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
> index 0cd9bc2056e8..f3aad49633d6 100644
> --- a/drivers/gpu/drm/tegra/hdmi.c
> +++ b/drivers/gpu/drm/tegra/hdmi.c
> @@ -12,6 +12,7 @@
>  #include <linux/debugfs.h>
>  #include <linux/hdmi.h>
>  #include <linux/regulator/consumer.h>
> +#include <linux/reset.h>

But here the linux/clk/tegra.h include can again be dropped.

Thierry

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[PATCH 09/31] drm/tegra: use reset framework

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:54:04PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Terje Bergstr?m <tbergstrom@nvidia.com>
> Cc: David Airlie <airlied@linux.ie>
> Cc: dri-devel at lists.freedesktop.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/gpu/drm/tegra/Kconfig |  1 +
>  drivers/gpu/drm/tegra/dc.c    |  9 ++++++++-
>  drivers/gpu/drm/tegra/drm.h   |  3 +++
>  drivers/gpu/drm/tegra/gr3d.c  | 16 ++++++++++++++++
>  drivers/gpu/drm/tegra/hdmi.c  | 14 +++++++++++---
>  5 files changed, 39 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/tegra/Kconfig b/drivers/gpu/drm/tegra/Kconfig
> index 8961ba6a34b8..8db9b3bce001 100644
> --- a/drivers/gpu/drm/tegra/Kconfig
> +++ b/drivers/gpu/drm/tegra/Kconfig
> @@ -2,6 +2,7 @@ config DRM_TEGRA
>  	bool "NVIDIA Tegra DRM"
>  	depends on ARCH_TEGRA || ARCH_MULTIPLATFORM
>  	depends on DRM
> +	depends on RESET_CONTROLLER

Is this really needed? ARCH_TEGRA already selects RESET_CONTROLLER and
we depend on ARCH_TEGRA. Or perhaps you need this because it might also
be that ARCH_MULTIPLATFORM is selected without ARCH_TEGRA support? In
either case I guess a good thing would be to add dummies for the reset
API so that we don't have this additional compile-time dependency.

>  	select TEGRA_HOST1X
>  	select DRM_KMS_HELPER
>  	select DRM_KMS_FB_HELPER
> diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
> index ae1cb31ead7e..c3be92879bea 100644
> --- a/drivers/gpu/drm/tegra/dc.c
> +++ b/drivers/gpu/drm/tegra/dc.c
> @@ -10,6 +10,7 @@
>  #include <linux/clk.h>
>  #include <linux/clk/tegra.h>
>  #include <linux/debugfs.h>
> +#include <linux/reset.h>

You should be able to drop linux/clk/tegra.h now.

> diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c
> index 4cec8f526af7..f629e38b00e4 100644
> --- a/drivers/gpu/drm/tegra/gr3d.c
> +++ b/drivers/gpu/drm/tegra/gr3d.c
> @@ -11,6 +11,7 @@
>  #include <linux/host1x.h>
>  #include <linux/module.h>
>  #include <linux/platform_device.h>
> +#include <linux/reset.h>

I was going to say "Same here", but interestingly this driver doesn't
use the old Tegra-specific reset API. It's actually handled internally
by the tegra_powergate_sequence_power_up() function and I think that'll
be handled by a separate patch in your series if I recall correctly.

> diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
> index 0cd9bc2056e8..f3aad49633d6 100644
> --- a/drivers/gpu/drm/tegra/hdmi.c
> +++ b/drivers/gpu/drm/tegra/hdmi.c
> @@ -12,6 +12,7 @@
>  #include <linux/debugfs.h>
>  #include <linux/hdmi.h>
>  #include <linux/regulator/consumer.h>
> +#include <linux/reset.h>

But here the linux/clk/tegra.h include can again be dropped.

Thierry
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[PATCH 10/31] ARM: tegra: pass reset to tegra_powergate_sequence_power_up()

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

Cc: treding@nvidia.com
Cc: pdeschrijver@nvidia.com
Cc: linux-tegra@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org
Cc: Terje Bergström <tbergstrom@nvidia.com>
Cc: David Airlie <airlied@linux.ie>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 arch/arm/mach-tegra/powergate.c | 8 +++++---
 drivers/gpu/drm/tegra/gr3d.c    | 6 ++++--
 drivers/pci/host/pci-tegra.c    | 3 ++-
 include/linux/tegra-powergate.h | 4 +++-
 4 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 85d28e756bb7..f6f5b54ff95e 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -25,6 +25,7 @@
 #include <linux/export.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/reset.h>
 #include <linux/seq_file.h>
 #include <linux/spinlock.h>
 #include <linux/clk/tegra.h>
@@ -144,11 +145,12 @@ int tegra_powergate_remove_clamping(int id)
 }
 
 /* Must be called with clk disabled, and returns with clk enabled */
-int tegra_powergate_sequence_power_up(int id, struct clk *clk)
+int tegra_powergate_sequence_power_up(int id, struct clk *clk,
+					struct reset_control *rst)
 {
 	int ret;
 
-	tegra_periph_reset_assert(clk);
+	reset_control_assert(rst);
 
 	ret = tegra_powergate_power_on(id);
 	if (ret)
@@ -165,7 +167,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
 		goto err_clamp;
 
 	udelay(10);
-	tegra_periph_reset_deassert(clk);
+	reset_control_deassert(rst);
 
 	return 0;
 
diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c
index f629e38b00e4..0cbb24b1ae04 100644
--- a/drivers/gpu/drm/tegra/gr3d.c
+++ b/drivers/gpu/drm/tegra/gr3d.c
@@ -279,7 +279,8 @@ static int gr3d_probe(struct platform_device *pdev)
 		}
 	}
 
-	err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk);
+	err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk,
+						gr3d->rst);
 	if (err < 0) {
 		dev_err(&pdev->dev, "failed to power up 3D unit\n");
 		return err;
@@ -287,7 +288,8 @@ static int gr3d_probe(struct platform_device *pdev)
 
 	if (gr3d->clk_secondary) {
 		err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D1,
-							gr3d->clk_secondary);
+							gr3d->clk_secondary,
+							gr3d->rst_secondary);
 		if (err < 0) {
 			dev_err(&pdev->dev,
 				"failed to power up secondary 3D unit\n");
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 174a5bc2d993..aace19edc469 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -956,7 +956,8 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
 	}
 
 	err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
-						pcie->pex_clk);
+						pcie->pex_clk,
+						pcie->pex_rst);
 	if (err) {
 		dev_err(pcie->dev, "powerup sequence failed: %d\n", err);
 		return err;
diff --git a/include/linux/tegra-powergate.h b/include/linux/tegra-powergate.h
index c98cfa406952..b5ad64aca071 100644
--- a/include/linux/tegra-powergate.h
+++ b/include/linux/tegra-powergate.h
@@ -19,6 +19,7 @@
 #define _MACH_TEGRA_POWERGATE_H_
 
 struct clk;
+struct reset_control;
 
 #define TEGRA_POWERGATE_CPU	0
 #define TEGRA_POWERGATE_3D	1
@@ -51,6 +52,7 @@ int tegra_powergate_power_off(int id);
 int tegra_powergate_remove_clamping(int id);
 
 /* Must be called with clk disabled, and returns with clk enabled */
-int tegra_powergate_sequence_power_up(int id, struct clk *clk);
+int tegra_powergate_sequence_power_up(int id, struct clk *clk,
+					struct reset_control *rst);
 
 #endif /* _MACH_TEGRA_POWERGATE_H_ */
-- 
1.8.1.5

[PATCH 10/31] ARM: tegra: pass reset to tegra_powergate_sequence_power_up()

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci at vger.kernel.org
Cc: Terje Bergstr?m <tbergstrom@nvidia.com>
Cc: David Airlie <airlied@linux.ie>
Cc: dri-devel at lists.freedesktop.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 arch/arm/mach-tegra/powergate.c | 8 +++++---
 drivers/gpu/drm/tegra/gr3d.c    | 6 ++++--
 drivers/pci/host/pci-tegra.c    | 3 ++-
 include/linux/tegra-powergate.h | 4 +++-
 4 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 85d28e756bb7..f6f5b54ff95e 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -25,6 +25,7 @@
 #include <linux/export.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/reset.h>
 #include <linux/seq_file.h>
 #include <linux/spinlock.h>
 #include <linux/clk/tegra.h>
@@ -144,11 +145,12 @@ int tegra_powergate_remove_clamping(int id)
 }
 
 /* Must be called with clk disabled, and returns with clk enabled */
-int tegra_powergate_sequence_power_up(int id, struct clk *clk)
+int tegra_powergate_sequence_power_up(int id, struct clk *clk,
+					struct reset_control *rst)
 {
 	int ret;
 
-	tegra_periph_reset_assert(clk);
+	reset_control_assert(rst);
 
 	ret = tegra_powergate_power_on(id);
 	if (ret)
@@ -165,7 +167,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
 		goto err_clamp;
 
 	udelay(10);
-	tegra_periph_reset_deassert(clk);
+	reset_control_deassert(rst);
 
 	return 0;
 
diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c
index f629e38b00e4..0cbb24b1ae04 100644
--- a/drivers/gpu/drm/tegra/gr3d.c
+++ b/drivers/gpu/drm/tegra/gr3d.c
@@ -279,7 +279,8 @@ static int gr3d_probe(struct platform_device *pdev)
 		}
 	}
 
-	err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk);
+	err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk,
+						gr3d->rst);
 	if (err < 0) {
 		dev_err(&pdev->dev, "failed to power up 3D unit\n");
 		return err;
@@ -287,7 +288,8 @@ static int gr3d_probe(struct platform_device *pdev)
 
 	if (gr3d->clk_secondary) {
 		err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D1,
-							gr3d->clk_secondary);
+							gr3d->clk_secondary,
+							gr3d->rst_secondary);
 		if (err < 0) {
 			dev_err(&pdev->dev,
 				"failed to power up secondary 3D unit\n");
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 174a5bc2d993..aace19edc469 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -956,7 +956,8 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
 	}
 
 	err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
-						pcie->pex_clk);
+						pcie->pex_clk,
+						pcie->pex_rst);
 	if (err) {
 		dev_err(pcie->dev, "powerup sequence failed: %d\n", err);
 		return err;
diff --git a/include/linux/tegra-powergate.h b/include/linux/tegra-powergate.h
index c98cfa406952..b5ad64aca071 100644
--- a/include/linux/tegra-powergate.h
+++ b/include/linux/tegra-powergate.h
@@ -19,6 +19,7 @@
 #define _MACH_TEGRA_POWERGATE_H_
 
 struct clk;
+struct reset_control;
 
 #define TEGRA_POWERGATE_CPU	0
 #define TEGRA_POWERGATE_3D	1
@@ -51,6 +52,7 @@ int tegra_powergate_power_off(int id);
 int tegra_powergate_remove_clamping(int id);
 
 /* Must be called with clk disabled, and returns with clk enabled */
-int tegra_powergate_sequence_power_up(int id, struct clk *clk);
+int tegra_powergate_sequence_power_up(int id, struct clk *clk,
+					struct reset_control *rst);
 
 #endif /* _MACH_TEGRA_POWERGATE_H_ */
-- 
1.8.1.5

Re: [PATCH 10/31] ARM: tegra: pass reset to tegra_powergate_sequence_power_up()

[Bjorn Helgaas]

On Fri, Nov 15, 2013 at 1:54 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
>
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
> Cc: linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: Terje Bergström <tbergstrom-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> Cc: David Airlie <airlied-cv59FeDIM0c@public.gmane.org>
> Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Acked-by: Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>

> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  arch/arm/mach-tegra/powergate.c | 8 +++++---
>  drivers/gpu/drm/tegra/gr3d.c    | 6 ++++--
>  drivers/pci/host/pci-tegra.c    | 3 ++-
>  include/linux/tegra-powergate.h | 4 +++-
>  4 files changed, 14 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
> index 85d28e756bb7..f6f5b54ff95e 100644
> --- a/arch/arm/mach-tegra/powergate.c
> +++ b/arch/arm/mach-tegra/powergate.c
> @@ -25,6 +25,7 @@
>  #include <linux/export.h>
>  #include <linux/init.h>
>  #include <linux/io.h>
> +#include <linux/reset.h>
>  #include <linux/seq_file.h>
>  #include <linux/spinlock.h>
>  #include <linux/clk/tegra.h>
> @@ -144,11 +145,12 @@ int tegra_powergate_remove_clamping(int id)
>  }
>
>  /* Must be called with clk disabled, and returns with clk enabled */
> -int tegra_powergate_sequence_power_up(int id, struct clk *clk)
> +int tegra_powergate_sequence_power_up(int id, struct clk *clk,
> +                                       struct reset_control *rst)
>  {
>         int ret;
>
> -       tegra_periph_reset_assert(clk);
> +       reset_control_assert(rst);
>
>         ret = tegra_powergate_power_on(id);
>         if (ret)
> @@ -165,7 +167,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
>                 goto err_clamp;
>
>         udelay(10);
> -       tegra_periph_reset_deassert(clk);
> +       reset_control_deassert(rst);
>
>         return 0;
>
> diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c
> index f629e38b00e4..0cbb24b1ae04 100644
> --- a/drivers/gpu/drm/tegra/gr3d.c
> +++ b/drivers/gpu/drm/tegra/gr3d.c
> @@ -279,7 +279,8 @@ static int gr3d_probe(struct platform_device *pdev)
>                 }
>         }
>
> -       err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk);
> +       err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk,
> +                                               gr3d->rst);
>         if (err < 0) {
>                 dev_err(&pdev->dev, "failed to power up 3D unit\n");
>                 return err;
> @@ -287,7 +288,8 @@ static int gr3d_probe(struct platform_device *pdev)
>
>         if (gr3d->clk_secondary) {
>                 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D1,
> -                                                       gr3d->clk_secondary);
> +                                                       gr3d->clk_secondary,
> +                                                       gr3d->rst_secondary);
>                 if (err < 0) {
>                         dev_err(&pdev->dev,
>                                 "failed to power up secondary 3D unit\n");
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index 174a5bc2d993..aace19edc469 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -956,7 +956,8 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
>         }
>
>         err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
> -                                               pcie->pex_clk);
> +                                               pcie->pex_clk,
> +                                               pcie->pex_rst);
>         if (err) {
>                 dev_err(pcie->dev, "powerup sequence failed: %d\n", err);
>                 return err;
> diff --git a/include/linux/tegra-powergate.h b/include/linux/tegra-powergate.h
> index c98cfa406952..b5ad64aca071 100644
> --- a/include/linux/tegra-powergate.h
> +++ b/include/linux/tegra-powergate.h
> @@ -19,6 +19,7 @@
>  #define _MACH_TEGRA_POWERGATE_H_
>
>  struct clk;
> +struct reset_control;
>
>  #define TEGRA_POWERGATE_CPU    0
>  #define TEGRA_POWERGATE_3D     1
> @@ -51,6 +52,7 @@ int tegra_powergate_power_off(int id);
>  int tegra_powergate_remove_clamping(int id);
>
>  /* Must be called with clk disabled, and returns with clk enabled */
> -int tegra_powergate_sequence_power_up(int id, struct clk *clk);
> +int tegra_powergate_sequence_power_up(int id, struct clk *clk,
> +                                       struct reset_control *rst);
>
>  #endif /* _MACH_TEGRA_POWERGATE_H_ */
> --
> 1.8.1.5
>

[PATCH 10/31] ARM: tegra: pass reset to tegra_powergate_sequence_power_up()

[Bjorn Helgaas]

On Fri, Nov 15, 2013 at 1:54 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
>
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: linux-pci at vger.kernel.org
> Cc: Terje Bergstr?m <tbergstrom@nvidia.com>
> Cc: David Airlie <airlied@linux.ie>
> Cc: dri-devel at lists.freedesktop.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>

Acked-by: Bjorn Helgaas <bhelgaas@google.com>

> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  arch/arm/mach-tegra/powergate.c | 8 +++++---
>  drivers/gpu/drm/tegra/gr3d.c    | 6 ++++--
>  drivers/pci/host/pci-tegra.c    | 3 ++-
>  include/linux/tegra-powergate.h | 4 +++-
>  4 files changed, 14 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
> index 85d28e756bb7..f6f5b54ff95e 100644
> --- a/arch/arm/mach-tegra/powergate.c
> +++ b/arch/arm/mach-tegra/powergate.c
> @@ -25,6 +25,7 @@
>  #include <linux/export.h>
>  #include <linux/init.h>
>  #include <linux/io.h>
> +#include <linux/reset.h>
>  #include <linux/seq_file.h>
>  #include <linux/spinlock.h>
>  #include <linux/clk/tegra.h>
> @@ -144,11 +145,12 @@ int tegra_powergate_remove_clamping(int id)
>  }
>
>  /* Must be called with clk disabled, and returns with clk enabled */
> -int tegra_powergate_sequence_power_up(int id, struct clk *clk)
> +int tegra_powergate_sequence_power_up(int id, struct clk *clk,
> +                                       struct reset_control *rst)
>  {
>         int ret;
>
> -       tegra_periph_reset_assert(clk);
> +       reset_control_assert(rst);
>
>         ret = tegra_powergate_power_on(id);
>         if (ret)
> @@ -165,7 +167,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
>                 goto err_clamp;
>
>         udelay(10);
> -       tegra_periph_reset_deassert(clk);
> +       reset_control_deassert(rst);
>
>         return 0;
>
> diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c
> index f629e38b00e4..0cbb24b1ae04 100644
> --- a/drivers/gpu/drm/tegra/gr3d.c
> +++ b/drivers/gpu/drm/tegra/gr3d.c
> @@ -279,7 +279,8 @@ static int gr3d_probe(struct platform_device *pdev)
>                 }
>         }
>
> -       err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk);
> +       err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk,
> +                                               gr3d->rst);
>         if (err < 0) {
>                 dev_err(&pdev->dev, "failed to power up 3D unit\n");
>                 return err;
> @@ -287,7 +288,8 @@ static int gr3d_probe(struct platform_device *pdev)
>
>         if (gr3d->clk_secondary) {
>                 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D1,
> -                                                       gr3d->clk_secondary);
> +                                                       gr3d->clk_secondary,
> +                                                       gr3d->rst_secondary);
>                 if (err < 0) {
>                         dev_err(&pdev->dev,
>                                 "failed to power up secondary 3D unit\n");
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index 174a5bc2d993..aace19edc469 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -956,7 +956,8 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
>         }
>
>         err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
> -                                               pcie->pex_clk);
> +                                               pcie->pex_clk,
> +                                               pcie->pex_rst);
>         if (err) {
>                 dev_err(pcie->dev, "powerup sequence failed: %d\n", err);
>                 return err;
> diff --git a/include/linux/tegra-powergate.h b/include/linux/tegra-powergate.h
> index c98cfa406952..b5ad64aca071 100644
> --- a/include/linux/tegra-powergate.h
> +++ b/include/linux/tegra-powergate.h
> @@ -19,6 +19,7 @@
>  #define _MACH_TEGRA_POWERGATE_H_
>
>  struct clk;
> +struct reset_control;
>
>  #define TEGRA_POWERGATE_CPU    0
>  #define TEGRA_POWERGATE_3D     1
> @@ -51,6 +52,7 @@ int tegra_powergate_power_off(int id);
>  int tegra_powergate_remove_clamping(int id);
>
>  /* Must be called with clk disabled, and returns with clk enabled */
> -int tegra_powergate_sequence_power_up(int id, struct clk *clk);
> +int tegra_powergate_sequence_power_up(int id, struct clk *clk,
> +                                       struct reset_control *rst);
>
>  #endif /* _MACH_TEGRA_POWERGATE_H_ */
> --
> 1.8.1.5
>

Re: [PATCH 10/31] ARM: tegra: pass reset to tegra_powergate_sequence_power_up()

[Bjorn Helgaas]

On Fri, Nov 15, 2013 at 1:54 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
>
> Cc: treding@nvidia.com
> Cc: pdeschrijver@nvidia.com
> Cc: linux-tegra@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: linux-pci@vger.kernel.org
> Cc: Terje Bergström <tbergstrom@nvidia.com>
> Cc: David Airlie <airlied@linux.ie>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>

Acked-by: Bjorn Helgaas <bhelgaas@google.com>

> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  arch/arm/mach-tegra/powergate.c | 8 +++++---
>  drivers/gpu/drm/tegra/gr3d.c    | 6 ++++--
>  drivers/pci/host/pci-tegra.c    | 3 ++-
>  include/linux/tegra-powergate.h | 4 +++-
>  4 files changed, 14 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
> index 85d28e756bb7..f6f5b54ff95e 100644
> --- a/arch/arm/mach-tegra/powergate.c
> +++ b/arch/arm/mach-tegra/powergate.c
> @@ -25,6 +25,7 @@
>  #include <linux/export.h>
>  #include <linux/init.h>
>  #include <linux/io.h>
> +#include <linux/reset.h>
>  #include <linux/seq_file.h>
>  #include <linux/spinlock.h>
>  #include <linux/clk/tegra.h>
> @@ -144,11 +145,12 @@ int tegra_powergate_remove_clamping(int id)
>  }
>
>  /* Must be called with clk disabled, and returns with clk enabled */
> -int tegra_powergate_sequence_power_up(int id, struct clk *clk)
> +int tegra_powergate_sequence_power_up(int id, struct clk *clk,
> +                                       struct reset_control *rst)
>  {
>         int ret;
>
> -       tegra_periph_reset_assert(clk);
> +       reset_control_assert(rst);
>
>         ret = tegra_powergate_power_on(id);
>         if (ret)
> @@ -165,7 +167,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
>                 goto err_clamp;
>
>         udelay(10);
> -       tegra_periph_reset_deassert(clk);
> +       reset_control_deassert(rst);
>
>         return 0;
>
> diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c
> index f629e38b00e4..0cbb24b1ae04 100644
> --- a/drivers/gpu/drm/tegra/gr3d.c
> +++ b/drivers/gpu/drm/tegra/gr3d.c
> @@ -279,7 +279,8 @@ static int gr3d_probe(struct platform_device *pdev)
>                 }
>         }
>
> -       err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk);
> +       err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk,
> +                                               gr3d->rst);
>         if (err < 0) {
>                 dev_err(&pdev->dev, "failed to power up 3D unit\n");
>                 return err;
> @@ -287,7 +288,8 @@ static int gr3d_probe(struct platform_device *pdev)
>
>         if (gr3d->clk_secondary) {
>                 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D1,
> -                                                       gr3d->clk_secondary);
> +                                                       gr3d->clk_secondary,
> +                                                       gr3d->rst_secondary);
>                 if (err < 0) {
>                         dev_err(&pdev->dev,
>                                 "failed to power up secondary 3D unit\n");
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index 174a5bc2d993..aace19edc469 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -956,7 +956,8 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
>         }
>
>         err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
> -                                               pcie->pex_clk);
> +                                               pcie->pex_clk,
> +                                               pcie->pex_rst);
>         if (err) {
>                 dev_err(pcie->dev, "powerup sequence failed: %d\n", err);
>                 return err;
> diff --git a/include/linux/tegra-powergate.h b/include/linux/tegra-powergate.h
> index c98cfa406952..b5ad64aca071 100644
> --- a/include/linux/tegra-powergate.h
> +++ b/include/linux/tegra-powergate.h
> @@ -19,6 +19,7 @@
>  #define _MACH_TEGRA_POWERGATE_H_
>
>  struct clk;
> +struct reset_control;
>
>  #define TEGRA_POWERGATE_CPU    0
>  #define TEGRA_POWERGATE_3D     1
> @@ -51,6 +52,7 @@ int tegra_powergate_power_off(int id);
>  int tegra_powergate_remove_clamping(int id);
>
>  /* Must be called with clk disabled, and returns with clk enabled */
> -int tegra_powergate_sequence_power_up(int id, struct clk *clk);
> +int tegra_powergate_sequence_power_up(int id, struct clk *clk,
> +                                       struct reset_control *rst);
>
>  #endif /* _MACH_TEGRA_POWERGATE_H_ */
> --
> 1.8.1.5
>

Re: [PATCH 10/31] ARM: tegra: pass reset to tegra_powergate_sequence_power_up()

[Thierry Reding]

[-- Attachment #1.1: Type: text/plain, Size: 372 bytes --]

On Fri, Nov 15, 2013 at 01:54:05PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.

Ah, there it is!

Reviewed-by: Thierry Reding <treding@nvidia.com>

[-- Attachment #1.2: Type: application/pgp-signature, Size: 836 bytes --]

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_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH 10/31] ARM: tegra: pass reset to tegra_powergate_sequence_power_up()

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:54:05PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.

Ah, there it is!

Reviewed-by: Thierry Reding <treding@nvidia.com>
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Re: [PATCH 10/31] ARM: tegra: pass reset to tegra_powergate_sequence_power_up()

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 372 bytes --]

On Fri, Nov 15, 2013 at 01:54:05PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.

Ah, there it is!

Reviewed-by: Thierry Reding <treding@nvidia.com>

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Re: [PATCH 10/31] ARM: tegra: pass reset to tegra_powergate_sequence_power_up()

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 598 bytes --]

On Fri, Nov 29, 2013 at 02:45:33PM +0100, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:54:05PM -0700, Stephen Warren wrote:
> > From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> > 
> > Tegra's clock driver now provides an implementation of the common
> > reset API (include/linux/reset.h). Use this instead of the old Tegra-
> > specific API; that will soon be removed.
> 
> Ah, there it is!
> 
> Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

And: Acked-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

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[PATCH 10/31] ARM: tegra: pass reset to tegra_powergate_sequence_power_up()

[Thierry Reding]

On Fri, Nov 29, 2013 at 02:45:33PM +0100, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:54:05PM -0700, Stephen Warren wrote:
> > From: Stephen Warren <swarren@nvidia.com>
> > 
> > Tegra's clock driver now provides an implementation of the common
> > reset API (include/linux/reset.h). Use this instead of the old Tegra-
> > specific API; that will soon be removed.
> 
> Ah, there it is!
> 
> Reviewed-by: Thierry Reding <treding@nvidia.com>

And: Acked-by: Thierry Reding <treding@nvidia.com>
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Re: [PATCH 10/31] ARM: tegra: pass reset to tegra_powergate_sequence_power_up()

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 511 bytes --]

On Fri, Nov 29, 2013 at 02:45:33PM +0100, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:54:05PM -0700, Stephen Warren wrote:
> > From: Stephen Warren <swarren@nvidia.com>
> > 
> > Tegra's clock driver now provides an implementation of the common
> > reset API (include/linux/reset.h). Use this instead of the old Tegra-
> > specific API; that will soon be removed.
> 
> Ah, there it is!
> 
> Reviewed-by: Thierry Reding <treding@nvidia.com>

And: Acked-by: Thierry Reding <treding@nvidia.com>

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[PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Many of the Tegra DT binding documents say nothing about the clocks or
clock-names properties, yet those are present and required in DT files.
This patch simply updates the documentation file to match the implicit
definition of the binding, based on real-world DT content.

All Tegra bindings that mention clocks are updated to have consistent
wording and formatting of the clock-related properties.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../bindings/arm/tegra/nvidia,tegra20-pmc.txt      |  1 +
 .../devicetree/bindings/dma/tegra20-apbdma.txt     |  3 ++
 .../bindings/gpu/nvidia,tegra20-host1x.txt         | 61 ++++++++++++++++++++++
 .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt | 14 ++---
 .../bindings/input/nvidia,tegra20-kbc.txt          |  3 ++
 .../bindings/mmc/nvidia,tegra20-sdhci.txt          |  3 ++
 .../devicetree/bindings/nvec/nvidia,nvec.txt       |  8 +++
 .../bindings/pci/nvidia,tegra20-pcie.txt           | 16 +++---
 .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt |  3 ++
 .../devicetree/bindings/rtc/nvidia,tegra20-rtc.txt |  3 ++
 .../bindings/serial/nvidia,tegra20-hsuart.txt      |  3 ++
 .../bindings/sound/nvidia,tegra-audio-alc5632.txt  |  7 +--
 .../bindings/sound/nvidia,tegra-audio-rt5640.txt   |  7 +--
 .../bindings/sound/nvidia,tegra-audio-wm8753.txt   |  7 +--
 .../bindings/sound/nvidia,tegra-audio-wm8903.txt   |  7 +--
 .../bindings/sound/nvidia,tegra-audio-wm9712.txt   |  7 +--
 .../bindings/sound/nvidia,tegra20-ac97.txt         |  4 ++
 .../bindings/sound/nvidia,tegra20-i2s.txt          |  3 ++
 .../bindings/sound/nvidia,tegra30-ahub.txt         | 21 ++++++--
 .../bindings/sound/nvidia,tegra30-i2s.txt          |  5 +-
 .../bindings/spi/nvidia,tegra114-spi.txt           |  8 ++-
 .../bindings/spi/nvidia,tegra20-sflash.txt         |  4 +-
 .../bindings/spi/nvidia,tegra20-slink.txt          |  4 +-
 .../bindings/timer/nvidia,tegra20-timer.txt        |  3 ++
 .../bindings/timer/nvidia,tegra30-timer.txt        |  3 ++
 .../bindings/usb/nvidia,tegra20-ehci.txt           |  3 +-
 26 files changed, 172 insertions(+), 39 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
index 1608a54e90e1..68ac65f82a1c 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
@@ -9,6 +9,7 @@ Required properties:
 - compatible : Should contain "nvidia,tegra<chip>-pmc".
 - reg : Offset and length of the register set for the device
 - clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
   "pclk" (The Tegra clock of that name),
   "clk32k_in" (The 32KHz clock input to Tegra).
diff --git a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
index 90fa7da525b8..74bfc54bb184 100644
--- a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
+++ b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
@@ -5,6 +5,8 @@ Required properties:
 - reg: Should contain DMA registers location and length. This shuld include
   all of the per-channel registers.
 - interrupts: Should contain all of the per-channel DMA interrupts.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Examples:
 
@@ -27,4 +29,5 @@ apbdma: dma@6000a000 {
 		       0 149 0x04
 		       0 150 0x04
 		       0 151 0x04 >;
+	clocks = <&tegra_car 34>;
 };
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
index b4fa934ae3a2..c9a715a75f60 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
@@ -9,6 +9,8 @@ Required properties:
 - #size-cells: The number of cells used to represent the size of an address
   range in the host1x address space. Should be 1.
 - ranges: The mapping of the host1x address space to the CPU address space.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 The host1x top-level node defines a number of children, each representing one
 of the following host1x client modules:
@@ -19,6 +21,8 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-mpe"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
 
 - vi: video input
 
@@ -26,6 +30,8 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-vi"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
 
 - epp: encoder pre-processor
 
@@ -33,6 +39,8 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-epp"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
 
 - isp: image signal processor
 
@@ -40,6 +48,8 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-isp"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
 
 - gr2d: 2D graphics engine
 
@@ -47,12 +57,23 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-gr2d"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
 
 - gr3d: 3D graphics engine
 
   Required properties:
   - compatible: "nvidia,tegra<chip>-gr3d"
   - reg: Physical base address and length of the controller's registers.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
+  - clocks : Must contain an entry for each entry in clock-names.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names : Must include the following entries:
+    (This property may be omitted if the only clock in the list is "3d")
+    - 3d
+      This MUST be the first entry.
+    - 3d2 (Only required on SoCs with two 3D clocks)
 
 - dc: display controller
 
@@ -60,6 +81,12 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-dc"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain an entry for each entry in clock-names.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names : Must include the following entries:
+    - disp1 or disp2 (depending on the controller instance)
+      This MUST be the first entry.
+    - parent
 
   Each display controller node has a child node, named "rgb", that represents
   the RGB output associated with the controller. It can take the following
@@ -76,6 +103,12 @@ of the following host1x client modules:
   - interrupts: The interrupt outputs from the controller.
   - vdd-supply: regulator for supply voltage
   - pll-supply: regulator for PLL
+  - clocks : Must contain an entry for each entry in clock-names.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names : Must include the following entries:
+    - hdmi
+      This MUST be the first entry.
+    - parent
 
   Optional properties:
   - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
@@ -88,12 +121,22 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-tvo"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
 
 - dsi: display serial interface
 
   Required properties:
   - compatible: "nvidia,tegra<chip>-dsi"
   - reg: Physical base address and length of the controller's registers.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
+  - clocks : Must contain an entry for each entry in clock-names.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names : Must include the following entries:
+    - dsi
+      This MUST be the first entry.
+    - parent
 
 Example:
 
@@ -105,6 +148,7 @@ Example:
 		reg = <0x50000000 0x00024000>;
 		interrupts = <0 65 0x04   /* mpcore syncpt */
 			      0 67 0x04>; /* mpcore general */
+		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
 
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -115,41 +159,50 @@ Example:
 			compatible = "nvidia,tegra20-mpe";
 			reg = <0x54040000 0x00040000>;
 			interrupts = <0 68 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_MPE>;
 		};
 
 		vi {
 			compatible = "nvidia,tegra20-vi";
 			reg = <0x54080000 0x00040000>;
 			interrupts = <0 69 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_VI>;
 		};
 
 		epp {
 			compatible = "nvidia,tegra20-epp";
 			reg = <0x540c0000 0x00040000>;
 			interrupts = <0 70 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_EPP>;
 		};
 
 		isp {
 			compatible = "nvidia,tegra20-isp";
 			reg = <0x54100000 0x00040000>;
 			interrupts = <0 71 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_ISP>;
 		};
 
 		gr2d {
 			compatible = "nvidia,tegra20-gr2d";
 			reg = <0x54140000 0x00040000>;
 			interrupts = <0 72 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_GR2D>;
 		};
 
 		gr3d {
 			compatible = "nvidia,tegra20-gr3d";
 			reg = <0x54180000 0x00040000>;
+			clocks = <&tegra_car TEGRA20_CLK_GR3D>;
 		};
 
 		dc@54200000 {
 			compatible = "nvidia,tegra20-dc";
 			reg = <0x54200000 0x00040000>;
 			interrupts = <0 73 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
+				 <&tegra_car TEGRA20_CLK_PLL_P>;
+			clock-names = "disp1", "parent";
 
 			rgb {
 				status = "disabled";
@@ -160,6 +213,9 @@ Example:
 			compatible = "nvidia,tegra20-dc";
 			reg = <0x54240000 0x00040000>;
 			interrupts = <0 74 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_DISP2>,
+				 <&tegra_car TEGRA20_CLK_PLL_P>;
+			clock-names = "disp2", "parent";
 
 			rgb {
 				status = "disabled";
@@ -170,6 +226,9 @@ Example:
 			compatible = "nvidia,tegra20-hdmi";
 			reg = <0x54280000 0x00040000>;
 			interrupts = <0 75 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_HDMI>,
+				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
+			clock-names = "hdmi", "parent";
 			status = "disabled";
 		};
 
@@ -177,12 +236,14 @@ Example:
 			compatible = "nvidia,tegra20-tvo";
 			reg = <0x542c0000 0x00040000>;
 			interrupts = <0 76 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_TVO>;
 			status = "disabled";
 		};
 
 		dsi {
 			compatible = "nvidia,tegra20-dsi";
 			reg = <0x54300000 0x00040000>;
+			clocks = <&tegra_car TEGRA20_CLK_DSI>;
 			status = "disabled";
 		};
 	};
diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
index ef77cc7a0e46..96ab40131ae1 100644
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
@@ -39,12 +39,14 @@ Required properties:
 - interrupts: Should contain I2C controller interrupts.
 - address-cells: Address cells for I2C device address.
 - size-cells: Size of the I2C device address.
-- clocks: Clock ID as per
-		Documentation/devicetree/bindings/clock/tegra<chip-id>.txt
-	for I2C controller.
-- clock-names: Name of the clock:
-	Tegra20/Tegra30 I2C controller: "div-clk and "fast-clk".
-	Tegra114 I2C controller: "div-clk".
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names : Must include the following entries:
+  Tegra20/Tegra30:
+  - div-clk
+  - fast-clk
+  Tegra114:
+  - div-clk
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
index 2995fae7ee47..cc28d2194c37 100644
--- a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
+++ b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
@@ -13,6 +13,8 @@ Required properties:
   array of pin numbers which is used as column.
 - linux,keymap: The keymap for keys as described in the binding document
   devicetree/bindings/input/matrix-keymap.txt.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Optional properties, in addition to those specified by the shared
 matrix-keyboard bindings:
@@ -31,6 +33,7 @@ keyboard: keyboard {
 	compatible = "nvidia,tegra20-kbc";
 	reg = <0x7000e200 0x100>;
 	interrupts = <0 85 0x04>;
+	clocks = <&tegra_car 36>;
 	nvidia,ghost-filter;
 	nvidia,debounce-delay-ms = <640>;
 	nvidia,kbc-row-pins = <0 1 2>;    /* pin 0, 1, 2 as rows */
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
index c6d7b11db9eb..f727902a9e8d 100644
--- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
@@ -8,6 +8,8 @@ by mmc.txt and the properties used by the sdhci-tegra driver.
 
 Required properties:
 - compatible : Should be "nvidia,<chip>-sdhci"
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Optional properties:
 - power-gpios : Specify GPIOs for power control
@@ -18,6 +20,7 @@ sdhci@c8000200 {
 	compatible = "nvidia,tegra20-sdhci";
 	reg = <0xc8000200 0x200>;
 	interrupts = <47>;
+	clocks = <&tegra_car 14>;
 	cd-gpios = <&gpio 69 0>; /* gpio PI5 */
 	wp-gpios = <&gpio 57 0>; /* gpio PH1 */
 	power-gpios = <&gpio 155 0>; /* gpio PT3 */
diff --git a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
index 5aeee53ff9f4..a97fe575ca29 100644
--- a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
+++ b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
@@ -7,3 +7,11 @@ Required properties:
 - clock-frequency : the frequency of the i2c bus
 - gpios : the gpio used for ec request
 - slave-addr: the i2c address of the slave controller
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names : Must include the following entries:
+  Tegra20/Tegra30:
+  - div-clk
+  - fast-clk
+  Tegra114:
+  - div-clk
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
index 6b7510775c50..ad2eb9804afa 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
@@ -42,14 +42,14 @@ Required properties:
     - 0xc2000000: prefetchable memory region
   Please refer to the standard PCI bus binding document for a more detailed
   explanation.
-- clocks: List of clock inputs of the controller. Must contain an entry for
-  each entry in the clock-names property.
-- clock-names: Must include the following entries:
-  "pex": The Tegra clock of that name
-  "afi": The Tegra clock of that name
-  "pcie_xclk": The Tegra clock of that name
-  "pll_e": The Tegra clock of that name
-  "cml": The Tegra clock of that name (not required for Tegra20)
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names : Must include the following entries:
+  - pex
+  - afi
+  - pcie_xclk
+  - pll_e
+  - cml (not required for Tegra20)
 
 Root ports are defined as subnodes of the PCIe controller node.
 
diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
index c3fc57af8772..0d608d34fed0 100644
--- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
@@ -7,6 +7,8 @@ Required properties:
 - reg: physical base address and length of the controller's registers
 - #pwm-cells: should be 2. See pwm.txt in this directory for a description of
   the cells format.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Example:
 
@@ -14,4 +16,5 @@ Example:
 		compatible = "nvidia,tegra20-pwm";
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
+		clocks = <&tegra_car 17>;
 	};
diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
index 93f45e9dce7c..652d1ff2e8be 100644
--- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
@@ -9,6 +9,8 @@ Required properties:
 - compatible : should be "nvidia,tegra20-rtc".
 - reg : Specifies base physical address and size of the registers.
 - interrupts : A single interrupt specifier.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Example:
 
@@ -16,4 +18,5 @@ timer {
 	compatible = "nvidia,tegra20-rtc";
 	reg = <0x7000e000 0x100>;
 	interrupts = <0 2 0x04>;
+	clocks = <&tegra_car 4>;
 };
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
index 392a4493eebd..39148b6236a1 100644
--- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
+++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
@@ -6,6 +6,8 @@ Required properties:
 - interrupts: Should contain UART controller interrupts.
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for this UART controller.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Optional properties:
 - nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
@@ -20,5 +22,6 @@ serial@70006000 {
 	interrupts = <0 36 0x04>;
 	nvidia,dma-request-selector = <&apbdma 8>;
 	nvidia,enable-modem-interrupt;
+	clocks = <&tegra_car 6>;
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
index 8b8903ef0800..57f40f93453e 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
 Required properties:
 - compatible : "nvidia,tegra-audio-alc5632"
 - clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
-  "pll_a" (The Tegra clock of that name),
-  "pll_a_out0" (The Tegra clock of that name),
-  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
+  - pll_a
+  - pll_a_out0
+  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
 - nvidia,model : The user-visible name of this sound complex.
 - nvidia,audio-routing : A list of the connections between audio components.
   Each entry is a pair of strings, the first being the connection's sink,
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
index dc6224994d69..7788808dcd0b 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex, with RT5640 CODEC
 Required properties:
 - compatible : "nvidia,tegra-audio-rt5640"
 - clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
-  "pll_a" (The Tegra clock of that name),
-  "pll_a_out0" (The Tegra clock of that name),
-  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
+  - pll_a
+  - pll_a_out0
+  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
 - nvidia,model : The user-visible name of this sound complex.
 - nvidia,audio-routing : A list of the connections between audio components.
   Each entry is a pair of strings, the first being the connection's sink,
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
index aab6ce0ad2fc..96f6a57dd6b4 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
 Required properties:
 - compatible : "nvidia,tegra-audio-wm8753"
 - clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
-  "pll_a" (The Tegra clock of that name),
-  "pll_a_out0" (The Tegra clock of that name),
-  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
+  - pll_a
+  - pll_a_out0
+  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
 - nvidia,model : The user-visible name of this sound complex.
 - nvidia,audio-routing : A list of the connections between audio components.
   Each entry is a pair of strings, the first being the connection's sink,
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
index 4b44dfb6ca0d..b795d282818d 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
 Required properties:
 - compatible : "nvidia,tegra-audio-wm8903"
 - clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
-  "pll_a" (The Tegra clock of that name),
-  "pll_a_out0" (The Tegra clock of that name),
-  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
+  - pll_a
+  - pll_a_out0
+  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
 - nvidia,model : The user-visible name of this sound complex.
 - nvidia,audio-routing : A list of the connections between audio components.
   Each entry is a pair of strings, the first being the connection's sink,
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
index ad589b163639..436f6cd9d07c 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
 Required properties:
 - compatible : "nvidia,tegra-audio-wm9712"
 - clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
-  "pll_a" (The Tegra clock of that name),
-  "pll_a_out0" (The Tegra clock of that name),
-  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
+  - pll_a
+  - pll_a_out0
+  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
 - nvidia,model : The user-visible name of this sound complex.
 - nvidia,audio-routing : A list of the connections between audio components.
   Each entry is a pair of strings, the first being the connection's sink,
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
index c1454979c1ef..37f4ebf5b184 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
@@ -4,12 +4,15 @@ Required properties:
 - compatible : "nvidia,tegra20-ac97"
 - reg : Should contain AC97 controller registers location and length
 - interrupts : Should contain AC97 interrupt
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for the AC97 controller
 - nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the number
   of the GPIO used to reset the external AC97 codec
 - nvidia,codec-sync-gpio : The Tegra GPIO controller's phandle and the number
   of the GPIO corresponding with the AC97 DAP _FS line
+
 Example:
 
 ac97@70002000 {
@@ -19,4 +22,5 @@ ac97@70002000 {
 	nvidia,dma-request-selector = <&apbdma 12>;
 	nvidia,codec-reset-gpio = <&gpio 170 0>;
 	nvidia,codec-sync-gpio = <&gpio 120 0>;
+	clocks = <&tegra_car 3>;
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
index 0df2b5c816e3..ba0c9452916d 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
@@ -4,6 +4,8 @@ Required properties:
 - compatible : "nvidia,tegra20-i2s"
 - reg : Should contain I2S registers location and length
 - interrupts : Should contain I2S interrupt
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for this I2S controller
 
@@ -14,4 +16,5 @@ i2s@70002800 {
 	reg = <0x70002800 0x200>;
 	interrupts = < 45 >;
 	nvidia,dma-request-selector = < &apbdma 2 >;
+	clocks = <&tegra_car 11>;
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
index 0e5c12c66523..7299eeadd588 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
@@ -12,11 +12,24 @@ Required properties:
   If a single entry is present, the request selectors for the channels are
   assumed to be contiguous, and increment from this value.
   If multiple values are given, one value must be given per channel.
-- clocks : Must contain an entry for each required entry in clock-names.
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
-  - Tegra30: Requires d_audio, apbif, i2s0, i2s1, i2s2, i2s3, i2s4, dam0,
-    dam1, dam2, spdif_in.
-  - Tegra114: Additionally requires amx, adx.
+  Tegra30 and later:
+  - d_audio
+  - apbif
+  - i2s0
+  - i2s1
+  - i2s2
+  - i2s3
+  - i2s4
+  - dam0
+  - dam1
+  - dam2
+  - spdif_in
+  Tegra114 and later additionally require:
+  - amx
+  - adx
 - ranges : The bus address mapping for the configlink register bus.
   Can be empty since the mapping is 1:1.
 - #address-cells : For the configlink bus. Should be <1>;
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
index dfa6c037124a..7a3112bc135c 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
@@ -3,13 +3,16 @@ NVIDIA Tegra30 I2S controller
 Required properties:
 - compatible : "nvidia,tegra30-i2s"
 - reg : Should contain I2S registers location and length
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 - nvidia,ahub-cif-ids : The list of AHUB CIF IDs for this port, rx (playback)
   first, tx (capture) second. See nvidia,tegra30-ahub.txt for values.
 
 Example:
 
-i2s@70002800 {
+i2s@70080300 {
 	compatible = "nvidia,tegra30-i2s";
 	reg = <0x70080300 0x100>;
 	nvidia,ahub-cif-ids = <4 4>;
+	clocks = <&tegra_car 11>;
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
index 91ff771c7e77..d4f2d534934b 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
@@ -6,8 +6,10 @@ Required properties:
 - interrupts: Should contain SPI interrupts.
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for this SPI controller.
-- This is also require clock named "spi" as per binding document
-  Documentation/devicetree/bindings/clock/clock-bindings.txt
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names : Must include the following entries:
+  - spi
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -22,5 +24,7 @@ spi@7000d600 {
 	spi-max-frequency = <25000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
+	clocks = <&tegra_car 44>;
+	clock-names = "spi";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
index 7b53da5cb75b..66e16c7f5939 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
@@ -6,6 +6,8 @@ Required properties:
 - interrupts: Should contain SFLASH interrupts.
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for this SFLASH controller.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -21,6 +23,6 @@ spi@7000c380 {
 	spi-max-frequency = <25000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
+	clocks = <&tegra_car 43>;
 	status = "disabled";
 };
-
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
index eefe15e3d95e..0e6e94eb2b2a 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
@@ -6,6 +6,8 @@ Required properties:
 - interrupts: Should contain SLINK interrupts.
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for this SLINK controller.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -21,6 +23,6 @@ spi@7000d600 {
 	spi-max-frequency = <25000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
+	clocks = <&tegra_car 44>;
 	status = "disabled";
 };
-
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
index e019fdc38773..4a864bd10d3d 100644
--- a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
@@ -8,6 +8,8 @@ Required properties:
 - compatible : should be "nvidia,tegra20-timer".
 - reg : Specifies base physical address and size of the registers.
 - interrupts : A list of 4 interrupts; one per timer channel.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Example:
 
@@ -18,4 +20,5 @@ timer {
 			0 1 0x04
 			0 41 0x04
 			0 42 0x04>;
+	clocks = <&tegra_car 132>;
 };
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
index 906109d4c593..b5082a1cf461 100644
--- a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
@@ -10,6 +10,8 @@ Required properties:
 - reg : Specifies base physical address and size of the registers.
 - interrupts : A list of 6 interrupts; one per each of timer channels 1
     through 5, and one for the shared interrupt for the remaining channels.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 timer {
 	compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
@@ -20,4 +22,5 @@ timer {
 		      0 42 0x04
 		      0 121 0x04
 		      0 122 0x04>;
+	clocks = <&tegra_car 214>;
 };
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
index df0933043a5b..b98d0bdfa248 100644
--- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
@@ -8,7 +8,8 @@ and additions :
 Required properties :
  - compatible : Should be "nvidia,tegra20-ehci".
  - nvidia,phy : phandle of the PHY that the controller is connected to.
- - clocks : Contains a single entry which defines the USB controller's clock.
+ - clocks : Must contain one entry, for the module clock.
+   See ../clocks/clock-bindings.txt for details.
 
 Optional properties:
  - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20
-- 
1.8.1.5

[PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Many of the Tegra DT binding documents say nothing about the clocks or
clock-names properties, yet those are present and required in DT files.
This patch simply updates the documentation file to match the implicit
definition of the binding, based on real-world DT content.

All Tegra bindings that mention clocks are updated to have consistent
wording and formatting of the clock-related properties.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: devicetree at vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 .../bindings/arm/tegra/nvidia,tegra20-pmc.txt      |  1 +
 .../devicetree/bindings/dma/tegra20-apbdma.txt     |  3 ++
 .../bindings/gpu/nvidia,tegra20-host1x.txt         | 61 ++++++++++++++++++++++
 .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt | 14 ++---
 .../bindings/input/nvidia,tegra20-kbc.txt          |  3 ++
 .../bindings/mmc/nvidia,tegra20-sdhci.txt          |  3 ++
 .../devicetree/bindings/nvec/nvidia,nvec.txt       |  8 +++
 .../bindings/pci/nvidia,tegra20-pcie.txt           | 16 +++---
 .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt |  3 ++
 .../devicetree/bindings/rtc/nvidia,tegra20-rtc.txt |  3 ++
 .../bindings/serial/nvidia,tegra20-hsuart.txt      |  3 ++
 .../bindings/sound/nvidia,tegra-audio-alc5632.txt  |  7 +--
 .../bindings/sound/nvidia,tegra-audio-rt5640.txt   |  7 +--
 .../bindings/sound/nvidia,tegra-audio-wm8753.txt   |  7 +--
 .../bindings/sound/nvidia,tegra-audio-wm8903.txt   |  7 +--
 .../bindings/sound/nvidia,tegra-audio-wm9712.txt   |  7 +--
 .../bindings/sound/nvidia,tegra20-ac97.txt         |  4 ++
 .../bindings/sound/nvidia,tegra20-i2s.txt          |  3 ++
 .../bindings/sound/nvidia,tegra30-ahub.txt         | 21 ++++++--
 .../bindings/sound/nvidia,tegra30-i2s.txt          |  5 +-
 .../bindings/spi/nvidia,tegra114-spi.txt           |  8 ++-
 .../bindings/spi/nvidia,tegra20-sflash.txt         |  4 +-
 .../bindings/spi/nvidia,tegra20-slink.txt          |  4 +-
 .../bindings/timer/nvidia,tegra20-timer.txt        |  3 ++
 .../bindings/timer/nvidia,tegra30-timer.txt        |  3 ++
 .../bindings/usb/nvidia,tegra20-ehci.txt           |  3 +-
 26 files changed, 172 insertions(+), 39 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
index 1608a54e90e1..68ac65f82a1c 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
@@ -9,6 +9,7 @@ Required properties:
 - compatible : Should contain "nvidia,tegra<chip>-pmc".
 - reg : Offset and length of the register set for the device
 - clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
   "pclk" (The Tegra clock of that name),
   "clk32k_in" (The 32KHz clock input to Tegra).
diff --git a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
index 90fa7da525b8..74bfc54bb184 100644
--- a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
+++ b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
@@ -5,6 +5,8 @@ Required properties:
 - reg: Should contain DMA registers location and length. This shuld include
   all of the per-channel registers.
 - interrupts: Should contain all of the per-channel DMA interrupts.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Examples:
 
@@ -27,4 +29,5 @@ apbdma: dma at 6000a000 {
 		       0 149 0x04
 		       0 150 0x04
 		       0 151 0x04 >;
+	clocks = <&tegra_car 34>;
 };
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
index b4fa934ae3a2..c9a715a75f60 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
@@ -9,6 +9,8 @@ Required properties:
 - #size-cells: The number of cells used to represent the size of an address
   range in the host1x address space. Should be 1.
 - ranges: The mapping of the host1x address space to the CPU address space.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 The host1x top-level node defines a number of children, each representing one
 of the following host1x client modules:
@@ -19,6 +21,8 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-mpe"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
 
 - vi: video input
 
@@ -26,6 +30,8 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-vi"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
 
 - epp: encoder pre-processor
 
@@ -33,6 +39,8 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-epp"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
 
 - isp: image signal processor
 
@@ -40,6 +48,8 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-isp"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
 
 - gr2d: 2D graphics engine
 
@@ -47,12 +57,23 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-gr2d"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
 
 - gr3d: 3D graphics engine
 
   Required properties:
   - compatible: "nvidia,tegra<chip>-gr3d"
   - reg: Physical base address and length of the controller's registers.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
+  - clocks : Must contain an entry for each entry in clock-names.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names : Must include the following entries:
+    (This property may be omitted if the only clock in the list is "3d")
+    - 3d
+      This MUST be the first entry.
+    - 3d2 (Only required on SoCs with two 3D clocks)
 
 - dc: display controller
 
@@ -60,6 +81,12 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-dc"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain an entry for each entry in clock-names.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names : Must include the following entries:
+    - disp1 or disp2 (depending on the controller instance)
+      This MUST be the first entry.
+    - parent
 
   Each display controller node has a child node, named "rgb", that represents
   the RGB output associated with the controller. It can take the following
@@ -76,6 +103,12 @@ of the following host1x client modules:
   - interrupts: The interrupt outputs from the controller.
   - vdd-supply: regulator for supply voltage
   - pll-supply: regulator for PLL
+  - clocks : Must contain an entry for each entry in clock-names.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names : Must include the following entries:
+    - hdmi
+      This MUST be the first entry.
+    - parent
 
   Optional properties:
   - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
@@ -88,12 +121,22 @@ of the following host1x client modules:
   - compatible: "nvidia,tegra<chip>-tvo"
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
 
 - dsi: display serial interface
 
   Required properties:
   - compatible: "nvidia,tegra<chip>-dsi"
   - reg: Physical base address and length of the controller's registers.
+  - clocks : Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
+  - clocks : Must contain an entry for each entry in clock-names.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names : Must include the following entries:
+    - dsi
+      This MUST be the first entry.
+    - parent
 
 Example:
 
@@ -105,6 +148,7 @@ Example:
 		reg = <0x50000000 0x00024000>;
 		interrupts = <0 65 0x04   /* mpcore syncpt */
 			      0 67 0x04>; /* mpcore general */
+		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
 
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -115,41 +159,50 @@ Example:
 			compatible = "nvidia,tegra20-mpe";
 			reg = <0x54040000 0x00040000>;
 			interrupts = <0 68 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_MPE>;
 		};
 
 		vi {
 			compatible = "nvidia,tegra20-vi";
 			reg = <0x54080000 0x00040000>;
 			interrupts = <0 69 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_VI>;
 		};
 
 		epp {
 			compatible = "nvidia,tegra20-epp";
 			reg = <0x540c0000 0x00040000>;
 			interrupts = <0 70 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_EPP>;
 		};
 
 		isp {
 			compatible = "nvidia,tegra20-isp";
 			reg = <0x54100000 0x00040000>;
 			interrupts = <0 71 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_ISP>;
 		};
 
 		gr2d {
 			compatible = "nvidia,tegra20-gr2d";
 			reg = <0x54140000 0x00040000>;
 			interrupts = <0 72 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_GR2D>;
 		};
 
 		gr3d {
 			compatible = "nvidia,tegra20-gr3d";
 			reg = <0x54180000 0x00040000>;
+			clocks = <&tegra_car TEGRA20_CLK_GR3D>;
 		};
 
 		dc at 54200000 {
 			compatible = "nvidia,tegra20-dc";
 			reg = <0x54200000 0x00040000>;
 			interrupts = <0 73 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
+				 <&tegra_car TEGRA20_CLK_PLL_P>;
+			clock-names = "disp1", "parent";
 
 			rgb {
 				status = "disabled";
@@ -160,6 +213,9 @@ Example:
 			compatible = "nvidia,tegra20-dc";
 			reg = <0x54240000 0x00040000>;
 			interrupts = <0 74 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_DISP2>,
+				 <&tegra_car TEGRA20_CLK_PLL_P>;
+			clock-names = "disp2", "parent";
 
 			rgb {
 				status = "disabled";
@@ -170,6 +226,9 @@ Example:
 			compatible = "nvidia,tegra20-hdmi";
 			reg = <0x54280000 0x00040000>;
 			interrupts = <0 75 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_HDMI>,
+				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
+			clock-names = "hdmi", "parent";
 			status = "disabled";
 		};
 
@@ -177,12 +236,14 @@ Example:
 			compatible = "nvidia,tegra20-tvo";
 			reg = <0x542c0000 0x00040000>;
 			interrupts = <0 76 0x04>;
+			clocks = <&tegra_car TEGRA20_CLK_TVO>;
 			status = "disabled";
 		};
 
 		dsi {
 			compatible = "nvidia,tegra20-dsi";
 			reg = <0x54300000 0x00040000>;
+			clocks = <&tegra_car TEGRA20_CLK_DSI>;
 			status = "disabled";
 		};
 	};
diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
index ef77cc7a0e46..96ab40131ae1 100644
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
@@ -39,12 +39,14 @@ Required properties:
 - interrupts: Should contain I2C controller interrupts.
 - address-cells: Address cells for I2C device address.
 - size-cells: Size of the I2C device address.
-- clocks: Clock ID as per
-		Documentation/devicetree/bindings/clock/tegra<chip-id>.txt
-	for I2C controller.
-- clock-names: Name of the clock:
-	Tegra20/Tegra30 I2C controller: "div-clk and "fast-clk".
-	Tegra114 I2C controller: "div-clk".
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names : Must include the following entries:
+  Tegra20/Tegra30:
+  - div-clk
+  - fast-clk
+  Tegra114:
+  - div-clk
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
index 2995fae7ee47..cc28d2194c37 100644
--- a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
+++ b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
@@ -13,6 +13,8 @@ Required properties:
   array of pin numbers which is used as column.
 - linux,keymap: The keymap for keys as described in the binding document
   devicetree/bindings/input/matrix-keymap.txt.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Optional properties, in addition to those specified by the shared
 matrix-keyboard bindings:
@@ -31,6 +33,7 @@ keyboard: keyboard {
 	compatible = "nvidia,tegra20-kbc";
 	reg = <0x7000e200 0x100>;
 	interrupts = <0 85 0x04>;
+	clocks = <&tegra_car 36>;
 	nvidia,ghost-filter;
 	nvidia,debounce-delay-ms = <640>;
 	nvidia,kbc-row-pins = <0 1 2>;    /* pin 0, 1, 2 as rows */
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
index c6d7b11db9eb..f727902a9e8d 100644
--- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
@@ -8,6 +8,8 @@ by mmc.txt and the properties used by the sdhci-tegra driver.
 
 Required properties:
 - compatible : Should be "nvidia,<chip>-sdhci"
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Optional properties:
 - power-gpios : Specify GPIOs for power control
@@ -18,6 +20,7 @@ sdhci at c8000200 {
 	compatible = "nvidia,tegra20-sdhci";
 	reg = <0xc8000200 0x200>;
 	interrupts = <47>;
+	clocks = <&tegra_car 14>;
 	cd-gpios = <&gpio 69 0>; /* gpio PI5 */
 	wp-gpios = <&gpio 57 0>; /* gpio PH1 */
 	power-gpios = <&gpio 155 0>; /* gpio PT3 */
diff --git a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
index 5aeee53ff9f4..a97fe575ca29 100644
--- a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
+++ b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
@@ -7,3 +7,11 @@ Required properties:
 - clock-frequency : the frequency of the i2c bus
 - gpios : the gpio used for ec request
 - slave-addr: the i2c address of the slave controller
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names : Must include the following entries:
+  Tegra20/Tegra30:
+  - div-clk
+  - fast-clk
+  Tegra114:
+  - div-clk
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
index 6b7510775c50..ad2eb9804afa 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
@@ -42,14 +42,14 @@ Required properties:
     - 0xc2000000: prefetchable memory region
   Please refer to the standard PCI bus binding document for a more detailed
   explanation.
-- clocks: List of clock inputs of the controller. Must contain an entry for
-  each entry in the clock-names property.
-- clock-names: Must include the following entries:
-  "pex": The Tegra clock of that name
-  "afi": The Tegra clock of that name
-  "pcie_xclk": The Tegra clock of that name
-  "pll_e": The Tegra clock of that name
-  "cml": The Tegra clock of that name (not required for Tegra20)
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names : Must include the following entries:
+  - pex
+  - afi
+  - pcie_xclk
+  - pll_e
+  - cml (not required for Tegra20)
 
 Root ports are defined as subnodes of the PCIe controller node.
 
diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
index c3fc57af8772..0d608d34fed0 100644
--- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
@@ -7,6 +7,8 @@ Required properties:
 - reg: physical base address and length of the controller's registers
 - #pwm-cells: should be 2. See pwm.txt in this directory for a description of
   the cells format.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Example:
 
@@ -14,4 +16,5 @@ Example:
 		compatible = "nvidia,tegra20-pwm";
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
+		clocks = <&tegra_car 17>;
 	};
diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
index 93f45e9dce7c..652d1ff2e8be 100644
--- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
@@ -9,6 +9,8 @@ Required properties:
 - compatible : should be "nvidia,tegra20-rtc".
 - reg : Specifies base physical address and size of the registers.
 - interrupts : A single interrupt specifier.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Example:
 
@@ -16,4 +18,5 @@ timer {
 	compatible = "nvidia,tegra20-rtc";
 	reg = <0x7000e000 0x100>;
 	interrupts = <0 2 0x04>;
+	clocks = <&tegra_car 4>;
 };
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
index 392a4493eebd..39148b6236a1 100644
--- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
+++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
@@ -6,6 +6,8 @@ Required properties:
 - interrupts: Should contain UART controller interrupts.
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for this UART controller.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Optional properties:
 - nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
@@ -20,5 +22,6 @@ serial at 70006000 {
 	interrupts = <0 36 0x04>;
 	nvidia,dma-request-selector = <&apbdma 8>;
 	nvidia,enable-modem-interrupt;
+	clocks = <&tegra_car 6>;
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
index 8b8903ef0800..57f40f93453e 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
 Required properties:
 - compatible : "nvidia,tegra-audio-alc5632"
 - clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
-  "pll_a" (The Tegra clock of that name),
-  "pll_a_out0" (The Tegra clock of that name),
-  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
+  - pll_a
+  - pll_a_out0
+  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
 - nvidia,model : The user-visible name of this sound complex.
 - nvidia,audio-routing : A list of the connections between audio components.
   Each entry is a pair of strings, the first being the connection's sink,
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
index dc6224994d69..7788808dcd0b 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex, with RT5640 CODEC
 Required properties:
 - compatible : "nvidia,tegra-audio-rt5640"
 - clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
-  "pll_a" (The Tegra clock of that name),
-  "pll_a_out0" (The Tegra clock of that name),
-  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
+  - pll_a
+  - pll_a_out0
+  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
 - nvidia,model : The user-visible name of this sound complex.
 - nvidia,audio-routing : A list of the connections between audio components.
   Each entry is a pair of strings, the first being the connection's sink,
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
index aab6ce0ad2fc..96f6a57dd6b4 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
 Required properties:
 - compatible : "nvidia,tegra-audio-wm8753"
 - clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
-  "pll_a" (The Tegra clock of that name),
-  "pll_a_out0" (The Tegra clock of that name),
-  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
+  - pll_a
+  - pll_a_out0
+  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
 - nvidia,model : The user-visible name of this sound complex.
 - nvidia,audio-routing : A list of the connections between audio components.
   Each entry is a pair of strings, the first being the connection's sink,
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
index 4b44dfb6ca0d..b795d282818d 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
 Required properties:
 - compatible : "nvidia,tegra-audio-wm8903"
 - clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
-  "pll_a" (The Tegra clock of that name),
-  "pll_a_out0" (The Tegra clock of that name),
-  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
+  - pll_a
+  - pll_a_out0
+  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
 - nvidia,model : The user-visible name of this sound complex.
 - nvidia,audio-routing : A list of the connections between audio components.
   Each entry is a pair of strings, the first being the connection's sink,
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
index ad589b163639..436f6cd9d07c 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
 Required properties:
 - compatible : "nvidia,tegra-audio-wm9712"
 - clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
-  "pll_a" (The Tegra clock of that name),
-  "pll_a_out0" (The Tegra clock of that name),
-  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
+  - pll_a
+  - pll_a_out0
+  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
 - nvidia,model : The user-visible name of this sound complex.
 - nvidia,audio-routing : A list of the connections between audio components.
   Each entry is a pair of strings, the first being the connection's sink,
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
index c1454979c1ef..37f4ebf5b184 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
@@ -4,12 +4,15 @@ Required properties:
 - compatible : "nvidia,tegra20-ac97"
 - reg : Should contain AC97 controller registers location and length
 - interrupts : Should contain AC97 interrupt
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for the AC97 controller
 - nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the number
   of the GPIO used to reset the external AC97 codec
 - nvidia,codec-sync-gpio : The Tegra GPIO controller's phandle and the number
   of the GPIO corresponding with the AC97 DAP _FS line
+
 Example:
 
 ac97 at 70002000 {
@@ -19,4 +22,5 @@ ac97 at 70002000 {
 	nvidia,dma-request-selector = <&apbdma 12>;
 	nvidia,codec-reset-gpio = <&gpio 170 0>;
 	nvidia,codec-sync-gpio = <&gpio 120 0>;
+	clocks = <&tegra_car 3>;
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
index 0df2b5c816e3..ba0c9452916d 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
@@ -4,6 +4,8 @@ Required properties:
 - compatible : "nvidia,tegra20-i2s"
 - reg : Should contain I2S registers location and length
 - interrupts : Should contain I2S interrupt
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for this I2S controller
 
@@ -14,4 +16,5 @@ i2s at 70002800 {
 	reg = <0x70002800 0x200>;
 	interrupts = < 45 >;
 	nvidia,dma-request-selector = < &apbdma 2 >;
+	clocks = <&tegra_car 11>;
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
index 0e5c12c66523..7299eeadd588 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
@@ -12,11 +12,24 @@ Required properties:
   If a single entry is present, the request selectors for the channels are
   assumed to be contiguous, and increment from this value.
   If multiple values are given, one value must be given per channel.
-- clocks : Must contain an entry for each required entry in clock-names.
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
-  - Tegra30: Requires d_audio, apbif, i2s0, i2s1, i2s2, i2s3, i2s4, dam0,
-    dam1, dam2, spdif_in.
-  - Tegra114: Additionally requires amx, adx.
+  Tegra30 and later:
+  - d_audio
+  - apbif
+  - i2s0
+  - i2s1
+  - i2s2
+  - i2s3
+  - i2s4
+  - dam0
+  - dam1
+  - dam2
+  - spdif_in
+  Tegra114 and later additionally require:
+  - amx
+  - adx
 - ranges : The bus address mapping for the configlink register bus.
   Can be empty since the mapping is 1:1.
 - #address-cells : For the configlink bus. Should be <1>;
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
index dfa6c037124a..7a3112bc135c 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
@@ -3,13 +3,16 @@ NVIDIA Tegra30 I2S controller
 Required properties:
 - compatible : "nvidia,tegra30-i2s"
 - reg : Should contain I2S registers location and length
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 - nvidia,ahub-cif-ids : The list of AHUB CIF IDs for this port, rx (playback)
   first, tx (capture) second. See nvidia,tegra30-ahub.txt for values.
 
 Example:
 
-i2s at 70002800 {
+i2s at 70080300 {
 	compatible = "nvidia,tegra30-i2s";
 	reg = <0x70080300 0x100>;
 	nvidia,ahub-cif-ids = <4 4>;
+	clocks = <&tegra_car 11>;
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
index 91ff771c7e77..d4f2d534934b 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
@@ -6,8 +6,10 @@ Required properties:
 - interrupts: Should contain SPI interrupts.
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for this SPI controller.
-- This is also require clock named "spi" as per binding document
-  Documentation/devicetree/bindings/clock/clock-bindings.txt
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names : Must include the following entries:
+  - spi
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -22,5 +24,7 @@ spi at 7000d600 {
 	spi-max-frequency = <25000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
+	clocks = <&tegra_car 44>;
+	clock-names = "spi";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
index 7b53da5cb75b..66e16c7f5939 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
@@ -6,6 +6,8 @@ Required properties:
 - interrupts: Should contain SFLASH interrupts.
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for this SFLASH controller.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -21,6 +23,6 @@ spi at 7000c380 {
 	spi-max-frequency = <25000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
+	clocks = <&tegra_car 43>;
 	status = "disabled";
 };
-
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
index eefe15e3d95e..0e6e94eb2b2a 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
@@ -6,6 +6,8 @@ Required properties:
 - interrupts: Should contain SLINK interrupts.
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for this SLINK controller.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -21,6 +23,6 @@ spi at 7000d600 {
 	spi-max-frequency = <25000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
+	clocks = <&tegra_car 44>;
 	status = "disabled";
 };
-
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
index e019fdc38773..4a864bd10d3d 100644
--- a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
@@ -8,6 +8,8 @@ Required properties:
 - compatible : should be "nvidia,tegra20-timer".
 - reg : Specifies base physical address and size of the registers.
 - interrupts : A list of 4 interrupts; one per timer channel.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Example:
 
@@ -18,4 +20,5 @@ timer {
 			0 1 0x04
 			0 41 0x04
 			0 42 0x04>;
+	clocks = <&tegra_car 132>;
 };
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
index 906109d4c593..b5082a1cf461 100644
--- a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
@@ -10,6 +10,8 @@ Required properties:
 - reg : Specifies base physical address and size of the registers.
 - interrupts : A list of 6 interrupts; one per each of timer channels 1
     through 5, and one for the shared interrupt for the remaining channels.
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 timer {
 	compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
@@ -20,4 +22,5 @@ timer {
 		      0 42 0x04
 		      0 121 0x04
 		      0 122 0x04>;
+	clocks = <&tegra_car 214>;
 };
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
index df0933043a5b..b98d0bdfa248 100644
--- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
@@ -8,7 +8,8 @@ and additions :
 Required properties :
  - compatible : Should be "nvidia,tegra20-ehci".
  - nvidia,phy : phandle of the PHY that the controller is connected to.
- - clocks : Contains a single entry which defines the USB controller's clock.
+ - clocks : Must contain one entry, for the module clock.
+   See ../clocks/clock-bindings.txt for details.
 
 Optional properties:
  - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20
-- 
1.8.1.5

Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Marc Dietrich]

Hi Stephen,

On Friday 15 November 2013 13:53:56 Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Many of the Tegra DT binding documents say nothing about the clocks or
> clock-names properties, yet those are present and required in DT files.
> This patch simply updates the documentation file to match the implicit
> definition of the binding, based on real-world DT content.
> 
> All Tegra bindings that mention clocks are updated to have consistent
> wording and formatting of the clock-related properties.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
> Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>  .../bindings/arm/tegra/nvidia,tegra20-pmc.txt      |  1 +
>  .../devicetree/bindings/dma/tegra20-apbdma.txt     |  3 ++
>  .../bindings/gpu/nvidia,tegra20-host1x.txt         | 61
> ++++++++++++++++++++++ .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt |
> 14 ++---
>  .../bindings/input/nvidia,tegra20-kbc.txt          |  3 ++
>  .../bindings/mmc/nvidia,tegra20-sdhci.txt          |  3 ++
>  .../devicetree/bindings/nvec/nvidia,nvec.txt       |  8 +++
>  .../bindings/pci/nvidia,tegra20-pcie.txt           | 16 +++---
>  .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt |  3 ++
>  .../devicetree/bindings/rtc/nvidia,tegra20-rtc.txt |  3 ++
>  .../bindings/serial/nvidia,tegra20-hsuart.txt      |  3 ++
>  .../bindings/sound/nvidia,tegra-audio-alc5632.txt  |  7 +--
>  .../bindings/sound/nvidia,tegra-audio-rt5640.txt   |  7 +--
>  .../bindings/sound/nvidia,tegra-audio-wm8753.txt   |  7 +--
>  .../bindings/sound/nvidia,tegra-audio-wm8903.txt   |  7 +--
>  .../bindings/sound/nvidia,tegra-audio-wm9712.txt   |  7 +--
>  .../bindings/sound/nvidia,tegra20-ac97.txt         |  4 ++
>  .../bindings/sound/nvidia,tegra20-i2s.txt          |  3 ++
>  .../bindings/sound/nvidia,tegra30-ahub.txt         | 21 ++++++--
>  .../bindings/sound/nvidia,tegra30-i2s.txt          |  5 +-
>  .../bindings/spi/nvidia,tegra114-spi.txt           |  8 ++-
>  .../bindings/spi/nvidia,tegra20-sflash.txt         |  4 +-
>  .../bindings/spi/nvidia,tegra20-slink.txt          |  4 +-
>  .../bindings/timer/nvidia,tegra20-timer.txt        |  3 ++
>  .../bindings/timer/nvidia,tegra30-timer.txt        |  3 ++
>  .../bindings/usb/nvidia,tegra20-ehci.txt           |  3 +-
>  26 files changed, 172 insertions(+), 39 deletions(-)
> 
> diff --git
> a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
> b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt index
> 1608a54e90e1..68ac65f82a1c 100644
> --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
> @@ -9,6 +9,7 @@ Required properties:
>  - compatible : Should contain "nvidia,tegra<chip>-pmc".
>  - reg : Offset and length of the register set for the device
>  - clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
>    "pclk" (The Tegra clock of that name),
>    "clk32k_in" (The 32KHz clock input to Tegra).
> diff --git a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt index
> 90fa7da525b8..74bfc54bb184 100644
> --- a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> +++ b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> @@ -5,6 +5,8 @@ Required properties:
>  - reg: Should contain DMA registers location and length. This shuld include
> all of the per-channel registers.
>  - interrupts: Should contain all of the per-channel DMA interrupts.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Examples:
> 
> @@ -27,4 +29,5 @@ apbdma: dma@6000a000 {
>  		       0 149 0x04
>  		       0 150 0x04
>  		       0 151 0x04 >;
> +	clocks = <&tegra_car 34>;
>  };
> diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt index
> b4fa934ae3a2..c9a715a75f60 100644
> --- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> +++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> @@ -9,6 +9,8 @@ Required properties:
>  - #size-cells: The number of cells used to represent the size of an address
> range in the host1x address space. Should be 1.
>  - ranges: The mapping of the host1x address space to the CPU address space.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  The host1x top-level node defines a number of children, each representing
> one of the following host1x client modules:
> @@ -19,6 +21,8 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-mpe"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> 
>  - vi: video input
> 
> @@ -26,6 +30,8 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-vi"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> 
>  - epp: encoder pre-processor
> 
> @@ -33,6 +39,8 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-epp"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> 
>  - isp: image signal processor
> 
> @@ -40,6 +48,8 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-isp"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> 
>  - gr2d: 2D graphics engine
> 
> @@ -47,12 +57,23 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-gr2d"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> 
>  - gr3d: 3D graphics engine
> 
>    Required properties:
>    - compatible: "nvidia,tegra<chip>-gr3d"
>    - reg: Physical base address and length of the controller's registers.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.

double clocks entry

> +  - clocks : Must contain an entry for each entry in clock-names.
> +    See ../clocks/clock-bindings.txt for details.
> +  - clock-names : Must include the following entries:
> +    (This property may be omitted if the only clock in the list is "3d")
> +    - 3d
> +      This MUST be the first entry.

why? isn't the purpose of names that the order is irrelevant?

> +    - 3d2 (Only required on SoCs with two 3D clocks)
> 
>  - dc: display controller
> 
> @@ -60,6 +81,12 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-dc"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain an entry for each entry in clock-names.
> +    See ../clocks/clock-bindings.txt for details.
> +  - clock-names : Must include the following entries:
> +    - disp1 or disp2 (depending on the controller instance)
> +      This MUST be the first entry.
> +    - parent
> 
>    Each display controller node has a child node, named "rgb", that
> represents the RGB output associated with the controller. It can take the
> following @@ -76,6 +103,12 @@ of the following host1x client modules:
>    - interrupts: The interrupt outputs from the controller.
>    - vdd-supply: regulator for supply voltage
>    - pll-supply: regulator for PLL
> +  - clocks : Must contain an entry for each entry in clock-names.
> +    See ../clocks/clock-bindings.txt for details.
> +  - clock-names : Must include the following entries:
> +    - hdmi
> +      This MUST be the first entry.
> +    - parent
> 
>    Optional properties:
>    - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID
> probing @@ -88,12 +121,22 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-tvo"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> 
>  - dsi: display serial interface
> 
>    Required properties:
>    - compatible: "nvidia,tegra<chip>-dsi"
>    - reg: Physical base address and length of the controller's registers.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.

double clocks entry

> +  - clocks : Must contain an entry for each entry in clock-names.
> +    See ../clocks/clock-bindings.txt for details.
> +  - clock-names : Must include the following entries:
> +    - dsi
> +      This MUST be the first entry.
> +    - parent

The clock-names property is marked as "required". So it should also been added 
to the examples below where it is required. Or is it "optional"?

>  Example:
> 
> @@ -105,6 +148,7 @@ Example:
>  		reg = <0x50000000 0x00024000>;
>  		interrupts = <0 65 0x04   /* mpcore syncpt */
>  			      0 67 0x04>; /* mpcore general */
> +		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
> 
>  		#address-cells = <1>;
>  		#size-cells = <1>;
> @@ -115,41 +159,50 @@ Example:
>  			compatible = "nvidia,tegra20-mpe";
>  			reg = <0x54040000 0x00040000>;
>  			interrupts = <0 68 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_MPE>;
>  		};
> 
>  		vi {
>  			compatible = "nvidia,tegra20-vi";
>  			reg = <0x54080000 0x00040000>;
>  			interrupts = <0 69 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_VI>;
>  		};
> 
>  		epp {
>  			compatible = "nvidia,tegra20-epp";
>  			reg = <0x540c0000 0x00040000>;
>  			interrupts = <0 70 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_EPP>;
>  		};
> 
>  		isp {
>  			compatible = "nvidia,tegra20-isp";
>  			reg = <0x54100000 0x00040000>;
>  			interrupts = <0 71 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_ISP>;
>  		};
> 
>  		gr2d {
>  			compatible = "nvidia,tegra20-gr2d";
>  			reg = <0x54140000 0x00040000>;
>  			interrupts = <0 72 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_GR2D>;
>  		};
> 
>  		gr3d {
>  			compatible = "nvidia,tegra20-gr3d";
>  			reg = <0x54180000 0x00040000>;
> +			clocks = <&tegra_car TEGRA20_CLK_GR3D>;
>  		};
> 
>  		dc@54200000 {
>  			compatible = "nvidia,tegra20-dc";
>  			reg = <0x54200000 0x00040000>;
>  			interrupts = <0 73 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
> +				 <&tegra_car TEGRA20_CLK_PLL_P>;
> +			clock-names = "disp1", "parent";
> 
>  			rgb {
>  				status = "disabled";
> @@ -160,6 +213,9 @@ Example:
>  			compatible = "nvidia,tegra20-dc";
>  			reg = <0x54240000 0x00040000>;
>  			interrupts = <0 74 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_DISP2>,
> +				 <&tegra_car TEGRA20_CLK_PLL_P>;
> +			clock-names = "disp2", "parent";
> 
>  			rgb {
>  				status = "disabled";
> @@ -170,6 +226,9 @@ Example:
>  			compatible = "nvidia,tegra20-hdmi";
>  			reg = <0x54280000 0x00040000>;
>  			interrupts = <0 75 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_HDMI>,
> +				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
> +			clock-names = "hdmi", "parent";
>  			status = "disabled";
>  		};
> 
> @@ -177,12 +236,14 @@ Example:
>  			compatible = "nvidia,tegra20-tvo";
>  			reg = <0x542c0000 0x00040000>;
>  			interrupts = <0 76 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_TVO>;
>  			status = "disabled";
>  		};
> 
>  		dsi {
>  			compatible = "nvidia,tegra20-dsi";
>  			reg = <0x54300000 0x00040000>;
> +			clocks = <&tegra_car TEGRA20_CLK_DSI>;
>  			status = "disabled";
>  		};
>  	};
> diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
> b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt index
> ef77cc7a0e46..96ab40131ae1 100644
> --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
> +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
> @@ -39,12 +39,14 @@ Required properties:
>  - interrupts: Should contain I2C controller interrupts.
>  - address-cells: Address cells for I2C device address.
>  - size-cells: Size of the I2C device address.
> -- clocks: Clock ID as per
> -		Documentation/devicetree/bindings/clock/tegra<chip-id>.txt
> -	for I2C controller.
> -- clock-names: Name of the clock:
> -	Tegra20/Tegra30 I2C controller: "div-clk and "fast-clk".
> -	Tegra114 I2C controller: "div-clk".
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
> +- clock-names : Must include the following entries:
> +  Tegra20/Tegra30:
> +  - div-clk
> +  - fast-clk
> +  Tegra114:
> +  - div-clk
> 
>  Example:
> 
> diff --git a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
> b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt index
> 2995fae7ee47..cc28d2194c37 100644
> --- a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
> +++ b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
> @@ -13,6 +13,8 @@ Required properties:
>    array of pin numbers which is used as column.
>  - linux,keymap: The keymap for keys as described in the binding document
>    devicetree/bindings/input/matrix-keymap.txt.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Optional properties, in addition to those specified by the shared
>  matrix-keyboard bindings:
> @@ -31,6 +33,7 @@ keyboard: keyboard {
>  	compatible = "nvidia,tegra20-kbc";
>  	reg = <0x7000e200 0x100>;
>  	interrupts = <0 85 0x04>;
> +	clocks = <&tegra_car 36>;
>  	nvidia,ghost-filter;
>  	nvidia,debounce-delay-ms = <640>;
>  	nvidia,kbc-row-pins = <0 1 2>;    /* pin 0, 1, 2 as rows */
> diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt index
> c6d7b11db9eb..f727902a9e8d 100644
> --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> @@ -8,6 +8,8 @@ by mmc.txt and the properties used by the sdhci-tegra
> driver.
> 
>  Required properties:
>  - compatible : Should be "nvidia,<chip>-sdhci"
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Optional properties:
>  - power-gpios : Specify GPIOs for power control
> @@ -18,6 +20,7 @@ sdhci@c8000200 {
>  	compatible = "nvidia,tegra20-sdhci";
>  	reg = <0xc8000200 0x200>;
>  	interrupts = <47>;
> +	clocks = <&tegra_car 14>;
>  	cd-gpios = <&gpio 69 0>; /* gpio PI5 */
>  	wp-gpios = <&gpio 57 0>; /* gpio PH1 */
>  	power-gpios = <&gpio 155 0>; /* gpio PT3 */
> diff --git a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
> b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt index
> 5aeee53ff9f4..a97fe575ca29 100644
> --- a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
> +++ b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
> @@ -7,3 +7,11 @@ Required properties:
>  - clock-frequency : the frequency of the i2c bus
>  - gpios : the gpio used for ec request
>  - slave-addr: the i2c address of the slave controller
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
> +- clock-names : Must include the following entries:
> +  Tegra20/Tegra30:
> +  - div-clk
> +  - fast-clk
> +  Tegra114:
> +  - div-clk
> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
> b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt index
> 6b7510775c50..ad2eb9804afa 100644
> --- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
> @@ -42,14 +42,14 @@ Required properties:
>      - 0xc2000000: prefetchable memory region
>    Please refer to the standard PCI bus binding document for a more detailed
> explanation.
> -- clocks: List of clock inputs of the controller. Must contain an entry for
> -  each entry in the clock-names property.
> -- clock-names: Must include the following entries:
> -  "pex": The Tegra clock of that name
> -  "afi": The Tegra clock of that name
> -  "pcie_xclk": The Tegra clock of that name
> -  "pll_e": The Tegra clock of that name
> -  "cml": The Tegra clock of that name (not required for Tegra20)
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
> +- clock-names : Must include the following entries:
> +  - pex
> +  - afi
> +  - pcie_xclk
> +  - pll_e
> +  - cml (not required for Tegra20)
> 
>  Root ports are defined as subnodes of the PCIe controller node.
> 
> diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt index
> c3fc57af8772..0d608d34fed0 100644
> --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> @@ -7,6 +7,8 @@ Required properties:
>  - reg: physical base address and length of the controller's registers
>  - #pwm-cells: should be 2. See pwm.txt in this directory for a description
> of the cells format.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Example:
> 
> @@ -14,4 +16,5 @@ Example:
>  		compatible = "nvidia,tegra20-pwm";
>  		reg = <0x7000a000 0x100>;
>  		#pwm-cells = <2>;
> +		clocks = <&tegra_car 17>;
>  	};
> diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
> b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt index
> 93f45e9dce7c..652d1ff2e8be 100644
> --- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
> +++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
> @@ -9,6 +9,8 @@ Required properties:
>  - compatible : should be "nvidia,tegra20-rtc".
>  - reg : Specifies base physical address and size of the registers.
>  - interrupts : A single interrupt specifier.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Example:
> 
> @@ -16,4 +18,5 @@ timer {
>  	compatible = "nvidia,tegra20-rtc";
>  	reg = <0x7000e000 0x100>;
>  	interrupts = <0 2 0x04>;
> +	clocks = <&tegra_car 4>;
>  };
> diff --git
> a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
> b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt index
> 392a4493eebd..39148b6236a1 100644
> --- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
> +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
> @@ -6,6 +6,8 @@ Required properties:
>  - interrupts: Should contain UART controller interrupts.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for this UART controller.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Optional properties:
>  - nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
> @@ -20,5 +22,6 @@ serial@70006000 {
>  	interrupts = <0 36 0x04>;
>  	nvidia,dma-request-selector = <&apbdma 8>;
>  	nvidia,enable-modem-interrupt;
> +	clocks = <&tegra_car 6>;
>  	status = "disabled";
>  };
> diff --git
> a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
> index 8b8903ef0800..57f40f93453e 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
> +++
> b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt @@
> -3,10 +3,11 @@ NVIDIA Tegra audio complex
>  Required properties:
>  - compatible : "nvidia,tegra-audio-alc5632"
>  - clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> -  "pll_a" (The Tegra clock of that name),
> -  "pll_a_out0" (The Tegra clock of that name),
> -  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
> +  - pll_a
> +  - pll_a_out0
> +  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
>  - nvidia,model : The user-visible name of this sound complex.
>  - nvidia,audio-routing : A list of the connections between audio
> components. Each entry is a pair of strings, the first being the
> connection's sink, diff --git
> a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
> index dc6224994d69..7788808dcd0b 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
> @@ -3,10 +3,11 @@ NVIDIA Tegra audio complex, with RT5640 CODEC
>  Required properties:
>  - compatible : "nvidia,tegra-audio-rt5640"
>  - clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> -  "pll_a" (The Tegra clock of that name),
> -  "pll_a_out0" (The Tegra clock of that name),
> -  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
> +  - pll_a
> +  - pll_a_out0
> +  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
>  - nvidia,model : The user-visible name of this sound complex.
>  - nvidia,audio-routing : A list of the connections between audio
> components. Each entry is a pair of strings, the first being the
> connection's sink, diff --git
> a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
> index aab6ce0ad2fc..96f6a57dd6b4 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
> @@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
>  Required properties:
>  - compatible : "nvidia,tegra-audio-wm8753"
>  - clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> -  "pll_a" (The Tegra clock of that name),
> -  "pll_a_out0" (The Tegra clock of that name),
> -  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
> +  - pll_a
> +  - pll_a_out0
> +  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
>  - nvidia,model : The user-visible name of this sound complex.
>  - nvidia,audio-routing : A list of the connections between audio
> components. Each entry is a pair of strings, the first being the
> connection's sink, diff --git
> a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
> index 4b44dfb6ca0d..b795d282818d 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
> @@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
>  Required properties:
>  - compatible : "nvidia,tegra-audio-wm8903"
>  - clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> -  "pll_a" (The Tegra clock of that name),
> -  "pll_a_out0" (The Tegra clock of that name),
> -  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
> +  - pll_a
> +  - pll_a_out0
> +  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
>  - nvidia,model : The user-visible name of this sound complex.
>  - nvidia,audio-routing : A list of the connections between audio
> components. Each entry is a pair of strings, the first being the
> connection's sink, diff --git
> a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
> index ad589b163639..436f6cd9d07c 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
> @@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
>  Required properties:
>  - compatible : "nvidia,tegra-audio-wm9712"
>  - clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> -  "pll_a" (The Tegra clock of that name),
> -  "pll_a_out0" (The Tegra clock of that name),
> -  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
> +  - pll_a
> +  - pll_a_out0
> +  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
>  - nvidia,model : The user-visible name of this sound complex.
>  - nvidia,audio-routing : A list of the connections between audio
> components. Each entry is a pair of strings, the first being the
> connection's sink, diff --git
> a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt index
> c1454979c1ef..37f4ebf5b184 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> @@ -4,12 +4,15 @@ Required properties:
>  - compatible : "nvidia,tegra20-ac97"
>  - reg : Should contain AC97 controller registers location and length
>  - interrupts : Should contain AC97 interrupt
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for the AC97 controller
>  - nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the
> number of the GPIO used to reset the external AC97 codec
>  - nvidia,codec-sync-gpio : The Tegra GPIO controller's phandle and the
> number of the GPIO corresponding with the AC97 DAP _FS line
> +
>  Example:
> 
>  ac97@70002000 {
> @@ -19,4 +22,5 @@ ac97@70002000 {
>  	nvidia,dma-request-selector = <&apbdma 12>;
>  	nvidia,codec-reset-gpio = <&gpio 170 0>;
>  	nvidia,codec-sync-gpio = <&gpio 120 0>;
> +	clocks = <&tegra_car 3>;
>  };
> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt index
> 0df2b5c816e3..ba0c9452916d 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
> @@ -4,6 +4,8 @@ Required properties:
>  - compatible : "nvidia,tegra20-i2s"
>  - reg : Should contain I2S registers location and length
>  - interrupts : Should contain I2S interrupt
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for this I2S controller
> 
> @@ -14,4 +16,5 @@ i2s@70002800 {
>  	reg = <0x70002800 0x200>;
>  	interrupts = < 45 >;
>  	nvidia,dma-request-selector = < &apbdma 2 >;
> +	clocks = <&tegra_car 11>;
>  };
> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt index
> 0e5c12c66523..7299eeadd588 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> @@ -12,11 +12,24 @@ Required properties:
>    If a single entry is present, the request selectors for the channels are
>    assumed to be contiguous, and increment from this value.
>    If multiple values are given, one value must be given per channel.
> -- clocks : Must contain an entry for each required entry in clock-names.
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> -  - Tegra30: Requires d_audio, apbif, i2s0, i2s1, i2s2, i2s3, i2s4, dam0,
> -    dam1, dam2, spdif_in.
> -  - Tegra114: Additionally requires amx, adx.
> +  Tegra30 and later:
> +  - d_audio
> +  - apbif
> +  - i2s0
> +  - i2s1
> +  - i2s2
> +  - i2s3
> +  - i2s4
> +  - dam0
> +  - dam1
> +  - dam2
> +  - spdif_in
> +  Tegra114 and later additionally require:
> +  - amx
> +  - adx
>  - ranges : The bus address mapping for the configlink register bus.
>    Can be empty since the mapping is 1:1.
>  - #address-cells : For the configlink bus. Should be <1>;
> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt index
> dfa6c037124a..7a3112bc135c 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
> @@ -3,13 +3,16 @@ NVIDIA Tegra30 I2S controller
>  Required properties:
>  - compatible : "nvidia,tegra30-i2s"
>  - reg : Should contain I2S registers location and length
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
>  - nvidia,ahub-cif-ids : The list of AHUB CIF IDs for this port, rx
> (playback) first, tx (capture) second. See nvidia,tegra30-ahub.txt for
> values.
> 
>  Example:
> 
> -i2s@70002800 {
> +i2s@70080300 {
>  	compatible = "nvidia,tegra30-i2s";
>  	reg = <0x70080300 0x100>;
>  	nvidia,ahub-cif-ids = <4 4>;
> +	clocks = <&tegra_car 11>;
>  };
> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt index
> 91ff771c7e77..d4f2d534934b 100644
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> @@ -6,8 +6,10 @@ Required properties:
>  - interrupts: Should contain SPI interrupts.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for this SPI controller.
> -- This is also require clock named "spi" as per binding document
> -  Documentation/devicetree/bindings/clock/clock-bindings.txt
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
> +- clock-names : Must include the following entries:
> +  - spi
> 
>  Recommended properties:
>  - spi-max-frequency: Definition as per
> @@ -22,5 +24,7 @@ spi@7000d600 {
>  	spi-max-frequency = <25000000>;
>  	#address-cells = <1>;
>  	#size-cells = <0>;
> +	clocks = <&tegra_car 44>;
> +	clock-names = "spi";
>  	status = "disabled";
>  };
> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt index
> 7b53da5cb75b..66e16c7f5939 100644
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> @@ -6,6 +6,8 @@ Required properties:
>  - interrupts: Should contain SFLASH interrupts.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for this SFLASH controller.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Recommended properties:
>  - spi-max-frequency: Definition as per
> @@ -21,6 +23,6 @@ spi@7000c380 {
>  	spi-max-frequency = <25000000>;
>  	#address-cells = <1>;
>  	#size-cells = <0>;
> +	clocks = <&tegra_car 43>;
>  	status = "disabled";
>  };
> -
> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
> b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt index
> eefe15e3d95e..0e6e94eb2b2a 100644
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
> @@ -6,6 +6,8 @@ Required properties:
>  - interrupts: Should contain SLINK interrupts.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for this SLINK controller.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Recommended properties:
>  - spi-max-frequency: Definition as per
> @@ -21,6 +23,6 @@ spi@7000d600 {
>  	spi-max-frequency = <25000000>;
>  	#address-cells = <1>;
>  	#size-cells = <0>;
> +	clocks = <&tegra_car 44>;
>  	status = "disabled";
>  };
> -
> diff --git
> a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
> b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt index
> e019fdc38773..4a864bd10d3d 100644
> --- a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
> +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
> @@ -8,6 +8,8 @@ Required properties:
>  - compatible : should be "nvidia,tegra20-timer".
>  - reg : Specifies base physical address and size of the registers.
>  - interrupts : A list of 4 interrupts; one per timer channel.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Example:
> 
> @@ -18,4 +20,5 @@ timer {
>  			0 1 0x04
>  			0 41 0x04
>  			0 42 0x04>;
> +	clocks = <&tegra_car 132>;
>  };
> diff --git
> a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
> b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt index
> 906109d4c593..b5082a1cf461 100644
> --- a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
> +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
> @@ -10,6 +10,8 @@ Required properties:
>  - reg : Specifies base physical address and size of the registers.
>  - interrupts : A list of 6 interrupts; one per each of timer channels 1
>      through 5, and one for the shared interrupt for the remaining channels.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  timer {
>  	compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
> @@ -20,4 +22,5 @@ timer {
>  		      0 42 0x04
>  		      0 121 0x04
>  		      0 122 0x04>;
> +	clocks = <&tegra_car 214>;
>  };
> diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
> b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt index
> df0933043a5b..b98d0bdfa248 100644
> --- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
> +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
> @@ -8,7 +8,8 @@ and additions :
>  Required properties :
>   - compatible : Should be "nvidia,tegra20-ehci".
>   - nvidia,phy : phandle of the PHY that the controller is connected to.
> - - clocks : Contains a single entry which defines the USB controller's
> clock. + - clocks : Must contain one entry, for the module clock.
> +   See ../clocks/clock-bindings.txt for details.
> 
>  Optional properties:
>   - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20
--
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[PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Marc Dietrich]

Hi Stephen,

On Friday 15 November 2013 13:53:56 Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Many of the Tegra DT binding documents say nothing about the clocks or
> clock-names properties, yet those are present and required in DT files.
> This patch simply updates the documentation file to match the implicit
> definition of the binding, based on real-world DT content.
> 
> All Tegra bindings that mention clocks are updated to have consistent
> wording and formatting of the clock-related properties.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Pawel Moll <pawel.moll@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
> Cc: devicetree at vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
>  .../bindings/arm/tegra/nvidia,tegra20-pmc.txt      |  1 +
>  .../devicetree/bindings/dma/tegra20-apbdma.txt     |  3 ++
>  .../bindings/gpu/nvidia,tegra20-host1x.txt         | 61
> ++++++++++++++++++++++ .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt |
> 14 ++---
>  .../bindings/input/nvidia,tegra20-kbc.txt          |  3 ++
>  .../bindings/mmc/nvidia,tegra20-sdhci.txt          |  3 ++
>  .../devicetree/bindings/nvec/nvidia,nvec.txt       |  8 +++
>  .../bindings/pci/nvidia,tegra20-pcie.txt           | 16 +++---
>  .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt |  3 ++
>  .../devicetree/bindings/rtc/nvidia,tegra20-rtc.txt |  3 ++
>  .../bindings/serial/nvidia,tegra20-hsuart.txt      |  3 ++
>  .../bindings/sound/nvidia,tegra-audio-alc5632.txt  |  7 +--
>  .../bindings/sound/nvidia,tegra-audio-rt5640.txt   |  7 +--
>  .../bindings/sound/nvidia,tegra-audio-wm8753.txt   |  7 +--
>  .../bindings/sound/nvidia,tegra-audio-wm8903.txt   |  7 +--
>  .../bindings/sound/nvidia,tegra-audio-wm9712.txt   |  7 +--
>  .../bindings/sound/nvidia,tegra20-ac97.txt         |  4 ++
>  .../bindings/sound/nvidia,tegra20-i2s.txt          |  3 ++
>  .../bindings/sound/nvidia,tegra30-ahub.txt         | 21 ++++++--
>  .../bindings/sound/nvidia,tegra30-i2s.txt          |  5 +-
>  .../bindings/spi/nvidia,tegra114-spi.txt           |  8 ++-
>  .../bindings/spi/nvidia,tegra20-sflash.txt         |  4 +-
>  .../bindings/spi/nvidia,tegra20-slink.txt          |  4 +-
>  .../bindings/timer/nvidia,tegra20-timer.txt        |  3 ++
>  .../bindings/timer/nvidia,tegra30-timer.txt        |  3 ++
>  .../bindings/usb/nvidia,tegra20-ehci.txt           |  3 +-
>  26 files changed, 172 insertions(+), 39 deletions(-)
> 
> diff --git
> a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
> b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt index
> 1608a54e90e1..68ac65f82a1c 100644
> --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
> @@ -9,6 +9,7 @@ Required properties:
>  - compatible : Should contain "nvidia,tegra<chip>-pmc".
>  - reg : Offset and length of the register set for the device
>  - clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
>    "pclk" (The Tegra clock of that name),
>    "clk32k_in" (The 32KHz clock input to Tegra).
> diff --git a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt index
> 90fa7da525b8..74bfc54bb184 100644
> --- a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> +++ b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> @@ -5,6 +5,8 @@ Required properties:
>  - reg: Should contain DMA registers location and length. This shuld include
> all of the per-channel registers.
>  - interrupts: Should contain all of the per-channel DMA interrupts.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Examples:
> 
> @@ -27,4 +29,5 @@ apbdma: dma at 6000a000 {
>  		       0 149 0x04
>  		       0 150 0x04
>  		       0 151 0x04 >;
> +	clocks = <&tegra_car 34>;
>  };
> diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt index
> b4fa934ae3a2..c9a715a75f60 100644
> --- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> +++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> @@ -9,6 +9,8 @@ Required properties:
>  - #size-cells: The number of cells used to represent the size of an address
> range in the host1x address space. Should be 1.
>  - ranges: The mapping of the host1x address space to the CPU address space.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  The host1x top-level node defines a number of children, each representing
> one of the following host1x client modules:
> @@ -19,6 +21,8 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-mpe"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> 
>  - vi: video input
> 
> @@ -26,6 +30,8 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-vi"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> 
>  - epp: encoder pre-processor
> 
> @@ -33,6 +39,8 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-epp"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> 
>  - isp: image signal processor
> 
> @@ -40,6 +48,8 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-isp"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> 
>  - gr2d: 2D graphics engine
> 
> @@ -47,12 +57,23 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-gr2d"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> 
>  - gr3d: 3D graphics engine
> 
>    Required properties:
>    - compatible: "nvidia,tegra<chip>-gr3d"
>    - reg: Physical base address and length of the controller's registers.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.

double clocks entry

> +  - clocks : Must contain an entry for each entry in clock-names.
> +    See ../clocks/clock-bindings.txt for details.
> +  - clock-names : Must include the following entries:
> +    (This property may be omitted if the only clock in the list is "3d")
> +    - 3d
> +      This MUST be the first entry.

why? isn't the purpose of names that the order is irrelevant?

> +    - 3d2 (Only required on SoCs with two 3D clocks)
> 
>  - dc: display controller
> 
> @@ -60,6 +81,12 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-dc"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain an entry for each entry in clock-names.
> +    See ../clocks/clock-bindings.txt for details.
> +  - clock-names : Must include the following entries:
> +    - disp1 or disp2 (depending on the controller instance)
> +      This MUST be the first entry.
> +    - parent
> 
>    Each display controller node has a child node, named "rgb", that
> represents the RGB output associated with the controller. It can take the
> following @@ -76,6 +103,12 @@ of the following host1x client modules:
>    - interrupts: The interrupt outputs from the controller.
>    - vdd-supply: regulator for supply voltage
>    - pll-supply: regulator for PLL
> +  - clocks : Must contain an entry for each entry in clock-names.
> +    See ../clocks/clock-bindings.txt for details.
> +  - clock-names : Must include the following entries:
> +    - hdmi
> +      This MUST be the first entry.
> +    - parent
> 
>    Optional properties:
>    - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID
> probing @@ -88,12 +121,22 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-tvo"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> 
>  - dsi: display serial interface
> 
>    Required properties:
>    - compatible: "nvidia,tegra<chip>-dsi"
>    - reg: Physical base address and length of the controller's registers.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.

double clocks entry

> +  - clocks : Must contain an entry for each entry in clock-names.
> +    See ../clocks/clock-bindings.txt for details.
> +  - clock-names : Must include the following entries:
> +    - dsi
> +      This MUST be the first entry.
> +    - parent

The clock-names property is marked as "required". So it should also been added 
to the examples below where it is required. Or is it "optional"?

>  Example:
> 
> @@ -105,6 +148,7 @@ Example:
>  		reg = <0x50000000 0x00024000>;
>  		interrupts = <0 65 0x04   /* mpcore syncpt */
>  			      0 67 0x04>; /* mpcore general */
> +		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
> 
>  		#address-cells = <1>;
>  		#size-cells = <1>;
> @@ -115,41 +159,50 @@ Example:
>  			compatible = "nvidia,tegra20-mpe";
>  			reg = <0x54040000 0x00040000>;
>  			interrupts = <0 68 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_MPE>;
>  		};
> 
>  		vi {
>  			compatible = "nvidia,tegra20-vi";
>  			reg = <0x54080000 0x00040000>;
>  			interrupts = <0 69 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_VI>;
>  		};
> 
>  		epp {
>  			compatible = "nvidia,tegra20-epp";
>  			reg = <0x540c0000 0x00040000>;
>  			interrupts = <0 70 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_EPP>;
>  		};
> 
>  		isp {
>  			compatible = "nvidia,tegra20-isp";
>  			reg = <0x54100000 0x00040000>;
>  			interrupts = <0 71 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_ISP>;
>  		};
> 
>  		gr2d {
>  			compatible = "nvidia,tegra20-gr2d";
>  			reg = <0x54140000 0x00040000>;
>  			interrupts = <0 72 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_GR2D>;
>  		};
> 
>  		gr3d {
>  			compatible = "nvidia,tegra20-gr3d";
>  			reg = <0x54180000 0x00040000>;
> +			clocks = <&tegra_car TEGRA20_CLK_GR3D>;
>  		};
> 
>  		dc at 54200000 {
>  			compatible = "nvidia,tegra20-dc";
>  			reg = <0x54200000 0x00040000>;
>  			interrupts = <0 73 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
> +				 <&tegra_car TEGRA20_CLK_PLL_P>;
> +			clock-names = "disp1", "parent";
> 
>  			rgb {
>  				status = "disabled";
> @@ -160,6 +213,9 @@ Example:
>  			compatible = "nvidia,tegra20-dc";
>  			reg = <0x54240000 0x00040000>;
>  			interrupts = <0 74 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_DISP2>,
> +				 <&tegra_car TEGRA20_CLK_PLL_P>;
> +			clock-names = "disp2", "parent";
> 
>  			rgb {
>  				status = "disabled";
> @@ -170,6 +226,9 @@ Example:
>  			compatible = "nvidia,tegra20-hdmi";
>  			reg = <0x54280000 0x00040000>;
>  			interrupts = <0 75 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_HDMI>,
> +				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
> +			clock-names = "hdmi", "parent";
>  			status = "disabled";
>  		};
> 
> @@ -177,12 +236,14 @@ Example:
>  			compatible = "nvidia,tegra20-tvo";
>  			reg = <0x542c0000 0x00040000>;
>  			interrupts = <0 76 0x04>;
> +			clocks = <&tegra_car TEGRA20_CLK_TVO>;
>  			status = "disabled";
>  		};
> 
>  		dsi {
>  			compatible = "nvidia,tegra20-dsi";
>  			reg = <0x54300000 0x00040000>;
> +			clocks = <&tegra_car TEGRA20_CLK_DSI>;
>  			status = "disabled";
>  		};
>  	};
> diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
> b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt index
> ef77cc7a0e46..96ab40131ae1 100644
> --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
> +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
> @@ -39,12 +39,14 @@ Required properties:
>  - interrupts: Should contain I2C controller interrupts.
>  - address-cells: Address cells for I2C device address.
>  - size-cells: Size of the I2C device address.
> -- clocks: Clock ID as per
> -		Documentation/devicetree/bindings/clock/tegra<chip-id>.txt
> -	for I2C controller.
> -- clock-names: Name of the clock:
> -	Tegra20/Tegra30 I2C controller: "div-clk and "fast-clk".
> -	Tegra114 I2C controller: "div-clk".
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
> +- clock-names : Must include the following entries:
> +  Tegra20/Tegra30:
> +  - div-clk
> +  - fast-clk
> +  Tegra114:
> +  - div-clk
> 
>  Example:
> 
> diff --git a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
> b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt index
> 2995fae7ee47..cc28d2194c37 100644
> --- a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
> +++ b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
> @@ -13,6 +13,8 @@ Required properties:
>    array of pin numbers which is used as column.
>  - linux,keymap: The keymap for keys as described in the binding document
>    devicetree/bindings/input/matrix-keymap.txt.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Optional properties, in addition to those specified by the shared
>  matrix-keyboard bindings:
> @@ -31,6 +33,7 @@ keyboard: keyboard {
>  	compatible = "nvidia,tegra20-kbc";
>  	reg = <0x7000e200 0x100>;
>  	interrupts = <0 85 0x04>;
> +	clocks = <&tegra_car 36>;
>  	nvidia,ghost-filter;
>  	nvidia,debounce-delay-ms = <640>;
>  	nvidia,kbc-row-pins = <0 1 2>;    /* pin 0, 1, 2 as rows */
> diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt index
> c6d7b11db9eb..f727902a9e8d 100644
> --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> @@ -8,6 +8,8 @@ by mmc.txt and the properties used by the sdhci-tegra
> driver.
> 
>  Required properties:
>  - compatible : Should be "nvidia,<chip>-sdhci"
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Optional properties:
>  - power-gpios : Specify GPIOs for power control
> @@ -18,6 +20,7 @@ sdhci at c8000200 {
>  	compatible = "nvidia,tegra20-sdhci";
>  	reg = <0xc8000200 0x200>;
>  	interrupts = <47>;
> +	clocks = <&tegra_car 14>;
>  	cd-gpios = <&gpio 69 0>; /* gpio PI5 */
>  	wp-gpios = <&gpio 57 0>; /* gpio PH1 */
>  	power-gpios = <&gpio 155 0>; /* gpio PT3 */
> diff --git a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
> b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt index
> 5aeee53ff9f4..a97fe575ca29 100644
> --- a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
> +++ b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
> @@ -7,3 +7,11 @@ Required properties:
>  - clock-frequency : the frequency of the i2c bus
>  - gpios : the gpio used for ec request
>  - slave-addr: the i2c address of the slave controller
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
> +- clock-names : Must include the following entries:
> +  Tegra20/Tegra30:
> +  - div-clk
> +  - fast-clk
> +  Tegra114:
> +  - div-clk
> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
> b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt index
> 6b7510775c50..ad2eb9804afa 100644
> --- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
> @@ -42,14 +42,14 @@ Required properties:
>      - 0xc2000000: prefetchable memory region
>    Please refer to the standard PCI bus binding document for a more detailed
> explanation.
> -- clocks: List of clock inputs of the controller. Must contain an entry for
> -  each entry in the clock-names property.
> -- clock-names: Must include the following entries:
> -  "pex": The Tegra clock of that name
> -  "afi": The Tegra clock of that name
> -  "pcie_xclk": The Tegra clock of that name
> -  "pll_e": The Tegra clock of that name
> -  "cml": The Tegra clock of that name (not required for Tegra20)
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
> +- clock-names : Must include the following entries:
> +  - pex
> +  - afi
> +  - pcie_xclk
> +  - pll_e
> +  - cml (not required for Tegra20)
> 
>  Root ports are defined as subnodes of the PCIe controller node.
> 
> diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt index
> c3fc57af8772..0d608d34fed0 100644
> --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> @@ -7,6 +7,8 @@ Required properties:
>  - reg: physical base address and length of the controller's registers
>  - #pwm-cells: should be 2. See pwm.txt in this directory for a description
> of the cells format.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Example:
> 
> @@ -14,4 +16,5 @@ Example:
>  		compatible = "nvidia,tegra20-pwm";
>  		reg = <0x7000a000 0x100>;
>  		#pwm-cells = <2>;
> +		clocks = <&tegra_car 17>;
>  	};
> diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
> b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt index
> 93f45e9dce7c..652d1ff2e8be 100644
> --- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
> +++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
> @@ -9,6 +9,8 @@ Required properties:
>  - compatible : should be "nvidia,tegra20-rtc".
>  - reg : Specifies base physical address and size of the registers.
>  - interrupts : A single interrupt specifier.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Example:
> 
> @@ -16,4 +18,5 @@ timer {
>  	compatible = "nvidia,tegra20-rtc";
>  	reg = <0x7000e000 0x100>;
>  	interrupts = <0 2 0x04>;
> +	clocks = <&tegra_car 4>;
>  };
> diff --git
> a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
> b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt index
> 392a4493eebd..39148b6236a1 100644
> --- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
> +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
> @@ -6,6 +6,8 @@ Required properties:
>  - interrupts: Should contain UART controller interrupts.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for this UART controller.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Optional properties:
>  - nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
> @@ -20,5 +22,6 @@ serial at 70006000 {
>  	interrupts = <0 36 0x04>;
>  	nvidia,dma-request-selector = <&apbdma 8>;
>  	nvidia,enable-modem-interrupt;
> +	clocks = <&tegra_car 6>;
>  	status = "disabled";
>  };
> diff --git
> a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
> index 8b8903ef0800..57f40f93453e 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
> +++
> b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt @@
> -3,10 +3,11 @@ NVIDIA Tegra audio complex
>  Required properties:
>  - compatible : "nvidia,tegra-audio-alc5632"
>  - clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> -  "pll_a" (The Tegra clock of that name),
> -  "pll_a_out0" (The Tegra clock of that name),
> -  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
> +  - pll_a
> +  - pll_a_out0
> +  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
>  - nvidia,model : The user-visible name of this sound complex.
>  - nvidia,audio-routing : A list of the connections between audio
> components. Each entry is a pair of strings, the first being the
> connection's sink, diff --git
> a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
> index dc6224994d69..7788808dcd0b 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
> @@ -3,10 +3,11 @@ NVIDIA Tegra audio complex, with RT5640 CODEC
>  Required properties:
>  - compatible : "nvidia,tegra-audio-rt5640"
>  - clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> -  "pll_a" (The Tegra clock of that name),
> -  "pll_a_out0" (The Tegra clock of that name),
> -  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
> +  - pll_a
> +  - pll_a_out0
> +  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
>  - nvidia,model : The user-visible name of this sound complex.
>  - nvidia,audio-routing : A list of the connections between audio
> components. Each entry is a pair of strings, the first being the
> connection's sink, diff --git
> a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
> index aab6ce0ad2fc..96f6a57dd6b4 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
> @@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
>  Required properties:
>  - compatible : "nvidia,tegra-audio-wm8753"
>  - clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> -  "pll_a" (The Tegra clock of that name),
> -  "pll_a_out0" (The Tegra clock of that name),
> -  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
> +  - pll_a
> +  - pll_a_out0
> +  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
>  - nvidia,model : The user-visible name of this sound complex.
>  - nvidia,audio-routing : A list of the connections between audio
> components. Each entry is a pair of strings, the first being the
> connection's sink, diff --git
> a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
> index 4b44dfb6ca0d..b795d282818d 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
> @@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
>  Required properties:
>  - compatible : "nvidia,tegra-audio-wm8903"
>  - clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> -  "pll_a" (The Tegra clock of that name),
> -  "pll_a_out0" (The Tegra clock of that name),
> -  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
> +  - pll_a
> +  - pll_a_out0
> +  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
>  - nvidia,model : The user-visible name of this sound complex.
>  - nvidia,audio-routing : A list of the connections between audio
> components. Each entry is a pair of strings, the first being the
> connection's sink, diff --git
> a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
> index ad589b163639..436f6cd9d07c 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
> @@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
>  Required properties:
>  - compatible : "nvidia,tegra-audio-wm9712"
>  - clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> -  "pll_a" (The Tegra clock of that name),
> -  "pll_a_out0" (The Tegra clock of that name),
> -  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
> +  - pll_a
> +  - pll_a_out0
> +  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
>  - nvidia,model : The user-visible name of this sound complex.
>  - nvidia,audio-routing : A list of the connections between audio
> components. Each entry is a pair of strings, the first being the
> connection's sink, diff --git
> a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt index
> c1454979c1ef..37f4ebf5b184 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> @@ -4,12 +4,15 @@ Required properties:
>  - compatible : "nvidia,tegra20-ac97"
>  - reg : Should contain AC97 controller registers location and length
>  - interrupts : Should contain AC97 interrupt
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for the AC97 controller
>  - nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the
> number of the GPIO used to reset the external AC97 codec
>  - nvidia,codec-sync-gpio : The Tegra GPIO controller's phandle and the
> number of the GPIO corresponding with the AC97 DAP _FS line
> +
>  Example:
> 
>  ac97 at 70002000 {
> @@ -19,4 +22,5 @@ ac97 at 70002000 {
>  	nvidia,dma-request-selector = <&apbdma 12>;
>  	nvidia,codec-reset-gpio = <&gpio 170 0>;
>  	nvidia,codec-sync-gpio = <&gpio 120 0>;
> +	clocks = <&tegra_car 3>;
>  };
> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt index
> 0df2b5c816e3..ba0c9452916d 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
> @@ -4,6 +4,8 @@ Required properties:
>  - compatible : "nvidia,tegra20-i2s"
>  - reg : Should contain I2S registers location and length
>  - interrupts : Should contain I2S interrupt
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for this I2S controller
> 
> @@ -14,4 +16,5 @@ i2s at 70002800 {
>  	reg = <0x70002800 0x200>;
>  	interrupts = < 45 >;
>  	nvidia,dma-request-selector = < &apbdma 2 >;
> +	clocks = <&tegra_car 11>;
>  };
> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt index
> 0e5c12c66523..7299eeadd588 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> @@ -12,11 +12,24 @@ Required properties:
>    If a single entry is present, the request selectors for the channels are
>    assumed to be contiguous, and increment from this value.
>    If multiple values are given, one value must be given per channel.
> -- clocks : Must contain an entry for each required entry in clock-names.
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> -  - Tegra30: Requires d_audio, apbif, i2s0, i2s1, i2s2, i2s3, i2s4, dam0,
> -    dam1, dam2, spdif_in.
> -  - Tegra114: Additionally requires amx, adx.
> +  Tegra30 and later:
> +  - d_audio
> +  - apbif
> +  - i2s0
> +  - i2s1
> +  - i2s2
> +  - i2s3
> +  - i2s4
> +  - dam0
> +  - dam1
> +  - dam2
> +  - spdif_in
> +  Tegra114 and later additionally require:
> +  - amx
> +  - adx
>  - ranges : The bus address mapping for the configlink register bus.
>    Can be empty since the mapping is 1:1.
>  - #address-cells : For the configlink bus. Should be <1>;
> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
> b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt index
> dfa6c037124a..7a3112bc135c 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
> @@ -3,13 +3,16 @@ NVIDIA Tegra30 I2S controller
>  Required properties:
>  - compatible : "nvidia,tegra30-i2s"
>  - reg : Should contain I2S registers location and length
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
>  - nvidia,ahub-cif-ids : The list of AHUB CIF IDs for this port, rx
> (playback) first, tx (capture) second. See nvidia,tegra30-ahub.txt for
> values.
> 
>  Example:
> 
> -i2s at 70002800 {
> +i2s at 70080300 {
>  	compatible = "nvidia,tegra30-i2s";
>  	reg = <0x70080300 0x100>;
>  	nvidia,ahub-cif-ids = <4 4>;
> +	clocks = <&tegra_car 11>;
>  };
> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt index
> 91ff771c7e77..d4f2d534934b 100644
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> @@ -6,8 +6,10 @@ Required properties:
>  - interrupts: Should contain SPI interrupts.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for this SPI controller.
> -- This is also require clock named "spi" as per binding document
> -  Documentation/devicetree/bindings/clock/clock-bindings.txt
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
> +- clock-names : Must include the following entries:
> +  - spi
> 
>  Recommended properties:
>  - spi-max-frequency: Definition as per
> @@ -22,5 +24,7 @@ spi at 7000d600 {
>  	spi-max-frequency = <25000000>;
>  	#address-cells = <1>;
>  	#size-cells = <0>;
> +	clocks = <&tegra_car 44>;
> +	clock-names = "spi";
>  	status = "disabled";
>  };
> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt index
> 7b53da5cb75b..66e16c7f5939 100644
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> @@ -6,6 +6,8 @@ Required properties:
>  - interrupts: Should contain SFLASH interrupts.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for this SFLASH controller.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Recommended properties:
>  - spi-max-frequency: Definition as per
> @@ -21,6 +23,6 @@ spi at 7000c380 {
>  	spi-max-frequency = <25000000>;
>  	#address-cells = <1>;
>  	#size-cells = <0>;
> +	clocks = <&tegra_car 43>;
>  	status = "disabled";
>  };
> -
> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
> b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt index
> eefe15e3d95e..0e6e94eb2b2a 100644
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
> @@ -6,6 +6,8 @@ Required properties:
>  - interrupts: Should contain SLINK interrupts.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for this SLINK controller.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Recommended properties:
>  - spi-max-frequency: Definition as per
> @@ -21,6 +23,6 @@ spi at 7000d600 {
>  	spi-max-frequency = <25000000>;
>  	#address-cells = <1>;
>  	#size-cells = <0>;
> +	clocks = <&tegra_car 44>;
>  	status = "disabled";
>  };
> -
> diff --git
> a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
> b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt index
> e019fdc38773..4a864bd10d3d 100644
> --- a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
> +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
> @@ -8,6 +8,8 @@ Required properties:
>  - compatible : should be "nvidia,tegra20-timer".
>  - reg : Specifies base physical address and size of the registers.
>  - interrupts : A list of 4 interrupts; one per timer channel.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  Example:
> 
> @@ -18,4 +20,5 @@ timer {
>  			0 1 0x04
>  			0 41 0x04
>  			0 42 0x04>;
> +	clocks = <&tegra_car 132>;
>  };
> diff --git
> a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
> b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt index
> 906109d4c593..b5082a1cf461 100644
> --- a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
> +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
> @@ -10,6 +10,8 @@ Required properties:
>  - reg : Specifies base physical address and size of the registers.
>  - interrupts : A list of 6 interrupts; one per each of timer channels 1
>      through 5, and one for the shared interrupt for the remaining channels.
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.
> 
>  timer {
>  	compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
> @@ -20,4 +22,5 @@ timer {
>  		      0 42 0x04
>  		      0 121 0x04
>  		      0 122 0x04>;
> +	clocks = <&tegra_car 214>;
>  };
> diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
> b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt index
> df0933043a5b..b98d0bdfa248 100644
> --- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
> +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
> @@ -8,7 +8,8 @@ and additions :
>  Required properties :
>   - compatible : Should be "nvidia,tegra20-ehci".
>   - nvidia,phy : phandle of the PHY that the controller is connected to.
> - - clocks : Contains a single entry which defines the USB controller's
> clock. + - clocks : Must contain one entry, for the module clock.
> +   See ../clocks/clock-bindings.txt for details.
> 
>  Optional properties:
>   - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20

Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Stephen Warren]

On 11/16/2013 03:00 PM, Marc Dietrich wrote:
> Hi Stephen,
> 
> On Friday 15 November 2013 13:53:56 Stephen Warren wrote:
>> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
>> Many of the Tegra DT binding documents say nothing about the clocks or
>> clock-names properties, yet those are present and required in DT files.
>> This patch simply updates the documentation file to match the implicit
>> definition of the binding, based on real-world DT content.
>>
>> All Tegra bindings that mention clocks are updated to have consistent
>> wording and formatting of the clock-related properties.

>> diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt

(Thanks for pointing out the duplicate entries; I'll fix those.)

>> +  - clocks : Must contain an entry for each entry in clock-names.
>> +    See ../clocks/clock-bindings.txt for details.
>> +  - clock-names : Must include the following entries:
>> +    (This property may be omitted if the only clock in the list is "3d")
>> +    - 3d
>> +      This MUST be the first entry.
> 
> why? isn't the purpose of names that the order is irrelevant?

If we used names from the start, then the order would be irrelevant.

However, this binding didn't use names from the start, and hence the
order of appearance in "clocks" is part of the original binding.
"clock-names" only became part of the binding when the second clock was
introduced.

We can either: (a) document the existing requirements as I have done, or
(b) go through all the bindings and drivers and make potentially
incompatible changes so that all ordering is purely defined by
"clock-names". I was tempted to do (b) for cleanliness, but didn't want
to push my luck on too many ABI-incompatible changes. (b) /might/ also
affect more drivers than this series already does, thus bloating it even
more:-(

P.S. only quoting the parts of the patch you're replying to makes it a
lot easier and quicker to find your replies.

[PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Stephen Warren]

On 11/16/2013 03:00 PM, Marc Dietrich wrote:
> Hi Stephen,
> 
> On Friday 15 November 2013 13:53:56 Stephen Warren wrote:
>> From: Stephen Warren <swarren@nvidia.com>
>>
>> Many of the Tegra DT binding documents say nothing about the clocks or
>> clock-names properties, yet those are present and required in DT files.
>> This patch simply updates the documentation file to match the implicit
>> definition of the binding, based on real-world DT content.
>>
>> All Tegra bindings that mention clocks are updated to have consistent
>> wording and formatting of the clock-related properties.

>> diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt

(Thanks for pointing out the duplicate entries; I'll fix those.)

>> +  - clocks : Must contain an entry for each entry in clock-names.
>> +    See ../clocks/clock-bindings.txt for details.
>> +  - clock-names : Must include the following entries:
>> +    (This property may be omitted if the only clock in the list is "3d")
>> +    - 3d
>> +      This MUST be the first entry.
> 
> why? isn't the purpose of names that the order is irrelevant?

If we used names from the start, then the order would be irrelevant.

However, this binding didn't use names from the start, and hence the
order of appearance in "clocks" is part of the original binding.
"clock-names" only became part of the binding when the second clock was
introduced.

We can either: (a) document the existing requirements as I have done, or
(b) go through all the bindings and drivers and make potentially
incompatible changes so that all ordering is purely defined by
"clock-names". I was tempted to do (b) for cleanliness, but didn't want
to push my luck on too many ABI-incompatible changes. (b) /might/ also
affect more drivers than this series already does, thus bloating it even
more:-(

P.S. only quoting the parts of the patch you're replying to makes it a
lot easier and quicker to find your replies.

Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 2855 bytes --]

On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote:
[...]
> @@ -60,6 +81,12 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-dc"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain an entry for each entry in clock-names.
> +    See ../clocks/clock-bindings.txt for details.
> +  - clock-names : Must include the following entries:
> +    - disp1 or disp2 (depending on the controller instance)

I'm not sure if this makes sense. The name could be the same independent
of which controller uses it. If it isn't then the driver would need
additional code to find out which instance it is and construct a dynamic
string.

Any objection to just make this entry "disp", or "dc"?

>  - dsi: display serial interface
>  
>    Required properties:
>    - compatible: "nvidia,tegra<chip>-dsi"
>    - reg: Physical base address and length of the controller's registers.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> +  - clocks : Must contain an entry for each entry in clock-names.
> +    See ../clocks/clock-bindings.txt for details.

There's another duplicate clocks entry here, although perhaps Marc
already caught that.

> +  - clock-names : Must include the following entries:

One other thing I noticed here is that you use a space between the
property name and the :. None of the other properties have that, so it
looks somewhat out of place. The same is true for other bindings, but
there seem to be inconsistencies in some places anyway, so perhaps we
don't care? Well, I do care, don't know about you. =)

> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> index 91ff771c7e77..d4f2d534934b 100644
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> @@ -6,8 +6,10 @@ Required properties:
>  - interrupts: Should contain SPI interrupts.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for this SPI controller.
> -- This is also require clock named "spi" as per binding document
> -  Documentation/devicetree/bindings/clock/clock-bindings.txt
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
> +- clock-names : Must include the following entries:
> +  - spi

This is inconsistent with other bindings that require only a single
clock entry. I suppose that this is required because of the driver
requesting a specifically named clock, in which case that's fine.

Thierry

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[PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote:
[...]
> @@ -60,6 +81,12 @@ of the following host1x client modules:
>    - compatible: "nvidia,tegra<chip>-dc"
>    - reg: Physical base address and length of the controller's registers.
>    - interrupts: The interrupt outputs from the controller.
> +  - clocks : Must contain an entry for each entry in clock-names.
> +    See ../clocks/clock-bindings.txt for details.
> +  - clock-names : Must include the following entries:
> +    - disp1 or disp2 (depending on the controller instance)

I'm not sure if this makes sense. The name could be the same independent
of which controller uses it. If it isn't then the driver would need
additional code to find out which instance it is and construct a dynamic
string.

Any objection to just make this entry "disp", or "dc"?

>  - dsi: display serial interface
>  
>    Required properties:
>    - compatible: "nvidia,tegra<chip>-dsi"
>    - reg: Physical base address and length of the controller's registers.
> +  - clocks : Must contain one entry, for the module clock.
> +    See ../clocks/clock-bindings.txt for details.
> +  - clocks : Must contain an entry for each entry in clock-names.
> +    See ../clocks/clock-bindings.txt for details.

There's another duplicate clocks entry here, although perhaps Marc
already caught that.

> +  - clock-names : Must include the following entries:

One other thing I noticed here is that you use a space between the
property name and the :. None of the other properties have that, so it
looks somewhat out of place. The same is true for other bindings, but
there seem to be inconsistencies in some places anyway, so perhaps we
don't care? Well, I do care, don't know about you. =)

> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> index 91ff771c7e77..d4f2d534934b 100644
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> @@ -6,8 +6,10 @@ Required properties:
>  - interrupts: Should contain SPI interrupts.
>  - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
>    request selector for this SPI controller.
> -- This is also require clock named "spi" as per binding document
> -  Documentation/devicetree/bindings/clock/clock-bindings.txt
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
> +- clock-names : Must include the following entries:
> +  - spi

This is inconsistent with other bindings that require only a single
clock entry. I suppose that this is required because of the driver
requesting a specifically named clock, in which case that's fine.

Thierry
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Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Stephen Warren]

On 11/29/2013 04:49 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote: 
> [...]
>> @@ -60,6 +81,12 @@ of the following host1x client modules: -
>> compatible: "nvidia,tegra<chip>-dc" - reg: Physical base address
>> and length of the controller's registers. - interrupts: The
>> interrupt outputs from the controller. +  - clocks : Must contain
>> an entry for each entry in clock-names. +    See
>> ../clocks/clock-bindings.txt for details. +  - clock-names : Must
>> include the following entries: +    - disp1 or disp2 (depending
>> on the controller instance)
> 
> I'm not sure if this makes sense. The name could be the same
> independent of which controller uses it. If it isn't then the
> driver would need additional code to find out which instance it is
> and construct a dynamic string.
> 
> Any objection to just make this entry "disp", or "dc"?

This patch simply documents the binding that the various drivers
already require and/or whatever is already in the DT files if there
are any clocks the drivers don't currently use. I did consider fixing
up all the current usage to actually be sane, but that would require
even more driver changes (in addition to those required for the reset
framework patches).

>> +  - clock-names : Must include the following entries:
> 
> One other thing I noticed here is that you use a space between the 
> property name and the :. None of the other properties have that, so
> it looks somewhat out of place. The same is true for other
> bindings, but there seem to be inconsistencies in some places
> anyway, so perhaps we don't care? Well, I do care, don't know about
> you. =)

Yes, I simply cut/paste the clock docs from one binding into the other
to make sure the wording was consistent. I guess I need to go through
and adjust the pasted format to match the various bindings. It's a
pity they're plain-text not a schema, so there is no consistency here:-(

>> diff --git
>> a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
>> b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt 
>> index 91ff771c7e77..d4f2d534934b 100644 ---
>> a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt 
>> +++
>> b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt 
>> @@ -6,8 +6,10 @@ Required properties: - interrupts: Should
>> contain SPI interrupts. - nvidia,dma-request-selector : The Tegra
>> DMA controller's phandle and request selector for this SPI
>> controller. -- This is also require clock named "spi" as per
>> binding document -
>> Documentation/devicetree/bindings/clock/clock-bindings.txt +-
>> clocks : Must contain an entry for each entry in clock-names. +
>> See ../clocks/clock-bindings.txt for details. +- clock-names :
>> Must include the following entries: +  - spi
> 
> This is inconsistent with other bindings that require only a
> single clock entry. I suppose that this is required because of the
> driver requesting a specifically named clock, in which case that's
> fine.

This driver does clk_get(dev, "spi") rather than clk_get(dev, NULL),
so this requires a specific name. Again, I did consider updating all
drivers to use names, but decided I didn't want to do even more driver
changes, but instead just document what was currently required.

[PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Stephen Warren]

On 11/29/2013 04:49 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote: 
> [...]
>> @@ -60,6 +81,12 @@ of the following host1x client modules: -
>> compatible: "nvidia,tegra<chip>-dc" - reg: Physical base address
>> and length of the controller's registers. - interrupts: The
>> interrupt outputs from the controller. +  - clocks : Must contain
>> an entry for each entry in clock-names. +    See
>> ../clocks/clock-bindings.txt for details. +  - clock-names : Must
>> include the following entries: +    - disp1 or disp2 (depending
>> on the controller instance)
> 
> I'm not sure if this makes sense. The name could be the same
> independent of which controller uses it. If it isn't then the
> driver would need additional code to find out which instance it is
> and construct a dynamic string.
> 
> Any objection to just make this entry "disp", or "dc"?

This patch simply documents the binding that the various drivers
already require and/or whatever is already in the DT files if there
are any clocks the drivers don't currently use. I did consider fixing
up all the current usage to actually be sane, but that would require
even more driver changes (in addition to those required for the reset
framework patches).

>> +  - clock-names : Must include the following entries:
> 
> One other thing I noticed here is that you use a space between the 
> property name and the :. None of the other properties have that, so
> it looks somewhat out of place. The same is true for other
> bindings, but there seem to be inconsistencies in some places
> anyway, so perhaps we don't care? Well, I do care, don't know about
> you. =)

Yes, I simply cut/paste the clock docs from one binding into the other
to make sure the wording was consistent. I guess I need to go through
and adjust the pasted format to match the various bindings. It's a
pity they're plain-text not a schema, so there is no consistency here:-(

>> diff --git
>> a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
>> b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt 
>> index 91ff771c7e77..d4f2d534934b 100644 ---
>> a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt 
>> +++
>> b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt 
>> @@ -6,8 +6,10 @@ Required properties: - interrupts: Should
>> contain SPI interrupts. - nvidia,dma-request-selector : The Tegra
>> DMA controller's phandle and request selector for this SPI
>> controller. -- This is also require clock named "spi" as per
>> binding document -
>> Documentation/devicetree/bindings/clock/clock-bindings.txt +-
>> clocks : Must contain an entry for each entry in clock-names. +
>> See ../clocks/clock-bindings.txt for details. +- clock-names :
>> Must include the following entries: +  - spi
> 
> This is inconsistent with other bindings that require only a
> single clock entry. I suppose that this is required because of the
> driver requesting a specifically named clock, in which case that's
> fine.

This driver does clk_get(dev, "spi") rather than clk_get(dev, NULL),
so this requires a specific name. Again, I did consider updating all
drivers to use names, but decided I didn't want to do even more driver
changes, but instead just document what was currently required.

Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 3914 bytes --]

On Sun, Dec 01, 2013 at 12:05:44PM -0700, Stephen Warren wrote:
> On 11/29/2013 04:49 AM, Thierry Reding wrote:
> > On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote: 
> > [...]
> >> @@ -60,6 +81,12 @@ of the following host1x client modules: -
> >> compatible: "nvidia,tegra<chip>-dc" - reg: Physical base address
> >> and length of the controller's registers. - interrupts: The
> >> interrupt outputs from the controller. +  - clocks : Must contain
> >> an entry for each entry in clock-names. +    See
> >> ../clocks/clock-bindings.txt for details. +  - clock-names : Must
> >> include the following entries: +    - disp1 or disp2 (depending
> >> on the controller instance)
> > 
> > I'm not sure if this makes sense. The name could be the same
> > independent of which controller uses it. If it isn't then the
> > driver would need additional code to find out which instance it is
> > and construct a dynamic string.
> > 
> > Any objection to just make this entry "disp", or "dc"?
> 
> This patch simply documents the binding that the various drivers
> already require and/or whatever is already in the DT files if there
> are any clocks the drivers don't currently use. I did consider fixing
> up all the current usage to actually be sane, but that would require
> even more driver changes (in addition to those required for the reset
> framework patches).

Okay, I understand. I still think we should change the usage for this
particular use-case subsequently. In retrospect the entry in clock-names
wasn't thought out very well. It seems like the reason for using disp1
and disp2 respectively was so that it would match the system-wide clock
name, rather than the clock's label within the display controller's
context.

Just to clarify what I mean, if we stick to the above, then we'll need
to add code to the driver along the lines of:

	char clock_name[6];

	if (regs->start == 0x54200000)
		index = 1;
	else
		index = 2;

	sprintf(clock_name, "disp%u", index);

	clk = devm_clk_get(&pdev->dev, clock_name);

rather than the much more simple and elegant:

	clk = devm_clk_get(&pdev->dev, "disp");

The whole purpose of the clock consumer ID is to be generic and as such
independent of the specific IP block or instance thereof.

> >> diff --git
> >> a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> >> b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt 
> >> index 91ff771c7e77..d4f2d534934b 100644 ---
> >> a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt 
> >> +++
> >> b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt 
> >> @@ -6,8 +6,10 @@ Required properties: - interrupts: Should
> >> contain SPI interrupts. - nvidia,dma-request-selector : The Tegra
> >> DMA controller's phandle and request selector for this SPI
> >> controller. -- This is also require clock named "spi" as per
> >> binding document -
> >> Documentation/devicetree/bindings/clock/clock-bindings.txt +-
> >> clocks : Must contain an entry for each entry in clock-names. +
> >> See ../clocks/clock-bindings.txt for details. +- clock-names :
> >> Must include the following entries: +  - spi
> > 
> > This is inconsistent with other bindings that require only a
> > single clock entry. I suppose that this is required because of the
> > driver requesting a specifically named clock, in which case that's
> > fine.
> 
> This driver does clk_get(dev, "spi") rather than clk_get(dev, NULL),
> so this requires a specific name. Again, I did consider updating all
> drivers to use names, but decided I didn't want to do even more driver
> changes, but instead just document what was currently required.

Yes, I realized that as well. Oh well, I guess that's part of the "pain"
for not doing it right from the start. Although, admittedly, this really
isn't a big issue.

Thierry

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[PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Thierry Reding]

On Sun, Dec 01, 2013 at 12:05:44PM -0700, Stephen Warren wrote:
> On 11/29/2013 04:49 AM, Thierry Reding wrote:
> > On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote: 
> > [...]
> >> @@ -60,6 +81,12 @@ of the following host1x client modules: -
> >> compatible: "nvidia,tegra<chip>-dc" - reg: Physical base address
> >> and length of the controller's registers. - interrupts: The
> >> interrupt outputs from the controller. +  - clocks : Must contain
> >> an entry for each entry in clock-names. +    See
> >> ../clocks/clock-bindings.txt for details. +  - clock-names : Must
> >> include the following entries: +    - disp1 or disp2 (depending
> >> on the controller instance)
> > 
> > I'm not sure if this makes sense. The name could be the same
> > independent of which controller uses it. If it isn't then the
> > driver would need additional code to find out which instance it is
> > and construct a dynamic string.
> > 
> > Any objection to just make this entry "disp", or "dc"?
> 
> This patch simply documents the binding that the various drivers
> already require and/or whatever is already in the DT files if there
> are any clocks the drivers don't currently use. I did consider fixing
> up all the current usage to actually be sane, but that would require
> even more driver changes (in addition to those required for the reset
> framework patches).

Okay, I understand. I still think we should change the usage for this
particular use-case subsequently. In retrospect the entry in clock-names
wasn't thought out very well. It seems like the reason for using disp1
and disp2 respectively was so that it would match the system-wide clock
name, rather than the clock's label within the display controller's
context.

Just to clarify what I mean, if we stick to the above, then we'll need
to add code to the driver along the lines of:

	char clock_name[6];

	if (regs->start == 0x54200000)
		index = 1;
	else
		index = 2;

	sprintf(clock_name, "disp%u", index);

	clk = devm_clk_get(&pdev->dev, clock_name);

rather than the much more simple and elegant:

	clk = devm_clk_get(&pdev->dev, "disp");

The whole purpose of the clock consumer ID is to be generic and as such
independent of the specific IP block or instance thereof.

> >> diff --git
> >> a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> >> b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt 
> >> index 91ff771c7e77..d4f2d534934b 100644 ---
> >> a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt 
> >> +++
> >> b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt 
> >> @@ -6,8 +6,10 @@ Required properties: - interrupts: Should
> >> contain SPI interrupts. - nvidia,dma-request-selector : The Tegra
> >> DMA controller's phandle and request selector for this SPI
> >> controller. -- This is also require clock named "spi" as per
> >> binding document -
> >> Documentation/devicetree/bindings/clock/clock-bindings.txt +-
> >> clocks : Must contain an entry for each entry in clock-names. +
> >> See ../clocks/clock-bindings.txt for details. +- clock-names :
> >> Must include the following entries: +  - spi
> > 
> > This is inconsistent with other bindings that require only a
> > single clock entry. I suppose that this is required because of the
> > driver requesting a specifically named clock, in which case that's
> > fine.
> 
> This driver does clk_get(dev, "spi") rather than clk_get(dev, NULL),
> so this requires a specific name. Again, I did consider updating all
> drivers to use names, but decided I didn't want to do even more driver
> changes, but instead just document what was currently required.

Yes, I realized that as well. Oh well, I guess that's part of the "pain"
for not doing it right from the start. Although, admittedly, this really
isn't a big issue.

Thierry
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Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Stephen Warren]

On 12/02/2013 01:52 AM, Thierry Reding wrote:
> On Sun, Dec 01, 2013 at 12:05:44PM -0700, Stephen Warren wrote:
>> On 11/29/2013 04:49 AM, Thierry Reding wrote:
>>> On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote:
>>>  [...]
>>>> @@ -60,6 +81,12 @@ of the following host1x client modules: - 
>>>> compatible: "nvidia,tegra<chip>-dc" - reg: Physical base
>>>> address and length of the controller's registers. -
>>>> interrupts: The interrupt outputs from the controller. +  -
>>>> clocks : Must contain an entry for each entry in clock-names.
>>>> +    See ../clocks/clock-bindings.txt for details. +  -
>>>> clock-names : Must include the following entries: +    -
>>>> disp1 or disp2 (depending on the controller instance)
>>> 
>>> I'm not sure if this makes sense. The name could be the same 
>>> independent of which controller uses it. If it isn't then the 
>>> driver would need additional code to find out which instance it
>>> is and construct a dynamic string.
>>> 
>>> Any objection to just make this entry "disp", or "dc"?
>> 
>> This patch simply documents the binding that the various drivers 
>> already require and/or whatever is already in the DT files if
>> there are any clocks the drivers don't currently use. I did
>> consider fixing up all the current usage to actually be sane, but
>> that would require even more driver changes (in addition to those
>> required for the reset framework patches).
> 
> Okay, I understand. I still think we should change the usage for
> this particular use-case subsequently. In retrospect the entry in
> clock-names wasn't thought out very well. It seems like the reason
> for using disp1 and disp2 respectively was so that it would match
> the system-wide clock name, rather than the clock's label within
> the display controller's context.
> 
> Just to clarify what I mean, if we stick to the above, then we'll
> need to add code to the driver along the lines of:
> 
> char clock_name[6];
> 
> if (regs->start == 0x54200000) index = 1; else index = 2;
> 
> sprintf(clock_name, "disp%u", index);
> 
> clk = devm_clk_get(&pdev->dev, clock_name);
> 
> rather than the much more simple and elegant:
> 
> clk = devm_clk_get(&pdev->dev, "disp");
> 
> The whole purpose of the clock consumer ID is to be generic and as
> such independent of the specific IP block or instance thereof.

I think if the code needs this clock, I'd be tempted to do the following:

clk = clk_get(dev, "disp1");
if (IS_ERR(clk) && PTR_ERR(clk) != -EPROBE_DEFERRED)
    clk = clk_get(dev, "disp2");
if (IS_ERR(clk))
    return PTR_ERR(clk);

That avoids having to hard-code IP block base addresses and construct
clock names at run-time.

[PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Stephen Warren]

On 12/02/2013 01:52 AM, Thierry Reding wrote:
> On Sun, Dec 01, 2013 at 12:05:44PM -0700, Stephen Warren wrote:
>> On 11/29/2013 04:49 AM, Thierry Reding wrote:
>>> On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote:
>>>  [...]
>>>> @@ -60,6 +81,12 @@ of the following host1x client modules: - 
>>>> compatible: "nvidia,tegra<chip>-dc" - reg: Physical base
>>>> address and length of the controller's registers. -
>>>> interrupts: The interrupt outputs from the controller. +  -
>>>> clocks : Must contain an entry for each entry in clock-names.
>>>> +    See ../clocks/clock-bindings.txt for details. +  -
>>>> clock-names : Must include the following entries: +    -
>>>> disp1 or disp2 (depending on the controller instance)
>>> 
>>> I'm not sure if this makes sense. The name could be the same 
>>> independent of which controller uses it. If it isn't then the 
>>> driver would need additional code to find out which instance it
>>> is and construct a dynamic string.
>>> 
>>> Any objection to just make this entry "disp", or "dc"?
>> 
>> This patch simply documents the binding that the various drivers 
>> already require and/or whatever is already in the DT files if
>> there are any clocks the drivers don't currently use. I did
>> consider fixing up all the current usage to actually be sane, but
>> that would require even more driver changes (in addition to those
>> required for the reset framework patches).
> 
> Okay, I understand. I still think we should change the usage for
> this particular use-case subsequently. In retrospect the entry in
> clock-names wasn't thought out very well. It seems like the reason
> for using disp1 and disp2 respectively was so that it would match
> the system-wide clock name, rather than the clock's label within
> the display controller's context.
> 
> Just to clarify what I mean, if we stick to the above, then we'll
> need to add code to the driver along the lines of:
> 
> char clock_name[6];
> 
> if (regs->start == 0x54200000) index = 1; else index = 2;
> 
> sprintf(clock_name, "disp%u", index);
> 
> clk = devm_clk_get(&pdev->dev, clock_name);
> 
> rather than the much more simple and elegant:
> 
> clk = devm_clk_get(&pdev->dev, "disp");
> 
> The whole purpose of the clock consumer ID is to be generic and as
> such independent of the specific IP block or instance thereof.

I think if the code needs this clock, I'd be tempted to do the following:

clk = clk_get(dev, "disp1");
if (IS_ERR(clk) && PTR_ERR(clk) != -EPROBE_DEFERRED)
    clk = clk_get(dev, "disp2");
if (IS_ERR(clk))
    return PTR_ERR(clk);

That avoids having to hard-code IP block base addresses and construct
clock names at run-time.

Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 3837 bytes --]

On Tue, Dec 03, 2013 at 11:31:00AM -0700, Stephen Warren wrote:
> On 12/02/2013 01:52 AM, Thierry Reding wrote:
> > On Sun, Dec 01, 2013 at 12:05:44PM -0700, Stephen Warren wrote:
> >> On 11/29/2013 04:49 AM, Thierry Reding wrote:
> >>> On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote:
> >>>  [...]
> >>>> @@ -60,6 +81,12 @@ of the following host1x client modules: - 
> >>>> compatible: "nvidia,tegra<chip>-dc" - reg: Physical base
> >>>> address and length of the controller's registers. -
> >>>> interrupts: The interrupt outputs from the controller. +  -
> >>>> clocks : Must contain an entry for each entry in clock-names.
> >>>> +    See ../clocks/clock-bindings.txt for details. +  -
> >>>> clock-names : Must include the following entries: +    -
> >>>> disp1 or disp2 (depending on the controller instance)
> >>> 
> >>> I'm not sure if this makes sense. The name could be the same 
> >>> independent of which controller uses it. If it isn't then the 
> >>> driver would need additional code to find out which instance it
> >>> is and construct a dynamic string.
> >>> 
> >>> Any objection to just make this entry "disp", or "dc"?
> >> 
> >> This patch simply documents the binding that the various drivers 
> >> already require and/or whatever is already in the DT files if
> >> there are any clocks the drivers don't currently use. I did
> >> consider fixing up all the current usage to actually be sane, but
> >> that would require even more driver changes (in addition to those
> >> required for the reset framework patches).
> > 
> > Okay, I understand. I still think we should change the usage for
> > this particular use-case subsequently. In retrospect the entry in
> > clock-names wasn't thought out very well. It seems like the reason
> > for using disp1 and disp2 respectively was so that it would match
> > the system-wide clock name, rather than the clock's label within
> > the display controller's context.
> > 
> > Just to clarify what I mean, if we stick to the above, then we'll
> > need to add code to the driver along the lines of:
> > 
> > char clock_name[6];
> > 
> > if (regs->start == 0x54200000) index = 1; else index = 2;
> > 
> > sprintf(clock_name, "disp%u", index);
> > 
> > clk = devm_clk_get(&pdev->dev, clock_name);
> > 
> > rather than the much more simple and elegant:
> > 
> > clk = devm_clk_get(&pdev->dev, "disp");
> > 
> > The whole purpose of the clock consumer ID is to be generic and as
> > such independent of the specific IP block or instance thereof.
> 
> I think if the code needs this clock, I'd be tempted to do the following:
> 
> clk = clk_get(dev, "disp1");
> if (IS_ERR(clk) && PTR_ERR(clk) != -EPROBE_DEFERRED)
>     clk = clk_get(dev, "disp2");
> if (IS_ERR(clk))
>     return PTR_ERR(clk);
> 
> That avoids having to hard-code IP block base addresses and construct
> clock names at run-time.

I think perhaps we're getting our wires crossed. What I've been trying
to say is that I think the binding should define the first clock to be
named simply "disp".

The reason why I think "disp" is a better choice than "disp1" and
"disp2" is that it merely encodes the purpose of the clock for the
display controller, and doesn't contain knowledge about the particular
instance of the display controller. That's analogous to I2C or SPI nodes
where the clock isn't named "i2c1", "i2c2", ... or "spi1", "spi2", ...
but simply "i2c" or "spi" respectively.

I know that existing DTS files use "disp1" and "disp2", respectively,
but I think that was a wrong choice back at the time and therefore I
suggest that we change it while we still can (DTS files are changing in
3.14 anyway because of the reset and DMA binding updates).

Is that any clearer than what I was saying before?

Thierry

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[PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Thierry Reding]

On Tue, Dec 03, 2013 at 11:31:00AM -0700, Stephen Warren wrote:
> On 12/02/2013 01:52 AM, Thierry Reding wrote:
> > On Sun, Dec 01, 2013 at 12:05:44PM -0700, Stephen Warren wrote:
> >> On 11/29/2013 04:49 AM, Thierry Reding wrote:
> >>> On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote:
> >>>  [...]
> >>>> @@ -60,6 +81,12 @@ of the following host1x client modules: - 
> >>>> compatible: "nvidia,tegra<chip>-dc" - reg: Physical base
> >>>> address and length of the controller's registers. -
> >>>> interrupts: The interrupt outputs from the controller. +  -
> >>>> clocks : Must contain an entry for each entry in clock-names.
> >>>> +    See ../clocks/clock-bindings.txt for details. +  -
> >>>> clock-names : Must include the following entries: +    -
> >>>> disp1 or disp2 (depending on the controller instance)
> >>> 
> >>> I'm not sure if this makes sense. The name could be the same 
> >>> independent of which controller uses it. If it isn't then the 
> >>> driver would need additional code to find out which instance it
> >>> is and construct a dynamic string.
> >>> 
> >>> Any objection to just make this entry "disp", or "dc"?
> >> 
> >> This patch simply documents the binding that the various drivers 
> >> already require and/or whatever is already in the DT files if
> >> there are any clocks the drivers don't currently use. I did
> >> consider fixing up all the current usage to actually be sane, but
> >> that would require even more driver changes (in addition to those
> >> required for the reset framework patches).
> > 
> > Okay, I understand. I still think we should change the usage for
> > this particular use-case subsequently. In retrospect the entry in
> > clock-names wasn't thought out very well. It seems like the reason
> > for using disp1 and disp2 respectively was so that it would match
> > the system-wide clock name, rather than the clock's label within
> > the display controller's context.
> > 
> > Just to clarify what I mean, if we stick to the above, then we'll
> > need to add code to the driver along the lines of:
> > 
> > char clock_name[6];
> > 
> > if (regs->start == 0x54200000) index = 1; else index = 2;
> > 
> > sprintf(clock_name, "disp%u", index);
> > 
> > clk = devm_clk_get(&pdev->dev, clock_name);
> > 
> > rather than the much more simple and elegant:
> > 
> > clk = devm_clk_get(&pdev->dev, "disp");
> > 
> > The whole purpose of the clock consumer ID is to be generic and as
> > such independent of the specific IP block or instance thereof.
> 
> I think if the code needs this clock, I'd be tempted to do the following:
> 
> clk = clk_get(dev, "disp1");
> if (IS_ERR(clk) && PTR_ERR(clk) != -EPROBE_DEFERRED)
>     clk = clk_get(dev, "disp2");
> if (IS_ERR(clk))
>     return PTR_ERR(clk);
> 
> That avoids having to hard-code IP block base addresses and construct
> clock names at run-time.

I think perhaps we're getting our wires crossed. What I've been trying
to say is that I think the binding should define the first clock to be
named simply "disp".

The reason why I think "disp" is a better choice than "disp1" and
"disp2" is that it merely encodes the purpose of the clock for the
display controller, and doesn't contain knowledge about the particular
instance of the display controller. That's analogous to I2C or SPI nodes
where the clock isn't named "i2c1", "i2c2", ... or "spi1", "spi2", ...
but simply "i2c" or "spi" respectively.

I know that existing DTS files use "disp1" and "disp2", respectively,
but I think that was a wrong choice back at the time and therefore I
suggest that we change it while we still can (DTS files are changing in
3.14 anyway because of the reset and DMA binding updates).

Is that any clearer than what I was saying before?

Thierry
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Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Stephen Warren]

On 12/04/2013 01:48 AM, Thierry Reding wrote:
> On Tue, Dec 03, 2013 at 11:31:00AM -0700, Stephen Warren wrote:
>> On 12/02/2013 01:52 AM, Thierry Reding wrote:
>>> On Sun, Dec 01, 2013 at 12:05:44PM -0700, Stephen Warren 
>>> wrote:
>>>> On 11/29/2013 04:49 AM, Thierry Reding wrote:
>>>>> On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren 
>>>>> wrote: [...]
>>>>>> @@ -60,6 +81,12 @@ of the following host1x client 
>>>>>> modules: - compatible: "nvidia,tegra<chip>-dc" - reg: 
>>>>>> Physical base address and length of the controller's 
>>>>>> registers. - interrupts: The interrupt outputs from the 
>>>>>> controller. +  - clocks : Must contain an entry for each 
>>>>>> entry in clock-names. +    See 
>>>>>> ../clocks/clock-bindings.txt for details. +  - 
>>>>>> clock-names : Must include the following entries: +    -
>>>>>>  disp1 or disp2 (depending on the controller instance)
>>>>> 
>>>>> I'm not sure if this makes sense. The name could be the 
>>>>> same independent of which controller uses it. If it isn't 
>>>>> then the driver would need additional code to find out 
>>>>> which instance it is and construct a dynamic string.
>>>>> 
>>>>> Any objection to just make this entry "disp", or "dc"?
>>>> 
>>>> This patch simply documents the binding that the various 
>>>> drivers already require and/or whatever is already in the DT 
>>>> files if there are any clocks the drivers don't currently 
>>>> use. I did consider fixing up all the current usage to 
>>>> actually be sane, but that would require even more driver 
>>>> changes (in addition to those required for the reset 
>>>> framework patches).
>>> 
>>> Okay, I understand. I still think we should change the usage 
>>> for this particular use-case subsequently. In retrospect the 
>>> entry in clock-names wasn't thought out very well. It seems 
>>> like the reason for using disp1 and disp2 respectively was so 
>>> that it would match the system-wide clock name, rather than
>>> the clock's label within the display controller's context.
>>> 
>>> Just to clarify what I mean, if we stick to the above, then 
>>> we'll need to add code to the driver along the lines of:
>>> 
>>> char clock_name[6];
>>> 
>>> if (regs->start == 0x54200000) index = 1; else index = 2;
>>> 
>>> sprintf(clock_name, "disp%u", index);
>>> 
>>> clk = devm_clk_get(&pdev->dev, clock_name);
>>> 
>>> rather than the much more simple and elegant:
>>> 
>>> clk = devm_clk_get(&pdev->dev, "disp");
>>> 
>>> The whole purpose of the clock consumer ID is to be generic
>>> and as such independent of the specific IP block or instance 
>>> thereof.
>> 
>> I think if the code needs this clock, I'd be tempted to do the 
>> following:
>> 
>> clk = clk_get(dev, "disp1"); if (IS_ERR(clk) && PTR_ERR(clk) != 
>> -EPROBE_DEFERRED) clk = clk_get(dev, "disp2"); if (IS_ERR(clk)) 
>> return PTR_ERR(clk);
>> 
>> That avoids having to hard-code IP block base addresses and 
>> construct clock names at run-time.
> 
> I think perhaps we're getting our wires crossed. What I've been 
> trying to say is that I think the binding should define the first 
> clock to be named simply "disp".
> 
> The reason why I think "disp" is a better choice than "disp1" and 
> "disp2" is that it merely encodes the purpose of the clock for the
>  display controller, and doesn't contain knowledge about the 
> particular instance of the display controller. That's analogous to 
> I2C or SPI nodes where the clock isn't named "i2c1", "i2c2", ...
> or "spi1", "spi2", ... but simply "i2c" or "spi" respectively.
> 
> I know that existing DTS files use "disp1" and "disp2", 
> respectively, but I think that was a wrong choice back at the time 
> and therefore I suggest that we change it while we still can (DTS 
> files are changing in 3.14 anyway because of the reset and DMA 
> binding updates).
> 
> Is that any clearer than what I was saying before?

No, because I know what you meant before:-)

The thing I was missing is that the existing disp1/disp2 naming is
/only/ something that's in the DT. The driver (and hence the exiting
as-yet-undocumented ABI) looks up this clock as "index 0" not as "name
disp1". Hence, we /can/ change the documented name without affecting
the ABI at all, and not affecting the ABI is something I was trying to
avoid in this patch.

So, how about I fold the following into this patch:

> diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> index 42fe3a498e71..ab45c02aa658 100644
> --- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> +++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> @@ -111,7 +111,7 @@ of the following host1x client modules:
>    - clocks: Must contain an entry for each entry in clock-names.
>      See ../clocks/clock-bindings.txt for details.
>    - clock-names: Must include the following entries:
> -    - disp1 or disp2 (depending on the controller instance)
> +    - dc
>        This MUST be the first entry.
>      - parent
>    - resets: Must contain an entry for each entry in reset-names.
> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> index 01c20c7dbb51..648c494e927f 100644
> --- a/arch/arm/boot/dts/tegra20.dtsi
> +++ b/arch/arm/boot/dts/tegra20.dtsi
> @@ -89,7 +89,7 @@
>                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
>                         clocks = <&tegra_car TEGRA20_CLK_DISP1>,
>                                  <&tegra_car TEGRA20_CLK_PLL_P>;
> -                       clock-names = "disp1", "parent";
> +                       clock-names = "dc", "parent";
>                         resets = <&tegra_car 27>;
>                         reset-names = "dc";
>  
> @@ -104,7 +104,7 @@
>                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>                         clocks = <&tegra_car TEGRA20_CLK_DISP2>,
>                                  <&tegra_car TEGRA20_CLK_PLL_P>;
> -                       clock-names = "disp2", "parent";
> +                       clock-names = "dc", "parent";
>                         resets = <&tegra_car 26>;
>                         reset-names = "dc";
>  
> diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
> index 58a3dca24c49..829eb4b5091d 100644
> --- a/arch/arm/boot/dts/tegra30.dtsi
> +++ b/arch/arm/boot/dts/tegra30.dtsi
> @@ -165,7 +165,7 @@
>                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
>                         clocks = <&tegra_car TEGRA30_CLK_DISP1>,
>                                  <&tegra_car TEGRA30_CLK_PLL_P>;
> -                       clock-names = "disp1", "parent";
> +                       clock-names = "dc", "parent";
>                         resets = <&tegra_car 27>;
>                         reset-names = "dc";
>  
> @@ -180,7 +180,7 @@
>                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>                         clocks = <&tegra_car TEGRA30_CLK_DISP2>,
>                                  <&tegra_car TEGRA30_CLK_PLL_P>;
> -                       clock-names = "disp2", "parent";
> +                       clock-names = "dc", "parent";
>                         resets = <&tegra_car 26>;
>                         reset-names = "dc";
>  

[PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Stephen Warren]

On 12/04/2013 01:48 AM, Thierry Reding wrote:
> On Tue, Dec 03, 2013 at 11:31:00AM -0700, Stephen Warren wrote:
>> On 12/02/2013 01:52 AM, Thierry Reding wrote:
>>> On Sun, Dec 01, 2013 at 12:05:44PM -0700, Stephen Warren 
>>> wrote:
>>>> On 11/29/2013 04:49 AM, Thierry Reding wrote:
>>>>> On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren 
>>>>> wrote: [...]
>>>>>> @@ -60,6 +81,12 @@ of the following host1x client 
>>>>>> modules: - compatible: "nvidia,tegra<chip>-dc" - reg: 
>>>>>> Physical base address and length of the controller's 
>>>>>> registers. - interrupts: The interrupt outputs from the 
>>>>>> controller. +  - clocks : Must contain an entry for each 
>>>>>> entry in clock-names. +    See 
>>>>>> ../clocks/clock-bindings.txt for details. +  - 
>>>>>> clock-names : Must include the following entries: +    -
>>>>>>  disp1 or disp2 (depending on the controller instance)
>>>>> 
>>>>> I'm not sure if this makes sense. The name could be the 
>>>>> same independent of which controller uses it. If it isn't 
>>>>> then the driver would need additional code to find out 
>>>>> which instance it is and construct a dynamic string.
>>>>> 
>>>>> Any objection to just make this entry "disp", or "dc"?
>>>> 
>>>> This patch simply documents the binding that the various 
>>>> drivers already require and/or whatever is already in the DT 
>>>> files if there are any clocks the drivers don't currently 
>>>> use. I did consider fixing up all the current usage to 
>>>> actually be sane, but that would require even more driver 
>>>> changes (in addition to those required for the reset 
>>>> framework patches).
>>> 
>>> Okay, I understand. I still think we should change the usage 
>>> for this particular use-case subsequently. In retrospect the 
>>> entry in clock-names wasn't thought out very well. It seems 
>>> like the reason for using disp1 and disp2 respectively was so 
>>> that it would match the system-wide clock name, rather than
>>> the clock's label within the display controller's context.
>>> 
>>> Just to clarify what I mean, if we stick to the above, then 
>>> we'll need to add code to the driver along the lines of:
>>> 
>>> char clock_name[6];
>>> 
>>> if (regs->start == 0x54200000) index = 1; else index = 2;
>>> 
>>> sprintf(clock_name, "disp%u", index);
>>> 
>>> clk = devm_clk_get(&pdev->dev, clock_name);
>>> 
>>> rather than the much more simple and elegant:
>>> 
>>> clk = devm_clk_get(&pdev->dev, "disp");
>>> 
>>> The whole purpose of the clock consumer ID is to be generic
>>> and as such independent of the specific IP block or instance 
>>> thereof.
>> 
>> I think if the code needs this clock, I'd be tempted to do the 
>> following:
>> 
>> clk = clk_get(dev, "disp1"); if (IS_ERR(clk) && PTR_ERR(clk) != 
>> -EPROBE_DEFERRED) clk = clk_get(dev, "disp2"); if (IS_ERR(clk)) 
>> return PTR_ERR(clk);
>> 
>> That avoids having to hard-code IP block base addresses and 
>> construct clock names at run-time.
> 
> I think perhaps we're getting our wires crossed. What I've been 
> trying to say is that I think the binding should define the first 
> clock to be named simply "disp".
> 
> The reason why I think "disp" is a better choice than "disp1" and 
> "disp2" is that it merely encodes the purpose of the clock for the
>  display controller, and doesn't contain knowledge about the 
> particular instance of the display controller. That's analogous to 
> I2C or SPI nodes where the clock isn't named "i2c1", "i2c2", ...
> or "spi1", "spi2", ... but simply "i2c" or "spi" respectively.
> 
> I know that existing DTS files use "disp1" and "disp2", 
> respectively, but I think that was a wrong choice back at the time 
> and therefore I suggest that we change it while we still can (DTS 
> files are changing in 3.14 anyway because of the reset and DMA 
> binding updates).
> 
> Is that any clearer than what I was saying before?

No, because I know what you meant before:-)

The thing I was missing is that the existing disp1/disp2 naming is
/only/ something that's in the DT. The driver (and hence the exiting
as-yet-undocumented ABI) looks up this clock as "index 0" not as "name
disp1". Hence, we /can/ change the documented name without affecting
the ABI at all, and not affecting the ABI is something I was trying to
avoid in this patch.

So, how about I fold the following into this patch:

> diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> index 42fe3a498e71..ab45c02aa658 100644
> --- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> +++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> @@ -111,7 +111,7 @@ of the following host1x client modules:
>    - clocks: Must contain an entry for each entry in clock-names.
>      See ../clocks/clock-bindings.txt for details.
>    - clock-names: Must include the following entries:
> -    - disp1 or disp2 (depending on the controller instance)
> +    - dc
>        This MUST be the first entry.
>      - parent
>    - resets: Must contain an entry for each entry in reset-names.
> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> index 01c20c7dbb51..648c494e927f 100644
> --- a/arch/arm/boot/dts/tegra20.dtsi
> +++ b/arch/arm/boot/dts/tegra20.dtsi
> @@ -89,7 +89,7 @@
>                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
>                         clocks = <&tegra_car TEGRA20_CLK_DISP1>,
>                                  <&tegra_car TEGRA20_CLK_PLL_P>;
> -                       clock-names = "disp1", "parent";
> +                       clock-names = "dc", "parent";
>                         resets = <&tegra_car 27>;
>                         reset-names = "dc";
>  
> @@ -104,7 +104,7 @@
>                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>                         clocks = <&tegra_car TEGRA20_CLK_DISP2>,
>                                  <&tegra_car TEGRA20_CLK_PLL_P>;
> -                       clock-names = "disp2", "parent";
> +                       clock-names = "dc", "parent";
>                         resets = <&tegra_car 26>;
>                         reset-names = "dc";
>  
> diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
> index 58a3dca24c49..829eb4b5091d 100644
> --- a/arch/arm/boot/dts/tegra30.dtsi
> +++ b/arch/arm/boot/dts/tegra30.dtsi
> @@ -165,7 +165,7 @@
>                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
>                         clocks = <&tegra_car TEGRA30_CLK_DISP1>,
>                                  <&tegra_car TEGRA30_CLK_PLL_P>;
> -                       clock-names = "disp1", "parent";
> +                       clock-names = "dc", "parent";
>                         resets = <&tegra_car 27>;
>                         reset-names = "dc";
>  
> @@ -180,7 +180,7 @@
>                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>                         clocks = <&tegra_car TEGRA30_CLK_DISP2>,
>                                  <&tegra_car TEGRA30_CLK_PLL_P>;
> -                       clock-names = "disp2", "parent";
> +                       clock-names = "dc", "parent";
>                         resets = <&tegra_car 26>;
>                         reset-names = "dc";
>  

Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 7925 bytes --]

On Wed, Dec 04, 2013 at 10:34:17AM -0700, Stephen Warren wrote:
> On 12/04/2013 01:48 AM, Thierry Reding wrote:
> > On Tue, Dec 03, 2013 at 11:31:00AM -0700, Stephen Warren wrote:
> >> On 12/02/2013 01:52 AM, Thierry Reding wrote:
> >>> On Sun, Dec 01, 2013 at 12:05:44PM -0700, Stephen Warren 
> >>> wrote:
> >>>> On 11/29/2013 04:49 AM, Thierry Reding wrote:
> >>>>> On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren 
> >>>>> wrote: [...]
> >>>>>> @@ -60,6 +81,12 @@ of the following host1x client 
> >>>>>> modules: - compatible: "nvidia,tegra<chip>-dc" - reg: 
> >>>>>> Physical base address and length of the controller's 
> >>>>>> registers. - interrupts: The interrupt outputs from the 
> >>>>>> controller. +  - clocks : Must contain an entry for each 
> >>>>>> entry in clock-names. +    See 
> >>>>>> ../clocks/clock-bindings.txt for details. +  - 
> >>>>>> clock-names : Must include the following entries: +    -
> >>>>>>  disp1 or disp2 (depending on the controller instance)
> >>>>> 
> >>>>> I'm not sure if this makes sense. The name could be the 
> >>>>> same independent of which controller uses it. If it isn't 
> >>>>> then the driver would need additional code to find out 
> >>>>> which instance it is and construct a dynamic string.
> >>>>> 
> >>>>> Any objection to just make this entry "disp", or "dc"?
> >>>> 
> >>>> This patch simply documents the binding that the various 
> >>>> drivers already require and/or whatever is already in the DT 
> >>>> files if there are any clocks the drivers don't currently 
> >>>> use. I did consider fixing up all the current usage to 
> >>>> actually be sane, but that would require even more driver 
> >>>> changes (in addition to those required for the reset 
> >>>> framework patches).
> >>> 
> >>> Okay, I understand. I still think we should change the usage 
> >>> for this particular use-case subsequently. In retrospect the 
> >>> entry in clock-names wasn't thought out very well. It seems 
> >>> like the reason for using disp1 and disp2 respectively was so 
> >>> that it would match the system-wide clock name, rather than
> >>> the clock's label within the display controller's context.
> >>> 
> >>> Just to clarify what I mean, if we stick to the above, then 
> >>> we'll need to add code to the driver along the lines of:
> >>> 
> >>> char clock_name[6];
> >>> 
> >>> if (regs->start == 0x54200000) index = 1; else index = 2;
> >>> 
> >>> sprintf(clock_name, "disp%u", index);
> >>> 
> >>> clk = devm_clk_get(&pdev->dev, clock_name);
> >>> 
> >>> rather than the much more simple and elegant:
> >>> 
> >>> clk = devm_clk_get(&pdev->dev, "disp");
> >>> 
> >>> The whole purpose of the clock consumer ID is to be generic
> >>> and as such independent of the specific IP block or instance 
> >>> thereof.
> >> 
> >> I think if the code needs this clock, I'd be tempted to do the 
> >> following:
> >> 
> >> clk = clk_get(dev, "disp1"); if (IS_ERR(clk) && PTR_ERR(clk) != 
> >> -EPROBE_DEFERRED) clk = clk_get(dev, "disp2"); if (IS_ERR(clk)) 
> >> return PTR_ERR(clk);
> >> 
> >> That avoids having to hard-code IP block base addresses and 
> >> construct clock names at run-time.
> > 
> > I think perhaps we're getting our wires crossed. What I've been 
> > trying to say is that I think the binding should define the first 
> > clock to be named simply "disp".
> > 
> > The reason why I think "disp" is a better choice than "disp1" and 
> > "disp2" is that it merely encodes the purpose of the clock for the
> >  display controller, and doesn't contain knowledge about the 
> > particular instance of the display controller. That's analogous to 
> > I2C or SPI nodes where the clock isn't named "i2c1", "i2c2", ...
> > or "spi1", "spi2", ... but simply "i2c" or "spi" respectively.
> > 
> > I know that existing DTS files use "disp1" and "disp2", 
> > respectively, but I think that was a wrong choice back at the time 
> > and therefore I suggest that we change it while we still can (DTS 
> > files are changing in 3.14 anyway because of the reset and DMA 
> > binding updates).
> > 
> > Is that any clearer than what I was saying before?
> 
> No, because I know what you meant before:-)
> 
> The thing I was missing is that the existing disp1/disp2 naming is
> /only/ something that's in the DT. The driver (and hence the exiting
> as-yet-undocumented ABI) looks up this clock as "index 0" not as "name
> disp1". Hence, we /can/ change the documented name without affecting
> the ABI at all, and not affecting the ABI is something I was trying to
> avoid in this patch.

Excellent. Glad we're finally on the same page.

> So, how about I fold the following into this patch:
> 
> > diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> > index 42fe3a498e71..ab45c02aa658 100644
> > --- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> > +++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> > @@ -111,7 +111,7 @@ of the following host1x client modules:
> >    - clocks: Must contain an entry for each entry in clock-names.
> >      See ../clocks/clock-bindings.txt for details.
> >    - clock-names: Must include the following entries:
> > -    - disp1 or disp2 (depending on the controller instance)
> > +    - dc
> >        This MUST be the first entry.
> >      - parent
> >    - resets: Must contain an entry for each entry in reset-names.
> > diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> > index 01c20c7dbb51..648c494e927f 100644
> > --- a/arch/arm/boot/dts/tegra20.dtsi
> > +++ b/arch/arm/boot/dts/tegra20.dtsi
> > @@ -89,7 +89,7 @@
> >                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> >                         clocks = <&tegra_car TEGRA20_CLK_DISP1>,
> >                                  <&tegra_car TEGRA20_CLK_PLL_P>;
> > -                       clock-names = "disp1", "parent";
> > +                       clock-names = "dc", "parent";
> >                         resets = <&tegra_car 27>;
> >                         reset-names = "dc";
> >  
> > @@ -104,7 +104,7 @@
> >                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> >                         clocks = <&tegra_car TEGRA20_CLK_DISP2>,
> >                                  <&tegra_car TEGRA20_CLK_PLL_P>;
> > -                       clock-names = "disp2", "parent";
> > +                       clock-names = "dc", "parent";
> >                         resets = <&tegra_car 26>;
> >                         reset-names = "dc";
> >  
> > diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
> > index 58a3dca24c49..829eb4b5091d 100644
> > --- a/arch/arm/boot/dts/tegra30.dtsi
> > +++ b/arch/arm/boot/dts/tegra30.dtsi
> > @@ -165,7 +165,7 @@
> >                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> >                         clocks = <&tegra_car TEGRA30_CLK_DISP1>,
> >                                  <&tegra_car TEGRA30_CLK_PLL_P>;
> > -                       clock-names = "disp1", "parent";
> > +                       clock-names = "dc", "parent";
> >                         resets = <&tegra_car 27>;
> >                         reset-names = "dc";
> >  
> > @@ -180,7 +180,7 @@
> >                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> >                         clocks = <&tegra_car TEGRA30_CLK_DISP2>,
> >                                  <&tegra_car TEGRA30_CLK_PLL_P>;
> > -                       clock-names = "disp2", "parent";
> > +                       clock-names = "dc", "parent";
> >                         resets = <&tegra_car 26>;
> >                         reset-names = "dc";
> >  

That looks perfect. Thanks!

Thierry

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[PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Thierry Reding]

On Wed, Dec 04, 2013 at 10:34:17AM -0700, Stephen Warren wrote:
> On 12/04/2013 01:48 AM, Thierry Reding wrote:
> > On Tue, Dec 03, 2013 at 11:31:00AM -0700, Stephen Warren wrote:
> >> On 12/02/2013 01:52 AM, Thierry Reding wrote:
> >>> On Sun, Dec 01, 2013 at 12:05:44PM -0700, Stephen Warren 
> >>> wrote:
> >>>> On 11/29/2013 04:49 AM, Thierry Reding wrote:
> >>>>> On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren 
> >>>>> wrote: [...]
> >>>>>> @@ -60,6 +81,12 @@ of the following host1x client 
> >>>>>> modules: - compatible: "nvidia,tegra<chip>-dc" - reg: 
> >>>>>> Physical base address and length of the controller's 
> >>>>>> registers. - interrupts: The interrupt outputs from the 
> >>>>>> controller. +  - clocks : Must contain an entry for each 
> >>>>>> entry in clock-names. +    See 
> >>>>>> ../clocks/clock-bindings.txt for details. +  - 
> >>>>>> clock-names : Must include the following entries: +    -
> >>>>>>  disp1 or disp2 (depending on the controller instance)
> >>>>> 
> >>>>> I'm not sure if this makes sense. The name could be the 
> >>>>> same independent of which controller uses it. If it isn't 
> >>>>> then the driver would need additional code to find out 
> >>>>> which instance it is and construct a dynamic string.
> >>>>> 
> >>>>> Any objection to just make this entry "disp", or "dc"?
> >>>> 
> >>>> This patch simply documents the binding that the various 
> >>>> drivers already require and/or whatever is already in the DT 
> >>>> files if there are any clocks the drivers don't currently 
> >>>> use. I did consider fixing up all the current usage to 
> >>>> actually be sane, but that would require even more driver 
> >>>> changes (in addition to those required for the reset 
> >>>> framework patches).
> >>> 
> >>> Okay, I understand. I still think we should change the usage 
> >>> for this particular use-case subsequently. In retrospect the 
> >>> entry in clock-names wasn't thought out very well. It seems 
> >>> like the reason for using disp1 and disp2 respectively was so 
> >>> that it would match the system-wide clock name, rather than
> >>> the clock's label within the display controller's context.
> >>> 
> >>> Just to clarify what I mean, if we stick to the above, then 
> >>> we'll need to add code to the driver along the lines of:
> >>> 
> >>> char clock_name[6];
> >>> 
> >>> if (regs->start == 0x54200000) index = 1; else index = 2;
> >>> 
> >>> sprintf(clock_name, "disp%u", index);
> >>> 
> >>> clk = devm_clk_get(&pdev->dev, clock_name);
> >>> 
> >>> rather than the much more simple and elegant:
> >>> 
> >>> clk = devm_clk_get(&pdev->dev, "disp");
> >>> 
> >>> The whole purpose of the clock consumer ID is to be generic
> >>> and as such independent of the specific IP block or instance 
> >>> thereof.
> >> 
> >> I think if the code needs this clock, I'd be tempted to do the 
> >> following:
> >> 
> >> clk = clk_get(dev, "disp1"); if (IS_ERR(clk) && PTR_ERR(clk) != 
> >> -EPROBE_DEFERRED) clk = clk_get(dev, "disp2"); if (IS_ERR(clk)) 
> >> return PTR_ERR(clk);
> >> 
> >> That avoids having to hard-code IP block base addresses and 
> >> construct clock names at run-time.
> > 
> > I think perhaps we're getting our wires crossed. What I've been 
> > trying to say is that I think the binding should define the first 
> > clock to be named simply "disp".
> > 
> > The reason why I think "disp" is a better choice than "disp1" and 
> > "disp2" is that it merely encodes the purpose of the clock for the
> >  display controller, and doesn't contain knowledge about the 
> > particular instance of the display controller. That's analogous to 
> > I2C or SPI nodes where the clock isn't named "i2c1", "i2c2", ...
> > or "spi1", "spi2", ... but simply "i2c" or "spi" respectively.
> > 
> > I know that existing DTS files use "disp1" and "disp2", 
> > respectively, but I think that was a wrong choice back at the time 
> > and therefore I suggest that we change it while we still can (DTS 
> > files are changing in 3.14 anyway because of the reset and DMA 
> > binding updates).
> > 
> > Is that any clearer than what I was saying before?
> 
> No, because I know what you meant before:-)
> 
> The thing I was missing is that the existing disp1/disp2 naming is
> /only/ something that's in the DT. The driver (and hence the exiting
> as-yet-undocumented ABI) looks up this clock as "index 0" not as "name
> disp1". Hence, we /can/ change the documented name without affecting
> the ABI at all, and not affecting the ABI is something I was trying to
> avoid in this patch.

Excellent. Glad we're finally on the same page.

> So, how about I fold the following into this patch:
> 
> > diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> > index 42fe3a498e71..ab45c02aa658 100644
> > --- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> > +++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> > @@ -111,7 +111,7 @@ of the following host1x client modules:
> >    - clocks: Must contain an entry for each entry in clock-names.
> >      See ../clocks/clock-bindings.txt for details.
> >    - clock-names: Must include the following entries:
> > -    - disp1 or disp2 (depending on the controller instance)
> > +    - dc
> >        This MUST be the first entry.
> >      - parent
> >    - resets: Must contain an entry for each entry in reset-names.
> > diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> > index 01c20c7dbb51..648c494e927f 100644
> > --- a/arch/arm/boot/dts/tegra20.dtsi
> > +++ b/arch/arm/boot/dts/tegra20.dtsi
> > @@ -89,7 +89,7 @@
> >                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> >                         clocks = <&tegra_car TEGRA20_CLK_DISP1>,
> >                                  <&tegra_car TEGRA20_CLK_PLL_P>;
> > -                       clock-names = "disp1", "parent";
> > +                       clock-names = "dc", "parent";
> >                         resets = <&tegra_car 27>;
> >                         reset-names = "dc";
> >  
> > @@ -104,7 +104,7 @@
> >                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> >                         clocks = <&tegra_car TEGRA20_CLK_DISP2>,
> >                                  <&tegra_car TEGRA20_CLK_PLL_P>;
> > -                       clock-names = "disp2", "parent";
> > +                       clock-names = "dc", "parent";
> >                         resets = <&tegra_car 26>;
> >                         reset-names = "dc";
> >  
> > diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
> > index 58a3dca24c49..829eb4b5091d 100644
> > --- a/arch/arm/boot/dts/tegra30.dtsi
> > +++ b/arch/arm/boot/dts/tegra30.dtsi
> > @@ -165,7 +165,7 @@
> >                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> >                         clocks = <&tegra_car TEGRA30_CLK_DISP1>,
> >                                  <&tegra_car TEGRA30_CLK_PLL_P>;
> > -                       clock-names = "disp1", "parent";
> > +                       clock-names = "dc", "parent";
> >                         resets = <&tegra_car 27>;
> >                         reset-names = "dc";
> >  
> > @@ -180,7 +180,7 @@
> >                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> >                         clocks = <&tegra_car TEGRA30_CLK_DISP2>,
> >                                  <&tegra_car TEGRA30_CLK_PLL_P>;
> > -                       clock-names = "disp2", "parent";
> > +                       clock-names = "dc", "parent";
> >                         resets = <&tegra_car 26>;
> >                         reset-names = "dc";
> >  

That looks perfect. Thanks!

Thierry
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Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Stephen Warren]

On 11/29/2013 04:49 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote:
...
>> +  - clock-names : Must include the following entries:
> 
> One other thing I noticed here is that you use a space between the 
> property name and the :. None of the other properties have that, so
> it looks somewhat out of place. The same is true for other
> bindings, but there seem to be inconsistencies in some places
> anyway, so perhaps we don't care? Well, I do care, don't know about
> you. =)

I've fixed those up locally. I assume you don't want a repost for such
a trivial change? I'll double-check the "resets" patch for the same issue.

[PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Stephen Warren]

On 11/29/2013 04:49 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote:
...
>> +  - clock-names : Must include the following entries:
> 
> One other thing I noticed here is that you use a space between the 
> property name and the :. None of the other properties have that, so
> it looks somewhat out of place. The same is true for other
> bindings, but there seem to be inconsistencies in some places
> anyway, so perhaps we don't care? Well, I do care, don't know about
> you. =)

I've fixed those up locally. I assume you don't want a repost for such
a trivial change? I'll double-check the "resets" patch for the same issue.

Re: [PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 962 bytes --]

On Tue, Dec 03, 2013 at 11:36:19AM -0700, Stephen Warren wrote:
> On 11/29/2013 04:49 AM, Thierry Reding wrote:
> > On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote:
> ...
> >> +  - clock-names : Must include the following entries:
> > 
> > One other thing I noticed here is that you use a space between the 
> > property name and the :. None of the other properties have that, so
> > it looks somewhat out of place. The same is true for other
> > bindings, but there seem to be inconsistencies in some places
> > anyway, so perhaps we don't care? Well, I do care, don't know about
> > you. =)
> 
> I've fixed those up locally. I assume you don't want a repost for such
> a trivial change? I'll double-check the "resets" patch for the same issue.

No need for a repost. I'll trust you on that one. But I'll urge you to
consider what I said about the "disp" clock entry for the display
controllers before merging this.

Thierry

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[PATCH 01/31] ARM: tegra: add missing clock documentation to DT bindings

[Thierry Reding]

On Tue, Dec 03, 2013 at 11:36:19AM -0700, Stephen Warren wrote:
> On 11/29/2013 04:49 AM, Thierry Reding wrote:
> > On Fri, Nov 15, 2013 at 01:53:56PM -0700, Stephen Warren wrote:
> ...
> >> +  - clock-names : Must include the following entries:
> > 
> > One other thing I noticed here is that you use a space between the 
> > property name and the :. None of the other properties have that, so
> > it looks somewhat out of place. The same is true for other
> > bindings, but there seem to be inconsistencies in some places
> > anyway, so perhaps we don't care? Well, I do care, don't know about
> > you. =)
> 
> I've fixed those up locally. I assume you don't want a repost for such
> a trivial change? I'll double-check the "resets" patch for the same issue.

No need for a repost. I'll trust you on that one. But I'll urge you to
consider what I said about the "disp" clock entry for the display
controllers before merging this.

Thierry
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[PATCH 02/31] ARM: tegra: document reset properties in DT bindings

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Update all the Tegra DT bindings to require resets/reset-names properties
where the HW module has reset inputs. Remove any entries from clocks or
clock-names that were only required to identify reset inputs, rather than
referring to real clocks.

This is a DT-ABI-incompatible change. It is the first of two changes
required for me to consider the Tegra DT bindings as stable, the other
being conversion to the common DMA DT bindings.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../bindings/clock/nvidia,tegra114-car.txt         |  4 ++
 .../bindings/clock/nvidia,tegra124-car.txt         |  4 ++
 .../bindings/clock/nvidia,tegra20-car.txt          |  4 ++
 .../bindings/clock/nvidia,tegra30-car.txt          |  4 ++
 .../devicetree/bindings/dma/tegra20-apbdma.txt     |  6 +++
 .../bindings/gpu/nvidia,tegra20-host1x.txt         | 63 ++++++++++++++++++++++
 .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt |  6 +++
 .../bindings/input/nvidia,tegra20-kbc.txt          |  6 +++
 .../bindings/mmc/nvidia,tegra20-sdhci.txt          |  6 +++
 .../devicetree/bindings/nvec/nvidia,nvec.txt       |  4 ++
 .../bindings/pci/nvidia,tegra20-pcie.txt           | 14 +++--
 .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt |  6 +++
 .../bindings/serial/nvidia,tegra20-hsuart.txt      |  6 +++
 .../bindings/sound/nvidia,tegra20-ac97.txt         |  6 +++
 .../bindings/sound/nvidia,tegra20-i2s.txt          |  6 +++
 .../bindings/sound/nvidia,tegra30-ahub.txt         | 17 ++++--
 .../bindings/sound/nvidia,tegra30-i2s.txt          |  6 +++
 .../bindings/spi/nvidia,tegra114-spi.txt           |  6 +++
 .../bindings/spi/nvidia,tegra20-sflash.txt         |  6 +++
 .../bindings/spi/nvidia,tegra20-slink.txt          |  6 +++
 .../bindings/usb/nvidia,tegra20-ehci.txt           |  4 ++
 21 files changed, 181 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
index 0c80c2677104..9acea9d93160 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
@@ -15,6 +15,9 @@ Required properties :
   In clock consumers, this cell represents the clock ID exposed by the
   CAR. The assignments may be found in header file
   <dt-bindings/clock/tegra114-car.h>.
+- #reset-cells : Should be 1.
+  In clock consumers, this cell represents the bit number in the CAR's
+  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
 
 Example SoC include file:
 
@@ -23,6 +26,7 @@ Example SoC include file:
 		compatible = "nvidia,tegra114-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	usb@c5004000 {
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
index 1a91ec60dee5..ded5d6212c84 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
@@ -15,6 +15,9 @@ Required properties :
   In clock consumers, this cell represents the clock ID exposed by the
   CAR. The assignments may be found in header file
   <dt-bindings/clock/tegra124-car.h>.
+- #reset-cells : Should be 1.
+  In clock consumers, this cell represents the bit number in the CAR's
+  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
 
 Example SoC include file:
 
@@ -23,6 +26,7 @@ Example SoC include file:
 		compatible = "nvidia,tegra124-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	usb@c5004000 {
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
index fcfed5bf73fb..6c5901b503d0 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -15,6 +15,9 @@ Required properties :
   In clock consumers, this cell represents the clock ID exposed by the
   CAR. The assignments may be found in header file
   <dt-bindings/clock/tegra20-car.h>.
+- #reset-cells : Should be 1.
+  In clock consumers, this cell represents the bit number in the CAR's
+  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
 
 Example SoC include file:
 
@@ -23,6 +26,7 @@ Example SoC include file:
 		compatible = "nvidia,tegra20-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	usb@c5004000 {
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
index 0f714081e986..63618cde12df 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
@@ -15,6 +15,9 @@ Required properties :
   In clock consumers, this cell represents the clock ID exposed by the
   CAR. The assignments may be found in header file
   <dt-bindings/clock/tegra30-car.h>.
+- #reset-cells : Should be 1.
+  In clock consumers, this cell represents the bit number in the CAR's
+  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
 
 Example SoC include file:
 
@@ -23,6 +26,7 @@ Example SoC include file:
 		compatible = "nvidia,tegra30-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	usb@c5004000 {
diff --git a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
index 74bfc54bb184..0b1e577ab9d3 100644
--- a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
+++ b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
@@ -7,6 +7,10 @@ Required properties:
 - interrupts: Should contain all of the per-channel DMA interrupts.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - dma
 
 Examples:
 
@@ -30,4 +34,6 @@ apbdma: dma@6000a000 {
 		       0 150 0x04
 		       0 151 0x04 >;
 	clocks = <&tegra_car 34>;
+	resets = <&tegra_car 34>;
+	reset-names = "dma";
 };
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
index c9a715a75f60..8e22d234dc4c 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
@@ -11,6 +11,10 @@ Required properties:
 - ranges: The mapping of the host1x address space to the CPU address space.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - host1x
 
 The host1x top-level node defines a number of children, each representing one
 of the following host1x client modules:
@@ -23,6 +27,10 @@ of the following host1x client modules:
   - interrupts: The interrupt outputs from the controller.
   - clocks : Must contain one entry, for the module clock.
     See ../clocks/clock-bindings.txt for details.
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - mpe
 
 - vi: video input
 
@@ -32,6 +40,10 @@ of the following host1x client modules:
   - interrupts: The interrupt outputs from the controller.
   - clocks : Must contain one entry, for the module clock.
     See ../clocks/clock-bindings.txt for details.
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - vi
 
 - epp: encoder pre-processor
 
@@ -41,6 +53,10 @@ of the following host1x client modules:
   - interrupts: The interrupt outputs from the controller.
   - clocks : Must contain one entry, for the module clock.
     See ../clocks/clock-bindings.txt for details.
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - epp
 
 - isp: image signal processor
 
@@ -50,6 +66,10 @@ of the following host1x client modules:
   - interrupts: The interrupt outputs from the controller.
   - clocks : Must contain one entry, for the module clock.
     See ../clocks/clock-bindings.txt for details.
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - isp
 
 - gr2d: 2D graphics engine
 
@@ -59,6 +79,10 @@ of the following host1x client modules:
   - interrupts: The interrupt outputs from the controller.
   - clocks : Must contain one entry, for the module clock.
     See ../clocks/clock-bindings.txt for details.
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - 2d
 
 - gr3d: 3D graphics engine
 
@@ -74,6 +98,11 @@ of the following host1x client modules:
     - 3d
       This MUST be the first entry.
     - 3d2 (Only required on SoCs with two 3D clocks)
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - 3d
+    - 3d2 (Only required on SoCs with two 3D clocks)
 
 - dc: display controller
 
@@ -87,6 +116,10 @@ of the following host1x client modules:
     - disp1 or disp2 (depending on the controller instance)
       This MUST be the first entry.
     - parent
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - dc
 
   Each display controller node has a child node, named "rgb", that represents
   the RGB output associated with the controller. It can take the following
@@ -109,6 +142,10 @@ of the following host1x client modules:
     - hdmi
       This MUST be the first entry.
     - parent
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - hdmi
 
   Optional properties:
   - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
@@ -137,6 +174,10 @@ of the following host1x client modules:
     - dsi
       This MUST be the first entry.
     - parent
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - dsi
 
 Example:
 
@@ -149,6 +190,8 @@ Example:
 		interrupts = <0 65 0x04   /* mpcore syncpt */
 			      0 67 0x04>; /* mpcore general */
 		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
+		resets = <&tegra_car 28>;
+		reset-names = "host1x";
 
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -160,6 +203,8 @@ Example:
 			reg = <0x54040000 0x00040000>;
 			interrupts = <0 68 0x04>;
 			clocks = <&tegra_car TEGRA20_CLK_MPE>;
+			resets = <&tegra_car 60>;
+			reset-names = "mpe";
 		};
 
 		vi {
@@ -167,6 +212,8 @@ Example:
 			reg = <0x54080000 0x00040000>;
 			interrupts = <0 69 0x04>;
 			clocks = <&tegra_car TEGRA20_CLK_VI>;
+			resets = <&tegra_car 100>;
+			reset-names = "vi";
 		};
 
 		epp {
@@ -174,6 +221,8 @@ Example:
 			reg = <0x540c0000 0x00040000>;
 			interrupts = <0 70 0x04>;
 			clocks = <&tegra_car TEGRA20_CLK_EPP>;
+			resets = <&tegra_car 19>;
+			reset-names = "epp";
 		};
 
 		isp {
@@ -181,6 +230,8 @@ Example:
 			reg = <0x54100000 0x00040000>;
 			interrupts = <0 71 0x04>;
 			clocks = <&tegra_car TEGRA20_CLK_ISP>;
+			resets = <&tegra_car 23>;
+			reset-names = "isp";
 		};
 
 		gr2d {
@@ -188,12 +239,16 @@ Example:
 			reg = <0x54140000 0x00040000>;
 			interrupts = <0 72 0x04>;
 			clocks = <&tegra_car TEGRA20_CLK_GR2D>;
+			resets = <&tegra_car 21>;
+			reset-names = "2d";
 		};
 
 		gr3d {
 			compatible = "nvidia,tegra20-gr3d";
 			reg = <0x54180000 0x00040000>;
 			clocks = <&tegra_car TEGRA20_CLK_GR3D>;
+			resets = <&tegra_car 24>;
+			reset-names = "3d";
 		};
 
 		dc@54200000 {
@@ -203,6 +258,8 @@ Example:
 			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
 				 <&tegra_car TEGRA20_CLK_PLL_P>;
 			clock-names = "disp1", "parent";
+			resets = <&tegra_car 27>;
+			reset-names = "dc";
 
 			rgb {
 				status = "disabled";
@@ -216,6 +273,8 @@ Example:
 			clocks = <&tegra_car TEGRA20_CLK_DISP2>,
 				 <&tegra_car TEGRA20_CLK_PLL_P>;
 			clock-names = "disp2", "parent";
+			resets = <&tegra_car 26>;
+			reset-names = "dc";
 
 			rgb {
 				status = "disabled";
@@ -229,6 +288,8 @@ Example:
 			clocks = <&tegra_car TEGRA20_CLK_HDMI>,
 				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 			clock-names = "hdmi", "parent";
+			resets = <&tegra_car 51>;
+			reset-names = "hdmi";
 			status = "disabled";
 		};
 
@@ -244,6 +305,8 @@ Example:
 			compatible = "nvidia,tegra20-dsi";
 			reg = <0x54300000 0x00040000>;
 			clocks = <&tegra_car TEGRA20_CLK_DSI>;
+			resets = <&tegra_car 48>;
+			reset-names = "dsi";
 			status = "disabled";
 		};
 	};
diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
index 96ab40131ae1..2b3af72dfb9c 100644
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
@@ -47,6 +47,10 @@ Required properties:
   - fast-clk
   Tegra114:
   - div-clk
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - i2c
 
 Example:
 
@@ -58,5 +62,7 @@ Example:
 		#size-cells = <0>;
 		clocks = <&tegra_car 12>, <&tegra_car 124>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 12>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
diff --git a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
index cc28d2194c37..83b14b6389fc 100644
--- a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
+++ b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
@@ -15,6 +15,10 @@ Required properties:
   devicetree/bindings/input/matrix-keymap.txt.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - kbc
 
 Optional properties, in addition to those specified by the shared
 matrix-keyboard bindings:
@@ -34,6 +38,8 @@ keyboard: keyboard {
 	reg = <0x7000e200 0x100>;
 	interrupts = <0 85 0x04>;
 	clocks = <&tegra_car 36>;
+	resets = <&tegra_car 36>;
+	reset-names = "kbc";
 	nvidia,ghost-filter;
 	nvidia,debounce-delay-ms = <640>;
 	nvidia,kbc-row-pins = <0 1 2>;    /* pin 0, 1, 2 as rows */
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
index f727902a9e8d..f357c16ea815 100644
--- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
@@ -10,6 +10,10 @@ Required properties:
 - compatible : Should be "nvidia,<chip>-sdhci"
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - sdhci
 
 Optional properties:
 - power-gpios : Specify GPIOs for power control
@@ -21,6 +25,8 @@ sdhci@c8000200 {
 	reg = <0xc8000200 0x200>;
 	interrupts = <47>;
 	clocks = <&tegra_car 14>;
+	resets = <&tegra_car 14>;
+	reset-names = "sdhci";
 	cd-gpios = <&gpio 69 0>; /* gpio PI5 */
 	wp-gpios = <&gpio 57 0>; /* gpio PH1 */
 	power-gpios = <&gpio 155 0>; /* gpio PT3 */
diff --git a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
index a97fe575ca29..5ae601e7f51f 100644
--- a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
+++ b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
@@ -15,3 +15,7 @@ Required properties:
   - fast-clk
   Tegra114:
   - div-clk
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - i2c
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
index ad2eb9804afa..6d91016100b3 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
@@ -47,9 +47,14 @@ Required properties:
 - clock-names : Must include the following entries:
   - pex
   - afi
-  - pcie_xclk
   - pll_e
   - cml (not required for Tegra20)
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - pex
+  - afi
+  - pcie_x
 
 Root ports are defined as subnodes of the PCIe controller node.
 
@@ -91,9 +96,10 @@ SoC DTSI:
 			  0x82000000 0 0xa0000000 0xa0000000 0 0x10000000   /* non-prefetchable memory */
 			  0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
 
-		clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>,
-			 <&tegra_car 118>;
-		clock-names = "pex", "afi", "pcie_xclk", "pll_e";
+		clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>;
+		clock-names = "pex", "afi", "pll_e";
+		resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>;
+		reset-names = "pex", "afi", "pcie_x";
 		status = "disabled";
 
 		pci@1,0 {
diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
index 0d608d34fed0..a65d4c3be231 100644
--- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
@@ -9,6 +9,10 @@ Required properties:
   the cells format.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - pwm
 
 Example:
 
@@ -17,4 +21,6 @@ Example:
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
 		clocks = <&tegra_car 17>;
+		resets = <&tegra_car 17>;
+		reset-names = "pwm";
 	};
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
index 39148b6236a1..69ccdbe3760e 100644
--- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
+++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
@@ -8,6 +8,10 @@ Required properties:
   request selector for this UART controller.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - serial
 
 Optional properties:
 - nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
@@ -23,5 +27,7 @@ serial@70006000 {
 	nvidia,dma-request-selector = <&apbdma 8>;
 	nvidia,enable-modem-interrupt;
 	clocks = <&tegra_car 6>;
+	resets = <&tegra_car 6>;
+	reset-names = "serial";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
index 37f4ebf5b184..2b6817f6e40e 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
@@ -6,6 +6,10 @@ Required properties:
 - interrupts : Should contain AC97 interrupt
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - ac97
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for the AC97 controller
 - nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the number
@@ -23,4 +27,6 @@ ac97@70002000 {
 	nvidia,codec-reset-gpio = <&gpio 170 0>;
 	nvidia,codec-sync-gpio = <&gpio 120 0>;
 	clocks = <&tegra_car 3>;
+	resets = <&tegra_car 3>;
+	reset-names = "ac97";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
index ba0c9452916d..8b070aeca3db 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
@@ -6,6 +6,10 @@ Required properties:
 - interrupts : Should contain I2S interrupt
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - i2s
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for this I2S controller
 
@@ -17,4 +21,6 @@ i2s@70002800 {
 	interrupts = < 45 >;
 	nvidia,dma-request-selector = < &apbdma 2 >;
 	clocks = <&tegra_car 11>;
+	resets = <&tegra_car 11>;
+	reset-names = "i2s";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
index 7299eeadd588..60d59a54ca07 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
@@ -15,6 +15,11 @@ Required properties:
 - clocks : Must contain an entry for each entry in clock-names.
   See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
+  - d_audio
+  - apbif
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
   Tegra30 and later:
   - d_audio
   - apbif
@@ -26,7 +31,7 @@ Required properties:
   - dam0
   - dam1
   - dam2
-  - spdif_in
+  - spdif
   Tegra114 and later additionally require:
   - amx
   - adx
@@ -48,13 +53,15 @@ ahub@70080000 {
 	reg = <0x70080000 0x200 0x70080200 0x100>;
 	interrupts = < 0 103 0x04 >;
 	nvidia,dma-request-selector = <&apbdma 1>;
-	clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
+	clocks = <&tegra_car 106>, <&tegra_car 107>;
+	clock-names = "d_audio", "apbif";
+	resets = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
 		<&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
 		<&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
-		<&tegra_car 110>, <&tegra_car 162>;
-	clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+		<&tegra_car 110>, <&tegra_car 10>;
+	reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 		"i2s3", "i2s4", "dam0", "dam1", "dam2",
-		"spdif_in";
+		"spdif";
 	ranges;
 	#address-cells = <1>;
 	#size-cells = <1>;
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
index 7a3112bc135c..0c113ffe3814 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
@@ -5,6 +5,10 @@ Required properties:
 - reg : Should contain I2S registers location and length
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - i2s
 - nvidia,ahub-cif-ids : The list of AHUB CIF IDs for this port, rx (playback)
   first, tx (capture) second. See nvidia,tegra30-ahub.txt for values.
 
@@ -15,4 +19,6 @@ i2s@70080300 {
 	reg = <0x70080300 0x100>;
 	nvidia,ahub-cif-ids = <4 4>;
 	clocks = <&tegra_car 11>;
+	resets = <&tegra_car 11>;
+	reset-names = "i2s";
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
index d4f2d534934b..fcd9f67999de 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
@@ -10,6 +10,10 @@ Required properties:
   See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
   - spi
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - spi
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -26,5 +30,7 @@ spi@7000d600 {
 	#size-cells = <0>;
 	clocks = <&tegra_car 44>;
 	clock-names = "spi";
+	resets = <&tegra_car 44>;
+	reset-names = "spi";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
index 66e16c7f5939..e144f144717f 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
@@ -8,6 +8,10 @@ Required properties:
   request selector for this SFLASH controller.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - spi
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -24,5 +28,7 @@ spi@7000c380 {
 	#address-cells = <1>;
 	#size-cells = <0>;
 	clocks = <&tegra_car 43>;
+	resets = <&tegra_car 43>;
+	reset-names = "spi";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
index 0e6e94eb2b2a..9393e28f444b 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
@@ -8,6 +8,10 @@ Required properties:
   request selector for this SLINK controller.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - spi
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -24,5 +28,7 @@ spi@7000d600 {
 	#address-cells = <1>;
 	#size-cells = <0>;
 	clocks = <&tegra_car 44>;
+	resets = <&tegra_car 44>;
+	reset-names = "spi";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
index b98d0bdfa248..3dc9140e3dfb 100644
--- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
@@ -10,6 +10,10 @@ Required properties :
  - nvidia,phy : phandle of the PHY that the controller is connected to.
  - clocks : Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.
+ - resets : Must contain an entry for each entry in reset-names.
+   See ../reset/reset.txt for details.
+ - reset-names : Must include the following entries:
+   - usb
 
 Optional properties:
  - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20
-- 
1.8.1.5

[PATCH 02/31] ARM: tegra: document reset properties in DT bindings

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Update all the Tegra DT bindings to require resets/reset-names properties
where the HW module has reset inputs. Remove any entries from clocks or
clock-names that were only required to identify reset inputs, rather than
referring to real clocks.

This is a DT-ABI-incompatible change. It is the first of two changes
required for me to consider the Tegra DT bindings as stable, the other
being conversion to the common DMA DT bindings.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: devicetree at vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 .../bindings/clock/nvidia,tegra114-car.txt         |  4 ++
 .../bindings/clock/nvidia,tegra124-car.txt         |  4 ++
 .../bindings/clock/nvidia,tegra20-car.txt          |  4 ++
 .../bindings/clock/nvidia,tegra30-car.txt          |  4 ++
 .../devicetree/bindings/dma/tegra20-apbdma.txt     |  6 +++
 .../bindings/gpu/nvidia,tegra20-host1x.txt         | 63 ++++++++++++++++++++++
 .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt |  6 +++
 .../bindings/input/nvidia,tegra20-kbc.txt          |  6 +++
 .../bindings/mmc/nvidia,tegra20-sdhci.txt          |  6 +++
 .../devicetree/bindings/nvec/nvidia,nvec.txt       |  4 ++
 .../bindings/pci/nvidia,tegra20-pcie.txt           | 14 +++--
 .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt |  6 +++
 .../bindings/serial/nvidia,tegra20-hsuart.txt      |  6 +++
 .../bindings/sound/nvidia,tegra20-ac97.txt         |  6 +++
 .../bindings/sound/nvidia,tegra20-i2s.txt          |  6 +++
 .../bindings/sound/nvidia,tegra30-ahub.txt         | 17 ++++--
 .../bindings/sound/nvidia,tegra30-i2s.txt          |  6 +++
 .../bindings/spi/nvidia,tegra114-spi.txt           |  6 +++
 .../bindings/spi/nvidia,tegra20-sflash.txt         |  6 +++
 .../bindings/spi/nvidia,tegra20-slink.txt          |  6 +++
 .../bindings/usb/nvidia,tegra20-ehci.txt           |  4 ++
 21 files changed, 181 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
index 0c80c2677104..9acea9d93160 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
@@ -15,6 +15,9 @@ Required properties :
   In clock consumers, this cell represents the clock ID exposed by the
   CAR. The assignments may be found in header file
   <dt-bindings/clock/tegra114-car.h>.
+- #reset-cells : Should be 1.
+  In clock consumers, this cell represents the bit number in the CAR's
+  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
 
 Example SoC include file:
 
@@ -23,6 +26,7 @@ Example SoC include file:
 		compatible = "nvidia,tegra114-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	usb at c5004000 {
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
index 1a91ec60dee5..ded5d6212c84 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
@@ -15,6 +15,9 @@ Required properties :
   In clock consumers, this cell represents the clock ID exposed by the
   CAR. The assignments may be found in header file
   <dt-bindings/clock/tegra124-car.h>.
+- #reset-cells : Should be 1.
+  In clock consumers, this cell represents the bit number in the CAR's
+  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
 
 Example SoC include file:
 
@@ -23,6 +26,7 @@ Example SoC include file:
 		compatible = "nvidia,tegra124-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	usb at c5004000 {
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
index fcfed5bf73fb..6c5901b503d0 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -15,6 +15,9 @@ Required properties :
   In clock consumers, this cell represents the clock ID exposed by the
   CAR. The assignments may be found in header file
   <dt-bindings/clock/tegra20-car.h>.
+- #reset-cells : Should be 1.
+  In clock consumers, this cell represents the bit number in the CAR's
+  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
 
 Example SoC include file:
 
@@ -23,6 +26,7 @@ Example SoC include file:
 		compatible = "nvidia,tegra20-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	usb at c5004000 {
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
index 0f714081e986..63618cde12df 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
@@ -15,6 +15,9 @@ Required properties :
   In clock consumers, this cell represents the clock ID exposed by the
   CAR. The assignments may be found in header file
   <dt-bindings/clock/tegra30-car.h>.
+- #reset-cells : Should be 1.
+  In clock consumers, this cell represents the bit number in the CAR's
+  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
 
 Example SoC include file:
 
@@ -23,6 +26,7 @@ Example SoC include file:
 		compatible = "nvidia,tegra30-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	usb at c5004000 {
diff --git a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
index 74bfc54bb184..0b1e577ab9d3 100644
--- a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
+++ b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
@@ -7,6 +7,10 @@ Required properties:
 - interrupts: Should contain all of the per-channel DMA interrupts.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - dma
 
 Examples:
 
@@ -30,4 +34,6 @@ apbdma: dma at 6000a000 {
 		       0 150 0x04
 		       0 151 0x04 >;
 	clocks = <&tegra_car 34>;
+	resets = <&tegra_car 34>;
+	reset-names = "dma";
 };
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
index c9a715a75f60..8e22d234dc4c 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
@@ -11,6 +11,10 @@ Required properties:
 - ranges: The mapping of the host1x address space to the CPU address space.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - host1x
 
 The host1x top-level node defines a number of children, each representing one
 of the following host1x client modules:
@@ -23,6 +27,10 @@ of the following host1x client modules:
   - interrupts: The interrupt outputs from the controller.
   - clocks : Must contain one entry, for the module clock.
     See ../clocks/clock-bindings.txt for details.
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - mpe
 
 - vi: video input
 
@@ -32,6 +40,10 @@ of the following host1x client modules:
   - interrupts: The interrupt outputs from the controller.
   - clocks : Must contain one entry, for the module clock.
     See ../clocks/clock-bindings.txt for details.
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - vi
 
 - epp: encoder pre-processor
 
@@ -41,6 +53,10 @@ of the following host1x client modules:
   - interrupts: The interrupt outputs from the controller.
   - clocks : Must contain one entry, for the module clock.
     See ../clocks/clock-bindings.txt for details.
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - epp
 
 - isp: image signal processor
 
@@ -50,6 +66,10 @@ of the following host1x client modules:
   - interrupts: The interrupt outputs from the controller.
   - clocks : Must contain one entry, for the module clock.
     See ../clocks/clock-bindings.txt for details.
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - isp
 
 - gr2d: 2D graphics engine
 
@@ -59,6 +79,10 @@ of the following host1x client modules:
   - interrupts: The interrupt outputs from the controller.
   - clocks : Must contain one entry, for the module clock.
     See ../clocks/clock-bindings.txt for details.
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - 2d
 
 - gr3d: 3D graphics engine
 
@@ -74,6 +98,11 @@ of the following host1x client modules:
     - 3d
       This MUST be the first entry.
     - 3d2 (Only required on SoCs with two 3D clocks)
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - 3d
+    - 3d2 (Only required on SoCs with two 3D clocks)
 
 - dc: display controller
 
@@ -87,6 +116,10 @@ of the following host1x client modules:
     - disp1 or disp2 (depending on the controller instance)
       This MUST be the first entry.
     - parent
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - dc
 
   Each display controller node has a child node, named "rgb", that represents
   the RGB output associated with the controller. It can take the following
@@ -109,6 +142,10 @@ of the following host1x client modules:
     - hdmi
       This MUST be the first entry.
     - parent
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - hdmi
 
   Optional properties:
   - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
@@ -137,6 +174,10 @@ of the following host1x client modules:
     - dsi
       This MUST be the first entry.
     - parent
+  - resets : Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names : Must include the following entries:
+    - dsi
 
 Example:
 
@@ -149,6 +190,8 @@ Example:
 		interrupts = <0 65 0x04   /* mpcore syncpt */
 			      0 67 0x04>; /* mpcore general */
 		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
+		resets = <&tegra_car 28>;
+		reset-names = "host1x";
 
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -160,6 +203,8 @@ Example:
 			reg = <0x54040000 0x00040000>;
 			interrupts = <0 68 0x04>;
 			clocks = <&tegra_car TEGRA20_CLK_MPE>;
+			resets = <&tegra_car 60>;
+			reset-names = "mpe";
 		};
 
 		vi {
@@ -167,6 +212,8 @@ Example:
 			reg = <0x54080000 0x00040000>;
 			interrupts = <0 69 0x04>;
 			clocks = <&tegra_car TEGRA20_CLK_VI>;
+			resets = <&tegra_car 100>;
+			reset-names = "vi";
 		};
 
 		epp {
@@ -174,6 +221,8 @@ Example:
 			reg = <0x540c0000 0x00040000>;
 			interrupts = <0 70 0x04>;
 			clocks = <&tegra_car TEGRA20_CLK_EPP>;
+			resets = <&tegra_car 19>;
+			reset-names = "epp";
 		};
 
 		isp {
@@ -181,6 +230,8 @@ Example:
 			reg = <0x54100000 0x00040000>;
 			interrupts = <0 71 0x04>;
 			clocks = <&tegra_car TEGRA20_CLK_ISP>;
+			resets = <&tegra_car 23>;
+			reset-names = "isp";
 		};
 
 		gr2d {
@@ -188,12 +239,16 @@ Example:
 			reg = <0x54140000 0x00040000>;
 			interrupts = <0 72 0x04>;
 			clocks = <&tegra_car TEGRA20_CLK_GR2D>;
+			resets = <&tegra_car 21>;
+			reset-names = "2d";
 		};
 
 		gr3d {
 			compatible = "nvidia,tegra20-gr3d";
 			reg = <0x54180000 0x00040000>;
 			clocks = <&tegra_car TEGRA20_CLK_GR3D>;
+			resets = <&tegra_car 24>;
+			reset-names = "3d";
 		};
 
 		dc at 54200000 {
@@ -203,6 +258,8 @@ Example:
 			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
 				 <&tegra_car TEGRA20_CLK_PLL_P>;
 			clock-names = "disp1", "parent";
+			resets = <&tegra_car 27>;
+			reset-names = "dc";
 
 			rgb {
 				status = "disabled";
@@ -216,6 +273,8 @@ Example:
 			clocks = <&tegra_car TEGRA20_CLK_DISP2>,
 				 <&tegra_car TEGRA20_CLK_PLL_P>;
 			clock-names = "disp2", "parent";
+			resets = <&tegra_car 26>;
+			reset-names = "dc";
 
 			rgb {
 				status = "disabled";
@@ -229,6 +288,8 @@ Example:
 			clocks = <&tegra_car TEGRA20_CLK_HDMI>,
 				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 			clock-names = "hdmi", "parent";
+			resets = <&tegra_car 51>;
+			reset-names = "hdmi";
 			status = "disabled";
 		};
 
@@ -244,6 +305,8 @@ Example:
 			compatible = "nvidia,tegra20-dsi";
 			reg = <0x54300000 0x00040000>;
 			clocks = <&tegra_car TEGRA20_CLK_DSI>;
+			resets = <&tegra_car 48>;
+			reset-names = "dsi";
 			status = "disabled";
 		};
 	};
diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
index 96ab40131ae1..2b3af72dfb9c 100644
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
@@ -47,6 +47,10 @@ Required properties:
   - fast-clk
   Tegra114:
   - div-clk
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - i2c
 
 Example:
 
@@ -58,5 +62,7 @@ Example:
 		#size-cells = <0>;
 		clocks = <&tegra_car 12>, <&tegra_car 124>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 12>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
diff --git a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
index cc28d2194c37..83b14b6389fc 100644
--- a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
+++ b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
@@ -15,6 +15,10 @@ Required properties:
   devicetree/bindings/input/matrix-keymap.txt.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - kbc
 
 Optional properties, in addition to those specified by the shared
 matrix-keyboard bindings:
@@ -34,6 +38,8 @@ keyboard: keyboard {
 	reg = <0x7000e200 0x100>;
 	interrupts = <0 85 0x04>;
 	clocks = <&tegra_car 36>;
+	resets = <&tegra_car 36>;
+	reset-names = "kbc";
 	nvidia,ghost-filter;
 	nvidia,debounce-delay-ms = <640>;
 	nvidia,kbc-row-pins = <0 1 2>;    /* pin 0, 1, 2 as rows */
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
index f727902a9e8d..f357c16ea815 100644
--- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
@@ -10,6 +10,10 @@ Required properties:
 - compatible : Should be "nvidia,<chip>-sdhci"
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - sdhci
 
 Optional properties:
 - power-gpios : Specify GPIOs for power control
@@ -21,6 +25,8 @@ sdhci at c8000200 {
 	reg = <0xc8000200 0x200>;
 	interrupts = <47>;
 	clocks = <&tegra_car 14>;
+	resets = <&tegra_car 14>;
+	reset-names = "sdhci";
 	cd-gpios = <&gpio 69 0>; /* gpio PI5 */
 	wp-gpios = <&gpio 57 0>; /* gpio PH1 */
 	power-gpios = <&gpio 155 0>; /* gpio PT3 */
diff --git a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
index a97fe575ca29..5ae601e7f51f 100644
--- a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
+++ b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
@@ -15,3 +15,7 @@ Required properties:
   - fast-clk
   Tegra114:
   - div-clk
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - i2c
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
index ad2eb9804afa..6d91016100b3 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
@@ -47,9 +47,14 @@ Required properties:
 - clock-names : Must include the following entries:
   - pex
   - afi
-  - pcie_xclk
   - pll_e
   - cml (not required for Tegra20)
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - pex
+  - afi
+  - pcie_x
 
 Root ports are defined as subnodes of the PCIe controller node.
 
@@ -91,9 +96,10 @@ SoC DTSI:
 			  0x82000000 0 0xa0000000 0xa0000000 0 0x10000000   /* non-prefetchable memory */
 			  0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
 
-		clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>,
-			 <&tegra_car 118>;
-		clock-names = "pex", "afi", "pcie_xclk", "pll_e";
+		clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>;
+		clock-names = "pex", "afi", "pll_e";
+		resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>;
+		reset-names = "pex", "afi", "pcie_x";
 		status = "disabled";
 
 		pci at 1,0 {
diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
index 0d608d34fed0..a65d4c3be231 100644
--- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
@@ -9,6 +9,10 @@ Required properties:
   the cells format.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - pwm
 
 Example:
 
@@ -17,4 +21,6 @@ Example:
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
 		clocks = <&tegra_car 17>;
+		resets = <&tegra_car 17>;
+		reset-names = "pwm";
 	};
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
index 39148b6236a1..69ccdbe3760e 100644
--- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
+++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
@@ -8,6 +8,10 @@ Required properties:
   request selector for this UART controller.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - serial
 
 Optional properties:
 - nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
@@ -23,5 +27,7 @@ serial at 70006000 {
 	nvidia,dma-request-selector = <&apbdma 8>;
 	nvidia,enable-modem-interrupt;
 	clocks = <&tegra_car 6>;
+	resets = <&tegra_car 6>;
+	reset-names = "serial";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
index 37f4ebf5b184..2b6817f6e40e 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
@@ -6,6 +6,10 @@ Required properties:
 - interrupts : Should contain AC97 interrupt
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - ac97
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for the AC97 controller
 - nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the number
@@ -23,4 +27,6 @@ ac97 at 70002000 {
 	nvidia,codec-reset-gpio = <&gpio 170 0>;
 	nvidia,codec-sync-gpio = <&gpio 120 0>;
 	clocks = <&tegra_car 3>;
+	resets = <&tegra_car 3>;
+	reset-names = "ac97";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
index ba0c9452916d..8b070aeca3db 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
@@ -6,6 +6,10 @@ Required properties:
 - interrupts : Should contain I2S interrupt
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - i2s
 - nvidia,dma-request-selector : The Tegra DMA controller's phandle and
   request selector for this I2S controller
 
@@ -17,4 +21,6 @@ i2s at 70002800 {
 	interrupts = < 45 >;
 	nvidia,dma-request-selector = < &apbdma 2 >;
 	clocks = <&tegra_car 11>;
+	resets = <&tegra_car 11>;
+	reset-names = "i2s";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
index 7299eeadd588..60d59a54ca07 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
@@ -15,6 +15,11 @@ Required properties:
 - clocks : Must contain an entry for each entry in clock-names.
   See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
+  - d_audio
+  - apbif
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
   Tegra30 and later:
   - d_audio
   - apbif
@@ -26,7 +31,7 @@ Required properties:
   - dam0
   - dam1
   - dam2
-  - spdif_in
+  - spdif
   Tegra114 and later additionally require:
   - amx
   - adx
@@ -48,13 +53,15 @@ ahub at 70080000 {
 	reg = <0x70080000 0x200 0x70080200 0x100>;
 	interrupts = < 0 103 0x04 >;
 	nvidia,dma-request-selector = <&apbdma 1>;
-	clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
+	clocks = <&tegra_car 106>, <&tegra_car 107>;
+	clock-names = "d_audio", "apbif";
+	resets = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
 		<&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
 		<&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
-		<&tegra_car 110>, <&tegra_car 162>;
-	clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+		<&tegra_car 110>, <&tegra_car 10>;
+	reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 		"i2s3", "i2s4", "dam0", "dam1", "dam2",
-		"spdif_in";
+		"spdif";
 	ranges;
 	#address-cells = <1>;
 	#size-cells = <1>;
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
index 7a3112bc135c..0c113ffe3814 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
@@ -5,6 +5,10 @@ Required properties:
 - reg : Should contain I2S registers location and length
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - i2s
 - nvidia,ahub-cif-ids : The list of AHUB CIF IDs for this port, rx (playback)
   first, tx (capture) second. See nvidia,tegra30-ahub.txt for values.
 
@@ -15,4 +19,6 @@ i2s at 70080300 {
 	reg = <0x70080300 0x100>;
 	nvidia,ahub-cif-ids = <4 4>;
 	clocks = <&tegra_car 11>;
+	resets = <&tegra_car 11>;
+	reset-names = "i2s";
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
index d4f2d534934b..fcd9f67999de 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
@@ -10,6 +10,10 @@ Required properties:
   See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
   - spi
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - spi
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -26,5 +30,7 @@ spi at 7000d600 {
 	#size-cells = <0>;
 	clocks = <&tegra_car 44>;
 	clock-names = "spi";
+	resets = <&tegra_car 44>;
+	reset-names = "spi";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
index 66e16c7f5939..e144f144717f 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
@@ -8,6 +8,10 @@ Required properties:
   request selector for this SFLASH controller.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - spi
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -24,5 +28,7 @@ spi at 7000c380 {
 	#address-cells = <1>;
 	#size-cells = <0>;
 	clocks = <&tegra_car 43>;
+	resets = <&tegra_car 43>;
+	reset-names = "spi";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
index 0e6e94eb2b2a..9393e28f444b 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
@@ -8,6 +8,10 @@ Required properties:
   request selector for this SLINK controller.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - spi
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -24,5 +28,7 @@ spi at 7000d600 {
 	#address-cells = <1>;
 	#size-cells = <0>;
 	clocks = <&tegra_car 44>;
+	resets = <&tegra_car 44>;
+	reset-names = "spi";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
index b98d0bdfa248..3dc9140e3dfb 100644
--- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
@@ -10,6 +10,10 @@ Required properties :
  - nvidia,phy : phandle of the PHY that the controller is connected to.
  - clocks : Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.
+ - resets : Must contain an entry for each entry in reset-names.
+   See ../reset/reset.txt for details.
+ - reset-names : Must include the following entries:
+   - usb
 
 Optional properties:
  - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20
-- 
1.8.1.5

Re: [PATCH 02/31] ARM: tegra: document reset properties in DT bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 726 bytes --]

On Fri, Nov 15, 2013 at 01:53:57PM -0700, Stephen Warren wrote:
[...]
> diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
[...]
> +  - resets : Must contain an entry for each entry in reset-names.
> +    See ../reset/reset.txt for details.
> +  - reset-names : Must include the following entries:
> +    - dc

For consistency with this, the clock-names entry for the first clock in
this node should then be "dc" as well.

> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
[...]
> -  - spdif_in
> +  - spdif

Why is this renamed?

Thierry

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[PATCH 02/31] ARM: tegra: document reset properties in DT bindings

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:53:57PM -0700, Stephen Warren wrote:
[...]
> diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
[...]
> +  - resets : Must contain an entry for each entry in reset-names.
> +    See ../reset/reset.txt for details.
> +  - reset-names : Must include the following entries:
> +    - dc

For consistency with this, the clock-names entry for the first clock in
this node should then be "dc" as well.

> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
[...]
> -  - spdif_in
> +  - spdif

Why is this renamed?

Thierry
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Re: [PATCH 02/31] ARM: tegra: document reset properties in DT bindings

[Stephen Warren]

On 11/29/2013 05:23 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:57PM -0700, Stephen Warren wrote: 
> [...]
>> diff --git
>> a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
>> b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
>
>> 
[...]
>> +  - resets : Must contain an entry for each entry in
>> reset-names. +    See ../reset/reset.txt for details. +  -
>> reset-names : Must include the following entries: +    - dc
> 
> For consistency with this, the clock-names entry for the first
> clock in this node should then be "dc" as well.

The dc driver gets the clock by name, so this isn't a requirement.

>> diff --git
>> a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
>> b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
>
>> 
[...]
>> -  - spdif_in +  - spdif
> 
> Why is this renamed?

There are two separate clocks for the SPDIF input and output modules,
but just a single reset.

[PATCH 02/31] ARM: tegra: document reset properties in DT bindings

[Stephen Warren]

On 11/29/2013 05:23 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:57PM -0700, Stephen Warren wrote: 
> [...]
>> diff --git
>> a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
>> b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
>
>> 
[...]
>> +  - resets : Must contain an entry for each entry in
>> reset-names. +    See ../reset/reset.txt for details. +  -
>> reset-names : Must include the following entries: +    - dc
> 
> For consistency with this, the clock-names entry for the first
> clock in this node should then be "dc" as well.

The dc driver gets the clock by name, so this isn't a requirement.

>> diff --git
>> a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
>> b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
>
>> 
[...]
>> -  - spdif_in +  - spdif
> 
> Why is this renamed?

There are two separate clocks for the SPDIF input and output modules,
but just a single reset.

Re: [PATCH 02/31] ARM: tegra: document reset properties in DT bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1508 bytes --]

On Sun, Dec 01, 2013 at 12:06:49PM -0700, Stephen Warren wrote:
> On 11/29/2013 05:23 AM, Thierry Reding wrote:
> > On Fri, Nov 15, 2013 at 01:53:57PM -0700, Stephen Warren wrote: 
> > [...]
> >> diff --git
> >> a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> >> b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> >
> >> 
> [...]
> >> +  - resets : Must contain an entry for each entry in
> >> reset-names. +    See ../reset/reset.txt for details. +  -
> >> reset-names : Must include the following entries: +    - dc
> > 
> > For consistency with this, the clock-names entry for the first
> > clock in this node should then be "dc" as well.
> 
> The dc driver gets the clock by name, so this isn't a requirement.

Right, but like I've said in another reply, I'd very much like for this
to be fixed up so we don't have to mess around with per-instance names
for clocks. So instead of naming the first clock in the display
controller node "disp", we could rename it to "dc" for consistency with
the reset bindings.

> >> diff --git
> >> a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> >> b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> >
> >> 
> [...]
> >> -  - spdif_in +  - spdif
> > 
> > Why is this renamed?
> 
> There are two separate clocks for the SPDIF input and output modules,
> but just a single reset.

I also realized that when reviewing one of the subsequent patches.

Thierry

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[PATCH 02/31] ARM: tegra: document reset properties in DT bindings

[Thierry Reding]

On Sun, Dec 01, 2013 at 12:06:49PM -0700, Stephen Warren wrote:
> On 11/29/2013 05:23 AM, Thierry Reding wrote:
> > On Fri, Nov 15, 2013 at 01:53:57PM -0700, Stephen Warren wrote: 
> > [...]
> >> diff --git
> >> a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> >> b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> >
> >> 
> [...]
> >> +  - resets : Must contain an entry for each entry in
> >> reset-names. +    See ../reset/reset.txt for details. +  -
> >> reset-names : Must include the following entries: +    - dc
> > 
> > For consistency with this, the clock-names entry for the first
> > clock in this node should then be "dc" as well.
> 
> The dc driver gets the clock by name, so this isn't a requirement.

Right, but like I've said in another reply, I'd very much like for this
to be fixed up so we don't have to mess around with per-instance names
for clocks. So instead of naming the first clock in the display
controller node "disp", we could rename it to "dc" for consistency with
the reset bindings.

> >> diff --git
> >> a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> >> b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> >
> >> 
> [...]
> >> -  - spdif_in +  - spdif
> > 
> > Why is this renamed?
> 
> There are two separate clocks for the SPDIF input and output modules,
> but just a single reset.

I also realized that when reviewing one of the subsequent patches.

Thierry
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Re: [PATCH 02/31] ARM: tegra: document reset properties in DT bindings

[Stephen Warren]

On 12/02/2013 02:08 AM, Thierry Reding wrote:
> On Sun, Dec 01, 2013 at 12:06:49PM -0700, Stephen Warren wrote:
>> On 11/29/2013 05:23 AM, Thierry Reding wrote:
>>> On Fri, Nov 15, 2013 at 01:53:57PM -0700, Stephen Warren wrote:
>>>  [...]
>>>> diff --git 
>>>> a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
>>>>
>>>> 
b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
>>> 
>>>> 
>> [...]
>>>> +  - resets : Must contain an entry for each entry in 
>>>> reset-names. +    See ../reset/reset.txt for details. +  - 
>>>> reset-names : Must include the following entries: +    - dc
>>> 
>>> For consistency with this, the clock-names entry for the first 
>>> clock in this node should then be "dc" as well.
>> 
>> The dc driver gets the clock by name, so this isn't a
>> requirement.
> 
> Right, but like I've said in another reply, I'd very much like for
> this to be fixed up so we don't have to mess around with
> per-instance names for clocks. So instead of naming the first clock
> in the display controller node "disp", we could rename it to "dc"
> for consistency with the reset bindings.

I assume you're now OK with not changing the clock names, given my
explanation?

[PATCH 02/31] ARM: tegra: document reset properties in DT bindings

[Stephen Warren]

On 12/02/2013 02:08 AM, Thierry Reding wrote:
> On Sun, Dec 01, 2013 at 12:06:49PM -0700, Stephen Warren wrote:
>> On 11/29/2013 05:23 AM, Thierry Reding wrote:
>>> On Fri, Nov 15, 2013 at 01:53:57PM -0700, Stephen Warren wrote:
>>>  [...]
>>>> diff --git 
>>>> a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
>>>>
>>>> 
b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
>>> 
>>>> 
>> [...]
>>>> +  - resets : Must contain an entry for each entry in 
>>>> reset-names. +    See ../reset/reset.txt for details. +  - 
>>>> reset-names : Must include the following entries: +    - dc
>>> 
>>> For consistency with this, the clock-names entry for the first 
>>> clock in this node should then be "dc" as well.
>> 
>> The dc driver gets the clock by name, so this isn't a
>> requirement.
> 
> Right, but like I've said in another reply, I'd very much like for
> this to be fixed up so we don't have to mess around with
> per-instance names for clocks. So instead of naming the first clock
> in the display controller node "disp", we could rename it to "dc"
> for consistency with the reset bindings.

I assume you're now OK with not changing the clock names, given my
explanation?

Re: [PATCH 02/31] ARM: tegra: document reset properties in DT bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 2606 bytes --]

On Tue, Dec 03, 2013 at 11:48:33AM -0700, Stephen Warren wrote:
> On 12/02/2013 02:08 AM, Thierry Reding wrote:
> > On Sun, Dec 01, 2013 at 12:06:49PM -0700, Stephen Warren wrote:
> >> On 11/29/2013 05:23 AM, Thierry Reding wrote:
> >>> On Fri, Nov 15, 2013 at 01:53:57PM -0700, Stephen Warren wrote:
> >>>  [...]
> >>>> diff --git 
> >>>> a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> >>>>
> >>>> 
> b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> >>> 
> >>>> 
> >> [...]
> >>>> +  - resets : Must contain an entry for each entry in 
> >>>> reset-names. +    See ../reset/reset.txt for details. +  - 
> >>>> reset-names : Must include the following entries: +    - dc
> >>> 
> >>> For consistency with this, the clock-names entry for the first 
> >>> clock in this node should then be "dc" as well.
> >> 
> >> The dc driver gets the clock by name, so this isn't a
> >> requirement.
> > 
> > Right, but like I've said in another reply, I'd very much like for
> > this to be fixed up so we don't have to mess around with
> > per-instance names for clocks. So instead of naming the first clock
> > in the display controller node "disp", we could rename it to "dc"
> > for consistency with the reset bindings.
> 
> I assume you're now OK with not changing the clock names, given my
> explanation?

No. Rather I hope that I was able to clarify what I was aiming for. To
illustrate with another example: if we were to mirror the naming of the
clocks for the resets, the nodes would look like this:

	dc@54200000 {
		...
		clock-names = "disp1", "parent";
		...
		reset-names = "dc1";
	};

	dc@54240000 {
		...
		clock-names = "disp2", "parent";
		...
		reset-names = "dc2";
	};

Rather than what I proposed, which would be either:

	dc@54200000 {
		...
		clock-names = "disp", "parent";
		...
		reset-names = "dc";
	};

	dc@54240000 {
		...
		clock-names = "disp", "parent";
		...
		reset-names = "dc";
	};

Or this:

	dc@54200000 {
		...
		clock-names = "disp", "parent";
		...
		reset-names = "disp";
	};

	dc@54240000 {
		...
		clock-names = "disp", "parent";
		...
		reset-names = "disp";
	};

Or even this:

	dc@54200000 {
		...
		clock-names = "dc", "parent";
		...
		reset-names = "dc";
	};

	dc@54240000 {
		...
		clock-names = "dc", "parent";
		...
		reset-names = "dc";
	};

The display controller driver doesn't request the first clock by name,
so it doesn't really matter what it's called, but "disp1" and "disp2"
are just wrong in my opinion.

Thierry

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[PATCH 02/31] ARM: tegra: document reset properties in DT bindings

[Thierry Reding]

On Tue, Dec 03, 2013 at 11:48:33AM -0700, Stephen Warren wrote:
> On 12/02/2013 02:08 AM, Thierry Reding wrote:
> > On Sun, Dec 01, 2013 at 12:06:49PM -0700, Stephen Warren wrote:
> >> On 11/29/2013 05:23 AM, Thierry Reding wrote:
> >>> On Fri, Nov 15, 2013 at 01:53:57PM -0700, Stephen Warren wrote:
> >>>  [...]
> >>>> diff --git 
> >>>> a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> >>>>
> >>>> 
> b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
> >>> 
> >>>> 
> >> [...]
> >>>> +  - resets : Must contain an entry for each entry in 
> >>>> reset-names. +    See ../reset/reset.txt for details. +  - 
> >>>> reset-names : Must include the following entries: +    - dc
> >>> 
> >>> For consistency with this, the clock-names entry for the first 
> >>> clock in this node should then be "dc" as well.
> >> 
> >> The dc driver gets the clock by name, so this isn't a
> >> requirement.
> > 
> > Right, but like I've said in another reply, I'd very much like for
> > this to be fixed up so we don't have to mess around with
> > per-instance names for clocks. So instead of naming the first clock
> > in the display controller node "disp", we could rename it to "dc"
> > for consistency with the reset bindings.
> 
> I assume you're now OK with not changing the clock names, given my
> explanation?

No. Rather I hope that I was able to clarify what I was aiming for. To
illustrate with another example: if we were to mirror the naming of the
clocks for the resets, the nodes would look like this:

	dc at 54200000 {
		...
		clock-names = "disp1", "parent";
		...
		reset-names = "dc1";
	};

	dc at 54240000 {
		...
		clock-names = "disp2", "parent";
		...
		reset-names = "dc2";
	};

Rather than what I proposed, which would be either:

	dc at 54200000 {
		...
		clock-names = "disp", "parent";
		...
		reset-names = "dc";
	};

	dc at 54240000 {
		...
		clock-names = "disp", "parent";
		...
		reset-names = "dc";
	};

Or this:

	dc at 54200000 {
		...
		clock-names = "disp", "parent";
		...
		reset-names = "disp";
	};

	dc at 54240000 {
		...
		clock-names = "disp", "parent";
		...
		reset-names = "disp";
	};

Or even this:

	dc at 54200000 {
		...
		clock-names = "dc", "parent";
		...
		reset-names = "dc";
	};

	dc at 54240000 {
		...
		clock-names = "dc", "parent";
		...
		reset-names = "dc";
	};

The display controller driver doesn't request the first clock by name,
so it doesn't really matter what it's called, but "disp1" and "disp2"
are just wrong in my opinion.

Thierry
-------------- next part --------------
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[PATCH 03/31] ARM: tegra: document use of standard DMA DT bindings

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Update all the Tegra DT bindings to require the standard dmas/dma-names
properties rather than non-standard nvidia,dma-request-selector property.

This is a DT-ABI-incompatible change. It is the second of two changes
required for me to consider the Tegra DT bindings as stable, the other
being the previous conversion to the common reset bindings.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt     |  7 +++++++
 .../bindings/serial/nvidia,tegra20-hsuart.txt          | 10 +++++++---
 .../devicetree/bindings/sound/nvidia,tegra20-ac97.txt  | 14 +++++++++-----
 .../devicetree/bindings/sound/nvidia,tegra20-i2s.txt   | 14 +++++++++-----
 .../devicetree/bindings/sound/nvidia,tegra30-ahub.txt  | 18 +++++++++++++-----
 .../devicetree/bindings/spi/nvidia,tegra114-spi.txt    | 14 +++++++++-----
 .../devicetree/bindings/spi/nvidia,tegra20-sflash.txt  | 10 +++++++---
 .../devicetree/bindings/spi/nvidia,tegra20-slink.txt   | 10 +++++++---
 8 files changed, 68 insertions(+), 29 deletions(-)

diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
index 2b3af72dfb9c..13a7f9dc1681 100644
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
@@ -51,6 +51,11 @@ Required properties:
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - i2c
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
 
 Example:
 
@@ -64,5 +69,7 @@ Example:
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 12>;
 		reset-names = "i2c";
+		dmas = <&apbdma 16>, <&apbdma 16>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
index 69ccdbe3760e..e2b18972a674 100644
--- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
+++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
@@ -4,14 +4,17 @@ Required properties:
 - compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
 - reg: Should contain UART controller registers location and length.
 - interrupts: Should contain UART controller interrupts.
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for this UART controller.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
 - resets : Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - serial
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
 
 Optional properties:
 - nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
@@ -24,10 +27,11 @@ serial@70006000 {
 	reg = <0x70006000 0x40>;
 	reg-shift = <2>;
 	interrupts = <0 36 0x04>;
-	nvidia,dma-request-selector = <&apbdma 8>;
 	nvidia,enable-modem-interrupt;
 	clocks = <&tegra_car 6>;
 	resets = <&tegra_car 6>;
 	reset-names = "serial";
+	dmas = <&apbdma 8>, <&apbdma 8>;
+	dma-names = "rx", "tx";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
index 2b6817f6e40e..eaf00102d92c 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
@@ -4,14 +4,17 @@ Required properties:
 - compatible : "nvidia,tegra20-ac97"
 - reg : Should contain AC97 controller registers location and length
 - interrupts : Should contain AC97 interrupt
-- clocks : Must contain one entry, for the module clock.
-  See ../clocks/clock-bindings.txt for details.
 - resets : Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - ac97
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for the AC97 controller
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 - nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the number
   of the GPIO used to reset the external AC97 codec
 - nvidia,codec-sync-gpio : The Tegra GPIO controller's phandle and the number
@@ -23,10 +26,11 @@ ac97@70002000 {
 	compatible = "nvidia,tegra20-ac97";
 	reg = <0x70002000 0x200>;
 	interrupts = <0 81 0x04>;
-	nvidia,dma-request-selector = <&apbdma 12>;
 	nvidia,codec-reset-gpio = <&gpio 170 0>;
 	nvidia,codec-sync-gpio = <&gpio 120 0>;
 	clocks = <&tegra_car 3>;
 	resets = <&tegra_car 3>;
 	reset-names = "ac97";
+	dmas = <&apbdma 12>, <&apbdma 12>;
+	dma-names = "rx", "tx";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
index 8b070aeca3db..dc30c6bfbe95 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
@@ -4,14 +4,17 @@ Required properties:
 - compatible : "nvidia,tegra20-i2s"
 - reg : Should contain I2S registers location and length
 - interrupts : Should contain I2S interrupt
-- clocks : Must contain one entry, for the module clock.
-  See ../clocks/clock-bindings.txt for details.
 - resets : Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - i2s
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for this I2S controller
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Example:
 
@@ -19,8 +22,9 @@ i2s@70002800 {
 	compatible = "nvidia,tegra20-i2s";
 	reg = <0x70002800 0x200>;
 	interrupts = < 45 >;
-	nvidia,dma-request-selector = < &apbdma 2 >;
 	clocks = <&tegra_car 11>;
 	resets = <&tegra_car 11>;
 	reset-names = "i2s";
+	dmas = <&apbdma 21>, <&apbdma 21>;
+	dma-names = "rx", "tx";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
index 60d59a54ca07..3376ba42a209 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
@@ -7,11 +7,6 @@ Required properties:
   - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
   - Tegra114 requires an additional entry, for the APBIF2 register block.
 - interrupts : Should contain AHUB interrupt
-- nvidia,dma-request-selector : A list of the DMA channel specifiers. Each
-  entry contains the Tegra DMA controller's phandle and request selector.
-  If a single entry is present, the request selectors for the channels are
-  assumed to be contiguous, and increment from this value.
-  If multiple values are given, one value must be given per channel.
 - clocks : Must contain an entry for each entry in clock-names.
   See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
@@ -36,6 +31,14 @@ Required properties:
   - amx
   - adx
 - ranges : The bus address mapping for the configlink register bus.
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx0 .. rx<n>
+  - tx0 .. tx<n>
+  ... where n is:
+  Tegra30: 3
+  Tegra114, Tegra124: 9
   Can be empty since the mapping is 1:1.
 - #address-cells : For the configlink bus. Should be <1>;
 - #size-cells : For the configlink bus. Should be <1>.
@@ -62,6 +65,11 @@ ahub@70080000 {
 	reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 		"i2s3", "i2s4", "dam0", "dam1", "dam2",
 		"spdif";
+	dmas = <&apbdma 1>, <&apbdma 1>;
+	       <&apbdma 2>, <&apbdma 2>;
+	       <&apbdma 3>, <&apbdma 3>;
+	       <&apbdma 4>, <&apbdma 4>;
+	dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", "rx3", "tx3";
 	ranges;
 	#address-cells = <1>;
 	#size-cells = <1>;
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
index fcd9f67999de..7ea701e07dc2 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
@@ -4,16 +4,19 @@ Required properties:
 - compatible : should be "nvidia,tegra114-spi".
 - reg: Should contain SPI registers location and length.
 - interrupts: Should contain SPI interrupts.
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for this SPI controller.
-- clocks : Must contain an entry for each entry in clock-names.
-  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
   - spi
 - resets : Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - spi
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -24,7 +27,6 @@ spi@7000d600 {
 	compatible = "nvidia,tegra114-spi";
 	reg = <0x7000d600 0x200>;
 	interrupts = <0 82 0x04>;
-	nvidia,dma-request-selector = <&apbdma 16>;
 	spi-max-frequency = <25000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -32,5 +34,7 @@ spi@7000d600 {
 	clock-names = "spi";
 	resets = <&tegra_car 44>;
 	reset-names = "spi";
+	dmas = <&apbdma 16>, <&apbdma 16>;
+	dma-names = "rx", "tx";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
index e144f144717f..bdf08e6dec9b 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
@@ -4,14 +4,17 @@ Required properties:
 - compatible : should be "nvidia,tegra20-sflash".
 - reg: Should contain SFLASH registers location and length.
 - interrupts: Should contain SFLASH interrupts.
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for this SFLASH controller.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
 - resets : Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - spi
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -23,12 +26,13 @@ spi@7000c380 {
 	compatible = "nvidia,tegra20-sflash";
 	reg = <0x7000c380 0x80>;
 	interrupts = <0 39 0x04>;
-	nvidia,dma-request-selector = <&apbdma 16>;
 	spi-max-frequency = <25000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
 	clocks = <&tegra_car 43>;
 	resets = <&tegra_car 43>;
 	reset-names = "spi";
+	dmas = <&apbdma 11>, <&apbdma 11>;
+	dma-names = "rx", "tx";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
index 9393e28f444b..5db9144a33c8 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
@@ -4,14 +4,17 @@ Required properties:
 - compatible : should be "nvidia,tegra20-slink", "nvidia,tegra30-slink".
 - reg: Should contain SLINK registers location and length.
 - interrupts: Should contain SLINK interrupts.
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for this SLINK controller.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
 - resets : Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - spi
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -23,12 +26,13 @@ spi@7000d600 {
 	compatible = "nvidia,tegra20-slink";
 	reg = <0x7000d600 0x200>;
 	interrupts = <0 82 0x04>;
-	nvidia,dma-request-selector = <&apbdma 16>;
 	spi-max-frequency = <25000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
 	clocks = <&tegra_car 44>;
 	resets = <&tegra_car 44>;
 	reset-names = "spi";
+	dmas = <&apbdma 16>, <&apbdma 16>;
+	dma-names = "rx", "tx";
 	status = "disabled";
 };
-- 
1.8.1.5

[PATCH 03/31] ARM: tegra: document use of standard DMA DT bindings

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Update all the Tegra DT bindings to require the standard dmas/dma-names
properties rather than non-standard nvidia,dma-request-selector property.

This is a DT-ABI-incompatible change. It is the second of two changes
required for me to consider the Tegra DT bindings as stable, the other
being the previous conversion to the common reset bindings.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: devicetree at vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 .../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt     |  7 +++++++
 .../bindings/serial/nvidia,tegra20-hsuart.txt          | 10 +++++++---
 .../devicetree/bindings/sound/nvidia,tegra20-ac97.txt  | 14 +++++++++-----
 .../devicetree/bindings/sound/nvidia,tegra20-i2s.txt   | 14 +++++++++-----
 .../devicetree/bindings/sound/nvidia,tegra30-ahub.txt  | 18 +++++++++++++-----
 .../devicetree/bindings/spi/nvidia,tegra114-spi.txt    | 14 +++++++++-----
 .../devicetree/bindings/spi/nvidia,tegra20-sflash.txt  | 10 +++++++---
 .../devicetree/bindings/spi/nvidia,tegra20-slink.txt   | 10 +++++++---
 8 files changed, 68 insertions(+), 29 deletions(-)

diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
index 2b3af72dfb9c..13a7f9dc1681 100644
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
@@ -51,6 +51,11 @@ Required properties:
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - i2c
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
 
 Example:
 
@@ -64,5 +69,7 @@ Example:
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 12>;
 		reset-names = "i2c";
+		dmas = <&apbdma 16>, <&apbdma 16>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
index 69ccdbe3760e..e2b18972a674 100644
--- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
+++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
@@ -4,14 +4,17 @@ Required properties:
 - compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
 - reg: Should contain UART controller registers location and length.
 - interrupts: Should contain UART controller interrupts.
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for this UART controller.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
 - resets : Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - serial
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
 
 Optional properties:
 - nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
@@ -24,10 +27,11 @@ serial at 70006000 {
 	reg = <0x70006000 0x40>;
 	reg-shift = <2>;
 	interrupts = <0 36 0x04>;
-	nvidia,dma-request-selector = <&apbdma 8>;
 	nvidia,enable-modem-interrupt;
 	clocks = <&tegra_car 6>;
 	resets = <&tegra_car 6>;
 	reset-names = "serial";
+	dmas = <&apbdma 8>, <&apbdma 8>;
+	dma-names = "rx", "tx";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
index 2b6817f6e40e..eaf00102d92c 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
@@ -4,14 +4,17 @@ Required properties:
 - compatible : "nvidia,tegra20-ac97"
 - reg : Should contain AC97 controller registers location and length
 - interrupts : Should contain AC97 interrupt
-- clocks : Must contain one entry, for the module clock.
-  See ../clocks/clock-bindings.txt for details.
 - resets : Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - ac97
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for the AC97 controller
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 - nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the number
   of the GPIO used to reset the external AC97 codec
 - nvidia,codec-sync-gpio : The Tegra GPIO controller's phandle and the number
@@ -23,10 +26,11 @@ ac97 at 70002000 {
 	compatible = "nvidia,tegra20-ac97";
 	reg = <0x70002000 0x200>;
 	interrupts = <0 81 0x04>;
-	nvidia,dma-request-selector = <&apbdma 12>;
 	nvidia,codec-reset-gpio = <&gpio 170 0>;
 	nvidia,codec-sync-gpio = <&gpio 120 0>;
 	clocks = <&tegra_car 3>;
 	resets = <&tegra_car 3>;
 	reset-names = "ac97";
+	dmas = <&apbdma 12>, <&apbdma 12>;
+	dma-names = "rx", "tx";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
index 8b070aeca3db..dc30c6bfbe95 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
@@ -4,14 +4,17 @@ Required properties:
 - compatible : "nvidia,tegra20-i2s"
 - reg : Should contain I2S registers location and length
 - interrupts : Should contain I2S interrupt
-- clocks : Must contain one entry, for the module clock.
-  See ../clocks/clock-bindings.txt for details.
 - resets : Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - i2s
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for this I2S controller
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
+- clocks : Must contain one entry, for the module clock.
+  See ../clocks/clock-bindings.txt for details.
 
 Example:
 
@@ -19,8 +22,9 @@ i2s at 70002800 {
 	compatible = "nvidia,tegra20-i2s";
 	reg = <0x70002800 0x200>;
 	interrupts = < 45 >;
-	nvidia,dma-request-selector = < &apbdma 2 >;
 	clocks = <&tegra_car 11>;
 	resets = <&tegra_car 11>;
 	reset-names = "i2s";
+	dmas = <&apbdma 21>, <&apbdma 21>;
+	dma-names = "rx", "tx";
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
index 60d59a54ca07..3376ba42a209 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
@@ -7,11 +7,6 @@ Required properties:
   - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
   - Tegra114 requires an additional entry, for the APBIF2 register block.
 - interrupts : Should contain AHUB interrupt
-- nvidia,dma-request-selector : A list of the DMA channel specifiers. Each
-  entry contains the Tegra DMA controller's phandle and request selector.
-  If a single entry is present, the request selectors for the channels are
-  assumed to be contiguous, and increment from this value.
-  If multiple values are given, one value must be given per channel.
 - clocks : Must contain an entry for each entry in clock-names.
   See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
@@ -36,6 +31,14 @@ Required properties:
   - amx
   - adx
 - ranges : The bus address mapping for the configlink register bus.
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx0 .. rx<n>
+  - tx0 .. tx<n>
+  ... where n is:
+  Tegra30: 3
+  Tegra114, Tegra124: 9
   Can be empty since the mapping is 1:1.
 - #address-cells : For the configlink bus. Should be <1>;
 - #size-cells : For the configlink bus. Should be <1>.
@@ -62,6 +65,11 @@ ahub at 70080000 {
 	reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 		"i2s3", "i2s4", "dam0", "dam1", "dam2",
 		"spdif";
+	dmas = <&apbdma 1>, <&apbdma 1>;
+	       <&apbdma 2>, <&apbdma 2>;
+	       <&apbdma 3>, <&apbdma 3>;
+	       <&apbdma 4>, <&apbdma 4>;
+	dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", "rx3", "tx3";
 	ranges;
 	#address-cells = <1>;
 	#size-cells = <1>;
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
index fcd9f67999de..7ea701e07dc2 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
@@ -4,16 +4,19 @@ Required properties:
 - compatible : should be "nvidia,tegra114-spi".
 - reg: Should contain SPI registers location and length.
 - interrupts: Should contain SPI interrupts.
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for this SPI controller.
-- clocks : Must contain an entry for each entry in clock-names.
-  See ../clocks/clock-bindings.txt for details.
 - clock-names : Must include the following entries:
   - spi
 - resets : Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - spi
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -24,7 +27,6 @@ spi at 7000d600 {
 	compatible = "nvidia,tegra114-spi";
 	reg = <0x7000d600 0x200>;
 	interrupts = <0 82 0x04>;
-	nvidia,dma-request-selector = <&apbdma 16>;
 	spi-max-frequency = <25000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -32,5 +34,7 @@ spi at 7000d600 {
 	clock-names = "spi";
 	resets = <&tegra_car 44>;
 	reset-names = "spi";
+	dmas = <&apbdma 16>, <&apbdma 16>;
+	dma-names = "rx", "tx";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
index e144f144717f..bdf08e6dec9b 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
@@ -4,14 +4,17 @@ Required properties:
 - compatible : should be "nvidia,tegra20-sflash".
 - reg: Should contain SFLASH registers location and length.
 - interrupts: Should contain SFLASH interrupts.
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for this SFLASH controller.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
 - resets : Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - spi
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -23,12 +26,13 @@ spi at 7000c380 {
 	compatible = "nvidia,tegra20-sflash";
 	reg = <0x7000c380 0x80>;
 	interrupts = <0 39 0x04>;
-	nvidia,dma-request-selector = <&apbdma 16>;
 	spi-max-frequency = <25000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
 	clocks = <&tegra_car 43>;
 	resets = <&tegra_car 43>;
 	reset-names = "spi";
+	dmas = <&apbdma 11>, <&apbdma 11>;
+	dma-names = "rx", "tx";
 	status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
index 9393e28f444b..5db9144a33c8 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
@@ -4,14 +4,17 @@ Required properties:
 - compatible : should be "nvidia,tegra20-slink", "nvidia,tegra30-slink".
 - reg: Should contain SLINK registers location and length.
 - interrupts: Should contain SLINK interrupts.
-- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
-  request selector for this SLINK controller.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
 - resets : Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - spi
+- dmas : Must contain an entry for each entry in clock-names.
+  See ../dma/dma.txt for details.
+- dma-names : Must include the following entries:
+  - rx
+  - tx
 
 Recommended properties:
 - spi-max-frequency: Definition as per
@@ -23,12 +26,13 @@ spi at 7000d600 {
 	compatible = "nvidia,tegra20-slink";
 	reg = <0x7000d600 0x200>;
 	interrupts = <0 82 0x04>;
-	nvidia,dma-request-selector = <&apbdma 16>;
 	spi-max-frequency = <25000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
 	clocks = <&tegra_car 44>;
 	resets = <&tegra_car 44>;
 	reset-names = "spi";
+	dmas = <&apbdma 16>, <&apbdma 16>;
+	dma-names = "rx", "tx";
 	status = "disabled";
 };
-- 
1.8.1.5

Re: [PATCH 03/31] ARM: tegra: document use of standard DMA DT bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 6402 bytes --]

On Fri, Nov 15, 2013 at 01:53:58PM -0700, Stephen Warren wrote:
[...]
> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> index 2b6817f6e40e..eaf00102d92c 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> @@ -4,14 +4,17 @@ Required properties:
>  - compatible : "nvidia,tegra20-ac97"
>  - reg : Should contain AC97 controller registers location and length
>  - interrupts : Should contain AC97 interrupt
> -- clocks : Must contain one entry, for the module clock.
> -  See ../clocks/clock-bindings.txt for details.
>  - resets : Must contain an entry for each entry in reset-names.
>    See ../reset/reset.txt for details.
>  - reset-names : Must include the following entries:
>    - ac97
> -- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
> -  request selector for the AC97 controller
> +- dmas : Must contain an entry for each entry in clock-names.
> +  See ../dma/dma.txt for details.
> +- dma-names : Must include the following entries:
> +  - rx
> +  - tx
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.

Was this unintentionally moved?

> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
> index 8b070aeca3db..dc30c6bfbe95 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
> @@ -4,14 +4,17 @@ Required properties:
>  - compatible : "nvidia,tegra20-i2s"
>  - reg : Should contain I2S registers location and length
>  - interrupts : Should contain I2S interrupt
> -- clocks : Must contain one entry, for the module clock.
> -  See ../clocks/clock-bindings.txt for details.
>  - resets : Must contain an entry for each entry in reset-names.
>    See ../reset/reset.txt for details.
>  - reset-names : Must include the following entries:
>    - i2s
> -- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
> -  request selector for this I2S controller
> +- dmas : Must contain an entry for each entry in clock-names.
> +  See ../dma/dma.txt for details.
> +- dma-names : Must include the following entries:
> +  - rx
> +  - tx
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.

This too?

> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> index 60d59a54ca07..3376ba42a209 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> @@ -7,11 +7,6 @@ Required properties:
>    - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
>    - Tegra114 requires an additional entry, for the APBIF2 register block.
>  - interrupts : Should contain AHUB interrupt
> -- nvidia,dma-request-selector : A list of the DMA channel specifiers. Each
> -  entry contains the Tegra DMA controller's phandle and request selector.
> -  If a single entry is present, the request selectors for the channels are
> -  assumed to be contiguous, and increment from this value.
> -  If multiple values are given, one value must be given per channel.
>  - clocks : Must contain an entry for each entry in clock-names.
>    See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> @@ -36,6 +31,14 @@ Required properties:
>    - amx
>    - adx
>  - ranges : The bus address mapping for the configlink register bus.
> +- dmas : Must contain an entry for each entry in clock-names.
> +  See ../dma/dma.txt for details.
> +- dma-names : Must include the following entries:
> +  - rx0 .. rx<n>
> +  - tx0 .. tx<n>
> +  ... where n is:
> +  Tegra30: 3
> +  Tegra114, Tegra124: 9
>    Can be empty since the mapping is 1:1.

I think this line belongs to the description of the "ranges" property.

> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> index fcd9f67999de..7ea701e07dc2 100644
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> @@ -4,16 +4,19 @@ Required properties:
>  - compatible : should be "nvidia,tegra114-spi".
>  - reg: Should contain SPI registers location and length.
>  - interrupts: Should contain SPI interrupts.
> -- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
> -  request selector for this SPI controller.
> -- clocks : Must contain an entry for each entry in clock-names.
> -  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
>    - spi
>  - resets : Must contain an entry for each entry in reset-names.
>    See ../reset/reset.txt for details.
>  - reset-names : Must include the following entries:
>    - spi
> +- dmas : Must contain an entry for each entry in clock-names.
> +  See ../dma/dma.txt for details.
> +- dma-names : Must include the following entries:
> +  - rx
> +  - tx
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.

Another accidental move? I beginning to think there might be a pattern
to this, but I haven't figured it out yet.

> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> index e144f144717f..bdf08e6dec9b 100644
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> @@ -4,14 +4,17 @@ Required properties:
>  - compatible : should be "nvidia,tegra20-sflash".
>  - reg: Should contain SFLASH registers location and length.
>  - interrupts: Should contain SFLASH interrupts.
> -- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
> -  request selector for this SFLASH controller.
>  - clocks : Must contain one entry, for the module clock.

But then this doesn't move it... perhaps it really is accidental in
other places. =)

Thierry

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[PATCH 03/31] ARM: tegra: document use of standard DMA DT bindings

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:53:58PM -0700, Stephen Warren wrote:
[...]
> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> index 2b6817f6e40e..eaf00102d92c 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> @@ -4,14 +4,17 @@ Required properties:
>  - compatible : "nvidia,tegra20-ac97"
>  - reg : Should contain AC97 controller registers location and length
>  - interrupts : Should contain AC97 interrupt
> -- clocks : Must contain one entry, for the module clock.
> -  See ../clocks/clock-bindings.txt for details.
>  - resets : Must contain an entry for each entry in reset-names.
>    See ../reset/reset.txt for details.
>  - reset-names : Must include the following entries:
>    - ac97
> -- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
> -  request selector for the AC97 controller
> +- dmas : Must contain an entry for each entry in clock-names.
> +  See ../dma/dma.txt for details.
> +- dma-names : Must include the following entries:
> +  - rx
> +  - tx
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.

Was this unintentionally moved?

> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
> index 8b070aeca3db..dc30c6bfbe95 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
> @@ -4,14 +4,17 @@ Required properties:
>  - compatible : "nvidia,tegra20-i2s"
>  - reg : Should contain I2S registers location and length
>  - interrupts : Should contain I2S interrupt
> -- clocks : Must contain one entry, for the module clock.
> -  See ../clocks/clock-bindings.txt for details.
>  - resets : Must contain an entry for each entry in reset-names.
>    See ../reset/reset.txt for details.
>  - reset-names : Must include the following entries:
>    - i2s
> -- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
> -  request selector for this I2S controller
> +- dmas : Must contain an entry for each entry in clock-names.
> +  See ../dma/dma.txt for details.
> +- dma-names : Must include the following entries:
> +  - rx
> +  - tx
> +- clocks : Must contain one entry, for the module clock.
> +  See ../clocks/clock-bindings.txt for details.

This too?

> diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> index 60d59a54ca07..3376ba42a209 100644
> --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> @@ -7,11 +7,6 @@ Required properties:
>    - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
>    - Tegra114 requires an additional entry, for the APBIF2 register block.
>  - interrupts : Should contain AHUB interrupt
> -- nvidia,dma-request-selector : A list of the DMA channel specifiers. Each
> -  entry contains the Tegra DMA controller's phandle and request selector.
> -  If a single entry is present, the request selectors for the channels are
> -  assumed to be contiguous, and increment from this value.
> -  If multiple values are given, one value must be given per channel.
>  - clocks : Must contain an entry for each entry in clock-names.
>    See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
> @@ -36,6 +31,14 @@ Required properties:
>    - amx
>    - adx
>  - ranges : The bus address mapping for the configlink register bus.
> +- dmas : Must contain an entry for each entry in clock-names.
> +  See ../dma/dma.txt for details.
> +- dma-names : Must include the following entries:
> +  - rx0 .. rx<n>
> +  - tx0 .. tx<n>
> +  ... where n is:
> +  Tegra30: 3
> +  Tegra114, Tegra124: 9
>    Can be empty since the mapping is 1:1.

I think this line belongs to the description of the "ranges" property.

> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> index fcd9f67999de..7ea701e07dc2 100644
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
> @@ -4,16 +4,19 @@ Required properties:
>  - compatible : should be "nvidia,tegra114-spi".
>  - reg: Should contain SPI registers location and length.
>  - interrupts: Should contain SPI interrupts.
> -- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
> -  request selector for this SPI controller.
> -- clocks : Must contain an entry for each entry in clock-names.
> -  See ../clocks/clock-bindings.txt for details.
>  - clock-names : Must include the following entries:
>    - spi
>  - resets : Must contain an entry for each entry in reset-names.
>    See ../reset/reset.txt for details.
>  - reset-names : Must include the following entries:
>    - spi
> +- dmas : Must contain an entry for each entry in clock-names.
> +  See ../dma/dma.txt for details.
> +- dma-names : Must include the following entries:
> +  - rx
> +  - tx
> +- clocks : Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.

Another accidental move? I beginning to think there might be a pattern
to this, but I haven't figured it out yet.

> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> index e144f144717f..bdf08e6dec9b 100644
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> @@ -4,14 +4,17 @@ Required properties:
>  - compatible : should be "nvidia,tegra20-sflash".
>  - reg: Should contain SFLASH registers location and length.
>  - interrupts: Should contain SFLASH interrupts.
> -- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
> -  request selector for this SFLASH controller.
>  - clocks : Must contain one entry, for the module clock.

But then this doesn't move it... perhaps it really is accidental in
other places. =)

Thierry
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Re: [PATCH 03/31] ARM: tegra: document use of standard DMA DT bindings

[Stephen Warren]

On 11/29/2013 05:29 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:58PM -0700, Stephen Warren wrote: 
> [...]
>> diff --git
>> a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
>> b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
>>
>> 
index 2b6817f6e40e..eaf00102d92c 100644
>> ---
>> a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
>>
>> 
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
>> @@ -4,14 +4,17 @@ Required properties: - compatible :
>> "nvidia,tegra20-ac97" - reg : Should contain AC97 controller
>> registers location and length - interrupts : Should contain AC97
>> interrupt -- clocks : Must contain one entry, for the module
>> clock. -  See ../clocks/clock-bindings.txt for details. - resets
>> : Must contain an entry for each entry in reset-names. See
>> ../reset/reset.txt for details. - reset-names : Must include the
>> following entries: - ac97 -- nvidia,dma-request-selector : The
>> Tegra DMA controller's phandle and -  request selector for the
>> AC97 controller +- dmas : Must contain an entry for each entry in
>> clock-names. +  See ../dma/dma.txt for details. +- dma-names :
>> Must include the following entries: +  - rx +  - tx +- clocks :
>> Must contain one entry, for the module clock. +  See
>> ../clocks/clock-bindings.txt for details.
> 
> Was this unintentionally moved?

IIRC, at the end of the series, each binding describes reg,
interrupts, clocks, reset, dmas in that order, for consistency.

>> diff --git
>> a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
>> b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
>>
>> 
index e144f144717f..bdf08e6dec9b 100644
>> ---
>> a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
>>
>> 
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
>> @@ -4,14 +4,17 @@ Required properties: - compatible : should be
>> "nvidia,tegra20-sflash". - reg: Should contain SFLASH registers
>> location and length. - interrupts: Should contain SFLASH
>> interrupts. -- nvidia,dma-request-selector : The Tegra DMA
>> controller's phandle and -  request selector for this SFLASH
>> controller. - clocks : Must contain one entry, for the module
>> clock.
> 
> But then this doesn't move it... perhaps it really is accidental
> in other places. =)

The patch to that file does move the docs for the dmas property...

[PATCH 03/31] ARM: tegra: document use of standard DMA DT bindings

[Stephen Warren]

On 11/29/2013 05:29 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:58PM -0700, Stephen Warren wrote: 
> [...]
>> diff --git
>> a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
>> b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
>>
>> 
index 2b6817f6e40e..eaf00102d92c 100644
>> ---
>> a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
>>
>> 
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
>> @@ -4,14 +4,17 @@ Required properties: - compatible :
>> "nvidia,tegra20-ac97" - reg : Should contain AC97 controller
>> registers location and length - interrupts : Should contain AC97
>> interrupt -- clocks : Must contain one entry, for the module
>> clock. -  See ../clocks/clock-bindings.txt for details. - resets
>> : Must contain an entry for each entry in reset-names. See
>> ../reset/reset.txt for details. - reset-names : Must include the
>> following entries: - ac97 -- nvidia,dma-request-selector : The
>> Tegra DMA controller's phandle and -  request selector for the
>> AC97 controller +- dmas : Must contain an entry for each entry in
>> clock-names. +  See ../dma/dma.txt for details. +- dma-names :
>> Must include the following entries: +  - rx +  - tx +- clocks :
>> Must contain one entry, for the module clock. +  See
>> ../clocks/clock-bindings.txt for details.
> 
> Was this unintentionally moved?

IIRC, at the end of the series, each binding describes reg,
interrupts, clocks, reset, dmas in that order, for consistency.

>> diff --git
>> a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
>> b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
>>
>> 
index e144f144717f..bdf08e6dec9b 100644
>> ---
>> a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
>>
>> 
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
>> @@ -4,14 +4,17 @@ Required properties: - compatible : should be
>> "nvidia,tegra20-sflash". - reg: Should contain SFLASH registers
>> location and length. - interrupts: Should contain SFLASH
>> interrupts. -- nvidia,dma-request-selector : The Tegra DMA
>> controller's phandle and -  request selector for this SFLASH
>> controller. - clocks : Must contain one entry, for the module
>> clock.
> 
> But then this doesn't move it... perhaps it really is accidental
> in other places. =)

The patch to that file does move the docs for the dmas property...

Re: [PATCH 03/31] ARM: tegra: document use of standard DMA DT bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 2973 bytes --]

On Sun, Dec 01, 2013 at 12:09:51PM -0700, Stephen Warren wrote:
> On 11/29/2013 05:29 AM, Thierry Reding wrote:
> > On Fri, Nov 15, 2013 at 01:53:58PM -0700, Stephen Warren wrote: 
> > [...]
> >> diff --git
> >> a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> >> b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> >>
> >> 
> index 2b6817f6e40e..eaf00102d92c 100644
> >> ---
> >> a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> >>
> >> 
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> >> @@ -4,14 +4,17 @@ Required properties: - compatible :
> >> "nvidia,tegra20-ac97" - reg : Should contain AC97 controller
> >> registers location and length - interrupts : Should contain AC97
> >> interrupt -- clocks : Must contain one entry, for the module
> >> clock. -  See ../clocks/clock-bindings.txt for details. - resets
> >> : Must contain an entry for each entry in reset-names. See
> >> ../reset/reset.txt for details. - reset-names : Must include the
> >> following entries: - ac97 -- nvidia,dma-request-selector : The
> >> Tegra DMA controller's phandle and -  request selector for the
> >> AC97 controller +- dmas : Must contain an entry for each entry in
> >> clock-names. +  See ../dma/dma.txt for details. +- dma-names :
> >> Must include the following entries: +  - rx +  - tx +- clocks :
> >> Must contain one entry, for the module clock. +  See
> >> ../clocks/clock-bindings.txt for details.
> > 
> > Was this unintentionally moved?
> 
> IIRC, at the end of the series, each binding describes reg,
> interrupts, clocks, reset, dmas in that order, for consistency.

Okay, that's fine then. I was just making sure this hadn't slipped
through the cracks.

> >> diff --git
> >> a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> >> b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> >>
> >> 
> index e144f144717f..bdf08e6dec9b 100644
> >> ---
> >> a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> >>
> >> 
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> >> @@ -4,14 +4,17 @@ Required properties: - compatible : should be
> >> "nvidia,tegra20-sflash". - reg: Should contain SFLASH registers
> >> location and length. - interrupts: Should contain SFLASH
> >> interrupts. -- nvidia,dma-request-selector : The Tegra DMA
> >> controller's phandle and -  request selector for this SFLASH
> >> controller. - clocks : Must contain one entry, for the module
> >> clock.
> > 
> > But then this doesn't move it... perhaps it really is accidental
> > in other places. =)
> 
> The patch to that file does move the docs for the dmas property...

My point was that the clocks and clock-names properties didn't move like
they did for other hunks. But if all those changes end up making the
bindings documentation more consistent, then I'm all for it.

Thierry

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[PATCH 03/31] ARM: tegra: document use of standard DMA DT bindings

[Thierry Reding]

On Sun, Dec 01, 2013 at 12:09:51PM -0700, Stephen Warren wrote:
> On 11/29/2013 05:29 AM, Thierry Reding wrote:
> > On Fri, Nov 15, 2013 at 01:53:58PM -0700, Stephen Warren wrote: 
> > [...]
> >> diff --git
> >> a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> >> b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> >>
> >> 
> index 2b6817f6e40e..eaf00102d92c 100644
> >> ---
> >> a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> >>
> >> 
> +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
> >> @@ -4,14 +4,17 @@ Required properties: - compatible :
> >> "nvidia,tegra20-ac97" - reg : Should contain AC97 controller
> >> registers location and length - interrupts : Should contain AC97
> >> interrupt -- clocks : Must contain one entry, for the module
> >> clock. -  See ../clocks/clock-bindings.txt for details. - resets
> >> : Must contain an entry for each entry in reset-names. See
> >> ../reset/reset.txt for details. - reset-names : Must include the
> >> following entries: - ac97 -- nvidia,dma-request-selector : The
> >> Tegra DMA controller's phandle and -  request selector for the
> >> AC97 controller +- dmas : Must contain an entry for each entry in
> >> clock-names. +  See ../dma/dma.txt for details. +- dma-names :
> >> Must include the following entries: +  - rx +  - tx +- clocks :
> >> Must contain one entry, for the module clock. +  See
> >> ../clocks/clock-bindings.txt for details.
> > 
> > Was this unintentionally moved?
> 
> IIRC, at the end of the series, each binding describes reg,
> interrupts, clocks, reset, dmas in that order, for consistency.

Okay, that's fine then. I was just making sure this hadn't slipped
through the cracks.

> >> diff --git
> >> a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> >> b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> >>
> >> 
> index e144f144717f..bdf08e6dec9b 100644
> >> ---
> >> a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> >>
> >> 
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
> >> @@ -4,14 +4,17 @@ Required properties: - compatible : should be
> >> "nvidia,tegra20-sflash". - reg: Should contain SFLASH registers
> >> location and length. - interrupts: Should contain SFLASH
> >> interrupts. -- nvidia,dma-request-selector : The Tegra DMA
> >> controller's phandle and -  request selector for this SFLASH
> >> controller. - clocks : Must contain one entry, for the module
> >> clock.
> > 
> > But then this doesn't move it... perhaps it really is accidental
> > in other places. =)
> 
> The patch to that file does move the docs for the dmas property...

My point was that the clocks and clock-names properties didn't move like
they did for other hunks. But if all those changes end up making the
bindings documentation more consistent, then I'm all for it.

Thierry
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Re: [PATCH 03/31] ARM: tegra: document use of standard DMA DT bindings

[Stephen Warren]

On 11/29/2013 05:29 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:58PM -0700, Stephen Warren wrote:

>> diff --git
>> a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
>> b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt

>>
>> 
- ranges : The bus address mapping for the configlink register bus.
>> +- dmas : Must contain an entry for each entry in clock-names. +
>> See ../dma/dma.txt for details. +- dma-names : Must include the
>> following entries: +  - rx0 .. rx<n> +  - tx0 .. tx<n> +  ...
>> where n is: +  Tegra30: 3 +  Tegra114, Tegra124: 9 Can be empty
>> since the mapping is 1:1.
> 
> I think this line belongs to the description of the "ranges"
> property.

Yes, I've fixed that up locally simply by moving the inserted lines 1
line lower. I assume you don't want a repost for that?

[PATCH 03/31] ARM: tegra: document use of standard DMA DT bindings

[Stephen Warren]

On 11/29/2013 05:29 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:58PM -0700, Stephen Warren wrote:

>> diff --git
>> a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
>> b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt

>>
>> 
- ranges : The bus address mapping for the configlink register bus.
>> +- dmas : Must contain an entry for each entry in clock-names. +
>> See ../dma/dma.txt for details. +- dma-names : Must include the
>> following entries: +  - rx0 .. rx<n> +  - tx0 .. tx<n> +  ...
>> where n is: +  Tegra30: 3 +  Tegra114, Tegra124: 9 Can be empty
>> since the mapping is 1:1.
> 
> I think this line belongs to the description of the "ranges"
> property.

Yes, I've fixed that up locally simply by moving the inserted lines 1
line lower. I assume you don't want a repost for that?

Re: [PATCH 03/31] ARM: tegra: document use of standard DMA DT bindings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1005 bytes --]

On Tue, Dec 03, 2013 at 11:52:23AM -0700, Stephen Warren wrote:
> On 11/29/2013 05:29 AM, Thierry Reding wrote:
> > On Fri, Nov 15, 2013 at 01:53:58PM -0700, Stephen Warren wrote:
> 
> >> diff --git
> >> a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> >> b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> 
> >>
> >> 
> - ranges : The bus address mapping for the configlink register bus.
> >> +- dmas : Must contain an entry for each entry in clock-names. +
> >> See ../dma/dma.txt for details. +- dma-names : Must include the
> >> following entries: +  - rx0 .. rx<n> +  - tx0 .. tx<n> +  ...
> >> where n is: +  Tegra30: 3 +  Tegra114, Tegra124: 9 Can be empty
> >> since the mapping is 1:1.
> > 
> > I think this line belongs to the description of the "ranges"
> > property.
> 
> Yes, I've fixed that up locally simply by moving the inserted lines 1
> line lower. I assume you don't want a repost for that?

No need for a repost.

Thierry

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[PATCH 03/31] ARM: tegra: document use of standard DMA DT bindings

[Thierry Reding]

On Tue, Dec 03, 2013 at 11:52:23AM -0700, Stephen Warren wrote:
> On 11/29/2013 05:29 AM, Thierry Reding wrote:
> > On Fri, Nov 15, 2013 at 01:53:58PM -0700, Stephen Warren wrote:
> 
> >> diff --git
> >> a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> >> b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
> 
> >>
> >> 
> - ranges : The bus address mapping for the configlink register bus.
> >> +- dmas : Must contain an entry for each entry in clock-names. +
> >> See ../dma/dma.txt for details. +- dma-names : Must include the
> >> following entries: +  - rx0 .. rx<n> +  - tx0 .. tx<n> +  ...
> >> where n is: +  Tegra30: 3 +  Tegra114, Tegra124: 9 Can be empty
> >> since the mapping is 1:1.
> > 
> > I think this line belongs to the description of the "ranges"
> > property.
> 
> Yes, I've fixed that up locally simply by moving the inserted lines 1
> line lower. I assume you don't want a repost for that?

No need for a repost.

Thierry
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[PATCH 04/31] ARM: tegra: update DT files to add reset properties

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

An earlier patch updated the Tegra DT bindings to require resets and
reset-names properties to be filled in. This patch updates the DT files
to include those properties.

Note that any legacy clocks and clock-names entries that are replaced by
reset properties are not yet removed; the drivers must be updated to use
the new resets and reset-names properties first.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/tegra114.dtsi     |  83 ++++++++++++++++++++++++++--
 arch/arm/boot/dts/tegra20-paz00.dts |   2 +
 arch/arm/boot/dts/tegra20.dtsi      |  81 ++++++++++++++++++++++++++++
 arch/arm/boot/dts/tegra30.dtsi      | 104 ++++++++++++++++++++++++++++++++++++
 4 files changed, 266 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 8d42787c8ff1..c40dbdcb3741 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -43,6 +43,7 @@
 		compatible = "nvidia,tegra114-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	apbdma: dma {
@@ -81,6 +82,8 @@
 			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
+		resets = <&tegra_car 34>;
+		reset-names = "dma";
 	};
 
 	ahb: ahb {
@@ -125,8 +128,10 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 8>;
-		status = "disabled";
 		clocks = <&tegra_car TEGRA114_CLK_UARTA>;
+		resets = <&tegra_car 6>;
+		reset-names = "serial";
+		status = "disabled";
 	};
 
 	uartb: serial@70006040 {
@@ -135,8 +140,10 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 9>;
-		status = "disabled";
 		clocks = <&tegra_car TEGRA114_CLK_UARTB>;
+		resets = <&tegra_car 7>;
+		reset-names = "serial";
+		status = "disabled";
 	};
 
 	uartc: serial@70006200 {
@@ -145,8 +152,10 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 10>;
-		status = "disabled";
 		clocks = <&tegra_car TEGRA114_CLK_UARTC>;
+		resets = <&tegra_car 55>;
+		reset-names = "serial";
+		status = "disabled";
 	};
 
 	uartd: serial@70006300 {
@@ -155,8 +164,10 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 19>;
-		status = "disabled";
 		clocks = <&tegra_car TEGRA114_CLK_UARTD>;
+		resets = <&tegra_car 65>;
+		reset-names = "serial";
+		status = "disabled";
 	};
 
 	pwm: pwm {
@@ -164,6 +175,8 @@
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
 		clocks = <&tegra_car TEGRA114_CLK_PWM>;
+		resets = <&tegra_car 17>;
+		reset-names = "pwm";
 		status = "disabled";
 	};
 
@@ -175,6 +188,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_I2C1>;
 		clock-names = "div-clk";
+		resets = <&tegra_car 12>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -186,6 +201,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_I2C2>;
 		clock-names = "div-clk";
+		resets = <&tegra_car 54>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -197,6 +214,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_I2C3>;
 		clock-names = "div-clk";
+		resets = <&tegra_car 67>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -208,6 +227,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_I2C4>;
 		clock-names = "div-clk";
+		resets = <&tegra_car 103>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -219,6 +240,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_I2C5>;
 		clock-names = "div-clk";
+		resets = <&tegra_car 47>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -231,6 +254,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC1>;
 		clock-names = "spi";
+		resets = <&tegra_car 41>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -243,6 +268,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC2>;
 		clock-names = "spi";
+		resets = <&tegra_car 44>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -255,6 +282,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC3>;
 		clock-names = "spi";
+		resets = <&tegra_car 46>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -267,6 +296,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC4>;
 		clock-names = "spi";
+		resets = <&tegra_car 68>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -279,6 +310,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC5>;
 		clock-names = "spi";
+		resets = <&tegra_car 104>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -291,6 +324,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC6>;
 		clock-names = "spi";
+		resets = <&tegra_car 105>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -306,6 +341,8 @@
 		reg = <0x7000e200 0x100>;
 		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA114_CLK_KBC>;
+		resets = <&tegra_car 36>;
+		reset-names = "kbc";
 		status = "disabled";
 	};
 
@@ -353,6 +390,22 @@
 		clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
 			      "spdif_in", "amx", "adx";
+		resets = <&tegra_car 106>, /* d_audio */
+			 <&tegra_car 107>, /* apbif */
+			 <&tegra_car 30>,  /* i2s0 */
+			 <&tegra_car 11>,  /* i2s1 */
+			 <&tegra_car 18>,  /* i2s2 */
+			 <&tegra_car 101>, /* i2s3 */
+			 <&tegra_car 102>, /* i2s4 */
+			 <&tegra_car 108>, /* dam0 */
+			 <&tegra_car 109>, /* dam1 */
+			 <&tegra_car 110>, /* dam2 */
+			 <&tegra_car 10>,  /* spdif */
+			 <&tegra_car 153>, /* amx */
+			 <&tegra_car 154>; /* adx */
+		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
+			      "spdif", "amx", "adx";
 		ranges;
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -362,6 +415,8 @@
 			reg = <0x70080300 0x100>;
 			nvidia,ahub-cif-ids = <4 4>;
 			clocks = <&tegra_car TEGRA114_CLK_I2S0>;
+			resets = <&tegra_car 30>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -370,6 +425,8 @@
 			reg = <0x70080400 0x100>;
 			nvidia,ahub-cif-ids = <5 5>;
 			clocks = <&tegra_car TEGRA114_CLK_I2S1>;
+			resets = <&tegra_car 11>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -378,6 +435,8 @@
 			reg = <0x70080500 0x100>;
 			nvidia,ahub-cif-ids = <6 6>;
 			clocks = <&tegra_car TEGRA114_CLK_I2S2>;
+			resets = <&tegra_car 18>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -386,6 +445,8 @@
 			reg = <0x70080600 0x100>;
 			nvidia,ahub-cif-ids = <7 7>;
 			clocks = <&tegra_car TEGRA114_CLK_I2S3>;
+			resets = <&tegra_car 101>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -394,6 +455,8 @@
 			reg = <0x70080700 0x100>;
 			nvidia,ahub-cif-ids = <8 8>;
 			clocks = <&tegra_car TEGRA114_CLK_I2S4>;
+			resets = <&tegra_car 102>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 	};
@@ -403,6 +466,8 @@
 		reg = <0x78000000 0x200>;
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
+		resets = <&tegra_car 14>;
+		reset-names = "sdhci";
 		status = "disable";
 	};
 
@@ -411,6 +476,8 @@
 		reg = <0x78000200 0x200>;
 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
+		resets = <&tegra_car 9>;
+		reset-names = "sdhci";
 		status = "disable";
 	};
 
@@ -419,6 +486,8 @@
 		reg = <0x78000400 0x200>;
 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
+		resets = <&tegra_car 69>;
+		reset-names = "sdhci";
 		status = "disable";
 	};
 
@@ -427,6 +496,8 @@
 		reg = <0x78000600 0x200>;
 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
+		resets = <&tegra_car 15>;
+		reset-names = "sdhci";
 		status = "disable";
 	};
 
@@ -436,6 +507,8 @@
 		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		clocks = <&tegra_car TEGRA114_CLK_USBD>;
+		resets = <&tegra_car 22>;
+		reset-names = "usb";
 		nvidia,phy = <&phy1>;
 		status = "disabled";
 	};
@@ -467,6 +540,8 @@
 		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		clocks = <&tegra_car TEGRA114_CLK_USB3>;
+		resets = <&tegra_car 59>;
+		reset-names = "usb";
 		nvidia,phy = <&phy3>;
 		status = "disabled";
 	};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 8d71fc9d8a2f..e57fb3aefc2a 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -280,6 +280,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2C3>,
 		       	 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 67>;
+		reset-names = "i2c";
 	};
 
 	i2c@7000d000 {
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index df40b54fd8bc..159facbce524 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -22,6 +22,8 @@
 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
 		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
+		resets = <&tegra_car 28>;
+		reset-names = "host1x";
 
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -33,6 +35,8 @@
 			reg = <0x54040000 0x00040000>;
 			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_MPE>;
+			resets = <&tegra_car 60>;
+			reset-names = "mpe";
 		};
 
 		vi {
@@ -40,6 +44,8 @@
 			reg = <0x54080000 0x00040000>;
 			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_VI>;
+			resets = <&tegra_car 100>;
+			reset-names = "vi";
 		};
 
 		epp {
@@ -47,6 +53,8 @@
 			reg = <0x540c0000 0x00040000>;
 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_EPP>;
+			resets = <&tegra_car 19>;
+			reset-names = "epp";
 		};
 
 		isp {
@@ -54,6 +62,8 @@
 			reg = <0x54100000 0x00040000>;
 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_ISP>;
+			resets = <&tegra_car 23>;
+			reset-names = "isp";
 		};
 
 		gr2d {
@@ -61,12 +71,16 @@
 			reg = <0x54140000 0x00040000>;
 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_GR2D>;
+			resets = <&tegra_car 21>;
+			reset-names = "2d";
 		};
 
 		gr3d {
 			compatible = "nvidia,tegra20-gr3d";
 			reg = <0x54180000 0x00040000>;
 			clocks = <&tegra_car TEGRA20_CLK_GR3D>;
+			resets = <&tegra_car 24>;
+			reset-names = "3d";
 		};
 
 		dc@54200000 {
@@ -76,6 +90,8 @@
 			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
 				 <&tegra_car TEGRA20_CLK_PLL_P>;
 			clock-names = "disp1", "parent";
+			resets = <&tegra_car 27>;
+			reset-names = "dc";
 
 			rgb {
 				status = "disabled";
@@ -89,6 +105,8 @@
 			clocks = <&tegra_car TEGRA20_CLK_DISP2>,
 				 <&tegra_car TEGRA20_CLK_PLL_P>;
 			clock-names = "disp2", "parent";
+			resets = <&tegra_car 26>;
+			reset-names = "dc";
 
 			rgb {
 				status = "disabled";
@@ -102,6 +120,8 @@
 			clocks = <&tegra_car TEGRA20_CLK_HDMI>,
 				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 			clock-names = "hdmi", "parent";
+			resets = <&tegra_car 51>;
+			reset-names = "hdmi";
 			status = "disabled";
 		};
 
@@ -117,6 +137,8 @@
 			compatible = "nvidia,tegra20-dsi";
 			reg = <0x54300000 0x00040000>;
 			clocks = <&tegra_car TEGRA20_CLK_DSI>;
+			resets = <&tegra_car 48>;
+			reset-names = "dsi";
 			status = "disabled";
 		};
 	};
@@ -160,6 +182,7 @@
 		compatible = "nvidia,tegra20-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	apbdma: dma {
@@ -182,6 +205,8 @@
 			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
+		resets = <&tegra_car 34>;
+		reset-names = "dma";
 	};
 
 	ahb {
@@ -224,6 +249,8 @@
 		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 12>;
 		clocks = <&tegra_car TEGRA20_CLK_AC97>;
+		resets = <&tegra_car 3>;
+		reset-names = "ac97";
 		status = "disabled";
 	};
 
@@ -233,6 +260,8 @@
 		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 2>;
 		clocks = <&tegra_car TEGRA20_CLK_I2S1>;
+		resets = <&tegra_car 11>;
+		reset-names = "i2s";
 		status = "disabled";
 	};
 
@@ -242,6 +271,8 @@
 		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 1>;
 		clocks = <&tegra_car TEGRA20_CLK_I2S2>;
+		resets = <&tegra_car 18>;
+		reset-names = "i2s";
 		status = "disabled";
 	};
 
@@ -259,6 +290,8 @@
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 8>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTA>;
+		resets = <&tegra_car 6>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -269,6 +302,8 @@
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 9>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTB>;
+		resets = <&tegra_car 7>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -279,6 +314,8 @@
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 10>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTC>;
+		resets = <&tegra_car 55>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -289,6 +326,8 @@
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 19>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTD>;
+		resets = <&tegra_car 65>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -299,6 +338,8 @@
 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 20>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTE>;
+		resets = <&tegra_car 66>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -307,6 +348,8 @@
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
 		clocks = <&tegra_car TEGRA20_CLK_PWM>;
+		resets = <&tegra_car 17>;
+		reset-names = "pwm";
 		status = "disabled";
 	};
 
@@ -326,6 +369,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2C1>,
 			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 12>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -337,6 +382,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SPI>;
+		resets = <&tegra_car 43>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -349,6 +396,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2C2>,
 			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 54>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -361,6 +410,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2C3>,
 			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 67>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -373,6 +424,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_DVC>,
 			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 47>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -384,6 +437,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC1>;
+		resets = <&tegra_car 41>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -395,6 +450,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC2>;
+		resets = <&tegra_car 44>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -406,6 +463,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC3>;
+		resets = <&tegra_car 46>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -417,6 +476,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC4>;
+		resets = <&tegra_car 68>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -425,6 +486,8 @@
 		reg = <0x7000e200 0x100>;
 		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_KBC>;
+		resets = <&tegra_car 36>;
+		reset-names = "kbc";
 		status = "disabled";
 	};
 
@@ -481,6 +544,10 @@
 			 <&tegra_car TEGRA20_CLK_PCIE_XCLK>,
 			 <&tegra_car TEGRA20_CLK_PLL_E>;
 		clock-names = "pex", "afi", "pcie_xclk", "pll_e";
+		resets = <&tegra_car 70>,
+		         <&tegra_car 72>,
+		         <&tegra_car 74>;
+		reset-names = "pex", "afi", "pcie_x";
 		status = "disabled";
 
 		pci@1,0 {
@@ -517,6 +584,8 @@
 		phy_type = "utmi";
 		nvidia,has-legacy-mode;
 		clocks = <&tegra_car TEGRA20_CLK_USBD>;
+		resets = <&tegra_car 22>;
+		reset-names = "usb";
 		nvidia,needs-double-reset;
 		nvidia,phy = <&phy1>;
 		status = "disabled";
@@ -548,6 +617,8 @@
 		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "ulpi";
 		clocks = <&tegra_car TEGRA20_CLK_USB2>;
+		resets = <&tegra_car 58>;
+		reset-names = "usb";
 		nvidia,phy = <&phy2>;
 		status = "disabled";
 	};
@@ -569,6 +640,8 @@
 		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		clocks = <&tegra_car TEGRA20_CLK_USB3>;
+		resets = <&tegra_car 59>;
+		reset-names = "usb";
 		nvidia,phy = <&phy3>;
 		status = "disabled";
 	};
@@ -597,6 +670,8 @@
 		reg = <0xc8000000 0x200>;
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
+		resets = <&tegra_car 14>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -605,6 +680,8 @@
 		reg = <0xc8000200 0x200>;
 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
+		resets = <&tegra_car 9>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -613,6 +690,8 @@
 		reg = <0xc8000400 0x200>;
 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
+		resets = <&tegra_car 69>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -621,6 +700,8 @@
 		reg = <0xc8000600 0x200>;
 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
+		resets = <&tegra_car 15>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 2bd55cfd88ad..95635e54bd34 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -44,6 +44,10 @@
 			 <&tegra_car TEGRA30_CLK_PLL_E>,
 			 <&tegra_car TEGRA30_CLK_CML0>;
 		clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
+		resets = <&tegra_car 70>,
+		         <&tegra_car 72>,
+		         <&tegra_car 74>;
+		reset-names = "pex", "afi", "pcie_x";
 		status = "disabled";
 
 		pci@1,0 {
@@ -92,6 +96,8 @@
 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
 		clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
+		resets = <&tegra_car 28>;
+		reset-names = "host1x";
 
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -103,6 +109,8 @@
 			reg = <0x54040000 0x00040000>;
 			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA30_CLK_MPE>;
+			resets = <&tegra_car 60>;
+			reset-names = "mpe";
 		};
 
 		vi {
@@ -110,6 +118,8 @@
 			reg = <0x54080000 0x00040000>;
 			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA30_CLK_VI>;
+			resets = <&tegra_car 164>;
+			reset-names = "vi";
 		};
 
 		epp {
@@ -117,6 +127,8 @@
 			reg = <0x540c0000 0x00040000>;
 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA30_CLK_EPP>;
+			resets = <&tegra_car 19>;
+			reset-names = "epp";
 		};
 
 		isp {
@@ -124,12 +136,16 @@
 			reg = <0x54100000 0x00040000>;
 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA30_CLK_ISP>;
+			resets = <&tegra_car 23>;
+			reset-names = "isp";
 		};
 
 		gr2d {
 			compatible = "nvidia,tegra30-gr2d";
 			reg = <0x54140000 0x00040000>;
 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&tegra_car 21>;
+			reset-names = "2d";
 			clocks = <&tegra_car TEGRA30_CLK_GR2D>;
 		};
 
@@ -139,6 +155,9 @@
 			clocks = <&tegra_car TEGRA30_CLK_GR3D
 				  &tegra_car TEGRA30_CLK_GR3D2>;
 			clock-names = "3d", "3d2";
+			resets = <&tegra_car 24>,
+			         <&tegra_car 98>;
+			reset-names = "3d", "3d2";
 		};
 
 		dc@54200000 {
@@ -148,6 +167,8 @@
 			clocks = <&tegra_car TEGRA30_CLK_DISP1>,
 				 <&tegra_car TEGRA30_CLK_PLL_P>;
 			clock-names = "disp1", "parent";
+			resets = <&tegra_car 27>;
+			reset-names = "dc";
 
 			rgb {
 				status = "disabled";
@@ -161,6 +182,8 @@
 			clocks = <&tegra_car TEGRA30_CLK_DISP2>,
 				 <&tegra_car TEGRA30_CLK_PLL_P>;
 			clock-names = "disp2", "parent";
+			resets = <&tegra_car 26>;
+			reset-names = "dc";
 
 			rgb {
 				status = "disabled";
@@ -174,6 +197,8 @@
 			clocks = <&tegra_car TEGRA30_CLK_HDMI>,
 				 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
 			clock-names = "hdmi", "parent";
+			resets = <&tegra_car 51>;
+			reset-names = "hdmi";
 			status = "disabled";
 		};
 
@@ -189,6 +214,8 @@
 			compatible = "nvidia,tegra30-dsi";
 			reg = <0x54300000 0x00040000>;
 			clocks = <&tegra_car TEGRA30_CLK_DSIA>;
+			resets = <&tegra_car 48>;
+			reset-names = "dsi";
 			status = "disabled";
 		};
 	};
@@ -234,6 +261,7 @@
 		compatible = "nvidia,tegra30-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	apbdma: dma {
@@ -272,6 +300,8 @@
 			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
+		resets = <&tegra_car 34>;
+		reset-names = "dma";
 	};
 
 	ahb: ahb {
@@ -317,6 +347,8 @@
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 8>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTA>;
+		resets = <&tegra_car 6>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -327,6 +359,8 @@
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 9>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTB>;
+		resets = <&tegra_car 7>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -337,6 +371,8 @@
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 10>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTC>;
+		resets = <&tegra_car 55>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -347,6 +383,8 @@
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 19>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTD>;
+		resets = <&tegra_car 65>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -357,6 +395,8 @@
 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 20>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTE>;
+		resets = <&tegra_car 66>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -365,6 +405,8 @@
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
 		clocks = <&tegra_car TEGRA30_CLK_PWM>;
+		resets = <&tegra_car 17>;
+		reset-names = "pwm";
 		status = "disabled";
 	};
 
@@ -384,6 +426,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_I2C1>,
 			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 12>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -396,6 +440,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_I2C2>,
 			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 54>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -408,6 +454,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_I2C3>,
 			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 67>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -419,6 +467,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_I2C4>,
 			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
+		resets = <&tegra_car 103>;
+		reset-names = "i2c";
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -432,6 +482,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_I2C5>,
 			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 47>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -443,6 +495,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC1>;
+		resets = <&tegra_car 41>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -454,6 +508,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC2>;
+		resets = <&tegra_car 44>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -465,6 +521,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC3>;
+		resets = <&tegra_car 46>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -476,6 +534,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC4>;
+		resets = <&tegra_car 68>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -487,6 +547,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC5>;
+		resets = <&tegra_car 104>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -498,6 +560,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC6>;
+		resets = <&tegra_car 106>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -506,6 +570,8 @@
 		reg = <0x7000e200 0x100>;
 		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_KBC>;
+		resets = <&tegra_car 36>;
+		reset-names = "kbc";
 		status = "disabled";
 	};
 
@@ -555,6 +621,20 @@
 		clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
 			      "spdif_in";
+		resets = <&tegra_car 106>, /* d_audio */
+			 <&tegra_car 107>, /* apbif */
+			 <&tegra_car 30>,  /* i2s0 */
+			 <&tegra_car 11>,  /* i2s1 */
+			 <&tegra_car 18>,  /* i2s2 */
+			 <&tegra_car 101>, /* i2s3 */
+			 <&tegra_car 102>, /* i2s4 */
+			 <&tegra_car 108>, /* dam0 */
+			 <&tegra_car 109>, /* dam1 */
+			 <&tegra_car 110>, /* dam2 */
+			 <&tegra_car 10>;  /* spdif */
+		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
+			      "spdif";
 		ranges;
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -564,6 +644,8 @@
 			reg = <0x70080300 0x100>;
 			nvidia,ahub-cif-ids = <4 4>;
 			clocks = <&tegra_car TEGRA30_CLK_I2S0>;
+			resets = <&tegra_car 30>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -572,6 +654,8 @@
 			reg = <0x70080400 0x100>;
 			nvidia,ahub-cif-ids = <5 5>;
 			clocks = <&tegra_car TEGRA30_CLK_I2S1>;
+			resets = <&tegra_car 11>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -580,6 +664,8 @@
 			reg = <0x70080500 0x100>;
 			nvidia,ahub-cif-ids = <6 6>;
 			clocks = <&tegra_car TEGRA30_CLK_I2S2>;
+			resets = <&tegra_car 18>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -588,6 +674,8 @@
 			reg = <0x70080600 0x100>;
 			nvidia,ahub-cif-ids = <7 7>;
 			clocks = <&tegra_car TEGRA30_CLK_I2S3>;
+			resets = <&tegra_car 101>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -596,6 +684,8 @@
 			reg = <0x70080700 0x100>;
 			nvidia,ahub-cif-ids = <8 8>;
 			clocks = <&tegra_car TEGRA30_CLK_I2S4>;
+			resets = <&tegra_car 102>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 	};
@@ -605,6 +695,8 @@
 		reg = <0x78000000 0x200>;
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
+		resets = <&tegra_car 14>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -613,6 +705,8 @@
 		reg = <0x78000200 0x200>;
 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
+		resets = <&tegra_car 9>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -621,6 +715,8 @@
 		reg = <0x78000400 0x200>;
 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
+		resets = <&tegra_car 69>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -629,6 +725,8 @@
 		reg = <0x78000600 0x200>;
 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
+		resets = <&tegra_car 15>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -638,6 +736,8 @@
 		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		clocks = <&tegra_car TEGRA30_CLK_USBD>;
+		resets = <&tegra_car 22>;
+		reset-names = "usb";
 		nvidia,needs-double-reset;
 		nvidia,phy = <&phy1>;
 		status = "disabled";
@@ -671,6 +771,8 @@
 		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "ulpi";
 		clocks = <&tegra_car TEGRA30_CLK_USB2>;
+		resets = <&tegra_car 58>;
+		reset-names = "usb";
 		nvidia,phy = <&phy2>;
 		status = "disabled";
 	};
@@ -692,6 +794,8 @@
 		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		clocks = <&tegra_car TEGRA30_CLK_USB3>;
+		resets = <&tegra_car 59>;
+		reset-names = "usb";
 		nvidia,phy = <&phy3>;
 		status = "disabled";
 	};
-- 
1.8.1.5

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[PATCH 04/31] ARM: tegra: update DT files to add reset properties

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

An earlier patch updated the Tegra DT bindings to require resets and
reset-names properties to be filled in. This patch updates the DT files
to include those properties.

Note that any legacy clocks and clock-names entries that are replaced by
reset properties are not yet removed; the drivers must be updated to use
the new resets and reset-names properties first.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: devicetree at vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 arch/arm/boot/dts/tegra114.dtsi     |  83 ++++++++++++++++++++++++++--
 arch/arm/boot/dts/tegra20-paz00.dts |   2 +
 arch/arm/boot/dts/tegra20.dtsi      |  81 ++++++++++++++++++++++++++++
 arch/arm/boot/dts/tegra30.dtsi      | 104 ++++++++++++++++++++++++++++++++++++
 4 files changed, 266 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 8d42787c8ff1..c40dbdcb3741 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -43,6 +43,7 @@
 		compatible = "nvidia,tegra114-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	apbdma: dma {
@@ -81,6 +82,8 @@
 			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
+		resets = <&tegra_car 34>;
+		reset-names = "dma";
 	};
 
 	ahb: ahb {
@@ -125,8 +128,10 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 8>;
-		status = "disabled";
 		clocks = <&tegra_car TEGRA114_CLK_UARTA>;
+		resets = <&tegra_car 6>;
+		reset-names = "serial";
+		status = "disabled";
 	};
 
 	uartb: serial at 70006040 {
@@ -135,8 +140,10 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 9>;
-		status = "disabled";
 		clocks = <&tegra_car TEGRA114_CLK_UARTB>;
+		resets = <&tegra_car 7>;
+		reset-names = "serial";
+		status = "disabled";
 	};
 
 	uartc: serial at 70006200 {
@@ -145,8 +152,10 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 10>;
-		status = "disabled";
 		clocks = <&tegra_car TEGRA114_CLK_UARTC>;
+		resets = <&tegra_car 55>;
+		reset-names = "serial";
+		status = "disabled";
 	};
 
 	uartd: serial at 70006300 {
@@ -155,8 +164,10 @@
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 19>;
-		status = "disabled";
 		clocks = <&tegra_car TEGRA114_CLK_UARTD>;
+		resets = <&tegra_car 65>;
+		reset-names = "serial";
+		status = "disabled";
 	};
 
 	pwm: pwm {
@@ -164,6 +175,8 @@
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
 		clocks = <&tegra_car TEGRA114_CLK_PWM>;
+		resets = <&tegra_car 17>;
+		reset-names = "pwm";
 		status = "disabled";
 	};
 
@@ -175,6 +188,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_I2C1>;
 		clock-names = "div-clk";
+		resets = <&tegra_car 12>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -186,6 +201,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_I2C2>;
 		clock-names = "div-clk";
+		resets = <&tegra_car 54>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -197,6 +214,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_I2C3>;
 		clock-names = "div-clk";
+		resets = <&tegra_car 67>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -208,6 +227,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_I2C4>;
 		clock-names = "div-clk";
+		resets = <&tegra_car 103>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -219,6 +240,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_I2C5>;
 		clock-names = "div-clk";
+		resets = <&tegra_car 47>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -231,6 +254,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC1>;
 		clock-names = "spi";
+		resets = <&tegra_car 41>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -243,6 +268,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC2>;
 		clock-names = "spi";
+		resets = <&tegra_car 44>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -255,6 +282,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC3>;
 		clock-names = "spi";
+		resets = <&tegra_car 46>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -267,6 +296,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC4>;
 		clock-names = "spi";
+		resets = <&tegra_car 68>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -279,6 +310,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC5>;
 		clock-names = "spi";
+		resets = <&tegra_car 104>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -291,6 +324,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC6>;
 		clock-names = "spi";
+		resets = <&tegra_car 105>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -306,6 +341,8 @@
 		reg = <0x7000e200 0x100>;
 		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA114_CLK_KBC>;
+		resets = <&tegra_car 36>;
+		reset-names = "kbc";
 		status = "disabled";
 	};
 
@@ -353,6 +390,22 @@
 		clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
 			      "spdif_in", "amx", "adx";
+		resets = <&tegra_car 106>, /* d_audio */
+			 <&tegra_car 107>, /* apbif */
+			 <&tegra_car 30>,  /* i2s0 */
+			 <&tegra_car 11>,  /* i2s1 */
+			 <&tegra_car 18>,  /* i2s2 */
+			 <&tegra_car 101>, /* i2s3 */
+			 <&tegra_car 102>, /* i2s4 */
+			 <&tegra_car 108>, /* dam0 */
+			 <&tegra_car 109>, /* dam1 */
+			 <&tegra_car 110>, /* dam2 */
+			 <&tegra_car 10>,  /* spdif */
+			 <&tegra_car 153>, /* amx */
+			 <&tegra_car 154>; /* adx */
+		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
+			      "spdif", "amx", "adx";
 		ranges;
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -362,6 +415,8 @@
 			reg = <0x70080300 0x100>;
 			nvidia,ahub-cif-ids = <4 4>;
 			clocks = <&tegra_car TEGRA114_CLK_I2S0>;
+			resets = <&tegra_car 30>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -370,6 +425,8 @@
 			reg = <0x70080400 0x100>;
 			nvidia,ahub-cif-ids = <5 5>;
 			clocks = <&tegra_car TEGRA114_CLK_I2S1>;
+			resets = <&tegra_car 11>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -378,6 +435,8 @@
 			reg = <0x70080500 0x100>;
 			nvidia,ahub-cif-ids = <6 6>;
 			clocks = <&tegra_car TEGRA114_CLK_I2S2>;
+			resets = <&tegra_car 18>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -386,6 +445,8 @@
 			reg = <0x70080600 0x100>;
 			nvidia,ahub-cif-ids = <7 7>;
 			clocks = <&tegra_car TEGRA114_CLK_I2S3>;
+			resets = <&tegra_car 101>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -394,6 +455,8 @@
 			reg = <0x70080700 0x100>;
 			nvidia,ahub-cif-ids = <8 8>;
 			clocks = <&tegra_car TEGRA114_CLK_I2S4>;
+			resets = <&tegra_car 102>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 	};
@@ -403,6 +466,8 @@
 		reg = <0x78000000 0x200>;
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
+		resets = <&tegra_car 14>;
+		reset-names = "sdhci";
 		status = "disable";
 	};
 
@@ -411,6 +476,8 @@
 		reg = <0x78000200 0x200>;
 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
+		resets = <&tegra_car 9>;
+		reset-names = "sdhci";
 		status = "disable";
 	};
 
@@ -419,6 +486,8 @@
 		reg = <0x78000400 0x200>;
 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
+		resets = <&tegra_car 69>;
+		reset-names = "sdhci";
 		status = "disable";
 	};
 
@@ -427,6 +496,8 @@
 		reg = <0x78000600 0x200>;
 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
+		resets = <&tegra_car 15>;
+		reset-names = "sdhci";
 		status = "disable";
 	};
 
@@ -436,6 +507,8 @@
 		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		clocks = <&tegra_car TEGRA114_CLK_USBD>;
+		resets = <&tegra_car 22>;
+		reset-names = "usb";
 		nvidia,phy = <&phy1>;
 		status = "disabled";
 	};
@@ -467,6 +540,8 @@
 		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		clocks = <&tegra_car TEGRA114_CLK_USB3>;
+		resets = <&tegra_car 59>;
+		reset-names = "usb";
 		nvidia,phy = <&phy3>;
 		status = "disabled";
 	};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 8d71fc9d8a2f..e57fb3aefc2a 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -280,6 +280,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2C3>,
 		       	 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 67>;
+		reset-names = "i2c";
 	};
 
 	i2c at 7000d000 {
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index df40b54fd8bc..159facbce524 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -22,6 +22,8 @@
 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
 		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
+		resets = <&tegra_car 28>;
+		reset-names = "host1x";
 
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -33,6 +35,8 @@
 			reg = <0x54040000 0x00040000>;
 			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_MPE>;
+			resets = <&tegra_car 60>;
+			reset-names = "mpe";
 		};
 
 		vi {
@@ -40,6 +44,8 @@
 			reg = <0x54080000 0x00040000>;
 			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_VI>;
+			resets = <&tegra_car 100>;
+			reset-names = "vi";
 		};
 
 		epp {
@@ -47,6 +53,8 @@
 			reg = <0x540c0000 0x00040000>;
 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_EPP>;
+			resets = <&tegra_car 19>;
+			reset-names = "epp";
 		};
 
 		isp {
@@ -54,6 +62,8 @@
 			reg = <0x54100000 0x00040000>;
 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_ISP>;
+			resets = <&tegra_car 23>;
+			reset-names = "isp";
 		};
 
 		gr2d {
@@ -61,12 +71,16 @@
 			reg = <0x54140000 0x00040000>;
 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_GR2D>;
+			resets = <&tegra_car 21>;
+			reset-names = "2d";
 		};
 
 		gr3d {
 			compatible = "nvidia,tegra20-gr3d";
 			reg = <0x54180000 0x00040000>;
 			clocks = <&tegra_car TEGRA20_CLK_GR3D>;
+			resets = <&tegra_car 24>;
+			reset-names = "3d";
 		};
 
 		dc at 54200000 {
@@ -76,6 +90,8 @@
 			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
 				 <&tegra_car TEGRA20_CLK_PLL_P>;
 			clock-names = "disp1", "parent";
+			resets = <&tegra_car 27>;
+			reset-names = "dc";
 
 			rgb {
 				status = "disabled";
@@ -89,6 +105,8 @@
 			clocks = <&tegra_car TEGRA20_CLK_DISP2>,
 				 <&tegra_car TEGRA20_CLK_PLL_P>;
 			clock-names = "disp2", "parent";
+			resets = <&tegra_car 26>;
+			reset-names = "dc";
 
 			rgb {
 				status = "disabled";
@@ -102,6 +120,8 @@
 			clocks = <&tegra_car TEGRA20_CLK_HDMI>,
 				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 			clock-names = "hdmi", "parent";
+			resets = <&tegra_car 51>;
+			reset-names = "hdmi";
 			status = "disabled";
 		};
 
@@ -117,6 +137,8 @@
 			compatible = "nvidia,tegra20-dsi";
 			reg = <0x54300000 0x00040000>;
 			clocks = <&tegra_car TEGRA20_CLK_DSI>;
+			resets = <&tegra_car 48>;
+			reset-names = "dsi";
 			status = "disabled";
 		};
 	};
@@ -160,6 +182,7 @@
 		compatible = "nvidia,tegra20-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	apbdma: dma {
@@ -182,6 +205,8 @@
 			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
+		resets = <&tegra_car 34>;
+		reset-names = "dma";
 	};
 
 	ahb {
@@ -224,6 +249,8 @@
 		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 12>;
 		clocks = <&tegra_car TEGRA20_CLK_AC97>;
+		resets = <&tegra_car 3>;
+		reset-names = "ac97";
 		status = "disabled";
 	};
 
@@ -233,6 +260,8 @@
 		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 2>;
 		clocks = <&tegra_car TEGRA20_CLK_I2S1>;
+		resets = <&tegra_car 11>;
+		reset-names = "i2s";
 		status = "disabled";
 	};
 
@@ -242,6 +271,8 @@
 		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 1>;
 		clocks = <&tegra_car TEGRA20_CLK_I2S2>;
+		resets = <&tegra_car 18>;
+		reset-names = "i2s";
 		status = "disabled";
 	};
 
@@ -259,6 +290,8 @@
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 8>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTA>;
+		resets = <&tegra_car 6>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -269,6 +302,8 @@
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 9>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTB>;
+		resets = <&tegra_car 7>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -279,6 +314,8 @@
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 10>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTC>;
+		resets = <&tegra_car 55>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -289,6 +326,8 @@
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 19>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTD>;
+		resets = <&tegra_car 65>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -299,6 +338,8 @@
 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 20>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTE>;
+		resets = <&tegra_car 66>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -307,6 +348,8 @@
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
 		clocks = <&tegra_car TEGRA20_CLK_PWM>;
+		resets = <&tegra_car 17>;
+		reset-names = "pwm";
 		status = "disabled";
 	};
 
@@ -326,6 +369,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2C1>,
 			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 12>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -337,6 +382,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SPI>;
+		resets = <&tegra_car 43>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -349,6 +396,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2C2>,
 			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 54>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -361,6 +410,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2C3>,
 			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 67>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -373,6 +424,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_DVC>,
 			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 47>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -384,6 +437,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC1>;
+		resets = <&tegra_car 41>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -395,6 +450,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC2>;
+		resets = <&tegra_car 44>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -406,6 +463,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC3>;
+		resets = <&tegra_car 46>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -417,6 +476,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC4>;
+		resets = <&tegra_car 68>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -425,6 +486,8 @@
 		reg = <0x7000e200 0x100>;
 		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_KBC>;
+		resets = <&tegra_car 36>;
+		reset-names = "kbc";
 		status = "disabled";
 	};
 
@@ -481,6 +544,10 @@
 			 <&tegra_car TEGRA20_CLK_PCIE_XCLK>,
 			 <&tegra_car TEGRA20_CLK_PLL_E>;
 		clock-names = "pex", "afi", "pcie_xclk", "pll_e";
+		resets = <&tegra_car 70>,
+		         <&tegra_car 72>,
+		         <&tegra_car 74>;
+		reset-names = "pex", "afi", "pcie_x";
 		status = "disabled";
 
 		pci at 1,0 {
@@ -517,6 +584,8 @@
 		phy_type = "utmi";
 		nvidia,has-legacy-mode;
 		clocks = <&tegra_car TEGRA20_CLK_USBD>;
+		resets = <&tegra_car 22>;
+		reset-names = "usb";
 		nvidia,needs-double-reset;
 		nvidia,phy = <&phy1>;
 		status = "disabled";
@@ -548,6 +617,8 @@
 		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "ulpi";
 		clocks = <&tegra_car TEGRA20_CLK_USB2>;
+		resets = <&tegra_car 58>;
+		reset-names = "usb";
 		nvidia,phy = <&phy2>;
 		status = "disabled";
 	};
@@ -569,6 +640,8 @@
 		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		clocks = <&tegra_car TEGRA20_CLK_USB3>;
+		resets = <&tegra_car 59>;
+		reset-names = "usb";
 		nvidia,phy = <&phy3>;
 		status = "disabled";
 	};
@@ -597,6 +670,8 @@
 		reg = <0xc8000000 0x200>;
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
+		resets = <&tegra_car 14>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -605,6 +680,8 @@
 		reg = <0xc8000200 0x200>;
 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
+		resets = <&tegra_car 9>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -613,6 +690,8 @@
 		reg = <0xc8000400 0x200>;
 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
+		resets = <&tegra_car 69>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -621,6 +700,8 @@
 		reg = <0xc8000600 0x200>;
 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
+		resets = <&tegra_car 15>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 2bd55cfd88ad..95635e54bd34 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -44,6 +44,10 @@
 			 <&tegra_car TEGRA30_CLK_PLL_E>,
 			 <&tegra_car TEGRA30_CLK_CML0>;
 		clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
+		resets = <&tegra_car 70>,
+		         <&tegra_car 72>,
+		         <&tegra_car 74>;
+		reset-names = "pex", "afi", "pcie_x";
 		status = "disabled";
 
 		pci at 1,0 {
@@ -92,6 +96,8 @@
 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
 		clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
+		resets = <&tegra_car 28>;
+		reset-names = "host1x";
 
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -103,6 +109,8 @@
 			reg = <0x54040000 0x00040000>;
 			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA30_CLK_MPE>;
+			resets = <&tegra_car 60>;
+			reset-names = "mpe";
 		};
 
 		vi {
@@ -110,6 +118,8 @@
 			reg = <0x54080000 0x00040000>;
 			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA30_CLK_VI>;
+			resets = <&tegra_car 164>;
+			reset-names = "vi";
 		};
 
 		epp {
@@ -117,6 +127,8 @@
 			reg = <0x540c0000 0x00040000>;
 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA30_CLK_EPP>;
+			resets = <&tegra_car 19>;
+			reset-names = "epp";
 		};
 
 		isp {
@@ -124,12 +136,16 @@
 			reg = <0x54100000 0x00040000>;
 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA30_CLK_ISP>;
+			resets = <&tegra_car 23>;
+			reset-names = "isp";
 		};
 
 		gr2d {
 			compatible = "nvidia,tegra30-gr2d";
 			reg = <0x54140000 0x00040000>;
 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&tegra_car 21>;
+			reset-names = "2d";
 			clocks = <&tegra_car TEGRA30_CLK_GR2D>;
 		};
 
@@ -139,6 +155,9 @@
 			clocks = <&tegra_car TEGRA30_CLK_GR3D
 				  &tegra_car TEGRA30_CLK_GR3D2>;
 			clock-names = "3d", "3d2";
+			resets = <&tegra_car 24>,
+			         <&tegra_car 98>;
+			reset-names = "3d", "3d2";
 		};
 
 		dc at 54200000 {
@@ -148,6 +167,8 @@
 			clocks = <&tegra_car TEGRA30_CLK_DISP1>,
 				 <&tegra_car TEGRA30_CLK_PLL_P>;
 			clock-names = "disp1", "parent";
+			resets = <&tegra_car 27>;
+			reset-names = "dc";
 
 			rgb {
 				status = "disabled";
@@ -161,6 +182,8 @@
 			clocks = <&tegra_car TEGRA30_CLK_DISP2>,
 				 <&tegra_car TEGRA30_CLK_PLL_P>;
 			clock-names = "disp2", "parent";
+			resets = <&tegra_car 26>;
+			reset-names = "dc";
 
 			rgb {
 				status = "disabled";
@@ -174,6 +197,8 @@
 			clocks = <&tegra_car TEGRA30_CLK_HDMI>,
 				 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
 			clock-names = "hdmi", "parent";
+			resets = <&tegra_car 51>;
+			reset-names = "hdmi";
 			status = "disabled";
 		};
 
@@ -189,6 +214,8 @@
 			compatible = "nvidia,tegra30-dsi";
 			reg = <0x54300000 0x00040000>;
 			clocks = <&tegra_car TEGRA30_CLK_DSIA>;
+			resets = <&tegra_car 48>;
+			reset-names = "dsi";
 			status = "disabled";
 		};
 	};
@@ -234,6 +261,7 @@
 		compatible = "nvidia,tegra30-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	apbdma: dma {
@@ -272,6 +300,8 @@
 			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
+		resets = <&tegra_car 34>;
+		reset-names = "dma";
 	};
 
 	ahb: ahb {
@@ -317,6 +347,8 @@
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 8>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTA>;
+		resets = <&tegra_car 6>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -327,6 +359,8 @@
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 9>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTB>;
+		resets = <&tegra_car 7>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -337,6 +371,8 @@
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 10>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTC>;
+		resets = <&tegra_car 55>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -347,6 +383,8 @@
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 19>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTD>;
+		resets = <&tegra_car 65>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -357,6 +395,8 @@
 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 20>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTE>;
+		resets = <&tegra_car 66>;
+		reset-names = "serial";
 		status = "disabled";
 	};
 
@@ -365,6 +405,8 @@
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
 		clocks = <&tegra_car TEGRA30_CLK_PWM>;
+		resets = <&tegra_car 17>;
+		reset-names = "pwm";
 		status = "disabled";
 	};
 
@@ -384,6 +426,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_I2C1>,
 			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 12>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -396,6 +440,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_I2C2>,
 			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 54>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -408,6 +454,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_I2C3>,
 			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 67>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -419,6 +467,8 @@
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_I2C4>,
 			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
+		resets = <&tegra_car 103>;
+		reset-names = "i2c";
 		clock-names = "div-clk", "fast-clk";
 		status = "disabled";
 	};
@@ -432,6 +482,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_I2C5>,
 			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 47>;
+		reset-names = "i2c";
 		status = "disabled";
 	};
 
@@ -443,6 +495,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC1>;
+		resets = <&tegra_car 41>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -454,6 +508,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC2>;
+		resets = <&tegra_car 44>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -465,6 +521,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC3>;
+		resets = <&tegra_car 46>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -476,6 +534,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC4>;
+		resets = <&tegra_car 68>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -487,6 +547,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC5>;
+		resets = <&tegra_car 104>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -498,6 +560,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC6>;
+		resets = <&tegra_car 106>;
+		reset-names = "spi";
 		status = "disabled";
 	};
 
@@ -506,6 +570,8 @@
 		reg = <0x7000e200 0x100>;
 		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_KBC>;
+		resets = <&tegra_car 36>;
+		reset-names = "kbc";
 		status = "disabled";
 	};
 
@@ -555,6 +621,20 @@
 		clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
 			      "spdif_in";
+		resets = <&tegra_car 106>, /* d_audio */
+			 <&tegra_car 107>, /* apbif */
+			 <&tegra_car 30>,  /* i2s0 */
+			 <&tegra_car 11>,  /* i2s1 */
+			 <&tegra_car 18>,  /* i2s2 */
+			 <&tegra_car 101>, /* i2s3 */
+			 <&tegra_car 102>, /* i2s4 */
+			 <&tegra_car 108>, /* dam0 */
+			 <&tegra_car 109>, /* dam1 */
+			 <&tegra_car 110>, /* dam2 */
+			 <&tegra_car 10>;  /* spdif */
+		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
+			      "spdif";
 		ranges;
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -564,6 +644,8 @@
 			reg = <0x70080300 0x100>;
 			nvidia,ahub-cif-ids = <4 4>;
 			clocks = <&tegra_car TEGRA30_CLK_I2S0>;
+			resets = <&tegra_car 30>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -572,6 +654,8 @@
 			reg = <0x70080400 0x100>;
 			nvidia,ahub-cif-ids = <5 5>;
 			clocks = <&tegra_car TEGRA30_CLK_I2S1>;
+			resets = <&tegra_car 11>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -580,6 +664,8 @@
 			reg = <0x70080500 0x100>;
 			nvidia,ahub-cif-ids = <6 6>;
 			clocks = <&tegra_car TEGRA30_CLK_I2S2>;
+			resets = <&tegra_car 18>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -588,6 +674,8 @@
 			reg = <0x70080600 0x100>;
 			nvidia,ahub-cif-ids = <7 7>;
 			clocks = <&tegra_car TEGRA30_CLK_I2S3>;
+			resets = <&tegra_car 101>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 
@@ -596,6 +684,8 @@
 			reg = <0x70080700 0x100>;
 			nvidia,ahub-cif-ids = <8 8>;
 			clocks = <&tegra_car TEGRA30_CLK_I2S4>;
+			resets = <&tegra_car 102>;
+			reset-names = "i2s";
 			status = "disabled";
 		};
 	};
@@ -605,6 +695,8 @@
 		reg = <0x78000000 0x200>;
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
+		resets = <&tegra_car 14>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -613,6 +705,8 @@
 		reg = <0x78000200 0x200>;
 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
+		resets = <&tegra_car 9>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -621,6 +715,8 @@
 		reg = <0x78000400 0x200>;
 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
+		resets = <&tegra_car 69>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -629,6 +725,8 @@
 		reg = <0x78000600 0x200>;
 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
+		resets = <&tegra_car 15>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};
 
@@ -638,6 +736,8 @@
 		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		clocks = <&tegra_car TEGRA30_CLK_USBD>;
+		resets = <&tegra_car 22>;
+		reset-names = "usb";
 		nvidia,needs-double-reset;
 		nvidia,phy = <&phy1>;
 		status = "disabled";
@@ -671,6 +771,8 @@
 		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "ulpi";
 		clocks = <&tegra_car TEGRA30_CLK_USB2>;
+		resets = <&tegra_car 58>;
+		reset-names = "usb";
 		nvidia,phy = <&phy2>;
 		status = "disabled";
 	};
@@ -692,6 +794,8 @@
 		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		clocks = <&tegra_car TEGRA30_CLK_USB3>;
+		resets = <&tegra_car 59>;
+		reset-names = "usb";
 		nvidia,phy = <&phy3>;
 		status = "disabled";
 	};
-- 
1.8.1.5

Re: [PATCH 04/31] ARM: tegra: update DT files to add reset properties

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1758 bytes --]

On Fri, Nov 15, 2013 at 01:53:59PM -0700, Stephen Warren wrote:
[...]
> @@ -135,8 +140,10 @@
>  		reg-shift = <2>;
>  		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
>  		nvidia,dma-request-selector = <&apbdma 9>;
> -		status = "disabled";
>  		clocks = <&tegra_car TEGRA114_CLK_UARTB>;
> +		resets = <&tegra_car 7>;

This is confusing. For some reason that escapes me the tegra114-car.h
file defines TEGRA114_CLK_UARTB as 192. Other reset entries match the
numerical value of the TEGRA114_CLK_* define, which makes it easy to
double-check this.

But UARTB is indeed at bit 7, so this looks good.

Oh, I think perhaps it's caused by bit 7 being shared by both the UARTB
and the VFIR controllers for reset, but not for the clocks.

>  			reg = <0x70080300 0x100>;
>  			nvidia,ahub-cif-ids = <4 4>;
>  			clocks = <&tegra_car TEGRA114_CLK_I2S0>;

The clocks for these i2s devices are already listed in the ahub node. Is
that on purpose?

> @@ -110,6 +118,8 @@
>  			reg = <0x54080000 0x00040000>;
>  			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&tegra_car TEGRA30_CLK_VI>;
> +			resets = <&tegra_car 164>;

I think this needs to be 20.

> @@ -139,6 +155,9 @@
>  			clocks = <&tegra_car TEGRA30_CLK_GR3D
>  				  &tegra_car TEGRA30_CLK_GR3D2>;
>  			clock-names = "3d", "3d2";
> +			resets = <&tegra_car 24>,

For some reason bit 24 is missing from the register definition. Given
that this has worked before I suppose either the documentation is stale
or it's not necessary to take this module out of reset.

> +			 <&tegra_car 30>,  /* i2s0 */
> +			 <&tegra_car 11>,  /* i2s1 */
> +			 <&tegra_car 18>,  /* i2s2 */
> +			 <&tegra_car 101>, /* i2s3 */
> +			 <&tegra_car 102>, /* i2s4 */

Some comment for these as for Tegra20.

Thierry

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[PATCH 04/31] ARM: tegra: update DT files to add reset properties

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:53:59PM -0700, Stephen Warren wrote:
[...]
> @@ -135,8 +140,10 @@
>  		reg-shift = <2>;
>  		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
>  		nvidia,dma-request-selector = <&apbdma 9>;
> -		status = "disabled";
>  		clocks = <&tegra_car TEGRA114_CLK_UARTB>;
> +		resets = <&tegra_car 7>;

This is confusing. For some reason that escapes me the tegra114-car.h
file defines TEGRA114_CLK_UARTB as 192. Other reset entries match the
numerical value of the TEGRA114_CLK_* define, which makes it easy to
double-check this.

But UARTB is indeed at bit 7, so this looks good.

Oh, I think perhaps it's caused by bit 7 being shared by both the UARTB
and the VFIR controllers for reset, but not for the clocks.

>  			reg = <0x70080300 0x100>;
>  			nvidia,ahub-cif-ids = <4 4>;
>  			clocks = <&tegra_car TEGRA114_CLK_I2S0>;

The clocks for these i2s devices are already listed in the ahub node. Is
that on purpose?

> @@ -110,6 +118,8 @@
>  			reg = <0x54080000 0x00040000>;
>  			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&tegra_car TEGRA30_CLK_VI>;
> +			resets = <&tegra_car 164>;

I think this needs to be 20.

> @@ -139,6 +155,9 @@
>  			clocks = <&tegra_car TEGRA30_CLK_GR3D
>  				  &tegra_car TEGRA30_CLK_GR3D2>;
>  			clock-names = "3d", "3d2";
> +			resets = <&tegra_car 24>,

For some reason bit 24 is missing from the register definition. Given
that this has worked before I suppose either the documentation is stale
or it's not necessary to take this module out of reset.

> +			 <&tegra_car 30>,  /* i2s0 */
> +			 <&tegra_car 11>,  /* i2s1 */
> +			 <&tegra_car 18>,  /* i2s2 */
> +			 <&tegra_car 101>, /* i2s3 */
> +			 <&tegra_car 102>, /* i2s4 */

Some comment for these as for Tegra20.

Thierry
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Re: [PATCH 04/31] ARM: tegra: update DT files to add reset properties

[Stephen Warren]

On 11/29/2013 06:00 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:59PM -0700, Stephen Warren wrote: 
> [...]
>> @@ -135,8 +140,10 @@ reg-shift = <2>; interrupts = <GIC_SPI 37
>> IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 9>; 
>> -		status = "disabled"; clocks = <&tegra_car
>> TEGRA114_CLK_UARTB>; +		resets = <&tegra_car 7>;
> 
> This is confusing. For some reason that escapes me the
> tegra114-car.h file defines TEGRA114_CLK_UARTB as 192. Other reset
> entries match the numerical value of the TEGRA114_CLK_* define,
> which makes it easy to double-check this.
> 
> But UARTB is indeed at bit 7, so this looks good.
> 
> Oh, I think perhaps it's caused by bit 7 being shared by both the
> UARTB and the VFIR controllers for reset, but not for the clocks.

Yes, there's a single reset bit that affects 2 HW modules, yet each HW
module has its own clock. So the reset and clock IDs don't exactly
align. That's the main reason I wanted to switch the drivers to the
reset framework rather than piggy-backing on the clock framework to do
resets, so the difference in name-spaces is explicit.

>> reg = <0x70080300 0x100>; nvidia,ahub-cif-ids = <4 4>; clocks =
>> <&tegra_car TEGRA114_CLK_I2S0>;
> 
> The clocks for these i2s devices are already listed in the ahub
> node. Is that on purpose?

Yes.

The AHUB driver needs to remove reset from the HW modules, so that the
configlink bus works. Reset removal used to require a custom Tegra API
that took a clock as a parameter. Hence, the AHUB node needed the
clock reference. After this series, the AHUB only needs a reset handle
to use the standard reset API. However, the clock references are left
in the AHUB node until after the AHUB driver is converted, so the
series is bisectable. After the series, only the I2S driver needs to
clock references.

>> @@ -110,6 +118,8 @@ reg = <0x54080000 0x00040000>; interrupts =
>> <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car
>> TEGRA30_CLK_VI>; +			resets = <&tegra_car 164>;
> 
> I think this needs to be 20.

OK, I'll check that when I get back...

>> +			 <&tegra_car 30>,  /* i2s0 */ +			 <&tegra_car 11>,  /* i2s1
>> */ +			 <&tegra_car 18>,  /* i2s2 */ +			 <&tegra_car 101>, /*
>> i2s3 */ +			 <&tegra_car 102>, /* i2s4 */
> 
> Some comment for these as for Tegra20.

I'm not sure which other comment was "for Tegra20", since none of the
filenames were quoted, but I'll try to check when I get back.

[PATCH 04/31] ARM: tegra: update DT files to add reset properties

[Stephen Warren]

On 11/29/2013 06:00 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:59PM -0700, Stephen Warren wrote: 
> [...]
>> @@ -135,8 +140,10 @@ reg-shift = <2>; interrupts = <GIC_SPI 37
>> IRQ_TYPE_LEVEL_HIGH>; nvidia,dma-request-selector = <&apbdma 9>; 
>> -		status = "disabled"; clocks = <&tegra_car
>> TEGRA114_CLK_UARTB>; +		resets = <&tegra_car 7>;
> 
> This is confusing. For some reason that escapes me the
> tegra114-car.h file defines TEGRA114_CLK_UARTB as 192. Other reset
> entries match the numerical value of the TEGRA114_CLK_* define,
> which makes it easy to double-check this.
> 
> But UARTB is indeed at bit 7, so this looks good.
> 
> Oh, I think perhaps it's caused by bit 7 being shared by both the
> UARTB and the VFIR controllers for reset, but not for the clocks.

Yes, there's a single reset bit that affects 2 HW modules, yet each HW
module has its own clock. So the reset and clock IDs don't exactly
align. That's the main reason I wanted to switch the drivers to the
reset framework rather than piggy-backing on the clock framework to do
resets, so the difference in name-spaces is explicit.

>> reg = <0x70080300 0x100>; nvidia,ahub-cif-ids = <4 4>; clocks =
>> <&tegra_car TEGRA114_CLK_I2S0>;
> 
> The clocks for these i2s devices are already listed in the ahub
> node. Is that on purpose?

Yes.

The AHUB driver needs to remove reset from the HW modules, so that the
configlink bus works. Reset removal used to require a custom Tegra API
that took a clock as a parameter. Hence, the AHUB node needed the
clock reference. After this series, the AHUB only needs a reset handle
to use the standard reset API. However, the clock references are left
in the AHUB node until after the AHUB driver is converted, so the
series is bisectable. After the series, only the I2S driver needs to
clock references.

>> @@ -110,6 +118,8 @@ reg = <0x54080000 0x00040000>; interrupts =
>> <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car
>> TEGRA30_CLK_VI>; +			resets = <&tegra_car 164>;
> 
> I think this needs to be 20.

OK, I'll check that when I get back...

>> +			 <&tegra_car 30>,  /* i2s0 */ +			 <&tegra_car 11>,  /* i2s1
>> */ +			 <&tegra_car 18>,  /* i2s2 */ +			 <&tegra_car 101>, /*
>> i2s3 */ +			 <&tegra_car 102>, /* i2s4 */
> 
> Some comment for these as for Tegra20.

I'm not sure which other comment was "for Tegra20", since none of the
filenames were quoted, but I'll try to check when I get back.

Re: [PATCH 04/31] ARM: tegra: update DT files to add reset properties

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1586 bytes --]

On Sun, Dec 01, 2013 at 12:15:07PM -0700, Stephen Warren wrote:
> On 11/29/2013 06:00 AM, Thierry Reding wrote:
> > On Fri, Nov 15, 2013 at 01:53:59PM -0700, Stephen Warren wrote: 
[...]
> >> reg = <0x70080300 0x100>; nvidia,ahub-cif-ids = <4 4>; clocks =
> >> <&tegra_car TEGRA114_CLK_I2S0>;
> > 
> > The clocks for these i2s devices are already listed in the ahub
> > node. Is that on purpose?
> 
> Yes.
> 
> The AHUB driver needs to remove reset from the HW modules, so that the
> configlink bus works. Reset removal used to require a custom Tegra API
> that took a clock as a parameter. Hence, the AHUB node needed the
> clock reference. After this series, the AHUB only needs a reset handle
> to use the standard reset API. However, the clock references are left
> in the AHUB node until after the AHUB driver is converted, so the
> series is bisectable. After the series, only the I2S driver needs to
> clock references.
[...]
> >> +			 <&tegra_car 30>,  /* i2s0 */ +			 <&tegra_car 11>,  /* i2s1
> >> */ +			 <&tegra_car 18>,  /* i2s2 */ +			 <&tegra_car 101>, /*
> >> i2s3 */ +			 <&tegra_car 102>, /* i2s4 */
> > 
> > Some comment for these as for Tegra20.
> 
> I'm not sure which other comment was "for Tegra20", since none of the
> filenames were quoted, but I'll try to check when I get back.

Indeed. I didn't quote the filenames. =( And I typoed Tegra114 as
Tegra20. I was referring to the "I2S clocks are listed in both the AHUB
and I2S nodes" comment above for Tegra114. From your earlier reply,
though this looks good then.

Thierry

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[PATCH 04/31] ARM: tegra: update DT files to add reset properties

[Thierry Reding]

On Sun, Dec 01, 2013 at 12:15:07PM -0700, Stephen Warren wrote:
> On 11/29/2013 06:00 AM, Thierry Reding wrote:
> > On Fri, Nov 15, 2013 at 01:53:59PM -0700, Stephen Warren wrote: 
[...]
> >> reg = <0x70080300 0x100>; nvidia,ahub-cif-ids = <4 4>; clocks =
> >> <&tegra_car TEGRA114_CLK_I2S0>;
> > 
> > The clocks for these i2s devices are already listed in the ahub
> > node. Is that on purpose?
> 
> Yes.
> 
> The AHUB driver needs to remove reset from the HW modules, so that the
> configlink bus works. Reset removal used to require a custom Tegra API
> that took a clock as a parameter. Hence, the AHUB node needed the
> clock reference. After this series, the AHUB only needs a reset handle
> to use the standard reset API. However, the clock references are left
> in the AHUB node until after the AHUB driver is converted, so the
> series is bisectable. After the series, only the I2S driver needs to
> clock references.
[...]
> >> +			 <&tegra_car 30>,  /* i2s0 */ +			 <&tegra_car 11>,  /* i2s1
> >> */ +			 <&tegra_car 18>,  /* i2s2 */ +			 <&tegra_car 101>, /*
> >> i2s3 */ +			 <&tegra_car 102>, /* i2s4 */
> > 
> > Some comment for these as for Tegra20.
> 
> I'm not sure which other comment was "for Tegra20", since none of the
> filenames were quoted, but I'll try to check when I get back.

Indeed. I didn't quote the filenames. =( And I typoed Tegra114 as
Tegra20. I was referring to the "I2S clocks are listed in both the AHUB
and I2S nodes" comment above for Tegra114. From your earlier reply,
though this looks good then.

Thierry
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Re: [PATCH 04/31] ARM: tegra: update DT files to add reset properties

[Stephen Warren]

On 11/29/2013 06:00 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:59PM -0700, Stephen Warren wrote:
...
>> @@ -110,6 +118,8 @@ reg = <0x54080000 0x00040000>; interrupts =
>> <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car
>> TEGRA30_CLK_VI>; +			resets = <&tegra_car 164>;
> 
> I think this needs to be 20.

Yes, I've fixed that to be 20 in both tegra20.dtsi and tegra30.dtsi in
this patch.

[PATCH 04/31] ARM: tegra: update DT files to add reset properties

[Stephen Warren]

On 11/29/2013 06:00 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:53:59PM -0700, Stephen Warren wrote:
...
>> @@ -110,6 +118,8 @@ reg = <0x54080000 0x00040000>; interrupts =
>> <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car
>> TEGRA30_CLK_VI>; +			resets = <&tegra_car 164>;
> 
> I think this needs to be 20.

Yes, I've fixed that to be 20 in both tegra20.dtsi and tegra30.dtsi in
this patch.

[PATCH 05/31] ARM: tegra: update DT files to add DMA properties

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

This patch switches the Tegra DT files to use the standard DMA DT bindings
rather than custom properties. Note that the legacy properties are not yet
removed; the drivers must be updated to use the new properties first.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/tegra114.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/tegra20.dtsi  | 35 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/tegra30.dtsi  | 39 +++++++++++++++++++++++++++++++++++
 3 files changed, 119 insertions(+)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index c40dbdcb3741..b4f2e62909a7 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -84,6 +84,7 @@
 		clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
 		resets = <&tegra_car 34>;
 		reset-names = "dma";
+		#dma-cells = <1>;
 	};
 
 	ahb: ahb {
@@ -131,6 +132,8 @@
 		clocks = <&tegra_car TEGRA114_CLK_UARTA>;
 		resets = <&tegra_car 6>;
 		reset-names = "serial";
+		dmas = <&apbdma 8>, <&apbdma 8>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -143,6 +146,8 @@
 		clocks = <&tegra_car TEGRA114_CLK_UARTB>;
 		resets = <&tegra_car 7>;
 		reset-names = "serial";
+		dmas = <&apbdma 9>, <&apbdma 9>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -155,6 +160,8 @@
 		clocks = <&tegra_car TEGRA114_CLK_UARTC>;
 		resets = <&tegra_car 55>;
 		reset-names = "serial";
+		dmas = <&apbdma 10>, <&apbdma 10>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -167,6 +174,8 @@
 		clocks = <&tegra_car TEGRA114_CLK_UARTD>;
 		resets = <&tegra_car 65>;
 		reset-names = "serial";
+		dmas = <&apbdma 19>, <&apbdma 19>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -190,6 +199,8 @@
 		clock-names = "div-clk";
 		resets = <&tegra_car 12>;
 		reset-names = "i2c";
+		dmas = <&apbdma 21>, <&apbdma 21>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -203,6 +214,8 @@
 		clock-names = "div-clk";
 		resets = <&tegra_car 54>;
 		reset-names = "i2c";
+		dmas = <&apbdma 22>, <&apbdma 22>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -216,6 +229,8 @@
 		clock-names = "div-clk";
 		resets = <&tegra_car 67>;
 		reset-names = "i2c";
+		dmas = <&apbdma 23>, <&apbdma 23>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -229,6 +244,8 @@
 		clock-names = "div-clk";
 		resets = <&tegra_car 103>;
 		reset-names = "i2c";
+		dmas = <&apbdma 26>, <&apbdma 26>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -242,6 +259,8 @@
 		clock-names = "div-clk";
 		resets = <&tegra_car 47>;
 		reset-names = "i2c";
+		dmas = <&apbdma 24>, <&apbdma 24>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -256,6 +275,8 @@
 		clock-names = "spi";
 		resets = <&tegra_car 41>;
 		reset-names = "spi";
+		dmas = <&apbdma 15>, <&apbdma 15>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -270,6 +291,8 @@
 		clock-names = "spi";
 		resets = <&tegra_car 44>;
 		reset-names = "spi";
+		dmas = <&apbdma 16>, <&apbdma 16>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -284,6 +307,8 @@
 		clock-names = "spi";
 		resets = <&tegra_car 46>;
 		reset-names = "spi";
+		dmas = <&apbdma 17>, <&apbdma 17>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -298,6 +323,8 @@
 		clock-names = "spi";
 		resets = <&tegra_car 68>;
 		reset-names = "spi";
+		dmas = <&apbdma 18>, <&apbdma 18>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -312,6 +339,8 @@
 		clock-names = "spi";
 		resets = <&tegra_car 104>;
 		reset-names = "spi";
+		dmas = <&apbdma 27>, <&apbdma 27>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -326,6 +355,8 @@
 		clock-names = "spi";
 		resets = <&tegra_car 105>;
 		reset-names = "spi";
+		dmas = <&apbdma 28>, <&apbdma 28>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -406,6 +437,20 @@
 		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
 			      "spdif", "amx", "adx";
+		dmas = <&apbdma 1>, <&apbdma 1>,
+		       <&apbdma 2>, <&apbdma 2>,
+		       <&apbdma 3>, <&apbdma 3>,
+		       <&apbdma 4>, <&apbdma 4>,
+		       <&apbdma 6>, <&apbdma 6>,
+		       <&apbdma 7>, <&apbdma 7>,
+		       <&apbdma 12>, <&apbdma 12>,
+		       <&apbdma 13>, <&apbdma 13>,
+		       <&apbdma 14>, <&apbdma 14>,
+		       <&apbdma 29>, <&apbdma 29>;
+		dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
+			    "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
+			    "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
+			    "rx9", "tx9";
 		ranges;
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 159facbce524..c53e02e08310 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -207,6 +207,7 @@
 		clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
 		resets = <&tegra_car 34>;
 		reset-names = "dma";
+		#dma-cells = <1>;
 	};
 
 	ahb {
@@ -251,6 +252,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_AC97>;
 		resets = <&tegra_car 3>;
 		reset-names = "ac97";
+		dmas = <&apbdma 12>, <&apbdma 12>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -262,6 +265,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2S1>;
 		resets = <&tegra_car 11>;
 		reset-names = "i2s";
+		dmas = <&apbdma 2>, <&apbdma 2>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -273,6 +278,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2S2>;
 		resets = <&tegra_car 18>;
 		reset-names = "i2s";
+		dmas = <&apbdma 1>, <&apbdma 1>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -292,6 +299,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_UARTA>;
 		resets = <&tegra_car 6>;
 		reset-names = "serial";
+		dmas = <&apbdma 8>, <&apbdma 8>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -304,6 +313,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_UARTB>;
 		resets = <&tegra_car 7>;
 		reset-names = "serial";
+		dmas = <&apbdma 9>, <&apbdma 9>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -316,6 +327,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_UARTC>;
 		resets = <&tegra_car 55>;
 		reset-names = "serial";
+		dmas = <&apbdma 10>, <&apbdma 10>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -328,6 +341,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_UARTD>;
 		resets = <&tegra_car 65>;
 		reset-names = "serial";
+		dmas = <&apbdma 19>, <&apbdma 19>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -340,6 +355,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_UARTE>;
 		resets = <&tegra_car 66>;
 		reset-names = "serial";
+		dmas = <&apbdma 20>, <&apbdma 20>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -371,6 +388,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 12>;
 		reset-names = "i2c";
+		dmas = <&apbdma 21>, <&apbdma 21>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -384,6 +403,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_SPI>;
 		resets = <&tegra_car 43>;
 		reset-names = "spi";
+		dmas = <&apbdma 11>, <&apbdma 11>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -398,6 +419,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 54>;
 		reset-names = "i2c";
+		dmas = <&apbdma 22>, <&apbdma 22>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -412,6 +435,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 67>;
 		reset-names = "i2c";
+		dmas = <&apbdma 23>, <&apbdma 23>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -426,6 +451,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 47>;
 		reset-names = "i2c";
+		dmas = <&apbdma 24>, <&apbdma 24>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -439,6 +466,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_SBC1>;
 		resets = <&tegra_car 41>;
 		reset-names = "spi";
+		dmas = <&apbdma 15>, <&apbdma 15>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -452,6 +481,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_SBC2>;
 		resets = <&tegra_car 44>;
 		reset-names = "spi";
+		dmas = <&apbdma 16>, <&apbdma 16>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -465,6 +496,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_SBC3>;
 		resets = <&tegra_car 46>;
 		reset-names = "spi";
+		dmas = <&apbdma 17>, <&apbdma 17>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -478,6 +511,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_SBC4>;
 		resets = <&tegra_car 68>;
 		reset-names = "spi";
+		dmas = <&apbdma 18>, <&apbdma 18>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 95635e54bd34..0e69dd9f33e6 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -302,6 +302,7 @@
 		clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
 		resets = <&tegra_car 34>;
 		reset-names = "dma";
+		#dma-cells = <1>;
 	};
 
 	ahb: ahb {
@@ -349,6 +350,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_UARTA>;
 		resets = <&tegra_car 6>;
 		reset-names = "serial";
+		dmas = <&apbdma 8>, <&apbdma 8>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -361,6 +364,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_UARTB>;
 		resets = <&tegra_car 7>;
 		reset-names = "serial";
+		dmas = <&apbdma 9>, <&apbdma 9>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -373,6 +378,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_UARTC>;
 		resets = <&tegra_car 55>;
 		reset-names = "serial";
+		dmas = <&apbdma 10>, <&apbdma 10>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -385,6 +392,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_UARTD>;
 		resets = <&tegra_car 65>;
 		reset-names = "serial";
+		dmas = <&apbdma 19>, <&apbdma 19>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -397,6 +406,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_UARTE>;
 		resets = <&tegra_car 66>;
 		reset-names = "serial";
+		dmas = <&apbdma 20>, <&apbdma 20>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -428,6 +439,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 12>;
 		reset-names = "i2c";
+		dmas = <&apbdma 21>, <&apbdma 21>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -442,6 +455,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 54>;
 		reset-names = "i2c";
+		dmas = <&apbdma 22>, <&apbdma 22>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -456,6 +471,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 67>;
 		reset-names = "i2c";
+		dmas = <&apbdma 23>, <&apbdma 23>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -470,6 +487,8 @@
 		resets = <&tegra_car 103>;
 		reset-names = "i2c";
 		clock-names = "div-clk", "fast-clk";
+		dmas = <&apbdma 26>, <&apbdma 26>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -484,6 +503,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 47>;
 		reset-names = "i2c";
+		dmas = <&apbdma 24>, <&apbdma 24>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -497,6 +518,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_SBC1>;
 		resets = <&tegra_car 41>;
 		reset-names = "spi";
+		dmas = <&apbdma 15>, <&apbdma 15>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -510,6 +533,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_SBC2>;
 		resets = <&tegra_car 44>;
 		reset-names = "spi";
+		dmas = <&apbdma 16>, <&apbdma 16>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -523,6 +548,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_SBC3>;
 		resets = <&tegra_car 46>;
 		reset-names = "spi";
+		dmas = <&apbdma 17>, <&apbdma 17>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -536,6 +563,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_SBC4>;
 		resets = <&tegra_car 68>;
 		reset-names = "spi";
+		dmas = <&apbdma 18>, <&apbdma 18>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -549,6 +578,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_SBC5>;
 		resets = <&tegra_car 104>;
 		reset-names = "spi";
+		dmas = <&apbdma 27>, <&apbdma 27>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -562,6 +593,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_SBC6>;
 		resets = <&tegra_car 106>;
 		reset-names = "spi";
+		dmas = <&apbdma 28>, <&apbdma 28>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -635,6 +668,12 @@
 		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
 			      "spdif";
+		dmas = <&apbdma 1>, <&apbdma 1>,
+		       <&apbdma 2>, <&apbdma 2>,
+		       <&apbdma 3>, <&apbdma 3>,
+		       <&apbdma 4>, <&apbdma 4>;
+		dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
+			    "rx3", "tx3";
 		ranges;
 		#address-cells = <1>;
 		#size-cells = <1>;
-- 
1.8.1.5

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[PATCH 05/31] ARM: tegra: update DT files to add DMA properties

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

This patch switches the Tegra DT files to use the standard DMA DT bindings
rather than custom properties. Note that the legacy properties are not yet
removed; the drivers must be updated to use the new properties first.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: devicetree at vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 arch/arm/boot/dts/tegra114.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/tegra20.dtsi  | 35 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/tegra30.dtsi  | 39 +++++++++++++++++++++++++++++++++++
 3 files changed, 119 insertions(+)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index c40dbdcb3741..b4f2e62909a7 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -84,6 +84,7 @@
 		clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
 		resets = <&tegra_car 34>;
 		reset-names = "dma";
+		#dma-cells = <1>;
 	};
 
 	ahb: ahb {
@@ -131,6 +132,8 @@
 		clocks = <&tegra_car TEGRA114_CLK_UARTA>;
 		resets = <&tegra_car 6>;
 		reset-names = "serial";
+		dmas = <&apbdma 8>, <&apbdma 8>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -143,6 +146,8 @@
 		clocks = <&tegra_car TEGRA114_CLK_UARTB>;
 		resets = <&tegra_car 7>;
 		reset-names = "serial";
+		dmas = <&apbdma 9>, <&apbdma 9>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -155,6 +160,8 @@
 		clocks = <&tegra_car TEGRA114_CLK_UARTC>;
 		resets = <&tegra_car 55>;
 		reset-names = "serial";
+		dmas = <&apbdma 10>, <&apbdma 10>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -167,6 +174,8 @@
 		clocks = <&tegra_car TEGRA114_CLK_UARTD>;
 		resets = <&tegra_car 65>;
 		reset-names = "serial";
+		dmas = <&apbdma 19>, <&apbdma 19>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -190,6 +199,8 @@
 		clock-names = "div-clk";
 		resets = <&tegra_car 12>;
 		reset-names = "i2c";
+		dmas = <&apbdma 21>, <&apbdma 21>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -203,6 +214,8 @@
 		clock-names = "div-clk";
 		resets = <&tegra_car 54>;
 		reset-names = "i2c";
+		dmas = <&apbdma 22>, <&apbdma 22>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -216,6 +229,8 @@
 		clock-names = "div-clk";
 		resets = <&tegra_car 67>;
 		reset-names = "i2c";
+		dmas = <&apbdma 23>, <&apbdma 23>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -229,6 +244,8 @@
 		clock-names = "div-clk";
 		resets = <&tegra_car 103>;
 		reset-names = "i2c";
+		dmas = <&apbdma 26>, <&apbdma 26>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -242,6 +259,8 @@
 		clock-names = "div-clk";
 		resets = <&tegra_car 47>;
 		reset-names = "i2c";
+		dmas = <&apbdma 24>, <&apbdma 24>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -256,6 +275,8 @@
 		clock-names = "spi";
 		resets = <&tegra_car 41>;
 		reset-names = "spi";
+		dmas = <&apbdma 15>, <&apbdma 15>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -270,6 +291,8 @@
 		clock-names = "spi";
 		resets = <&tegra_car 44>;
 		reset-names = "spi";
+		dmas = <&apbdma 16>, <&apbdma 16>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -284,6 +307,8 @@
 		clock-names = "spi";
 		resets = <&tegra_car 46>;
 		reset-names = "spi";
+		dmas = <&apbdma 17>, <&apbdma 17>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -298,6 +323,8 @@
 		clock-names = "spi";
 		resets = <&tegra_car 68>;
 		reset-names = "spi";
+		dmas = <&apbdma 18>, <&apbdma 18>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -312,6 +339,8 @@
 		clock-names = "spi";
 		resets = <&tegra_car 104>;
 		reset-names = "spi";
+		dmas = <&apbdma 27>, <&apbdma 27>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -326,6 +355,8 @@
 		clock-names = "spi";
 		resets = <&tegra_car 105>;
 		reset-names = "spi";
+		dmas = <&apbdma 28>, <&apbdma 28>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -406,6 +437,20 @@
 		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
 			      "spdif", "amx", "adx";
+		dmas = <&apbdma 1>, <&apbdma 1>,
+		       <&apbdma 2>, <&apbdma 2>,
+		       <&apbdma 3>, <&apbdma 3>,
+		       <&apbdma 4>, <&apbdma 4>,
+		       <&apbdma 6>, <&apbdma 6>,
+		       <&apbdma 7>, <&apbdma 7>,
+		       <&apbdma 12>, <&apbdma 12>,
+		       <&apbdma 13>, <&apbdma 13>,
+		       <&apbdma 14>, <&apbdma 14>,
+		       <&apbdma 29>, <&apbdma 29>;
+		dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
+			    "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
+			    "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
+			    "rx9", "tx9";
 		ranges;
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 159facbce524..c53e02e08310 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -207,6 +207,7 @@
 		clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
 		resets = <&tegra_car 34>;
 		reset-names = "dma";
+		#dma-cells = <1>;
 	};
 
 	ahb {
@@ -251,6 +252,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_AC97>;
 		resets = <&tegra_car 3>;
 		reset-names = "ac97";
+		dmas = <&apbdma 12>, <&apbdma 12>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -262,6 +265,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2S1>;
 		resets = <&tegra_car 11>;
 		reset-names = "i2s";
+		dmas = <&apbdma 2>, <&apbdma 2>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -273,6 +278,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2S2>;
 		resets = <&tegra_car 18>;
 		reset-names = "i2s";
+		dmas = <&apbdma 1>, <&apbdma 1>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -292,6 +299,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_UARTA>;
 		resets = <&tegra_car 6>;
 		reset-names = "serial";
+		dmas = <&apbdma 8>, <&apbdma 8>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -304,6 +313,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_UARTB>;
 		resets = <&tegra_car 7>;
 		reset-names = "serial";
+		dmas = <&apbdma 9>, <&apbdma 9>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -316,6 +327,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_UARTC>;
 		resets = <&tegra_car 55>;
 		reset-names = "serial";
+		dmas = <&apbdma 10>, <&apbdma 10>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -328,6 +341,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_UARTD>;
 		resets = <&tegra_car 65>;
 		reset-names = "serial";
+		dmas = <&apbdma 19>, <&apbdma 19>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -340,6 +355,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_UARTE>;
 		resets = <&tegra_car 66>;
 		reset-names = "serial";
+		dmas = <&apbdma 20>, <&apbdma 20>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -371,6 +388,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 12>;
 		reset-names = "i2c";
+		dmas = <&apbdma 21>, <&apbdma 21>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -384,6 +403,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_SPI>;
 		resets = <&tegra_car 43>;
 		reset-names = "spi";
+		dmas = <&apbdma 11>, <&apbdma 11>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -398,6 +419,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 54>;
 		reset-names = "i2c";
+		dmas = <&apbdma 22>, <&apbdma 22>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -412,6 +435,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 67>;
 		reset-names = "i2c";
+		dmas = <&apbdma 23>, <&apbdma 23>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -426,6 +451,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 47>;
 		reset-names = "i2c";
+		dmas = <&apbdma 24>, <&apbdma 24>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -439,6 +466,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_SBC1>;
 		resets = <&tegra_car 41>;
 		reset-names = "spi";
+		dmas = <&apbdma 15>, <&apbdma 15>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -452,6 +481,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_SBC2>;
 		resets = <&tegra_car 44>;
 		reset-names = "spi";
+		dmas = <&apbdma 16>, <&apbdma 16>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -465,6 +496,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_SBC3>;
 		resets = <&tegra_car 46>;
 		reset-names = "spi";
+		dmas = <&apbdma 17>, <&apbdma 17>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -478,6 +511,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_SBC4>;
 		resets = <&tegra_car 68>;
 		reset-names = "spi";
+		dmas = <&apbdma 18>, <&apbdma 18>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 95635e54bd34..0e69dd9f33e6 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -302,6 +302,7 @@
 		clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
 		resets = <&tegra_car 34>;
 		reset-names = "dma";
+		#dma-cells = <1>;
 	};
 
 	ahb: ahb {
@@ -349,6 +350,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_UARTA>;
 		resets = <&tegra_car 6>;
 		reset-names = "serial";
+		dmas = <&apbdma 8>, <&apbdma 8>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -361,6 +364,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_UARTB>;
 		resets = <&tegra_car 7>;
 		reset-names = "serial";
+		dmas = <&apbdma 9>, <&apbdma 9>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -373,6 +378,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_UARTC>;
 		resets = <&tegra_car 55>;
 		reset-names = "serial";
+		dmas = <&apbdma 10>, <&apbdma 10>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -385,6 +392,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_UARTD>;
 		resets = <&tegra_car 65>;
 		reset-names = "serial";
+		dmas = <&apbdma 19>, <&apbdma 19>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -397,6 +406,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_UARTE>;
 		resets = <&tegra_car 66>;
 		reset-names = "serial";
+		dmas = <&apbdma 20>, <&apbdma 20>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -428,6 +439,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 12>;
 		reset-names = "i2c";
+		dmas = <&apbdma 21>, <&apbdma 21>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -442,6 +455,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 54>;
 		reset-names = "i2c";
+		dmas = <&apbdma 22>, <&apbdma 22>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -456,6 +471,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 67>;
 		reset-names = "i2c";
+		dmas = <&apbdma 23>, <&apbdma 23>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -470,6 +487,8 @@
 		resets = <&tegra_car 103>;
 		reset-names = "i2c";
 		clock-names = "div-clk", "fast-clk";
+		dmas = <&apbdma 26>, <&apbdma 26>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -484,6 +503,8 @@
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 47>;
 		reset-names = "i2c";
+		dmas = <&apbdma 24>, <&apbdma 24>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -497,6 +518,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_SBC1>;
 		resets = <&tegra_car 41>;
 		reset-names = "spi";
+		dmas = <&apbdma 15>, <&apbdma 15>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -510,6 +533,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_SBC2>;
 		resets = <&tegra_car 44>;
 		reset-names = "spi";
+		dmas = <&apbdma 16>, <&apbdma 16>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -523,6 +548,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_SBC3>;
 		resets = <&tegra_car 46>;
 		reset-names = "spi";
+		dmas = <&apbdma 17>, <&apbdma 17>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -536,6 +563,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_SBC4>;
 		resets = <&tegra_car 68>;
 		reset-names = "spi";
+		dmas = <&apbdma 18>, <&apbdma 18>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -549,6 +578,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_SBC5>;
 		resets = <&tegra_car 104>;
 		reset-names = "spi";
+		dmas = <&apbdma 27>, <&apbdma 27>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -562,6 +593,8 @@
 		clocks = <&tegra_car TEGRA30_CLK_SBC6>;
 		resets = <&tegra_car 106>;
 		reset-names = "spi";
+		dmas = <&apbdma 28>, <&apbdma 28>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
@@ -635,6 +668,12 @@
 		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
 			      "spdif";
+		dmas = <&apbdma 1>, <&apbdma 1>,
+		       <&apbdma 2>, <&apbdma 2>,
+		       <&apbdma 3>, <&apbdma 3>,
+		       <&apbdma 4>, <&apbdma 4>;
+		dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
+			    "rx3", "tx3";
 		ranges;
 		#address-cells = <1>;
 		#size-cells = <1>;
-- 
1.8.1.5

Re: [PATCH 05/31] ARM: tegra: update DT files to add DMA properties

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1400 bytes --]

On Fri, Nov 15, 2013 at 01:54:00PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> This patch switches the Tegra DT files to use the standard DMA DT bindings
> rather than custom properties. Note that the legacy properties are not yet
> removed; the drivers must be updated to use the new properties first.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
> Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>  arch/arm/boot/dts/tegra114.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/tegra20.dtsi  | 35 ++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/tegra30.dtsi  | 39 +++++++++++++++++++++++++++++++++++
>  3 files changed, 119 insertions(+)

Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]

[PATCH 05/31] ARM: tegra: update DT files to add DMA properties

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:54:00PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> This patch switches the Tegra DT files to use the standard DMA DT bindings
> rather than custom properties. Note that the legacy properties are not yet
> removed; the drivers must be updated to use the new properties first.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Pawel Moll <pawel.moll@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
> Cc: devicetree at vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
>  arch/arm/boot/dts/tegra114.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/tegra20.dtsi  | 35 ++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/tegra30.dtsi  | 39 +++++++++++++++++++++++++++++++++++
>  3 files changed, 119 insertions(+)

Reviewed-by: Thierry Reding <treding@nvidia.com>
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[PATCH 06/31] ARM: tegra: select the reset framework

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

The Tegra clock driver is built unconditionally when Tegra support is
enabled. In order to avoid having to ifdef the forthcoming reset driver
implementation, have ARCH_TEGRA select RESET_CONTROLLER.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/mach-tegra/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 09e740f58b27..15c09294effa 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -14,6 +14,8 @@ config ARCH_TEGRA
 	select MIGHT_HAVE_CACHE_L2X0
 	select MIGHT_HAVE_PCI
 	select PINCTRL
+	select ARCH_HAS_RESET_CONTROLLER
+	select RESET_CONTROLLER
 	select SOC_BUS
 	select SPARSE_IRQ
 	select USB_ARCH_HAS_EHCI if USB_SUPPORT
-- 
1.8.1.5

[PATCH 06/31] ARM: tegra: select the reset framework

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

The Tegra clock driver is built unconditionally when Tegra support is
enabled. In order to avoid having to ifdef the forthcoming reset driver
implementation, have ARCH_TEGRA select RESET_CONTROLLER.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 arch/arm/mach-tegra/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 09e740f58b27..15c09294effa 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -14,6 +14,8 @@ config ARCH_TEGRA
 	select MIGHT_HAVE_CACHE_L2X0
 	select MIGHT_HAVE_PCI
 	select PINCTRL
+	select ARCH_HAS_RESET_CONTROLLER
+	select RESET_CONTROLLER
 	select SOC_BUS
 	select SPARSE_IRQ
 	select USB_ARCH_HAS_EHCI if USB_SUPPORT
-- 
1.8.1.5

Re: [PATCH 06/31] ARM: tegra: select the reset framework

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1537 bytes --]

On Fri, Nov 15, 2013 at 01:54:01PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> The Tegra clock driver is built unconditionally when Tegra support is
> enabled. In order to avoid having to ifdef the forthcoming reset driver
> implementation, have ARCH_TEGRA select RESET_CONTROLLER.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>  arch/arm/mach-tegra/Kconfig | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
> index 09e740f58b27..15c09294effa 100644
> --- a/arch/arm/mach-tegra/Kconfig
> +++ b/arch/arm/mach-tegra/Kconfig
> @@ -14,6 +14,8 @@ config ARCH_TEGRA
>  	select MIGHT_HAVE_CACHE_L2X0
>  	select MIGHT_HAVE_PCI
>  	select PINCTRL
> +	select ARCH_HAS_RESET_CONTROLLER
> +	select RESET_CONTROLLER

I don't think RESET_CONTROLLER is necessary given this:

	menuconfig RESET_CONTROLLER
		bool "Reset Controller Support"
		default y if ARCH_HAS_RESET_CONTROLLER

I suppose that would still make it possible to deselect RESET_CONTROLLER
and cause breakage. Explicitly selecting it avoids that, so:

Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

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[PATCH 06/31] ARM: tegra: select the reset framework

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:54:01PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> The Tegra clock driver is built unconditionally when Tegra support is
> enabled. In order to avoid having to ifdef the forthcoming reset driver
> implementation, have ARCH_TEGRA select RESET_CONTROLLER.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
>  arch/arm/mach-tegra/Kconfig | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
> index 09e740f58b27..15c09294effa 100644
> --- a/arch/arm/mach-tegra/Kconfig
> +++ b/arch/arm/mach-tegra/Kconfig
> @@ -14,6 +14,8 @@ config ARCH_TEGRA
>  	select MIGHT_HAVE_CACHE_L2X0
>  	select MIGHT_HAVE_PCI
>  	select PINCTRL
> +	select ARCH_HAS_RESET_CONTROLLER
> +	select RESET_CONTROLLER

I don't think RESET_CONTROLLER is necessary given this:

	menuconfig RESET_CONTROLLER
		bool "Reset Controller Support"
		default y if ARCH_HAS_RESET_CONTROLLER

I suppose that would still make it possible to deselect RESET_CONTROLLER
and cause breakage. Explicitly selecting it avoids that, so:

Reviewed-by: Thierry Reding <treding@nvidia.com>
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[PATCH 07/31] clk: tegra: implement a reset driver

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

The Tegra CAR module implements both a clock and reset controller. So
far, the driver exposes the clock feature via the common clock API and
the reset feature using a custom API. This patch adds an implementation
of the common reset framework API (include/linux/reset*.h). The legacy
reset implementation will be removed once all drivers have been
converted.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/clk/tegra/clk-tegra114.c |  3 ++-
 drivers/clk/tegra/clk-tegra124.c |  2 +-
 drivers/clk/tegra/clk-tegra20.c  |  3 ++-
 drivers/clk/tegra/clk-tegra30.c  |  3 ++-
 drivers/clk/tegra/clk.c          | 55 +++++++++++++++++++++++++++++++++++++++-
 drivers/clk/tegra/clk.h          |  2 +-
 6 files changed, 62 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 9036a22ee5aa..207a15ac062f 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1464,7 +1464,8 @@ static void __init tegra114_clock_init(struct device_node *np)
 		return;
 	}
 
-	clks = tegra_clk_init(TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_PERIPH_BANKS);
+	clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX,
+				TEGRA114_CLK_PERIPH_BANKS);
 	if (!clks)
 		return;
 
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 266e80b51d38..9adee736d7fa 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1404,7 +1404,7 @@ static void __init tegra124_clock_init(struct device_node *np)
 		return;
 	}
 
-	clks = tegra_clk_init(TEGRA124_CLK_CLK_MAX, 6);
+	clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX, 6);
 	if (!clks)
 		return;
 
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 58faac5f509e..eeffff6c6778 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1114,7 +1114,8 @@ static void __init tegra20_clock_init(struct device_node *np)
 		BUG();
 	}
 
-	clks = tegra_clk_init(TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_PERIPH_BANKS);
+	clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX,
+				TEGRA20_CLK_PERIPH_BANKS);
 	if (!clks)
 		return;
 
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 51c093c96657..e9b6a305be92 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1436,7 +1436,8 @@ static void __init tegra30_clock_init(struct device_node *np)
 		BUG();
 	}
 
-	clks = tegra_clk_init(TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_PERIPH_BANKS);
+	clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,
+				TEGRA30_CLK_PERIPH_BANKS);
 	if (!clks)
 		return;
 
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index a12a5f5107ec..f20199a534bd 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -18,6 +18,8 @@
 #include <linux/clk-provider.h>
 #include <linux/of.h>
 #include <linux/clk/tegra.h>
+#include <linux/reset-controller.h>
+#include <linux/tegra-soc.h>
 
 #include "clk.h"
 
@@ -60,6 +62,11 @@
 #define RST_DEVICES_SET_X		0x290
 #define RST_DEVICES_CLR_X		0x294
 
+static int tegra_clk_rst_assert(struct reset_controller_dev *rcdev,
+		unsigned long id);
+static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev,
+		unsigned long id);
+
 /* Global data of Tegra CPU CAR ops */
 static struct tegra_cpu_car_ops dummy_car_ops;
 struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
@@ -70,6 +77,17 @@ static struct clk **clks;
 static int clk_num;
 static struct clk_onecell_data clk_data;
 
+static struct reset_control_ops rst_ops = {
+	.assert = tegra_clk_rst_assert,
+	.deassert = tegra_clk_rst_deassert,
+};
+
+static struct reset_controller_dev rst_ctlr = {
+	.ops = &rst_ops,
+	.owner = THIS_MODULE,
+	.of_reset_n_cells = 1,
+};
+
 static struct tegra_clk_periph_regs periph_regs[] = {
 	[0] = {
 		.enb_reg = CLK_OUT_ENB_L,
@@ -121,6 +139,35 @@ static struct tegra_clk_periph_regs periph_regs[] = {
 	},
 };
 
+static void __iomem *clk_base;
+
+static int tegra_clk_rst_assert(struct reset_controller_dev *rcdev,
+		unsigned long id)
+{
+	/*
+	 * If peripheral is on the APB bus then we must read the APB bus to
+	 * flush the write operation in apb bus. This will avoid peripheral
+	 * access after disabling clock. Since the reset driver has no
+	 * knowledge of which reset IDs represent which devices, simply do
+	 * this all the time.
+	 */
+	tegra_read_chipid();
+
+	writel_relaxed(BIT(id % 32),
+			clk_base + periph_regs[id / 32].rst_set_reg);
+
+	return 0;
+}
+
+static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev,
+		unsigned long id)
+{
+	writel_relaxed(BIT(id % 32),
+			clk_base + periph_regs[id / 32].rst_clr_reg);
+
+	return 0;
+}
+
 struct tegra_clk_periph_regs *get_reg_bank(int clkid)
 {
 	int reg_bank = clkid / 32;
@@ -133,8 +180,10 @@ struct tegra_clk_periph_regs *get_reg_bank(int clkid)
 	}
 }
 
-struct clk ** __init tegra_clk_init(int num, int banks)
+struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)
 {
+	clk_base = regs;
+
 	if (WARN_ON(banks > ARRAY_SIZE(periph_regs)))
 		return NULL;
 
@@ -220,6 +269,10 @@ void __init tegra_add_of_provider(struct device_node *np)
 	clk_data.clks = clks;
 	clk_data.clk_num = clk_num;
 	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+	rst_ctlr.of_node = np;
+	rst_ctlr.nr_resets = clk_num * 32;
+	reset_controller_register(&rst_ctlr);
 }
 
 void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num)
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 7f110acfe2a1..39f24959daf7 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -594,7 +594,7 @@ void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
 		struct clk *clks[], int clk_max);
 
 struct tegra_clk_periph_regs *get_reg_bank(int clkid);
-struct clk **tegra_clk_init(int num, int periph_banks);
+struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks);
 
 struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk);
 
-- 
1.8.1.5

[PATCH 07/31] clk: tegra: implement a reset driver

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

The Tegra CAR module implements both a clock and reset controller. So
far, the driver exposes the clock feature via the common clock API and
the reset feature using a custom API. This patch adds an implementation
of the common reset framework API (include/linux/reset*.h). The legacy
reset implementation will be removed once all drivers have been
converted.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/clk/tegra/clk-tegra114.c |  3 ++-
 drivers/clk/tegra/clk-tegra124.c |  2 +-
 drivers/clk/tegra/clk-tegra20.c  |  3 ++-
 drivers/clk/tegra/clk-tegra30.c  |  3 ++-
 drivers/clk/tegra/clk.c          | 55 +++++++++++++++++++++++++++++++++++++++-
 drivers/clk/tegra/clk.h          |  2 +-
 6 files changed, 62 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 9036a22ee5aa..207a15ac062f 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1464,7 +1464,8 @@ static void __init tegra114_clock_init(struct device_node *np)
 		return;
 	}
 
-	clks = tegra_clk_init(TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_PERIPH_BANKS);
+	clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX,
+				TEGRA114_CLK_PERIPH_BANKS);
 	if (!clks)
 		return;
 
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 266e80b51d38..9adee736d7fa 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1404,7 +1404,7 @@ static void __init tegra124_clock_init(struct device_node *np)
 		return;
 	}
 
-	clks = tegra_clk_init(TEGRA124_CLK_CLK_MAX, 6);
+	clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX, 6);
 	if (!clks)
 		return;
 
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 58faac5f509e..eeffff6c6778 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1114,7 +1114,8 @@ static void __init tegra20_clock_init(struct device_node *np)
 		BUG();
 	}
 
-	clks = tegra_clk_init(TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_PERIPH_BANKS);
+	clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX,
+				TEGRA20_CLK_PERIPH_BANKS);
 	if (!clks)
 		return;
 
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 51c093c96657..e9b6a305be92 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1436,7 +1436,8 @@ static void __init tegra30_clock_init(struct device_node *np)
 		BUG();
 	}
 
-	clks = tegra_clk_init(TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_PERIPH_BANKS);
+	clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,
+				TEGRA30_CLK_PERIPH_BANKS);
 	if (!clks)
 		return;
 
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index a12a5f5107ec..f20199a534bd 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -18,6 +18,8 @@
 #include <linux/clk-provider.h>
 #include <linux/of.h>
 #include <linux/clk/tegra.h>
+#include <linux/reset-controller.h>
+#include <linux/tegra-soc.h>
 
 #include "clk.h"
 
@@ -60,6 +62,11 @@
 #define RST_DEVICES_SET_X		0x290
 #define RST_DEVICES_CLR_X		0x294
 
+static int tegra_clk_rst_assert(struct reset_controller_dev *rcdev,
+		unsigned long id);
+static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev,
+		unsigned long id);
+
 /* Global data of Tegra CPU CAR ops */
 static struct tegra_cpu_car_ops dummy_car_ops;
 struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
@@ -70,6 +77,17 @@ static struct clk **clks;
 static int clk_num;
 static struct clk_onecell_data clk_data;
 
+static struct reset_control_ops rst_ops = {
+	.assert = tegra_clk_rst_assert,
+	.deassert = tegra_clk_rst_deassert,
+};
+
+static struct reset_controller_dev rst_ctlr = {
+	.ops = &rst_ops,
+	.owner = THIS_MODULE,
+	.of_reset_n_cells = 1,
+};
+
 static struct tegra_clk_periph_regs periph_regs[] = {
 	[0] = {
 		.enb_reg = CLK_OUT_ENB_L,
@@ -121,6 +139,35 @@ static struct tegra_clk_periph_regs periph_regs[] = {
 	},
 };
 
+static void __iomem *clk_base;
+
+static int tegra_clk_rst_assert(struct reset_controller_dev *rcdev,
+		unsigned long id)
+{
+	/*
+	 * If peripheral is on the APB bus then we must read the APB bus to
+	 * flush the write operation in apb bus. This will avoid peripheral
+	 * access after disabling clock. Since the reset driver has no
+	 * knowledge of which reset IDs represent which devices, simply do
+	 * this all the time.
+	 */
+	tegra_read_chipid();
+
+	writel_relaxed(BIT(id % 32),
+			clk_base + periph_regs[id / 32].rst_set_reg);
+
+	return 0;
+}
+
+static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev,
+		unsigned long id)
+{
+	writel_relaxed(BIT(id % 32),
+			clk_base + periph_regs[id / 32].rst_clr_reg);
+
+	return 0;
+}
+
 struct tegra_clk_periph_regs *get_reg_bank(int clkid)
 {
 	int reg_bank = clkid / 32;
@@ -133,8 +180,10 @@ struct tegra_clk_periph_regs *get_reg_bank(int clkid)
 	}
 }
 
-struct clk ** __init tegra_clk_init(int num, int banks)
+struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)
 {
+	clk_base = regs;
+
 	if (WARN_ON(banks > ARRAY_SIZE(periph_regs)))
 		return NULL;
 
@@ -220,6 +269,10 @@ void __init tegra_add_of_provider(struct device_node *np)
 	clk_data.clks = clks;
 	clk_data.clk_num = clk_num;
 	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+	rst_ctlr.of_node = np;
+	rst_ctlr.nr_resets = clk_num * 32;
+	reset_controller_register(&rst_ctlr);
 }
 
 void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num)
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 7f110acfe2a1..39f24959daf7 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -594,7 +594,7 @@ void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
 		struct clk *clks[], int clk_max);
 
 struct tegra_clk_periph_regs *get_reg_bank(int clkid);
-struct clk **tegra_clk_init(int num, int periph_banks);
+struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks);
 
 struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk);
 
-- 
1.8.1.5

Re: [PATCH 07/31] clk: tegra: implement a reset driver

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1711 bytes --]

On Fri, Nov 15, 2013 at 01:54:02PM -0700, Stephen Warren wrote:
[...]
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
[...]
> -	clks = tegra_clk_init(TEGRA124_CLK_CLK_MAX, 6);
> +	clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX, 6);

This doesn't really concern this patch, but this is inconsistent with
the drivers for other generations. We should probably make that
consistent in a separate patch.

> diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c

> +static int tegra_clk_rst_assert(struct reset_controller_dev *rcdev,
> +		unsigned long id);
> +static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev,
> +		unsigned long id);

Can you reorder the code so that these forward-declarations can be
avoided?

>  /* Global data of Tegra CPU CAR ops */
>  static struct tegra_cpu_car_ops dummy_car_ops;
>  struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
> @@ -70,6 +77,17 @@ static struct clk **clks;
>  static int clk_num;
>  static struct clk_onecell_data clk_data;
>  
> +static struct reset_control_ops rst_ops = {
> +	.assert = tegra_clk_rst_assert,
> +	.deassert = tegra_clk_rst_deassert,
> +};
> +
> +static struct reset_controller_dev rst_ctlr = {
> +	.ops = &rst_ops,
> +	.owner = THIS_MODULE,
> +	.of_reset_n_cells = 1,
> +};

It looks like these can be moved further down (below the implementation
of tegra_clk_rst_assert() and tegra_clk_rst_deassert()). I rather like
not having to modify two locations when the signature changes, but it's
not that big a deal, so with or without that fixed up:

Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]

[PATCH 07/31] clk: tegra: implement a reset driver

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:54:02PM -0700, Stephen Warren wrote:
[...]
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
[...]
> -	clks = tegra_clk_init(TEGRA124_CLK_CLK_MAX, 6);
> +	clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX, 6);

This doesn't really concern this patch, but this is inconsistent with
the drivers for other generations. We should probably make that
consistent in a separate patch.

> diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c

> +static int tegra_clk_rst_assert(struct reset_controller_dev *rcdev,
> +		unsigned long id);
> +static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev,
> +		unsigned long id);

Can you reorder the code so that these forward-declarations can be
avoided?

>  /* Global data of Tegra CPU CAR ops */
>  static struct tegra_cpu_car_ops dummy_car_ops;
>  struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
> @@ -70,6 +77,17 @@ static struct clk **clks;
>  static int clk_num;
>  static struct clk_onecell_data clk_data;
>  
> +static struct reset_control_ops rst_ops = {
> +	.assert = tegra_clk_rst_assert,
> +	.deassert = tegra_clk_rst_deassert,
> +};
> +
> +static struct reset_controller_dev rst_ctlr = {
> +	.ops = &rst_ops,
> +	.owner = THIS_MODULE,
> +	.of_reset_n_cells = 1,
> +};

It looks like these can be moved further down (below the implementation
of tegra_clk_rst_assert() and tegra_clk_rst_deassert()). I rather like
not having to modify two locations when the signature changes, but it's
not that big a deal, so with or without that fixed up:

Reviewed-by: Thierry Reding <treding@nvidia.com>
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Re: [PATCH 07/31] clk: tegra: implement a reset driver

[Stephen Warren]

On 11/29/2013 06:26 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:54:02PM -0700, Stephen Warren wrote: 
> [...]
>> diff --git a/drivers/clk/tegra/clk-tegra114.c
>> b/drivers/clk/tegra/clk-tegra114.c
> [...]
>> -	clks = tegra_clk_init(TEGRA124_CLK_CLK_MAX, 6); +	clks =
>> tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX, 6);
> 
> This doesn't really concern this patch, but this is inconsistent
> with the drivers for other generations. We should probably make
> that consistent in a separate patch.
> 
>> diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
> 
>> +static int tegra_clk_rst_assert(struct reset_controller_dev
>> *rcdev, +		unsigned long id); +static int
>> tegra_clk_rst_deassert(struct reset_controller_dev *rcdev, +
>> unsigned long id);
> 
> Can you reorder the code so that these forward-declarations can be 
> avoided?
> 
>> /* Global data of Tegra CPU CAR ops */ static struct
>> tegra_cpu_car_ops dummy_car_ops; struct tegra_cpu_car_ops
>> *tegra_cpu_car_ops = &dummy_car_ops; @@ -70,6 +77,17 @@ static
>> struct clk **clks; static int clk_num; static struct
>> clk_onecell_data clk_data;
>> 
>> +static struct reset_control_ops rst_ops = { +	.assert =
>> tegra_clk_rst_assert, +	.deassert = tegra_clk_rst_deassert, +}; 
>> + +static struct reset_controller_dev rst_ctlr = { +	.ops =
>> &rst_ops, +	.owner = THIS_MODULE, +	.of_reset_n_cells = 1, +};
> 
> It looks like these can be moved further down (below the
> implementation of tegra_clk_rst_assert() and
> tegra_clk_rst_deassert()). I rather like not having to modify two
> locations when the signature changes, but it's not that big a deal,
> so with or without that fixed up:
> 
> Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

OK, I moved the structs right before the function that uses them,
removed the function prototypes, and maintained your tag. Thanks.

[PATCH 07/31] clk: tegra: implement a reset driver

[Stephen Warren]

On 11/29/2013 06:26 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:54:02PM -0700, Stephen Warren wrote: 
> [...]
>> diff --git a/drivers/clk/tegra/clk-tegra114.c
>> b/drivers/clk/tegra/clk-tegra114.c
> [...]
>> -	clks = tegra_clk_init(TEGRA124_CLK_CLK_MAX, 6); +	clks =
>> tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX, 6);
> 
> This doesn't really concern this patch, but this is inconsistent
> with the drivers for other generations. We should probably make
> that consistent in a separate patch.
> 
>> diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
> 
>> +static int tegra_clk_rst_assert(struct reset_controller_dev
>> *rcdev, +		unsigned long id); +static int
>> tegra_clk_rst_deassert(struct reset_controller_dev *rcdev, +
>> unsigned long id);
> 
> Can you reorder the code so that these forward-declarations can be 
> avoided?
> 
>> /* Global data of Tegra CPU CAR ops */ static struct
>> tegra_cpu_car_ops dummy_car_ops; struct tegra_cpu_car_ops
>> *tegra_cpu_car_ops = &dummy_car_ops; @@ -70,6 +77,17 @@ static
>> struct clk **clks; static int clk_num; static struct
>> clk_onecell_data clk_data;
>> 
>> +static struct reset_control_ops rst_ops = { +	.assert =
>> tegra_clk_rst_assert, +	.deassert = tegra_clk_rst_deassert, +}; 
>> + +static struct reset_controller_dev rst_ctlr = { +	.ops =
>> &rst_ops, +	.owner = THIS_MODULE, +	.of_reset_n_cells = 1, +};
> 
> It looks like these can be moved further down (below the
> implementation of tegra_clk_rst_assert() and
> tegra_clk_rst_deassert()). I rather like not having to modify two
> locations when the signature changes, but it's not that big a deal,
> so with or without that fixed up:
> 
> Reviewed-by: Thierry Reding <treding@nvidia.com>

OK, I moved the structs right before the function that uses them,
removed the function prototypes, and maintained your tag. Thanks.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

dma_request_slave_channel() simply returns NULL whenever DMA channel
lookup fails. Lookup could fail for two distinct reasons:

a) No DMA specification exists for the channel name.
   This includes situations where no DMA specifications exist at all, or
   other general lookup problems.

b) A DMA specification does exist, yet the driver for that channel is not
   yet registered.

Case (b) should trigger deferred probe in client drivers. However, since
they have no way to differentiate the two situations, it cannot.

Implement new function dma_request_slave_channel_or_err(), which performs
identically to dma_request_slave_channel(), except that it returns an
error-pointer rather than NULL, which allows callers to detect when
deferred probe should occur.

Eventually, all drivers should be converted to this new API, the old API
removed, and the new API renamed to the more desirable name. This patch
doesn't convert the existing API and all drivers in one go, since some
drivers call dma_request_slave_channel() then dma_request_channel() if
that fails. That would require modifying dma_request_channel() in the
same way, which would then require modifying close to 100 drivers at once,
rather than just the 15-20 or so that use dma_request_slave_channel(),
which might be tenable in a single patch.

acpi_dma_request_slave_chan_by_index() doesn't actually implement
deferred probe. Perhaps it should?

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Dan Williams <dan.j.williams-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/dma/acpi-dma.c    | 12 ++++++------
 drivers/dma/dmaengine.c   | 44 ++++++++++++++++++++++++++++++++++++++++----
 drivers/dma/of-dma.c      | 12 +++++++-----
 include/linux/dmaengine.h |  7 +++++++
 include/linux/of_dma.h    |  9 ++++++---
 5 files changed, 66 insertions(+), 18 deletions(-)

diff --git a/drivers/dma/acpi-dma.c b/drivers/dma/acpi-dma.c
index e69b03c0fa50..c83d40f14467 100644
--- a/drivers/dma/acpi-dma.c
+++ b/drivers/dma/acpi-dma.c
@@ -334,7 +334,7 @@ static int acpi_dma_parse_fixed_dma(struct acpi_resource *res, void *data)
  * @dev:	struct device to get DMA request from
  * @index:	index of FixedDMA descriptor for @dev
  *
- * Returns pointer to appropriate dma channel on success or NULL on error.
+ * Returns pointer to appropriate dma channel on success or an error pointer.
  */
 struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
 		size_t index)
@@ -349,10 +349,10 @@ struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
 
 	/* Check if the device was enumerated by ACPI */
 	if (!dev || !ACPI_HANDLE(dev))
-		return NULL;
+		return ERR_PTR(-ENODEV);
 
 	if (acpi_bus_get_device(ACPI_HANDLE(dev), &adev))
-		return NULL;
+		return ERR_PTR(-ENODEV);
 
 	memset(&pdata, 0, sizeof(pdata));
 	pdata.index = index;
@@ -367,7 +367,7 @@ struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
 	acpi_dev_free_resource_list(&resource_list);
 
 	if (dma_spec->slave_id < 0 || dma_spec->chan_id < 0)
-		return NULL;
+		return ERR_PTR(-ENODEV);
 
 	mutex_lock(&acpi_dma_lock);
 
@@ -403,7 +403,7 @@ EXPORT_SYMBOL_GPL(acpi_dma_request_slave_chan_by_index);
  * translate the names "tx" and "rx" here based on the most common case where
  * the first FixedDMA descriptor is TX and second is RX.
  *
- * Returns pointer to appropriate dma channel on success or NULL on error.
+ * Returns pointer to appropriate dma channel on success or an error pointer.
  */
 struct dma_chan *acpi_dma_request_slave_chan_by_name(struct device *dev,
 		const char *name)
@@ -415,7 +415,7 @@ struct dma_chan *acpi_dma_request_slave_chan_by_name(struct device *dev,
 	else if (!strcmp(name, "rx"))
 		index = 1;
 	else
-		return NULL;
+		return ERR_PTR(-ENODEV);
 
 	return acpi_dma_request_slave_chan_by_index(dev, index);
 }
diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
index ea806bdc12ef..5e7f8af2f0ec 100644
--- a/drivers/dma/dmaengine.c
+++ b/drivers/dma/dmaengine.c
@@ -540,6 +540,8 @@ EXPORT_SYMBOL_GPL(dma_get_slave_channel);
  * @mask: capabilities that the channel must satisfy
  * @fn: optional callback to disposition available channels
  * @fn_param: opaque parameter to pass to dma_filter_fn
+ *
+ * Returns pointer to appropriate dma channel on success or NULL.
  */
 struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
 				       dma_filter_fn fn, void *fn_param)
@@ -588,24 +590,58 @@ struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
 EXPORT_SYMBOL_GPL(__dma_request_channel);
 
 /**
- * dma_request_slave_channel - try to allocate an exclusive slave channel
+ * __dma_request_slave_channel - try to allocate an exclusive slave
+ *   channel
  * @dev:	pointer to client device structure
  * @name:	slave channel name
+ *
+ * Returns pointer to appropriate dma channel on success or an error pointer.
  */
-struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name)
+static struct dma_chan *__dma_request_slave_channel(struct device *dev,
+					const char *name, bool defer)
 {
 	/* If device-tree is present get slave info from here */
 	if (dev->of_node)
-		return of_dma_request_slave_channel(dev->of_node, name);
+		return of_dma_request_slave_channel(dev->of_node, name, defer);
 
 	/* If device was enumerated by ACPI get slave info from here */
 	if (ACPI_HANDLE(dev))
 		return acpi_dma_request_slave_chan_by_name(dev, name);
 
-	return NULL;
+	return ERR_PTR(-ENODEV);
+}
+
+/**
+ * dma_request_slave_channel - try to allocate an exclusive slave channel
+ * @dev:	pointer to client device structure
+ * @name:	slave channel name
+ *
+ * Returns pointer to appropriate dma channel on success or NULL.
+ */
+struct dma_chan *dma_request_slave_channel(struct device *dev,
+					   const char *name)
+{
+	struct dma_chan *ch = __dma_request_slave_channel(dev, name, false);
+	if (IS_ERR(ch))
+		return NULL;
+	return ch;
 }
 EXPORT_SYMBOL_GPL(dma_request_slave_channel);
 
+/**
+ * dma_request_slave_channel_or_err - try to allocate an exclusive slave channel
+ * @dev:	pointer to client device structure
+ * @name:	slave channel name
+ *
+ * Returns pointer to appropriate dma channel on success or an error pointer.
+ */
+struct dma_chan *dma_request_slave_channel_or_err(struct device *dev,
+						  const char *name)
+{
+	return __dma_request_slave_channel(dev, name, true);
+}
+EXPORT_SYMBOL_GPL(dma_request_slave_channel_or_err);
+
 void dma_release_channel(struct dma_chan *chan)
 {
 	mutex_lock(&dma_list_mutex);
diff --git a/drivers/dma/of-dma.c b/drivers/dma/of-dma.c
index 0b88dd3d05f4..928141f6f21b 100644
--- a/drivers/dma/of-dma.c
+++ b/drivers/dma/of-dma.c
@@ -143,10 +143,10 @@ static int of_dma_match_channel(struct device_node *np, const char *name,
  * @np:		device node to get DMA request from
  * @name:	name of desired channel
  *
- * Returns pointer to appropriate dma channel on success or NULL on error.
+ * Returns pointer to appropriate dma channel on success or an error pointer.
  */
 struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
-					      const char *name)
+					      const char *name, bool defer)
 {
 	struct of_phandle_args	dma_spec;
 	struct of_dma		*ofdma;
@@ -155,14 +155,14 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
 
 	if (!np || !name) {
 		pr_err("%s: not enough information provided\n", __func__);
-		return NULL;
+		return ERR_PTR(-ENODEV);
 	}
 
 	count = of_property_count_strings(np, "dma-names");
 	if (count < 0) {
 		pr_err("%s: dma-names property of node '%s' missing or empty\n",
 			__func__, np->full_name);
-		return NULL;
+		return ERR_PTR(-ENODEV);
 	}
 
 	for (i = 0; i < count; i++) {
@@ -181,11 +181,13 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
 
 		of_node_put(dma_spec.np);
 
+		if (!ofdma && defer)
+			return ERR_PTR(-EPROBE_DEFER);
 		if (chan)
 			return chan;
 	}
 
-	return NULL;
+	return ERR_PTR(-ENODEV);
 }
 
 /**
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 41cf0c399288..b908b0fda72b 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -1041,6 +1041,8 @@ void dma_issue_pending_all(void);
 struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
 					dma_filter_fn fn, void *fn_param);
 struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
+struct dma_chan *dma_request_slave_channel_or_err(struct device *dev,
+						  const char *name);
 void dma_release_channel(struct dma_chan *chan);
 #else
 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
@@ -1068,6 +1070,11 @@ static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
 {
 	return NULL;
 }
+static inline struct dma_chan *dma_request_slave_channel_or_err(
+					struct device *dev, const char *name)
+{
+	return ERR_PTR(-ENODEV);
+}
 static inline void dma_release_channel(struct dma_chan *chan)
 {
 }
diff --git a/include/linux/of_dma.h b/include/linux/of_dma.h
index ae36298ba076..0504461574c6 100644
--- a/include/linux/of_dma.h
+++ b/include/linux/of_dma.h
@@ -38,7 +38,8 @@ extern int of_dma_controller_register(struct device_node *np,
 		void *data);
 extern void of_dma_controller_free(struct device_node *np);
 extern struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
-						     const char *name);
+						     const char *name,
+						     bool defer);
 extern struct dma_chan *of_dma_simple_xlate(struct of_phandle_args *dma_spec,
 		struct of_dma *ofdma);
 #else
@@ -54,8 +55,10 @@ static inline void of_dma_controller_free(struct device_node *np)
 {
 }
 
-static inline struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
-						     const char *name)
+static inline struct dma_chan *of_dma_request_slave_channel(
+					struct device_node *np,
+					const char *name,
+					bool defer)
 {
 	return NULL;
 }
-- 
1.8.1.5

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

dma_request_slave_channel() simply returns NULL whenever DMA channel
lookup fails. Lookup could fail for two distinct reasons:

a) No DMA specification exists for the channel name.
   This includes situations where no DMA specifications exist at all, or
   other general lookup problems.

b) A DMA specification does exist, yet the driver for that channel is not
   yet registered.

Case (b) should trigger deferred probe in client drivers. However, since
they have no way to differentiate the two situations, it cannot.

Implement new function dma_request_slave_channel_or_err(), which performs
identically to dma_request_slave_channel(), except that it returns an
error-pointer rather than NULL, which allows callers to detect when
deferred probe should occur.

Eventually, all drivers should be converted to this new API, the old API
removed, and the new API renamed to the more desirable name. This patch
doesn't convert the existing API and all drivers in one go, since some
drivers call dma_request_slave_channel() then dma_request_channel() if
that fails. That would require modifying dma_request_channel() in the
same way, which would then require modifying close to 100 drivers at once,
rather than just the 15-20 or so that use dma_request_slave_channel(),
which might be tenable in a single patch.

acpi_dma_request_slave_chan_by_index() doesn't actually implement
deferred probe. Perhaps it should?

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/dma/acpi-dma.c    | 12 ++++++------
 drivers/dma/dmaengine.c   | 44 ++++++++++++++++++++++++++++++++++++++++----
 drivers/dma/of-dma.c      | 12 +++++++-----
 include/linux/dmaengine.h |  7 +++++++
 include/linux/of_dma.h    |  9 ++++++---
 5 files changed, 66 insertions(+), 18 deletions(-)

diff --git a/drivers/dma/acpi-dma.c b/drivers/dma/acpi-dma.c
index e69b03c0fa50..c83d40f14467 100644
--- a/drivers/dma/acpi-dma.c
+++ b/drivers/dma/acpi-dma.c
@@ -334,7 +334,7 @@ static int acpi_dma_parse_fixed_dma(struct acpi_resource *res, void *data)
  * @dev:	struct device to get DMA request from
  * @index:	index of FixedDMA descriptor for @dev
  *
- * Returns pointer to appropriate dma channel on success or NULL on error.
+ * Returns pointer to appropriate dma channel on success or an error pointer.
  */
 struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
 		size_t index)
@@ -349,10 +349,10 @@ struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
 
 	/* Check if the device was enumerated by ACPI */
 	if (!dev || !ACPI_HANDLE(dev))
-		return NULL;
+		return ERR_PTR(-ENODEV);
 
 	if (acpi_bus_get_device(ACPI_HANDLE(dev), &adev))
-		return NULL;
+		return ERR_PTR(-ENODEV);
 
 	memset(&pdata, 0, sizeof(pdata));
 	pdata.index = index;
@@ -367,7 +367,7 @@ struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
 	acpi_dev_free_resource_list(&resource_list);
 
 	if (dma_spec->slave_id < 0 || dma_spec->chan_id < 0)
-		return NULL;
+		return ERR_PTR(-ENODEV);
 
 	mutex_lock(&acpi_dma_lock);
 
@@ -403,7 +403,7 @@ EXPORT_SYMBOL_GPL(acpi_dma_request_slave_chan_by_index);
  * translate the names "tx" and "rx" here based on the most common case where
  * the first FixedDMA descriptor is TX and second is RX.
  *
- * Returns pointer to appropriate dma channel on success or NULL on error.
+ * Returns pointer to appropriate dma channel on success or an error pointer.
  */
 struct dma_chan *acpi_dma_request_slave_chan_by_name(struct device *dev,
 		const char *name)
@@ -415,7 +415,7 @@ struct dma_chan *acpi_dma_request_slave_chan_by_name(struct device *dev,
 	else if (!strcmp(name, "rx"))
 		index = 1;
 	else
-		return NULL;
+		return ERR_PTR(-ENODEV);
 
 	return acpi_dma_request_slave_chan_by_index(dev, index);
 }
diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
index ea806bdc12ef..5e7f8af2f0ec 100644
--- a/drivers/dma/dmaengine.c
+++ b/drivers/dma/dmaengine.c
@@ -540,6 +540,8 @@ EXPORT_SYMBOL_GPL(dma_get_slave_channel);
  * @mask: capabilities that the channel must satisfy
  * @fn: optional callback to disposition available channels
  * @fn_param: opaque parameter to pass to dma_filter_fn
+ *
+ * Returns pointer to appropriate dma channel on success or NULL.
  */
 struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
 				       dma_filter_fn fn, void *fn_param)
@@ -588,24 +590,58 @@ struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
 EXPORT_SYMBOL_GPL(__dma_request_channel);
 
 /**
- * dma_request_slave_channel - try to allocate an exclusive slave channel
+ * __dma_request_slave_channel - try to allocate an exclusive slave
+ *   channel
  * @dev:	pointer to client device structure
  * @name:	slave channel name
+ *
+ * Returns pointer to appropriate dma channel on success or an error pointer.
  */
-struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name)
+static struct dma_chan *__dma_request_slave_channel(struct device *dev,
+					const char *name, bool defer)
 {
 	/* If device-tree is present get slave info from here */
 	if (dev->of_node)
-		return of_dma_request_slave_channel(dev->of_node, name);
+		return of_dma_request_slave_channel(dev->of_node, name, defer);
 
 	/* If device was enumerated by ACPI get slave info from here */
 	if (ACPI_HANDLE(dev))
 		return acpi_dma_request_slave_chan_by_name(dev, name);
 
-	return NULL;
+	return ERR_PTR(-ENODEV);
+}
+
+/**
+ * dma_request_slave_channel - try to allocate an exclusive slave channel
+ * @dev:	pointer to client device structure
+ * @name:	slave channel name
+ *
+ * Returns pointer to appropriate dma channel on success or NULL.
+ */
+struct dma_chan *dma_request_slave_channel(struct device *dev,
+					   const char *name)
+{
+	struct dma_chan *ch = __dma_request_slave_channel(dev, name, false);
+	if (IS_ERR(ch))
+		return NULL;
+	return ch;
 }
 EXPORT_SYMBOL_GPL(dma_request_slave_channel);
 
+/**
+ * dma_request_slave_channel_or_err - try to allocate an exclusive slave channel
+ * @dev:	pointer to client device structure
+ * @name:	slave channel name
+ *
+ * Returns pointer to appropriate dma channel on success or an error pointer.
+ */
+struct dma_chan *dma_request_slave_channel_or_err(struct device *dev,
+						  const char *name)
+{
+	return __dma_request_slave_channel(dev, name, true);
+}
+EXPORT_SYMBOL_GPL(dma_request_slave_channel_or_err);
+
 void dma_release_channel(struct dma_chan *chan)
 {
 	mutex_lock(&dma_list_mutex);
diff --git a/drivers/dma/of-dma.c b/drivers/dma/of-dma.c
index 0b88dd3d05f4..928141f6f21b 100644
--- a/drivers/dma/of-dma.c
+++ b/drivers/dma/of-dma.c
@@ -143,10 +143,10 @@ static int of_dma_match_channel(struct device_node *np, const char *name,
  * @np:		device node to get DMA request from
  * @name:	name of desired channel
  *
- * Returns pointer to appropriate dma channel on success or NULL on error.
+ * Returns pointer to appropriate dma channel on success or an error pointer.
  */
 struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
-					      const char *name)
+					      const char *name, bool defer)
 {
 	struct of_phandle_args	dma_spec;
 	struct of_dma		*ofdma;
@@ -155,14 +155,14 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
 
 	if (!np || !name) {
 		pr_err("%s: not enough information provided\n", __func__);
-		return NULL;
+		return ERR_PTR(-ENODEV);
 	}
 
 	count = of_property_count_strings(np, "dma-names");
 	if (count < 0) {
 		pr_err("%s: dma-names property of node '%s' missing or empty\n",
 			__func__, np->full_name);
-		return NULL;
+		return ERR_PTR(-ENODEV);
 	}
 
 	for (i = 0; i < count; i++) {
@@ -181,11 +181,13 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
 
 		of_node_put(dma_spec.np);
 
+		if (!ofdma && defer)
+			return ERR_PTR(-EPROBE_DEFER);
 		if (chan)
 			return chan;
 	}
 
-	return NULL;
+	return ERR_PTR(-ENODEV);
 }
 
 /**
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 41cf0c399288..b908b0fda72b 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -1041,6 +1041,8 @@ void dma_issue_pending_all(void);
 struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
 					dma_filter_fn fn, void *fn_param);
 struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
+struct dma_chan *dma_request_slave_channel_or_err(struct device *dev,
+						  const char *name);
 void dma_release_channel(struct dma_chan *chan);
 #else
 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
@@ -1068,6 +1070,11 @@ static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
 {
 	return NULL;
 }
+static inline struct dma_chan *dma_request_slave_channel_or_err(
+					struct device *dev, const char *name)
+{
+	return ERR_PTR(-ENODEV);
+}
 static inline void dma_release_channel(struct dma_chan *chan)
 {
 }
diff --git a/include/linux/of_dma.h b/include/linux/of_dma.h
index ae36298ba076..0504461574c6 100644
--- a/include/linux/of_dma.h
+++ b/include/linux/of_dma.h
@@ -38,7 +38,8 @@ extern int of_dma_controller_register(struct device_node *np,
 		void *data);
 extern void of_dma_controller_free(struct device_node *np);
 extern struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
-						     const char *name);
+						     const char *name,
+						     bool defer);
 extern struct dma_chan *of_dma_simple_xlate(struct of_phandle_args *dma_spec,
 		struct of_dma *ofdma);
 #else
@@ -54,8 +55,10 @@ static inline void of_dma_controller_free(struct device_node *np)
 {
 }
 
-static inline struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
-						     const char *name)
+static inline struct dma_chan *of_dma_request_slave_channel(
+					struct device_node *np,
+					const char *name,
+					bool defer)
 {
 	return NULL;
 }
-- 
1.8.1.5

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

[ adding dmaengine list and Vinod ]

On Fri, Nov 15, 2013 at 12:54 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> dma_request_slave_channel() simply returns NULL whenever DMA channel
> lookup fails. Lookup could fail for two distinct reasons:
>
> a) No DMA specification exists for the channel name.
>    This includes situations where no DMA specifications exist at all, or
>    other general lookup problems.
>
> b) A DMA specification does exist, yet the driver for that channel is not
>    yet registered.
>
> Case (b) should trigger deferred probe in client drivers. However, since
> they have no way to differentiate the two situations, it cannot.
>
> Implement new function dma_request_slave_channel_or_err(), which performs
> identically to dma_request_slave_channel(), except that it returns an
> error-pointer rather than NULL, which allows callers to detect when
> deferred probe should occur.
>
> Eventually, all drivers should be converted to this new API, the old API
> removed, and the new API renamed to the more desirable name. This patch
> doesn't convert the existing API and all drivers in one go, since some
> drivers call dma_request_slave_channel() then dma_request_channel() if
> that fails. That would require modifying dma_request_channel() in the
> same way, which would then require modifying close to 100 drivers at once,
> rather than just the 15-20 or so that use dma_request_slave_channel(),
> which might be tenable in a single patch.
>
> acpi_dma_request_slave_chan_by_index() doesn't actually implement
> deferred probe. Perhaps it should?
>
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Dan Williams <dan.j.williams-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/dma/acpi-dma.c    | 12 ++++++------
>  drivers/dma/dmaengine.c   | 44 ++++++++++++++++++++++++++++++++++++++++----
>  drivers/dma/of-dma.c      | 12 +++++++-----
>  include/linux/dmaengine.h |  7 +++++++
>  include/linux/of_dma.h    |  9 ++++++---
>  5 files changed, 66 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/dma/acpi-dma.c b/drivers/dma/acpi-dma.c
> index e69b03c0fa50..c83d40f14467 100644
> --- a/drivers/dma/acpi-dma.c
> +++ b/drivers/dma/acpi-dma.c
> @@ -334,7 +334,7 @@ static int acpi_dma_parse_fixed_dma(struct acpi_resource *res, void *data)
>   * @dev:       struct device to get DMA request from
>   * @index:     index of FixedDMA descriptor for @dev
>   *
> - * Returns pointer to appropriate dma channel on success or NULL on error.
> + * Returns pointer to appropriate dma channel on success or an error pointer.
>   */
>  struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
>                 size_t index)
> @@ -349,10 +349,10 @@ struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
>
>         /* Check if the device was enumerated by ACPI */
>         if (!dev || !ACPI_HANDLE(dev))
> -               return NULL;
> +               return ERR_PTR(-ENODEV);
>
>         if (acpi_bus_get_device(ACPI_HANDLE(dev), &adev))
> -               return NULL;
> +               return ERR_PTR(-ENODEV);
>
>         memset(&pdata, 0, sizeof(pdata));
>         pdata.index = index;
> @@ -367,7 +367,7 @@ struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
>         acpi_dev_free_resource_list(&resource_list);
>
>         if (dma_spec->slave_id < 0 || dma_spec->chan_id < 0)
> -               return NULL;
> +               return ERR_PTR(-ENODEV);
>
>         mutex_lock(&acpi_dma_lock);
>
> @@ -403,7 +403,7 @@ EXPORT_SYMBOL_GPL(acpi_dma_request_slave_chan_by_index);
>   * translate the names "tx" and "rx" here based on the most common case where
>   * the first FixedDMA descriptor is TX and second is RX.
>   *
> - * Returns pointer to appropriate dma channel on success or NULL on error.
> + * Returns pointer to appropriate dma channel on success or an error pointer.
>   */
>  struct dma_chan *acpi_dma_request_slave_chan_by_name(struct device *dev,
>                 const char *name)
> @@ -415,7 +415,7 @@ struct dma_chan *acpi_dma_request_slave_chan_by_name(struct device *dev,
>         else if (!strcmp(name, "rx"))
>                 index = 1;
>         else
> -               return NULL;
> +               return ERR_PTR(-ENODEV);
>
>         return acpi_dma_request_slave_chan_by_index(dev, index);
>  }
> diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
> index ea806bdc12ef..5e7f8af2f0ec 100644
> --- a/drivers/dma/dmaengine.c
> +++ b/drivers/dma/dmaengine.c
> @@ -540,6 +540,8 @@ EXPORT_SYMBOL_GPL(dma_get_slave_channel);
>   * @mask: capabilities that the channel must satisfy
>   * @fn: optional callback to disposition available channels
>   * @fn_param: opaque parameter to pass to dma_filter_fn
> + *
> + * Returns pointer to appropriate dma channel on success or NULL.
>   */
>  struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
>                                        dma_filter_fn fn, void *fn_param)
> @@ -588,24 +590,58 @@ struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
>  EXPORT_SYMBOL_GPL(__dma_request_channel);
>
>  /**
> - * dma_request_slave_channel - try to allocate an exclusive slave channel
> + * __dma_request_slave_channel - try to allocate an exclusive slave
> + *   channel
>   * @dev:       pointer to client device structure
>   * @name:      slave channel name
> + *
> + * Returns pointer to appropriate dma channel on success or an error pointer.
>   */
> -struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name)
> +static struct dma_chan *__dma_request_slave_channel(struct device *dev,
> +                                       const char *name, bool defer)
>  {
>         /* If device-tree is present get slave info from here */
>         if (dev->of_node)
> -               return of_dma_request_slave_channel(dev->of_node, name);
> +               return of_dma_request_slave_channel(dev->of_node, name, defer);
>
>         /* If device was enumerated by ACPI get slave info from here */
>         if (ACPI_HANDLE(dev))
>                 return acpi_dma_request_slave_chan_by_name(dev, name);
>
> -       return NULL;
> +       return ERR_PTR(-ENODEV);
> +}
> +
> +/**
> + * dma_request_slave_channel - try to allocate an exclusive slave channel
> + * @dev:       pointer to client device structure
> + * @name:      slave channel name
> + *
> + * Returns pointer to appropriate dma channel on success or NULL.
> + */
> +struct dma_chan *dma_request_slave_channel(struct device *dev,
> +                                          const char *name)
> +{
> +       struct dma_chan *ch = __dma_request_slave_channel(dev, name, false);
> +       if (IS_ERR(ch))
> +               return NULL;
> +       return ch;
>  }
>  EXPORT_SYMBOL_GPL(dma_request_slave_channel);
>
> +/**
> + * dma_request_slave_channel_or_err - try to allocate an exclusive slave channel
> + * @dev:       pointer to client device structure
> + * @name:      slave channel name
> + *
> + * Returns pointer to appropriate dma channel on success or an error pointer.
> + */
> +struct dma_chan *dma_request_slave_channel_or_err(struct device *dev,
> +                                                 const char *name)
> +{
> +       return __dma_request_slave_channel(dev, name, true);
> +}
> +EXPORT_SYMBOL_GPL(dma_request_slave_channel_or_err);
> +
>  void dma_release_channel(struct dma_chan *chan)
>  {
>         mutex_lock(&dma_list_mutex);
> diff --git a/drivers/dma/of-dma.c b/drivers/dma/of-dma.c
> index 0b88dd3d05f4..928141f6f21b 100644
> --- a/drivers/dma/of-dma.c
> +++ b/drivers/dma/of-dma.c
> @@ -143,10 +143,10 @@ static int of_dma_match_channel(struct device_node *np, const char *name,
>   * @np:                device node to get DMA request from
>   * @name:      name of desired channel
>   *
> - * Returns pointer to appropriate dma channel on success or NULL on error.
> + * Returns pointer to appropriate dma channel on success or an error pointer.
>   */
>  struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
> -                                             const char *name)
> +                                             const char *name, bool defer)
>  {
>         struct of_phandle_args  dma_spec;
>         struct of_dma           *ofdma;
> @@ -155,14 +155,14 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
>
>         if (!np || !name) {
>                 pr_err("%s: not enough information provided\n", __func__);
> -               return NULL;
> +               return ERR_PTR(-ENODEV);
>         }
>
>         count = of_property_count_strings(np, "dma-names");
>         if (count < 0) {
>                 pr_err("%s: dma-names property of node '%s' missing or empty\n",
>                         __func__, np->full_name);
> -               return NULL;
> +               return ERR_PTR(-ENODEV);
>         }
>
>         for (i = 0; i < count; i++) {
> @@ -181,11 +181,13 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
>
>                 of_node_put(dma_spec.np);
>
> +               if (!ofdma && defer)
> +                       return ERR_PTR(-EPROBE_DEFER);
>                 if (chan)
>                         return chan;
>         }
>
> -       return NULL;
> +       return ERR_PTR(-ENODEV);
>  }
>
>  /**
> diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
> index 41cf0c399288..b908b0fda72b 100644
> --- a/include/linux/dmaengine.h
> +++ b/include/linux/dmaengine.h
> @@ -1041,6 +1041,8 @@ void dma_issue_pending_all(void);
>  struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
>                                         dma_filter_fn fn, void *fn_param);
>  struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
> +struct dma_chan *dma_request_slave_channel_or_err(struct device *dev,
> +                                                 const char *name);
>  void dma_release_channel(struct dma_chan *chan);
>  #else
>  static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
> @@ -1068,6 +1070,11 @@ static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
>  {
>         return NULL;
>  }
> +static inline struct dma_chan *dma_request_slave_channel_or_err(
> +                                       struct device *dev, const char *name)
> +{
> +       return ERR_PTR(-ENODEV);
> +}
>  static inline void dma_release_channel(struct dma_chan *chan)
>  {
>  }
> diff --git a/include/linux/of_dma.h b/include/linux/of_dma.h
> index ae36298ba076..0504461574c6 100644
> --- a/include/linux/of_dma.h
> +++ b/include/linux/of_dma.h
> @@ -38,7 +38,8 @@ extern int of_dma_controller_register(struct device_node *np,
>                 void *data);
>  extern void of_dma_controller_free(struct device_node *np);
>  extern struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
> -                                                    const char *name);
> +                                                    const char *name,
> +                                                    bool defer);
>  extern struct dma_chan *of_dma_simple_xlate(struct of_phandle_args *dma_spec,
>                 struct of_dma *ofdma);
>  #else
> @@ -54,8 +55,10 @@ static inline void of_dma_controller_free(struct device_node *np)
>  {
>  }
>
> -static inline struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
> -                                                    const char *name)
> +static inline struct dma_chan *of_dma_request_slave_channel(
> +                                       struct device_node *np,
> +                                       const char *name,
> +                                       bool defer)
>  {
>         return NULL;
>  }
> --
> 1.8.1.5
>

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

[ adding dmaengine list and Vinod ]

On Fri, Nov 15, 2013 at 12:54 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> dma_request_slave_channel() simply returns NULL whenever DMA channel
> lookup fails. Lookup could fail for two distinct reasons:
>
> a) No DMA specification exists for the channel name.
>    This includes situations where no DMA specifications exist at all, or
>    other general lookup problems.
>
> b) A DMA specification does exist, yet the driver for that channel is not
>    yet registered.
>
> Case (b) should trigger deferred probe in client drivers. However, since
> they have no way to differentiate the two situations, it cannot.
>
> Implement new function dma_request_slave_channel_or_err(), which performs
> identically to dma_request_slave_channel(), except that it returns an
> error-pointer rather than NULL, which allows callers to detect when
> deferred probe should occur.
>
> Eventually, all drivers should be converted to this new API, the old API
> removed, and the new API renamed to the more desirable name. This patch
> doesn't convert the existing API and all drivers in one go, since some
> drivers call dma_request_slave_channel() then dma_request_channel() if
> that fails. That would require modifying dma_request_channel() in the
> same way, which would then require modifying close to 100 drivers at once,
> rather than just the 15-20 or so that use dma_request_slave_channel(),
> which might be tenable in a single patch.
>
> acpi_dma_request_slave_chan_by_index() doesn't actually implement
> deferred probe. Perhaps it should?
>
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/dma/acpi-dma.c    | 12 ++++++------
>  drivers/dma/dmaengine.c   | 44 ++++++++++++++++++++++++++++++++++++++++----
>  drivers/dma/of-dma.c      | 12 +++++++-----
>  include/linux/dmaengine.h |  7 +++++++
>  include/linux/of_dma.h    |  9 ++++++---
>  5 files changed, 66 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/dma/acpi-dma.c b/drivers/dma/acpi-dma.c
> index e69b03c0fa50..c83d40f14467 100644
> --- a/drivers/dma/acpi-dma.c
> +++ b/drivers/dma/acpi-dma.c
> @@ -334,7 +334,7 @@ static int acpi_dma_parse_fixed_dma(struct acpi_resource *res, void *data)
>   * @dev:       struct device to get DMA request from
>   * @index:     index of FixedDMA descriptor for @dev
>   *
> - * Returns pointer to appropriate dma channel on success or NULL on error.
> + * Returns pointer to appropriate dma channel on success or an error pointer.
>   */
>  struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
>                 size_t index)
> @@ -349,10 +349,10 @@ struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
>
>         /* Check if the device was enumerated by ACPI */
>         if (!dev || !ACPI_HANDLE(dev))
> -               return NULL;
> +               return ERR_PTR(-ENODEV);
>
>         if (acpi_bus_get_device(ACPI_HANDLE(dev), &adev))
> -               return NULL;
> +               return ERR_PTR(-ENODEV);
>
>         memset(&pdata, 0, sizeof(pdata));
>         pdata.index = index;
> @@ -367,7 +367,7 @@ struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
>         acpi_dev_free_resource_list(&resource_list);
>
>         if (dma_spec->slave_id < 0 || dma_spec->chan_id < 0)
> -               return NULL;
> +               return ERR_PTR(-ENODEV);
>
>         mutex_lock(&acpi_dma_lock);
>
> @@ -403,7 +403,7 @@ EXPORT_SYMBOL_GPL(acpi_dma_request_slave_chan_by_index);
>   * translate the names "tx" and "rx" here based on the most common case where
>   * the first FixedDMA descriptor is TX and second is RX.
>   *
> - * Returns pointer to appropriate dma channel on success or NULL on error.
> + * Returns pointer to appropriate dma channel on success or an error pointer.
>   */
>  struct dma_chan *acpi_dma_request_slave_chan_by_name(struct device *dev,
>                 const char *name)
> @@ -415,7 +415,7 @@ struct dma_chan *acpi_dma_request_slave_chan_by_name(struct device *dev,
>         else if (!strcmp(name, "rx"))
>                 index = 1;
>         else
> -               return NULL;
> +               return ERR_PTR(-ENODEV);
>
>         return acpi_dma_request_slave_chan_by_index(dev, index);
>  }
> diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
> index ea806bdc12ef..5e7f8af2f0ec 100644
> --- a/drivers/dma/dmaengine.c
> +++ b/drivers/dma/dmaengine.c
> @@ -540,6 +540,8 @@ EXPORT_SYMBOL_GPL(dma_get_slave_channel);
>   * @mask: capabilities that the channel must satisfy
>   * @fn: optional callback to disposition available channels
>   * @fn_param: opaque parameter to pass to dma_filter_fn
> + *
> + * Returns pointer to appropriate dma channel on success or NULL.
>   */
>  struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
>                                        dma_filter_fn fn, void *fn_param)
> @@ -588,24 +590,58 @@ struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
>  EXPORT_SYMBOL_GPL(__dma_request_channel);
>
>  /**
> - * dma_request_slave_channel - try to allocate an exclusive slave channel
> + * __dma_request_slave_channel - try to allocate an exclusive slave
> + *   channel
>   * @dev:       pointer to client device structure
>   * @name:      slave channel name
> + *
> + * Returns pointer to appropriate dma channel on success or an error pointer.
>   */
> -struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name)
> +static struct dma_chan *__dma_request_slave_channel(struct device *dev,
> +                                       const char *name, bool defer)
>  {
>         /* If device-tree is present get slave info from here */
>         if (dev->of_node)
> -               return of_dma_request_slave_channel(dev->of_node, name);
> +               return of_dma_request_slave_channel(dev->of_node, name, defer);
>
>         /* If device was enumerated by ACPI get slave info from here */
>         if (ACPI_HANDLE(dev))
>                 return acpi_dma_request_slave_chan_by_name(dev, name);
>
> -       return NULL;
> +       return ERR_PTR(-ENODEV);
> +}
> +
> +/**
> + * dma_request_slave_channel - try to allocate an exclusive slave channel
> + * @dev:       pointer to client device structure
> + * @name:      slave channel name
> + *
> + * Returns pointer to appropriate dma channel on success or NULL.
> + */
> +struct dma_chan *dma_request_slave_channel(struct device *dev,
> +                                          const char *name)
> +{
> +       struct dma_chan *ch = __dma_request_slave_channel(dev, name, false);
> +       if (IS_ERR(ch))
> +               return NULL;
> +       return ch;
>  }
>  EXPORT_SYMBOL_GPL(dma_request_slave_channel);
>
> +/**
> + * dma_request_slave_channel_or_err - try to allocate an exclusive slave channel
> + * @dev:       pointer to client device structure
> + * @name:      slave channel name
> + *
> + * Returns pointer to appropriate dma channel on success or an error pointer.
> + */
> +struct dma_chan *dma_request_slave_channel_or_err(struct device *dev,
> +                                                 const char *name)
> +{
> +       return __dma_request_slave_channel(dev, name, true);
> +}
> +EXPORT_SYMBOL_GPL(dma_request_slave_channel_or_err);
> +
>  void dma_release_channel(struct dma_chan *chan)
>  {
>         mutex_lock(&dma_list_mutex);
> diff --git a/drivers/dma/of-dma.c b/drivers/dma/of-dma.c
> index 0b88dd3d05f4..928141f6f21b 100644
> --- a/drivers/dma/of-dma.c
> +++ b/drivers/dma/of-dma.c
> @@ -143,10 +143,10 @@ static int of_dma_match_channel(struct device_node *np, const char *name,
>   * @np:                device node to get DMA request from
>   * @name:      name of desired channel
>   *
> - * Returns pointer to appropriate dma channel on success or NULL on error.
> + * Returns pointer to appropriate dma channel on success or an error pointer.
>   */
>  struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
> -                                             const char *name)
> +                                             const char *name, bool defer)
>  {
>         struct of_phandle_args  dma_spec;
>         struct of_dma           *ofdma;
> @@ -155,14 +155,14 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
>
>         if (!np || !name) {
>                 pr_err("%s: not enough information provided\n", __func__);
> -               return NULL;
> +               return ERR_PTR(-ENODEV);
>         }
>
>         count = of_property_count_strings(np, "dma-names");
>         if (count < 0) {
>                 pr_err("%s: dma-names property of node '%s' missing or empty\n",
>                         __func__, np->full_name);
> -               return NULL;
> +               return ERR_PTR(-ENODEV);
>         }
>
>         for (i = 0; i < count; i++) {
> @@ -181,11 +181,13 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
>
>                 of_node_put(dma_spec.np);
>
> +               if (!ofdma && defer)
> +                       return ERR_PTR(-EPROBE_DEFER);
>                 if (chan)
>                         return chan;
>         }
>
> -       return NULL;
> +       return ERR_PTR(-ENODEV);
>  }
>
>  /**
> diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
> index 41cf0c399288..b908b0fda72b 100644
> --- a/include/linux/dmaengine.h
> +++ b/include/linux/dmaengine.h
> @@ -1041,6 +1041,8 @@ void dma_issue_pending_all(void);
>  struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
>                                         dma_filter_fn fn, void *fn_param);
>  struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
> +struct dma_chan *dma_request_slave_channel_or_err(struct device *dev,
> +                                                 const char *name);
>  void dma_release_channel(struct dma_chan *chan);
>  #else
>  static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
> @@ -1068,6 +1070,11 @@ static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
>  {
>         return NULL;
>  }
> +static inline struct dma_chan *dma_request_slave_channel_or_err(
> +                                       struct device *dev, const char *name)
> +{
> +       return ERR_PTR(-ENODEV);
> +}
>  static inline void dma_release_channel(struct dma_chan *chan)
>  {
>  }
> diff --git a/include/linux/of_dma.h b/include/linux/of_dma.h
> index ae36298ba076..0504461574c6 100644
> --- a/include/linux/of_dma.h
> +++ b/include/linux/of_dma.h
> @@ -38,7 +38,8 @@ extern int of_dma_controller_register(struct device_node *np,
>                 void *data);
>  extern void of_dma_controller_free(struct device_node *np);
>  extern struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
> -                                                    const char *name);
> +                                                    const char *name,
> +                                                    bool defer);
>  extern struct dma_chan *of_dma_simple_xlate(struct of_phandle_args *dma_spec,
>                 struct of_dma *ofdma);
>  #else
> @@ -54,8 +55,10 @@ static inline void of_dma_controller_free(struct device_node *np)
>  {
>  }
>
> -static inline struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
> -                                                    const char *name)
> +static inline struct dma_chan *of_dma_request_slave_channel(
> +                                       struct device_node *np,
> +                                       const char *name,
> +                                       bool defer)
>  {
>         return NULL;
>  }
> --
> 1.8.1.5
>

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

[ Also adding Andy to comment on the acpi-dma.c question ]

On Fri, Nov 15, 2013 at 1:01 PM, Dan Williams <dan.j.williams-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> wrote:
> [ adding dmaengine list and Vinod ]
>
> On Fri, Nov 15, 2013 at 12:54 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
>> dma_request_slave_channel() simply returns NULL whenever DMA channel
>> lookup fails. Lookup could fail for two distinct reasons:
>>
>> a) No DMA specification exists for the channel name.
>>    This includes situations where no DMA specifications exist at all, or
>>    other general lookup problems.
>>
>> b) A DMA specification does exist, yet the driver for that channel is not
>>    yet registered.
>>
>> Case (b) should trigger deferred probe in client drivers. However, since
>> they have no way to differentiate the two situations, it cannot.
>>
>> Implement new function dma_request_slave_channel_or_err(), which performs
>> identically to dma_request_slave_channel(), except that it returns an
>> error-pointer rather than NULL, which allows callers to detect when
>> deferred probe should occur.
>>
>> Eventually, all drivers should be converted to this new API, the old API
>> removed, and the new API renamed to the more desirable name. This patch
>> doesn't convert the existing API and all drivers in one go, since some
>> drivers call dma_request_slave_channel() then dma_request_channel() if
>> that fails. That would require modifying dma_request_channel() in the
>> same way, which would then require modifying close to 100 drivers at once,
>> rather than just the 15-20 or so that use dma_request_slave_channel(),
>> which might be tenable in a single patch.
>>
>> acpi_dma_request_slave_chan_by_index() doesn't actually implement
>> deferred probe. Perhaps it should?
>>
>> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
>> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
>> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>> Cc: Dan Williams <dan.j.williams-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
>> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> ---
>> This patch is part of a series with strong internal depdendencies. I'm
>> looking for an ack so that I can take the entire series through the Tegra
>> and arm-soc trees. The series will be part of a stable branch that can be
>> merged into other subsystems if needed to avoid/resolve dependencies.
>> ---
>>  drivers/dma/acpi-dma.c    | 12 ++++++------
>>  drivers/dma/dmaengine.c   | 44 ++++++++++++++++++++++++++++++++++++++++----
>>  drivers/dma/of-dma.c      | 12 +++++++-----
>>  include/linux/dmaengine.h |  7 +++++++
>>  include/linux/of_dma.h    |  9 ++++++---
>>  5 files changed, 66 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/dma/acpi-dma.c b/drivers/dma/acpi-dma.c
>> index e69b03c0fa50..c83d40f14467 100644
>> --- a/drivers/dma/acpi-dma.c
>> +++ b/drivers/dma/acpi-dma.c
>> @@ -334,7 +334,7 @@ static int acpi_dma_parse_fixed_dma(struct acpi_resource *res, void *data)
>>   * @dev:       struct device to get DMA request from
>>   * @index:     index of FixedDMA descriptor for @dev
>>   *
>> - * Returns pointer to appropriate dma channel on success or NULL on error.
>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>>   */
>>  struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
>>                 size_t index)
>> @@ -349,10 +349,10 @@ struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
>>
>>         /* Check if the device was enumerated by ACPI */
>>         if (!dev || !ACPI_HANDLE(dev))
>> -               return NULL;
>> +               return ERR_PTR(-ENODEV);
>>
>>         if (acpi_bus_get_device(ACPI_HANDLE(dev), &adev))
>> -               return NULL;
>> +               return ERR_PTR(-ENODEV);
>>
>>         memset(&pdata, 0, sizeof(pdata));
>>         pdata.index = index;
>> @@ -367,7 +367,7 @@ struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
>>         acpi_dev_free_resource_list(&resource_list);
>>
>>         if (dma_spec->slave_id < 0 || dma_spec->chan_id < 0)
>> -               return NULL;
>> +               return ERR_PTR(-ENODEV);
>>
>>         mutex_lock(&acpi_dma_lock);
>>
>> @@ -403,7 +403,7 @@ EXPORT_SYMBOL_GPL(acpi_dma_request_slave_chan_by_index);
>>   * translate the names "tx" and "rx" here based on the most common case where
>>   * the first FixedDMA descriptor is TX and second is RX.
>>   *
>> - * Returns pointer to appropriate dma channel on success or NULL on error.
>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>>   */
>>  struct dma_chan *acpi_dma_request_slave_chan_by_name(struct device *dev,
>>                 const char *name)
>> @@ -415,7 +415,7 @@ struct dma_chan *acpi_dma_request_slave_chan_by_name(struct device *dev,
>>         else if (!strcmp(name, "rx"))
>>                 index = 1;
>>         else
>> -               return NULL;
>> +               return ERR_PTR(-ENODEV);
>>
>>         return acpi_dma_request_slave_chan_by_index(dev, index);
>>  }
>> diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
>> index ea806bdc12ef..5e7f8af2f0ec 100644
>> --- a/drivers/dma/dmaengine.c
>> +++ b/drivers/dma/dmaengine.c
>> @@ -540,6 +540,8 @@ EXPORT_SYMBOL_GPL(dma_get_slave_channel);
>>   * @mask: capabilities that the channel must satisfy
>>   * @fn: optional callback to disposition available channels
>>   * @fn_param: opaque parameter to pass to dma_filter_fn
>> + *
>> + * Returns pointer to appropriate dma channel on success or NULL.
>>   */
>>  struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
>>                                        dma_filter_fn fn, void *fn_param)
>> @@ -588,24 +590,58 @@ struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
>>  EXPORT_SYMBOL_GPL(__dma_request_channel);
>>
>>  /**
>> - * dma_request_slave_channel - try to allocate an exclusive slave channel
>> + * __dma_request_slave_channel - try to allocate an exclusive slave
>> + *   channel
>>   * @dev:       pointer to client device structure
>>   * @name:      slave channel name
>> + *
>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>>   */
>> -struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name)
>> +static struct dma_chan *__dma_request_slave_channel(struct device *dev,
>> +                                       const char *name, bool defer)
>>  {
>>         /* If device-tree is present get slave info from here */
>>         if (dev->of_node)
>> -               return of_dma_request_slave_channel(dev->of_node, name);
>> +               return of_dma_request_slave_channel(dev->of_node, name, defer);
>>
>>         /* If device was enumerated by ACPI get slave info from here */
>>         if (ACPI_HANDLE(dev))
>>                 return acpi_dma_request_slave_chan_by_name(dev, name);
>>
>> -       return NULL;
>> +       return ERR_PTR(-ENODEV);
>> +}
>> +
>> +/**
>> + * dma_request_slave_channel - try to allocate an exclusive slave channel
>> + * @dev:       pointer to client device structure
>> + * @name:      slave channel name
>> + *
>> + * Returns pointer to appropriate dma channel on success or NULL.
>> + */
>> +struct dma_chan *dma_request_slave_channel(struct device *dev,
>> +                                          const char *name)
>> +{
>> +       struct dma_chan *ch = __dma_request_slave_channel(dev, name, false);
>> +       if (IS_ERR(ch))
>> +               return NULL;
>> +       return ch;
>>  }
>>  EXPORT_SYMBOL_GPL(dma_request_slave_channel);
>>
>> +/**
>> + * dma_request_slave_channel_or_err - try to allocate an exclusive slave channel
>> + * @dev:       pointer to client device structure
>> + * @name:      slave channel name
>> + *
>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>> + */
>> +struct dma_chan *dma_request_slave_channel_or_err(struct device *dev,
>> +                                                 const char *name)
>> +{
>> +       return __dma_request_slave_channel(dev, name, true);
>> +}
>> +EXPORT_SYMBOL_GPL(dma_request_slave_channel_or_err);
>> +
>>  void dma_release_channel(struct dma_chan *chan)
>>  {
>>         mutex_lock(&dma_list_mutex);
>> diff --git a/drivers/dma/of-dma.c b/drivers/dma/of-dma.c
>> index 0b88dd3d05f4..928141f6f21b 100644
>> --- a/drivers/dma/of-dma.c
>> +++ b/drivers/dma/of-dma.c
>> @@ -143,10 +143,10 @@ static int of_dma_match_channel(struct device_node *np, const char *name,
>>   * @np:                device node to get DMA request from
>>   * @name:      name of desired channel
>>   *
>> - * Returns pointer to appropriate dma channel on success or NULL on error.
>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>>   */
>>  struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
>> -                                             const char *name)
>> +                                             const char *name, bool defer)
>>  {
>>         struct of_phandle_args  dma_spec;
>>         struct of_dma           *ofdma;
>> @@ -155,14 +155,14 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
>>
>>         if (!np || !name) {
>>                 pr_err("%s: not enough information provided\n", __func__);
>> -               return NULL;
>> +               return ERR_PTR(-ENODEV);
>>         }
>>
>>         count = of_property_count_strings(np, "dma-names");
>>         if (count < 0) {
>>                 pr_err("%s: dma-names property of node '%s' missing or empty\n",
>>                         __func__, np->full_name);
>> -               return NULL;
>> +               return ERR_PTR(-ENODEV);
>>         }
>>
>>         for (i = 0; i < count; i++) {
>> @@ -181,11 +181,13 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
>>
>>                 of_node_put(dma_spec.np);
>>
>> +               if (!ofdma && defer)
>> +                       return ERR_PTR(-EPROBE_DEFER);
>>                 if (chan)
>>                         return chan;
>>         }
>>
>> -       return NULL;
>> +       return ERR_PTR(-ENODEV);
>>  }
>>
>>  /**
>> diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
>> index 41cf0c399288..b908b0fda72b 100644
>> --- a/include/linux/dmaengine.h
>> +++ b/include/linux/dmaengine.h
>> @@ -1041,6 +1041,8 @@ void dma_issue_pending_all(void);
>>  struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
>>                                         dma_filter_fn fn, void *fn_param);
>>  struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
>> +struct dma_chan *dma_request_slave_channel_or_err(struct device *dev,
>> +                                                 const char *name);
>>  void dma_release_channel(struct dma_chan *chan);
>>  #else
>>  static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
>> @@ -1068,6 +1070,11 @@ static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
>>  {
>>         return NULL;
>>  }
>> +static inline struct dma_chan *dma_request_slave_channel_or_err(
>> +                                       struct device *dev, const char *name)
>> +{
>> +       return ERR_PTR(-ENODEV);
>> +}
>>  static inline void dma_release_channel(struct dma_chan *chan)
>>  {
>>  }
>> diff --git a/include/linux/of_dma.h b/include/linux/of_dma.h
>> index ae36298ba076..0504461574c6 100644
>> --- a/include/linux/of_dma.h
>> +++ b/include/linux/of_dma.h
>> @@ -38,7 +38,8 @@ extern int of_dma_controller_register(struct device_node *np,
>>                 void *data);
>>  extern void of_dma_controller_free(struct device_node *np);
>>  extern struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
>> -                                                    const char *name);
>> +                                                    const char *name,
>> +                                                    bool defer);
>>  extern struct dma_chan *of_dma_simple_xlate(struct of_phandle_args *dma_spec,
>>                 struct of_dma *ofdma);
>>  #else
>> @@ -54,8 +55,10 @@ static inline void of_dma_controller_free(struct device_node *np)
>>  {
>>  }
>>
>> -static inline struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
>> -                                                    const char *name)
>> +static inline struct dma_chan *of_dma_request_slave_channel(
>> +                                       struct device_node *np,
>> +                                       const char *name,
>> +                                       bool defer)
>>  {
>>         return NULL;
>>  }
>> --
>> 1.8.1.5
>>

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

[ Also adding Andy to comment on the acpi-dma.c question ]

On Fri, Nov 15, 2013 at 1:01 PM, Dan Williams <dan.j.williams@intel.com> wrote:
> [ adding dmaengine list and Vinod ]
>
> On Fri, Nov 15, 2013 at 12:54 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> From: Stephen Warren <swarren@nvidia.com>
>>
>> dma_request_slave_channel() simply returns NULL whenever DMA channel
>> lookup fails. Lookup could fail for two distinct reasons:
>>
>> a) No DMA specification exists for the channel name.
>>    This includes situations where no DMA specifications exist at all, or
>>    other general lookup problems.
>>
>> b) A DMA specification does exist, yet the driver for that channel is not
>>    yet registered.
>>
>> Case (b) should trigger deferred probe in client drivers. However, since
>> they have no way to differentiate the two situations, it cannot.
>>
>> Implement new function dma_request_slave_channel_or_err(), which performs
>> identically to dma_request_slave_channel(), except that it returns an
>> error-pointer rather than NULL, which allows callers to detect when
>> deferred probe should occur.
>>
>> Eventually, all drivers should be converted to this new API, the old API
>> removed, and the new API renamed to the more desirable name. This patch
>> doesn't convert the existing API and all drivers in one go, since some
>> drivers call dma_request_slave_channel() then dma_request_channel() if
>> that fails. That would require modifying dma_request_channel() in the
>> same way, which would then require modifying close to 100 drivers at once,
>> rather than just the 15-20 or so that use dma_request_slave_channel(),
>> which might be tenable in a single patch.
>>
>> acpi_dma_request_slave_chan_by_index() doesn't actually implement
>> deferred probe. Perhaps it should?
>>
>> Cc: treding at nvidia.com
>> Cc: pdeschrijver at nvidia.com
>> Cc: linux-tegra at vger.kernel.org
>> Cc: linux-arm-kernel at lists.infradead.org
>> Cc: Dan Williams <dan.j.williams@intel.com>
>> Signed-off-by: Stephen Warren <swarren@nvidia.com>
>> ---
>> This patch is part of a series with strong internal depdendencies. I'm
>> looking for an ack so that I can take the entire series through the Tegra
>> and arm-soc trees. The series will be part of a stable branch that can be
>> merged into other subsystems if needed to avoid/resolve dependencies.
>> ---
>>  drivers/dma/acpi-dma.c    | 12 ++++++------
>>  drivers/dma/dmaengine.c   | 44 ++++++++++++++++++++++++++++++++++++++++----
>>  drivers/dma/of-dma.c      | 12 +++++++-----
>>  include/linux/dmaengine.h |  7 +++++++
>>  include/linux/of_dma.h    |  9 ++++++---
>>  5 files changed, 66 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/dma/acpi-dma.c b/drivers/dma/acpi-dma.c
>> index e69b03c0fa50..c83d40f14467 100644
>> --- a/drivers/dma/acpi-dma.c
>> +++ b/drivers/dma/acpi-dma.c
>> @@ -334,7 +334,7 @@ static int acpi_dma_parse_fixed_dma(struct acpi_resource *res, void *data)
>>   * @dev:       struct device to get DMA request from
>>   * @index:     index of FixedDMA descriptor for @dev
>>   *
>> - * Returns pointer to appropriate dma channel on success or NULL on error.
>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>>   */
>>  struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
>>                 size_t index)
>> @@ -349,10 +349,10 @@ struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
>>
>>         /* Check if the device was enumerated by ACPI */
>>         if (!dev || !ACPI_HANDLE(dev))
>> -               return NULL;
>> +               return ERR_PTR(-ENODEV);
>>
>>         if (acpi_bus_get_device(ACPI_HANDLE(dev), &adev))
>> -               return NULL;
>> +               return ERR_PTR(-ENODEV);
>>
>>         memset(&pdata, 0, sizeof(pdata));
>>         pdata.index = index;
>> @@ -367,7 +367,7 @@ struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
>>         acpi_dev_free_resource_list(&resource_list);
>>
>>         if (dma_spec->slave_id < 0 || dma_spec->chan_id < 0)
>> -               return NULL;
>> +               return ERR_PTR(-ENODEV);
>>
>>         mutex_lock(&acpi_dma_lock);
>>
>> @@ -403,7 +403,7 @@ EXPORT_SYMBOL_GPL(acpi_dma_request_slave_chan_by_index);
>>   * translate the names "tx" and "rx" here based on the most common case where
>>   * the first FixedDMA descriptor is TX and second is RX.
>>   *
>> - * Returns pointer to appropriate dma channel on success or NULL on error.
>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>>   */
>>  struct dma_chan *acpi_dma_request_slave_chan_by_name(struct device *dev,
>>                 const char *name)
>> @@ -415,7 +415,7 @@ struct dma_chan *acpi_dma_request_slave_chan_by_name(struct device *dev,
>>         else if (!strcmp(name, "rx"))
>>                 index = 1;
>>         else
>> -               return NULL;
>> +               return ERR_PTR(-ENODEV);
>>
>>         return acpi_dma_request_slave_chan_by_index(dev, index);
>>  }
>> diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
>> index ea806bdc12ef..5e7f8af2f0ec 100644
>> --- a/drivers/dma/dmaengine.c
>> +++ b/drivers/dma/dmaengine.c
>> @@ -540,6 +540,8 @@ EXPORT_SYMBOL_GPL(dma_get_slave_channel);
>>   * @mask: capabilities that the channel must satisfy
>>   * @fn: optional callback to disposition available channels
>>   * @fn_param: opaque parameter to pass to dma_filter_fn
>> + *
>> + * Returns pointer to appropriate dma channel on success or NULL.
>>   */
>>  struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
>>                                        dma_filter_fn fn, void *fn_param)
>> @@ -588,24 +590,58 @@ struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
>>  EXPORT_SYMBOL_GPL(__dma_request_channel);
>>
>>  /**
>> - * dma_request_slave_channel - try to allocate an exclusive slave channel
>> + * __dma_request_slave_channel - try to allocate an exclusive slave
>> + *   channel
>>   * @dev:       pointer to client device structure
>>   * @name:      slave channel name
>> + *
>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>>   */
>> -struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name)
>> +static struct dma_chan *__dma_request_slave_channel(struct device *dev,
>> +                                       const char *name, bool defer)
>>  {
>>         /* If device-tree is present get slave info from here */
>>         if (dev->of_node)
>> -               return of_dma_request_slave_channel(dev->of_node, name);
>> +               return of_dma_request_slave_channel(dev->of_node, name, defer);
>>
>>         /* If device was enumerated by ACPI get slave info from here */
>>         if (ACPI_HANDLE(dev))
>>                 return acpi_dma_request_slave_chan_by_name(dev, name);
>>
>> -       return NULL;
>> +       return ERR_PTR(-ENODEV);
>> +}
>> +
>> +/**
>> + * dma_request_slave_channel - try to allocate an exclusive slave channel
>> + * @dev:       pointer to client device structure
>> + * @name:      slave channel name
>> + *
>> + * Returns pointer to appropriate dma channel on success or NULL.
>> + */
>> +struct dma_chan *dma_request_slave_channel(struct device *dev,
>> +                                          const char *name)
>> +{
>> +       struct dma_chan *ch = __dma_request_slave_channel(dev, name, false);
>> +       if (IS_ERR(ch))
>> +               return NULL;
>> +       return ch;
>>  }
>>  EXPORT_SYMBOL_GPL(dma_request_slave_channel);
>>
>> +/**
>> + * dma_request_slave_channel_or_err - try to allocate an exclusive slave channel
>> + * @dev:       pointer to client device structure
>> + * @name:      slave channel name
>> + *
>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>> + */
>> +struct dma_chan *dma_request_slave_channel_or_err(struct device *dev,
>> +                                                 const char *name)
>> +{
>> +       return __dma_request_slave_channel(dev, name, true);
>> +}
>> +EXPORT_SYMBOL_GPL(dma_request_slave_channel_or_err);
>> +
>>  void dma_release_channel(struct dma_chan *chan)
>>  {
>>         mutex_lock(&dma_list_mutex);
>> diff --git a/drivers/dma/of-dma.c b/drivers/dma/of-dma.c
>> index 0b88dd3d05f4..928141f6f21b 100644
>> --- a/drivers/dma/of-dma.c
>> +++ b/drivers/dma/of-dma.c
>> @@ -143,10 +143,10 @@ static int of_dma_match_channel(struct device_node *np, const char *name,
>>   * @np:                device node to get DMA request from
>>   * @name:      name of desired channel
>>   *
>> - * Returns pointer to appropriate dma channel on success or NULL on error.
>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>>   */
>>  struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
>> -                                             const char *name)
>> +                                             const char *name, bool defer)
>>  {
>>         struct of_phandle_args  dma_spec;
>>         struct of_dma           *ofdma;
>> @@ -155,14 +155,14 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
>>
>>         if (!np || !name) {
>>                 pr_err("%s: not enough information provided\n", __func__);
>> -               return NULL;
>> +               return ERR_PTR(-ENODEV);
>>         }
>>
>>         count = of_property_count_strings(np, "dma-names");
>>         if (count < 0) {
>>                 pr_err("%s: dma-names property of node '%s' missing or empty\n",
>>                         __func__, np->full_name);
>> -               return NULL;
>> +               return ERR_PTR(-ENODEV);
>>         }
>>
>>         for (i = 0; i < count; i++) {
>> @@ -181,11 +181,13 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
>>
>>                 of_node_put(dma_spec.np);
>>
>> +               if (!ofdma && defer)
>> +                       return ERR_PTR(-EPROBE_DEFER);
>>                 if (chan)
>>                         return chan;
>>         }
>>
>> -       return NULL;
>> +       return ERR_PTR(-ENODEV);
>>  }
>>
>>  /**
>> diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
>> index 41cf0c399288..b908b0fda72b 100644
>> --- a/include/linux/dmaengine.h
>> +++ b/include/linux/dmaengine.h
>> @@ -1041,6 +1041,8 @@ void dma_issue_pending_all(void);
>>  struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
>>                                         dma_filter_fn fn, void *fn_param);
>>  struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
>> +struct dma_chan *dma_request_slave_channel_or_err(struct device *dev,
>> +                                                 const char *name);
>>  void dma_release_channel(struct dma_chan *chan);
>>  #else
>>  static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
>> @@ -1068,6 +1070,11 @@ static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
>>  {
>>         return NULL;
>>  }
>> +static inline struct dma_chan *dma_request_slave_channel_or_err(
>> +                                       struct device *dev, const char *name)
>> +{
>> +       return ERR_PTR(-ENODEV);
>> +}
>>  static inline void dma_release_channel(struct dma_chan *chan)
>>  {
>>  }
>> diff --git a/include/linux/of_dma.h b/include/linux/of_dma.h
>> index ae36298ba076..0504461574c6 100644
>> --- a/include/linux/of_dma.h
>> +++ b/include/linux/of_dma.h
>> @@ -38,7 +38,8 @@ extern int of_dma_controller_register(struct device_node *np,
>>                 void *data);
>>  extern void of_dma_controller_free(struct device_node *np);
>>  extern struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
>> -                                                    const char *name);
>> +                                                    const char *name,
>> +                                                    bool defer);
>>  extern struct dma_chan *of_dma_simple_xlate(struct of_phandle_args *dma_spec,
>>                 struct of_dma *ofdma);
>>  #else
>> @@ -54,8 +55,10 @@ static inline void of_dma_controller_free(struct device_node *np)
>>  {
>>  }
>>
>> -static inline struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
>> -                                                    const char *name)
>> +static inline struct dma_chan *of_dma_request_slave_channel(
>> +                                       struct device_node *np,
>> +                                       const char *name,
>> +                                       bool defer)
>>  {
>>         return NULL;
>>  }
>> --
>> 1.8.1.5
>>

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Shevchenko, Andriy]

On Fri, 2013-11-15 at 13:01 -0800, Dan Williams wrote:
> On Fri, Nov 15, 2013 at 12:54 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:

> > Eventually, all drivers should be converted to this new API, the old API
> > removed, and the new API renamed to the more desirable name. 

I really would like to see more sensible and shorter names for the API
functions.

[]

> > acpi_dma_request_slave_chan_by_index() doesn't actually implement
> > deferred probe. Perhaps it should?

Yes it should, though I propose we will add this a bit later since we
will survive w/o it.

My comments regarding acpi-dma.c below.

[]

> > --- a/drivers/dma/acpi-dma.c
> > +++ b/drivers/dma/acpi-dma.c
> > @@ -334,7 +334,7 @@ static int acpi_dma_parse_fixed_dma(struct acpi_resource *res, void *data)
> >   * @dev:       struct device to get DMA request from
> >   * @index:     index of FixedDMA descriptor for @dev
> >   *
> > - * Returns pointer to appropriate dma channel on success or NULL on error.
> > + * Returns pointer to appropriate dma channel on success or an error pointer.
> >   */
> >  struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
> >                 size_t index)
> > @@ -349,10 +349,10 @@ struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,

We use default value of chan if it's not found. Perhaps you have to
change it as well to something like ERR_PTR(-ENOENT).

[]

> > @@ -367,7 +367,7 @@ struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
> >         acpi_dev_free_resource_list(&resource_list);
> >
> >         if (dma_spec->slave_id < 0 || dma_spec->chan_id < 0)
> > -               return NULL;
> > +               return ERR_PTR(-ENODEV);

In this case I would rather use -ENODATA, since it means we have no
FixedDMA descriptor for the device under question.

[]

> >  struct dma_chan *acpi_dma_request_slave_chan_by_name(struct device *dev,
> >                 const char *name)
> > @@ -415,7 +415,7 @@ struct dma_chan *acpi_dma_request_slave_chan_by_name(struct device *dev,
> >         else if (!strcmp(name, "rx"))
> >                 index = 1;
> >         else
> > -               return NULL;
> > +               return ERR_PTR(-ENODEV);

Perhaps -EINVAL, since it means the input parameter kinda wrong.


-- 
Andy Shevchenko <andriy.shevchenko@intel.com>
Intel Finland Oy
---------------------------------------------------------------------
Intel Finland Oy
Registered Address: PL 281, 00181 Helsinki 
Business Identity Code: 0357606 - 4 
Domiciled in Helsinki 

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Shevchenko, Andriy]

On Fri, 2013-11-15 at 13:01 -0800, Dan Williams wrote:
> On Fri, Nov 15, 2013 at 12:54 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:

> > Eventually, all drivers should be converted to this new API, the old API
> > removed, and the new API renamed to the more desirable name. 

I really would like to see more sensible and shorter names for the API
functions.

[]

> > acpi_dma_request_slave_chan_by_index() doesn't actually implement
> > deferred probe. Perhaps it should?

Yes it should, though I propose we will add this a bit later since we
will survive w/o it.

My comments regarding acpi-dma.c below.

[]

> > --- a/drivers/dma/acpi-dma.c
> > +++ b/drivers/dma/acpi-dma.c
> > @@ -334,7 +334,7 @@ static int acpi_dma_parse_fixed_dma(struct acpi_resource *res, void *data)
> >   * @dev:       struct device to get DMA request from
> >   * @index:     index of FixedDMA descriptor for @dev
> >   *
> > - * Returns pointer to appropriate dma channel on success or NULL on error.
> > + * Returns pointer to appropriate dma channel on success or an error pointer.
> >   */
> >  struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
> >                 size_t index)
> > @@ -349,10 +349,10 @@ struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,

We use default value of chan if it's not found. Perhaps you have to
change it as well to something like ERR_PTR(-ENOENT).

[]

> > @@ -367,7 +367,7 @@ struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
> >         acpi_dev_free_resource_list(&resource_list);
> >
> >         if (dma_spec->slave_id < 0 || dma_spec->chan_id < 0)
> > -               return NULL;
> > +               return ERR_PTR(-ENODEV);

In this case I would rather use -ENODATA, since it means we have no
FixedDMA descriptor for the device under question.

[]

> >  struct dma_chan *acpi_dma_request_slave_chan_by_name(struct device *dev,
> >                 const char *name)
> > @@ -415,7 +415,7 @@ struct dma_chan *acpi_dma_request_slave_chan_by_name(struct device *dev,
> >         else if (!strcmp(name, "rx"))
> >                 index = 1;
> >         else
> > -               return NULL;
> > +               return ERR_PTR(-ENODEV);

Perhaps -EINVAL, since it means the input parameter kinda wrong.


-- 
Andy Shevchenko <andriy.shevchenko@intel.com>
Intel Finland Oy
---------------------------------------------------------------------
Intel Finland Oy
Registered Address: PL 281, 00181 Helsinki 
Business Identity Code: 0357606 - 4 
Domiciled in Helsinki 

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/18/2013 02:18 AM, Shevchenko, Andriy wrote:
> On Fri, 2013-11-15 at 13:01 -0800, Dan Williams wrote:
>> On Fri, Nov 15, 2013 at 12:54 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> 
>>> Eventually, all drivers should be converted to this new API, the old API
>>> removed, and the new API renamed to the more desirable name. 
> 
> I really would like to see more sensible and shorter names for the API
> functions.

I'm not sure if you're suggesting that you:

a) Really want to API renaming I mention above to happen at some time.

b) We need to pick a better name now, for the new API this patch
introduces. If so, do you have any better suggestion?

>>> --- a/drivers/dma/acpi-dma.c
>>> +++ b/drivers/dma/acpi-dma.c
>>> @@ -334,7 +334,7 @@ static int acpi_dma_parse_fixed_dma(struct acpi_resource *res, void *data)
>>>   * @dev:       struct device to get DMA request from
>>>   * @index:     index of FixedDMA descriptor for @dev
>>>   *
>>> - * Returns pointer to appropriate dma channel on success or NULL on error.
>>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>>>   */
>>>  struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
>>>                 size_t index)
>>> @@ -349,10 +349,10 @@ struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
> 
> We use default value of chan if it's not found. Perhaps you have to
> change it as well to something like ERR_PTR(-ENOENT).

Ah yes. I think I'll keep the default value of chan = NULL, and just
change the return statement to something like:

return chan ? chan : ERR_PTR(-ENOENT);

That way, the fact that adma->acpi_dma_xlate() returns
NULL-or-valid-pointer and the check of chan against NULL inside the
list_for_each_entry() won't have to change.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/18/2013 02:18 AM, Shevchenko, Andriy wrote:
> On Fri, 2013-11-15 at 13:01 -0800, Dan Williams wrote:
>> On Fri, Nov 15, 2013 at 12:54 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> 
>>> Eventually, all drivers should be converted to this new API, the old API
>>> removed, and the new API renamed to the more desirable name. 
> 
> I really would like to see more sensible and shorter names for the API
> functions.

I'm not sure if you're suggesting that you:

a) Really want to API renaming I mention above to happen at some time.

b) We need to pick a better name now, for the new API this patch
introduces. If so, do you have any better suggestion?

>>> --- a/drivers/dma/acpi-dma.c
>>> +++ b/drivers/dma/acpi-dma.c
>>> @@ -334,7 +334,7 @@ static int acpi_dma_parse_fixed_dma(struct acpi_resource *res, void *data)
>>>   * @dev:       struct device to get DMA request from
>>>   * @index:     index of FixedDMA descriptor for @dev
>>>   *
>>> - * Returns pointer to appropriate dma channel on success or NULL on error.
>>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>>>   */
>>>  struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
>>>                 size_t index)
>>> @@ -349,10 +349,10 @@ struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev,
> 
> We use default value of chan if it's not found. Perhaps you have to
> change it as well to something like ERR_PTR(-ENOENT).

Ah yes. I think I'll keep the default value of chan = NULL, and just
change the return statement to something like:

return chan ? chan : ERR_PTR(-ENOENT);

That way, the fact that adma->acpi_dma_xlate() returns
NULL-or-valid-pointer and the check of chan against NULL inside the
list_for_each_entry() won't have to change.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Andy Shevchenko]

On Mon, 2013-11-18 at 10:42 -0700, Stephen Warren wrote:
> On 11/18/2013 02:18 AM, Shevchenko, Andriy wrote:
> > On Fri, 2013-11-15 at 13:01 -0800, Dan Williams wrote:
> >> On Fri, Nov 15, 2013 at 12:54 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> > 
> >>> Eventually, all drivers should be converted to this new API, the old API
> >>> removed, and the new API renamed to the more desirable name. 
> > 
> > I really would like to see more sensible and shorter names for the API
> > functions.
> 
> I'm not sure if you're suggesting that you:
> 
> a) Really want to API renaming I mention above to happen at some time.
> 
> b) We need to pick a better name now, for the new API this patch
> introduces. If so, do you have any better suggestion?

Sooner better, I think. 

Now only what I can propose is to change
dma_slave_request_channel_or_err() to dma_slave_request_chan().

In any way the dma_slave_request_* API is quite new and we, as far as I
understood, will come when the main request function will always return
channel or error.

-- 
Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
Intel Finland Oy

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Andy Shevchenko]

On Mon, 2013-11-18 at 10:42 -0700, Stephen Warren wrote:
> On 11/18/2013 02:18 AM, Shevchenko, Andriy wrote:
> > On Fri, 2013-11-15 at 13:01 -0800, Dan Williams wrote:
> >> On Fri, Nov 15, 2013 at 12:54 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> > 
> >>> Eventually, all drivers should be converted to this new API, the old API
> >>> removed, and the new API renamed to the more desirable name. 
> > 
> > I really would like to see more sensible and shorter names for the API
> > functions.
> 
> I'm not sure if you're suggesting that you:
> 
> a) Really want to API renaming I mention above to happen at some time.
> 
> b) We need to pick a better name now, for the new API this patch
> introduces. If so, do you have any better suggestion?

Sooner better, I think. 

Now only what I can propose is to change
dma_slave_request_channel_or_err() to dma_slave_request_chan().

In any way the dma_slave_request_* API is quite new and we, as far as I
understood, will come when the main request function will always return
channel or error.

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/19/2013 05:00 AM, Andy Shevchenko wrote:
> On Mon, 2013-11-18 at 10:42 -0700, Stephen Warren wrote:
>> On 11/18/2013 02:18 AM, Shevchenko, Andriy wrote:
>>> On Fri, 2013-11-15 at 13:01 -0800, Dan Williams wrote:
>>>> On Fri, Nov 15, 2013 at 12:54 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>>>
>>>>> Eventually, all drivers should be converted to this new API, the old API
>>>>> removed, and the new API renamed to the more desirable name. 
>>>
>>> I really would like to see more sensible and shorter names for the API
>>> functions.
>>
>> I'm not sure if you're suggesting that you:
>>
>> a) Really want to API renaming I mention above to happen at some time.
>>
>> b) We need to pick a better name now, for the new API this patch
>> introduces. If so, do you have any better suggestion?
> 
> Sooner better, I think. 
> 
> Now only what I can propose is to change
> dma_slave_request_channel_or_err() to dma_slave_request_chan().

The one downside I see with the name dma_slave_request_chan() is that
it's very similar to the existing dma_request_slave_channel(); driver
authors may well be confused which is which, and end up using the wrong
one. That's why I added an explicit "_or_err" to the function name.
Still, I can go for dma_slave_request_chan() if the dmaengine
maintainers think it's the right choice; just let me know.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/19/2013 05:00 AM, Andy Shevchenko wrote:
> On Mon, 2013-11-18 at 10:42 -0700, Stephen Warren wrote:
>> On 11/18/2013 02:18 AM, Shevchenko, Andriy wrote:
>>> On Fri, 2013-11-15 at 13:01 -0800, Dan Williams wrote:
>>>> On Fri, Nov 15, 2013 at 12:54 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>>
>>>>> Eventually, all drivers should be converted to this new API, the old API
>>>>> removed, and the new API renamed to the more desirable name. 
>>>
>>> I really would like to see more sensible and shorter names for the API
>>> functions.
>>
>> I'm not sure if you're suggesting that you:
>>
>> a) Really want to API renaming I mention above to happen at some time.
>>
>> b) We need to pick a better name now, for the new API this patch
>> introduces. If so, do you have any better suggestion?
> 
> Sooner better, I think. 
> 
> Now only what I can propose is to change
> dma_slave_request_channel_or_err() to dma_slave_request_chan().

The one downside I see with the name dma_slave_request_chan() is that
it's very similar to the existing dma_request_slave_channel(); driver
authors may well be confused which is which, and end up using the wrong
one. That's why I added an explicit "_or_err" to the function name.
Still, I can go for dma_slave_request_chan() if the dmaengine
maintainers think it's the right choice; just let me know.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Tue, Nov 19, 2013 at 9:15 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> On 11/19/2013 05:00 AM, Andy Shevchenko wrote:
>> On Mon, 2013-11-18 at 10:42 -0700, Stephen Warren wrote:
>>> On 11/18/2013 02:18 AM, Shevchenko, Andriy wrote:
>>>> On Fri, 2013-11-15 at 13:01 -0800, Dan Williams wrote:
>>>>> On Fri, Nov 15, 2013 at 12:54 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>>>>
>>>>>> Eventually, all drivers should be converted to this new API, the old API
>>>>>> removed, and the new API renamed to the more desirable name.
>>>>
>>>> I really would like to see more sensible and shorter names for the API
>>>> functions.
>>>
>>> I'm not sure if you're suggesting that you:
>>>
>>> a) Really want to API renaming I mention above to happen at some time.
>>>
>>> b) We need to pick a better name now, for the new API this patch
>>> introduces. If so, do you have any better suggestion?
>>
>> Sooner better, I think.
>>
>> Now only what I can propose is to change
>> dma_slave_request_channel_or_err() to dma_slave_request_chan().
>
> The one downside I see with the name dma_slave_request_chan() is that
> it's very similar to the existing dma_request_slave_channel(); driver
> authors may well be confused which is which, and end up using the wrong
> one. That's why I added an explicit "_or_err" to the function name.
> Still, I can go for dma_slave_request_chan() if the dmaengine
> maintainers think it's the right choice; just let me know.

I think the problem with dma_slave_request_channel_or_err() is that it
does not tell you what the function does or how it's different from
the existing one.  I think dma_slave_request_channel_defer() with a
comment about what error value callers should be expecting to
delineate a permanent error vs "try again later".

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Tue, Nov 19, 2013 at 9:15 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 11/19/2013 05:00 AM, Andy Shevchenko wrote:
>> On Mon, 2013-11-18 at 10:42 -0700, Stephen Warren wrote:
>>> On 11/18/2013 02:18 AM, Shevchenko, Andriy wrote:
>>>> On Fri, 2013-11-15 at 13:01 -0800, Dan Williams wrote:
>>>>> On Fri, Nov 15, 2013 at 12:54 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>>>
>>>>>> Eventually, all drivers should be converted to this new API, the old API
>>>>>> removed, and the new API renamed to the more desirable name.
>>>>
>>>> I really would like to see more sensible and shorter names for the API
>>>> functions.
>>>
>>> I'm not sure if you're suggesting that you:
>>>
>>> a) Really want to API renaming I mention above to happen at some time.
>>>
>>> b) We need to pick a better name now, for the new API this patch
>>> introduces. If so, do you have any better suggestion?
>>
>> Sooner better, I think.
>>
>> Now only what I can propose is to change
>> dma_slave_request_channel_or_err() to dma_slave_request_chan().
>
> The one downside I see with the name dma_slave_request_chan() is that
> it's very similar to the existing dma_request_slave_channel(); driver
> authors may well be confused which is which, and end up using the wrong
> one. That's why I added an explicit "_or_err" to the function name.
> Still, I can go for dma_slave_request_chan() if the dmaengine
> maintainers think it's the right choice; just let me know.

I think the problem with dma_slave_request_channel_or_err() is that it
does not tell you what the function does or how it's different from
the existing one.  I think dma_slave_request_channel_defer() with a
comment about what error value callers should be expecting to
delineate a permanent error vs "try again later".

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/19/2013 04:37 PM, Dan Williams wrote:
> On Tue, Nov 19, 2013 at 9:15 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>> On 11/19/2013 05:00 AM, Andy Shevchenko wrote:
>>> On Mon, 2013-11-18 at 10:42 -0700, Stephen Warren wrote:
>>>> On 11/18/2013 02:18 AM, Shevchenko, Andriy wrote:
>>>>> On Fri, 2013-11-15 at 13:01 -0800, Dan Williams wrote:
>>>>>> On Fri, Nov 15, 2013 at 12:54 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>>>>>
>>>>>>> Eventually, all drivers should be converted to this new API, the old API
>>>>>>> removed, and the new API renamed to the more desirable name.
>>>>>
>>>>> I really would like to see more sensible and shorter names for the API
>>>>> functions.
>>>>
>>>> I'm not sure if you're suggesting that you:
>>>>
>>>> a) Really want to API renaming I mention above to happen at some time.
>>>>
>>>> b) We need to pick a better name now, for the new API this patch
>>>> introduces. If so, do you have any better suggestion?
>>>
>>> Sooner better, I think.
>>>
>>> Now only what I can propose is to change
>>> dma_slave_request_channel_or_err() to dma_slave_request_chan().
>>
>> The one downside I see with the name dma_slave_request_chan() is that
>> it's very similar to the existing dma_request_slave_channel(); driver
>> authors may well be confused which is which, and end up using the wrong
>> one. That's why I added an explicit "_or_err" to the function name.
>> Still, I can go for dma_slave_request_chan() if the dmaengine
>> maintainers think it's the right choice; just let me know.
> 
> I think the problem with dma_slave_request_channel_or_err() is that it
> does not tell you what the function does or how it's different from
> the existing one.  I think dma_slave_request_channel_defer() with a
> comment about what error value callers should be expecting to
> delineate a permanent error vs "try again later".

Deferred probe certainly isn't the only error that can be returned
though, so I don't think "defer" in the name makes much sense. The
function as I wrote it returns a standard "error pointer" value.
Typically, callers would simply propagate *any* error code back to the
caller of probe() without even looking at it; it's the driver core that
checks for -EPROBE_DEFER vs. other error codes. In some cases, drivers
do check in order to avoid printing failure messages in the deferred
probe case, but again that's pretty standard, and not something specific
to this API.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/19/2013 04:37 PM, Dan Williams wrote:
> On Tue, Nov 19, 2013 at 9:15 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> On 11/19/2013 05:00 AM, Andy Shevchenko wrote:
>>> On Mon, 2013-11-18 at 10:42 -0700, Stephen Warren wrote:
>>>> On 11/18/2013 02:18 AM, Shevchenko, Andriy wrote:
>>>>> On Fri, 2013-11-15 at 13:01 -0800, Dan Williams wrote:
>>>>>> On Fri, Nov 15, 2013 at 12:54 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>>>>
>>>>>>> Eventually, all drivers should be converted to this new API, the old API
>>>>>>> removed, and the new API renamed to the more desirable name.
>>>>>
>>>>> I really would like to see more sensible and shorter names for the API
>>>>> functions.
>>>>
>>>> I'm not sure if you're suggesting that you:
>>>>
>>>> a) Really want to API renaming I mention above to happen at some time.
>>>>
>>>> b) We need to pick a better name now, for the new API this patch
>>>> introduces. If so, do you have any better suggestion?
>>>
>>> Sooner better, I think.
>>>
>>> Now only what I can propose is to change
>>> dma_slave_request_channel_or_err() to dma_slave_request_chan().
>>
>> The one downside I see with the name dma_slave_request_chan() is that
>> it's very similar to the existing dma_request_slave_channel(); driver
>> authors may well be confused which is which, and end up using the wrong
>> one. That's why I added an explicit "_or_err" to the function name.
>> Still, I can go for dma_slave_request_chan() if the dmaengine
>> maintainers think it's the right choice; just let me know.
> 
> I think the problem with dma_slave_request_channel_or_err() is that it
> does not tell you what the function does or how it's different from
> the existing one.  I think dma_slave_request_channel_defer() with a
> comment about what error value callers should be expecting to
> delineate a permanent error vs "try again later".

Deferred probe certainly isn't the only error that can be returned
though, so I don't think "defer" in the name makes much sense. The
function as I wrote it returns a standard "error pointer" value.
Typically, callers would simply propagate *any* error code back to the
caller of probe() without even looking at it; it's the driver core that
checks for -EPROBE_DEFER vs. other error codes. In some cases, drivers
do check in order to avoid printing failure messages in the deferred
probe case, but again that's pretty standard, and not something specific
to this API.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Tue, Nov 19, 2013 at 4:09 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> Deferred probe certainly isn't the only error that can be returned
> though,

Of course, but do any of those other ones matter?  Certainly not if
they've all been hidden behind a NULL return from
dma_request_slave_channel().

> so I don't think "defer" in the name makes much sense. The
> function as I wrote it returns a standard "error pointer" value.
> Typically, callers would simply propagate *any* error code back to the
> caller of probe() without even looking at it; it's the driver core that
> checks for -EPROBE_DEFER vs. other error codes. In some cases, drivers
> do check in order to avoid printing failure messages in the deferred
> probe case, but again that's pretty standard, and not something specific
> to this API.

Right, but the only reason to introduce this API is to propagate
EPROBE_DEFER, right?  It also serves to document drivers that are
prepared for / depend on deferred probing support.

Good old bike shedding... I only jumped in because I think changing it
to dma_slave_request_chan() would indeed be confusing .

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Tue, Nov 19, 2013 at 4:09 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> Deferred probe certainly isn't the only error that can be returned
> though,

Of course, but do any of those other ones matter?  Certainly not if
they've all been hidden behind a NULL return from
dma_request_slave_channel().

> so I don't think "defer" in the name makes much sense. The
> function as I wrote it returns a standard "error pointer" value.
> Typically, callers would simply propagate *any* error code back to the
> caller of probe() without even looking at it; it's the driver core that
> checks for -EPROBE_DEFER vs. other error codes. In some cases, drivers
> do check in order to avoid printing failure messages in the deferred
> probe case, but again that's pretty standard, and not something specific
> to this API.

Right, but the only reason to introduce this API is to propagate
EPROBE_DEFER, right?  It also serves to document drivers that are
prepared for / depend on deferred probing support.

Good old bike shedding... I only jumped in because I think changing it
to dma_slave_request_chan() would indeed be confusing .

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/19/2013 05:38 PM, Dan Williams wrote:
> On Tue, Nov 19, 2013 at 4:09 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>> Deferred probe certainly isn't the only error that can be returned
>> though,
> 
> Of course, but do any of those other ones matter?  Certainly not if
> they've all been hidden behind a NULL return from
> dma_request_slave_channel().
> 
>> so I don't think "defer" in the name makes much sense. The
>> function as I wrote it returns a standard "error pointer" value.
>> Typically, callers would simply propagate *any* error code back to the
>> caller of probe() without even looking at it; it's the driver core that
>> checks for -EPROBE_DEFER vs. other error codes. In some cases, drivers
>> do check in order to avoid printing failure messages in the deferred
>> probe case, but again that's pretty standard, and not something specific
>> to this API.
> 
> Right, but the only reason to introduce this API is to propagate
> EPROBE_DEFER, right?  It also serves to document drivers that are
> prepared for / depend on deferred probing support.

Well, that's the reason I'm introducing the API, but it's not really
what the API actually does.

That said, in the interests of moving this forward, I'll go for your
suggested name dma_slave_request_channel_defer().

Do I need an ack from Vinod on the function name, or the patches?

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/19/2013 05:38 PM, Dan Williams wrote:
> On Tue, Nov 19, 2013 at 4:09 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> Deferred probe certainly isn't the only error that can be returned
>> though,
> 
> Of course, but do any of those other ones matter?  Certainly not if
> they've all been hidden behind a NULL return from
> dma_request_slave_channel().
> 
>> so I don't think "defer" in the name makes much sense. The
>> function as I wrote it returns a standard "error pointer" value.
>> Typically, callers would simply propagate *any* error code back to the
>> caller of probe() without even looking at it; it's the driver core that
>> checks for -EPROBE_DEFER vs. other error codes. In some cases, drivers
>> do check in order to avoid printing failure messages in the deferred
>> probe case, but again that's pretty standard, and not something specific
>> to this API.
> 
> Right, but the only reason to introduce this API is to propagate
> EPROBE_DEFER, right?  It also serves to document drivers that are
> prepared for / depend on deferred probing support.

Well, that's the reason I'm introducing the API, but it's not really
what the API actually does.

That said, in the interests of moving this forward, I'll go for your
suggested name dma_slave_request_channel_defer().

Do I need an ack from Vinod on the function name, or the patches?

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Wed, Nov 20, 2013 at 10:24 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> On 11/19/2013 05:38 PM, Dan Williams wrote:
>> On Tue, Nov 19, 2013 at 4:09 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>>> Deferred probe certainly isn't the only error that can be returned
>>> though,
>>
>> Of course, but do any of those other ones matter?  Certainly not if
>> they've all been hidden behind a NULL return from
>> dma_request_slave_channel().
>>
>>> so I don't think "defer" in the name makes much sense. The
>>> function as I wrote it returns a standard "error pointer" value.
>>> Typically, callers would simply propagate *any* error code back to the
>>> caller of probe() without even looking at it; it's the driver core that
>>> checks for -EPROBE_DEFER vs. other error codes. In some cases, drivers
>>> do check in order to avoid printing failure messages in the deferred
>>> probe case, but again that's pretty standard, and not something specific
>>> to this API.
>>
>> Right, but the only reason to introduce this API is to propagate
>> EPROBE_DEFER, right?  It also serves to document drivers that are
>> prepared for / depend on deferred probing support.
>
> Well, that's the reason I'm introducing the API, but it's not really
> what the API actually does.
>

True, this is quite a bit of back and forth for something that will be
temporary.  How bad would it be to short-circuit this discussion and
go straight to converting dma_request_slave_channel().  Leave
dma_request_channel() as is and just convert the 20 or so users of
dma_request_slave_channel() over?

Also seems you could drop the changes to acpi-dma.c altogether if we
pass the result through IS_ERR_OR_NULL().

> That said, in the interests of moving this forward, I'll go for your
> suggested name dma_slave_request_channel_defer().
>
> Do I need an ack from Vinod on the function name, or the patches?

Yes, Vinod should ultimately ack all dma-slave patches... and throw in
another name recommendation for good measure ;-).

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Wed, Nov 20, 2013 at 10:24 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 11/19/2013 05:38 PM, Dan Williams wrote:
>> On Tue, Nov 19, 2013 at 4:09 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>> Deferred probe certainly isn't the only error that can be returned
>>> though,
>>
>> Of course, but do any of those other ones matter?  Certainly not if
>> they've all been hidden behind a NULL return from
>> dma_request_slave_channel().
>>
>>> so I don't think "defer" in the name makes much sense. The
>>> function as I wrote it returns a standard "error pointer" value.
>>> Typically, callers would simply propagate *any* error code back to the
>>> caller of probe() without even looking at it; it's the driver core that
>>> checks for -EPROBE_DEFER vs. other error codes. In some cases, drivers
>>> do check in order to avoid printing failure messages in the deferred
>>> probe case, but again that's pretty standard, and not something specific
>>> to this API.
>>
>> Right, but the only reason to introduce this API is to propagate
>> EPROBE_DEFER, right?  It also serves to document drivers that are
>> prepared for / depend on deferred probing support.
>
> Well, that's the reason I'm introducing the API, but it's not really
> what the API actually does.
>

True, this is quite a bit of back and forth for something that will be
temporary.  How bad would it be to short-circuit this discussion and
go straight to converting dma_request_slave_channel().  Leave
dma_request_channel() as is and just convert the 20 or so users of
dma_request_slave_channel() over?

Also seems you could drop the changes to acpi-dma.c altogether if we
pass the result through IS_ERR_OR_NULL().

> That said, in the interests of moving this forward, I'll go for your
> suggested name dma_slave_request_channel_defer().
>
> Do I need an ack from Vinod on the function name, or the patches?

Yes, Vinod should ultimately ack all dma-slave patches... and throw in
another name recommendation for good measure ;-).

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/20/2013 12:15 PM, Dan Williams wrote:
> On Wed, Nov 20, 2013 at 10:24 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>> On 11/19/2013 05:38 PM, Dan Williams wrote:
>>> On Tue, Nov 19, 2013 at 4:09 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>>>> Deferred probe certainly isn't the only error that can be returned
>>>> though,
>>>
>>> Of course, but do any of those other ones matter?  Certainly not if
>>> they've all been hidden behind a NULL return from
>>> dma_request_slave_channel().
>>>
>>>> so I don't think "defer" in the name makes much sense. The
>>>> function as I wrote it returns a standard "error pointer" value.
>>>> Typically, callers would simply propagate *any* error code back to the
>>>> caller of probe() without even looking at it; it's the driver core that
>>>> checks for -EPROBE_DEFER vs. other error codes. In some cases, drivers
>>>> do check in order to avoid printing failure messages in the deferred
>>>> probe case, but again that's pretty standard, and not something specific
>>>> to this API.
>>>
>>> Right, but the only reason to introduce this API is to propagate
>>> EPROBE_DEFER, right?  It also serves to document drivers that are
>>> prepared for / depend on deferred probing support.
>>
>> Well, that's the reason I'm introducing the API, but it's not really
>> what the API actually does.
>>
> 
> True, this is quite a bit of back and forth for something that will be
> temporary.  How bad would it be to short-circuit this discussion and
> go straight to converting dma_request_slave_channel().  Leave
> dma_request_channel() as is and just convert the 20 or so users of
> dma_request_slave_channel() over?

I had thought about that, but there are drivers that use
dma_request_slave_channel(), but fall back to dma_request_channel() if
that fails. I think there were other cases where the two APIs were
mixed. Drivers would then have a value that sometimes IS_ERR() or is
valid, and other times ==NULL or is valid. So, the values would have to
be checked using IS_ERR_OR_NULL() which I believe is now deprecated  -
certainly Russell will shout at me if I start introducing more usage! So
that means converting dma_request_channel()'s return value too, and that
is a /lot/ more to convert. I suppose an alternative might be to have
the individual affected drivers convert a NULL return from
dma_request_channel() to an ERR value, but for some reason I forget now,
even that looked problematic.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/20/2013 12:15 PM, Dan Williams wrote:
> On Wed, Nov 20, 2013 at 10:24 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> On 11/19/2013 05:38 PM, Dan Williams wrote:
>>> On Tue, Nov 19, 2013 at 4:09 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>>> Deferred probe certainly isn't the only error that can be returned
>>>> though,
>>>
>>> Of course, but do any of those other ones matter?  Certainly not if
>>> they've all been hidden behind a NULL return from
>>> dma_request_slave_channel().
>>>
>>>> so I don't think "defer" in the name makes much sense. The
>>>> function as I wrote it returns a standard "error pointer" value.
>>>> Typically, callers would simply propagate *any* error code back to the
>>>> caller of probe() without even looking at it; it's the driver core that
>>>> checks for -EPROBE_DEFER vs. other error codes. In some cases, drivers
>>>> do check in order to avoid printing failure messages in the deferred
>>>> probe case, but again that's pretty standard, and not something specific
>>>> to this API.
>>>
>>> Right, but the only reason to introduce this API is to propagate
>>> EPROBE_DEFER, right?  It also serves to document drivers that are
>>> prepared for / depend on deferred probing support.
>>
>> Well, that's the reason I'm introducing the API, but it's not really
>> what the API actually does.
>>
> 
> True, this is quite a bit of back and forth for something that will be
> temporary.  How bad would it be to short-circuit this discussion and
> go straight to converting dma_request_slave_channel().  Leave
> dma_request_channel() as is and just convert the 20 or so users of
> dma_request_slave_channel() over?

I had thought about that, but there are drivers that use
dma_request_slave_channel(), but fall back to dma_request_channel() if
that fails. I think there were other cases where the two APIs were
mixed. Drivers would then have a value that sometimes IS_ERR() or is
valid, and other times ==NULL or is valid. So, the values would have to
be checked using IS_ERR_OR_NULL() which I believe is now deprecated  -
certainly Russell will shout at me if I start introducing more usage! So
that means converting dma_request_channel()'s return value too, and that
is a /lot/ more to convert. I suppose an alternative might be to have
the individual affected drivers convert a NULL return from
dma_request_channel() to an ERR value, but for some reason I forget now,
even that looked problematic.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Williams, Dan J]

On Wed, 2013-11-20 at 12:22 -0700, Stephen Warren wrote:
> On 11/20/2013 12:15 PM, Dan Williams wrote:
> > On Wed, Nov 20, 2013 at 10:24 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> >> On 11/19/2013 05:38 PM, Dan Williams wrote:
> >>> On Tue, Nov 19, 2013 at 4:09 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> >>>> Deferred probe certainly isn't the only error that can be returned
> >>>> though,
> >>>
> >>> Of course, but do any of those other ones matter?  Certainly not if
> >>> they've all been hidden behind a NULL return from
> >>> dma_request_slave_channel().
> >>>
> >>>> so I don't think "defer" in the name makes much sense. The
> >>>> function as I wrote it returns a standard "error pointer" value.
> >>>> Typically, callers would simply propagate *any* error code back to the
> >>>> caller of probe() without even looking at it; it's the driver core that
> >>>> checks for -EPROBE_DEFER vs. other error codes. In some cases, drivers
> >>>> do check in order to avoid printing failure messages in the deferred
> >>>> probe case, but again that's pretty standard, and not something specific
> >>>> to this API.
> >>>
> >>> Right, but the only reason to introduce this API is to propagate
> >>> EPROBE_DEFER, right?  It also serves to document drivers that are
> >>> prepared for / depend on deferred probing support.
> >>
> >> Well, that's the reason I'm introducing the API, but it's not really
> >> what the API actually does.
> >>
> > 
> > True, this is quite a bit of back and forth for something that will be
> > temporary.  How bad would it be to short-circuit this discussion and
> > go straight to converting dma_request_slave_channel().  Leave
> > dma_request_channel() as is and just convert the 20 or so users of
> > dma_request_slave_channel() over?
> 
> I had thought about that, but there are drivers that use
> dma_request_slave_channel(), but fall back to dma_request_channel() if
> that fails. I think there were other cases where the two APIs were
> mixed. Drivers would then have a value that sometimes IS_ERR() or is
> valid, and other times ==NULL or is valid. So, the values would have to
> be checked using IS_ERR_OR_NULL() which I believe is now deprecated  -
> certainly Russell will shout at me if I start introducing more usage! 

Ok, I found the discussion about IS_ERR_OR_NULL(), but actually we would
not need to use it, just check for NULL and return an error in
__dma_request_slave_channel.

> So
> that means converting dma_request_channel()'s return value too, and that
> is a /lot/ more to convert. I suppose an alternative might be to have
> the individual affected drivers convert a NULL return from
> dma_request_channel() to an ERR value, but for some reason I forget now,
> even that looked problematic.

Why do the drivers that call dma_request_channel need to convert it to
an ERR value?  i.e. what's problematic about the below (not compile
tested)?

btw, samsung_dmadev_request() looks like a crash waiting to happen when
that hardware ip shows up on a 64-bit system.


diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
index ec0d731b0e7b..abee452bcf6e 100644
--- a/arch/arm/plat-samsung/dma-ops.c
+++ b/arch/arm/plat-samsung/dma-ops.c
@@ -22,16 +22,20 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
 				struct samsung_dma_req *param,
 				struct device *dev, char *ch_name)
 {
+	struct dma_chan *chan;
+
 	dma_cap_mask_t mask;
 
 	dma_cap_zero(mask);
 	dma_cap_set(param->cap, mask);
 
-	if (dev->of_node)
-		return (unsigned)dma_request_slave_channel(dev, ch_name);
-	else
+	if (dev->of_node) {
+		chan = dma_request_slave_channel(dev, ch_name);
+		return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
+	} else {
 		return (unsigned)dma_request_channel(mask, pl330_filter,
 							(void *)dma_ch);
+	}
 }
 
 static int samsung_dmadev_release(unsigned ch, void *param)
diff --git a/drivers/ata/pata_arasan_cf.c b/drivers/ata/pata_arasan_cf.c
index 853f610af28f..c483b095e157 100644
--- a/drivers/ata/pata_arasan_cf.c
+++ b/drivers/ata/pata_arasan_cf.c
@@ -528,7 +528,8 @@ static void data_xfer(struct work_struct *work)
 	/* request dma channels */
 	/* dma_request_channel may sleep, so calling from process context */
 	acdev->dma_chan = dma_request_slave_channel(acdev->host->dev, "data");
-	if (!acdev->dma_chan) {
+	if (IS_ERR(acdev->dma_chan)) {
+		acdev->dma_chan = NULL;
 		dev_err(acdev->host->dev, "Unable to get dma_chan\n");
 		goto chan_request_fail;
 	}
diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
index 9162ac80c18f..64c163664b9d 100644
--- a/drivers/dma/dmaengine.c
+++ b/drivers/dma/dmaengine.c
@@ -593,15 +593,20 @@ EXPORT_SYMBOL_GPL(__dma_request_channel);
  */
 struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name)
 {
+	struct dma_chan *chan = ERR_PTR(-ENODEV);
+
 	/* If device-tree is present get slave info from here */
 	if (dev->of_node)
 		return of_dma_request_slave_channel(dev->of_node, name);
 
 	/* If device was enumerated by ACPI get slave info from here */
-	if (ACPI_HANDLE(dev))
-		return acpi_dma_request_slave_chan_by_name(dev, name);
+	if (ACPI_HANDLE(dev)) {
+		chan = acpi_dma_request_slave_chan_by_name(dev, name);
+		if (!chan)
+			chan = ERR_PTR(-ENODEV);
+	}
 
-	return NULL;
+	return chan;
 }
 EXPORT_SYMBOL_GPL(dma_request_slave_channel);
 
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
index b7c857774708..777e18db654a 100644
--- a/drivers/i2c/busses/i2c-mxs.c
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -723,7 +723,8 @@ static int mxs_i2c_probe(struct platform_device *pdev)
 
 	/* Setup the DMA */
 	i2c->dmach = dma_request_slave_channel(dev, "rx-tx");
-	if (!i2c->dmach) {
+	if (IS_ERR(i2c->dmach)) {
+		i2c->dmach = NULL;
 		dev_err(dev, "Failed to request dma\n");
 		return -ENODEV;
 	}
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index c3785edc0e92..342408961590 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -350,6 +350,11 @@ static void mmci_dma_setup(struct mmci_host *host)
 	host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx");
 	host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx");
 
+	if (IS_ERR(host->dma_rx_channel))
+		host->dma_rx_channel = NULL;
+	if (IS_ERR(host->dma_tx_channel))
+		host->dma_tx_channel = NULL;
+
 	/* initialize pre request cookie */
 	host->next_data.cookie = 1;
 
diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
index c174c6a0d224..527c1a427b13 100644
--- a/drivers/mmc/host/mxcmmc.c
+++ b/drivers/mmc/host/mxcmmc.c
@@ -1170,11 +1170,13 @@ static int mxcmci_probe(struct platform_device *pdev)
 			host->dma = dma_request_channel(mask, filter, host);
 		}
 	}
-	if (host->dma)
+	if (!IS_ERR(host->dma))
 		mmc->max_seg_size = dma_get_max_seg_size(
 				host->dma->device->dev);
-	else
+	else {
+		host->dma = NULL;
 		dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
+	}
 
 	INIT_WORK(&host->datawork, mxcmci_datawork);
 
diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
index e1fa3ef735e0..f5411a6001fa 100644
--- a/drivers/mmc/host/mxs-mmc.c
+++ b/drivers/mmc/host/mxs-mmc.c
@@ -636,7 +636,8 @@ static int mxs_mmc_probe(struct platform_device *pdev)
 	}
 
 	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
-	if (!ssp->dmach) {
+	if (IS_ERR(ssp->dmach)) {
+		ssp->dmach = NULL;
 		dev_err(mmc_dev(host->mmc),
 			"%s: failed to request dma\n", __func__);
 		ret = -ENODEV;
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index 59ab0692f0b9..fbe1f372faca 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -564,7 +564,7 @@ static int acquire_dma_channels(struct gpmi_nand_data *this)
 
 	/* request dma channel */
 	dma_chan = dma_request_slave_channel(&pdev->dev, "rx-tx");
-	if (!dma_chan) {
+	if (IS_ERR(dma_chan)) {
 		pr_err("Failed to request DMA channel.\n");
 		goto acquire_err;
 	}
diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index de7b1141b90f..7a3ebe87b106 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -552,7 +552,8 @@ static int mxs_spi_probe(struct platform_device *pdev)
 		goto out_master_free;
 
 	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
-	if (!ssp->dmach) {
+	if (IS_ERR(ssp->dmach)) {
+		ssp->dmach = NULL;
 		dev_err(ssp->dev, "Failed to request DMA\n");
 		ret = -ENODEV;
 		goto out_master_free;
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index 9c511a954d21..38d4121f7073 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -1140,11 +1140,11 @@ static int pl022_dma_autoprobe(struct pl022 *pl022)
 
 	/* automatically configure DMA channels from platform, normally using DT */
 	pl022->dma_rx_channel = dma_request_slave_channel(dev, "rx");
-	if (!pl022->dma_rx_channel)
+	if (IS_ERR(pl022->dma_rx_channel))
 		goto err_no_rxchan;
 
 	pl022->dma_tx_channel = dma_request_slave_channel(dev, "tx");
-	if (!pl022->dma_tx_channel)
+	if (IS_ERR(pl022->dma_tx_channel))
 		goto err_no_txchan;
 
 	pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
@@ -1155,11 +1155,11 @@ static int pl022_dma_autoprobe(struct pl022 *pl022)
 
 err_no_dummypage:
 	dma_release_channel(pl022->dma_tx_channel);
-	pl022->dma_tx_channel = NULL;
 err_no_txchan:
+	pl022->dma_tx_channel = NULL;
 	dma_release_channel(pl022->dma_rx_channel);
-	pl022->dma_rx_channel = NULL;
 err_no_rxchan:
+	pl022->dma_rx_channel = NULL;
 	return -ENODEV;
 }
 		
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index aaa22867e656..c0f400c3c954 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -278,7 +278,7 @@ static void pl011_dma_probe_initcall(struct device *dev, struct uart_amba_port *
 
 	chan = dma_request_slave_channel(dev, "tx");
 
-	if (!chan) {
+	if (IS_ERR(chan)) {
 		/* We need platform data */
 		if (!plat || !plat->dma_filter) {
 			dev_info(uap->port.dev, "no DMA platform data\n");
@@ -305,8 +305,10 @@ static void pl011_dma_probe_initcall(struct device *dev, struct uart_amba_port *
 
 	/* Optionally make use of an RX channel as well */
 	chan = dma_request_slave_channel(dev, "rx");
+	if (IS_ERR(chan))
+		chan = NULL;
 	
-	if (!chan && plat->dma_rx_param) {
+	if (chan && plat->dma_rx_param) {
 		chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
 
 		if (!chan) {
diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index d067285a2d20..c0ae083e061c 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -723,8 +723,10 @@ static int atmel_prepare_tx_dma(struct uart_port *port)
 	dma_cap_set(DMA_SLAVE, mask);
 
 	atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
-	if (atmel_port->chan_tx == NULL)
+	if (IS_ERR(atmel_port->chan_tx)) {
+		atmel_port->chan_tx = NULL;
 		goto chan_err;
+	}
 	dev_info(port->dev, "using %s for tx DMA transfers\n",
 		dma_chan_name(atmel_port->chan_tx));
 
@@ -890,8 +892,10 @@ static int atmel_prepare_rx_dma(struct uart_port *port)
 	dma_cap_set(DMA_CYCLIC, mask);
 
 	atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
-	if (atmel_port->chan_rx == NULL)
+	if (IS_ERR(atmel_port->chan_rx)) {
+		atmel_port->chan_rx = NULL;
 		goto chan_err;
+	}
 	dev_info(port->dev, "using %s for rx DMA transfers\n",
 		dma_chan_name(atmel_port->chan_rx));
 
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 042aa077b5b3..1e4cb60ce0af 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -985,7 +985,8 @@ static int imx_uart_dma_init(struct imx_port *sport)
 
 	/* Prepare for RX : */
 	sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
-	if (!sport->dma_chan_rx) {
+	if (IS_ERR(sport->dma_chan_rx)) {
+		sport->dma_chan_rx = NULL;
 		dev_dbg(dev, "cannot get the DMA channel.\n");
 		ret = -EINVAL;
 		goto err;
@@ -1011,7 +1012,8 @@ static int imx_uart_dma_init(struct imx_port *sport)
 
 	/* Prepare for TX : */
 	sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
-	if (!sport->dma_chan_tx) {
+	if (IS_ERR(sport->dma_chan_tx)) {
+		sport->dma_chan_tx = NULL;
 		dev_err(dev, "cannot get the TX DMA channel!\n");
 		ret = -EINVAL;
 		goto err;
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
index 10e9d70b5c40..cc9747ab71cd 100644
--- a/drivers/tty/serial/mxs-auart.c
+++ b/drivers/tty/serial/mxs-auart.c
@@ -530,16 +530,20 @@ static int mxs_auart_dma_init(struct mxs_auart_port *s)
 
 	/* init for RX */
 	s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx");
-	if (!s->rx_dma_chan)
+	if (IS_ERR(s->rx_dma_chan)) {
+		s->rx_dma_chan = NULL;
 		goto err_out;
+	}
 	s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
 	if (!s->rx_dma_buf)
 		goto err_out;
 
 	/* init for TX */
 	s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx");
-	if (!s->tx_dma_chan)
+	if (IS_ERR(s->tx_dma_chan)) {
+		s->tx_dma_chan = NULL;
 		goto err_out;
+	}
 	s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
 	if (!s->tx_dma_buf)
 		goto err_out;
diff --git a/drivers/usb/musb/musb_cppi41.c b/drivers/usb/musb/musb_cppi41.c
index ff9d6de2b746..b71c5f138968 100644
--- a/drivers/usb/musb/musb_cppi41.c
+++ b/drivers/usb/musb/musb_cppi41.c
@@ -502,7 +502,7 @@ static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller)
 		musb_dma->max_len = SZ_4M;
 
 		dc = dma_request_slave_channel(dev, str);
-		if (!dc) {
+		if (IS_ERR(dc)) {
 			dev_err(dev, "Falied to request %s.\n", str);
 			ret = -EPROBE_DEFER;
 			goto err;
diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c
index 3700e9713258..6c863b90ad66 100644
--- a/drivers/usb/musb/ux500_dma.c
+++ b/drivers/usb/musb/ux500_dma.c
@@ -330,13 +330,14 @@ static int ux500_dma_controller_start(struct ux500_dma_controller *controller)
 			ux500_channel->dma_chan =
 				dma_request_slave_channel(dev, chan_names[ch_num]);
 
-			if (!ux500_channel->dma_chan)
+			if (IS_ERR(ux500_channel->dma_chan)) {
 				ux500_channel->dma_chan =
 					dma_request_channel(mask,
 							    data ?
 							    data->dma_filter :
 							    NULL,
 							    param_array[ch_num]);
+			}
 
 			if (!ux500_channel->dma_chan) {
 				ERR("Dma pipe allocation error dir=%d ch=%d\n",
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 0bc727534108..0da9425d64e7 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -1056,7 +1056,7 @@ static inline struct dma_chan
 	struct dma_chan *chan;
 
 	chan = dma_request_slave_channel(dev, name);
-	if (chan)
+	if (!IS_ERR(chan))
 		return chan;
 
 	return __dma_request_channel(mask, fn, fn_param);
diff --git a/sound/soc/omap/omap-pcm.c b/sound/soc/omap/omap-pcm.c
index a11405de86e8..56c3056cdac7 100644
--- a/sound/soc/omap/omap-pcm.c
+++ b/sound/soc/omap/omap-pcm.c
@@ -125,7 +125,7 @@ static int omap_pcm_open(struct snd_pcm_substream *substream)
 
 		chan = dma_request_slave_channel(rtd->cpu_dai->dev,
 						 dma_data->filter_data);
-		ret = snd_dmaengine_pcm_open(substream, chan);
+		ret = snd_dmaengine_pcm_open(substream, IS_ERR(chan) ? NULL : chan);
 	} else {
 		ret = snd_dmaengine_pcm_open_request_chan(substream,
 							  omap_dma_filter_fn,
diff --git a/sound/soc/soc-generic-dmaengine-pcm.c b/sound/soc/soc-generic-dmaengine-pcm.c
index e29ec3cd84b1..4182b203fad5 100644
--- a/sound/soc/soc-generic-dmaengine-pcm.c
+++ b/sound/soc/soc-generic-dmaengine-pcm.c
@@ -227,11 +227,15 @@ static void dmaengine_pcm_request_chan_of(struct dmaengine_pcm *pcm,
 
 	if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX) {
 		pcm->chan[0] = dma_request_slave_channel(dev, "rx-tx");
+		if (IS_ERR(pcm->chan[0]))
+			pcm->chan[0] = NULL;
 		pcm->chan[1] = pcm->chan[0];
 	} else {
 		for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE; i++) {
 			pcm->chan[i] = dma_request_slave_channel(dev,
 					dmaengine_pcm_dma_channel_names[i]);
+			if (IS_ERR(pcm->chan[i]))
+				pcm->chan[i] = NULL;
 		}
 	}
 }

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Williams, Dan J]

On Wed, 2013-11-20 at 12:22 -0700, Stephen Warren wrote:
> On 11/20/2013 12:15 PM, Dan Williams wrote:
> > On Wed, Nov 20, 2013 at 10:24 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> >> On 11/19/2013 05:38 PM, Dan Williams wrote:
> >>> On Tue, Nov 19, 2013 at 4:09 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> >>>> Deferred probe certainly isn't the only error that can be returned
> >>>> though,
> >>>
> >>> Of course, but do any of those other ones matter?  Certainly not if
> >>> they've all been hidden behind a NULL return from
> >>> dma_request_slave_channel().
> >>>
> >>>> so I don't think "defer" in the name makes much sense. The
> >>>> function as I wrote it returns a standard "error pointer" value.
> >>>> Typically, callers would simply propagate *any* error code back to the
> >>>> caller of probe() without even looking at it; it's the driver core that
> >>>> checks for -EPROBE_DEFER vs. other error codes. In some cases, drivers
> >>>> do check in order to avoid printing failure messages in the deferred
> >>>> probe case, but again that's pretty standard, and not something specific
> >>>> to this API.
> >>>
> >>> Right, but the only reason to introduce this API is to propagate
> >>> EPROBE_DEFER, right?  It also serves to document drivers that are
> >>> prepared for / depend on deferred probing support.
> >>
> >> Well, that's the reason I'm introducing the API, but it's not really
> >> what the API actually does.
> >>
> > 
> > True, this is quite a bit of back and forth for something that will be
> > temporary.  How bad would it be to short-circuit this discussion and
> > go straight to converting dma_request_slave_channel().  Leave
> > dma_request_channel() as is and just convert the 20 or so users of
> > dma_request_slave_channel() over?
> 
> I had thought about that, but there are drivers that use
> dma_request_slave_channel(), but fall back to dma_request_channel() if
> that fails. I think there were other cases where the two APIs were
> mixed. Drivers would then have a value that sometimes IS_ERR() or is
> valid, and other times ==NULL or is valid. So, the values would have to
> be checked using IS_ERR_OR_NULL() which I believe is now deprecated  -
> certainly Russell will shout at me if I start introducing more usage! 

Ok, I found the discussion about IS_ERR_OR_NULL(), but actually we would
not need to use it, just check for NULL and return an error in
__dma_request_slave_channel.

> So
> that means converting dma_request_channel()'s return value too, and that
> is a /lot/ more to convert. I suppose an alternative might be to have
> the individual affected drivers convert a NULL return from
> dma_request_channel() to an ERR value, but for some reason I forget now,
> even that looked problematic.

Why do the drivers that call dma_request_channel need to convert it to
an ERR value?  i.e. what's problematic about the below (not compile
tested)?

btw, samsung_dmadev_request() looks like a crash waiting to happen when
that hardware ip shows up on a 64-bit system.


diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
index ec0d731b0e7b..abee452bcf6e 100644
--- a/arch/arm/plat-samsung/dma-ops.c
+++ b/arch/arm/plat-samsung/dma-ops.c
@@ -22,16 +22,20 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
 				struct samsung_dma_req *param,
 				struct device *dev, char *ch_name)
 {
+	struct dma_chan *chan;
+
 	dma_cap_mask_t mask;
 
 	dma_cap_zero(mask);
 	dma_cap_set(param->cap, mask);
 
-	if (dev->of_node)
-		return (unsigned)dma_request_slave_channel(dev, ch_name);
-	else
+	if (dev->of_node) {
+		chan = dma_request_slave_channel(dev, ch_name);
+		return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
+	} else {
 		return (unsigned)dma_request_channel(mask, pl330_filter,
 							(void *)dma_ch);
+	}
 }
 
 static int samsung_dmadev_release(unsigned ch, void *param)
diff --git a/drivers/ata/pata_arasan_cf.c b/drivers/ata/pata_arasan_cf.c
index 853f610af28f..c483b095e157 100644
--- a/drivers/ata/pata_arasan_cf.c
+++ b/drivers/ata/pata_arasan_cf.c
@@ -528,7 +528,8 @@ static void data_xfer(struct work_struct *work)
 	/* request dma channels */
 	/* dma_request_channel may sleep, so calling from process context */
 	acdev->dma_chan = dma_request_slave_channel(acdev->host->dev, "data");
-	if (!acdev->dma_chan) {
+	if (IS_ERR(acdev->dma_chan)) {
+		acdev->dma_chan = NULL;
 		dev_err(acdev->host->dev, "Unable to get dma_chan\n");
 		goto chan_request_fail;
 	}
diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
index 9162ac80c18f..64c163664b9d 100644
--- a/drivers/dma/dmaengine.c
+++ b/drivers/dma/dmaengine.c
@@ -593,15 +593,20 @@ EXPORT_SYMBOL_GPL(__dma_request_channel);
  */
 struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name)
 {
+	struct dma_chan *chan = ERR_PTR(-ENODEV);
+
 	/* If device-tree is present get slave info from here */
 	if (dev->of_node)
 		return of_dma_request_slave_channel(dev->of_node, name);
 
 	/* If device was enumerated by ACPI get slave info from here */
-	if (ACPI_HANDLE(dev))
-		return acpi_dma_request_slave_chan_by_name(dev, name);
+	if (ACPI_HANDLE(dev)) {
+		chan = acpi_dma_request_slave_chan_by_name(dev, name);
+		if (!chan)
+			chan = ERR_PTR(-ENODEV);
+	}
 
-	return NULL;
+	return chan;
 }
 EXPORT_SYMBOL_GPL(dma_request_slave_channel);
 
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
index b7c857774708..777e18db654a 100644
--- a/drivers/i2c/busses/i2c-mxs.c
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -723,7 +723,8 @@ static int mxs_i2c_probe(struct platform_device *pdev)
 
 	/* Setup the DMA */
 	i2c->dmach = dma_request_slave_channel(dev, "rx-tx");
-	if (!i2c->dmach) {
+	if (IS_ERR(i2c->dmach)) {
+		i2c->dmach = NULL;
 		dev_err(dev, "Failed to request dma\n");
 		return -ENODEV;
 	}
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index c3785edc0e92..342408961590 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -350,6 +350,11 @@ static void mmci_dma_setup(struct mmci_host *host)
 	host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx");
 	host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx");
 
+	if (IS_ERR(host->dma_rx_channel))
+		host->dma_rx_channel = NULL;
+	if (IS_ERR(host->dma_tx_channel))
+		host->dma_tx_channel = NULL;
+
 	/* initialize pre request cookie */
 	host->next_data.cookie = 1;
 
diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
index c174c6a0d224..527c1a427b13 100644
--- a/drivers/mmc/host/mxcmmc.c
+++ b/drivers/mmc/host/mxcmmc.c
@@ -1170,11 +1170,13 @@ static int mxcmci_probe(struct platform_device *pdev)
 			host->dma = dma_request_channel(mask, filter, host);
 		}
 	}
-	if (host->dma)
+	if (!IS_ERR(host->dma))
 		mmc->max_seg_size = dma_get_max_seg_size(
 				host->dma->device->dev);
-	else
+	else {
+		host->dma = NULL;
 		dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
+	}
 
 	INIT_WORK(&host->datawork, mxcmci_datawork);
 
diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
index e1fa3ef735e0..f5411a6001fa 100644
--- a/drivers/mmc/host/mxs-mmc.c
+++ b/drivers/mmc/host/mxs-mmc.c
@@ -636,7 +636,8 @@ static int mxs_mmc_probe(struct platform_device *pdev)
 	}
 
 	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
-	if (!ssp->dmach) {
+	if (IS_ERR(ssp->dmach)) {
+		ssp->dmach = NULL;
 		dev_err(mmc_dev(host->mmc),
 			"%s: failed to request dma\n", __func__);
 		ret = -ENODEV;
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index 59ab0692f0b9..fbe1f372faca 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -564,7 +564,7 @@ static int acquire_dma_channels(struct gpmi_nand_data *this)
 
 	/* request dma channel */
 	dma_chan = dma_request_slave_channel(&pdev->dev, "rx-tx");
-	if (!dma_chan) {
+	if (IS_ERR(dma_chan)) {
 		pr_err("Failed to request DMA channel.\n");
 		goto acquire_err;
 	}
diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index de7b1141b90f..7a3ebe87b106 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -552,7 +552,8 @@ static int mxs_spi_probe(struct platform_device *pdev)
 		goto out_master_free;
 
 	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
-	if (!ssp->dmach) {
+	if (IS_ERR(ssp->dmach)) {
+		ssp->dmach = NULL;
 		dev_err(ssp->dev, "Failed to request DMA\n");
 		ret = -ENODEV;
 		goto out_master_free;
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index 9c511a954d21..38d4121f7073 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -1140,11 +1140,11 @@ static int pl022_dma_autoprobe(struct pl022 *pl022)
 
 	/* automatically configure DMA channels from platform, normally using DT */
 	pl022->dma_rx_channel = dma_request_slave_channel(dev, "rx");
-	if (!pl022->dma_rx_channel)
+	if (IS_ERR(pl022->dma_rx_channel))
 		goto err_no_rxchan;
 
 	pl022->dma_tx_channel = dma_request_slave_channel(dev, "tx");
-	if (!pl022->dma_tx_channel)
+	if (IS_ERR(pl022->dma_tx_channel))
 		goto err_no_txchan;
 
 	pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
@@ -1155,11 +1155,11 @@ static int pl022_dma_autoprobe(struct pl022 *pl022)
 
 err_no_dummypage:
 	dma_release_channel(pl022->dma_tx_channel);
-	pl022->dma_tx_channel = NULL;
 err_no_txchan:
+	pl022->dma_tx_channel = NULL;
 	dma_release_channel(pl022->dma_rx_channel);
-	pl022->dma_rx_channel = NULL;
 err_no_rxchan:
+	pl022->dma_rx_channel = NULL;
 	return -ENODEV;
 }
 		
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index aaa22867e656..c0f400c3c954 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -278,7 +278,7 @@ static void pl011_dma_probe_initcall(struct device *dev, struct uart_amba_port *
 
 	chan = dma_request_slave_channel(dev, "tx");
 
-	if (!chan) {
+	if (IS_ERR(chan)) {
 		/* We need platform data */
 		if (!plat || !plat->dma_filter) {
 			dev_info(uap->port.dev, "no DMA platform data\n");
@@ -305,8 +305,10 @@ static void pl011_dma_probe_initcall(struct device *dev, struct uart_amba_port *
 
 	/* Optionally make use of an RX channel as well */
 	chan = dma_request_slave_channel(dev, "rx");
+	if (IS_ERR(chan))
+		chan = NULL;
 	
-	if (!chan && plat->dma_rx_param) {
+	if (chan && plat->dma_rx_param) {
 		chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
 
 		if (!chan) {
diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index d067285a2d20..c0ae083e061c 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -723,8 +723,10 @@ static int atmel_prepare_tx_dma(struct uart_port *port)
 	dma_cap_set(DMA_SLAVE, mask);
 
 	atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
-	if (atmel_port->chan_tx == NULL)
+	if (IS_ERR(atmel_port->chan_tx)) {
+		atmel_port->chan_tx = NULL;
 		goto chan_err;
+	}
 	dev_info(port->dev, "using %s for tx DMA transfers\n",
 		dma_chan_name(atmel_port->chan_tx));
 
@@ -890,8 +892,10 @@ static int atmel_prepare_rx_dma(struct uart_port *port)
 	dma_cap_set(DMA_CYCLIC, mask);
 
 	atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
-	if (atmel_port->chan_rx == NULL)
+	if (IS_ERR(atmel_port->chan_rx)) {
+		atmel_port->chan_rx = NULL;
 		goto chan_err;
+	}
 	dev_info(port->dev, "using %s for rx DMA transfers\n",
 		dma_chan_name(atmel_port->chan_rx));
 
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 042aa077b5b3..1e4cb60ce0af 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -985,7 +985,8 @@ static int imx_uart_dma_init(struct imx_port *sport)
 
 	/* Prepare for RX : */
 	sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
-	if (!sport->dma_chan_rx) {
+	if (IS_ERR(sport->dma_chan_rx)) {
+		sport->dma_chan_rx = NULL;
 		dev_dbg(dev, "cannot get the DMA channel.\n");
 		ret = -EINVAL;
 		goto err;
@@ -1011,7 +1012,8 @@ static int imx_uart_dma_init(struct imx_port *sport)
 
 	/* Prepare for TX : */
 	sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
-	if (!sport->dma_chan_tx) {
+	if (IS_ERR(sport->dma_chan_tx)) {
+		sport->dma_chan_tx = NULL;
 		dev_err(dev, "cannot get the TX DMA channel!\n");
 		ret = -EINVAL;
 		goto err;
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
index 10e9d70b5c40..cc9747ab71cd 100644
--- a/drivers/tty/serial/mxs-auart.c
+++ b/drivers/tty/serial/mxs-auart.c
@@ -530,16 +530,20 @@ static int mxs_auart_dma_init(struct mxs_auart_port *s)
 
 	/* init for RX */
 	s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx");
-	if (!s->rx_dma_chan)
+	if (IS_ERR(s->rx_dma_chan)) {
+		s->rx_dma_chan = NULL;
 		goto err_out;
+	}
 	s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
 	if (!s->rx_dma_buf)
 		goto err_out;
 
 	/* init for TX */
 	s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx");
-	if (!s->tx_dma_chan)
+	if (IS_ERR(s->tx_dma_chan)) {
+		s->tx_dma_chan = NULL;
 		goto err_out;
+	}
 	s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
 	if (!s->tx_dma_buf)
 		goto err_out;
diff --git a/drivers/usb/musb/musb_cppi41.c b/drivers/usb/musb/musb_cppi41.c
index ff9d6de2b746..b71c5f138968 100644
--- a/drivers/usb/musb/musb_cppi41.c
+++ b/drivers/usb/musb/musb_cppi41.c
@@ -502,7 +502,7 @@ static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller)
 		musb_dma->max_len = SZ_4M;
 
 		dc = dma_request_slave_channel(dev, str);
-		if (!dc) {
+		if (IS_ERR(dc)) {
 			dev_err(dev, "Falied to request %s.\n", str);
 			ret = -EPROBE_DEFER;
 			goto err;
diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c
index 3700e9713258..6c863b90ad66 100644
--- a/drivers/usb/musb/ux500_dma.c
+++ b/drivers/usb/musb/ux500_dma.c
@@ -330,13 +330,14 @@ static int ux500_dma_controller_start(struct ux500_dma_controller *controller)
 			ux500_channel->dma_chan =
 				dma_request_slave_channel(dev, chan_names[ch_num]);
 
-			if (!ux500_channel->dma_chan)
+			if (IS_ERR(ux500_channel->dma_chan)) {
 				ux500_channel->dma_chan =
 					dma_request_channel(mask,
 							    data ?
 							    data->dma_filter :
 							    NULL,
 							    param_array[ch_num]);
+			}
 
 			if (!ux500_channel->dma_chan) {
 				ERR("Dma pipe allocation error dir=%d ch=%d\n",
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 0bc727534108..0da9425d64e7 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -1056,7 +1056,7 @@ static inline struct dma_chan
 	struct dma_chan *chan;
 
 	chan = dma_request_slave_channel(dev, name);
-	if (chan)
+	if (!IS_ERR(chan))
 		return chan;
 
 	return __dma_request_channel(mask, fn, fn_param);
diff --git a/sound/soc/omap/omap-pcm.c b/sound/soc/omap/omap-pcm.c
index a11405de86e8..56c3056cdac7 100644
--- a/sound/soc/omap/omap-pcm.c
+++ b/sound/soc/omap/omap-pcm.c
@@ -125,7 +125,7 @@ static int omap_pcm_open(struct snd_pcm_substream *substream)
 
 		chan = dma_request_slave_channel(rtd->cpu_dai->dev,
 						 dma_data->filter_data);
-		ret = snd_dmaengine_pcm_open(substream, chan);
+		ret = snd_dmaengine_pcm_open(substream, IS_ERR(chan) ? NULL : chan);
 	} else {
 		ret = snd_dmaengine_pcm_open_request_chan(substream,
 							  omap_dma_filter_fn,
diff --git a/sound/soc/soc-generic-dmaengine-pcm.c b/sound/soc/soc-generic-dmaengine-pcm.c
index e29ec3cd84b1..4182b203fad5 100644
--- a/sound/soc/soc-generic-dmaengine-pcm.c
+++ b/sound/soc/soc-generic-dmaengine-pcm.c
@@ -227,11 +227,15 @@ static void dmaengine_pcm_request_chan_of(struct dmaengine_pcm *pcm,
 
 	if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX) {
 		pcm->chan[0] = dma_request_slave_channel(dev, "rx-tx");
+		if (IS_ERR(pcm->chan[0]))
+			pcm->chan[0] = NULL;
 		pcm->chan[1] = pcm->chan[0];
 	} else {
 		for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE; i++) {
 			pcm->chan[i] = dma_request_slave_channel(dev,
 					dmaengine_pcm_dma_channel_names[i]);
+			if (IS_ERR(pcm->chan[i]))
+				pcm->chan[i] = NULL;
 		}
 	}
 }

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/20/2013 01:23 PM, Williams, Dan J wrote:
...
> Why do the drivers that call dma_request_channel need to convert it to
> an ERR value?  i.e. what's problematic about the below (not compile
> tested)?
...
> diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
...
> @@ -22,16 +22,20 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
>  				struct samsung_dma_req *param,
>  				struct device *dev, char *ch_name)
...
> +	if (dev->of_node) {
> +		chan = dma_request_slave_channel(dev, ch_name);
> +		return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
> +	} else {
>  		return (unsigned)dma_request_channel(mask, pl330_filter,
>  							(void *)dma_ch);
> +	}

The argument is that if a function returns errors encoded as an ERR
pointer, then callers must assume that any non-IS_ERR value that the
function returns is valid. NULL is one of those values. As such, callers
can no longer check the value against NULL, but must use IS_ERR().
Converting any IS_ERR() returns to NULL theoretically is the act of
converting one valid return value to some other completely random return
value.

The converse is true for functions that return errors encoded as NULL;
callers must check those return results against NULL.

There's no intersection between those two sets of legal tests.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/20/2013 01:23 PM, Williams, Dan J wrote:
...
> Why do the drivers that call dma_request_channel need to convert it to
> an ERR value?  i.e. what's problematic about the below (not compile
> tested)?
...
> diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
...
> @@ -22,16 +22,20 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
>  				struct samsung_dma_req *param,
>  				struct device *dev, char *ch_name)
...
> +	if (dev->of_node) {
> +		chan = dma_request_slave_channel(dev, ch_name);
> +		return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
> +	} else {
>  		return (unsigned)dma_request_channel(mask, pl330_filter,
>  							(void *)dma_ch);
> +	}

The argument is that if a function returns errors encoded as an ERR
pointer, then callers must assume that any non-IS_ERR value that the
function returns is valid. NULL is one of those values. As such, callers
can no longer check the value against NULL, but must use IS_ERR().
Converting any IS_ERR() returns to NULL theoretically is the act of
converting one valid return value to some other completely random return
value.

The converse is true for functions that return errors encoded as NULL;
callers must check those return results against NULL.

There's no intersection between those two sets of legal tests.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Wed, Nov 20, 2013 at 1:24 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> On 11/20/2013 01:23 PM, Williams, Dan J wrote:
> ...
>> Why do the drivers that call dma_request_channel need to convert it to
>> an ERR value?  i.e. what's problematic about the below (not compile
>> tested)?
> ...
>> diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
> ...
>> @@ -22,16 +22,20 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
>>                               struct samsung_dma_req *param,
>>                               struct device *dev, char *ch_name)
> ...
>> +     if (dev->of_node) {
>> +             chan = dma_request_slave_channel(dev, ch_name);
>> +             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
>> +     } else {
>>               return (unsigned)dma_request_channel(mask, pl330_filter,
>>                                                       (void *)dma_ch);
>> +     }
>
> The argument is that if a function returns errors encoded as an ERR
> pointer, then callers must assume that any non-IS_ERR value that the
> function returns is valid. NULL is one of those values. As such, callers
> can no longer check the value against NULL, but must use IS_ERR().
> Converting any IS_ERR() returns to NULL theoretically is the act of
> converting one valid return value to some other completely random return
> value.

You describe how IS_ERR() works, but you didn't address the patch.
There's nothing random about the changes to samsung_dmadev_request().
It still returns NULL or a valid channel just as before.

> The converse is true for functions that return errors encoded as NULL;
> callers must check those return results against NULL.
>
> There's no intersection between those two sets of legal tests.

I don't understand what you are trying to say.  I'm not proposing an
intersection.  I'm proposing that clients explicitly handle an updated
dma_request_slave_channel and we skip this interim
dma_request_slave_channel_no_err step.

Proliferating yet another *request_channel* api is worse than just
having clients understand that dma_request_slave_channel now encodes
errors while dma_request_slave_channel_compat and dma_request_channel
still just return NULL.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Wed, Nov 20, 2013 at 1:24 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 11/20/2013 01:23 PM, Williams, Dan J wrote:
> ...
>> Why do the drivers that call dma_request_channel need to convert it to
>> an ERR value?  i.e. what's problematic about the below (not compile
>> tested)?
> ...
>> diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
> ...
>> @@ -22,16 +22,20 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
>>                               struct samsung_dma_req *param,
>>                               struct device *dev, char *ch_name)
> ...
>> +     if (dev->of_node) {
>> +             chan = dma_request_slave_channel(dev, ch_name);
>> +             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
>> +     } else {
>>               return (unsigned)dma_request_channel(mask, pl330_filter,
>>                                                       (void *)dma_ch);
>> +     }
>
> The argument is that if a function returns errors encoded as an ERR
> pointer, then callers must assume that any non-IS_ERR value that the
> function returns is valid. NULL is one of those values. As such, callers
> can no longer check the value against NULL, but must use IS_ERR().
> Converting any IS_ERR() returns to NULL theoretically is the act of
> converting one valid return value to some other completely random return
> value.

You describe how IS_ERR() works, but you didn't address the patch.
There's nothing random about the changes to samsung_dmadev_request().
It still returns NULL or a valid channel just as before.

> The converse is true for functions that return errors encoded as NULL;
> callers must check those return results against NULL.
>
> There's no intersection between those two sets of legal tests.

I don't understand what you are trying to say.  I'm not proposing an
intersection.  I'm proposing that clients explicitly handle an updated
dma_request_slave_channel and we skip this interim
dma_request_slave_channel_no_err step.

Proliferating yet another *request_channel* api is worse than just
having clients understand that dma_request_slave_channel now encodes
errors while dma_request_slave_channel_compat and dma_request_channel
still just return NULL.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Andy Shevchenko]

On Wed, 2013-11-20 at 19:22 -0800, Dan Williams wrote:
> On Wed, Nov 20, 2013 at 1:24 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:

[]

> I'm proposing that clients explicitly handle an updated
> dma_request_slave_channel and we skip this interim
> dma_request_slave_channel_no_err step.

Actually this makes more sense.

-- 
Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
Intel Finland Oy

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Andy Shevchenko]

On Wed, 2013-11-20 at 19:22 -0800, Dan Williams wrote:
> On Wed, Nov 20, 2013 at 1:24 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:

[]

> I'm proposing that clients explicitly handle an updated
> dma_request_slave_channel and we skip this interim
> dma_request_slave_channel_no_err step.

Actually this makes more sense.

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/20/2013 08:22 PM, Dan Williams wrote:
> On Wed, Nov 20, 2013 at 1:24 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>> On 11/20/2013 01:23 PM, Williams, Dan J wrote:
>> ...
>>> Why do the drivers that call dma_request_channel need to convert it to
>>> an ERR value?  i.e. what's problematic about the below (not compile
>>> tested)?
>> ...
>>> diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
>> ...
>>> @@ -22,16 +22,20 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
>>>                               struct samsung_dma_req *param,
>>>                               struct device *dev, char *ch_name)
>> ...
>>> +     if (dev->of_node) {
>>> +             chan = dma_request_slave_channel(dev, ch_name);
>>> +             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
>>> +     } else {
>>>               return (unsigned)dma_request_channel(mask, pl330_filter,
>>>                                                       (void *)dma_ch);
>>> +     }
>>
>> The argument is that if a function returns errors encoded as an ERR
>> pointer, then callers must assume that any non-IS_ERR value that the
>> function returns is valid. NULL is one of those values. As such, callers
>> can no longer check the value against NULL, but must use IS_ERR().
>> Converting any IS_ERR() returns to NULL theoretically is the act of
>> converting one valid return value to some other completely random return
>> value.
> 
> You describe how IS_ERR() works, but you didn't address the patch.
> There's nothing random about the changes to samsung_dmadev_request().
> It still returns NULL or a valid channel just as before.

I was addressing the patch. I guess I should have explained as follows.

First, the following code is technically buggy:

+             chan = dma_request_slave_channel(dev, ch_name);
+             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;

... since it assumes that dma_request_slave_channel() never returns NULL
as a valid non-error value. This is specifically prohibited by the fact
that dma_request_slave_channel() returns either an ERR value or a valid
value; in that case, NULL is not an ERR value, and hence must be
considered valid.

Also, observe that the following are semantically equivalent:

1)

	/*
	 * This is a demonstration of using IS_ERR_OR_NULL for error
	 * checking. We want to remove use of IS_ERR_OR_NULL though.
	 */
	chan = dma_request_slave_channel(dev, ch_name);
	if (IS_ERR_OR_NULL(chan))
		return -ESOMETHING;

2)

	/* These first 3 lines are part of your patch */
	chan = dma_request_slave_channel(dev, ch_name);
	if (IS_ERR(chan)
		chan = NULL;
	if (!chan) // This test and the above are IS_ERR_OR_NULL
		attempt allocation some other way;
	/*
	 * This is code elsewhere in a driver where DMA is optional;
	 * that code must act differently based on whether a DMA
	 * channel was acquired or not. So, it tests chan against
	 * NULL.
	 */
	if (!chan) // This test and the above IS_ERR are IS_ERR_OR_NULL
		return -ESOMETHING;

In case (2) above, if the driver /only/ calls a modified
dma_request_slave_channel(), all the checks could just be if
(IS_ERR(chan)) instead - then problem solved. However, if the driver
mixes the new dma_request_slave_channel() and the unconverted
dma_request_channel(), it has to either (a) convert an ERR return from
dma_request_slave_channel() to match dma_request_channel()'s NULL error
return, or (b) convert a NULL return from dma_request_channel() to match
dma_request_slave_channel()'s ERR return. Without the conversion, all
tests would have to use the deprecated IS_ERR_OR_NULL. Either of those
conversion options converts an error value from 1 API into a
theoretically valid return value from the other API, which is a bug.

Perhaps one can argue that an API that returns either a valid value or
NULL can never return a value that matches an ERR value? If so, perhaps
the following would work in practice:

if (dev->of_node) {
	chan = dma_request_slave_channel(dev, ch_name);
} else {
	chan = dma_request_channel(mask, pl330_filter,
					(void *)dma_ch);
	if (!chan)
		chan = ERR_PTR(-ENODEV);
}
...
if (IS_ERR(chan))
...

... but I'm not sure whether that assumption is acceptable.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/20/2013 08:22 PM, Dan Williams wrote:
> On Wed, Nov 20, 2013 at 1:24 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> On 11/20/2013 01:23 PM, Williams, Dan J wrote:
>> ...
>>> Why do the drivers that call dma_request_channel need to convert it to
>>> an ERR value?  i.e. what's problematic about the below (not compile
>>> tested)?
>> ...
>>> diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
>> ...
>>> @@ -22,16 +22,20 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
>>>                               struct samsung_dma_req *param,
>>>                               struct device *dev, char *ch_name)
>> ...
>>> +     if (dev->of_node) {
>>> +             chan = dma_request_slave_channel(dev, ch_name);
>>> +             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
>>> +     } else {
>>>               return (unsigned)dma_request_channel(mask, pl330_filter,
>>>                                                       (void *)dma_ch);
>>> +     }
>>
>> The argument is that if a function returns errors encoded as an ERR
>> pointer, then callers must assume that any non-IS_ERR value that the
>> function returns is valid. NULL is one of those values. As such, callers
>> can no longer check the value against NULL, but must use IS_ERR().
>> Converting any IS_ERR() returns to NULL theoretically is the act of
>> converting one valid return value to some other completely random return
>> value.
> 
> You describe how IS_ERR() works, but you didn't address the patch.
> There's nothing random about the changes to samsung_dmadev_request().
> It still returns NULL or a valid channel just as before.

I was addressing the patch. I guess I should have explained as follows.

First, the following code is technically buggy:

+             chan = dma_request_slave_channel(dev, ch_name);
+             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;

... since it assumes that dma_request_slave_channel() never returns NULL
as a valid non-error value. This is specifically prohibited by the fact
that dma_request_slave_channel() returns either an ERR value or a valid
value; in that case, NULL is not an ERR value, and hence must be
considered valid.

Also, observe that the following are semantically equivalent:

1)

	/*
	 * This is a demonstration of using IS_ERR_OR_NULL for error
	 * checking. We want to remove use of IS_ERR_OR_NULL though.
	 */
	chan = dma_request_slave_channel(dev, ch_name);
	if (IS_ERR_OR_NULL(chan))
		return -ESOMETHING;

2)

	/* These first 3 lines are part of your patch */
	chan = dma_request_slave_channel(dev, ch_name);
	if (IS_ERR(chan)
		chan = NULL;
	if (!chan) // This test and the above are IS_ERR_OR_NULL
		attempt allocation some other way;
	/*
	 * This is code elsewhere in a driver where DMA is optional;
	 * that code must act differently based on whether a DMA
	 * channel was acquired or not. So, it tests chan against
	 * NULL.
	 */
	if (!chan) // This test and the above IS_ERR are IS_ERR_OR_NULL
		return -ESOMETHING;

In case (2) above, if the driver /only/ calls a modified
dma_request_slave_channel(), all the checks could just be if
(IS_ERR(chan)) instead - then problem solved. However, if the driver
mixes the new dma_request_slave_channel() and the unconverted
dma_request_channel(), it has to either (a) convert an ERR return from
dma_request_slave_channel() to match dma_request_channel()'s NULL error
return, or (b) convert a NULL return from dma_request_channel() to match
dma_request_slave_channel()'s ERR return. Without the conversion, all
tests would have to use the deprecated IS_ERR_OR_NULL. Either of those
conversion options converts an error value from 1 API into a
theoretically valid return value from the other API, which is a bug.

Perhaps one can argue that an API that returns either a valid value or
NULL can never return a value that matches an ERR value? If so, perhaps
the following would work in practice:

if (dev->of_node) {
	chan = dma_request_slave_channel(dev, ch_name);
} else {
	chan = dma_request_channel(mask, pl330_filter,
					(void *)dma_ch);
	if (!chan)
		chan = ERR_PTR(-ENODEV);
}
...
if (IS_ERR(chan))
...

... but I'm not sure whether that assumption is acceptable.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Thu, Nov 21, 2013 at 10:22 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> On 11/20/2013 08:22 PM, Dan Williams wrote:
>> On Wed, Nov 20, 2013 at 1:24 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>>> On 11/20/2013 01:23 PM, Williams, Dan J wrote:
>>> ...
>>>> Why do the drivers that call dma_request_channel need to convert it to
>>>> an ERR value?  i.e. what's problematic about the below (not compile
>>>> tested)?
>>> ...
>>>> diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
>>> ...
>>>> @@ -22,16 +22,20 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
>>>>                               struct samsung_dma_req *param,
>>>>                               struct device *dev, char *ch_name)
>>> ...
>>>> +     if (dev->of_node) {
>>>> +             chan = dma_request_slave_channel(dev, ch_name);
>>>> +             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
>>>> +     } else {
>>>>               return (unsigned)dma_request_channel(mask, pl330_filter,
>>>>                                                       (void *)dma_ch);
>>>> +     }
>>>
>>> The argument is that if a function returns errors encoded as an ERR
>>> pointer, then callers must assume that any non-IS_ERR value that the
>>> function returns is valid. NULL is one of those values. As such, callers
>>> can no longer check the value against NULL, but must use IS_ERR().
>>> Converting any IS_ERR() returns to NULL theoretically is the act of
>>> converting one valid return value to some other completely random return
>>> value.
>>
>> You describe how IS_ERR() works, but you didn't address the patch.
>> There's nothing random about the changes to samsung_dmadev_request().
>> It still returns NULL or a valid channel just as before.
>
> I was addressing the patch. I guess I should have explained as follows.
>
> First, the following code is technically buggy:

No, it's not, but I think we have different implementations in mind.

>
> +             chan = dma_request_slave_channel(dev, ch_name);
> +             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
>
> ... since it assumes that dma_request_slave_channel() never returns NULL
> as a valid non-error value. This is specifically prohibited by the fact
> that dma_request_slave_channel() returns either an ERR value or a valid
> value; in that case, NULL is not an ERR value, and hence must be
> considered valid.

Let's stop there and be clear we are talking about the same proposal.

The proposal is dma_request_slave_channel only returns errors or valid
pointers, never NULL.

diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
index 9162ac80c18f..64c163664b9d 100644
--- a/drivers/dma/dmaengine.c
+++ b/drivers/dma/dmaengine.c
@@ -593,15 +593,20 @@ EXPORT_SYMBOL_GPL(__dma_request_channel);
  */
 struct dma_chan *dma_request_slave_channel(struct device *dev, const
char *name)
 {
+       struct dma_chan *chan = ERR_PTR(-ENODEV);
+
        /* If device-tree is present get slave info from here */
        if (dev->of_node)
                return of_dma_request_slave_channel(dev->of_node, name);

        /* If device was enumerated by ACPI get slave info from here */
-       if (ACPI_HANDLE(dev))
-               return acpi_dma_request_slave_chan_by_name(dev, name);
+       if (ACPI_HANDLE(dev)) {
+               chan = acpi_dma_request_slave_chan_by_name(dev, name);
+               if (!chan)
+                       chan = ERR_PTR(-ENODEV);
+       }

-       return NULL;
+       return chan;
 }

In the above the assumption is that of_dma_request_slave_channel() is
modified to guarantee it only returns ERR_PTRs or valid pointers never
NULL.  acpi_dma_request_slave_chan_by_name() can continue returning
NULL and dma_request_slave_channel will translate it to an ERR_PTR, or
you can convert it as you do in your patch.  Not much value in
converting acpi_dma_request_slave_chan_by_name as it does not return
EPROBE_DEFER and nothing currently cares about the other error values.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Thu, Nov 21, 2013 at 10:22 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 11/20/2013 08:22 PM, Dan Williams wrote:
>> On Wed, Nov 20, 2013 at 1:24 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>> On 11/20/2013 01:23 PM, Williams, Dan J wrote:
>>> ...
>>>> Why do the drivers that call dma_request_channel need to convert it to
>>>> an ERR value?  i.e. what's problematic about the below (not compile
>>>> tested)?
>>> ...
>>>> diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
>>> ...
>>>> @@ -22,16 +22,20 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
>>>>                               struct samsung_dma_req *param,
>>>>                               struct device *dev, char *ch_name)
>>> ...
>>>> +     if (dev->of_node) {
>>>> +             chan = dma_request_slave_channel(dev, ch_name);
>>>> +             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
>>>> +     } else {
>>>>               return (unsigned)dma_request_channel(mask, pl330_filter,
>>>>                                                       (void *)dma_ch);
>>>> +     }
>>>
>>> The argument is that if a function returns errors encoded as an ERR
>>> pointer, then callers must assume that any non-IS_ERR value that the
>>> function returns is valid. NULL is one of those values. As such, callers
>>> can no longer check the value against NULL, but must use IS_ERR().
>>> Converting any IS_ERR() returns to NULL theoretically is the act of
>>> converting one valid return value to some other completely random return
>>> value.
>>
>> You describe how IS_ERR() works, but you didn't address the patch.
>> There's nothing random about the changes to samsung_dmadev_request().
>> It still returns NULL or a valid channel just as before.
>
> I was addressing the patch. I guess I should have explained as follows.
>
> First, the following code is technically buggy:

No, it's not, but I think we have different implementations in mind.

>
> +             chan = dma_request_slave_channel(dev, ch_name);
> +             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
>
> ... since it assumes that dma_request_slave_channel() never returns NULL
> as a valid non-error value. This is specifically prohibited by the fact
> that dma_request_slave_channel() returns either an ERR value or a valid
> value; in that case, NULL is not an ERR value, and hence must be
> considered valid.

Let's stop there and be clear we are talking about the same proposal.

The proposal is dma_request_slave_channel only returns errors or valid
pointers, never NULL.

diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
index 9162ac80c18f..64c163664b9d 100644
--- a/drivers/dma/dmaengine.c
+++ b/drivers/dma/dmaengine.c
@@ -593,15 +593,20 @@ EXPORT_SYMBOL_GPL(__dma_request_channel);
  */
 struct dma_chan *dma_request_slave_channel(struct device *dev, const
char *name)
 {
+       struct dma_chan *chan = ERR_PTR(-ENODEV);
+
        /* If device-tree is present get slave info from here */
        if (dev->of_node)
                return of_dma_request_slave_channel(dev->of_node, name);

        /* If device was enumerated by ACPI get slave info from here */
-       if (ACPI_HANDLE(dev))
-               return acpi_dma_request_slave_chan_by_name(dev, name);
+       if (ACPI_HANDLE(dev)) {
+               chan = acpi_dma_request_slave_chan_by_name(dev, name);
+               if (!chan)
+                       chan = ERR_PTR(-ENODEV);
+       }

-       return NULL;
+       return chan;
 }

In the above the assumption is that of_dma_request_slave_channel() is
modified to guarantee it only returns ERR_PTRs or valid pointers never
NULL.  acpi_dma_request_slave_chan_by_name() can continue returning
NULL and dma_request_slave_channel will translate it to an ERR_PTR, or
you can convert it as you do in your patch.  Not much value in
converting acpi_dma_request_slave_chan_by_name as it does not return
EPROBE_DEFER and nothing currently cares about the other error values.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/21/2013 11:54 PM, Dan Williams wrote:
> On Thu, Nov 21, 2013 at 10:22 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>> On 11/20/2013 08:22 PM, Dan Williams wrote:
>>> On Wed, Nov 20, 2013 at 1:24 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>>>> On 11/20/2013 01:23 PM, Williams, Dan J wrote:
>>>> ...
>>>>> Why do the drivers that call dma_request_channel need to convert it to
>>>>> an ERR value?  i.e. what's problematic about the below (not compile
>>>>> tested)?
>>>> ...
>>>>> diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
>>>> ...
>>>>> @@ -22,16 +22,20 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
>>>>>                               struct samsung_dma_req *param,
>>>>>                               struct device *dev, char *ch_name)
>>>> ...
>>>>> +     if (dev->of_node) {
>>>>> +             chan = dma_request_slave_channel(dev, ch_name);
>>>>> +             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
>>>>> +     } else {
>>>>>               return (unsigned)dma_request_channel(mask, pl330_filter,
>>>>>                                                       (void *)dma_ch);
>>>>> +     }
>>>>
>>>> The argument is that if a function returns errors encoded as an ERR
>>>> pointer, then callers must assume that any non-IS_ERR value that the
>>>> function returns is valid. NULL is one of those values. As such, callers
>>>> can no longer check the value against NULL, but must use IS_ERR().
>>>> Converting any IS_ERR() returns to NULL theoretically is the act of
>>>> converting one valid return value to some other completely random return
>>>> value.
>>>
>>> You describe how IS_ERR() works, but you didn't address the patch.
>>> There's nothing random about the changes to samsung_dmadev_request().
>>> It still returns NULL or a valid channel just as before.
>>
>> I was addressing the patch. I guess I should have explained as follows.
>>
>> First, the following code is technically buggy:
> 
> No, it's not, but I think we have different implementations in mind.
> 
>>
>> +             chan = dma_request_slave_channel(dev, ch_name);
>> +             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
>>
>> ... since it assumes that dma_request_slave_channel() never returns NULL
>> as a valid non-error value. This is specifically prohibited by the fact
>> that dma_request_slave_channel() returns either an ERR value or a valid
>> value; in that case, NULL is not an ERR value, and hence must be
>> considered valid.
> 
> Let's stop there and be clear we are talking about the same proposal.
> 
> The proposal is dma_request_slave_channel only returns errors or valid
> pointers, never NULL.

OK, so if you make that assumption, I guess it's safe. However, I
believe that's a new class of return value. To date, we have had two
classes:

a) Returns a valid value (which could include NULL), or an ERR value.

b) Returns a valid value (which doesn't include ERR values), or NULL.

You're talking about adding a third class:

c) Returns a valid value (which doesn't include NULL or ERR values), or
an ERR value.

Russell at least has argued in the past that APIs that return ERR values
for errors by definition can return NULL as a valid return value.
However, if we go against that and explicitly define the API the way you
propose, and nobody objects to defining it that way, then yes, that
would work out OK.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/21/2013 11:54 PM, Dan Williams wrote:
> On Thu, Nov 21, 2013 at 10:22 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> On 11/20/2013 08:22 PM, Dan Williams wrote:
>>> On Wed, Nov 20, 2013 at 1:24 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>>> On 11/20/2013 01:23 PM, Williams, Dan J wrote:
>>>> ...
>>>>> Why do the drivers that call dma_request_channel need to convert it to
>>>>> an ERR value?  i.e. what's problematic about the below (not compile
>>>>> tested)?
>>>> ...
>>>>> diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
>>>> ...
>>>>> @@ -22,16 +22,20 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
>>>>>                               struct samsung_dma_req *param,
>>>>>                               struct device *dev, char *ch_name)
>>>> ...
>>>>> +     if (dev->of_node) {
>>>>> +             chan = dma_request_slave_channel(dev, ch_name);
>>>>> +             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
>>>>> +     } else {
>>>>>               return (unsigned)dma_request_channel(mask, pl330_filter,
>>>>>                                                       (void *)dma_ch);
>>>>> +     }
>>>>
>>>> The argument is that if a function returns errors encoded as an ERR
>>>> pointer, then callers must assume that any non-IS_ERR value that the
>>>> function returns is valid. NULL is one of those values. As such, callers
>>>> can no longer check the value against NULL, but must use IS_ERR().
>>>> Converting any IS_ERR() returns to NULL theoretically is the act of
>>>> converting one valid return value to some other completely random return
>>>> value.
>>>
>>> You describe how IS_ERR() works, but you didn't address the patch.
>>> There's nothing random about the changes to samsung_dmadev_request().
>>> It still returns NULL or a valid channel just as before.
>>
>> I was addressing the patch. I guess I should have explained as follows.
>>
>> First, the following code is technically buggy:
> 
> No, it's not, but I think we have different implementations in mind.
> 
>>
>> +             chan = dma_request_slave_channel(dev, ch_name);
>> +             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
>>
>> ... since it assumes that dma_request_slave_channel() never returns NULL
>> as a valid non-error value. This is specifically prohibited by the fact
>> that dma_request_slave_channel() returns either an ERR value or a valid
>> value; in that case, NULL is not an ERR value, and hence must be
>> considered valid.
> 
> Let's stop there and be clear we are talking about the same proposal.
> 
> The proposal is dma_request_slave_channel only returns errors or valid
> pointers, never NULL.

OK, so if you make that assumption, I guess it's safe. However, I
believe that's a new class of return value. To date, we have had two
classes:

a) Returns a valid value (which could include NULL), or an ERR value.

b) Returns a valid value (which doesn't include ERR values), or NULL.

You're talking about adding a third class:

c) Returns a valid value (which doesn't include NULL or ERR values), or
an ERR value.

Russell at least has argued in the past that APIs that return ERR values
for errors by definition can return NULL as a valid return value.
However, if we go against that and explicitly define the API the way you
propose, and nobody objects to defining it that way, then yes, that
would work out OK.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Fri, Nov 22, 2013 at 9:34 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> On 11/21/2013 11:54 PM, Dan Williams wrote:
>> On Thu, Nov 21, 2013 at 10:22 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>>> On 11/20/2013 08:22 PM, Dan Williams wrote:
>>>> On Wed, Nov 20, 2013 at 1:24 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>>>>> On 11/20/2013 01:23 PM, Williams, Dan J wrote:
>>>>> ...
>>>>>> Why do the drivers that call dma_request_channel need to convert it to
>>>>>> an ERR value?  i.e. what's problematic about the below (not compile
>>>>>> tested)?
>>>>> ...
>>>>>> diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
>>>>> ...
>>>>>> @@ -22,16 +22,20 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
>>>>>>                               struct samsung_dma_req *param,
>>>>>>                               struct device *dev, char *ch_name)
>>>>> ...
>>>>>> +     if (dev->of_node) {
>>>>>> +             chan = dma_request_slave_channel(dev, ch_name);
>>>>>> +             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
>>>>>> +     } else {
>>>>>>               return (unsigned)dma_request_channel(mask, pl330_filter,
>>>>>>                                                       (void *)dma_ch);
>>>>>> +     }
>>>>>
>>>>> The argument is that if a function returns errors encoded as an ERR
>>>>> pointer, then callers must assume that any non-IS_ERR value that the
>>>>> function returns is valid. NULL is one of those values. As such, callers
>>>>> can no longer check the value against NULL, but must use IS_ERR().
>>>>> Converting any IS_ERR() returns to NULL theoretically is the act of
>>>>> converting one valid return value to some other completely random return
>>>>> value.
>>>>
>>>> You describe how IS_ERR() works, but you didn't address the patch.
>>>> There's nothing random about the changes to samsung_dmadev_request().
>>>> It still returns NULL or a valid channel just as before.
>>>
>>> I was addressing the patch. I guess I should have explained as follows.
>>>
>>> First, the following code is technically buggy:
>>
>> No, it's not, but I think we have different implementations in mind.
>>
>>>
>>> +             chan = dma_request_slave_channel(dev, ch_name);
>>> +             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
>>>
>>> ... since it assumes that dma_request_slave_channel() never returns NULL
>>> as a valid non-error value. This is specifically prohibited by the fact
>>> that dma_request_slave_channel() returns either an ERR value or a valid
>>> value; in that case, NULL is not an ERR value, and hence must be
>>> considered valid.
>>
>> Let's stop there and be clear we are talking about the same proposal.
>>
>> The proposal is dma_request_slave_channel only returns errors or valid
>> pointers, never NULL.
>
> OK, so if you make that assumption, I guess it's safe.

I made that assumption because that is what your original patch proposed:

+/**
+ * dma_request_slave_channel_or_err - try to allocate an exclusive
slave channel
+ * @dev:       pointer to client device structure
+ * @name:      slave channel name
+ *
+ * Returns pointer to appropriate dma channel on success or an error pointer.
+ */

What's the benefit of leaking NULL values to callers?  If they already
need to check for err, why force them to check for NULL too?

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Fri, Nov 22, 2013 at 9:34 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 11/21/2013 11:54 PM, Dan Williams wrote:
>> On Thu, Nov 21, 2013 at 10:22 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>> On 11/20/2013 08:22 PM, Dan Williams wrote:
>>>> On Wed, Nov 20, 2013 at 1:24 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>>>> On 11/20/2013 01:23 PM, Williams, Dan J wrote:
>>>>> ...
>>>>>> Why do the drivers that call dma_request_channel need to convert it to
>>>>>> an ERR value?  i.e. what's problematic about the below (not compile
>>>>>> tested)?
>>>>> ...
>>>>>> diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
>>>>> ...
>>>>>> @@ -22,16 +22,20 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
>>>>>>                               struct samsung_dma_req *param,
>>>>>>                               struct device *dev, char *ch_name)
>>>>> ...
>>>>>> +     if (dev->of_node) {
>>>>>> +             chan = dma_request_slave_channel(dev, ch_name);
>>>>>> +             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
>>>>>> +     } else {
>>>>>>               return (unsigned)dma_request_channel(mask, pl330_filter,
>>>>>>                                                       (void *)dma_ch);
>>>>>> +     }
>>>>>
>>>>> The argument is that if a function returns errors encoded as an ERR
>>>>> pointer, then callers must assume that any non-IS_ERR value that the
>>>>> function returns is valid. NULL is one of those values. As such, callers
>>>>> can no longer check the value against NULL, but must use IS_ERR().
>>>>> Converting any IS_ERR() returns to NULL theoretically is the act of
>>>>> converting one valid return value to some other completely random return
>>>>> value.
>>>>
>>>> You describe how IS_ERR() works, but you didn't address the patch.
>>>> There's nothing random about the changes to samsung_dmadev_request().
>>>> It still returns NULL or a valid channel just as before.
>>>
>>> I was addressing the patch. I guess I should have explained as follows.
>>>
>>> First, the following code is technically buggy:
>>
>> No, it's not, but I think we have different implementations in mind.
>>
>>>
>>> +             chan = dma_request_slave_channel(dev, ch_name);
>>> +             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
>>>
>>> ... since it assumes that dma_request_slave_channel() never returns NULL
>>> as a valid non-error value. This is specifically prohibited by the fact
>>> that dma_request_slave_channel() returns either an ERR value or a valid
>>> value; in that case, NULL is not an ERR value, and hence must be
>>> considered valid.
>>
>> Let's stop there and be clear we are talking about the same proposal.
>>
>> The proposal is dma_request_slave_channel only returns errors or valid
>> pointers, never NULL.
>
> OK, so if you make that assumption, I guess it's safe.

I made that assumption because that is what your original patch proposed:

+/**
+ * dma_request_slave_channel_or_err - try to allocate an exclusive
slave channel
+ * @dev:       pointer to client device structure
+ * @name:      slave channel name
+ *
+ * Returns pointer to appropriate dma channel on success or an error pointer.
+ */

What's the benefit of leaking NULL values to callers?  If they already
need to check for err, why force them to check for NULL too?

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/22/2013 11:04 AM, Dan Williams wrote:
> On Fri, Nov 22, 2013 at 9:34 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>> On 11/21/2013 11:54 PM, Dan Williams wrote:
>>> On Thu, Nov 21, 2013 at 10:22 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>>>> On 11/20/2013 08:22 PM, Dan Williams wrote:
>>>>> On Wed, Nov 20, 2013 at 1:24 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>>>>>> On 11/20/2013 01:23 PM, Williams, Dan J wrote:
>>>>>> ...
>>>>>>> Why do the drivers that call dma_request_channel need to convert it to
>>>>>>> an ERR value?  i.e. what's problematic about the below (not compile
>>>>>>> tested)?
>>>>>> ...
>>>>>>> diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
>>>>>> ...
>>>>>>> @@ -22,16 +22,20 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
>>>>>>>                               struct samsung_dma_req *param,
>>>>>>>                               struct device *dev, char *ch_name)
>>>>>> ...
>>>>>>> +     if (dev->of_node) {
>>>>>>> +             chan = dma_request_slave_channel(dev, ch_name);
>>>>>>> +             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
>>>>>>> +     } else {
>>>>>>>               return (unsigned)dma_request_channel(mask, pl330_filter,
>>>>>>>                                                       (void *)dma_ch);
>>>>>>> +     }
>>>>>>
>>>>>> The argument is that if a function returns errors encoded as an ERR
>>>>>> pointer, then callers must assume that any non-IS_ERR value that the
>>>>>> function returns is valid. NULL is one of those values. As such, callers
>>>>>> can no longer check the value against NULL, but must use IS_ERR().
>>>>>> Converting any IS_ERR() returns to NULL theoretically is the act of
>>>>>> converting one valid return value to some other completely random return
>>>>>> value.
>>>>>
>>>>> You describe how IS_ERR() works, but you didn't address the patch.
>>>>> There's nothing random about the changes to samsung_dmadev_request().
>>>>> It still returns NULL or a valid channel just as before.
>>>>
>>>> I was addressing the patch. I guess I should have explained as follows.
>>>>
>>>> First, the following code is technically buggy:
>>>
>>> No, it's not, but I think we have different implementations in mind.
>>>
>>>>
>>>> +             chan = dma_request_slave_channel(dev, ch_name);
>>>> +             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
>>>>
>>>> ... since it assumes that dma_request_slave_channel() never returns NULL
>>>> as a valid non-error value. This is specifically prohibited by the fact
>>>> that dma_request_slave_channel() returns either an ERR value or a valid
>>>> value; in that case, NULL is not an ERR value, and hence must be
>>>> considered valid.
>>>
>>> Let's stop there and be clear we are talking about the same proposal.
>>>
>>> The proposal is dma_request_slave_channel only returns errors or valid
>>> pointers, never NULL.
>>
>> OK, so if you make that assumption, I guess it's safe.
> 
> I made that assumption because that is what your original patch proposed:
> 
> +/**
> + * dma_request_slave_channel_or_err - try to allocate an exclusive
> slave channel
> + * @dev:       pointer to client device structure
> + * @name:      slave channel name
> + *
> + * Returns pointer to appropriate dma channel on success or an error pointer.
> + */
> 
> What's the benefit of leaking NULL values to callers?  If they already
> need to check for err, why force them to check for NULL too?

"Returns pointer to appropriate dma channel on success or an error
pointer." means that callers only have to check for an ERR value. If the
function returns NULL, then other DMA-related functions must treat that
as a valid channel ID. This is case (a) in my previous email.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/22/2013 11:04 AM, Dan Williams wrote:
> On Fri, Nov 22, 2013 at 9:34 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> On 11/21/2013 11:54 PM, Dan Williams wrote:
>>> On Thu, Nov 21, 2013 at 10:22 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>>> On 11/20/2013 08:22 PM, Dan Williams wrote:
>>>>> On Wed, Nov 20, 2013 at 1:24 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>>>>> On 11/20/2013 01:23 PM, Williams, Dan J wrote:
>>>>>> ...
>>>>>>> Why do the drivers that call dma_request_channel need to convert it to
>>>>>>> an ERR value?  i.e. what's problematic about the below (not compile
>>>>>>> tested)?
>>>>>> ...
>>>>>>> diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
>>>>>> ...
>>>>>>> @@ -22,16 +22,20 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
>>>>>>>                               struct samsung_dma_req *param,
>>>>>>>                               struct device *dev, char *ch_name)
>>>>>> ...
>>>>>>> +     if (dev->of_node) {
>>>>>>> +             chan = dma_request_slave_channel(dev, ch_name);
>>>>>>> +             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
>>>>>>> +     } else {
>>>>>>>               return (unsigned)dma_request_channel(mask, pl330_filter,
>>>>>>>                                                       (void *)dma_ch);
>>>>>>> +     }
>>>>>>
>>>>>> The argument is that if a function returns errors encoded as an ERR
>>>>>> pointer, then callers must assume that any non-IS_ERR value that the
>>>>>> function returns is valid. NULL is one of those values. As such, callers
>>>>>> can no longer check the value against NULL, but must use IS_ERR().
>>>>>> Converting any IS_ERR() returns to NULL theoretically is the act of
>>>>>> converting one valid return value to some other completely random return
>>>>>> value.
>>>>>
>>>>> You describe how IS_ERR() works, but you didn't address the patch.
>>>>> There's nothing random about the changes to samsung_dmadev_request().
>>>>> It still returns NULL or a valid channel just as before.
>>>>
>>>> I was addressing the patch. I guess I should have explained as follows.
>>>>
>>>> First, the following code is technically buggy:
>>>
>>> No, it's not, but I think we have different implementations in mind.
>>>
>>>>
>>>> +             chan = dma_request_slave_channel(dev, ch_name);
>>>> +             return IS_ERR(chan) ? (unsigned) NULL : (unsigned) chan;
>>>>
>>>> ... since it assumes that dma_request_slave_channel() never returns NULL
>>>> as a valid non-error value. This is specifically prohibited by the fact
>>>> that dma_request_slave_channel() returns either an ERR value or a valid
>>>> value; in that case, NULL is not an ERR value, and hence must be
>>>> considered valid.
>>>
>>> Let's stop there and be clear we are talking about the same proposal.
>>>
>>> The proposal is dma_request_slave_channel only returns errors or valid
>>> pointers, never NULL.
>>
>> OK, so if you make that assumption, I guess it's safe.
> 
> I made that assumption because that is what your original patch proposed:
> 
> +/**
> + * dma_request_slave_channel_or_err - try to allocate an exclusive
> slave channel
> + * @dev:       pointer to client device structure
> + * @name:      slave channel name
> + *
> + * Returns pointer to appropriate dma channel on success or an error pointer.
> + */
> 
> What's the benefit of leaking NULL values to callers?  If they already
> need to check for err, why force them to check for NULL too?

"Returns pointer to appropriate dma channel on success or an error
pointer." means that callers only have to check for an ERR value. If the
function returns NULL, then other DMA-related functions must treat that
as a valid channel ID. This is case (a) in my previous email.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Fri, Nov 22, 2013 at 10:10 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>>>> The proposal is dma_request_slave_channel only returns errors or valid
>>>> pointers, never NULL.
>>>
>>> OK, so if you make that assumption, I guess it's safe.
>>
>> I made that assumption because that is what your original patch proposed:
>>
>> +/**
>> + * dma_request_slave_channel_or_err - try to allocate an exclusive
>> slave channel
>> + * @dev:       pointer to client device structure
>> + * @name:      slave channel name
>> + *
>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>> + */
>>
>> What's the benefit of leaking NULL values to callers?  If they already
>> need to check for err, why force them to check for NULL too?
>
> "Returns pointer to appropriate dma channel on success or an error
> pointer." means that callers only have to check for an ERR value. If the
> function returns NULL, then other DMA-related functions must treat that
> as a valid channel ID. This is case (a) in my previous email.

How can a channel be "valid" and NULL at the same time?  Without the
guarantee that dma_request_channel always returns a non-null-channel
pointer or an error pointer you're forcing clients to use or open-code
IS_ERR_OR_NULL.  Make the caller's life easier and just turn success
or failure like before.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Fri, Nov 22, 2013 at 10:10 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>>> The proposal is dma_request_slave_channel only returns errors or valid
>>>> pointers, never NULL.
>>>
>>> OK, so if you make that assumption, I guess it's safe.
>>
>> I made that assumption because that is what your original patch proposed:
>>
>> +/**
>> + * dma_request_slave_channel_or_err - try to allocate an exclusive
>> slave channel
>> + * @dev:       pointer to client device structure
>> + * @name:      slave channel name
>> + *
>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>> + */
>>
>> What's the benefit of leaking NULL values to callers?  If they already
>> need to check for err, why force them to check for NULL too?
>
> "Returns pointer to appropriate dma channel on success or an error
> pointer." means that callers only have to check for an ERR value. If the
> function returns NULL, then other DMA-related functions must treat that
> as a valid channel ID. This is case (a) in my previous email.

How can a channel be "valid" and NULL at the same time?  Without the
guarantee that dma_request_channel always returns a non-null-channel
pointer or an error pointer you're forcing clients to use or open-code
IS_ERR_OR_NULL.  Make the caller's life easier and just turn success
or failure like before.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/22/2013 12:49 PM, Dan Williams wrote:
> On Fri, Nov 22, 2013 at 10:10 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>>>>> The proposal is dma_request_slave_channel only returns errors or valid
>>>>> pointers, never NULL.
>>>>
>>>> OK, so if you make that assumption, I guess it's safe.
>>>
>>> I made that assumption because that is what your original patch proposed:
>>>
>>> +/**
>>> + * dma_request_slave_channel_or_err - try to allocate an exclusive
>>> slave channel
>>> + * @dev:       pointer to client device structure
>>> + * @name:      slave channel name
>>> + *
>>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>>> + */
>>>
>>> What's the benefit of leaking NULL values to callers?  If they already
>>> need to check for err, why force them to check for NULL too?
>>
>> "Returns pointer to appropriate dma channel on success or an error
>> pointer." means that callers only have to check for an ERR value. If the
>> function returns NULL, then other DMA-related functions must treat that
>> as a valid channel ID. This is case (a) in my previous email.
> 
> How can a channel be "valid" and NULL at the same time?  Without the
> guarantee that dma_request_channel always returns a non-null-channel
> pointer or an error pointer you're forcing clients to use or open-code
> IS_ERR_OR_NULL.

No, callers should just follow the documentation. If all error cases are
indicated by an ERR pointer, then there is no need to check for NULL. In
fact, client must not check anything beyond whether the value is an ERR
value or not. So, there's no need to use IS_ERR_OR_NULL.

It's up to the API to make sure that it returns values that are valid
for other calls to related APIs. If that doesn't include NULL, it won't
return NULL. If it does, it might. But, that's an internal
implementation detail of the API (and associated APIs), not something
that clients should know about.

One situation where a NULL might be valid is where the return value
isn't really a pointer, but an integer index or ID cast to a pointer.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/22/2013 12:49 PM, Dan Williams wrote:
> On Fri, Nov 22, 2013 at 10:10 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>>>> The proposal is dma_request_slave_channel only returns errors or valid
>>>>> pointers, never NULL.
>>>>
>>>> OK, so if you make that assumption, I guess it's safe.
>>>
>>> I made that assumption because that is what your original patch proposed:
>>>
>>> +/**
>>> + * dma_request_slave_channel_or_err - try to allocate an exclusive
>>> slave channel
>>> + * @dev:       pointer to client device structure
>>> + * @name:      slave channel name
>>> + *
>>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>>> + */
>>>
>>> What's the benefit of leaking NULL values to callers?  If they already
>>> need to check for err, why force them to check for NULL too?
>>
>> "Returns pointer to appropriate dma channel on success or an error
>> pointer." means that callers only have to check for an ERR value. If the
>> function returns NULL, then other DMA-related functions must treat that
>> as a valid channel ID. This is case (a) in my previous email.
> 
> How can a channel be "valid" and NULL at the same time?  Without the
> guarantee that dma_request_channel always returns a non-null-channel
> pointer or an error pointer you're forcing clients to use or open-code
> IS_ERR_OR_NULL.

No, callers should just follow the documentation. If all error cases are
indicated by an ERR pointer, then there is no need to check for NULL. In
fact, client must not check anything beyond whether the value is an ERR
value or not. So, there's no need to use IS_ERR_OR_NULL.

It's up to the API to make sure that it returns values that are valid
for other calls to related APIs. If that doesn't include NULL, it won't
return NULL. If it does, it might. But, that's an internal
implementation detail of the API (and associated APIs), not something
that clients should know about.

One situation where a NULL might be valid is where the return value
isn't really a pointer, but an integer index or ID cast to a pointer.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Fri, Nov 22, 2013 at 11:53 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> On 11/22/2013 12:49 PM, Dan Williams wrote:
>> On Fri, Nov 22, 2013 at 10:10 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>>>>>> The proposal is dma_request_slave_channel only returns errors or valid
>>>>>> pointers, never NULL.
>>>>>
>>>>> OK, so if you make that assumption, I guess it's safe.
>>>>
>>>> I made that assumption because that is what your original patch proposed:
>>>>
>>>> +/**
>>>> + * dma_request_slave_channel_or_err - try to allocate an exclusive
>>>> slave channel
>>>> + * @dev:       pointer to client device structure
>>>> + * @name:      slave channel name
>>>> + *
>>>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>>>> + */
>>>>
>>>> What's the benefit of leaking NULL values to callers?  If they already
>>>> need to check for err, why force them to check for NULL too?
>>>
>>> "Returns pointer to appropriate dma channel on success or an error
>>> pointer." means that callers only have to check for an ERR value. If the
>>> function returns NULL, then other DMA-related functions must treat that
>>> as a valid channel ID. This is case (a) in my previous email.
>>
>> How can a channel be "valid" and NULL at the same time?  Without the
>> guarantee that dma_request_channel always returns a non-null-channel
>> pointer or an error pointer you're forcing clients to use or open-code
>> IS_ERR_OR_NULL.
>
> No, callers should just follow the documentation. If all error cases are
> indicated by an ERR pointer, then there is no need to check for NULL. In
> fact, client must not check anything beyond whether the value is an ERR
> value or not. So, there's no need to use IS_ERR_OR_NULL.
>
> It's up to the API to make sure that it returns values that are valid
> for other calls to related APIs. If that doesn't include NULL, it won't
> return NULL. If it does, it might. But, that's an internal
> implementation detail of the API (and associated APIs), not something
> that clients should know about.
>
> One situation where a NULL might be valid is where the return value
> isn't really a pointer, but an integer index or ID cast to a pointer.

Ok that's the piece I am missing, and maybe explains why
samsung_dmadev_request() looks so broken.  Are there really
implementations out there that somehow know that the return value from
dma_request_slave channel is not a (struct dma_chan *)??

At that point just change the prototype of dma_request_slave_channel to:

MAGIC_t dma_request_slave_channel(struct device *dev, const char *name)

Those clients need to be killed or fixed, otherwise how do you
guarantee that the 'integer index or ID' does not collide with the
ERR_PTR() number space?

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Fri, Nov 22, 2013 at 11:53 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 11/22/2013 12:49 PM, Dan Williams wrote:
>> On Fri, Nov 22, 2013 at 10:10 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>>>>> The proposal is dma_request_slave_channel only returns errors or valid
>>>>>> pointers, never NULL.
>>>>>
>>>>> OK, so if you make that assumption, I guess it's safe.
>>>>
>>>> I made that assumption because that is what your original patch proposed:
>>>>
>>>> +/**
>>>> + * dma_request_slave_channel_or_err - try to allocate an exclusive
>>>> slave channel
>>>> + * @dev:       pointer to client device structure
>>>> + * @name:      slave channel name
>>>> + *
>>>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>>>> + */
>>>>
>>>> What's the benefit of leaking NULL values to callers?  If they already
>>>> need to check for err, why force them to check for NULL too?
>>>
>>> "Returns pointer to appropriate dma channel on success or an error
>>> pointer." means that callers only have to check for an ERR value. If the
>>> function returns NULL, then other DMA-related functions must treat that
>>> as a valid channel ID. This is case (a) in my previous email.
>>
>> How can a channel be "valid" and NULL at the same time?  Without the
>> guarantee that dma_request_channel always returns a non-null-channel
>> pointer or an error pointer you're forcing clients to use or open-code
>> IS_ERR_OR_NULL.
>
> No, callers should just follow the documentation. If all error cases are
> indicated by an ERR pointer, then there is no need to check for NULL. In
> fact, client must not check anything beyond whether the value is an ERR
> value or not. So, there's no need to use IS_ERR_OR_NULL.
>
> It's up to the API to make sure that it returns values that are valid
> for other calls to related APIs. If that doesn't include NULL, it won't
> return NULL. If it does, it might. But, that's an internal
> implementation detail of the API (and associated APIs), not something
> that clients should know about.
>
> One situation where a NULL might be valid is where the return value
> isn't really a pointer, but an integer index or ID cast to a pointer.

Ok that's the piece I am missing, and maybe explains why
samsung_dmadev_request() looks so broken.  Are there really
implementations out there that somehow know that the return value from
dma_request_slave channel is not a (struct dma_chan *)??

At that point just change the prototype of dma_request_slave_channel to:

MAGIC_t dma_request_slave_channel(struct device *dev, const char *name)

Those clients need to be killed or fixed, otherwise how do you
guarantee that the 'integer index or ID' does not collide with the
ERR_PTR() number space?

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/22/2013 01:46 PM, Dan Williams wrote:
> On Fri, Nov 22, 2013 at 11:53 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>> On 11/22/2013 12:49 PM, Dan Williams wrote:
>>> On Fri, Nov 22, 2013 at 10:10 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>>>>>>> The proposal is dma_request_slave_channel only returns errors or valid
>>>>>>> pointers, never NULL.
>>>>>>
>>>>>> OK, so if you make that assumption, I guess it's safe.
>>>>>
>>>>> I made that assumption because that is what your original patch proposed:
>>>>>
>>>>> +/**
>>>>> + * dma_request_slave_channel_or_err - try to allocate an exclusive
>>>>> slave channel
>>>>> + * @dev:       pointer to client device structure
>>>>> + * @name:      slave channel name
>>>>> + *
>>>>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>>>>> + */
>>>>>
>>>>> What's the benefit of leaking NULL values to callers?  If they already
>>>>> need to check for err, why force them to check for NULL too?
>>>>
>>>> "Returns pointer to appropriate dma channel on success or an error
>>>> pointer." means that callers only have to check for an ERR value. If the
>>>> function returns NULL, then other DMA-related functions must treat that
>>>> as a valid channel ID. This is case (a) in my previous email.
>>>
>>> How can a channel be "valid" and NULL at the same time?  Without the
>>> guarantee that dma_request_channel always returns a non-null-channel
>>> pointer or an error pointer you're forcing clients to use or open-code
>>> IS_ERR_OR_NULL.
>>
>> No, callers should just follow the documentation. If all error cases are
>> indicated by an ERR pointer, then there is no need to check for NULL. In
>> fact, client must not check anything beyond whether the value is an ERR
>> value or not. So, there's no need to use IS_ERR_OR_NULL.
>>
>> It's up to the API to make sure that it returns values that are valid
>> for other calls to related APIs. If that doesn't include NULL, it won't
>> return NULL. If it does, it might. But, that's an internal
>> implementation detail of the API (and associated APIs), not something
>> that clients should know about.
>>
>> One situation where a NULL might be valid is where the return value
>> isn't really a pointer, but an integer index or ID cast to a pointer.
> 
> Ok that's the piece I am missing, and maybe explains why
> samsung_dmadev_request() looks so broken.  Are there really
> implementations out there that somehow know that the return value from
> dma_request_slave channel is not a (struct dma_chan *)??

No client of the API should know that; it'd be more like an agreement
between multiple functions in the subsystem:

handle = subsystemx_allocate_something();
...
subsystemx_use_handle(handle);

Where subsystemx_allocate_something() casts from ID to "pointer", and
subsystemx_use_handle() casts back from "pointer" to ID. The callers
would have no idea this was happening.

I'm not actually aware of any specific cases where that actually happens
right now, it's just that given the way subsystemx_allocate_something()
is documented (valid handle/cookie return or ERR value) it's legal for
"subsystemx" to work that way if it wants, and it should be able to
change between this cast-a-handle style and actual pointer returns
without clients being affected.

> At that point just change the prototype of dma_request_slave_channel to:
> 
> MAGIC_t dma_request_slave_channel(struct device *dev, const char *name)
> 
> Those clients need to be killed or fixed, otherwise how do you
> guarantee that the 'integer index or ID' does not collide with the
> ERR_PTR() number space?

subsystemx_allocate_something() would have to ensure that. Probably just
by imposing a maximum limit on the handle/ID values.

Anyway, your proposal can certainly /work/. I simply wanted to point out
that it was different to the two currently accepted styles of return
value. If you're sure e.g. Russell isn't going to shout at me or you for
introducing an API that works as you describe, we certainly could go
ahead with it. Should we explicitly ping him to confirm that?

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/22/2013 01:46 PM, Dan Williams wrote:
> On Fri, Nov 22, 2013 at 11:53 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> On 11/22/2013 12:49 PM, Dan Williams wrote:
>>> On Fri, Nov 22, 2013 at 10:10 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>>>>>> The proposal is dma_request_slave_channel only returns errors or valid
>>>>>>> pointers, never NULL.
>>>>>>
>>>>>> OK, so if you make that assumption, I guess it's safe.
>>>>>
>>>>> I made that assumption because that is what your original patch proposed:
>>>>>
>>>>> +/**
>>>>> + * dma_request_slave_channel_or_err - try to allocate an exclusive
>>>>> slave channel
>>>>> + * @dev:       pointer to client device structure
>>>>> + * @name:      slave channel name
>>>>> + *
>>>>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>>>>> + */
>>>>>
>>>>> What's the benefit of leaking NULL values to callers?  If they already
>>>>> need to check for err, why force them to check for NULL too?
>>>>
>>>> "Returns pointer to appropriate dma channel on success or an error
>>>> pointer." means that callers only have to check for an ERR value. If the
>>>> function returns NULL, then other DMA-related functions must treat that
>>>> as a valid channel ID. This is case (a) in my previous email.
>>>
>>> How can a channel be "valid" and NULL at the same time?  Without the
>>> guarantee that dma_request_channel always returns a non-null-channel
>>> pointer or an error pointer you're forcing clients to use or open-code
>>> IS_ERR_OR_NULL.
>>
>> No, callers should just follow the documentation. If all error cases are
>> indicated by an ERR pointer, then there is no need to check for NULL. In
>> fact, client must not check anything beyond whether the value is an ERR
>> value or not. So, there's no need to use IS_ERR_OR_NULL.
>>
>> It's up to the API to make sure that it returns values that are valid
>> for other calls to related APIs. If that doesn't include NULL, it won't
>> return NULL. If it does, it might. But, that's an internal
>> implementation detail of the API (and associated APIs), not something
>> that clients should know about.
>>
>> One situation where a NULL might be valid is where the return value
>> isn't really a pointer, but an integer index or ID cast to a pointer.
> 
> Ok that's the piece I am missing, and maybe explains why
> samsung_dmadev_request() looks so broken.  Are there really
> implementations out there that somehow know that the return value from
> dma_request_slave channel is not a (struct dma_chan *)??

No client of the API should know that; it'd be more like an agreement
between multiple functions in the subsystem:

handle = subsystemx_allocate_something();
...
subsystemx_use_handle(handle);

Where subsystemx_allocate_something() casts from ID to "pointer", and
subsystemx_use_handle() casts back from "pointer" to ID. The callers
would have no idea this was happening.

I'm not actually aware of any specific cases where that actually happens
right now, it's just that given the way subsystemx_allocate_something()
is documented (valid handle/cookie return or ERR value) it's legal for
"subsystemx" to work that way if it wants, and it should be able to
change between this cast-a-handle style and actual pointer returns
without clients being affected.

> At that point just change the prototype of dma_request_slave_channel to:
> 
> MAGIC_t dma_request_slave_channel(struct device *dev, const char *name)
> 
> Those clients need to be killed or fixed, otherwise how do you
> guarantee that the 'integer index or ID' does not collide with the
> ERR_PTR() number space?

subsystemx_allocate_something() would have to ensure that. Probably just
by imposing a maximum limit on the handle/ID values.

Anyway, your proposal can certainly /work/. I simply wanted to point out
that it was different to the two currently accepted styles of return
value. If you're sure e.g. Russell isn't going to shout at me or you for
introducing an API that works as you describe, we certainly could go
ahead with it. Should we explicitly ping him to confirm that?

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Fri, Nov 22, 2013 at 1:50 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> On 11/22/2013 01:46 PM, Dan Williams wrote:
>> On Fri, Nov 22, 2013 at 11:53 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>>> On 11/22/2013 12:49 PM, Dan Williams wrote:
>>>> On Fri, Nov 22, 2013 at 10:10 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>>>>>>>> The proposal is dma_request_slave_channel only returns errors or valid
>>>>>>>> pointers, never NULL.
>>>>>>>
>>>>>>> OK, so if you make that assumption, I guess it's safe.
>>>>>>
>>>>>> I made that assumption because that is what your original patch proposed:
>>>>>>
>>>>>> +/**
>>>>>> + * dma_request_slave_channel_or_err - try to allocate an exclusive
>>>>>> slave channel
>>>>>> + * @dev:       pointer to client device structure
>>>>>> + * @name:      slave channel name
>>>>>> + *
>>>>>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>>>>>> + */
>>>>>>
>>>>>> What's the benefit of leaking NULL values to callers?  If they already
>>>>>> need to check for err, why force them to check for NULL too?
>>>>>
>>>>> "Returns pointer to appropriate dma channel on success or an error
>>>>> pointer." means that callers only have to check for an ERR value. If the
>>>>> function returns NULL, then other DMA-related functions must treat that
>>>>> as a valid channel ID. This is case (a) in my previous email.
>>>>
>>>> How can a channel be "valid" and NULL at the same time?  Without the
>>>> guarantee that dma_request_channel always returns a non-null-channel
>>>> pointer or an error pointer you're forcing clients to use or open-code
>>>> IS_ERR_OR_NULL.
>>>
>>> No, callers should just follow the documentation. If all error cases are
>>> indicated by an ERR pointer, then there is no need to check for NULL. In
>>> fact, client must not check anything beyond whether the value is an ERR
>>> value or not. So, there's no need to use IS_ERR_OR_NULL.
>>>
>>> It's up to the API to make sure that it returns values that are valid
>>> for other calls to related APIs. If that doesn't include NULL, it won't
>>> return NULL. If it does, it might. But, that's an internal
>>> implementation detail of the API (and associated APIs), not something
>>> that clients should know about.
>>>
>>> One situation where a NULL might be valid is where the return value
>>> isn't really a pointer, but an integer index or ID cast to a pointer.
>>
>> Ok that's the piece I am missing, and maybe explains why
>> samsung_dmadev_request() looks so broken.  Are there really
>> implementations out there that somehow know that the return value from
>> dma_request_slave channel is not a (struct dma_chan *)??
>
> No client of the API should know that; it'd be more like an agreement
> between multiple functions in the subsystem:
>
> handle = subsystemx_allocate_something();
> ...
> subsystemx_use_handle(handle);
>
> Where subsystemx_allocate_something() casts from ID to "pointer", and
> subsystemx_use_handle() casts back from "pointer" to ID. The callers
> would have no idea this was happening.

That's a bug not a feature.  That's someone abusing an api and
breaking type safety to pass arbitrary data.  But since we're talking
in abstract 'buggy_subsytemx' terms why worry?

> I'm not actually aware of any specific cases where that actually happens
> right now, it's just that given the way subsystemx_allocate_something()
> is documented (valid handle/cookie return or ERR value) it's legal for
> "subsystemx" to work that way if it wants, and it should be able to
> change between this cast-a-handle style and actual pointer returns
> without clients being affected.

Wait, this busted way of doing things is documented?

>> At that point just change the prototype of dma_request_slave_channel to:
>>
>> MAGIC_t dma_request_slave_channel(struct device *dev, const char *name)
>>
>> Those clients need to be killed or fixed, otherwise how do you
>> guarantee that the 'integer index or ID' does not collide with the
>> ERR_PTR() number space?
>
> subsystemx_allocate_something() would have to ensure that. Probably just
> by imposing a maximum limit on the handle/ID values.
>
> Anyway, your proposal can certainly /work/. I simply wanted to point out
> that it was different to the two currently accepted styles of return
> value. If you're sure e.g. Russell isn't going to shout at me or you for
> introducing an API that works as you describe, we certainly could go
> ahead with it. Should we explicitly ping him to confirm that?

He already has in other threads IS_ERR_OR_NULL() must die, this
proposal is not that.  Let me go back to your note about "case 2" and
clarify.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Fri, Nov 22, 2013 at 1:50 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 11/22/2013 01:46 PM, Dan Williams wrote:
>> On Fri, Nov 22, 2013 at 11:53 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>> On 11/22/2013 12:49 PM, Dan Williams wrote:
>>>> On Fri, Nov 22, 2013 at 10:10 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>>>>>>> The proposal is dma_request_slave_channel only returns errors or valid
>>>>>>>> pointers, never NULL.
>>>>>>>
>>>>>>> OK, so if you make that assumption, I guess it's safe.
>>>>>>
>>>>>> I made that assumption because that is what your original patch proposed:
>>>>>>
>>>>>> +/**
>>>>>> + * dma_request_slave_channel_or_err - try to allocate an exclusive
>>>>>> slave channel
>>>>>> + * @dev:       pointer to client device structure
>>>>>> + * @name:      slave channel name
>>>>>> + *
>>>>>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>>>>>> + */
>>>>>>
>>>>>> What's the benefit of leaking NULL values to callers?  If they already
>>>>>> need to check for err, why force them to check for NULL too?
>>>>>
>>>>> "Returns pointer to appropriate dma channel on success or an error
>>>>> pointer." means that callers only have to check for an ERR value. If the
>>>>> function returns NULL, then other DMA-related functions must treat that
>>>>> as a valid channel ID. This is case (a) in my previous email.
>>>>
>>>> How can a channel be "valid" and NULL at the same time?  Without the
>>>> guarantee that dma_request_channel always returns a non-null-channel
>>>> pointer or an error pointer you're forcing clients to use or open-code
>>>> IS_ERR_OR_NULL.
>>>
>>> No, callers should just follow the documentation. If all error cases are
>>> indicated by an ERR pointer, then there is no need to check for NULL. In
>>> fact, client must not check anything beyond whether the value is an ERR
>>> value or not. So, there's no need to use IS_ERR_OR_NULL.
>>>
>>> It's up to the API to make sure that it returns values that are valid
>>> for other calls to related APIs. If that doesn't include NULL, it won't
>>> return NULL. If it does, it might. But, that's an internal
>>> implementation detail of the API (and associated APIs), not something
>>> that clients should know about.
>>>
>>> One situation where a NULL might be valid is where the return value
>>> isn't really a pointer, but an integer index or ID cast to a pointer.
>>
>> Ok that's the piece I am missing, and maybe explains why
>> samsung_dmadev_request() looks so broken.  Are there really
>> implementations out there that somehow know that the return value from
>> dma_request_slave channel is not a (struct dma_chan *)??
>
> No client of the API should know that; it'd be more like an agreement
> between multiple functions in the subsystem:
>
> handle = subsystemx_allocate_something();
> ...
> subsystemx_use_handle(handle);
>
> Where subsystemx_allocate_something() casts from ID to "pointer", and
> subsystemx_use_handle() casts back from "pointer" to ID. The callers
> would have no idea this was happening.

That's a bug not a feature.  That's someone abusing an api and
breaking type safety to pass arbitrary data.  But since we're talking
in abstract 'buggy_subsytemx' terms why worry?

> I'm not actually aware of any specific cases where that actually happens
> right now, it's just that given the way subsystemx_allocate_something()
> is documented (valid handle/cookie return or ERR value) it's legal for
> "subsystemx" to work that way if it wants, and it should be able to
> change between this cast-a-handle style and actual pointer returns
> without clients being affected.

Wait, this busted way of doing things is documented?

>> At that point just change the prototype of dma_request_slave_channel to:
>>
>> MAGIC_t dma_request_slave_channel(struct device *dev, const char *name)
>>
>> Those clients need to be killed or fixed, otherwise how do you
>> guarantee that the 'integer index or ID' does not collide with the
>> ERR_PTR() number space?
>
> subsystemx_allocate_something() would have to ensure that. Probably just
> by imposing a maximum limit on the handle/ID values.
>
> Anyway, your proposal can certainly /work/. I simply wanted to point out
> that it was different to the two currently accepted styles of return
> value. If you're sure e.g. Russell isn't going to shout at me or you for
> introducing an API that works as you describe, we certainly could go
> ahead with it. Should we explicitly ping him to confirm that?

He already has in other threads IS_ERR_OR_NULL() must die, this
proposal is not that.  Let me go back to your note about "case 2" and
clarify.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/22/2013 04:13 PM, Dan Williams wrote:
> On Fri, Nov 22, 2013 at 1:50 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>> On 11/22/2013 01:46 PM, Dan Williams wrote:
>>> On Fri, Nov 22, 2013 at 11:53 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>>>> On 11/22/2013 12:49 PM, Dan Williams wrote:
>>>>> On Fri, Nov 22, 2013 at 10:10 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>>>>>>>>> The proposal is dma_request_slave_channel only returns errors or valid
>>>>>>>>> pointers, never NULL.
>>>>>>>>
>>>>>>>> OK, so if you make that assumption, I guess it's safe.
>>>>>>>
>>>>>>> I made that assumption because that is what your original patch proposed:
>>>>>>>
>>>>>>> +/**
>>>>>>> + * dma_request_slave_channel_or_err - try to allocate an exclusive
>>>>>>> slave channel
>>>>>>> + * @dev:       pointer to client device structure
>>>>>>> + * @name:      slave channel name
>>>>>>> + *
>>>>>>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>>>>>>> + */
>>>>>>>
>>>>>>> What's the benefit of leaking NULL values to callers?  If they already
>>>>>>> need to check for err, why force them to check for NULL too?
>>>>>>
>>>>>> "Returns pointer to appropriate dma channel on success or an error
>>>>>> pointer." means that callers only have to check for an ERR value. If the
>>>>>> function returns NULL, then other DMA-related functions must treat that
>>>>>> as a valid channel ID. This is case (a) in my previous email.
>>>>>
>>>>> How can a channel be "valid" and NULL at the same time?  Without the
>>>>> guarantee that dma_request_channel always returns a non-null-channel
>>>>> pointer or an error pointer you're forcing clients to use or open-code
>>>>> IS_ERR_OR_NULL.
>>>>
>>>> No, callers should just follow the documentation. If all error cases are
>>>> indicated by an ERR pointer, then there is no need to check for NULL. In
>>>> fact, client must not check anything beyond whether the value is an ERR
>>>> value or not. So, there's no need to use IS_ERR_OR_NULL.
>>>>
>>>> It's up to the API to make sure that it returns values that are valid
>>>> for other calls to related APIs. If that doesn't include NULL, it won't
>>>> return NULL. If it does, it might. But, that's an internal
>>>> implementation detail of the API (and associated APIs), not something
>>>> that clients should know about.
>>>>
>>>> One situation where a NULL might be valid is where the return value
>>>> isn't really a pointer, but an integer index or ID cast to a pointer.
>>>
>>> Ok that's the piece I am missing, and maybe explains why
>>> samsung_dmadev_request() looks so broken.  Are there really
>>> implementations out there that somehow know that the return value from
>>> dma_request_slave channel is not a (struct dma_chan *)??
>>
>> No client of the API should know that; it'd be more like an agreement
>> between multiple functions in the subsystem:
>>
>> handle = subsystemx_allocate_something();
>> ...
>> subsystemx_use_handle(handle);
>>
>> Where subsystemx_allocate_something() casts from ID to "pointer", and
>> subsystemx_use_handle() casts back from "pointer" to ID. The callers
>> would have no idea this was happening.
> 
> That's a bug not a feature.  That's someone abusing an api and
> breaking type safety to pass arbitrary data.  But since we're talking
> in abstract 'buggy_subsytemx' terms why worry?
> 
>> I'm not actually aware of any specific cases where that actually happens
>> right now, it's just that given the way subsystemx_allocate_something()
>> is documented (valid handle/cookie return or ERR value) it's legal for
>> "subsystemx" to work that way if it wants, and it should be able to
>> change between this cast-a-handle style and actual pointer returns
>> without clients being affected.
> 
> Wait, this busted way of doing things is documented?

I should have said: s/is documented/would be documented/. Or perhaps
s/documented/discussed/. IIRC, in previous discussions of
IS_ERR_OR_NULL, this came up as a specific (perhaps hypothetical) thing
that APIs could legitimately do that made it important the API clients
didn't impose restrictions on return values beyond what APIs documented.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/22/2013 04:13 PM, Dan Williams wrote:
> On Fri, Nov 22, 2013 at 1:50 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> On 11/22/2013 01:46 PM, Dan Williams wrote:
>>> On Fri, Nov 22, 2013 at 11:53 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>>> On 11/22/2013 12:49 PM, Dan Williams wrote:
>>>>> On Fri, Nov 22, 2013 at 10:10 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>>>>>>>> The proposal is dma_request_slave_channel only returns errors or valid
>>>>>>>>> pointers, never NULL.
>>>>>>>>
>>>>>>>> OK, so if you make that assumption, I guess it's safe.
>>>>>>>
>>>>>>> I made that assumption because that is what your original patch proposed:
>>>>>>>
>>>>>>> +/**
>>>>>>> + * dma_request_slave_channel_or_err - try to allocate an exclusive
>>>>>>> slave channel
>>>>>>> + * @dev:       pointer to client device structure
>>>>>>> + * @name:      slave channel name
>>>>>>> + *
>>>>>>> + * Returns pointer to appropriate dma channel on success or an error pointer.
>>>>>>> + */
>>>>>>>
>>>>>>> What's the benefit of leaking NULL values to callers?  If they already
>>>>>>> need to check for err, why force them to check for NULL too?
>>>>>>
>>>>>> "Returns pointer to appropriate dma channel on success or an error
>>>>>> pointer." means that callers only have to check for an ERR value. If the
>>>>>> function returns NULL, then other DMA-related functions must treat that
>>>>>> as a valid channel ID. This is case (a) in my previous email.
>>>>>
>>>>> How can a channel be "valid" and NULL at the same time?  Without the
>>>>> guarantee that dma_request_channel always returns a non-null-channel
>>>>> pointer or an error pointer you're forcing clients to use or open-code
>>>>> IS_ERR_OR_NULL.
>>>>
>>>> No, callers should just follow the documentation. If all error cases are
>>>> indicated by an ERR pointer, then there is no need to check for NULL. In
>>>> fact, client must not check anything beyond whether the value is an ERR
>>>> value or not. So, there's no need to use IS_ERR_OR_NULL.
>>>>
>>>> It's up to the API to make sure that it returns values that are valid
>>>> for other calls to related APIs. If that doesn't include NULL, it won't
>>>> return NULL. If it does, it might. But, that's an internal
>>>> implementation detail of the API (and associated APIs), not something
>>>> that clients should know about.
>>>>
>>>> One situation where a NULL might be valid is where the return value
>>>> isn't really a pointer, but an integer index or ID cast to a pointer.
>>>
>>> Ok that's the piece I am missing, and maybe explains why
>>> samsung_dmadev_request() looks so broken.  Are there really
>>> implementations out there that somehow know that the return value from
>>> dma_request_slave channel is not a (struct dma_chan *)??
>>
>> No client of the API should know that; it'd be more like an agreement
>> between multiple functions in the subsystem:
>>
>> handle = subsystemx_allocate_something();
>> ...
>> subsystemx_use_handle(handle);
>>
>> Where subsystemx_allocate_something() casts from ID to "pointer", and
>> subsystemx_use_handle() casts back from "pointer" to ID. The callers
>> would have no idea this was happening.
> 
> That's a bug not a feature.  That's someone abusing an api and
> breaking type safety to pass arbitrary data.  But since we're talking
> in abstract 'buggy_subsytemx' terms why worry?
> 
>> I'm not actually aware of any specific cases where that actually happens
>> right now, it's just that given the way subsystemx_allocate_something()
>> is documented (valid handle/cookie return or ERR value) it's legal for
>> "subsystemx" to work that way if it wants, and it should be able to
>> change between this cast-a-handle style and actual pointer returns
>> without clients being affected.
> 
> Wait, this busted way of doing things is documented?

I should have said: s/is documented/would be documented/. Or perhaps
s/documented/discussed/. IIRC, in previous discussions of
IS_ERR_OR_NULL, this came up as a specific (perhaps hypothetical) thing
that APIs could legitimately do that made it important the API clients
didn't impose restrictions on return values beyond what APIs documented.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Russell King - ARM Linux]

On Fri, Nov 22, 2013 at 11:49:55AM -0800, Dan Williams wrote:
> On Fri, Nov 22, 2013 at 10:10 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> >>>> The proposal is dma_request_slave_channel only returns errors or valid
> >>>> pointers, never NULL.
> >>>
> >>> OK, so if you make that assumption, I guess it's safe.
> >>
> >> I made that assumption because that is what your original patch proposed:
> >>
> >> +/**
> >> + * dma_request_slave_channel_or_err - try to allocate an exclusive
> >> slave channel
> >> + * @dev:       pointer to client device structure
> >> + * @name:      slave channel name
> >> + *
> >> + * Returns pointer to appropriate dma channel on success or an error pointer.
> >> + */
> >>
> >> What's the benefit of leaking NULL values to callers?  If they already
> >> need to check for err, why force them to check for NULL too?
> >
> > "Returns pointer to appropriate dma channel on success or an error
> > pointer." means that callers only have to check for an ERR value. If the
> > function returns NULL, then other DMA-related functions must treat that
> > as a valid channel ID. This is case (a) in my previous email.
> 
> How can a channel be "valid" and NULL at the same time?  Without the
> guarantee that dma_request_channel always returns a non-null-channel
> pointer or an error pointer you're forcing clients to use or open-code
> IS_ERR_OR_NULL.  Make the caller's life easier and just turn success
> or failure like before.

It's absolutely fine for an API to return "valid pointers or an error
pointer" and not have to care about the NULL condition.  Really.

Think about it.

	chan = dma_request_blah();
	if (IS_ERR(chan))
		return PTR_ERR(chan);

	dma_do_something(chan);

Now, if the API is defined to be "valid pointers or error pointers" the
above code is quite sane.  The user is doing everything required to use
the API safely.

However, if dma_request_blah() happens to return NULL, that's a failure
of dma_request_blah() - not of the user to check for it.  If
dma_request_blah() is never supposed to return NULL, then there won't be
any checks done to handle a NULL pointer into dma_do_something(), and we
get to find out about this failure by a kernel NULL pointer deref oops.

That's a good thing.  We have a condition which can be debugged and the
bug which caused the NULL pointer to be returned can be found and fixed.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Russell King - ARM Linux]

On Fri, Nov 22, 2013 at 11:49:55AM -0800, Dan Williams wrote:
> On Fri, Nov 22, 2013 at 10:10 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> >>>> The proposal is dma_request_slave_channel only returns errors or valid
> >>>> pointers, never NULL.
> >>>
> >>> OK, so if you make that assumption, I guess it's safe.
> >>
> >> I made that assumption because that is what your original patch proposed:
> >>
> >> +/**
> >> + * dma_request_slave_channel_or_err - try to allocate an exclusive
> >> slave channel
> >> + * @dev:       pointer to client device structure
> >> + * @name:      slave channel name
> >> + *
> >> + * Returns pointer to appropriate dma channel on success or an error pointer.
> >> + */
> >>
> >> What's the benefit of leaking NULL values to callers?  If they already
> >> need to check for err, why force them to check for NULL too?
> >
> > "Returns pointer to appropriate dma channel on success or an error
> > pointer." means that callers only have to check for an ERR value. If the
> > function returns NULL, then other DMA-related functions must treat that
> > as a valid channel ID. This is case (a) in my previous email.
> 
> How can a channel be "valid" and NULL at the same time?  Without the
> guarantee that dma_request_channel always returns a non-null-channel
> pointer or an error pointer you're forcing clients to use or open-code
> IS_ERR_OR_NULL.  Make the caller's life easier and just turn success
> or failure like before.

It's absolutely fine for an API to return "valid pointers or an error
pointer" and not have to care about the NULL condition.  Really.

Think about it.

	chan = dma_request_blah();
	if (IS_ERR(chan))
		return PTR_ERR(chan);

	dma_do_something(chan);

Now, if the API is defined to be "valid pointers or error pointers" the
above code is quite sane.  The user is doing everything required to use
the API safely.

However, if dma_request_blah() happens to return NULL, that's a failure
of dma_request_blah() - not of the user to check for it.  If
dma_request_blah() is never supposed to return NULL, then there won't be
any checks done to handle a NULL pointer into dma_do_something(), and we
get to find out about this failure by a kernel NULL pointer deref oops.

That's a good thing.  We have a condition which can be debugged and the
bug which caused the NULL pointer to be returned can be found and fixed.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Russell King - ARM Linux]

On Fri, Nov 22, 2013 at 11:10:01AM -0700, Stephen Warren wrote:
> On 11/22/2013 11:04 AM, Dan Williams wrote:
> > I made that assumption because that is what your original patch proposed:
> > 
> > +/**
> > + * dma_request_slave_channel_or_err - try to allocate an exclusive
> > slave channel
> > + * @dev:       pointer to client device structure
> > + * @name:      slave channel name
> > + *
> > + * Returns pointer to appropriate dma channel on success or an error pointer.
> > + */
> > 
> > What's the benefit of leaking NULL values to callers?  If they already
> > need to check for err, why force them to check for NULL too?
> 
> "Returns pointer to appropriate dma channel on success or an error
> pointer." means that callers only have to check for an ERR value. If the
> function returns NULL, then other DMA-related functions must treat that
> as a valid channel ID. This is case (a) in my previous email.

Stephen, Dan,

My point (which you quoted) is a fine one - read the definition above.

"Returns pointer to appropriate DMA channel on success or an error pointer."

This defines the range of values which are considered successful, and
those which are considered to be errors.  Error pointers are defined
by IS_ERR(ptr) being true (not by IS_ERR_OR_NULL(ptr) being true.
Conversely, it defines what are considered to be non-errors.

Therefore, users of such a function _must_ check the return value using
IS_ERR() and not the IS_ERR_OR_NULL() abomination.

The question about NULL is unanswered, but with nothing specified, users
must assume that if a subsystem returns NULL, it's fine to pass that back
to the subsystem.  If the subsystem didn't intend for NULL to be valid,
it shouldn't be returning NULL from such a defined function.

It's not up to the user of the interface to dream up an error code if
the subsystem happens to return NULL, or do other crap stuff like this:

	if (IS_ERR_OR_NULL(ptr))
		return PTR_ERR(ptr);

which we already see cropping up from time to time.

So, my argument is that if you define an API to be "pointers on success,
or error pointers" then your API better handle any cookie you return
which satisfies IS_ERR(ptr) = false - which by definition includes NULL.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Russell King - ARM Linux]

On Fri, Nov 22, 2013 at 11:10:01AM -0700, Stephen Warren wrote:
> On 11/22/2013 11:04 AM, Dan Williams wrote:
> > I made that assumption because that is what your original patch proposed:
> > 
> > +/**
> > + * dma_request_slave_channel_or_err - try to allocate an exclusive
> > slave channel
> > + * @dev:       pointer to client device structure
> > + * @name:      slave channel name
> > + *
> > + * Returns pointer to appropriate dma channel on success or an error pointer.
> > + */
> > 
> > What's the benefit of leaking NULL values to callers?  If they already
> > need to check for err, why force them to check for NULL too?
> 
> "Returns pointer to appropriate dma channel on success or an error
> pointer." means that callers only have to check for an ERR value. If the
> function returns NULL, then other DMA-related functions must treat that
> as a valid channel ID. This is case (a) in my previous email.

Stephen, Dan,

My point (which you quoted) is a fine one - read the definition above.

"Returns pointer to appropriate DMA channel on success or an error pointer."

This defines the range of values which are considered successful, and
those which are considered to be errors.  Error pointers are defined
by IS_ERR(ptr) being true (not by IS_ERR_OR_NULL(ptr) being true.
Conversely, it defines what are considered to be non-errors.

Therefore, users of such a function _must_ check the return value using
IS_ERR() and not the IS_ERR_OR_NULL() abomination.

The question about NULL is unanswered, but with nothing specified, users
must assume that if a subsystem returns NULL, it's fine to pass that back
to the subsystem.  If the subsystem didn't intend for NULL to be valid,
it shouldn't be returning NULL from such a defined function.

It's not up to the user of the interface to dream up an error code if
the subsystem happens to return NULL, or do other crap stuff like this:

	if (IS_ERR_OR_NULL(ptr))
		return PTR_ERR(ptr);

which we already see cropping up from time to time.

So, my argument is that if you define an API to be "pointers on success,
or error pointers" then your API better handle any cookie you return
which satisfies IS_ERR(ptr) = false - which by definition includes NULL.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/22/2013 05:34 PM, Russell King - ARM Linux wrote:
[... various discussions re: IS_ERR, IS_ERR_OR_NULL, etc.]

Russell, so if we document dma_request_slave_channel() as follows:

> /*
>  * dma_request_slave_channel - try to allocate an exclusive slave channel
> ...
>  * Returns pointer to appropriate DMA channel on success or an error pointer.
>  * In order to ease compatibility with other DMA request APIs, this function
>  * guarantees NEVER to return NULL.
>  */

Are you then OK with clients doing either of e.g.:

chan = dma_request_slave_channel(...);
if (IS_ERR(chan))
	// This returns NULL or a valid handle/pointer
	chan = dma_request_channel()
if (!chan)
	Here, chan is invalid;
	return;
Here, chan is valid

or:

if (xxx) {
	chan = dma_request_slave_channel(...);
	// Convert to same error value as else{} block generates
	if (IS_ERR(chan))
		chan = NULL
} else {
	// This returns NULL or a valid handle/pointer
	chan = dma_request_channel()
}
if (!chan)
	Here, chan is invalid
	return;
Here, chan is valid

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/22/2013 05:34 PM, Russell King - ARM Linux wrote:
[... various discussions re: IS_ERR, IS_ERR_OR_NULL, etc.]

Russell, so if we document dma_request_slave_channel() as follows:

> /*
>  * dma_request_slave_channel - try to allocate an exclusive slave channel
> ...
>  * Returns pointer to appropriate DMA channel on success or an error pointer.
>  * In order to ease compatibility with other DMA request APIs, this function
>  * guarantees NEVER to return NULL.
>  */

Are you then OK with clients doing either of e.g.:

chan = dma_request_slave_channel(...);
if (IS_ERR(chan))
	// This returns NULL or a valid handle/pointer
	chan = dma_request_channel()
if (!chan)
	Here, chan is invalid;
	return;
Here, chan is valid

or:

if (xxx) {
	chan = dma_request_slave_channel(...);
	// Convert to same error value as else{} block generates
	if (IS_ERR(chan))
		chan = NULL
} else {
	// This returns NULL or a valid handle/pointer
	chan = dma_request_channel()
}
if (!chan)
	Here, chan is invalid
	return;
Here, chan is valid

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Mon, Nov 25, 2013 at 9:26 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> On 11/22/2013 05:34 PM, Russell King - ARM Linux wrote:
> [... various discussions re: IS_ERR, IS_ERR_OR_NULL, etc.]
>
> Russell, so if we document dma_request_slave_channel() as follows:
>
>> /*
>>  * dma_request_slave_channel - try to allocate an exclusive slave channel
>> ...
>>  * Returns pointer to appropriate DMA channel on success or an error pointer.
>>  * In order to ease compatibility with other DMA request APIs, this function
>>  * guarantees NEVER to return NULL.
>>  */
>
> Are you then OK with clients doing either of e.g.:
>
> chan = dma_request_slave_channel(...);
> if (IS_ERR(chan))
>         // This returns NULL or a valid handle/pointer
>         chan = dma_request_channel()
> if (!chan)
>         Here, chan is invalid;
>         return;
> Here, chan is valid
>

If the driver falls back to dma_request_channel then this one is cleaner.

> or:
>
> if (xxx) {
>         chan = dma_request_slave_channel(...);
>         // Convert to same error value as else{} block generates
>         if (IS_ERR(chan))
>                 chan = NULL
> } else {
>         // This returns NULL or a valid handle/pointer
>         chan = dma_request_channel()
> }
> if (!chan)
>         Here, chan is invalid
>         return;
> Here, chan is valid

Regardless of whether the driver was dma_request_channel as a
fallback, it will currently use NULL to indicate an allocation
failure.  We could go and audit the driver's usage of the result to
add more IS_ERR() guards.  In the absence of a later call to
dma_request_channel() immediately converting to NULL is the least
error prone conversion.  Of course it's up to the driver, for example:

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index aaa22867e656..c0f400c3c954 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -278,7 +278,7 @@ static void pl011_dma_probe_initcall(struct device
*dev, struct uart_amba_port *

        chan = dma_request_slave_channel(dev, "tx");

-       if (!chan) {
+       if (IS_ERR(chan)) {
                /* We need platform data */
                if (!plat || !plat->dma_filter) {
                        dev_info(uap->port.dev, "no DMA platform data\n");

...does not need to convert it to NULL.

Nor this one...
diff --git a/drivers/usb/musb/musb_cppi41.c b/drivers/usb/musb/musb_cppi41.c
index ff9d6de2b746..b71c5f138968 100644
--- a/drivers/usb/musb/musb_cppi41.c
+++ b/drivers/usb/musb/musb_cppi41.c
@@ -502,7 +502,7 @@ static int cppi41_dma_controller_start(struct
cppi41_dma_controller *controller)
                musb_dma->max_len = SZ_4M;

                dc = dma_request_slave_channel(dev, str);
-               if (!dc) {
+               if (IS_ERR(dc)) {
                        dev_err(dev, "Falied to request %s.\n", str);
                        ret = -EPROBE_DEFER;
                        goto err;

...but need to go back and see if this can be cleaned up to not invent
the error code here.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Mon, Nov 25, 2013 at 9:26 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 11/22/2013 05:34 PM, Russell King - ARM Linux wrote:
> [... various discussions re: IS_ERR, IS_ERR_OR_NULL, etc.]
>
> Russell, so if we document dma_request_slave_channel() as follows:
>
>> /*
>>  * dma_request_slave_channel - try to allocate an exclusive slave channel
>> ...
>>  * Returns pointer to appropriate DMA channel on success or an error pointer.
>>  * In order to ease compatibility with other DMA request APIs, this function
>>  * guarantees NEVER to return NULL.
>>  */
>
> Are you then OK with clients doing either of e.g.:
>
> chan = dma_request_slave_channel(...);
> if (IS_ERR(chan))
>         // This returns NULL or a valid handle/pointer
>         chan = dma_request_channel()
> if (!chan)
>         Here, chan is invalid;
>         return;
> Here, chan is valid
>

If the driver falls back to dma_request_channel then this one is cleaner.

> or:
>
> if (xxx) {
>         chan = dma_request_slave_channel(...);
>         // Convert to same error value as else{} block generates
>         if (IS_ERR(chan))
>                 chan = NULL
> } else {
>         // This returns NULL or a valid handle/pointer
>         chan = dma_request_channel()
> }
> if (!chan)
>         Here, chan is invalid
>         return;
> Here, chan is valid

Regardless of whether the driver was dma_request_channel as a
fallback, it will currently use NULL to indicate an allocation
failure.  We could go and audit the driver's usage of the result to
add more IS_ERR() guards.  In the absence of a later call to
dma_request_channel() immediately converting to NULL is the least
error prone conversion.  Of course it's up to the driver, for example:

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index aaa22867e656..c0f400c3c954 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -278,7 +278,7 @@ static void pl011_dma_probe_initcall(struct device
*dev, struct uart_amba_port *

        chan = dma_request_slave_channel(dev, "tx");

-       if (!chan) {
+       if (IS_ERR(chan)) {
                /* We need platform data */
                if (!plat || !plat->dma_filter) {
                        dev_info(uap->port.dev, "no DMA platform data\n");

...does not need to convert it to NULL.

Nor this one...
diff --git a/drivers/usb/musb/musb_cppi41.c b/drivers/usb/musb/musb_cppi41.c
index ff9d6de2b746..b71c5f138968 100644
--- a/drivers/usb/musb/musb_cppi41.c
+++ b/drivers/usb/musb/musb_cppi41.c
@@ -502,7 +502,7 @@ static int cppi41_dma_controller_start(struct
cppi41_dma_controller *controller)
                musb_dma->max_len = SZ_4M;

                dc = dma_request_slave_channel(dev, str);
-               if (!dc) {
+               if (IS_ERR(dc)) {
                        dev_err(dev, "Falied to request %s.\n", str);
                        ret = -EPROBE_DEFER;
                        goto err;

...but need to go back and see if this can be cleaned up to not invent
the error code here.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Russell King - ARM Linux]

On Mon, Nov 25, 2013 at 09:45:18AM -0800, Dan Williams wrote:
> Regardless of whether the driver was dma_request_channel as a
> fallback, it will currently use NULL to indicate an allocation
> failure.

At the moment, dma_request_slave_channel()'s return values are valid
pointer or NULL.  I'd suggest as that's how it's been established,
that function is left alone - changing the return values in this kind
of invisible way is Really Bad(tm) because you can't check that it's
right in any future users - unless you're prepared to review every
single new user of this function for the next few years or more.

Instead, leaving it as is and introducing a new function name with
the different return error method is the right way to do this.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Russell King - ARM Linux]

On Mon, Nov 25, 2013 at 09:45:18AM -0800, Dan Williams wrote:
> Regardless of whether the driver was dma_request_channel as a
> fallback, it will currently use NULL to indicate an allocation
> failure.

At the moment, dma_request_slave_channel()'s return values are valid
pointer or NULL.  I'd suggest as that's how it's been established,
that function is left alone - changing the return values in this kind
of invisible way is Really Bad(tm) because you can't check that it's
right in any future users - unless you're prepared to review every
single new user of this function for the next few years or more.

Instead, leaving it as is and introducing a new function name with
the different return error method is the right way to do this.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/25/2013 11:00 AM, Russell King - ARM Linux wrote:
> On Mon, Nov 25, 2013 at 09:45:18AM -0800, Dan Williams wrote:
>> Regardless of whether the driver was dma_request_channel as a
>> fallback, it will currently use NULL to indicate an allocation
>> failure.
> 
> At the moment, dma_request_slave_channel()'s return values are valid
> pointer or NULL.  I'd suggest as that's how it's been established,
> that function is left alone - changing the return values in this kind
> of invisible way is Really Bad(tm) because you can't check that it's
> right in any future users - unless you're prepared to review every
> single new user of this function for the next few years or more.
> 
> Instead, leaving it as is and introducing a new function name with
> the different return error method is the right way to do this.

Uggh. So here's the history of my patch series:

a) Started modifying dma_request_slave_channel() since there are very
few users right now, and it seemed simple to convert them all.

b) Found that some places mixed dma_request_slave_channel() and
dma_request_channel(). Converting dma_request_channel()'s return value
in the same way seemed prohibitive since it's much more widely used and
has been around for longer.

c) Rewrote patch to introduce a new function instead, since that didn't
require converting any existing drivers.

d) Received review feedback that I really should convert the existing
function's return code.

e) Started work on that using the return-value-conversion idea from Dan,
which allowed the two "return value styles" to co-exist easily, since I
figured that would be accepted.

Now you're telling me I should do what I already did in the patch, but
Dan is telling me to do the opposite:-(

How do we resolve this? Is there an option both you and Dan can accept?

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/25/2013 11:00 AM, Russell King - ARM Linux wrote:
> On Mon, Nov 25, 2013 at 09:45:18AM -0800, Dan Williams wrote:
>> Regardless of whether the driver was dma_request_channel as a
>> fallback, it will currently use NULL to indicate an allocation
>> failure.
> 
> At the moment, dma_request_slave_channel()'s return values are valid
> pointer or NULL.  I'd suggest as that's how it's been established,
> that function is left alone - changing the return values in this kind
> of invisible way is Really Bad(tm) because you can't check that it's
> right in any future users - unless you're prepared to review every
> single new user of this function for the next few years or more.
> 
> Instead, leaving it as is and introducing a new function name with
> the different return error method is the right way to do this.

Uggh. So here's the history of my patch series:

a) Started modifying dma_request_slave_channel() since there are very
few users right now, and it seemed simple to convert them all.

b) Found that some places mixed dma_request_slave_channel() and
dma_request_channel(). Converting dma_request_channel()'s return value
in the same way seemed prohibitive since it's much more widely used and
has been around for longer.

c) Rewrote patch to introduce a new function instead, since that didn't
require converting any existing drivers.

d) Received review feedback that I really should convert the existing
function's return code.

e) Started work on that using the return-value-conversion idea from Dan,
which allowed the two "return value styles" to co-exist easily, since I
figured that would be accepted.

Now you're telling me I should do what I already did in the patch, but
Dan is telling me to do the opposite:-(

How do we resolve this? Is there an option both you and Dan can accept?

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Mon, Nov 25, 2013 at 10:00 AM, Russell King - ARM Linux
<linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> wrote:
> On Mon, Nov 25, 2013 at 09:45:18AM -0800, Dan Williams wrote:
>> Regardless of whether the driver was dma_request_channel as a
>> fallback, it will currently use NULL to indicate an allocation
>> failure.
>
> At the moment, dma_request_slave_channel()'s return values are valid
> pointer or NULL.  I'd suggest as that's how it's been established,
> that function is left alone - changing the return values in this kind
> of invisible way is Really Bad(tm) because you can't check that it's
> right in any future users - unless you're prepared to review every
> single new user of this function for the next few years or more.
>
> Instead, leaving it as is and introducing a new function name with
> the different return error method is the right way to do this.

I was attempting to tap the brakes on the number of request_channel
apis in circulation.
dma_request_channel
dma_request_slave_channel
dma_request_slave_channel_compat
... and now dma_request_slave_channel_reason

...but given we already have things like samsung_dmadev_request() in
the wild, tracking correct usage going forward will be an uphill
battle.  We can do this the other way round.  Introduce the new api
and delete the old one (after some time).

Stephen,

Can we make the new api not pass the 'defer' flag.  You mention it is
for compat reasons, but since there are no users I'm not seeing how
there can be compatibility concerns.  Can you elaborate?

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Mon, Nov 25, 2013 at 10:00 AM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Mon, Nov 25, 2013 at 09:45:18AM -0800, Dan Williams wrote:
>> Regardless of whether the driver was dma_request_channel as a
>> fallback, it will currently use NULL to indicate an allocation
>> failure.
>
> At the moment, dma_request_slave_channel()'s return values are valid
> pointer or NULL.  I'd suggest as that's how it's been established,
> that function is left alone - changing the return values in this kind
> of invisible way is Really Bad(tm) because you can't check that it's
> right in any future users - unless you're prepared to review every
> single new user of this function for the next few years or more.
>
> Instead, leaving it as is and introducing a new function name with
> the different return error method is the right way to do this.

I was attempting to tap the brakes on the number of request_channel
apis in circulation.
dma_request_channel
dma_request_slave_channel
dma_request_slave_channel_compat
... and now dma_request_slave_channel_reason

...but given we already have things like samsung_dmadev_request() in
the wild, tracking correct usage going forward will be an uphill
battle.  We can do this the other way round.  Introduce the new api
and delete the old one (after some time).

Stephen,

Can we make the new api not pass the 'defer' flag.  You mention it is
for compat reasons, but since there are no users I'm not seeing how
there can be compatibility concerns.  Can you elaborate?

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/25/2013 11:42 AM, Dan Williams wrote:
> On Mon, Nov 25, 2013 at 10:00 AM, Russell King - ARM Linux
> <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> wrote:
>> On Mon, Nov 25, 2013 at 09:45:18AM -0800, Dan Williams wrote:
>>> Regardless of whether the driver was dma_request_channel as a
>>> fallback, it will currently use NULL to indicate an allocation
>>> failure.
>>
>> At the moment, dma_request_slave_channel()'s return values are valid
>> pointer or NULL.  I'd suggest as that's how it's been established,
>> that function is left alone - changing the return values in this kind
>> of invisible way is Really Bad(tm) because you can't check that it's
>> right in any future users - unless you're prepared to review every
>> single new user of this function for the next few years or more.
>>
>> Instead, leaving it as is and introducing a new function name with
>> the different return error method is the right way to do this.
> 
> I was attempting to tap the brakes on the number of request_channel
> apis in circulation.
> dma_request_channel
> dma_request_slave_channel
> dma_request_slave_channel_compat
> ... and now dma_request_slave_channel_reason
> 
> ...but given we already have things like samsung_dmadev_request() in
> the wild, tracking correct usage going forward will be an uphill
> battle.  We can do this the other way round.  Introduce the new api
> and delete the old one (after some time).
> 
> Stephen,
> 
> Can we make the new api not pass the 'defer' flag.  You mention it is
> for compat reasons, but since there are no users I'm not seeing how
> there can be compatibility concerns.  Can you elaborate?

dma_request_slave_channel_or_err() doesn't have a defer flag. Rather,
__dma_request_slave_channel_or_err() did, which is the shared
implementation between the existing existing dma_request_slave_channel()
and the new dma_request_slave_channel_or_err().

That flag exists so it can be passed to of_dma_request_slave_channel().
That function needs it because I didn't want to change the existing
behaviour of dma_request_slave_channel() at all, yet I wanted slightly
different behaviour from dma_request_slave_channel_or_err().

Specifically, if of_dma_request_slave_channel() finds an entry in the
dmas DT property for which there is no registered DMA controller, it
simply ignores that entry and carries on, hoping to find an alternative
entry that can satisfy the request (since some controllers can be
supported by multiple DMA controllers). However, to support deferred
probe, we really need to bail out from the loop early with -EPROBE_DEFER
if any DMA controller isn't found, in order to wait for it to be registered.

I suppose an alternative would be to remove that flag, and have the loop
in of_dma_request_slave_channel() initially ignore any unregistered DMA
controllers, and still continue to look through the property for any
alternative controller, and return a channel from one if it is found.
Then, at the very end of the function, we could always return
-EPROBE_DEFER if any unregistered DMA controllers were found, otherwise
return -ENODEV. That would keep compatible behaviour, but it would mean
that device probe order would/could influence which dmas entry provided
the channel, since some entries might be ignored based simply on
timing/ordering of DMA controller registration. Is that acceptable?

Either way, just let me know and I'll adjust the code accordingly; the
code changes for either option are simple.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/25/2013 11:42 AM, Dan Williams wrote:
> On Mon, Nov 25, 2013 at 10:00 AM, Russell King - ARM Linux
> <linux@arm.linux.org.uk> wrote:
>> On Mon, Nov 25, 2013 at 09:45:18AM -0800, Dan Williams wrote:
>>> Regardless of whether the driver was dma_request_channel as a
>>> fallback, it will currently use NULL to indicate an allocation
>>> failure.
>>
>> At the moment, dma_request_slave_channel()'s return values are valid
>> pointer or NULL.  I'd suggest as that's how it's been established,
>> that function is left alone - changing the return values in this kind
>> of invisible way is Really Bad(tm) because you can't check that it's
>> right in any future users - unless you're prepared to review every
>> single new user of this function for the next few years or more.
>>
>> Instead, leaving it as is and introducing a new function name with
>> the different return error method is the right way to do this.
> 
> I was attempting to tap the brakes on the number of request_channel
> apis in circulation.
> dma_request_channel
> dma_request_slave_channel
> dma_request_slave_channel_compat
> ... and now dma_request_slave_channel_reason
> 
> ...but given we already have things like samsung_dmadev_request() in
> the wild, tracking correct usage going forward will be an uphill
> battle.  We can do this the other way round.  Introduce the new api
> and delete the old one (after some time).
> 
> Stephen,
> 
> Can we make the new api not pass the 'defer' flag.  You mention it is
> for compat reasons, but since there are no users I'm not seeing how
> there can be compatibility concerns.  Can you elaborate?

dma_request_slave_channel_or_err() doesn't have a defer flag. Rather,
__dma_request_slave_channel_or_err() did, which is the shared
implementation between the existing existing dma_request_slave_channel()
and the new dma_request_slave_channel_or_err().

That flag exists so it can be passed to of_dma_request_slave_channel().
That function needs it because I didn't want to change the existing
behaviour of dma_request_slave_channel() at all, yet I wanted slightly
different behaviour from dma_request_slave_channel_or_err().

Specifically, if of_dma_request_slave_channel() finds an entry in the
dmas DT property for which there is no registered DMA controller, it
simply ignores that entry and carries on, hoping to find an alternative
entry that can satisfy the request (since some controllers can be
supported by multiple DMA controllers). However, to support deferred
probe, we really need to bail out from the loop early with -EPROBE_DEFER
if any DMA controller isn't found, in order to wait for it to be registered.

I suppose an alternative would be to remove that flag, and have the loop
in of_dma_request_slave_channel() initially ignore any unregistered DMA
controllers, and still continue to look through the property for any
alternative controller, and return a channel from one if it is found.
Then, at the very end of the function, we could always return
-EPROBE_DEFER if any unregistered DMA controllers were found, otherwise
return -ENODEV. That would keep compatible behaviour, but it would mean
that device probe order would/could influence which dmas entry provided
the channel, since some entries might be ignored based simply on
timing/ordering of DMA controller registration. Is that acceptable?

Either way, just let me know and I'll adjust the code accordingly; the
code changes for either option are simple.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Mon, Nov 25, 2013 at 11:00 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> I suppose an alternative would be to remove that flag, and have the loop
> in of_dma_request_slave_channel() initially ignore any unregistered DMA
> controllers, and still continue to look through the property for any
> alternative controller, and return a channel from one if it is found.
> Then, at the very end of the function, we could always return
> -EPROBE_DEFER if any unregistered DMA controllers were found, otherwise
> return -ENODEV. That would keep compatible behaviour, but it would mean
> that device probe order would/could influence which dmas entry provided
> the channel, since some entries might be ignored based simply on
> timing/ordering of DMA controller registration. Is that acceptable?
>

Yes, I think this option makes the most sense, and is just as
susceptible to probe order as the current implementation.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Mon, Nov 25, 2013 at 11:00 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> I suppose an alternative would be to remove that flag, and have the loop
> in of_dma_request_slave_channel() initially ignore any unregistered DMA
> controllers, and still continue to look through the property for any
> alternative controller, and return a channel from one if it is found.
> Then, at the very end of the function, we could always return
> -EPROBE_DEFER if any unregistered DMA controllers were found, otherwise
> return -ENODEV. That would keep compatible behaviour, but it would mean
> that device probe order would/could influence which dmas entry provided
> the channel, since some entries might be ignored based simply on
> timing/ordering of DMA controller registration. Is that acceptable?
>

Yes, I think this option makes the most sense, and is just as
susceptible to probe order as the current implementation.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/25/2013 12:28 PM, Dan Williams wrote:
> On Mon, Nov 25, 2013 at 11:00 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>> I suppose an alternative would be to remove that flag, and have the loop
>> in of_dma_request_slave_channel() initially ignore any unregistered DMA
>> controllers, and still continue to look through the property for any
>> alternative controller, and return a channel from one if it is found.
>> Then, at the very end of the function, we could always return
>> -EPROBE_DEFER if any unregistered DMA controllers were found, otherwise
>> return -ENODEV. That would keep compatible behaviour, but it would mean
>> that device probe order would/could influence which dmas entry provided
>> the channel, since some entries might be ignored based simply on
>> timing/ordering of DMA controller registration. Is that acceptable?
>>
> 
> Yes, I think this option makes the most sense, and is just as
> susceptible to probe order as the current implementation.

OK great. Last two questions then:

1) Do you want me to revert the changes to acpi-dma.c, and simply handle
the return value conversion inside __dma_request_slave_channel().

2) What's the final call on the new API name?

Just let me know on both - the changes are simple. Thanks.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/25/2013 12:28 PM, Dan Williams wrote:
> On Mon, Nov 25, 2013 at 11:00 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> I suppose an alternative would be to remove that flag, and have the loop
>> in of_dma_request_slave_channel() initially ignore any unregistered DMA
>> controllers, and still continue to look through the property for any
>> alternative controller, and return a channel from one if it is found.
>> Then, at the very end of the function, we could always return
>> -EPROBE_DEFER if any unregistered DMA controllers were found, otherwise
>> return -ENODEV. That would keep compatible behaviour, but it would mean
>> that device probe order would/could influence which dmas entry provided
>> the channel, since some entries might be ignored based simply on
>> timing/ordering of DMA controller registration. Is that acceptable?
>>
> 
> Yes, I think this option makes the most sense, and is just as
> susceptible to probe order as the current implementation.

OK great. Last two questions then:

1) Do you want me to revert the changes to acpi-dma.c, and simply handle
the return value conversion inside __dma_request_slave_channel().

2) What's the final call on the new API name?

Just let me know on both - the changes are simple. Thanks.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Mon, Nov 25, 2013 at 11:30 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> On 11/25/2013 12:28 PM, Dan Williams wrote:
>> On Mon, Nov 25, 2013 at 11:00 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>>> I suppose an alternative would be to remove that flag, and have the loop
>>> in of_dma_request_slave_channel() initially ignore any unregistered DMA
>>> controllers, and still continue to look through the property for any
>>> alternative controller, and return a channel from one if it is found.
>>> Then, at the very end of the function, we could always return
>>> -EPROBE_DEFER if any unregistered DMA controllers were found, otherwise
>>> return -ENODEV. That would keep compatible behaviour, but it would mean
>>> that device probe order would/could influence which dmas entry provided
>>> the channel, since some entries might be ignored based simply on
>>> timing/ordering of DMA controller registration. Is that acceptable?
>>>
>>
>> Yes, I think this option makes the most sense, and is just as
>> susceptible to probe order as the current implementation.
>
> OK great. Last two questions then:
>
> 1) Do you want me to revert the changes to acpi-dma.c, and simply handle
> the return value conversion inside __dma_request_slave_channel().

Yeah, no need to spread the complexity further than necessary.

> 2) What's the final call on the new API name?

What do you think of _reason?  I just read the existence of
dma_request_slave_channel_or_err() as an implication that
dma_request_slave_channel() may not fail.

> Just let me know on both - the changes are simple. Thanks.

Well thanks for hashing this back and forth, we can laugh about it
over a drink at the next conference.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Mon, Nov 25, 2013 at 11:30 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 11/25/2013 12:28 PM, Dan Williams wrote:
>> On Mon, Nov 25, 2013 at 11:00 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>> I suppose an alternative would be to remove that flag, and have the loop
>>> in of_dma_request_slave_channel() initially ignore any unregistered DMA
>>> controllers, and still continue to look through the property for any
>>> alternative controller, and return a channel from one if it is found.
>>> Then, at the very end of the function, we could always return
>>> -EPROBE_DEFER if any unregistered DMA controllers were found, otherwise
>>> return -ENODEV. That would keep compatible behaviour, but it would mean
>>> that device probe order would/could influence which dmas entry provided
>>> the channel, since some entries might be ignored based simply on
>>> timing/ordering of DMA controller registration. Is that acceptable?
>>>
>>
>> Yes, I think this option makes the most sense, and is just as
>> susceptible to probe order as the current implementation.
>
> OK great. Last two questions then:
>
> 1) Do you want me to revert the changes to acpi-dma.c, and simply handle
> the return value conversion inside __dma_request_slave_channel().

Yeah, no need to spread the complexity further than necessary.

> 2) What's the final call on the new API name?

What do you think of _reason?  I just read the existence of
dma_request_slave_channel_or_err() as an implication that
dma_request_slave_channel() may not fail.

> Just let me know on both - the changes are simple. Thanks.

Well thanks for hashing this back and forth, we can laugh about it
over a drink at the next conference.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/25/2013 12:45 PM, Dan Williams wrote:
> On Mon, Nov 25, 2013 at 11:30 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:

>> 2) What's the final call on the new API name?
> 
> What do you think of _reason?  I just read the existence of
> dma_request_slave_channel_or_err() as an implication that
> dma_request_slave_channel() may not fail.

OK, _reason makes good sense. Thanks.

>> Just let me know on both - the changes are simple. Thanks.
> 
> Well thanks for hashing this back and forth, we can laugh about it
> over a drink at the next conference.

:-)

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/25/2013 12:45 PM, Dan Williams wrote:
> On Mon, Nov 25, 2013 at 11:30 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:

>> 2) What's the final call on the new API name?
> 
> What do you think of _reason?  I just read the existence of
> dma_request_slave_channel_or_err() as an implication that
> dma_request_slave_channel() may not fail.

OK, _reason makes good sense. Thanks.

>> Just let me know on both - the changes are simple. Thanks.
> 
> Well thanks for hashing this back and forth, we can laugh about it
> over a drink at the next conference.

:-)

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Russell King - ARM Linux]

On Mon, Nov 25, 2013 at 10:42:52AM -0800, Dan Williams wrote:
> On Mon, Nov 25, 2013 at 10:00 AM, Russell King - ARM Linux
> <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> wrote:
> > On Mon, Nov 25, 2013 at 09:45:18AM -0800, Dan Williams wrote:
> >> Regardless of whether the driver was dma_request_channel as a
> >> fallback, it will currently use NULL to indicate an allocation
> >> failure.
> >
> > At the moment, dma_request_slave_channel()'s return values are valid
> > pointer or NULL.  I'd suggest as that's how it's been established,
> > that function is left alone - changing the return values in this kind
> > of invisible way is Really Bad(tm) because you can't check that it's
> > right in any future users - unless you're prepared to review every
> > single new user of this function for the next few years or more.
> >
> > Instead, leaving it as is and introducing a new function name with
> > the different return error method is the right way to do this.
> 
> I was attempting to tap the brakes on the number of request_channel
> apis in circulation.
> dma_request_channel
> dma_request_slave_channel
> dma_request_slave_channel_compat
> ... and now dma_request_slave_channel_reason
> 
> ...but given we already have things like samsung_dmadev_request() in
> the wild, tracking correct usage going forward will be an uphill
> battle.  We can do this the other way round.  Introduce the new api
> and delete the old one (after some time).

Yes, new and deprecate the old is the right way to do this.

> Can we make the new api not pass the 'defer' flag.  You mention it is
> for compat reasons, but since there are no users I'm not seeing how
> there can be compatibility concerns.  Can you elaborate?

Yes, I agree.  I don't think there's a compatibility concern here - with
the old interface, a non-present resource would be indicated as "does not
exist".

If we convert any error pointer including the one representing
-EPROBE_DEFER to the "does not exist" representation, we're not changing
the behaviour.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Russell King - ARM Linux]

On Mon, Nov 25, 2013 at 10:42:52AM -0800, Dan Williams wrote:
> On Mon, Nov 25, 2013 at 10:00 AM, Russell King - ARM Linux
> <linux@arm.linux.org.uk> wrote:
> > On Mon, Nov 25, 2013 at 09:45:18AM -0800, Dan Williams wrote:
> >> Regardless of whether the driver was dma_request_channel as a
> >> fallback, it will currently use NULL to indicate an allocation
> >> failure.
> >
> > At the moment, dma_request_slave_channel()'s return values are valid
> > pointer or NULL.  I'd suggest as that's how it's been established,
> > that function is left alone - changing the return values in this kind
> > of invisible way is Really Bad(tm) because you can't check that it's
> > right in any future users - unless you're prepared to review every
> > single new user of this function for the next few years or more.
> >
> > Instead, leaving it as is and introducing a new function name with
> > the different return error method is the right way to do this.
> 
> I was attempting to tap the brakes on the number of request_channel
> apis in circulation.
> dma_request_channel
> dma_request_slave_channel
> dma_request_slave_channel_compat
> ... and now dma_request_slave_channel_reason
> 
> ...but given we already have things like samsung_dmadev_request() in
> the wild, tracking correct usage going forward will be an uphill
> battle.  We can do this the other way round.  Introduce the new api
> and delete the old one (after some time).

Yes, new and deprecate the old is the right way to do this.

> Can we make the new api not pass the 'defer' flag.  You mention it is
> for compat reasons, but since there are no users I'm not seeing how
> there can be compatibility concerns.  Can you elaborate?

Yes, I agree.  I don't think there's a compatibility concern here - with
the old interface, a non-present resource would be indicated as "does not
exist".

If we convert any error pointer including the one representing
-EPROBE_DEFER to the "does not exist" representation, we're not changing
the behaviour.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Russell King - ARM Linux]

On Mon, Nov 25, 2013 at 10:26:18AM -0700, Stephen Warren wrote:
> On 11/22/2013 05:34 PM, Russell King - ARM Linux wrote:
> [... various discussions re: IS_ERR, IS_ERR_OR_NULL, etc.]
> 
> Russell, so if we document dma_request_slave_channel() as follows:
> 
> > /*
> >  * dma_request_slave_channel - try to allocate an exclusive slave channel
> > ...
> >  * Returns pointer to appropriate DMA channel on success or an error pointer.
> >  * In order to ease compatibility with other DMA request APIs, this function
> >  * guarantees NEVER to return NULL.
> >  */
> 
> Are you then OK with clients doing either of e.g.:
> 
> chan = dma_request_slave_channel(...);
> if (IS_ERR(chan))
> 	// This returns NULL or a valid handle/pointer
> 	chan = dma_request_channel()
> if (!chan)
> 	Here, chan is invalid;
> 	return;
> Here, chan is valid
> 
> or:
> 
> if (xxx) {
> 	chan = dma_request_slave_channel(...);
> 	// Convert to same error value as else{} block generates
> 	if (IS_ERR(chan))
> 		chan = NULL
> } else {
> 	// This returns NULL or a valid handle/pointer
> 	chan = dma_request_channel()
> }
> if (!chan)
> 	Here, chan is invalid
> 	return;
> Here, chan is valid

The cleaner way to write this is:

	chan = dma_request_slave_channel(...);
	if (IS_ERR(chan)) {
		chan = dma_request_channel();
		if (!chan)
			return;
	}

So, if you make it to this point, chan must be valid according to the
conditions on the API - you've applied the test individally to each
return function according to its documented behaviour.  If it does
happen to be NULL, that's not *your* problem as a user of the API.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Russell King - ARM Linux]

On Mon, Nov 25, 2013 at 10:26:18AM -0700, Stephen Warren wrote:
> On 11/22/2013 05:34 PM, Russell King - ARM Linux wrote:
> [... various discussions re: IS_ERR, IS_ERR_OR_NULL, etc.]
> 
> Russell, so if we document dma_request_slave_channel() as follows:
> 
> > /*
> >  * dma_request_slave_channel - try to allocate an exclusive slave channel
> > ...
> >  * Returns pointer to appropriate DMA channel on success or an error pointer.
> >  * In order to ease compatibility with other DMA request APIs, this function
> >  * guarantees NEVER to return NULL.
> >  */
> 
> Are you then OK with clients doing either of e.g.:
> 
> chan = dma_request_slave_channel(...);
> if (IS_ERR(chan))
> 	// This returns NULL or a valid handle/pointer
> 	chan = dma_request_channel()
> if (!chan)
> 	Here, chan is invalid;
> 	return;
> Here, chan is valid
> 
> or:
> 
> if (xxx) {
> 	chan = dma_request_slave_channel(...);
> 	// Convert to same error value as else{} block generates
> 	if (IS_ERR(chan))
> 		chan = NULL
> } else {
> 	// This returns NULL or a valid handle/pointer
> 	chan = dma_request_channel()
> }
> if (!chan)
> 	Here, chan is invalid
> 	return;
> Here, chan is valid

The cleaner way to write this is:

	chan = dma_request_slave_channel(...);
	if (IS_ERR(chan)) {
		chan = dma_request_channel();
		if (!chan)
			return;
	}

So, if you make it to this point, chan must be valid according to the
conditions on the API - you've applied the test individally to each
return function according to its documented behaviour.  If it does
happen to be NULL, that's not *your* problem as a user of the API.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/25/2013 10:53 AM, Russell King - ARM Linux wrote:
> On Mon, Nov 25, 2013 at 10:26:18AM -0700, Stephen Warren wrote:
>> On 11/22/2013 05:34 PM, Russell King - ARM Linux wrote:
>> [... various discussions re: IS_ERR, IS_ERR_OR_NULL, etc.]
>>
>> Russell, so if we document dma_request_slave_channel() as follows:
>>
>>> /*
>>>  * dma_request_slave_channel - try to allocate an exclusive slave channel
>>> ...
>>>  * Returns pointer to appropriate DMA channel on success or an error pointer.
>>>  * In order to ease compatibility with other DMA request APIs, this function
>>>  * guarantees NEVER to return NULL.
>>>  */
>>
>> Are you then OK with clients doing either of e.g.:
>>
>> chan = dma_request_slave_channel(...);
>> if (IS_ERR(chan))
>> 	// This returns NULL or a valid handle/pointer
>> 	chan = dma_request_channel()
>> if (!chan)
>> 	Here, chan is invalid;
>> 	return;
>> Here, chan is valid
>>
>> or:
>>
>> if (xxx) {
>> 	chan = dma_request_slave_channel(...);
>> 	// Convert to same error value as else{} block generates
>> 	if (IS_ERR(chan))
>> 		chan = NULL
>> } else {
>> 	// This returns NULL or a valid handle/pointer
>> 	chan = dma_request_channel()
>> }
>> if (!chan)
>> 	Here, chan is invalid
>> 	return;
>> Here, chan is valid
> 
> The cleaner way to write this is:
> 
> 	chan = dma_request_slave_channel(...);
> 	if (IS_ERR(chan)) {
> 		chan = dma_request_channel();
> 		if (!chan)
> 			return;
> 	}
> 
> So, if you make it to this point, chan must be valid according to the
> conditions on the API - you've applied the test individally to each
> return function according to its documented behaviour.  If it does
> happen to be NULL, that's not *your* problem as a user of the API.

As Dan pointed out, there are many drivers where DMA is optional, so
there's a lot of this sprinkled through the body of the driver:

if (chan) ...
if (!chan) ...

If we don't convert IS_ERR() values to NULL like I showed above, then
all those tests would need to be converted to something else. Can we
please avoid that?

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/25/2013 10:53 AM, Russell King - ARM Linux wrote:
> On Mon, Nov 25, 2013 at 10:26:18AM -0700, Stephen Warren wrote:
>> On 11/22/2013 05:34 PM, Russell King - ARM Linux wrote:
>> [... various discussions re: IS_ERR, IS_ERR_OR_NULL, etc.]
>>
>> Russell, so if we document dma_request_slave_channel() as follows:
>>
>>> /*
>>>  * dma_request_slave_channel - try to allocate an exclusive slave channel
>>> ...
>>>  * Returns pointer to appropriate DMA channel on success or an error pointer.
>>>  * In order to ease compatibility with other DMA request APIs, this function
>>>  * guarantees NEVER to return NULL.
>>>  */
>>
>> Are you then OK with clients doing either of e.g.:
>>
>> chan = dma_request_slave_channel(...);
>> if (IS_ERR(chan))
>> 	// This returns NULL or a valid handle/pointer
>> 	chan = dma_request_channel()
>> if (!chan)
>> 	Here, chan is invalid;
>> 	return;
>> Here, chan is valid
>>
>> or:
>>
>> if (xxx) {
>> 	chan = dma_request_slave_channel(...);
>> 	// Convert to same error value as else{} block generates
>> 	if (IS_ERR(chan))
>> 		chan = NULL
>> } else {
>> 	// This returns NULL or a valid handle/pointer
>> 	chan = dma_request_channel()
>> }
>> if (!chan)
>> 	Here, chan is invalid
>> 	return;
>> Here, chan is valid
> 
> The cleaner way to write this is:
> 
> 	chan = dma_request_slave_channel(...);
> 	if (IS_ERR(chan)) {
> 		chan = dma_request_channel();
> 		if (!chan)
> 			return;
> 	}
> 
> So, if you make it to this point, chan must be valid according to the
> conditions on the API - you've applied the test individally to each
> return function according to its documented behaviour.  If it does
> happen to be NULL, that's not *your* problem as a user of the API.

As Dan pointed out, there are many drivers where DMA is optional, so
there's a lot of this sprinkled through the body of the driver:

if (chan) ...
if (!chan) ...

If we don't convert IS_ERR() values to NULL like I showed above, then
all those tests would need to be converted to something else. Can we
please avoid that?

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Gerhard Sittig]

On Mon, Nov 25, 2013 at 10:57 -0700, Stephen Warren wrote:
> 
> As Dan pointed out, there are many drivers where DMA is optional, so
> there's a lot of this sprinkled through the body of the driver:
> 
> if (chan) ...
> if (!chan) ...
> 
> If we don't convert IS_ERR() values to NULL like I showed above, then
> all those tests would need to be converted to something else. Can we
> please avoid that?

Recently I had a similar situation with clocks.  It turned out to
be cumbersome to call allocation routines to assign the result
into state tracking variables, and to adjust the pointer to
become NULL in hindsight upon failure.  And I received feedback
that this feels dirty and somehow wrong.

What I did instead was to assign the allocation/lookup results to
local variables, then test them, and only assign to state
tracking variables when they are not error pointers (or expected
or acceptable errors which should go silently).

The shutdown logic then only had to check for the state tracking
variables against NULL, and release what was allocated as these
never could be errors.  Other references during the driver's
lifetime would be similar.

See 2771399a "fs_enet: cleanup clock API use" or b3bfce2bc "i2c:
mpc: cleanup clock API use" for an example.

Does this help in your case?  The "normalization" would be
concentrated in the acquisition spot, all error situations are
handled appropriately, and all other references in subsequent
code paths remain simple, and identical if there already are any.


virtually yours
Gerhard Sittig
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office-ynQEQJNshbs@public.gmane.org

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Gerhard Sittig]

On Mon, Nov 25, 2013 at 10:57 -0700, Stephen Warren wrote:
> 
> As Dan pointed out, there are many drivers where DMA is optional, so
> there's a lot of this sprinkled through the body of the driver:
> 
> if (chan) ...
> if (!chan) ...
> 
> If we don't convert IS_ERR() values to NULL like I showed above, then
> all those tests would need to be converted to something else. Can we
> please avoid that?

Recently I had a similar situation with clocks.  It turned out to
be cumbersome to call allocation routines to assign the result
into state tracking variables, and to adjust the pointer to
become NULL in hindsight upon failure.  And I received feedback
that this feels dirty and somehow wrong.

What I did instead was to assign the allocation/lookup results to
local variables, then test them, and only assign to state
tracking variables when they are not error pointers (or expected
or acceptable errors which should go silently).

The shutdown logic then only had to check for the state tracking
variables against NULL, and release what was allocated as these
never could be errors.  Other references during the driver's
lifetime would be similar.

See 2771399a "fs_enet: cleanup clock API use" or b3bfce2bc "i2c:
mpc: cleanup clock API use" for an example.

Does this help in your case?  The "normalization" would be
concentrated in the acquisition spot, all error situations are
handled appropriately, and all other references in subsequent
code paths remain simple, and identical if there already are any.


virtually yours
Gerhard Sittig
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Russell King - ARM Linux]

On Mon, Nov 25, 2013 at 09:28:08PM +0100, Gerhard Sittig wrote:
> See 2771399a "fs_enet: cleanup clock API use" or b3bfce2bc "i2c:
> mpc: cleanup clock API use" for an example.

And had I seen that change I'd have commented thusly:

+       /* make clock lookup non-fatal (the driver is shared among platforms),
+        * but require enable to succeed when a clock was specified/found,
+        * keep a reference to the clock upon successful acquisition
+        */
+       clk = devm_clk_get(&ofdev->dev, "per");
+       if (!IS_ERR(clk)) {
+               err = clk_prepare_enable(clk);
+               if (err) {
+                       ret = err;
+                       goto out_free_fpi;
+               }
+               fpi->clk_per = clk;
+       }

 out_put:
        of_node_put(fpi->phy_node);
+       if (fpi->clk_per)
+               clk_disable_unprepare(fpi->clk_per);

        of_node_put(fep->fpi->phy_node);
+       if (fep->fpi->clk_per)
+               clk_disable_unprepare(fep->fpi->clk_per);

So, lets consider what happens if clk_get() inside devm_clk_get() returns
NULL.

* devm_clk_get() allocates its tracking structure, and sets the clk pointer
  to be freed to NULL.
* !IS_ERR(NULL) is true, so we call clk_prepare_enable(NULL).  This succeeds.
* We store NULL into fpi->clk_per.
* The error cleanup/teardown paths check for a NULL pointer, and fail to
  call the CLK API in that case.

This is not very nice.  Better solution:

	fpi->clk_per = PTR_ERR(-EINVAL);
	clk = devm_clk_get(&ofdev->dev, "per");
	if (!IS_ERR(clk)) {
		err = clk_prepare_enable(clk);
		if (err) {
			ret = err;
			goto out_free_fpi;
		}
		fpi->clk_per = clk;
	}

...

        of_node_put(fpi->phy_node);
        if (!IS_ERR(fpi->clk_per))
                clk_disable_unprepare(fpi->clk_per);

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Russell King - ARM Linux]

On Mon, Nov 25, 2013 at 09:28:08PM +0100, Gerhard Sittig wrote:
> See 2771399a "fs_enet: cleanup clock API use" or b3bfce2bc "i2c:
> mpc: cleanup clock API use" for an example.

And had I seen that change I'd have commented thusly:

+       /* make clock lookup non-fatal (the driver is shared among platforms),
+        * but require enable to succeed when a clock was specified/found,
+        * keep a reference to the clock upon successful acquisition
+        */
+       clk = devm_clk_get(&ofdev->dev, "per");
+       if (!IS_ERR(clk)) {
+               err = clk_prepare_enable(clk);
+               if (err) {
+                       ret = err;
+                       goto out_free_fpi;
+               }
+               fpi->clk_per = clk;
+       }

 out_put:
        of_node_put(fpi->phy_node);
+       if (fpi->clk_per)
+               clk_disable_unprepare(fpi->clk_per);

        of_node_put(fep->fpi->phy_node);
+       if (fep->fpi->clk_per)
+               clk_disable_unprepare(fep->fpi->clk_per);

So, lets consider what happens if clk_get() inside devm_clk_get() returns
NULL.

* devm_clk_get() allocates its tracking structure, and sets the clk pointer
  to be freed to NULL.
* !IS_ERR(NULL) is true, so we call clk_prepare_enable(NULL).  This succeeds.
* We store NULL into fpi->clk_per.
* The error cleanup/teardown paths check for a NULL pointer, and fail to
  call the CLK API in that case.

This is not very nice.  Better solution:

	fpi->clk_per = PTR_ERR(-EINVAL);
	clk = devm_clk_get(&ofdev->dev, "per");
	if (!IS_ERR(clk)) {
		err = clk_prepare_enable(clk);
		if (err) {
			ret = err;
			goto out_free_fpi;
		}
		fpi->clk_per = clk;
	}

...

        of_node_put(fpi->phy_node);
        if (!IS_ERR(fpi->clk_per))
                clk_disable_unprepare(fpi->clk_per);

Re: NULL clock items (was: [PATCH 11/31] dma: add channel request API that supports deferred probe)

[Gerhard Sittig]

On Mon, Nov 25, 2013 at 20:52 +0000, Russell King - ARM Linux wrote:
> 
> [ ... 2771399a "fs_enet: cleanup clock API use" example ... ]
> [ ... NULL clocks won't get released, calls might get skipped ... ]

I agree that the NULL clock reference is not handled correctly in
that code.  Part of the issue is that NULL is both an
initialization value and a valid reference to something that was
acquired (and quite counter intuitive so).

This inability to tell the two reasons for NULL apart only
vanishes when each clock variable explicitly gets initialized or
pre-set to some ERR_PTR() value (or when the allocation and
assignment is unconditional, no code path depends on some other
condition).  I'm afraid that the source tree currently is not
there yet, and it may be quite some churn (with a lot of
potential for conflicts) to touch each driver, if it's at all
possible to identify all spots where those variables are NULL
because of
- static declarations without initializers
- static declarations with incomplete initializers
- memory allocation with "zeroes please" flags
- memset() calls
- clock acquisition code paths were not taken


Which platform or clock provider or specific clock driver exactly
is this mysterious instance which returns NULL for a valid clock?
Is this one or the very few instances easier to adjust and thus
(re-)gain certainty about correct operation with less effort and
much less risk of missing something?


> This is not very nice.  Better solution:
> 
> 	fpi->clk_per = PTR_ERR(-EINVAL);
> 	clk = devm_clk_get(&ofdev->dev, "per");
> 	if (!IS_ERR(clk)) {
> 		err = clk_prepare_enable(clk);
> 		if (err) {
> 			ret = err;
> 			goto out_free_fpi;
> 		}
> 		fpi->clk_per = clk;
> 	}
> 
> ...
> 
>         of_node_put(fpi->phy_node);
>         if (!IS_ERR(fpi->clk_per))
>                 clk_disable_unprepare(fpi->clk_per);

Assume in the above example that the fpi->clk_per assignment
would be in a conditional code path.  In that case the code is as
wrong (unpreparing a not acquired NULL reference) as leaking an
acquired NULL reference is.


virtually yours
Gerhard Sittig
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office-ynQEQJNshbs@public.gmane.org

NULL clock items (was: [PATCH 11/31] dma: add channel request API that supports deferred probe)

[Gerhard Sittig]

On Mon, Nov 25, 2013 at 20:52 +0000, Russell King - ARM Linux wrote:
> 
> [ ... 2771399a "fs_enet: cleanup clock API use" example ... ]
> [ ... NULL clocks won't get released, calls might get skipped ... ]

I agree that the NULL clock reference is not handled correctly in
that code.  Part of the issue is that NULL is both an
initialization value and a valid reference to something that was
acquired (and quite counter intuitive so).

This inability to tell the two reasons for NULL apart only
vanishes when each clock variable explicitly gets initialized or
pre-set to some ERR_PTR() value (or when the allocation and
assignment is unconditional, no code path depends on some other
condition).  I'm afraid that the source tree currently is not
there yet, and it may be quite some churn (with a lot of
potential for conflicts) to touch each driver, if it's at all
possible to identify all spots where those variables are NULL
because of
- static declarations without initializers
- static declarations with incomplete initializers
- memory allocation with "zeroes please" flags
- memset() calls
- clock acquisition code paths were not taken


Which platform or clock provider or specific clock driver exactly
is this mysterious instance which returns NULL for a valid clock?
Is this one or the very few instances easier to adjust and thus
(re-)gain certainty about correct operation with less effort and
much less risk of missing something?


> This is not very nice.  Better solution:
> 
> 	fpi->clk_per = PTR_ERR(-EINVAL);
> 	clk = devm_clk_get(&ofdev->dev, "per");
> 	if (!IS_ERR(clk)) {
> 		err = clk_prepare_enable(clk);
> 		if (err) {
> 			ret = err;
> 			goto out_free_fpi;
> 		}
> 		fpi->clk_per = clk;
> 	}
> 
> ...
> 
>         of_node_put(fpi->phy_node);
>         if (!IS_ERR(fpi->clk_per))
>                 clk_disable_unprepare(fpi->clk_per);

Assume in the above example that the fpi->clk_per assignment
would be in a conditional code path.  In that case the code is as
wrong (unpreparing a not acquired NULL reference) as leaking an
acquired NULL reference is.


virtually yours
Gerhard Sittig
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Thu, Nov 21, 2013 at 10:22 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> On 11/20/2013 08:22 PM, Dan Williams wrote:
> 2)
>
>         /* These first 3 lines are part of your patch */
>         chan = dma_request_slave_channel(dev, ch_name);
>         if (IS_ERR(chan)
>                 chan = NULL;
>         if (!chan) // This test and the above are IS_ERR_OR_NULL
>                 attempt allocation some other way;

No it isn't.  IS_ERR_OR_NULL means the api returns 3 states (channel,
null, error-pointer).  The client converting error-pointer to NULL
after the fact is explicit way to say that the client does not care
about the error value.  The client is simply throwing away the error
code and converting the result back into a pass fail.

>         /*
>          * This is code elsewhere in a driver where DMA is optional;
>          * that code must act differently based on whether a DMA
>          * channel was acquired or not. So, it tests chan against
>          * NULL.
>          */
>         if (!chan) // This test and the above IS_ERR are IS_ERR_OR_NULL
>                 return -ESOMETHING;

It's not, because at this point chan will never be an error pointer.
Sure you could do follow on cleanups to allow this driver to propagate
the dma_request_slave_channel error code up and change this to if
(IS_ERR(chan)) return PTR_ERR(chan), but that's incremental to the
initial conversion.

> In case (2) above, if the driver /only/ calls a modified
> dma_request_slave_channel(), all the checks could just be if
> (IS_ERR(chan)) instead - then problem solved.

It's not solved, you would need to audit the rest of the driver to
make sure that everywhere it checks a channel is NULL it checks for
IS_ERR instead.  That's a deeper / unnecessary rework for driver's
that don't care about the reason they did not get a channel.

> However, if the driver
> mixes the new dma_request_slave_channel() and the unconverted
> dma_request_channel(), it has to either (a) convert an ERR return from
> dma_request_slave_channel() to match dma_request_channel()'s NULL error

Yes, better to live with this situation and convert existing drivers
vs have a subset of drivers call a new
dma_request_slave_channel_or_err() API and then *still* need to
convert it to NULL.

> return, or (b) convert a NULL return from dma_request_channel() to match
> dma_request_slave_channel()'s ERR return. Without the conversion, all
> tests would have to use the deprecated IS_ERR_OR_NULL. Either of those
> conversion options converts an error value from 1 API into a
> theoretically valid return value from the other API, which is a bug.

Getting an error from dma_request_slave_channel() and converting that
value to NULL is a bug because dma_request_channel() would also return
NULL if it did not get a channel?  That's normalization, not a bug.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Thu, Nov 21, 2013 at 10:22 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 11/20/2013 08:22 PM, Dan Williams wrote:
> 2)
>
>         /* These first 3 lines are part of your patch */
>         chan = dma_request_slave_channel(dev, ch_name);
>         if (IS_ERR(chan)
>                 chan = NULL;
>         if (!chan) // This test and the above are IS_ERR_OR_NULL
>                 attempt allocation some other way;

No it isn't.  IS_ERR_OR_NULL means the api returns 3 states (channel,
null, error-pointer).  The client converting error-pointer to NULL
after the fact is explicit way to say that the client does not care
about the error value.  The client is simply throwing away the error
code and converting the result back into a pass fail.

>         /*
>          * This is code elsewhere in a driver where DMA is optional;
>          * that code must act differently based on whether a DMA
>          * channel was acquired or not. So, it tests chan against
>          * NULL.
>          */
>         if (!chan) // This test and the above IS_ERR are IS_ERR_OR_NULL
>                 return -ESOMETHING;

It's not, because at this point chan will never be an error pointer.
Sure you could do follow on cleanups to allow this driver to propagate
the dma_request_slave_channel error code up and change this to if
(IS_ERR(chan)) return PTR_ERR(chan), but that's incremental to the
initial conversion.

> In case (2) above, if the driver /only/ calls a modified
> dma_request_slave_channel(), all the checks could just be if
> (IS_ERR(chan)) instead - then problem solved.

It's not solved, you would need to audit the rest of the driver to
make sure that everywhere it checks a channel is NULL it checks for
IS_ERR instead.  That's a deeper / unnecessary rework for driver's
that don't care about the reason they did not get a channel.

> However, if the driver
> mixes the new dma_request_slave_channel() and the unconverted
> dma_request_channel(), it has to either (a) convert an ERR return from
> dma_request_slave_channel() to match dma_request_channel()'s NULL error

Yes, better to live with this situation and convert existing drivers
vs have a subset of drivers call a new
dma_request_slave_channel_or_err() API and then *still* need to
convert it to NULL.

> return, or (b) convert a NULL return from dma_request_channel() to match
> dma_request_slave_channel()'s ERR return. Without the conversion, all
> tests would have to use the deprecated IS_ERR_OR_NULL. Either of those
> conversion options converts an error value from 1 API into a
> theoretically valid return value from the other API, which is a bug.

Getting an error from dma_request_slave_channel() and converting that
value to NULL is a bug because dma_request_channel() would also return
NULL if it did not get a channel?  That's normalization, not a bug.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/22/2013 04:45 PM, Dan Williams wrote:
> On Thu, Nov 21, 2013 at 10:22 AM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>> On 11/20/2013 08:22 PM, Dan Williams wrote:
>> 2)
>>
>>         /* These first 3 lines are part of your patch */
>>         chan = dma_request_slave_channel(dev, ch_name);
>>         if (IS_ERR(chan)
>>                 chan = NULL;
>>         if (!chan) // This test and the above are IS_ERR_OR_NULL
>>                 attempt allocation some other way;
> 
> No it isn't.  IS_ERR_OR_NULL means the api returns 3 states (channel,
> null, error-pointer).  The client converting error-pointer to NULL
> after the fact is explicit way to say that the client does not care
> about the error value.  The client is simply throwing away the error
> code and converting the result back into a pass fail.

The client can only translate an ERR value to NULL if it knows that the
API will never return NULL. If the API could return NULL, then this
translation uses a valid return value to represent the error case.
Functions that return an ERR value or a valid value do NOT in general
say anything either way about a return value of NULL.

While this translation isn't *exactly* the same as an API returning 3
states, it is almost identical; the translation is only possible if the
set of numerically possible return values from the function are
segmented into 3 sets:

a) Valid
b) An ERR value
c) NULL (which is never returned)

I believe the important point in Russell's argument against
IS_ERR_OR_NULL is that the segmentation should be limited to two sets
(a, b) or (a, c) and not 3. I don't /think/ it was relevant whether the
function segmented the return values into 3 sets just so it could
guarantee that it didn't return one of those sets.

If that's not the case, the following would indeed solve the problem easily:

> /**
>  * dma_request_slave_channel - try to allocate an exclusive slave channel
...
>  * Returns pointer to appropriate DMA channel on success or an error pointer.
>  * In order to ease compatibility with other DMA request APIs, this function
>  * guarantees NEVER to return NULL.
>  */

>>         /*
>>          * This is code elsewhere in a driver where DMA is optional;
>>          * that code must act differently based on whether a DMA
>>          * channel was acquired or not. So, it tests chan against
>>          * NULL.
>>          */
>>         if (!chan) // This test and the above IS_ERR are IS_ERR_OR_NULL
>>                 return -ESOMETHING;
> 
> It's not, because at this point chan will never be an error pointer.

It's the combination of the two. IS_ERR_OR_NULL is two separate tests in
one macro. Simply separating the two tests into separate lines of code
doesn't change what the code is doing.

> Sure you could do follow on cleanups to allow this driver to propagate
> the dma_request_slave_channel error code up and change this to if
> (IS_ERR(chan)) return PTR_ERR(chan), but that's incremental to the
> initial conversion.
> 
>> In case (2) above, if the driver /only/ calls a modified
>> dma_request_slave_channel(), all the checks could just be if
>> (IS_ERR(chan)) instead - then problem solved.
> 
> It's not solved, you would need to audit the rest of the driver to
> make sure that everywhere it checks a channel is NULL it checks for
> IS_ERR instead.  That's a deeper / unnecessary rework for driver's
> that don't care about the reason they did not get a channel.

I was of course assuming that the auditing would be done, and indeed
when I first started work on this conversion, it's exactly what I was
doing. That's why I said *all* checks, not just "the first check".

>> However, if the driver
>> mixes the new dma_request_slave_channel() and the unconverted
>> dma_request_channel(), it has to either (a) convert an ERR return from
>> dma_request_slave_channel() to match dma_request_channel()'s NULL error
> 
> Yes, better to live with this situation and convert existing drivers
> vs have a subset of drivers call a new
> dma_request_slave_channel_or_err() API and then *still* need to
> convert it to NULL.
> 
>> return, or (b) convert a NULL return from dma_request_channel() to match
>> dma_request_slave_channel()'s ERR return. Without the conversion, all
>> tests would have to use the deprecated IS_ERR_OR_NULL. Either of those
>> conversion options converts an error value from 1 API into a
>> theoretically valid return value from the other API, which is a bug.
> 
> Getting an error from dma_request_slave_channel() and converting that
> value to NULL is a bug because dma_request_channel() would also return
> NULL if it did not get a channel?  That's normalization, not a bug.

No, it's a bug because if dma_request_slave_channel() is documented to
return valid-or-ERR, then assuming that it can never return NULL is
inconsistent with that. The translation is only possible if it's
documented to return valid-or-ERR-but-never-NULL.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/22/2013 04:45 PM, Dan Williams wrote:
> On Thu, Nov 21, 2013 at 10:22 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> On 11/20/2013 08:22 PM, Dan Williams wrote:
>> 2)
>>
>>         /* These first 3 lines are part of your patch */
>>         chan = dma_request_slave_channel(dev, ch_name);
>>         if (IS_ERR(chan)
>>                 chan = NULL;
>>         if (!chan) // This test and the above are IS_ERR_OR_NULL
>>                 attempt allocation some other way;
> 
> No it isn't.  IS_ERR_OR_NULL means the api returns 3 states (channel,
> null, error-pointer).  The client converting error-pointer to NULL
> after the fact is explicit way to say that the client does not care
> about the error value.  The client is simply throwing away the error
> code and converting the result back into a pass fail.

The client can only translate an ERR value to NULL if it knows that the
API will never return NULL. If the API could return NULL, then this
translation uses a valid return value to represent the error case.
Functions that return an ERR value or a valid value do NOT in general
say anything either way about a return value of NULL.

While this translation isn't *exactly* the same as an API returning 3
states, it is almost identical; the translation is only possible if the
set of numerically possible return values from the function are
segmented into 3 sets:

a) Valid
b) An ERR value
c) NULL (which is never returned)

I believe the important point in Russell's argument against
IS_ERR_OR_NULL is that the segmentation should be limited to two sets
(a, b) or (a, c) and not 3. I don't /think/ it was relevant whether the
function segmented the return values into 3 sets just so it could
guarantee that it didn't return one of those sets.

If that's not the case, the following would indeed solve the problem easily:

> /**
>  * dma_request_slave_channel - try to allocate an exclusive slave channel
...
>  * Returns pointer to appropriate DMA channel on success or an error pointer.
>  * In order to ease compatibility with other DMA request APIs, this function
>  * guarantees NEVER to return NULL.
>  */

>>         /*
>>          * This is code elsewhere in a driver where DMA is optional;
>>          * that code must act differently based on whether a DMA
>>          * channel was acquired or not. So, it tests chan against
>>          * NULL.
>>          */
>>         if (!chan) // This test and the above IS_ERR are IS_ERR_OR_NULL
>>                 return -ESOMETHING;
> 
> It's not, because at this point chan will never be an error pointer.

It's the combination of the two. IS_ERR_OR_NULL is two separate tests in
one macro. Simply separating the two tests into separate lines of code
doesn't change what the code is doing.

> Sure you could do follow on cleanups to allow this driver to propagate
> the dma_request_slave_channel error code up and change this to if
> (IS_ERR(chan)) return PTR_ERR(chan), but that's incremental to the
> initial conversion.
> 
>> In case (2) above, if the driver /only/ calls a modified
>> dma_request_slave_channel(), all the checks could just be if
>> (IS_ERR(chan)) instead - then problem solved.
> 
> It's not solved, you would need to audit the rest of the driver to
> make sure that everywhere it checks a channel is NULL it checks for
> IS_ERR instead.  That's a deeper / unnecessary rework for driver's
> that don't care about the reason they did not get a channel.

I was of course assuming that the auditing would be done, and indeed
when I first started work on this conversion, it's exactly what I was
doing. That's why I said *all* checks, not just "the first check".

>> However, if the driver
>> mixes the new dma_request_slave_channel() and the unconverted
>> dma_request_channel(), it has to either (a) convert an ERR return from
>> dma_request_slave_channel() to match dma_request_channel()'s NULL error
> 
> Yes, better to live with this situation and convert existing drivers
> vs have a subset of drivers call a new
> dma_request_slave_channel_or_err() API and then *still* need to
> convert it to NULL.
> 
>> return, or (b) convert a NULL return from dma_request_channel() to match
>> dma_request_slave_channel()'s ERR return. Without the conversion, all
>> tests would have to use the deprecated IS_ERR_OR_NULL. Either of those
>> conversion options converts an error value from 1 API into a
>> theoretically valid return value from the other API, which is a bug.
> 
> Getting an error from dma_request_slave_channel() and converting that
> value to NULL is a bug because dma_request_channel() would also return
> NULL if it did not get a channel?  That's normalization, not a bug.

No, it's a bug because if dma_request_slave_channel() is documented to
return valid-or-ERR, then assuming that it can never return NULL is
inconsistent with that. The translation is only possible if it's
documented to return valid-or-ERR-but-never-NULL.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Fri, Nov 22, 2013 at 4:17 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> No, it's a bug because if dma_request_slave_channel() is documented to
> return valid-or-ERR, then assuming that it can never return NULL is
> inconsistent with that. The translation is only possible if it's
> documented to return valid-or-ERR-but-never-NULL.

Yes!  We are in violent agreement about this point.  Make
dma_request_slave_channel return valid-or-ERR-but-never-NULL, and show
me the compat user that would care if it got an EPROBE_DEFER instead
of ENODEV.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

On Fri, Nov 22, 2013 at 4:17 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> No, it's a bug because if dma_request_slave_channel() is documented to
> return valid-or-ERR, then assuming that it can never return NULL is
> inconsistent with that. The translation is only possible if it's
> documented to return valid-or-ERR-but-never-NULL.

Yes!  We are in violent agreement about this point.  Make
dma_request_slave_channel return valid-or-ERR-but-never-NULL, and show
me the compat user that would care if it got an EPROBE_DEFER instead
of ENODEV.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/15/2013 01:54 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> dma_request_slave_channel() simply returns NULL whenever DMA channel
> lookup fails. Lookup could fail for two distinct reasons:
> 
> a) No DMA specification exists for the channel name.
>    This includes situations where no DMA specifications exist at all, or
>    other general lookup problems.
> 
> b) A DMA specification does exist, yet the driver for that channel is not
>    yet registered.
> 
> Case (b) should trigger deferred probe in client drivers. However, since
> they have no way to differentiate the two situations, it cannot.
> 
> Implement new function dma_request_slave_channel_or_err(), which performs
> identically to dma_request_slave_channel(), except that it returns an
> error-pointer rather than NULL, which allows callers to detect when
> deferred probe should occur.
...

...
> diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h

> +static inline struct dma_chan *dma_request_slave_channel_or_err(
> +					struct device *dev, const char *name)
> +{
> +	return ERR_PTR(-ENODEV);
> +}

That requires the following to be squashed into it, which I'll apply
locally:

diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index b908b0fda72b..f156c145fad2 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -22,6 +22,7 @@
 #define LINUX_DMAENGINE_H

 #include <linux/device.h>
+#include <linux/err.h>
 #include <linux/uio.h>
 #include <linux/bug.h>
 #include <linux/scatterlist.h>

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/15/2013 01:54 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> dma_request_slave_channel() simply returns NULL whenever DMA channel
> lookup fails. Lookup could fail for two distinct reasons:
> 
> a) No DMA specification exists for the channel name.
>    This includes situations where no DMA specifications exist at all, or
>    other general lookup problems.
> 
> b) A DMA specification does exist, yet the driver for that channel is not
>    yet registered.
> 
> Case (b) should trigger deferred probe in client drivers. However, since
> they have no way to differentiate the two situations, it cannot.
> 
> Implement new function dma_request_slave_channel_or_err(), which performs
> identically to dma_request_slave_channel(), except that it returns an
> error-pointer rather than NULL, which allows callers to detect when
> deferred probe should occur.
...

...
> diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h

> +static inline struct dma_chan *dma_request_slave_channel_or_err(
> +					struct device *dev, const char *name)
> +{
> +	return ERR_PTR(-ENODEV);
> +}

That requires the following to be squashed into it, which I'll apply
locally:

diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index b908b0fda72b..f156c145fad2 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -22,6 +22,7 @@
 #define LINUX_DMAENGINE_H

 #include <linux/device.h>
+#include <linux/err.h>
 #include <linux/uio.h>
 #include <linux/bug.h>
 #include <linux/scatterlist.h>

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

A question about the patch:

On Fri, Nov 15, 2013 at 12:54 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
[..]
> diff --git a/drivers/dma/of-dma.c b/drivers/dma/of-dma.c
> index 0b88dd3d05f4..928141f6f21b 100644
> --- a/drivers/dma/of-dma.c
> +++ b/drivers/dma/of-dma.c
> @@ -181,11 +181,13 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
>
>                 of_node_put(dma_spec.np);
>
> +               if (!ofdma && defer)
> +                       return ERR_PTR(-EPROBE_DEFER);
>                 if (chan)
>                         return chan;
>         }

Why do we need to make this conditional on the value of 'defer'?  If
the client cares it will propagate the error if it does not care then
nothing is gained by converting this to -ENODEV.

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Dan Williams]

A question about the patch:

On Fri, Nov 15, 2013 at 12:54 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> From: Stephen Warren <swarren@nvidia.com>
[..]
> diff --git a/drivers/dma/of-dma.c b/drivers/dma/of-dma.c
> index 0b88dd3d05f4..928141f6f21b 100644
> --- a/drivers/dma/of-dma.c
> +++ b/drivers/dma/of-dma.c
> @@ -181,11 +181,13 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
>
>                 of_node_put(dma_spec.np);
>
> +               if (!ofdma && defer)
> +                       return ERR_PTR(-EPROBE_DEFER);
>                 if (chan)
>                         return chan;
>         }

Why do we need to make this conditional on the value of 'defer'?  If
the client cares it will propagate the error if it does not care then
nothing is gained by converting this to -ENODEV.

Re: [PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/22/2013 04:50 PM, Dan Williams wrote:
> A question about the patch:
> 
> On Fri, Nov 15, 2013 at 12:54 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:
>> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> [..]
>> diff --git a/drivers/dma/of-dma.c b/drivers/dma/of-dma.c
>> index 0b88dd3d05f4..928141f6f21b 100644
>> --- a/drivers/dma/of-dma.c
>> +++ b/drivers/dma/of-dma.c
>> @@ -181,11 +181,13 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
>>
>>                 of_node_put(dma_spec.np);
>>
>> +               if (!ofdma && defer)
>> +                       return ERR_PTR(-EPROBE_DEFER);
>>                 if (chan)
>>                         return chan;
>>         }
> 
> Why do we need to make this conditional on the value of 'defer'?  If
> the client cares it will propagate the error if it does not care then
> nothing is gained by converting this to -ENODEV.

The function ends up being called from two code-paths. One of which
wants the new behaviour of deferring probe if a valid DMA specifier is
found but there's not registered driver for it, and the other
(compatibility) path wants exactly the old behaviour. The flag is passed
down from dma_request_slave_channel() (old behaviour) or
dma_request_slave_channel_or_err() (new behaviour).

[PATCH 11/31] dma: add channel request API that supports deferred probe

[Stephen Warren]

On 11/22/2013 04:50 PM, Dan Williams wrote:
> A question about the patch:
> 
> On Fri, Nov 15, 2013 at 12:54 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> From: Stephen Warren <swarren@nvidia.com>
> [..]
>> diff --git a/drivers/dma/of-dma.c b/drivers/dma/of-dma.c
>> index 0b88dd3d05f4..928141f6f21b 100644
>> --- a/drivers/dma/of-dma.c
>> +++ b/drivers/dma/of-dma.c
>> @@ -181,11 +181,13 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
>>
>>                 of_node_put(dma_spec.np);
>>
>> +               if (!ofdma && defer)
>> +                       return ERR_PTR(-EPROBE_DEFER);
>>                 if (chan)
>>                         return chan;
>>         }
> 
> Why do we need to make this conditional on the value of 'defer'?  If
> the client cares it will propagate the error if it does not care then
> nothing is gained by converting this to -ENODEV.

The function ends up being called from two code-paths. One of which
wants the new behaviour of deferring probe if a valid DMA specifier is
found but there's not registered driver for it, and the other
(compatibility) path wants exactly the old behaviour. The flag is passed
down from dma_request_slave_channel() (old behaviour) or
dma_request_slave_channel_or_err() (new behaviour).

[PATCH 12/31] dma: tegra: use reset framework

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Dan Williams <dan.j.williams-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/dma/tegra20-apb-dma.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index 73654e33f13b..afa5844c9346 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -32,8 +32,8 @@
 #include <linux/platform_device.h>
 #include <linux/pm.h>
 #include <linux/pm_runtime.h>
+#include <linux/reset.h>
 #include <linux/slab.h>
-#include <linux/clk/tegra.h>
 
 #include "dmaengine.h"
 
@@ -208,6 +208,7 @@ struct tegra_dma {
 	struct dma_device		dma_dev;
 	struct device			*dev;
 	struct clk			*dma_clk;
+	struct reset_control		*rst;
 	spinlock_t			global_lock;
 	void __iomem			*base_addr;
 	const struct tegra_dma_chip_data *chip_data;
@@ -1282,6 +1283,12 @@ static int tegra_dma_probe(struct platform_device *pdev)
 		return PTR_ERR(tdma->dma_clk);
 	}
 
+	tdma->rst = devm_reset_control_get(&pdev->dev, "dma");
+	if (IS_ERR(tdma->rst)) {
+		dev_err(&pdev->dev, "Error: Missing reset\n");
+		return PTR_ERR(tdma->rst);
+	}
+
 	spin_lock_init(&tdma->global_lock);
 
 	pm_runtime_enable(&pdev->dev);
@@ -1302,9 +1309,9 @@ static int tegra_dma_probe(struct platform_device *pdev)
 	}
 
 	/* Reset DMA controller */
-	tegra_periph_reset_assert(tdma->dma_clk);
+	reset_control_assert(tdma->rst);
 	udelay(2);
-	tegra_periph_reset_deassert(tdma->dma_clk);
+	reset_control_deassert(tdma->rst);
 
 	/* Enable global DMA registers */
 	tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
-- 
1.8.1.5

[PATCH 12/31] dma: tegra: use reset framework

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/dma/tegra20-apb-dma.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index 73654e33f13b..afa5844c9346 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -32,8 +32,8 @@
 #include <linux/platform_device.h>
 #include <linux/pm.h>
 #include <linux/pm_runtime.h>
+#include <linux/reset.h>
 #include <linux/slab.h>
-#include <linux/clk/tegra.h>
 
 #include "dmaengine.h"
 
@@ -208,6 +208,7 @@ struct tegra_dma {
 	struct dma_device		dma_dev;
 	struct device			*dev;
 	struct clk			*dma_clk;
+	struct reset_control		*rst;
 	spinlock_t			global_lock;
 	void __iomem			*base_addr;
 	const struct tegra_dma_chip_data *chip_data;
@@ -1282,6 +1283,12 @@ static int tegra_dma_probe(struct platform_device *pdev)
 		return PTR_ERR(tdma->dma_clk);
 	}
 
+	tdma->rst = devm_reset_control_get(&pdev->dev, "dma");
+	if (IS_ERR(tdma->rst)) {
+		dev_err(&pdev->dev, "Error: Missing reset\n");
+		return PTR_ERR(tdma->rst);
+	}
+
 	spin_lock_init(&tdma->global_lock);
 
 	pm_runtime_enable(&pdev->dev);
@@ -1302,9 +1309,9 @@ static int tegra_dma_probe(struct platform_device *pdev)
 	}
 
 	/* Reset DMA controller */
-	tegra_periph_reset_assert(tdma->dma_clk);
+	reset_control_assert(tdma->rst);
 	udelay(2);
-	tegra_periph_reset_deassert(tdma->dma_clk);
+	reset_control_deassert(tdma->rst);
 
 	/* Enable global DMA registers */
 	tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
-- 
1.8.1.5

Re: [PATCH 12/31] dma: tegra: use reset framework

[Stephen Warren]

On 11/15/2013 01:54 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.

Dan, Vinod,

It looks like I'm waiting for an ack on this patch. (although I forgot
to Cc Vinod when I first sent it, so adding him now, and hence quoting
the entire patch).

> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Dan Williams <dan.j.williams-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/dma/tegra20-apb-dma.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
> index 73654e33f13b..afa5844c9346 100644
> --- a/drivers/dma/tegra20-apb-dma.c
> +++ b/drivers/dma/tegra20-apb-dma.c
> @@ -32,8 +32,8 @@
>  #include <linux/platform_device.h>
>  #include <linux/pm.h>
>  #include <linux/pm_runtime.h>
> +#include <linux/reset.h>
>  #include <linux/slab.h>
> -#include <linux/clk/tegra.h>
>  
>  #include "dmaengine.h"
>  
> @@ -208,6 +208,7 @@ struct tegra_dma {
>  	struct dma_device		dma_dev;
>  	struct device			*dev;
>  	struct clk			*dma_clk;
> +	struct reset_control		*rst;
>  	spinlock_t			global_lock;
>  	void __iomem			*base_addr;
>  	const struct tegra_dma_chip_data *chip_data;
> @@ -1282,6 +1283,12 @@ static int tegra_dma_probe(struct platform_device *pdev)
>  		return PTR_ERR(tdma->dma_clk);
>  	}
>  
> +	tdma->rst = devm_reset_control_get(&pdev->dev, "dma");
> +	if (IS_ERR(tdma->rst)) {
> +		dev_err(&pdev->dev, "Error: Missing reset\n");
> +		return PTR_ERR(tdma->rst);
> +	}
> +
>  	spin_lock_init(&tdma->global_lock);
>  
>  	pm_runtime_enable(&pdev->dev);
> @@ -1302,9 +1309,9 @@ static int tegra_dma_probe(struct platform_device *pdev)
>  	}
>  
>  	/* Reset DMA controller */
> -	tegra_periph_reset_assert(tdma->dma_clk);
> +	reset_control_assert(tdma->rst);
>  	udelay(2);
> -	tegra_periph_reset_deassert(tdma->dma_clk);
> +	reset_control_deassert(tdma->rst);
>  
>  	/* Enable global DMA registers */
>  	tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
> 

[PATCH 12/31] dma: tegra: use reset framework

[Stephen Warren]

On 11/15/2013 01:54 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.

Dan, Vinod,

It looks like I'm waiting for an ack on this patch. (although I forgot
to Cc Vinod when I first sent it, so adding him now, and hence quoting
the entire patch).

> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/dma/tegra20-apb-dma.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
> index 73654e33f13b..afa5844c9346 100644
> --- a/drivers/dma/tegra20-apb-dma.c
> +++ b/drivers/dma/tegra20-apb-dma.c
> @@ -32,8 +32,8 @@
>  #include <linux/platform_device.h>
>  #include <linux/pm.h>
>  #include <linux/pm_runtime.h>
> +#include <linux/reset.h>
>  #include <linux/slab.h>
> -#include <linux/clk/tegra.h>
>  
>  #include "dmaengine.h"
>  
> @@ -208,6 +208,7 @@ struct tegra_dma {
>  	struct dma_device		dma_dev;
>  	struct device			*dev;
>  	struct clk			*dma_clk;
> +	struct reset_control		*rst;
>  	spinlock_t			global_lock;
>  	void __iomem			*base_addr;
>  	const struct tegra_dma_chip_data *chip_data;
> @@ -1282,6 +1283,12 @@ static int tegra_dma_probe(struct platform_device *pdev)
>  		return PTR_ERR(tdma->dma_clk);
>  	}
>  
> +	tdma->rst = devm_reset_control_get(&pdev->dev, "dma");
> +	if (IS_ERR(tdma->rst)) {
> +		dev_err(&pdev->dev, "Error: Missing reset\n");
> +		return PTR_ERR(tdma->rst);
> +	}
> +
>  	spin_lock_init(&tdma->global_lock);
>  
>  	pm_runtime_enable(&pdev->dev);
> @@ -1302,9 +1309,9 @@ static int tegra_dma_probe(struct platform_device *pdev)
>  	}
>  
>  	/* Reset DMA controller */
> -	tegra_periph_reset_assert(tdma->dma_clk);
> +	reset_control_assert(tdma->rst);
>  	udelay(2);
> -	tegra_periph_reset_deassert(tdma->dma_clk);
> +	reset_control_deassert(tdma->rst);
>  
>  	/* Enable global DMA registers */
>  	tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
> 

Re: [PATCH 12/31] dma: tegra: use reset framework

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1243 bytes --]

On Fri, Nov 15, 2013 at 01:54:07PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Dan Williams <dan.j.williams-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/dma/tegra20-apb-dma.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)

Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

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[PATCH 12/31] dma: tegra: use reset framework

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:54:07PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/dma/tegra20-apb-dma.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)

Reviewed-by: Thierry Reding <treding@nvidia.com>
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[PATCH 13/31] dma: tegra: register as an OF DMA controller

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Call of_dma_controller_register() so that DMA clients can look up the
Tegra DMA controller using standard APIs. This requires the OF filter
function to save off the DMA slave ID, and for tegra_dma_slave_config()
not to over-write this information; once DMA client drivers are converted
to dma_request_slave_channel() and DT-based lookups, they won't set this
field of struct dma_slave_config anymore.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Dan Williams <dan.j.williams-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/dma/tegra20-apb-dma.c | 36 +++++++++++++++++++++++++++++++++---
 1 file changed, 33 insertions(+), 3 deletions(-)

diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index afa5844c9346..72b76c755947 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -1,7 +1,7 @@
 /*
  * DMA driver for Nvidia's Tegra20 APB DMA controller.
  *
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,6 +29,7 @@
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
+#include <linux/of_dma.h>
 #include <linux/platform_device.h>
 #include <linux/pm.h>
 #include <linux/pm_runtime.h>
@@ -199,6 +200,7 @@ struct tegra_dma_channel {
 	void			*callback_param;
 
 	/* Channel-slave specific configuration */
+	unsigned int slave_id;
 	struct dma_slave_config dma_sconfig;
 	struct tegra_dma_channel_regs	channel_reg;
 };
@@ -340,6 +342,8 @@ static int tegra_dma_slave_config(struct dma_chan *dc,
 	}
 
 	memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
+	if (!tdc->slave_id)
+		tdc->slave_id = sconfig->slave_id;
 	tdc->config_init = true;
 	return 0;
 }
@@ -942,7 +946,7 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
 	ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
 
 	csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
-	csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
+	csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
 	if (flags & DMA_PREP_INTERRUPT)
 		csr |= TEGRA_APBDMA_CSR_IE_EOC;
 
@@ -1086,7 +1090,7 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
 	csr |= TEGRA_APBDMA_CSR_FLOW;
 	if (flags & DMA_PREP_INTERRUPT)
 		csr |= TEGRA_APBDMA_CSR_IE_EOC;
-	csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
+	csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
 
 	apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
 
@@ -1206,6 +1210,8 @@ static void tegra_dma_free_chan_resources(struct dma_chan *dc)
 		kfree(sg_req);
 	}
 	clk_disable_unprepare(tdma->dma_clk);
+
+	tdc->slave_id = 0;
 }
 
 /* Tegra20 specific DMA controller information */
@@ -1245,6 +1251,26 @@ static const struct of_device_id tegra_dma_of_match[] = {
 };
 MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
 
+static struct platform_driver tegra_dmac_driver;
+
+bool tegra_dma_filter_fn(struct dma_chan *dc, void *param)
+{
+	u32 slave_id = *(u32 *)param;
+	struct tegra_dma_channel *tdc;
+
+	if (dc->device->dev->driver != &tegra_dmac_driver.driver)
+		return false;
+
+	tdc = to_tegra_dma_chan(dc);
+	tdc->slave_id = slave_id;
+
+	return true;
+}
+
+static struct of_dma_filter_info tegra_dma_info = {
+	.filter_fn = tegra_dma_filter_fn,
+};
+
 static int tegra_dma_probe(struct platform_device *pdev)
 {
 	struct resource	*res;
@@ -1383,6 +1409,10 @@ static int tegra_dma_probe(struct platform_device *pdev)
 		goto err_irq;
 	}
 
+	tegra_dma_info.dma_cap = tdma->dma_dev.cap_mask;
+	ret = of_dma_controller_register(pdev->dev.of_node,
+					 of_dma_simple_xlate, &tegra_dma_info);
+
 	dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
 			cdata->nr_channels);
 	return 0;
-- 
1.8.1.5

[PATCH 13/31] dma: tegra: register as an OF DMA controller

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Call of_dma_controller_register() so that DMA clients can look up the
Tegra DMA controller using standard APIs. This requires the OF filter
function to save off the DMA slave ID, and for tegra_dma_slave_config()
not to over-write this information; once DMA client drivers are converted
to dma_request_slave_channel() and DT-based lookups, they won't set this
field of struct dma_slave_config anymore.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/dma/tegra20-apb-dma.c | 36 +++++++++++++++++++++++++++++++++---
 1 file changed, 33 insertions(+), 3 deletions(-)

diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index afa5844c9346..72b76c755947 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -1,7 +1,7 @@
 /*
  * DMA driver for Nvidia's Tegra20 APB DMA controller.
  *
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,6 +29,7 @@
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
+#include <linux/of_dma.h>
 #include <linux/platform_device.h>
 #include <linux/pm.h>
 #include <linux/pm_runtime.h>
@@ -199,6 +200,7 @@ struct tegra_dma_channel {
 	void			*callback_param;
 
 	/* Channel-slave specific configuration */
+	unsigned int slave_id;
 	struct dma_slave_config dma_sconfig;
 	struct tegra_dma_channel_regs	channel_reg;
 };
@@ -340,6 +342,8 @@ static int tegra_dma_slave_config(struct dma_chan *dc,
 	}
 
 	memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
+	if (!tdc->slave_id)
+		tdc->slave_id = sconfig->slave_id;
 	tdc->config_init = true;
 	return 0;
 }
@@ -942,7 +946,7 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
 	ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
 
 	csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
-	csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
+	csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
 	if (flags & DMA_PREP_INTERRUPT)
 		csr |= TEGRA_APBDMA_CSR_IE_EOC;
 
@@ -1086,7 +1090,7 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
 	csr |= TEGRA_APBDMA_CSR_FLOW;
 	if (flags & DMA_PREP_INTERRUPT)
 		csr |= TEGRA_APBDMA_CSR_IE_EOC;
-	csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
+	csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
 
 	apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
 
@@ -1206,6 +1210,8 @@ static void tegra_dma_free_chan_resources(struct dma_chan *dc)
 		kfree(sg_req);
 	}
 	clk_disable_unprepare(tdma->dma_clk);
+
+	tdc->slave_id = 0;
 }
 
 /* Tegra20 specific DMA controller information */
@@ -1245,6 +1251,26 @@ static const struct of_device_id tegra_dma_of_match[] = {
 };
 MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
 
+static struct platform_driver tegra_dmac_driver;
+
+bool tegra_dma_filter_fn(struct dma_chan *dc, void *param)
+{
+	u32 slave_id = *(u32 *)param;
+	struct tegra_dma_channel *tdc;
+
+	if (dc->device->dev->driver != &tegra_dmac_driver.driver)
+		return false;
+
+	tdc = to_tegra_dma_chan(dc);
+	tdc->slave_id = slave_id;
+
+	return true;
+}
+
+static struct of_dma_filter_info tegra_dma_info = {
+	.filter_fn = tegra_dma_filter_fn,
+};
+
 static int tegra_dma_probe(struct platform_device *pdev)
 {
 	struct resource	*res;
@@ -1383,6 +1409,10 @@ static int tegra_dma_probe(struct platform_device *pdev)
 		goto err_irq;
 	}
 
+	tegra_dma_info.dma_cap = tdma->dma_dev.cap_mask;
+	ret = of_dma_controller_register(pdev->dev.of_node,
+					 of_dma_simple_xlate, &tegra_dma_info);
+
 	dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
 			cdata->nr_channels);
 	return 0;
-- 
1.8.1.5

Re: [PATCH 13/31] dma: tegra: register as an OF DMA controller

[Arnd Bergmann]

On Friday 15 November 2013, Stephen Warren wrote:
> +bool tegra_dma_filter_fn(struct dma_chan *dc, void *param)
> +{
> +       u32 slave_id = *(u32 *)param;
> +       struct tegra_dma_channel *tdc;
> +
> +       if (dc->device->dev->driver != &tegra_dmac_driver.driver)
> +               return false;
> +
> +       tdc = to_tegra_dma_chan(dc);
> +       tdc->slave_id = slave_id;
> +
> +       return true;
> +}
> +
> +static struct of_dma_filter_info tegra_dma_info = {
> +       .filter_fn = tegra_dma_filter_fn,
> +};
> +
>  static int tegra_dma_probe(struct platform_device *pdev)
>  {
>         struct resource *res;
> @@ -1383,6 +1409,10 @@ static int tegra_dma_probe(struct platform_device *pdev)
>                 goto err_irq;
>         }
>  
> +       tegra_dma_info.dma_cap = tdma->dma_dev.cap_mask;
> +       ret = of_dma_controller_register(pdev->dev.of_node,
> +                                        of_dma_simple_xlate, &tegra_dma_info);
> +

I would suggest to use a custom xlate() function based on
dma_get_slave_channel() that was added recently: Iterating through all
channels is not necessary any more.

	Arnd

[PATCH 13/31] dma: tegra: register as an OF DMA controller

[Arnd Bergmann]

On Friday 15 November 2013, Stephen Warren wrote:
> +bool tegra_dma_filter_fn(struct dma_chan *dc, void *param)
> +{
> +       u32 slave_id = *(u32 *)param;
> +       struct tegra_dma_channel *tdc;
> +
> +       if (dc->device->dev->driver != &tegra_dmac_driver.driver)
> +               return false;
> +
> +       tdc = to_tegra_dma_chan(dc);
> +       tdc->slave_id = slave_id;
> +
> +       return true;
> +}
> +
> +static struct of_dma_filter_info tegra_dma_info = {
> +       .filter_fn = tegra_dma_filter_fn,
> +};
> +
>  static int tegra_dma_probe(struct platform_device *pdev)
>  {
>         struct resource *res;
> @@ -1383,6 +1409,10 @@ static int tegra_dma_probe(struct platform_device *pdev)
>                 goto err_irq;
>         }
>  
> +       tegra_dma_info.dma_cap = tdma->dma_dev.cap_mask;
> +       ret = of_dma_controller_register(pdev->dev.of_node,
> +                                        of_dma_simple_xlate, &tegra_dma_info);
> +

I would suggest to use a custom xlate() function based on
dma_get_slave_channel() that was added recently: Iterating through all
channels is not necessary any more.

	Arnd

Re: [PATCH 13/31] dma: tegra: register as an OF DMA controller

[Stephen Warren]

On 11/20/2013 08:28 AM, Arnd Bergmann wrote:
> On Friday 15 November 2013, Stephen Warren wrote:
...
>> @@ -1383,6 +1409,10 @@ static int tegra_dma_probe(struct platform_device *pdev)
>>                 goto err_irq;
>>         }
>>  
>> +       tegra_dma_info.dma_cap = tdma->dma_dev.cap_mask;
>> +       ret = of_dma_controller_register(pdev->dev.of_node,
>> +                                        of_dma_simple_xlate, &tegra_dma_info);
>> +
> 
> I would suggest to use a custom xlate() function based on
> dma_get_slave_channel() that was added recently: Iterating through all
> channels is not necessary any more.

OK, I've converted to that locally, and will repost soon.

[PATCH 13/31] dma: tegra: register as an OF DMA controller

[Stephen Warren]

On 11/20/2013 08:28 AM, Arnd Bergmann wrote:
> On Friday 15 November 2013, Stephen Warren wrote:
...
>> @@ -1383,6 +1409,10 @@ static int tegra_dma_probe(struct platform_device *pdev)
>>                 goto err_irq;
>>         }
>>  
>> +       tegra_dma_info.dma_cap = tdma->dma_dev.cap_mask;
>> +       ret = of_dma_controller_register(pdev->dev.of_node,
>> +                                        of_dma_simple_xlate, &tegra_dma_info);
>> +
> 
> I would suggest to use a custom xlate() function based on
> dma_get_slave_channel() that was added recently: Iterating through all
> channels is not necessary any more.

OK, I've converted to that locally, and will repost soon.

[PATCH 14/31] ASoC: dmaengine: support deferred probe for DMA channels

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Enhance dmaengine_pcm_request_chan_of() to support deferred probe for
DMA channels, by using the new dma_request_slave_channel_or_err() API.
This prevents snd_dmaengine_pcm_register() from succeeding without
acquiring DMA channels due to the relevant DMA controller not yet being
registered.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Liam Girdwood <lgirdwood-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 sound/soc/soc-generic-dmaengine-pcm.c | 77 +++++++++++++++++++++++++----------
 1 file changed, 55 insertions(+), 22 deletions(-)

diff --git a/sound/soc/soc-generic-dmaengine-pcm.c b/sound/soc/soc-generic-dmaengine-pcm.c
index cbc9c96ce1f4..f7e65e1552ef 100644
--- a/sound/soc/soc-generic-dmaengine-pcm.c
+++ b/sound/soc/soc-generic-dmaengine-pcm.c
@@ -284,24 +284,52 @@ static const char * const dmaengine_pcm_dma_channel_names[] = {
 	[SNDRV_PCM_STREAM_CAPTURE] = "rx",
 };
 
-static void dmaengine_pcm_request_chan_of(struct dmaengine_pcm *pcm,
-	struct device *dev)
+static int dmaengine_pcm_request_chan_of(struct dmaengine_pcm *pcm,
+					 struct device *dev)
 {
 	unsigned int i;
+	const char *name;
+	struct dma_chan *chan;
 
 	if ((pcm->flags & (SND_DMAENGINE_PCM_FLAG_NO_DT |
 			   SND_DMAENGINE_PCM_FLAG_CUSTOM_CHANNEL_NAME)) ||
 	    !dev->of_node)
-		return;
+		return 0;
+
+	for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE;
+	     i++) {
+		if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
+			name = "rx-tx";
+		else
+			name = dmaengine_pcm_dma_channel_names[i];
+		chan = dma_request_slave_channel_or_err(dev, name);
+		if (IS_ERR(chan)) {
+			if (PTR_ERR(pcm->chan[i]) == -EPROBE_DEFER)
+				return -EPROBE_DEFER;
+			pcm->chan[i] = NULL;
+		} else
+			pcm->chan[i] = chan;
+		if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
+			break;
+	}
 
-	if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX) {
-		pcm->chan[0] = dma_request_slave_channel(dev, "rx-tx");
+	if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
 		pcm->chan[1] = pcm->chan[0];
-	} else {
-		for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE; i++) {
-			pcm->chan[i] = dma_request_slave_channel(dev,
-					dmaengine_pcm_dma_channel_names[i]);
-		}
+
+	return 0;
+}
+
+static void dmaengine_pcm_release_chan(struct dmaengine_pcm *pcm)
+{
+	unsigned int i;
+
+	for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE;
+	     i++) {
+		if (!pcm->chan[i])
+			continue;
+		dma_release_channel(pcm->chan[i]);
+		if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
+			break;
 	}
 }
 
@@ -315,6 +343,7 @@ int snd_dmaengine_pcm_register(struct device *dev,
 	const struct snd_dmaengine_pcm_config *config, unsigned int flags)
 {
 	struct dmaengine_pcm *pcm;
+	int ret;
 
 	pcm = kzalloc(sizeof(*pcm), GFP_KERNEL);
 	if (!pcm)
@@ -323,14 +352,26 @@ int snd_dmaengine_pcm_register(struct device *dev,
 	pcm->config = config;
 	pcm->flags = flags;
 
-	dmaengine_pcm_request_chan_of(pcm, dev);
+	ret = dmaengine_pcm_request_chan_of(pcm, dev);
+	if (ret)
+		goto err_free_pcm;
 
 	if (flags & SND_DMAENGINE_PCM_FLAG_NO_RESIDUE)
-		return snd_soc_add_platform(dev, &pcm->platform,
+		ret = snd_soc_add_platform(dev, &pcm->platform,
 				&dmaengine_no_residue_pcm_platform);
 	else
-		return snd_soc_add_platform(dev, &pcm->platform,
+		ret = snd_soc_add_platform(dev, &pcm->platform,
 				&dmaengine_pcm_platform);
+	if (ret)
+		goto err_free_dma;
+
+	return 0;
+
+err_free_dma:
+	dmaengine_pcm_release_chan(pcm);
+err_free_pcm:
+	kfree(pcm);
+	return ret;
 }
 EXPORT_SYMBOL_GPL(snd_dmaengine_pcm_register);
 
@@ -345,7 +386,6 @@ void snd_dmaengine_pcm_unregister(struct device *dev)
 {
 	struct snd_soc_platform *platform;
 	struct dmaengine_pcm *pcm;
-	unsigned int i;
 
 	platform = snd_soc_lookup_platform(dev);
 	if (!platform)
@@ -353,15 +393,8 @@ void snd_dmaengine_pcm_unregister(struct device *dev)
 
 	pcm = soc_platform_to_pcm(platform);
 
-	for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE; i++) {
-		if (pcm->chan[i]) {
-			dma_release_channel(pcm->chan[i]);
-			if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
-				break;
-		}
-	}
-
 	snd_soc_remove_platform(platform);
+	dmaengine_pcm_release_chan(pcm);
 	kfree(pcm);
 }
 EXPORT_SYMBOL_GPL(snd_dmaengine_pcm_unregister);
-- 
1.8.1.5

[PATCH 14/31] ASoC: dmaengine: support deferred probe for DMA channels

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Enhance dmaengine_pcm_request_chan_of() to support deferred probe for
DMA channels, by using the new dma_request_slave_channel_or_err() API.
This prevents snd_dmaengine_pcm_register() from succeeding without
acquiring DMA channels due to the relevant DMA controller not yet being
registered.

Cc: treding at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: alsa-devel at alsa-project.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 sound/soc/soc-generic-dmaengine-pcm.c | 77 +++++++++++++++++++++++++----------
 1 file changed, 55 insertions(+), 22 deletions(-)

diff --git a/sound/soc/soc-generic-dmaengine-pcm.c b/sound/soc/soc-generic-dmaengine-pcm.c
index cbc9c96ce1f4..f7e65e1552ef 100644
--- a/sound/soc/soc-generic-dmaengine-pcm.c
+++ b/sound/soc/soc-generic-dmaengine-pcm.c
@@ -284,24 +284,52 @@ static const char * const dmaengine_pcm_dma_channel_names[] = {
 	[SNDRV_PCM_STREAM_CAPTURE] = "rx",
 };
 
-static void dmaengine_pcm_request_chan_of(struct dmaengine_pcm *pcm,
-	struct device *dev)
+static int dmaengine_pcm_request_chan_of(struct dmaengine_pcm *pcm,
+					 struct device *dev)
 {
 	unsigned int i;
+	const char *name;
+	struct dma_chan *chan;
 
 	if ((pcm->flags & (SND_DMAENGINE_PCM_FLAG_NO_DT |
 			   SND_DMAENGINE_PCM_FLAG_CUSTOM_CHANNEL_NAME)) ||
 	    !dev->of_node)
-		return;
+		return 0;
+
+	for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE;
+	     i++) {
+		if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
+			name = "rx-tx";
+		else
+			name = dmaengine_pcm_dma_channel_names[i];
+		chan = dma_request_slave_channel_or_err(dev, name);
+		if (IS_ERR(chan)) {
+			if (PTR_ERR(pcm->chan[i]) == -EPROBE_DEFER)
+				return -EPROBE_DEFER;
+			pcm->chan[i] = NULL;
+		} else
+			pcm->chan[i] = chan;
+		if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
+			break;
+	}
 
-	if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX) {
-		pcm->chan[0] = dma_request_slave_channel(dev, "rx-tx");
+	if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
 		pcm->chan[1] = pcm->chan[0];
-	} else {
-		for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE; i++) {
-			pcm->chan[i] = dma_request_slave_channel(dev,
-					dmaengine_pcm_dma_channel_names[i]);
-		}
+
+	return 0;
+}
+
+static void dmaengine_pcm_release_chan(struct dmaengine_pcm *pcm)
+{
+	unsigned int i;
+
+	for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE;
+	     i++) {
+		if (!pcm->chan[i])
+			continue;
+		dma_release_channel(pcm->chan[i]);
+		if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
+			break;
 	}
 }
 
@@ -315,6 +343,7 @@ int snd_dmaengine_pcm_register(struct device *dev,
 	const struct snd_dmaengine_pcm_config *config, unsigned int flags)
 {
 	struct dmaengine_pcm *pcm;
+	int ret;
 
 	pcm = kzalloc(sizeof(*pcm), GFP_KERNEL);
 	if (!pcm)
@@ -323,14 +352,26 @@ int snd_dmaengine_pcm_register(struct device *dev,
 	pcm->config = config;
 	pcm->flags = flags;
 
-	dmaengine_pcm_request_chan_of(pcm, dev);
+	ret = dmaengine_pcm_request_chan_of(pcm, dev);
+	if (ret)
+		goto err_free_pcm;
 
 	if (flags & SND_DMAENGINE_PCM_FLAG_NO_RESIDUE)
-		return snd_soc_add_platform(dev, &pcm->platform,
+		ret = snd_soc_add_platform(dev, &pcm->platform,
 				&dmaengine_no_residue_pcm_platform);
 	else
-		return snd_soc_add_platform(dev, &pcm->platform,
+		ret = snd_soc_add_platform(dev, &pcm->platform,
 				&dmaengine_pcm_platform);
+	if (ret)
+		goto err_free_dma;
+
+	return 0;
+
+err_free_dma:
+	dmaengine_pcm_release_chan(pcm);
+err_free_pcm:
+	kfree(pcm);
+	return ret;
 }
 EXPORT_SYMBOL_GPL(snd_dmaengine_pcm_register);
 
@@ -345,7 +386,6 @@ void snd_dmaengine_pcm_unregister(struct device *dev)
 {
 	struct snd_soc_platform *platform;
 	struct dmaengine_pcm *pcm;
-	unsigned int i;
 
 	platform = snd_soc_lookup_platform(dev);
 	if (!platform)
@@ -353,15 +393,8 @@ void snd_dmaengine_pcm_unregister(struct device *dev)
 
 	pcm = soc_platform_to_pcm(platform);
 
-	for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE; i++) {
-		if (pcm->chan[i]) {
-			dma_release_channel(pcm->chan[i]);
-			if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
-				break;
-		}
-	}
-
 	snd_soc_remove_platform(platform);
+	dmaengine_pcm_release_chan(pcm);
 	kfree(pcm);
 }
 EXPORT_SYMBOL_GPL(snd_dmaengine_pcm_unregister);
-- 
1.8.1.5

Re: [PATCH 14/31] ASoC: dmaengine: support deferred probe for DMA channels

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 563 bytes --]

On Fri, Nov 15, 2013 at 01:54:09PM -0700, Stephen Warren wrote:

> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.

Acked-by: Mark Brown <broonie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

but please do provide the branch (ideally just the ASoC core stuff)
since other drivers ought to be being enhanced to use this.

[-- Attachment #2: Digital signature --]
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[PATCH 14/31] ASoC: dmaengine: support deferred probe for DMA channels

[Mark Brown]

On Fri, Nov 15, 2013 at 01:54:09PM -0700, Stephen Warren wrote:

> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.

Acked-by: Mark Brown <broonie@linaro.org>

but please do provide the branch (ideally just the ASoC core stuff)
since other drivers ought to be being enhanced to use this.
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Re: [alsa-devel] [PATCH 14/31] ASoC: dmaengine: support deferred probe for DMA channels

[Lars-Peter Clausen]

On 11/15/2013 09:54 PM, Stephen Warren wrote:
>  
> @@ -315,6 +343,7 @@ int snd_dmaengine_pcm_register(struct device *dev,
>  	const struct snd_dmaengine_pcm_config *config, unsigned int flags)
>  {
>  	struct dmaengine_pcm *pcm;
> +	int ret;
>  
>  	pcm = kzalloc(sizeof(*pcm), GFP_KERNEL);
>  	if (!pcm)
> @@ -323,14 +352,26 @@ int snd_dmaengine_pcm_register(struct device *dev,
>  	pcm->config = config;
>  	pcm->flags = flags;
>  
> -	dmaengine_pcm_request_chan_of(pcm, dev);
> +	ret = dmaengine_pcm_request_chan_of(pcm, dev);
> +	if (ret)
> +		goto err_free_pcm;
>  

We should still call dmaengine_pcm_release_chan() in case requesting the
first channel succeeded, but the second did not.

>  	if (flags & SND_DMAENGINE_PCM_FLAG_NO_RESIDUE)
> -		return snd_soc_add_platform(dev, &pcm->platform,
> +		ret = snd_soc_add_platform(dev, &pcm->platform,
>  				&dmaengine_no_residue_pcm_platform);
>  	else
> -		return snd_soc_add_platform(dev, &pcm->platform,
> +		ret = snd_soc_add_platform(dev, &pcm->platform,
>  				&dmaengine_pcm_platform);
> +	if (ret)
> +		goto err_free_dma;
> +
> +	return 0;
> +
> +err_free_dma:
> +	dmaengine_pcm_release_chan(pcm);
> +err_free_pcm:
> +	kfree(pcm);
> +	return ret;
>  }
>  EXPORT_SYMBOL_GPL(snd_dmaengine_pcm_register);
[...]

[alsa-devel] [PATCH 14/31] ASoC: dmaengine: support deferred probe for DMA channels

[Lars-Peter Clausen]

On 11/15/2013 09:54 PM, Stephen Warren wrote:
>  
> @@ -315,6 +343,7 @@ int snd_dmaengine_pcm_register(struct device *dev,
>  	const struct snd_dmaengine_pcm_config *config, unsigned int flags)
>  {
>  	struct dmaengine_pcm *pcm;
> +	int ret;
>  
>  	pcm = kzalloc(sizeof(*pcm), GFP_KERNEL);
>  	if (!pcm)
> @@ -323,14 +352,26 @@ int snd_dmaengine_pcm_register(struct device *dev,
>  	pcm->config = config;
>  	pcm->flags = flags;
>  
> -	dmaengine_pcm_request_chan_of(pcm, dev);
> +	ret = dmaengine_pcm_request_chan_of(pcm, dev);
> +	if (ret)
> +		goto err_free_pcm;
>  

We should still call dmaengine_pcm_release_chan() in case requesting the
first channel succeeded, but the second did not.

>  	if (flags & SND_DMAENGINE_PCM_FLAG_NO_RESIDUE)
> -		return snd_soc_add_platform(dev, &pcm->platform,
> +		ret = snd_soc_add_platform(dev, &pcm->platform,
>  				&dmaengine_no_residue_pcm_platform);
>  	else
> -		return snd_soc_add_platform(dev, &pcm->platform,
> +		ret = snd_soc_add_platform(dev, &pcm->platform,
>  				&dmaengine_pcm_platform);
> +	if (ret)
> +		goto err_free_dma;
> +
> +	return 0;
> +
> +err_free_dma:
> +	dmaengine_pcm_release_chan(pcm);
> +err_free_pcm:
> +	kfree(pcm);
> +	return ret;
>  }
>  EXPORT_SYMBOL_GPL(snd_dmaengine_pcm_register);
[...]

Re: [alsa-devel] [PATCH 14/31] ASoC: dmaengine: support deferred probe for DMA channels

[Stephen Warren]

On 11/16/2013 03:49 AM, Lars-Peter Clausen wrote:
> On 11/15/2013 09:54 PM, Stephen Warren wrote:
>>  
>> @@ -315,6 +343,7 @@ int snd_dmaengine_pcm_register(struct device *dev,
>>  	const struct snd_dmaengine_pcm_config *config, unsigned int flags)
>>  {
>>  	struct dmaengine_pcm *pcm;
>> +	int ret;
>>  
>>  	pcm = kzalloc(sizeof(*pcm), GFP_KERNEL);
>>  	if (!pcm)
>> @@ -323,14 +352,26 @@ int snd_dmaengine_pcm_register(struct device *dev,
>>  	pcm->config = config;
>>  	pcm->flags = flags;
>>  
>> -	dmaengine_pcm_request_chan_of(pcm, dev);
>> +	ret = dmaengine_pcm_request_chan_of(pcm, dev);
>> +	if (ret)
>> +		goto err_free_pcm;
>>  
> 
> We should still call dmaengine_pcm_release_chan() in case requesting the
> first channel succeeded, but the second did not.

Oh yes, I'd meant to do that. I'll modify that goto, and remove the
now-unused err_free_pcm label. Thanks.

> 
>>  	if (flags & SND_DMAENGINE_PCM_FLAG_NO_RESIDUE)
>> -		return snd_soc_add_platform(dev, &pcm->platform,
>> +		ret = snd_soc_add_platform(dev, &pcm->platform,
>>  				&dmaengine_no_residue_pcm_platform);
>>  	else
>> -		return snd_soc_add_platform(dev, &pcm->platform,
>> +		ret = snd_soc_add_platform(dev, &pcm->platform,
>>  				&dmaengine_pcm_platform);
>> +	if (ret)
>> +		goto err_free_dma;
>> +
>> +	return 0;
>> +
>> +err_free_dma:
>> +	dmaengine_pcm_release_chan(pcm);
>> +err_free_pcm:
>> +	kfree(pcm);
>> +	return ret;
>>  }
>>  EXPORT_SYMBOL_GPL(snd_dmaengine_pcm_register);
> [...]

[alsa-devel] [PATCH 14/31] ASoC: dmaengine: support deferred probe for DMA channels

[Stephen Warren]

On 11/16/2013 03:49 AM, Lars-Peter Clausen wrote:
> On 11/15/2013 09:54 PM, Stephen Warren wrote:
>>  
>> @@ -315,6 +343,7 @@ int snd_dmaengine_pcm_register(struct device *dev,
>>  	const struct snd_dmaengine_pcm_config *config, unsigned int flags)
>>  {
>>  	struct dmaengine_pcm *pcm;
>> +	int ret;
>>  
>>  	pcm = kzalloc(sizeof(*pcm), GFP_KERNEL);
>>  	if (!pcm)
>> @@ -323,14 +352,26 @@ int snd_dmaengine_pcm_register(struct device *dev,
>>  	pcm->config = config;
>>  	pcm->flags = flags;
>>  
>> -	dmaengine_pcm_request_chan_of(pcm, dev);
>> +	ret = dmaengine_pcm_request_chan_of(pcm, dev);
>> +	if (ret)
>> +		goto err_free_pcm;
>>  
> 
> We should still call dmaengine_pcm_release_chan() in case requesting the
> first channel succeeded, but the second did not.

Oh yes, I'd meant to do that. I'll modify that goto, and remove the
now-unused err_free_pcm label. Thanks.

> 
>>  	if (flags & SND_DMAENGINE_PCM_FLAG_NO_RESIDUE)
>> -		return snd_soc_add_platform(dev, &pcm->platform,
>> +		ret = snd_soc_add_platform(dev, &pcm->platform,
>>  				&dmaengine_no_residue_pcm_platform);
>>  	else
>> -		return snd_soc_add_platform(dev, &pcm->platform,
>> +		ret = snd_soc_add_platform(dev, &pcm->platform,
>>  				&dmaengine_pcm_platform);
>> +	if (ret)
>> +		goto err_free_dma;
>> +
>> +	return 0;
>> +
>> +err_free_dma:
>> +	dmaengine_pcm_release_chan(pcm);
>> +err_free_pcm:
>> +	kfree(pcm);
>> +	return ret;
>>  }
>>  EXPORT_SYMBOL_GPL(snd_dmaengine_pcm_register);
> [...]

[PATCH 15/31] ASoC: dmaengine: add custom DMA config to snd_dmaengine_pcm_config

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Add fields to struct snd_dmaengine_pcm_config to allow custom:

- DMA channel names.

  This is useful when the default "tx" and "rx" channel names don't
  apply, for example if a HW module supports multiple channels, each
  having different DMA channel names. This is the case with the FIFOs
  in Tegra's AHUB. This new facility can replace
  SND_DMAENGINE_PCM_FLAG_CUSTOM_CHANNEL_NAME.

- DMA device

  This allows requesting DMA channels for a device other than the device
  which is registering the "PCM" driver. This is quite unusual, but is
  currently useful on Tegra. In much HW, and in Tegra20, each DAI HW
  module contains its own FIFOs which DMA writes to. However, in Tegra30,
  the DMA FIFOs were split out AHUB HW module, which then routes the data
  through a cross-bar, and into the DAI HW modules. However, the current
  ASoC driver structure does not expose this detail, and acts as if the
  FIFOs are still part of the DAI HW modules. Consequently, the "PCM"
  driver is registered with the DAI HW module, yet the DMA channels must
  be looked up in the AHUB HW module's device tree node. This new config
  field allows that to happen. Eventually, the Tegra drivers will be
  reworked to fully expose the AHUB, and this config field can be
  removed.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Liam Girdwood <lgirdwood-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 include/sound/dmaengine_pcm.h         | 6 ++++++
 sound/soc/soc-generic-dmaengine-pcm.c | 9 +++++++--
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/include/sound/dmaengine_pcm.h b/include/sound/dmaengine_pcm.h
index 15017311f2e9..87e9d481d7b6 100644
--- a/include/sound/dmaengine_pcm.h
+++ b/include/sound/dmaengine_pcm.h
@@ -114,6 +114,10 @@ void snd_dmaengine_pcm_set_config_from_dai_data(
  * @compat_filter_fn: Will be used as the filter function when requesting a
  *  channel for platforms which do not use devicetree. The filter parameter
  *  will be the DAI's DMA data.
+ * @dma_dev: If set, request DMA channel on this device rather than the DAI
+ *  device.
+ * @chan_names: If set, these custom DMA channel names will be requested at
+ *  registration time.
  * @pcm_hardware: snd_pcm_hardware struct to be used for the PCM.
  * @prealloc_buffer_size: Size of the preallocated audio buffer.
  *
@@ -130,6 +134,8 @@ struct snd_dmaengine_pcm_config {
 			struct snd_soc_pcm_runtime *rtd,
 			struct snd_pcm_substream *substream);
 	dma_filter_fn compat_filter_fn;
+	struct device *dma_dev;
+	const char *chan_names[SNDRV_PCM_STREAM_LAST + 1];
 
 	const struct snd_pcm_hardware *pcm_hardware;
 	unsigned int prealloc_buffer_size;
diff --git a/sound/soc/soc-generic-dmaengine-pcm.c b/sound/soc/soc-generic-dmaengine-pcm.c
index f7e65e1552ef..40e0943a06b8 100644
--- a/sound/soc/soc-generic-dmaengine-pcm.c
+++ b/sound/soc/soc-generic-dmaengine-pcm.c
@@ -285,7 +285,7 @@ static const char * const dmaengine_pcm_dma_channel_names[] = {
 };
 
 static int dmaengine_pcm_request_chan_of(struct dmaengine_pcm *pcm,
-					 struct device *dev)
+	struct device *dev, const struct snd_dmaengine_pcm_config *config)
 {
 	unsigned int i;
 	const char *name;
@@ -296,12 +296,17 @@ static int dmaengine_pcm_request_chan_of(struct dmaengine_pcm *pcm,
 	    !dev->of_node)
 		return 0;
 
+	if (config->dma_dev)
+		dev = config->dma_dev;
+
 	for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE;
 	     i++) {
 		if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
 			name = "rx-tx";
 		else
 			name = dmaengine_pcm_dma_channel_names[i];
+		if (config->chan_names[i])
+			name = config->chan_names[i];
 		chan = dma_request_slave_channel_or_err(dev, name);
 		if (IS_ERR(chan)) {
 			if (PTR_ERR(pcm->chan[i]) == -EPROBE_DEFER)
@@ -352,7 +357,7 @@ int snd_dmaengine_pcm_register(struct device *dev,
 	pcm->config = config;
 	pcm->flags = flags;
 
-	ret = dmaengine_pcm_request_chan_of(pcm, dev);
+	ret = dmaengine_pcm_request_chan_of(pcm, dev, config);
 	if (ret)
 		goto err_free_pcm;
 
-- 
1.8.1.5

[PATCH 15/31] ASoC: dmaengine: add custom DMA config to snd_dmaengine_pcm_config

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Add fields to struct snd_dmaengine_pcm_config to allow custom:

- DMA channel names.

  This is useful when the default "tx" and "rx" channel names don't
  apply, for example if a HW module supports multiple channels, each
  having different DMA channel names. This is the case with the FIFOs
  in Tegra's AHUB. This new facility can replace
  SND_DMAENGINE_PCM_FLAG_CUSTOM_CHANNEL_NAME.

- DMA device

  This allows requesting DMA channels for a device other than the device
  which is registering the "PCM" driver. This is quite unusual, but is
  currently useful on Tegra. In much HW, and in Tegra20, each DAI HW
  module contains its own FIFOs which DMA writes to. However, in Tegra30,
  the DMA FIFOs were split out AHUB HW module, which then routes the data
  through a cross-bar, and into the DAI HW modules. However, the current
  ASoC driver structure does not expose this detail, and acts as if the
  FIFOs are still part of the DAI HW modules. Consequently, the "PCM"
  driver is registered with the DAI HW module, yet the DMA channels must
  be looked up in the AHUB HW module's device tree node. This new config
  field allows that to happen. Eventually, the Tegra drivers will be
  reworked to fully expose the AHUB, and this config field can be
  removed.

Cc: treding at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: alsa-devel at alsa-project.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 include/sound/dmaengine_pcm.h         | 6 ++++++
 sound/soc/soc-generic-dmaengine-pcm.c | 9 +++++++--
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/include/sound/dmaengine_pcm.h b/include/sound/dmaengine_pcm.h
index 15017311f2e9..87e9d481d7b6 100644
--- a/include/sound/dmaengine_pcm.h
+++ b/include/sound/dmaengine_pcm.h
@@ -114,6 +114,10 @@ void snd_dmaengine_pcm_set_config_from_dai_data(
  * @compat_filter_fn: Will be used as the filter function when requesting a
  *  channel for platforms which do not use devicetree. The filter parameter
  *  will be the DAI's DMA data.
+ * @dma_dev: If set, request DMA channel on this device rather than the DAI
+ *  device.
+ * @chan_names: If set, these custom DMA channel names will be requested at
+ *  registration time.
  * @pcm_hardware: snd_pcm_hardware struct to be used for the PCM.
  * @prealloc_buffer_size: Size of the preallocated audio buffer.
  *
@@ -130,6 +134,8 @@ struct snd_dmaengine_pcm_config {
 			struct snd_soc_pcm_runtime *rtd,
 			struct snd_pcm_substream *substream);
 	dma_filter_fn compat_filter_fn;
+	struct device *dma_dev;
+	const char *chan_names[SNDRV_PCM_STREAM_LAST + 1];
 
 	const struct snd_pcm_hardware *pcm_hardware;
 	unsigned int prealloc_buffer_size;
diff --git a/sound/soc/soc-generic-dmaengine-pcm.c b/sound/soc/soc-generic-dmaengine-pcm.c
index f7e65e1552ef..40e0943a06b8 100644
--- a/sound/soc/soc-generic-dmaengine-pcm.c
+++ b/sound/soc/soc-generic-dmaengine-pcm.c
@@ -285,7 +285,7 @@ static const char * const dmaengine_pcm_dma_channel_names[] = {
 };
 
 static int dmaengine_pcm_request_chan_of(struct dmaengine_pcm *pcm,
-					 struct device *dev)
+	struct device *dev, const struct snd_dmaengine_pcm_config *config)
 {
 	unsigned int i;
 	const char *name;
@@ -296,12 +296,17 @@ static int dmaengine_pcm_request_chan_of(struct dmaengine_pcm *pcm,
 	    !dev->of_node)
 		return 0;
 
+	if (config->dma_dev)
+		dev = config->dma_dev;
+
 	for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE;
 	     i++) {
 		if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
 			name = "rx-tx";
 		else
 			name = dmaengine_pcm_dma_channel_names[i];
+		if (config->chan_names[i])
+			name = config->chan_names[i];
 		chan = dma_request_slave_channel_or_err(dev, name);
 		if (IS_ERR(chan)) {
 			if (PTR_ERR(pcm->chan[i]) == -EPROBE_DEFER)
@@ -352,7 +357,7 @@ int snd_dmaengine_pcm_register(struct device *dev,
 	pcm->config = config;
 	pcm->flags = flags;
 
-	ret = dmaengine_pcm_request_chan_of(pcm, dev);
+	ret = dmaengine_pcm_request_chan_of(pcm, dev, config);
 	if (ret)
 		goto err_free_pcm;
 
-- 
1.8.1.5

Re: [PATCH 15/31] ASoC: dmaengine: add custom DMA config to snd_dmaengine_pcm_config

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 824 bytes --]

On Fri, Nov 15, 2013 at 01:54:10PM -0700, Stephen Warren wrote:

> - DMA device

>   This allows requesting DMA channels for a device other than the device
>   which is registering the "PCM" driver. This is quite unusual, but is
>   currently useful on Tegra. In much HW, and in Tegra20, each DAI HW

Acked-by: Mark Brown <broonie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

but this one especially I'd like to get into ASoC as soon as possible
since this one should be being used by other things.

I'm a bit concerned about anything actually using dma_dev since it
indicates that something is being worked around, it'd be a bit nicer to
print a warning when doing this to give people a hint that they might
not be doing the right thing if they use it (unless someone comes up
with a system that has a clear use case for it).

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[PATCH 15/31] ASoC: dmaengine: add custom DMA config to snd_dmaengine_pcm_config

[Mark Brown]

On Fri, Nov 15, 2013 at 01:54:10PM -0700, Stephen Warren wrote:

> - DMA device

>   This allows requesting DMA channels for a device other than the device
>   which is registering the "PCM" driver. This is quite unusual, but is
>   currently useful on Tegra. In much HW, and in Tegra20, each DAI HW

Acked-by: Mark Brown <broonie@linaro.org>

but this one especially I'd like to get into ASoC as soon as possible
since this one should be being used by other things.

I'm a bit concerned about anything actually using dma_dev since it
indicates that something is being worked around, it'd be a bit nicer to
print a warning when doing this to give people a hint that they might
not be doing the right thing if they use it (unless someone comes up
with a system that has a clear use case for it).
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Re: [PATCH 15/31] ASoC: dmaengine: add custom DMA config to snd_dmaengine_pcm_config

[Stephen Warren]

On 11/16/2013 02:44 AM, Mark Brown wrote:
> On Fri, Nov 15, 2013 at 01:54:10PM -0700, Stephen Warren wrote:
> 
>> - DMA device
> 
>> This allows requesting DMA channels for a device other than the 
>> device which is registering the "PCM" driver. This is quite 
>> unusual, but is currently useful on Tegra. In much HW, and in 
>> Tegra20, each DAI HW
...
> I'm a bit concerned about anything actually using dma_dev since it
>  indicates that something is being worked around, it'd be a bit 
> nicer to print a warning when doing this to give people a hint
> that they might not be doing the right thing if they use it
> (unless someone comes up with a system that has a clear use case
> for it).

What if I squash the following into that patch:

> diff --git a/sound/soc/soc-generic-dmaengine-pcm.c b/sound/soc/soc-generic-dmaengine-pcm.c
> index 1160d1cba133..0e2645dee96a 100644
> --- a/sound/soc/soc-generic-dmaengine-pcm.c
> +++ b/sound/soc/soc-generic-dmaengine-pcm.c
> @@ -296,8 +296,17 @@ static int dmaengine_pcm_request_chan_of(struct dmaengine_pcm *pcm,
>  	    !dev->of_node)
>  		return 0;
>  
> -	if (config->dma_dev)
> +	if (config->dma_dev) {
> +		/*
> +		 * If this warning is seen, it probably means that your Linux
> +		 * device structure does not match your HW device structure.
> +		 * It would be best to refactor the Linux device structure to
> +		 * correctly match the HW structure.
> +		 */
> +		dev_warn(dev, "DMA channels sourced from device %s",
> +			 dev_name(config->dma_dev));
>  		dev = config->dma_dev;
> +	}
>  
>  	for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE;
>  	     i++) {

(a few patches later) That yields the following warning on Tegra, for
example:

> [    2.629623] tegra30-i2s 70080400.i2s: DMA channels sourced from device 70080000.ahub

[PATCH 15/31] ASoC: dmaengine: add custom DMA config to snd_dmaengine_pcm_config

[Stephen Warren]

On 11/16/2013 02:44 AM, Mark Brown wrote:
> On Fri, Nov 15, 2013 at 01:54:10PM -0700, Stephen Warren wrote:
> 
>> - DMA device
> 
>> This allows requesting DMA channels for a device other than the 
>> device which is registering the "PCM" driver. This is quite 
>> unusual, but is currently useful on Tegra. In much HW, and in 
>> Tegra20, each DAI HW
...
> I'm a bit concerned about anything actually using dma_dev since it
>  indicates that something is being worked around, it'd be a bit 
> nicer to print a warning when doing this to give people a hint
> that they might not be doing the right thing if they use it
> (unless someone comes up with a system that has a clear use case
> for it).

What if I squash the following into that patch:

> diff --git a/sound/soc/soc-generic-dmaengine-pcm.c b/sound/soc/soc-generic-dmaengine-pcm.c
> index 1160d1cba133..0e2645dee96a 100644
> --- a/sound/soc/soc-generic-dmaengine-pcm.c
> +++ b/sound/soc/soc-generic-dmaengine-pcm.c
> @@ -296,8 +296,17 @@ static int dmaengine_pcm_request_chan_of(struct dmaengine_pcm *pcm,
>  	    !dev->of_node)
>  		return 0;
>  
> -	if (config->dma_dev)
> +	if (config->dma_dev) {
> +		/*
> +		 * If this warning is seen, it probably means that your Linux
> +		 * device structure does not match your HW device structure.
> +		 * It would be best to refactor the Linux device structure to
> +		 * correctly match the HW structure.
> +		 */
> +		dev_warn(dev, "DMA channels sourced from device %s",
> +			 dev_name(config->dma_dev));
>  		dev = config->dma_dev;
> +	}
>  
>  	for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE;
>  	     i++) {

(a few patches later) That yields the following warning on Tegra, for
example:

> [    2.629623] tegra30-i2s 70080400.i2s: DMA channels sourced from device 70080000.ahub

Re: [PATCH 15/31] ASoC: dmaengine: add custom DMA config to snd_dmaengine_pcm_config

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 128 bytes --]

On Mon, Nov 18, 2013 at 11:45:17AM -0700, Stephen Warren wrote:

> What if I squash the following into that patch:

Looks good.

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[PATCH 15/31] ASoC: dmaengine: add custom DMA config to snd_dmaengine_pcm_config

[Mark Brown]

On Mon, Nov 18, 2013 at 11:45:17AM -0700, Stephen Warren wrote:

> What if I squash the following into that patch:

Looks good.
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Re: [alsa-devel] [PATCH 15/31] ASoC: dmaengine: add custom DMA config to snd_dmaengine_pcm_config

[Lars-Peter Clausen]

On 11/15/2013 09:54 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Add fields to struct snd_dmaengine_pcm_config to allow custom:
> 
> - DMA channel names.
> 
>   This is useful when the default "tx" and "rx" channel names don't
>   apply, for example if a HW module supports multiple channels, each
>   having different DMA channel names. This is the case with the FIFOs
>   in Tegra's AHUB. This new facility can replace
>   SND_DMAENGINE_PCM_FLAG_CUSTOM_CHANNEL_NAME.
> 
> - DMA device
> 
>   This allows requesting DMA channels for a device other than the device
>   which is registering the "PCM" driver. This is quite unusual, but is
>   currently useful on Tegra. In much HW, and in Tegra20, each DAI HW
>   module contains its own FIFOs which DMA writes to. However, in Tegra30,
>   the DMA FIFOs were split out AHUB HW module, which then routes the data
>   through a cross-bar, and into the DAI HW modules. However, the current
>   ASoC driver structure does not expose this detail, and acts as if the
>   FIFOs are still part of the DAI HW modules. Consequently, the "PCM"
>   driver is registered with the DAI HW module, yet the DMA channels must
>   be looked up in the AHUB HW module's device tree node. This new config
>   field allows that to happen. Eventually, the Tegra drivers will be
>   reworked to fully expose the AHUB, and this config field can be
>   removed.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Liam Girdwood <lgirdwood-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Acked-by: Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>

[alsa-devel] [PATCH 15/31] ASoC: dmaengine: add custom DMA config to snd_dmaengine_pcm_config

[Lars-Peter Clausen]

On 11/15/2013 09:54 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Add fields to struct snd_dmaengine_pcm_config to allow custom:
> 
> - DMA channel names.
> 
>   This is useful when the default "tx" and "rx" channel names don't
>   apply, for example if a HW module supports multiple channels, each
>   having different DMA channel names. This is the case with the FIFOs
>   in Tegra's AHUB. This new facility can replace
>   SND_DMAENGINE_PCM_FLAG_CUSTOM_CHANNEL_NAME.
> 
> - DMA device
> 
>   This allows requesting DMA channels for a device other than the device
>   which is registering the "PCM" driver. This is quite unusual, but is
>   currently useful on Tegra. In much HW, and in Tegra20, each DAI HW
>   module contains its own FIFOs which DMA writes to. However, in Tegra30,
>   the DMA FIFOs were split out AHUB HW module, which then routes the data
>   through a cross-bar, and into the DAI HW modules. However, the current
>   ASoC driver structure does not expose this detail, and acts as if the
>   FIFOs are still part of the DAI HW modules. Consequently, the "PCM"
>   driver is registered with the DAI HW module, yet the DMA channels must
>   be looked up in the AHUB HW module's device tree node. This new config
>   field allows that to happen. Eventually, the Tegra drivers will be
>   reworked to fully expose the AHUB, and this config field can be
>   removed.
> 
> Cc: treding at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Liam Girdwood <lgirdwood@gmail.com>
> Cc: Mark Brown <broonie@kernel.org>
> Cc: alsa-devel at alsa-project.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>

Acked-by: Lars-Peter Clausen <lars@metafoo.de>

[PATCH 16/31] ASoC: tegra: use reset framework

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

This change also renames "clock"/"clk" to "modules"/"mod" in symbols
related to entries in configlink_clocks[], since:
- We don't care about clock handles any more, but rather reset handles,
  so the old name isn't applicable.
- It really is a list of modules on the bus, about which we currently
  only care about reset handles.
If we start caring about any other aspect of the modules in the future,
we won't have to rename all these symbols again.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Liam Girdwood <lgirdwood-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 sound/soc/tegra/Kconfig        |  2 ++
 sound/soc/tegra/tegra30_ahub.c | 70 +++++++++++++++++++++++-------------------
 sound/soc/tegra/tegra30_ahub.h |  2 +-
 3 files changed, 41 insertions(+), 33 deletions(-)

diff --git a/sound/soc/tegra/Kconfig b/sound/soc/tegra/Kconfig
index 8fc653ca3ab4..896292bb853f 100644
--- a/sound/soc/tegra/Kconfig
+++ b/sound/soc/tegra/Kconfig
@@ -1,6 +1,8 @@
 config SND_SOC_TEGRA
 	tristate "SoC Audio for the Tegra System-on-Chip"
 	depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
+	depends on COMMON_CLK
+	depends on RESET_CONTROLLER
 	select REGMAP_MMIO
 	select SND_SOC_GENERIC_DMAENGINE_PCM
 	help
diff --git a/sound/soc/tegra/tegra30_ahub.c b/sound/soc/tegra/tegra30_ahub.c
index 31154338c1eb..5ce00dc48c44 100644
--- a/sound/soc/tegra/tegra30_ahub.c
+++ b/sound/soc/tegra/tegra30_ahub.c
@@ -24,6 +24,7 @@
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 #include <linux/regmap.h>
+#include <linux/reset.h>
 #include <linux/slab.h>
 #include <linux/clk/tegra.h>
 #include <sound/soc.h>
@@ -301,27 +302,27 @@ int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif)
 }
 EXPORT_SYMBOL_GPL(tegra30_ahub_unset_rx_cif_source);
 
-#define CLK_LIST_MASK_TEGRA30	BIT(0)
-#define CLK_LIST_MASK_TEGRA114	BIT(1)
+#define MOD_LIST_MASK_TEGRA30	BIT(0)
+#define MOD_LIST_MASK_TEGRA114	BIT(1)
 
-#define CLK_LIST_MASK_TEGRA30_OR_LATER \
-		(CLK_LIST_MASK_TEGRA30 | CLK_LIST_MASK_TEGRA114)
+#define MOD_LIST_MASK_TEGRA30_OR_LATER \
+		(MOD_LIST_MASK_TEGRA30 | MOD_LIST_MASK_TEGRA114)
 
 static const struct {
-	const char *clk_name;
-	u32 clk_list_mask;
-} configlink_clocks[] = {
-	{ "i2s0", CLK_LIST_MASK_TEGRA30_OR_LATER },
-	{ "i2s1", CLK_LIST_MASK_TEGRA30_OR_LATER },
-	{ "i2s2", CLK_LIST_MASK_TEGRA30_OR_LATER },
-	{ "i2s3", CLK_LIST_MASK_TEGRA30_OR_LATER },
-	{ "i2s4", CLK_LIST_MASK_TEGRA30_OR_LATER },
-	{ "dam0", CLK_LIST_MASK_TEGRA30_OR_LATER },
-	{ "dam1", CLK_LIST_MASK_TEGRA30_OR_LATER },
-	{ "dam2", CLK_LIST_MASK_TEGRA30_OR_LATER },
-	{ "spdif_in", CLK_LIST_MASK_TEGRA30_OR_LATER },
-	{ "amx", CLK_LIST_MASK_TEGRA114 },
-	{ "adx", CLK_LIST_MASK_TEGRA114 },
+	const char *rst_name;
+	u32 mod_list_mask;
+} configlink_mods[] = {
+	{ "i2s0", MOD_LIST_MASK_TEGRA30_OR_LATER },
+	{ "i2s1", MOD_LIST_MASK_TEGRA30_OR_LATER },
+	{ "i2s2", MOD_LIST_MASK_TEGRA30_OR_LATER },
+	{ "i2s3", MOD_LIST_MASK_TEGRA30_OR_LATER },
+	{ "i2s4", MOD_LIST_MASK_TEGRA30_OR_LATER },
+	{ "dam0", MOD_LIST_MASK_TEGRA30_OR_LATER },
+	{ "dam1", MOD_LIST_MASK_TEGRA30_OR_LATER },
+	{ "dam2", MOD_LIST_MASK_TEGRA30_OR_LATER },
+	{ "spdif", MOD_LIST_MASK_TEGRA30_OR_LATER },
+	{ "amx", MOD_LIST_MASK_TEGRA114 },
+	{ "adx", MOD_LIST_MASK_TEGRA114 },
 };
 
 #define LAST_REG(name) \
@@ -450,17 +451,17 @@ static const struct regmap_config tegra30_ahub_ahub_regmap_config = {
 };
 
 static struct tegra30_ahub_soc_data soc_data_tegra30 = {
-	.clk_list_mask = CLK_LIST_MASK_TEGRA30,
+	.mod_list_mask = MOD_LIST_MASK_TEGRA30,
 	.set_audio_cif = tegra30_ahub_set_cif,
 };
 
 static struct tegra30_ahub_soc_data soc_data_tegra114 = {
-	.clk_list_mask = CLK_LIST_MASK_TEGRA114,
+	.mod_list_mask = MOD_LIST_MASK_TEGRA114,
 	.set_audio_cif = tegra30_ahub_set_cif,
 };
 
 static struct tegra30_ahub_soc_data soc_data_tegra124 = {
-	.clk_list_mask = CLK_LIST_MASK_TEGRA114,
+	.mod_list_mask = MOD_LIST_MASK_TEGRA114,
 	.set_audio_cif = tegra124_ahub_set_cif,
 };
 
@@ -475,7 +476,7 @@ static int tegra30_ahub_probe(struct platform_device *pdev)
 {
 	const struct of_device_id *match;
 	const struct tegra30_ahub_soc_data *soc_data;
-	struct clk *clk;
+	struct reset_control *rst;
 	int i;
 	struct resource *res0, *res1, *region;
 	u32 of_dma[2];
@@ -495,19 +496,24 @@ static int tegra30_ahub_probe(struct platform_device *pdev)
 	 * operate correctly, all devices on this bus must be out of reset.
 	 * Ensure that here.
 	 */
-	for (i = 0; i < ARRAY_SIZE(configlink_clocks); i++) {
-		if (!(configlink_clocks[i].clk_list_mask &
-					soc_data->clk_list_mask))
+	for (i = 0; i < ARRAY_SIZE(configlink_mods); i++) {
+		if (!(configlink_mods[i].mod_list_mask &
+					soc_data->mod_list_mask))
 			continue;
-		clk = clk_get(&pdev->dev, configlink_clocks[i].clk_name);
-		if (IS_ERR(clk)) {
-			dev_err(&pdev->dev, "Can't get clock %s\n",
-				configlink_clocks[i].clk_name);
-			ret = PTR_ERR(clk);
+
+		rst = reset_control_get(&pdev->dev,
+					configlink_mods[i].rst_name);
+		if (IS_ERR(rst)) {
+			dev_err(&pdev->dev, "Can't get reset %s\n",
+				configlink_mods[i].rst_name);
+			ret = PTR_ERR(rst);
 			goto err;
 		}
-		tegra_periph_reset_deassert(clk);
-		clk_put(clk);
+
+		ret = reset_control_deassert(rst);
+		reset_control_put(rst);
+		if (ret)
+			goto err;
 	}
 
 	ahub = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_ahub),
diff --git a/sound/soc/tegra/tegra30_ahub.h b/sound/soc/tegra/tegra30_ahub.h
index d67321d90faa..1383f8cd3572 100644
--- a/sound/soc/tegra/tegra30_ahub.h
+++ b/sound/soc/tegra/tegra30_ahub.h
@@ -502,7 +502,7 @@ void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg,
 			   struct tegra30_ahub_cif_conf *conf);
 
 struct tegra30_ahub_soc_data {
-	u32 clk_list_mask;
+	u32 mod_list_mask;
 	void (*set_audio_cif)(struct regmap *regmap,
 			      unsigned int reg,
 			      struct tegra30_ahub_cif_conf *conf);
-- 
1.8.1.5

[PATCH 16/31] ASoC: tegra: use reset framework

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

This change also renames "clock"/"clk" to "modules"/"mod" in symbols
related to entries in configlink_clocks[], since:
- We don't care about clock handles any more, but rather reset handles,
  so the old name isn't applicable.
- It really is a list of modules on the bus, about which we currently
  only care about reset handles.
If we start caring about any other aspect of the modules in the future,
we won't have to rename all these symbols again.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: alsa-devel at alsa-project.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 sound/soc/tegra/Kconfig        |  2 ++
 sound/soc/tegra/tegra30_ahub.c | 70 +++++++++++++++++++++++-------------------
 sound/soc/tegra/tegra30_ahub.h |  2 +-
 3 files changed, 41 insertions(+), 33 deletions(-)

diff --git a/sound/soc/tegra/Kconfig b/sound/soc/tegra/Kconfig
index 8fc653ca3ab4..896292bb853f 100644
--- a/sound/soc/tegra/Kconfig
+++ b/sound/soc/tegra/Kconfig
@@ -1,6 +1,8 @@
 config SND_SOC_TEGRA
 	tristate "SoC Audio for the Tegra System-on-Chip"
 	depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
+	depends on COMMON_CLK
+	depends on RESET_CONTROLLER
 	select REGMAP_MMIO
 	select SND_SOC_GENERIC_DMAENGINE_PCM
 	help
diff --git a/sound/soc/tegra/tegra30_ahub.c b/sound/soc/tegra/tegra30_ahub.c
index 31154338c1eb..5ce00dc48c44 100644
--- a/sound/soc/tegra/tegra30_ahub.c
+++ b/sound/soc/tegra/tegra30_ahub.c
@@ -24,6 +24,7 @@
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 #include <linux/regmap.h>
+#include <linux/reset.h>
 #include <linux/slab.h>
 #include <linux/clk/tegra.h>
 #include <sound/soc.h>
@@ -301,27 +302,27 @@ int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif)
 }
 EXPORT_SYMBOL_GPL(tegra30_ahub_unset_rx_cif_source);
 
-#define CLK_LIST_MASK_TEGRA30	BIT(0)
-#define CLK_LIST_MASK_TEGRA114	BIT(1)
+#define MOD_LIST_MASK_TEGRA30	BIT(0)
+#define MOD_LIST_MASK_TEGRA114	BIT(1)
 
-#define CLK_LIST_MASK_TEGRA30_OR_LATER \
-		(CLK_LIST_MASK_TEGRA30 | CLK_LIST_MASK_TEGRA114)
+#define MOD_LIST_MASK_TEGRA30_OR_LATER \
+		(MOD_LIST_MASK_TEGRA30 | MOD_LIST_MASK_TEGRA114)
 
 static const struct {
-	const char *clk_name;
-	u32 clk_list_mask;
-} configlink_clocks[] = {
-	{ "i2s0", CLK_LIST_MASK_TEGRA30_OR_LATER },
-	{ "i2s1", CLK_LIST_MASK_TEGRA30_OR_LATER },
-	{ "i2s2", CLK_LIST_MASK_TEGRA30_OR_LATER },
-	{ "i2s3", CLK_LIST_MASK_TEGRA30_OR_LATER },
-	{ "i2s4", CLK_LIST_MASK_TEGRA30_OR_LATER },
-	{ "dam0", CLK_LIST_MASK_TEGRA30_OR_LATER },
-	{ "dam1", CLK_LIST_MASK_TEGRA30_OR_LATER },
-	{ "dam2", CLK_LIST_MASK_TEGRA30_OR_LATER },
-	{ "spdif_in", CLK_LIST_MASK_TEGRA30_OR_LATER },
-	{ "amx", CLK_LIST_MASK_TEGRA114 },
-	{ "adx", CLK_LIST_MASK_TEGRA114 },
+	const char *rst_name;
+	u32 mod_list_mask;
+} configlink_mods[] = {
+	{ "i2s0", MOD_LIST_MASK_TEGRA30_OR_LATER },
+	{ "i2s1", MOD_LIST_MASK_TEGRA30_OR_LATER },
+	{ "i2s2", MOD_LIST_MASK_TEGRA30_OR_LATER },
+	{ "i2s3", MOD_LIST_MASK_TEGRA30_OR_LATER },
+	{ "i2s4", MOD_LIST_MASK_TEGRA30_OR_LATER },
+	{ "dam0", MOD_LIST_MASK_TEGRA30_OR_LATER },
+	{ "dam1", MOD_LIST_MASK_TEGRA30_OR_LATER },
+	{ "dam2", MOD_LIST_MASK_TEGRA30_OR_LATER },
+	{ "spdif", MOD_LIST_MASK_TEGRA30_OR_LATER },
+	{ "amx", MOD_LIST_MASK_TEGRA114 },
+	{ "adx", MOD_LIST_MASK_TEGRA114 },
 };
 
 #define LAST_REG(name) \
@@ -450,17 +451,17 @@ static const struct regmap_config tegra30_ahub_ahub_regmap_config = {
 };
 
 static struct tegra30_ahub_soc_data soc_data_tegra30 = {
-	.clk_list_mask = CLK_LIST_MASK_TEGRA30,
+	.mod_list_mask = MOD_LIST_MASK_TEGRA30,
 	.set_audio_cif = tegra30_ahub_set_cif,
 };
 
 static struct tegra30_ahub_soc_data soc_data_tegra114 = {
-	.clk_list_mask = CLK_LIST_MASK_TEGRA114,
+	.mod_list_mask = MOD_LIST_MASK_TEGRA114,
 	.set_audio_cif = tegra30_ahub_set_cif,
 };
 
 static struct tegra30_ahub_soc_data soc_data_tegra124 = {
-	.clk_list_mask = CLK_LIST_MASK_TEGRA114,
+	.mod_list_mask = MOD_LIST_MASK_TEGRA114,
 	.set_audio_cif = tegra124_ahub_set_cif,
 };
 
@@ -475,7 +476,7 @@ static int tegra30_ahub_probe(struct platform_device *pdev)
 {
 	const struct of_device_id *match;
 	const struct tegra30_ahub_soc_data *soc_data;
-	struct clk *clk;
+	struct reset_control *rst;
 	int i;
 	struct resource *res0, *res1, *region;
 	u32 of_dma[2];
@@ -495,19 +496,24 @@ static int tegra30_ahub_probe(struct platform_device *pdev)
 	 * operate correctly, all devices on this bus must be out of reset.
 	 * Ensure that here.
 	 */
-	for (i = 0; i < ARRAY_SIZE(configlink_clocks); i++) {
-		if (!(configlink_clocks[i].clk_list_mask &
-					soc_data->clk_list_mask))
+	for (i = 0; i < ARRAY_SIZE(configlink_mods); i++) {
+		if (!(configlink_mods[i].mod_list_mask &
+					soc_data->mod_list_mask))
 			continue;
-		clk = clk_get(&pdev->dev, configlink_clocks[i].clk_name);
-		if (IS_ERR(clk)) {
-			dev_err(&pdev->dev, "Can't get clock %s\n",
-				configlink_clocks[i].clk_name);
-			ret = PTR_ERR(clk);
+
+		rst = reset_control_get(&pdev->dev,
+					configlink_mods[i].rst_name);
+		if (IS_ERR(rst)) {
+			dev_err(&pdev->dev, "Can't get reset %s\n",
+				configlink_mods[i].rst_name);
+			ret = PTR_ERR(rst);
 			goto err;
 		}
-		tegra_periph_reset_deassert(clk);
-		clk_put(clk);
+
+		ret = reset_control_deassert(rst);
+		reset_control_put(rst);
+		if (ret)
+			goto err;
 	}
 
 	ahub = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_ahub),
diff --git a/sound/soc/tegra/tegra30_ahub.h b/sound/soc/tegra/tegra30_ahub.h
index d67321d90faa..1383f8cd3572 100644
--- a/sound/soc/tegra/tegra30_ahub.h
+++ b/sound/soc/tegra/tegra30_ahub.h
@@ -502,7 +502,7 @@ void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg,
 			   struct tegra30_ahub_cif_conf *conf);
 
 struct tegra30_ahub_soc_data {
-	u32 clk_list_mask;
+	u32 mod_list_mask;
 	void (*set_audio_cif)(struct regmap *regmap,
 			      unsigned int reg,
 			      struct tegra30_ahub_cif_conf *conf);
-- 
1.8.1.5

Re: [PATCH 16/31] ASoC: tegra: use reset framework

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 458 bytes --]

On Fri, Nov 15, 2013 at 01:54:11PM -0700, Stephen Warren wrote:

> @@ -1,6 +1,8 @@
>  config SND_SOC_TEGRA
>  	tristate "SoC Audio for the Tegra System-on-Chip"
>  	depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
> +	depends on COMMON_CLK
> +	depends on RESET_CONTROLLER

Do you depend on COMMON_CLK here?  I only noticed reset controller API
dependencies here but perhaps I missed this (or it's fixing a dependency
that should be there already).

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[PATCH 16/31] ASoC: tegra: use reset framework

[Mark Brown]

On Fri, Nov 15, 2013 at 01:54:11PM -0700, Stephen Warren wrote:

> @@ -1,6 +1,8 @@
>  config SND_SOC_TEGRA
>  	tristate "SoC Audio for the Tegra System-on-Chip"
>  	depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
> +	depends on COMMON_CLK
> +	depends on RESET_CONTROLLER

Do you depend on COMMON_CLK here?  I only noticed reset controller API
dependencies here but perhaps I missed this (or it's fixing a dependency
that should be there already).
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Re: [PATCH 16/31] ASoC: tegra: use reset framework

[Stephen Warren]

On 11/16/2013 02:55 AM, Mark Brown wrote:
> On Fri, Nov 15, 2013 at 01:54:11PM -0700, Stephen Warren wrote:
> 
>> @@ -1,6 +1,8 @@ config SND_SOC_TEGRA tristate "SoC Audio for the
>> Tegra System-on-Chip" depends on (ARCH_TEGRA && TEGRA20_APB_DMA)
>> || COMPILE_TEST +	depends on COMMON_CLK +	depends on
>> RESET_CONTROLLER
> 
> Do you depend on COMMON_CLK here?  I only noticed reset controller
> API dependencies here but perhaps I missed this (or it's fixing a
> dependency that should be there already).

It's fixing a dependency that should already be there, in the
COMPILE_TEST case. In the (ARCH_TEGRA && TEGRA20_APB_DMA) case,
COMMON_CLOCK is always selected.

Do you want me to split this out into a separate patch? If so, I'd
prefer not to apply that separate patch immediately to 3.13 as a fix,
since then it'd delay applying this series until after -rc2 is out,
unless you can get the fix into -rc1 quickly...

[PATCH 16/31] ASoC: tegra: use reset framework

[Stephen Warren]

On 11/16/2013 02:55 AM, Mark Brown wrote:
> On Fri, Nov 15, 2013 at 01:54:11PM -0700, Stephen Warren wrote:
> 
>> @@ -1,6 +1,8 @@ config SND_SOC_TEGRA tristate "SoC Audio for the
>> Tegra System-on-Chip" depends on (ARCH_TEGRA && TEGRA20_APB_DMA)
>> || COMPILE_TEST +	depends on COMMON_CLK +	depends on
>> RESET_CONTROLLER
> 
> Do you depend on COMMON_CLK here?  I only noticed reset controller
> API dependencies here but perhaps I missed this (or it's fixing a
> dependency that should be there already).

It's fixing a dependency that should already be there, in the
COMPILE_TEST case. In the (ARCH_TEGRA && TEGRA20_APB_DMA) case,
COMMON_CLOCK is always selected.

Do you want me to split this out into a separate patch? If so, I'd
prefer not to apply that separate patch immediately to 3.13 as a fix,
since then it'd delay applying this series until after -rc2 is out,
unless you can get the fix into -rc1 quickly...

Re: [PATCH 16/31] ASoC: tegra: use reset framework

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 721 bytes --]

On Mon, Nov 18, 2013 at 10:21:16AM -0700, Stephen Warren wrote:

> It's fixing a dependency that should already be there, in the
> COMPILE_TEST case. In the (ARCH_TEGRA && TEGRA20_APB_DMA) case,
> COMMON_CLOCK is always selected.

> Do you want me to split this out into a separate patch? If so, I'd
> prefer not to apply that separate patch immediately to 3.13 as a fix,
> since then it'd delay applying this series until after -rc2 is out,
> unless you can get the fix into -rc1 quickly...

I don't really care, it was just that I was looking for something to do
with clocks in the patch and couldn't find anything.  Perhaps a note in
the changelog if you need to respin so I don't forget and say the same
thing again.

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[PATCH 16/31] ASoC: tegra: use reset framework

[Mark Brown]

On Mon, Nov 18, 2013 at 10:21:16AM -0700, Stephen Warren wrote:

> It's fixing a dependency that should already be there, in the
> COMPILE_TEST case. In the (ARCH_TEGRA && TEGRA20_APB_DMA) case,
> COMMON_CLOCK is always selected.

> Do you want me to split this out into a separate patch? If so, I'd
> prefer not to apply that separate patch immediately to 3.13 as a fix,
> since then it'd delay applying this series until after -rc2 is out,
> unless you can get the fix into -rc1 quickly...

I don't really care, it was just that I was looking for something to do
with clocks in the patch and couldn't find anything.  Perhaps a note in
the changelog if you need to respin so I don't forget and say the same
thing again.
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Re: [PATCH 16/31] ASoC: tegra: use reset framework

[Stephen Warren]

On 11/18/2013 11:37 AM, Mark Brown wrote:
> On Mon, Nov 18, 2013 at 10:21:16AM -0700, Stephen Warren wrote:
> 
>> It's fixing a dependency that should already be there, in the 
>> COMPILE_TEST case. In the (ARCH_TEGRA && TEGRA20_APB_DMA) case, 
>> COMMON_CLOCK is always selected.
> 
>> Do you want me to split this out into a separate patch? If so,
>> I'd prefer not to apply that separate patch immediately to 3.13
>> as a fix, since then it'd delay applying this series until after
>> -rc2 is out, unless you can get the fix into -rc1 quickly...
> 
> I don't really care, it was just that I was looking for something
> to do with clocks in the patch and couldn't find anything.  Perhaps
> a note in the changelog if you need to respin so I don't forget and
> say the same thing again.

I added the following to the changelog:

----------
Note: The addition of "depends COMMON_CLOCK" is something that was
missing before, not a new requirement.
----------

You didn't ack this one patch; I assume that was just an oversight?

[PATCH 16/31] ASoC: tegra: use reset framework

[Stephen Warren]

On 11/18/2013 11:37 AM, Mark Brown wrote:
> On Mon, Nov 18, 2013 at 10:21:16AM -0700, Stephen Warren wrote:
> 
>> It's fixing a dependency that should already be there, in the 
>> COMPILE_TEST case. In the (ARCH_TEGRA && TEGRA20_APB_DMA) case, 
>> COMMON_CLOCK is always selected.
> 
>> Do you want me to split this out into a separate patch? If so,
>> I'd prefer not to apply that separate patch immediately to 3.13
>> as a fix, since then it'd delay applying this series until after
>> -rc2 is out, unless you can get the fix into -rc1 quickly...
> 
> I don't really care, it was just that I was looking for something
> to do with clocks in the patch and couldn't find anything.  Perhaps
> a note in the changelog if you need to respin so I don't forget and
> say the same thing again.

I added the following to the changelog:

----------
Note: The addition of "depends COMMON_CLOCK" is something that was
missing before, not a new requirement.
----------

You didn't ack this one patch; I assume that was just an oversight?

Re: [PATCH 16/31] ASoC: tegra: use reset framework

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 241 bytes --]

On Mon, Nov 25, 2013 at 02:56:23PM -0700, Stephen Warren wrote:

> You didn't ack this one patch; I assume that was just an oversight?

No, it was because it looked incorrect based on the lack of tie in
between the description and the code.

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[PATCH 16/31] ASoC: tegra: use reset framework

[Mark Brown]

On Mon, Nov 25, 2013 at 02:56:23PM -0700, Stephen Warren wrote:

> You didn't ack this one patch; I assume that was just an oversight?

No, it was because it looked incorrect based on the lack of tie in
between the description and the code.
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Re: [PATCH 16/31] ASoC: tegra: use reset framework

[Stephen Warren]

On 11/26/2013 06:14 AM, Mark Brown wrote:
> On Mon, Nov 25, 2013 at 02:56:23PM -0700, Stephen Warren wrote:
> 
>> You didn't ack this one patch; I assume that was just an
>> oversight?
> 
> No, it was because it looked incorrect based on the lack of tie in 
> between the description and the code.

Hmm. You had asked:

>> @@ -1,6 +1,8 @@ config SND_SOC_TEGRA tristate "SoC Audio for the
>> Tegra System-on-Chip" depends on (ARCH_TEGRA && TEGRA20_APB_DMA)
>> || COMPILE_TEST +	depends on COMMON_CLK +	depends on
>> RESET_CONTROLLER
> 
> Do you depend on COMMON_CLK here?  I only noticed reset controller
> API dependencies here but perhaps I missed this (or it's fixing a
> dependency that should be there already).

I responded:

> It's fixing a dependency that should already be there, in the 
> COMPILE_TEST case. In the (ARCH_TEGRA && TEGRA20_APB_DMA) case, 
> COMMON_CLOCK is always selected.
> 
> Do you want me to split this out into a separate patch? If so, I'd 
> prefer not to apply that separate patch immediately to 3.13 as a
> fix, since then it'd delay applying this series until after -rc2 is
> out, unless you can get the fix into -rc1 quickly...

(although at this point in time, the DMA patches which this depend on
aren't likely to be ready soon enough for the delay to matter, so I
could send the addition of depends COMMON_CLK as a separate patch for
-rc2 if you want)

and you said:

> I don't really care, it was just that I was looking for something
> to do with clocks in the patch and couldn't find anything.  Perhaps
> a note in the changelog if you need to respin so I don't forget and
> say the same thing again.

... so, I thought you were OK with that one issue. Were there other
issues you didn't mention before?

[PATCH 16/31] ASoC: tegra: use reset framework

[Stephen Warren]

On 11/26/2013 06:14 AM, Mark Brown wrote:
> On Mon, Nov 25, 2013 at 02:56:23PM -0700, Stephen Warren wrote:
> 
>> You didn't ack this one patch; I assume that was just an
>> oversight?
> 
> No, it was because it looked incorrect based on the lack of tie in 
> between the description and the code.

Hmm. You had asked:

>> @@ -1,6 +1,8 @@ config SND_SOC_TEGRA tristate "SoC Audio for the
>> Tegra System-on-Chip" depends on (ARCH_TEGRA && TEGRA20_APB_DMA)
>> || COMPILE_TEST +	depends on COMMON_CLK +	depends on
>> RESET_CONTROLLER
> 
> Do you depend on COMMON_CLK here?  I only noticed reset controller
> API dependencies here but perhaps I missed this (or it's fixing a
> dependency that should be there already).

I responded:

> It's fixing a dependency that should already be there, in the 
> COMPILE_TEST case. In the (ARCH_TEGRA && TEGRA20_APB_DMA) case, 
> COMMON_CLOCK is always selected.
> 
> Do you want me to split this out into a separate patch? If so, I'd 
> prefer not to apply that separate patch immediately to 3.13 as a
> fix, since then it'd delay applying this series until after -rc2 is
> out, unless you can get the fix into -rc1 quickly...

(although at this point in time, the DMA patches which this depend on
aren't likely to be ready soon enough for the delay to matter, so I
could send the addition of depends COMMON_CLK as a separate patch for
-rc2 if you want)

and you said:

> I don't really care, it was just that I was looking for something
> to do with clocks in the patch and couldn't find anything.  Perhaps
> a note in the changelog if you need to respin so I don't forget and
> say the same thing again.

... so, I thought you were OK with that one issue. Were there other
issues you didn't mention before?

Re: [PATCH 16/31] ASoC: tegra: use reset framework

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 631 bytes --]

On Tue, Nov 26, 2013 at 09:31:25AM -0700, Stephen Warren wrote:

> ... so, I thought you were OK with that one issue. Were there other
> issues you didn't mention before?

Probably not but I'd need to reread it, I don't think I got that much
further than noticing that there weren't any clock changes (the fact
that the clock dependency was getting added in a DMA series set off
alarm bells).  To be honest given the number of revisions that seem to
be required I'd been expecting to see a respin of the series, the ASoC
generic DMA changes did need a respin before they can be merged and I do
want to get them into the ASoC tree.

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[PATCH 16/31] ASoC: tegra: use reset framework

[Mark Brown]

On Tue, Nov 26, 2013 at 09:31:25AM -0700, Stephen Warren wrote:

> ... so, I thought you were OK with that one issue. Were there other
> issues you didn't mention before?

Probably not but I'd need to reread it, I don't think I got that much
further than noticing that there weren't any clock changes (the fact
that the clock dependency was getting added in a DMA series set off
alarm bells).  To be honest given the number of revisions that seem to
be required I'd been expecting to see a respin of the series, the ASoC
generic DMA changes did need a respin before they can be merged and I do
want to get them into the ASoC tree.
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Re: [PATCH 16/31] ASoC: tegra: use reset framework

[Stephen Warren]

On 11/26/2013 11:37 AM, Mark Brown wrote:
> On Tue, Nov 26, 2013 at 09:31:25AM -0700, Stephen Warren wrote:
> 
>> ... so, I thought you were OK with that one issue. Were there
>> other issues you didn't mention before?
> 
> Probably not but I'd need to reread it, I don't think I got that
> much further than noticing that there weren't any clock changes
> (the fact that the clock dependency was getting added in a DMA
> series set off alarm bells).  To be honest given the number of
> revisions that seem to be required I'd been expecting to see a
> respin of the series, the ASoC generic DMA changes did need a
> respin before they can be merged and I do want to get them into the
> ASoC tree.

OK, I'll repost.

I'm waiting to repost the ASoC core changes until the dmaengine API
change settles. Hopefully very soon.

[PATCH 16/31] ASoC: tegra: use reset framework

[Stephen Warren]

On 11/26/2013 11:37 AM, Mark Brown wrote:
> On Tue, Nov 26, 2013 at 09:31:25AM -0700, Stephen Warren wrote:
> 
>> ... so, I thought you were OK with that one issue. Were there
>> other issues you didn't mention before?
> 
> Probably not but I'd need to reread it, I don't think I got that
> much further than noticing that there weren't any clock changes
> (the fact that the clock dependency was getting added in a DMA
> series set off alarm bells).  To be honest given the number of
> revisions that seem to be required I'd been expecting to see a
> respin of the series, the ASoC generic DMA changes did need a
> respin before they can be merged and I do want to get them into the
> ASoC tree.

OK, I'll repost.

I'm waiting to repost the ASoC core changes until the dmaengine API
change settles. Hopefully very soon.

[PATCH 17/31] ASoC: tegra: call pm_runtime APIs around register accesses

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Call pm_runtime_get_sync() before all register accesses; the HW requires
clocks to be running when accessing registers.

This hasn't been needed to date, since all register IO was performed
while playback was active, and hence the ASoC core had already called
pm_runtime_get(). However, an imminent future commit will allocate and
set up the FIFOs and routing during probe(), when that "protection"
won't be in place.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Liam Girdwood <lgirdwood-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 sound/soc/tegra/tegra30_ahub.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/sound/soc/tegra/tegra30_ahub.c b/sound/soc/tegra/tegra30_ahub.c
index 5ce00dc48c44..2f1a566dd9cc 100644
--- a/sound/soc/tegra/tegra30_ahub.c
+++ b/sound/soc/tegra/tegra30_ahub.c
@@ -115,6 +115,8 @@ int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
 		   (channel * TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE);
 	*reqsel = ahub->dma_sel + channel;
 
+	pm_runtime_get_sync(ahub->dev);
+
 	reg = TEGRA30_AHUB_CHANNEL_CTRL +
 	      (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
 	val = tegra30_apbif_read(reg);
@@ -141,6 +143,8 @@ int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
 	      (channel * TEGRA30_AHUB_CIF_RX_CTRL_STRIDE);
 	ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf);
 
+	pm_runtime_put(ahub->dev);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_rx_fifo);
@@ -150,12 +154,16 @@ int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif)
 	int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
 	int reg, val;
 
+	pm_runtime_get_sync(ahub->dev);
+
 	reg = TEGRA30_AHUB_CHANNEL_CTRL +
 	      (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
 	val = tegra30_apbif_read(reg);
 	val |= TEGRA30_AHUB_CHANNEL_CTRL_RX_EN;
 	tegra30_apbif_write(reg, val);
 
+	pm_runtime_put(ahub->dev);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(tegra30_ahub_enable_rx_fifo);
@@ -165,12 +173,16 @@ int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif)
 	int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
 	int reg, val;
 
+	pm_runtime_get_sync(ahub->dev);
+
 	reg = TEGRA30_AHUB_CHANNEL_CTRL +
 	      (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
 	val = tegra30_apbif_read(reg);
 	val &= ~TEGRA30_AHUB_CHANNEL_CTRL_RX_EN;
 	tegra30_apbif_write(reg, val);
 
+	pm_runtime_put(ahub->dev);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(tegra30_ahub_disable_rx_fifo);
@@ -205,6 +217,8 @@ int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
 		   (channel * TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE);
 	*reqsel = ahub->dma_sel + channel;
 
+	pm_runtime_get_sync(ahub->dev);
+
 	reg = TEGRA30_AHUB_CHANNEL_CTRL +
 	      (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
 	val = tegra30_apbif_read(reg);
@@ -231,6 +245,8 @@ int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
 	      (channel * TEGRA30_AHUB_CIF_TX_CTRL_STRIDE);
 	ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf);
 
+	pm_runtime_put(ahub->dev);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_tx_fifo);
@@ -240,12 +256,16 @@ int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif)
 	int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
 	int reg, val;
 
+	pm_runtime_get_sync(ahub->dev);
+
 	reg = TEGRA30_AHUB_CHANNEL_CTRL +
 	      (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
 	val = tegra30_apbif_read(reg);
 	val |= TEGRA30_AHUB_CHANNEL_CTRL_TX_EN;
 	tegra30_apbif_write(reg, val);
 
+	pm_runtime_put(ahub->dev);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(tegra30_ahub_enable_tx_fifo);
@@ -255,12 +275,16 @@ int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif)
 	int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
 	int reg, val;
 
+	pm_runtime_get_sync(ahub->dev);
+
 	reg = TEGRA30_AHUB_CHANNEL_CTRL +
 	      (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
 	val = tegra30_apbif_read(reg);
 	val &= ~TEGRA30_AHUB_CHANNEL_CTRL_TX_EN;
 	tegra30_apbif_write(reg, val);
 
+	pm_runtime_put(ahub->dev);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(tegra30_ahub_disable_tx_fifo);
@@ -281,10 +305,14 @@ int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif,
 	int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
 	int reg;
 
+	pm_runtime_get_sync(ahub->dev);
+
 	reg = TEGRA30_AHUB_AUDIO_RX +
 	      (channel * TEGRA30_AHUB_AUDIO_RX_STRIDE);
 	tegra30_audio_write(reg, 1 << txcif);
 
+	pm_runtime_put(ahub->dev);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(tegra30_ahub_set_rx_cif_source);
@@ -294,10 +322,14 @@ int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif)
 	int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
 	int reg;
 
+	pm_runtime_get_sync(ahub->dev);
+
 	reg = TEGRA30_AHUB_AUDIO_RX +
 	      (channel * TEGRA30_AHUB_AUDIO_RX_STRIDE);
 	tegra30_audio_write(reg, 0);
 
+	pm_runtime_put(ahub->dev);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(tegra30_ahub_unset_rx_cif_source);
-- 
1.8.1.5

[PATCH 17/31] ASoC: tegra: call pm_runtime APIs around register accesses

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Call pm_runtime_get_sync() before all register accesses; the HW requires
clocks to be running when accessing registers.

This hasn't been needed to date, since all register IO was performed
while playback was active, and hence the ASoC core had already called
pm_runtime_get(). However, an imminent future commit will allocate and
set up the FIFOs and routing during probe(), when that "protection"
won't be in place.

Cc: treding at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: alsa-devel at alsa-project.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 sound/soc/tegra/tegra30_ahub.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/sound/soc/tegra/tegra30_ahub.c b/sound/soc/tegra/tegra30_ahub.c
index 5ce00dc48c44..2f1a566dd9cc 100644
--- a/sound/soc/tegra/tegra30_ahub.c
+++ b/sound/soc/tegra/tegra30_ahub.c
@@ -115,6 +115,8 @@ int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
 		   (channel * TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE);
 	*reqsel = ahub->dma_sel + channel;
 
+	pm_runtime_get_sync(ahub->dev);
+
 	reg = TEGRA30_AHUB_CHANNEL_CTRL +
 	      (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
 	val = tegra30_apbif_read(reg);
@@ -141,6 +143,8 @@ int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
 	      (channel * TEGRA30_AHUB_CIF_RX_CTRL_STRIDE);
 	ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf);
 
+	pm_runtime_put(ahub->dev);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_rx_fifo);
@@ -150,12 +154,16 @@ int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif)
 	int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
 	int reg, val;
 
+	pm_runtime_get_sync(ahub->dev);
+
 	reg = TEGRA30_AHUB_CHANNEL_CTRL +
 	      (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
 	val = tegra30_apbif_read(reg);
 	val |= TEGRA30_AHUB_CHANNEL_CTRL_RX_EN;
 	tegra30_apbif_write(reg, val);
 
+	pm_runtime_put(ahub->dev);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(tegra30_ahub_enable_rx_fifo);
@@ -165,12 +173,16 @@ int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif)
 	int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
 	int reg, val;
 
+	pm_runtime_get_sync(ahub->dev);
+
 	reg = TEGRA30_AHUB_CHANNEL_CTRL +
 	      (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
 	val = tegra30_apbif_read(reg);
 	val &= ~TEGRA30_AHUB_CHANNEL_CTRL_RX_EN;
 	tegra30_apbif_write(reg, val);
 
+	pm_runtime_put(ahub->dev);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(tegra30_ahub_disable_rx_fifo);
@@ -205,6 +217,8 @@ int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
 		   (channel * TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE);
 	*reqsel = ahub->dma_sel + channel;
 
+	pm_runtime_get_sync(ahub->dev);
+
 	reg = TEGRA30_AHUB_CHANNEL_CTRL +
 	      (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
 	val = tegra30_apbif_read(reg);
@@ -231,6 +245,8 @@ int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
 	      (channel * TEGRA30_AHUB_CIF_TX_CTRL_STRIDE);
 	ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf);
 
+	pm_runtime_put(ahub->dev);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_tx_fifo);
@@ -240,12 +256,16 @@ int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif)
 	int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
 	int reg, val;
 
+	pm_runtime_get_sync(ahub->dev);
+
 	reg = TEGRA30_AHUB_CHANNEL_CTRL +
 	      (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
 	val = tegra30_apbif_read(reg);
 	val |= TEGRA30_AHUB_CHANNEL_CTRL_TX_EN;
 	tegra30_apbif_write(reg, val);
 
+	pm_runtime_put(ahub->dev);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(tegra30_ahub_enable_tx_fifo);
@@ -255,12 +275,16 @@ int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif)
 	int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
 	int reg, val;
 
+	pm_runtime_get_sync(ahub->dev);
+
 	reg = TEGRA30_AHUB_CHANNEL_CTRL +
 	      (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
 	val = tegra30_apbif_read(reg);
 	val &= ~TEGRA30_AHUB_CHANNEL_CTRL_TX_EN;
 	tegra30_apbif_write(reg, val);
 
+	pm_runtime_put(ahub->dev);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(tegra30_ahub_disable_tx_fifo);
@@ -281,10 +305,14 @@ int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif,
 	int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
 	int reg;
 
+	pm_runtime_get_sync(ahub->dev);
+
 	reg = TEGRA30_AHUB_AUDIO_RX +
 	      (channel * TEGRA30_AHUB_AUDIO_RX_STRIDE);
 	tegra30_audio_write(reg, 1 << txcif);
 
+	pm_runtime_put(ahub->dev);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(tegra30_ahub_set_rx_cif_source);
@@ -294,10 +322,14 @@ int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif)
 	int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
 	int reg;
 
+	pm_runtime_get_sync(ahub->dev);
+
 	reg = TEGRA30_AHUB_AUDIO_RX +
 	      (channel * TEGRA30_AHUB_AUDIO_RX_STRIDE);
 	tegra30_audio_write(reg, 0);
 
+	pm_runtime_put(ahub->dev);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(tegra30_ahub_unset_rx_cif_source);
-- 
1.8.1.5

Re: [PATCH 17/31] ASoC: tegra: call pm_runtime APIs around register accesses

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 921 bytes --]

On Fri, Nov 15, 2013 at 01:54:12PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Call pm_runtime_get_sync() before all register accesses; the HW requires
> clocks to be running when accessing registers.
> 
> This hasn't been needed to date, since all register IO was performed
> while playback was active, and hence the ASoC core had already called
> pm_runtime_get(). However, an imminent future commit will allocate and
> set up the FIFOs and routing during probe(), when that "protection"
> won't be in place.

Acked-by: Mark Brown <broonie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

However should we fix this at the regmap level in the same way that we
do for clocks?  That would need to be using _put_autosuspend() to avoid
being horrific.  Or alternatively should the driver be making the device
cache only when runtime PM is disabled?

[-- Attachment #2: Digital signature --]
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[PATCH 17/31] ASoC: tegra: call pm_runtime APIs around register accesses

[Mark Brown]

On Fri, Nov 15, 2013 at 01:54:12PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Call pm_runtime_get_sync() before all register accesses; the HW requires
> clocks to be running when accessing registers.
> 
> This hasn't been needed to date, since all register IO was performed
> while playback was active, and hence the ASoC core had already called
> pm_runtime_get(). However, an imminent future commit will allocate and
> set up the FIFOs and routing during probe(), when that "protection"
> won't be in place.

Acked-by: Mark Brown <broonie@linaro.org>

However should we fix this at the regmap level in the same way that we
do for clocks?  That would need to be using _put_autosuspend() to avoid
being horrific.  Or alternatively should the driver be making the device
cache only when runtime PM is disabled?
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Re: [PATCH 17/31] ASoC: tegra: call pm_runtime APIs around register accesses

[Stephen Warren]

On 11/16/2013 03:02 AM, Mark Brown wrote:
> On Fri, Nov 15, 2013 at 01:54:12PM -0700, Stephen Warren wrote:
>> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
>> Call pm_runtime_get_sync() before all register accesses; the HW requires
>> clocks to be running when accessing registers.
>>
>> This hasn't been needed to date, since all register IO was performed
>> while playback was active, and hence the ASoC core had already called
>> pm_runtime_get(). However, an imminent future commit will allocate and
>> set up the FIFOs and routing during probe(), when that "protection"
>> won't be in place.
> 
> Acked-by: Mark Brown <broonie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> 
> However should we fix this at the regmap level in the same way that we
> do for clocks?  That would need to be using _put_autosuspend() to avoid
> being horrific.

I did wonder about that, but it seemed like rather a lot of overhead?

> Or alternatively should the driver be making the device
> cache only when runtime PM is disabled?

The regmap is already cache-only when runtime-suspended. However the
registers don't get flushed during resume. I suppose that would require
only adding one extra call to the PM resume function?

For some reason, my gut prefers this current solution, but I could be
persuaded.

[PATCH 17/31] ASoC: tegra: call pm_runtime APIs around register accesses

[Stephen Warren]

On 11/16/2013 03:02 AM, Mark Brown wrote:
> On Fri, Nov 15, 2013 at 01:54:12PM -0700, Stephen Warren wrote:
>> From: Stephen Warren <swarren@nvidia.com>
>>
>> Call pm_runtime_get_sync() before all register accesses; the HW requires
>> clocks to be running when accessing registers.
>>
>> This hasn't been needed to date, since all register IO was performed
>> while playback was active, and hence the ASoC core had already called
>> pm_runtime_get(). However, an imminent future commit will allocate and
>> set up the FIFOs and routing during probe(), when that "protection"
>> won't be in place.
> 
> Acked-by: Mark Brown <broonie@linaro.org>
> 
> However should we fix this at the regmap level in the same way that we
> do for clocks?  That would need to be using _put_autosuspend() to avoid
> being horrific.

I did wonder about that, but it seemed like rather a lot of overhead?

> Or alternatively should the driver be making the device
> cache only when runtime PM is disabled?

The regmap is already cache-only when runtime-suspended. However the
registers don't get flushed during resume. I suppose that would require
only adding one extra call to the PM resume function?

For some reason, my gut prefers this current solution, but I could be
persuaded.

Re: [PATCH 17/31] ASoC: tegra: call pm_runtime APIs around register accesses

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 829 bytes --]

On Mon, Nov 18, 2013 at 10:25:46AM -0700, Stephen Warren wrote:
> On 11/16/2013 03:02 AM, Mark Brown wrote:

> > Or alternatively should the driver be making the device
> > cache only when runtime PM is disabled?

> The regmap is already cache-only when runtime-suspended. However the
> registers don't get flushed during resume. I suppose that would require
> only adding one extra call to the PM resume function?

Yup, should probably do that anyway since that's going to bite someone
otherwise.  We probably want a single operation to flush and enable
writes now I think about it, it's the common case.

> For some reason, my gut prefers this current solution, but I could be
> persuaded.

I'm not dead set against doing it this way, it's just that it feels like
if it's required something's not working as well as it should.

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[PATCH 17/31] ASoC: tegra: call pm_runtime APIs around register accesses

[Mark Brown]

On Mon, Nov 18, 2013 at 10:25:46AM -0700, Stephen Warren wrote:
> On 11/16/2013 03:02 AM, Mark Brown wrote:

> > Or alternatively should the driver be making the device
> > cache only when runtime PM is disabled?

> The regmap is already cache-only when runtime-suspended. However the
> registers don't get flushed during resume. I suppose that would require
> only adding one extra call to the PM resume function?

Yup, should probably do that anyway since that's going to bite someone
otherwise.  We probably want a single operation to flush and enable
writes now I think about it, it's the common case.

> For some reason, my gut prefers this current solution, but I could be
> persuaded.

I'm not dead set against doing it this way, it's just that it feels like
if it's required something's not working as well as it should.
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Re: [PATCH 17/31] ASoC: tegra: call pm_runtime APIs around register accesses

[Stephen Warren]

On 11/18/2013 11:39 AM, Mark Brown wrote:
> On Mon, Nov 18, 2013 at 10:25:46AM -0700, Stephen Warren wrote:
>> On 11/16/2013 03:02 AM, Mark Brown wrote:
> 
>>> Or alternatively should the driver be making the device cache
>>> only when runtime PM is disabled?
> 
>> The regmap is already cache-only when runtime-suspended. However
>> the registers don't get flushed during resume. I suppose that
>> would require only adding one extra call to the PM resume
>> function?
> 
> Yup, should probably do that anyway since that's going to bite
> someone otherwise.  We probably want a single operation to flush
> and enable writes now I think about it, it's the common case.
> 
>> For some reason, my gut prefers this current solution, but I
>> could be persuaded.
> 
> I'm not dead set against doing it this way, it's just that it feels
> like if it's required something's not working as well as it
> should.

The problems with the following approach:

 static int tegra30_ahub_runtime_resume(struct device *dev)
 ...
 	regcache_cache_only(ahub->regmap_apbif, false);
 	regcache_cache_only(ahub->regmap_ahub, false);
+	regcache_sync(ahub->regmap_apbif, false);
+	regcache_sync(ahub->regmap_ahub, false);

(or an automated variant of it, whereby regmap automatically does the
sync inside cache_only(false)) are:

1) regcache_sync() doesn't mean "if the cache is dirty, flush the
dirty registers to HW", but rather, "if the cache is dirty, write any
registers that don't match HW defaults to HW". If the HW was in
cache-only mode because simply because clocks were turned off but not
power, then the register values were retained, and the current HW
register values may not be "HW defaults", and you may in fact /need/
to write a value to HW that matches the HW default, yet is different
from the current retained register content.

2) tegra30_ahub_allocate_tx_fifo() does a read-modify-write of a
control register, and may execute when cache_only(true). If that
register was never touched while cache_only(false), which is the case
the first time the r-m-w happens, then there is no cached value, so
the regmap_read() for it will fail. This will either cause
tegra30_ahub_allocate_tx_fifo() to use uninitialized return data from
regmap_read() (if error-checking is missing, which it is), or fail (if
the error-checking were present). Neither is a good choice. Possible
solutions are:

a) Make regmap creation read the initial HW state to use as HW
defaults when the regmap is created. IIRC, this is done for some
regmap configurations but not others. That said, this doesn't seem
correct, since there's no guarantee that the HW state when the regmap
is created /is/ the default HW state.

b) Add a table of HW register defaults. Aside from this issue, there's
no need for this, so I'm not really motivated to do this. Besides, the
number of registers is rather large.

c) Simply put pm_runtime_get()/put() around the body of
tegra30_ahub_allocate_tx_fifo(), which works fine, and was my original
patch.

d) Have regmap_read/write do a pm_runtime_get()/put() themselves. I
know you mentioned this earlier in the thread, but you'd rejected this
approach when I first upstreamed this AHUB driver, and said to rely on
cache_only instead.

I think I still prefer option (c).

[PATCH 17/31] ASoC: tegra: call pm_runtime APIs around register accesses

[Stephen Warren]

On 11/18/2013 11:39 AM, Mark Brown wrote:
> On Mon, Nov 18, 2013 at 10:25:46AM -0700, Stephen Warren wrote:
>> On 11/16/2013 03:02 AM, Mark Brown wrote:
> 
>>> Or alternatively should the driver be making the device cache
>>> only when runtime PM is disabled?
> 
>> The regmap is already cache-only when runtime-suspended. However
>> the registers don't get flushed during resume. I suppose that
>> would require only adding one extra call to the PM resume
>> function?
> 
> Yup, should probably do that anyway since that's going to bite
> someone otherwise.  We probably want a single operation to flush
> and enable writes now I think about it, it's the common case.
> 
>> For some reason, my gut prefers this current solution, but I
>> could be persuaded.
> 
> I'm not dead set against doing it this way, it's just that it feels
> like if it's required something's not working as well as it
> should.

The problems with the following approach:

 static int tegra30_ahub_runtime_resume(struct device *dev)
 ...
 	regcache_cache_only(ahub->regmap_apbif, false);
 	regcache_cache_only(ahub->regmap_ahub, false);
+	regcache_sync(ahub->regmap_apbif, false);
+	regcache_sync(ahub->regmap_ahub, false);

(or an automated variant of it, whereby regmap automatically does the
sync inside cache_only(false)) are:

1) regcache_sync() doesn't mean "if the cache is dirty, flush the
dirty registers to HW", but rather, "if the cache is dirty, write any
registers that don't match HW defaults to HW". If the HW was in
cache-only mode because simply because clocks were turned off but not
power, then the register values were retained, and the current HW
register values may not be "HW defaults", and you may in fact /need/
to write a value to HW that matches the HW default, yet is different
from the current retained register content.

2) tegra30_ahub_allocate_tx_fifo() does a read-modify-write of a
control register, and may execute when cache_only(true). If that
register was never touched while cache_only(false), which is the case
the first time the r-m-w happens, then there is no cached value, so
the regmap_read() for it will fail. This will either cause
tegra30_ahub_allocate_tx_fifo() to use uninitialized return data from
regmap_read() (if error-checking is missing, which it is), or fail (if
the error-checking were present). Neither is a good choice. Possible
solutions are:

a) Make regmap creation read the initial HW state to use as HW
defaults when the regmap is created. IIRC, this is done for some
regmap configurations but not others. That said, this doesn't seem
correct, since there's no guarantee that the HW state when the regmap
is created /is/ the default HW state.

b) Add a table of HW register defaults. Aside from this issue, there's
no need for this, so I'm not really motivated to do this. Besides, the
number of registers is rather large.

c) Simply put pm_runtime_get()/put() around the body of
tegra30_ahub_allocate_tx_fifo(), which works fine, and was my original
patch.

d) Have regmap_read/write do a pm_runtime_get()/put() themselves. I
know you mentioned this earlier in the thread, but you'd rejected this
approach when I first upstreamed this AHUB driver, and said to rely on
cache_only instead.

I think I still prefer option (c).

Re: [PATCH 17/31] ASoC: tegra: call pm_runtime APIs around register accesses

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 1280 bytes --]

On Mon, Nov 18, 2013 at 03:38:36PM -0700, Stephen Warren wrote:

> 1) regcache_sync() doesn't mean "if the cache is dirty, flush the
> dirty registers to HW", but rather, "if the cache is dirty, write any
> registers that don't match HW defaults to HW". If the HW was in
> cache-only mode because simply because clocks were turned off but not
> power, then the register values were retained, and the current HW
> register values may not be "HW defaults", and you may in fact /need/
> to write a value to HW that matches the HW default, yet is different
> from the current retained register content.

OK, that's a potential problem in general...  Fortunately most of the
uses actually cut power.

> a) Make regmap creation read the initial HW state to use as HW
> defaults when the regmap is created. IIRC, this is done for some
> regmap configurations but not others. That said, this doesn't seem
> correct, since there's no guarantee that the HW state when the regmap
> is created /is/ the default HW state.

Right, this is why we don't initialise the cache by default.

> I think I still prefer option (c).

there's also the option of doing an explicit read on that register to
get it into the cache.  But yeah, like I say I'm not totally against
this and I did ack it already.

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[PATCH 17/31] ASoC: tegra: call pm_runtime APIs around register accesses

[Mark Brown]

On Mon, Nov 18, 2013 at 03:38:36PM -0700, Stephen Warren wrote:

> 1) regcache_sync() doesn't mean "if the cache is dirty, flush the
> dirty registers to HW", but rather, "if the cache is dirty, write any
> registers that don't match HW defaults to HW". If the HW was in
> cache-only mode because simply because clocks were turned off but not
> power, then the register values were retained, and the current HW
> register values may not be "HW defaults", and you may in fact /need/
> to write a value to HW that matches the HW default, yet is different
> from the current retained register content.

OK, that's a potential problem in general...  Fortunately most of the
uses actually cut power.

> a) Make regmap creation read the initial HW state to use as HW
> defaults when the regmap is created. IIRC, this is done for some
> regmap configurations but not others. That said, this doesn't seem
> correct, since there's no guarantee that the HW state when the regmap
> is created /is/ the default HW state.

Right, this is why we don't initialise the cache by default.

> I think I still prefer option (c).

there's also the option of doing an explicit read on that register to
get it into the cache.  But yeah, like I say I'm not totally against
this and I did ack it already.
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[PATCH 18/31] ASoC: tegra: allocate AHUB FIFO during probe() not startup()

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Teh Tegra30 I2S driver currently allocates DMA FIFOs from the AHUB only
when an audio stream starts playback. This is theoretically nice for
resource sharing, but makes no practical difference for any configuration
the drivers currently support. However, this deferral prevents conversion
to the standard DMA DT bindings, since conversion requires knowledge of
the specific DMA channel to be allocated, which in turn depends on which
specific FIFO was allocated.

For this reason, move the FIFO allocate into probe() to allow later
conversion to the standard DMA DT bindings.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Liam Girdwood <lgirdwood-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 sound/soc/tegra/tegra30_i2s.c | 91 ++++++++++++++++++++++---------------------
 1 file changed, 47 insertions(+), 44 deletions(-)

diff --git a/sound/soc/tegra/tegra30_i2s.c b/sound/soc/tegra/tegra30_i2s.c
index 231a785b3921..531a1ff2101d 100644
--- a/sound/soc/tegra/tegra30_i2s.c
+++ b/sound/soc/tegra/tegra30_i2s.c
@@ -73,47 +73,6 @@ static int tegra30_i2s_runtime_resume(struct device *dev)
 	return 0;
 }
 
-static int tegra30_i2s_startup(struct snd_pcm_substream *substream,
-			struct snd_soc_dai *dai)
-{
-	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-	int ret;
-
-	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-		ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
-					&i2s->playback_dma_data.addr,
-					&i2s->playback_dma_data.slave_id);
-		i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-		i2s->playback_dma_data.maxburst = 4;
-		tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
-					       i2s->playback_fifo_cif);
-	} else {
-		ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
-					&i2s->capture_dma_data.addr,
-					&i2s->capture_dma_data.slave_id);
-		i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-		i2s->capture_dma_data.maxburst = 4;
-		tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
-					       i2s->capture_i2s_cif);
-	}
-
-	return ret;
-}
-
-static void tegra30_i2s_shutdown(struct snd_pcm_substream *substream,
-			struct snd_soc_dai *dai)
-{
-	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-
-	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-		tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
-		tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
-	} else {
-		tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
-		tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
-	}
-}
-
 static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
 				unsigned int fmt)
 {
@@ -317,8 +276,6 @@ static int tegra30_i2s_probe(struct snd_soc_dai *dai)
 }
 
 static struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
-	.startup	= tegra30_i2s_startup,
-	.shutdown	= tegra30_i2s_shutdown,
 	.set_fmt	= tegra30_i2s_set_fmt,
 	.hw_params	= tegra30_i2s_hw_params,
 	.trigger	= tegra30_i2s_trigger,
@@ -499,12 +456,44 @@ static int tegra30_i2s_platform_probe(struct platform_device *pdev)
 			goto err_pm_disable;
 	}
 
+	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+	i2s->playback_dma_data.maxburst = 4;
+	ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
+					    &i2s->playback_dma_data.addr,
+					    &i2s->playback_dma_data.slave_id);
+	if (ret) {
+		dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret);
+		goto err_suspend;
+	}
+	ret = tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
+					     i2s->playback_fifo_cif);
+	if (ret) {
+		dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
+		goto err_free_tx_fifo;
+	}
+
+	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+	i2s->capture_dma_data.maxburst = 4;
+	ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
+					    &i2s->capture_dma_data.addr,
+					    &i2s->capture_dma_data.slave_id);
+	if (ret) {
+		dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret);
+		goto err_unroute_tx_fifo;
+	}
+	ret = tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
+					     i2s->capture_i2s_cif);
+	if (ret) {
+		dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
+		goto err_free_rx_fifo;
+	}
+
 	ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component,
 				   &i2s->dai, 1);
 	if (ret) {
 		dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
 		ret = -ENOMEM;
-		goto err_suspend;
+		goto err_unroute_rx_fifo;
 	}
 
 	ret = tegra_pcm_platform_register(&pdev->dev);
@@ -517,6 +506,14 @@ static int tegra30_i2s_platform_probe(struct platform_device *pdev)
 
 err_unregister_component:
 	snd_soc_unregister_component(&pdev->dev);
+err_unroute_rx_fifo:
+	tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
+err_free_rx_fifo:
+	tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
+err_unroute_tx_fifo:
+	tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
+err_free_tx_fifo:
+	tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
 err_suspend:
 	if (!pm_runtime_status_suspended(&pdev->dev))
 		tegra30_i2s_runtime_suspend(&pdev->dev);
@@ -539,6 +536,12 @@ static int tegra30_i2s_platform_remove(struct platform_device *pdev)
 	tegra_pcm_platform_unregister(&pdev->dev);
 	snd_soc_unregister_component(&pdev->dev);
 
+	tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
+	tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
+
+	tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
+	tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
+
 	clk_put(i2s->clk_i2s);
 
 	return 0;
-- 
1.8.1.5

[PATCH 18/31] ASoC: tegra: allocate AHUB FIFO during probe() not startup()

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Teh Tegra30 I2S driver currently allocates DMA FIFOs from the AHUB only
when an audio stream starts playback. This is theoretically nice for
resource sharing, but makes no practical difference for any configuration
the drivers currently support. However, this deferral prevents conversion
to the standard DMA DT bindings, since conversion requires knowledge of
the specific DMA channel to be allocated, which in turn depends on which
specific FIFO was allocated.

For this reason, move the FIFO allocate into probe() to allow later
conversion to the standard DMA DT bindings.

Cc: treding at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: alsa-devel at alsa-project.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 sound/soc/tegra/tegra30_i2s.c | 91 ++++++++++++++++++++++---------------------
 1 file changed, 47 insertions(+), 44 deletions(-)

diff --git a/sound/soc/tegra/tegra30_i2s.c b/sound/soc/tegra/tegra30_i2s.c
index 231a785b3921..531a1ff2101d 100644
--- a/sound/soc/tegra/tegra30_i2s.c
+++ b/sound/soc/tegra/tegra30_i2s.c
@@ -73,47 +73,6 @@ static int tegra30_i2s_runtime_resume(struct device *dev)
 	return 0;
 }
 
-static int tegra30_i2s_startup(struct snd_pcm_substream *substream,
-			struct snd_soc_dai *dai)
-{
-	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-	int ret;
-
-	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-		ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
-					&i2s->playback_dma_data.addr,
-					&i2s->playback_dma_data.slave_id);
-		i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-		i2s->playback_dma_data.maxburst = 4;
-		tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
-					       i2s->playback_fifo_cif);
-	} else {
-		ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
-					&i2s->capture_dma_data.addr,
-					&i2s->capture_dma_data.slave_id);
-		i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-		i2s->capture_dma_data.maxburst = 4;
-		tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
-					       i2s->capture_i2s_cif);
-	}
-
-	return ret;
-}
-
-static void tegra30_i2s_shutdown(struct snd_pcm_substream *substream,
-			struct snd_soc_dai *dai)
-{
-	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-
-	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-		tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
-		tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
-	} else {
-		tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
-		tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
-	}
-}
-
 static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
 				unsigned int fmt)
 {
@@ -317,8 +276,6 @@ static int tegra30_i2s_probe(struct snd_soc_dai *dai)
 }
 
 static struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
-	.startup	= tegra30_i2s_startup,
-	.shutdown	= tegra30_i2s_shutdown,
 	.set_fmt	= tegra30_i2s_set_fmt,
 	.hw_params	= tegra30_i2s_hw_params,
 	.trigger	= tegra30_i2s_trigger,
@@ -499,12 +456,44 @@ static int tegra30_i2s_platform_probe(struct platform_device *pdev)
 			goto err_pm_disable;
 	}
 
+	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+	i2s->playback_dma_data.maxburst = 4;
+	ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
+					    &i2s->playback_dma_data.addr,
+					    &i2s->playback_dma_data.slave_id);
+	if (ret) {
+		dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret);
+		goto err_suspend;
+	}
+	ret = tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
+					     i2s->playback_fifo_cif);
+	if (ret) {
+		dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
+		goto err_free_tx_fifo;
+	}
+
+	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+	i2s->capture_dma_data.maxburst = 4;
+	ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
+					    &i2s->capture_dma_data.addr,
+					    &i2s->capture_dma_data.slave_id);
+	if (ret) {
+		dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret);
+		goto err_unroute_tx_fifo;
+	}
+	ret = tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
+					     i2s->capture_i2s_cif);
+	if (ret) {
+		dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
+		goto err_free_rx_fifo;
+	}
+
 	ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component,
 				   &i2s->dai, 1);
 	if (ret) {
 		dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
 		ret = -ENOMEM;
-		goto err_suspend;
+		goto err_unroute_rx_fifo;
 	}
 
 	ret = tegra_pcm_platform_register(&pdev->dev);
@@ -517,6 +506,14 @@ static int tegra30_i2s_platform_probe(struct platform_device *pdev)
 
 err_unregister_component:
 	snd_soc_unregister_component(&pdev->dev);
+err_unroute_rx_fifo:
+	tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
+err_free_rx_fifo:
+	tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
+err_unroute_tx_fifo:
+	tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
+err_free_tx_fifo:
+	tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
 err_suspend:
 	if (!pm_runtime_status_suspended(&pdev->dev))
 		tegra30_i2s_runtime_suspend(&pdev->dev);
@@ -539,6 +536,12 @@ static int tegra30_i2s_platform_remove(struct platform_device *pdev)
 	tegra_pcm_platform_unregister(&pdev->dev);
 	snd_soc_unregister_component(&pdev->dev);
 
+	tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
+	tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
+
+	tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
+	tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
+
 	clk_put(i2s->clk_i2s);
 
 	return 0;
-- 
1.8.1.5

Re: [PATCH 18/31] ASoC: tegra: allocate AHUB FIFO during probe() not startup()

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 441 bytes --]

On Fri, Nov 15, 2013 at 01:54:13PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Teh Tegra30 I2S driver currently allocates DMA FIFOs from the AHUB only
> when an audio stream starts playback. This is theoretically nice for
> resource sharing, but makes no practical difference for any configuration

Acked-by: Mark Brown <broonie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

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[PATCH 18/31] ASoC: tegra: allocate AHUB FIFO during probe() not startup()

[Mark Brown]

On Fri, Nov 15, 2013 at 01:54:13PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Teh Tegra30 I2S driver currently allocates DMA FIFOs from the AHUB only
> when an audio stream starts playback. This is theoretically nice for
> resource sharing, but makes no practical difference for any configuration

Acked-by: Mark Brown <broonie@linaro.org>
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Re: [PATCH 18/31] ASoC: tegra: allocate AHUB FIFO during probe() not startup()

[Thierry Reding]

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On Fri, Nov 15, 2013 at 01:54:13PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Teh Tegra30 I2S driver currently allocates DMA FIFOs from the AHUB only

s/Teh/The/

> when an audio stream starts playback. This is theoretically nice for
> resource sharing, but makes no practical difference for any configuration
> the drivers currently support. However, this deferral prevents conversion
> to the standard DMA DT bindings, since conversion requires knowledge of
> the specific DMA channel to be allocated, which in turn depends on which
> specific FIFO was allocated.
> 
> For this reason, move the FIFO allocate into probe() to allow later

s/allocate/allocation/?

[...]
> +	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> +	i2s->playback_dma_data.maxburst = 4;
> +	ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
> +					    &i2s->playback_dma_data.addr,
> +					    &i2s->playback_dma_data.slave_id);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret);
> +		goto err_suspend;
> +	}
> +	ret = tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
> +					     i2s->playback_fifo_cif);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
> +		goto err_free_tx_fifo;
> +	}
> +
> +	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> +	i2s->capture_dma_data.maxburst = 4;
> +	ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
> +					    &i2s->capture_dma_data.addr,
> +					    &i2s->capture_dma_data.slave_id);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret);
> +		goto err_unroute_tx_fifo;
> +	}
> +	ret = tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
> +					     i2s->capture_i2s_cif);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
> +		goto err_free_rx_fifo;
> +	}
> +

It could be useful to have these in a separate function so as not to
make the .probe() any larger. It's already pretty big as it is.

Thierry

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[PATCH 18/31] ASoC: tegra: allocate AHUB FIFO during probe() not startup()

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:54:13PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Teh Tegra30 I2S driver currently allocates DMA FIFOs from the AHUB only

s/Teh/The/

> when an audio stream starts playback. This is theoretically nice for
> resource sharing, but makes no practical difference for any configuration
> the drivers currently support. However, this deferral prevents conversion
> to the standard DMA DT bindings, since conversion requires knowledge of
> the specific DMA channel to be allocated, which in turn depends on which
> specific FIFO was allocated.
> 
> For this reason, move the FIFO allocate into probe() to allow later

s/allocate/allocation/?

[...]
> +	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> +	i2s->playback_dma_data.maxburst = 4;
> +	ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
> +					    &i2s->playback_dma_data.addr,
> +					    &i2s->playback_dma_data.slave_id);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret);
> +		goto err_suspend;
> +	}
> +	ret = tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
> +					     i2s->playback_fifo_cif);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
> +		goto err_free_tx_fifo;
> +	}
> +
> +	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> +	i2s->capture_dma_data.maxburst = 4;
> +	ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
> +					    &i2s->capture_dma_data.addr,
> +					    &i2s->capture_dma_data.slave_id);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret);
> +		goto err_unroute_tx_fifo;
> +	}
> +	ret = tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
> +					     i2s->capture_i2s_cif);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
> +		goto err_free_rx_fifo;
> +	}
> +

It could be useful to have these in a separate function so as not to
make the .probe() any larger. It's already pretty big as it is.

Thierry
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Re: [PATCH 18/31] ASoC: tegra: allocate AHUB FIFO during probe() not startup()

[Stephen Warren]

On 11/29/2013 07:40 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:54:13PM -0700, Stephen Warren wrote:
>> Teh Tegra30 I2S driver currently allocates DMA FIFOs from the
>> AHUB only when an audio stream starts playback. This is
>> theoretically nice for resource sharing, but makes no practical
>> difference for any configuration the drivers currently support.
>> However, this deferral prevents conversion to the standard DMA DT
>> bindings, since conversion requires knowledge of the specific DMA
>> channel to be allocated, which in turn depends on which specific
>> FIFO was allocated.
>> 
>> For this reason, move the FIFO allocate into probe() to allow
>> later
...
>> +	i2s->playback_dma_data.addr_width =
>> DMA_SLAVE_BUSWIDTH_4_BYTES; +	i2s->playback_dma_data.maxburst =
>> 4; +	ret =
>> tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif, +
>> &i2s->playback_dma_data.addr, +
>> &i2s->playback_dma_data.slave_id); +	if (ret) { +
>> dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret); +
>> goto err_suspend; +	} +	ret =
>> tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif, +
>> i2s->playback_fifo_cif); +	if (ret) { +		dev_err(&pdev->dev,
>> "Could not route TX FIFO: %d\n", ret); +		goto err_free_tx_fifo; 
>> +	} + +	i2s->capture_dma_data.addr_width =
>> DMA_SLAVE_BUSWIDTH_4_BYTES; +	i2s->capture_dma_data.maxburst =
>> 4; +	ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif, 
>> +					    &i2s->capture_dma_data.addr, +
>> &i2s->capture_dma_data.slave_id); +	if (ret) { +
>> dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret); +
>> goto err_unroute_tx_fifo; +	} +	ret =
>> tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif, +
>> i2s->capture_i2s_cif); +	if (ret) { +		dev_err(&pdev->dev, "Could
>> not route TX FIFO: %d\n", ret); +		goto err_free_rx_fifo; +	} +
> 
> It could be useful to have these in a separate function so as not
> to make the .probe() any larger. It's already pretty big as it is.

May I ignore this; I personally prefer larger linear functions; it's
much easier to follow the code-flow without having to jump back/forth
between a bunch of single-use functions.

[PATCH 18/31] ASoC: tegra: allocate AHUB FIFO during probe() not startup()

[Stephen Warren]

On 11/29/2013 07:40 AM, Thierry Reding wrote:
> On Fri, Nov 15, 2013 at 01:54:13PM -0700, Stephen Warren wrote:
>> Teh Tegra30 I2S driver currently allocates DMA FIFOs from the
>> AHUB only when an audio stream starts playback. This is
>> theoretically nice for resource sharing, but makes no practical
>> difference for any configuration the drivers currently support.
>> However, this deferral prevents conversion to the standard DMA DT
>> bindings, since conversion requires knowledge of the specific DMA
>> channel to be allocated, which in turn depends on which specific
>> FIFO was allocated.
>> 
>> For this reason, move the FIFO allocate into probe() to allow
>> later
...
>> +	i2s->playback_dma_data.addr_width =
>> DMA_SLAVE_BUSWIDTH_4_BYTES; +	i2s->playback_dma_data.maxburst =
>> 4; +	ret =
>> tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif, +
>> &i2s->playback_dma_data.addr, +
>> &i2s->playback_dma_data.slave_id); +	if (ret) { +
>> dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret); +
>> goto err_suspend; +	} +	ret =
>> tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif, +
>> i2s->playback_fifo_cif); +	if (ret) { +		dev_err(&pdev->dev,
>> "Could not route TX FIFO: %d\n", ret); +		goto err_free_tx_fifo; 
>> +	} + +	i2s->capture_dma_data.addr_width =
>> DMA_SLAVE_BUSWIDTH_4_BYTES; +	i2s->capture_dma_data.maxburst =
>> 4; +	ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif, 
>> +					    &i2s->capture_dma_data.addr, +
>> &i2s->capture_dma_data.slave_id); +	if (ret) { +
>> dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret); +
>> goto err_unroute_tx_fifo; +	} +	ret =
>> tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif, +
>> i2s->capture_i2s_cif); +	if (ret) { +		dev_err(&pdev->dev, "Could
>> not route TX FIFO: %d\n", ret); +		goto err_free_rx_fifo; +	} +
> 
> It could be useful to have these in a separate function so as not
> to make the .probe() any larger. It's already pretty big as it is.

May I ignore this; I personally prefer larger linear functions; it's
much easier to follow the code-flow without having to jump back/forth
between a bunch of single-use functions.

Re: [PATCH 18/31] ASoC: tegra: allocate AHUB FIFO during probe() not startup()

[Thierry Reding]

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On Tue, Dec 03, 2013 at 12:55:55PM -0700, Stephen Warren wrote:
> On 11/29/2013 07:40 AM, Thierry Reding wrote:
> > On Fri, Nov 15, 2013 at 01:54:13PM -0700, Stephen Warren wrote:
> >> Teh Tegra30 I2S driver currently allocates DMA FIFOs from the
> >> AHUB only when an audio stream starts playback. This is
> >> theoretically nice for resource sharing, but makes no practical
> >> difference for any configuration the drivers currently support.
> >> However, this deferral prevents conversion to the standard DMA DT
> >> bindings, since conversion requires knowledge of the specific DMA
> >> channel to be allocated, which in turn depends on which specific
> >> FIFO was allocated.
> >> 
> >> For this reason, move the FIFO allocate into probe() to allow
> >> later
> ...
> >> +	i2s->playback_dma_data.addr_width =
> >> DMA_SLAVE_BUSWIDTH_4_BYTES; +	i2s->playback_dma_data.maxburst =
> >> 4; +	ret =
> >> tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif, +
> >> &i2s->playback_dma_data.addr, +
> >> &i2s->playback_dma_data.slave_id); +	if (ret) { +
> >> dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret); +
> >> goto err_suspend; +	} +	ret =
> >> tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif, +
> >> i2s->playback_fifo_cif); +	if (ret) { +		dev_err(&pdev->dev,
> >> "Could not route TX FIFO: %d\n", ret); +		goto err_free_tx_fifo; 
> >> +	} + +	i2s->capture_dma_data.addr_width =
> >> DMA_SLAVE_BUSWIDTH_4_BYTES; +	i2s->capture_dma_data.maxburst =
> >> 4; +	ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif, 
> >> +					    &i2s->capture_dma_data.addr, +
> >> &i2s->capture_dma_data.slave_id); +	if (ret) { +
> >> dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret); +
> >> goto err_unroute_tx_fifo; +	} +	ret =
> >> tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif, +
> >> i2s->capture_i2s_cif); +	if (ret) { +		dev_err(&pdev->dev, "Could
> >> not route TX FIFO: %d\n", ret); +		goto err_free_rx_fifo; +	} +
> > 
> > It could be useful to have these in a separate function so as not
> > to make the .probe() any larger. It's already pretty big as it is.
> 
> May I ignore this; I personally prefer larger linear functions; it's
> much easier to follow the code-flow without having to jump back/forth
> between a bunch of single-use functions.

Alright, I won't lose any sleep over it.

Thierry

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[PATCH 18/31] ASoC: tegra: allocate AHUB FIFO during probe() not startup()

[Thierry Reding]

On Tue, Dec 03, 2013 at 12:55:55PM -0700, Stephen Warren wrote:
> On 11/29/2013 07:40 AM, Thierry Reding wrote:
> > On Fri, Nov 15, 2013 at 01:54:13PM -0700, Stephen Warren wrote:
> >> Teh Tegra30 I2S driver currently allocates DMA FIFOs from the
> >> AHUB only when an audio stream starts playback. This is
> >> theoretically nice for resource sharing, but makes no practical
> >> difference for any configuration the drivers currently support.
> >> However, this deferral prevents conversion to the standard DMA DT
> >> bindings, since conversion requires knowledge of the specific DMA
> >> channel to be allocated, which in turn depends on which specific
> >> FIFO was allocated.
> >> 
> >> For this reason, move the FIFO allocate into probe() to allow
> >> later
> ...
> >> +	i2s->playback_dma_data.addr_width =
> >> DMA_SLAVE_BUSWIDTH_4_BYTES; +	i2s->playback_dma_data.maxburst =
> >> 4; +	ret =
> >> tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif, +
> >> &i2s->playback_dma_data.addr, +
> >> &i2s->playback_dma_data.slave_id); +	if (ret) { +
> >> dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret); +
> >> goto err_suspend; +	} +	ret =
> >> tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif, +
> >> i2s->playback_fifo_cif); +	if (ret) { +		dev_err(&pdev->dev,
> >> "Could not route TX FIFO: %d\n", ret); +		goto err_free_tx_fifo; 
> >> +	} + +	i2s->capture_dma_data.addr_width =
> >> DMA_SLAVE_BUSWIDTH_4_BYTES; +	i2s->capture_dma_data.maxburst =
> >> 4; +	ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif, 
> >> +					    &i2s->capture_dma_data.addr, +
> >> &i2s->capture_dma_data.slave_id); +	if (ret) { +
> >> dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret); +
> >> goto err_unroute_tx_fifo; +	} +	ret =
> >> tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif, +
> >> i2s->capture_i2s_cif); +	if (ret) { +		dev_err(&pdev->dev, "Could
> >> not route TX FIFO: %d\n", ret); +		goto err_free_rx_fifo; +	} +
> > 
> > It could be useful to have these in a separate function so as not
> > to make the .probe() any larger. It's already pretty big as it is.
> 
> May I ignore this; I personally prefer larger linear functions; it's
> much easier to follow the code-flow without having to jump back/forth
> between a bunch of single-use functions.

Alright, I won't lose any sleep over it.

Thierry
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[PATCH 19/31] ASoC: tegra: convert to standard DMA DT bindings

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

By passing no flags when calling snd_dmaengine_pcm_register() from
tegra_pcm.c, we end up using dma_request_slave_channel() rather than
dmaengine_pcm_compat_request_channel(), and hence rely on the standard
DMA DT bindings and stashing the DMA slave ID away during channel
allocation. This means there's no need to use a custom DT property to
store the slave ID. So, remove all the code that parsed it.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Liam Girdwood <lgirdwood-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 sound/soc/tegra/tegra20_ac97.c | 11 -----------
 sound/soc/tegra/tegra20_i2s.c  | 20 +-------------------
 sound/soc/tegra/tegra30_ahub.c | 23 ++++++-----------------
 sound/soc/tegra/tegra30_ahub.h |  9 ++++-----
 sound/soc/tegra/tegra30_i2s.c  | 14 +++++++++-----
 sound/soc/tegra/tegra30_i2s.h  |  3 +++
 sound/soc/tegra/tegra_pcm.c    | 17 ++++++++++++++---
 sound/soc/tegra/tegra_pcm.h    |  5 +++++
 8 files changed, 42 insertions(+), 60 deletions(-)

diff --git a/sound/soc/tegra/tegra20_ac97.c b/sound/soc/tegra/tegra20_ac97.c
index ae27bcd586d2..d8b98d70ff41 100644
--- a/sound/soc/tegra/tegra20_ac97.c
+++ b/sound/soc/tegra/tegra20_ac97.c
@@ -313,7 +313,6 @@ static int tegra20_ac97_platform_probe(struct platform_device *pdev)
 {
 	struct tegra20_ac97 *ac97;
 	struct resource *mem;
-	u32 of_dma[2];
 	void __iomem *regs;
 	int ret = 0;
 
@@ -348,14 +347,6 @@ static int tegra20_ac97_platform_probe(struct platform_device *pdev)
 		goto err_clk_put;
 	}
 
-	if (of_property_read_u32_array(pdev->dev.of_node,
-				       "nvidia,dma-request-selector",
-				       of_dma, 2) < 0) {
-		dev_err(&pdev->dev, "No DMA resource\n");
-		ret = -ENODEV;
-		goto err_clk_put;
-	}
-
 	ac97->reset_gpio = of_get_named_gpio(pdev->dev.of_node,
 					     "nvidia,codec-reset-gpio", 0);
 	if (gpio_is_valid(ac97->reset_gpio)) {
@@ -380,12 +371,10 @@ static int tegra20_ac97_platform_probe(struct platform_device *pdev)
 	ac97->capture_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_RX1;
 	ac97->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 	ac97->capture_dma_data.maxburst = 4;
-	ac97->capture_dma_data.slave_id = of_dma[1];
 
 	ac97->playback_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_TX1;
 	ac97->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 	ac97->playback_dma_data.maxburst = 4;
-	ac97->playback_dma_data.slave_id = of_dma[1];
 
 	ret = tegra_asoc_utils_init(&ac97->util_data, &pdev->dev);
 	if (ret)
diff --git a/sound/soc/tegra/tegra20_i2s.c b/sound/soc/tegra/tegra20_i2s.c
index 364bf6a907e1..1dc869c475e7 100644
--- a/sound/soc/tegra/tegra20_i2s.c
+++ b/sound/soc/tegra/tegra20_i2s.c
@@ -339,9 +339,7 @@ static const struct regmap_config tegra20_i2s_regmap_config = {
 static int tegra20_i2s_platform_probe(struct platform_device *pdev)
 {
 	struct tegra20_i2s *i2s;
-	struct resource *mem, *memregion, *dmareq;
-	u32 of_dma[2];
-	u32 dma_ch;
+	struct resource *mem, *memregion;
 	void __iomem *regs;
 	int ret;
 
@@ -370,20 +368,6 @@ static int tegra20_i2s_platform_probe(struct platform_device *pdev)
 		goto err_clk_put;
 	}
 
-	dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
-	if (!dmareq) {
-		if (of_property_read_u32_array(pdev->dev.of_node,
-					"nvidia,dma-request-selector",
-					of_dma, 2) < 0) {
-			dev_err(&pdev->dev, "No DMA resource\n");
-			ret = -ENODEV;
-			goto err_clk_put;
-		}
-		dma_ch = of_dma[1];
-	} else {
-		dma_ch = dmareq->start;
-	}
-
 	memregion = devm_request_mem_region(&pdev->dev, mem->start,
 					    resource_size(mem), DRV_NAME);
 	if (!memregion) {
@@ -410,12 +394,10 @@ static int tegra20_i2s_platform_probe(struct platform_device *pdev)
 	i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2;
 	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 	i2s->capture_dma_data.maxburst = 4;
-	i2s->capture_dma_data.slave_id = dma_ch;
 
 	i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1;
 	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 	i2s->playback_dma_data.maxburst = 4;
-	i2s->playback_dma_data.slave_id = dma_ch;
 
 	pm_runtime_enable(&pdev->dev);
 	if (!pm_runtime_enabled(&pdev->dev)) {
diff --git a/sound/soc/tegra/tegra30_ahub.c b/sound/soc/tegra/tegra30_ahub.c
index 2f1a566dd9cc..572fab23e75f 100644
--- a/sound/soc/tegra/tegra30_ahub.c
+++ b/sound/soc/tegra/tegra30_ahub.c
@@ -96,8 +96,8 @@ static int tegra30_ahub_runtime_resume(struct device *dev)
 }
 
 int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
-				  dma_addr_t *fiforeg,
-				  unsigned int *reqsel)
+				  char *dmachan, int dmachan_len,
+				  dma_addr_t *fiforeg)
 {
 	int channel;
 	u32 reg, val;
@@ -111,9 +111,9 @@ int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
 	__set_bit(channel, ahub->rx_usage);
 
 	*rxcif = TEGRA30_AHUB_RXCIF_APBIF_RX0 + channel;
+	snprintf(dmachan, dmachan_len, "rx%d", channel);
 	*fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_RXFIFO +
 		   (channel * TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE);
-	*reqsel = ahub->dma_sel + channel;
 
 	pm_runtime_get_sync(ahub->dev);
 
@@ -198,8 +198,8 @@ int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif)
 EXPORT_SYMBOL_GPL(tegra30_ahub_free_rx_fifo);
 
 int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
-				  dma_addr_t *fiforeg,
-				  unsigned int *reqsel)
+				  char *dmachan, int dmachan_len,
+				  dma_addr_t *fiforeg)
 {
 	int channel;
 	u32 reg, val;
@@ -213,9 +213,9 @@ int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
 	__set_bit(channel, ahub->tx_usage);
 
 	*txcif = TEGRA30_AHUB_TXCIF_APBIF_TX0 + channel;
+	snprintf(dmachan, dmachan_len, "tx%d", channel);
 	*fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_TXFIFO +
 		   (channel * TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE);
-	*reqsel = ahub->dma_sel + channel;
 
 	pm_runtime_get_sync(ahub->dev);
 
@@ -511,7 +511,6 @@ static int tegra30_ahub_probe(struct platform_device *pdev)
 	struct reset_control *rst;
 	int i;
 	struct resource *res0, *res1, *region;
-	u32 of_dma[2];
 	void __iomem *regs_apbif, *regs_ahub;
 	int ret = 0;
 
@@ -574,16 +573,6 @@ static int tegra30_ahub_probe(struct platform_device *pdev)
 		goto err_clk_put_d_audio;
 	}
 
-	if (of_property_read_u32_array(pdev->dev.of_node,
-				"nvidia,dma-request-selector",
-				of_dma, 2) < 0) {
-		dev_err(&pdev->dev,
-			"Missing property nvidia,dma-request-selector\n");
-		ret = -ENODEV;
-		goto err_clk_put_d_audio;
-	}
-	ahub->dma_sel = of_dma[1];
-
 	res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res0) {
 		dev_err(&pdev->dev, "No apbif memory resource\n");
diff --git a/sound/soc/tegra/tegra30_ahub.h b/sound/soc/tegra/tegra30_ahub.h
index 1383f8cd3572..fd7ba75ed814 100644
--- a/sound/soc/tegra/tegra30_ahub.h
+++ b/sound/soc/tegra/tegra30_ahub.h
@@ -465,15 +465,15 @@ enum tegra30_ahub_rxcif {
 };
 
 extern int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
-					 dma_addr_t *fiforeg,
-					 unsigned int *reqsel);
+					 char *dmachan, int dmachan_len,
+					 dma_addr_t *fiforeg);
 extern int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif);
 extern int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif);
 extern int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif);
 
 extern int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
-					 dma_addr_t *fiforeg,
-					 unsigned int *reqsel);
+					 char *dmachan, int dmachan_len,
+					 dma_addr_t *fiforeg);
 extern int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif);
 extern int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif);
 extern int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif);
@@ -524,7 +524,6 @@ struct tegra30_ahub {
 	struct device *dev;
 	struct clk *clk_d_audio;
 	struct clk *clk_apbif;
-	int dma_sel;
 	resource_size_t apbif_addr;
 	struct regmap *regmap_apbif;
 	struct regmap *regmap_ahub;
diff --git a/sound/soc/tegra/tegra30_i2s.c b/sound/soc/tegra/tegra30_i2s.c
index 531a1ff2101d..362e8f728ddf 100644
--- a/sound/soc/tegra/tegra30_i2s.c
+++ b/sound/soc/tegra/tegra30_i2s.c
@@ -459,8 +459,9 @@ static int tegra30_i2s_platform_probe(struct platform_device *pdev)
 	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 	i2s->playback_dma_data.maxburst = 4;
 	ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
-					    &i2s->playback_dma_data.addr,
-					    &i2s->playback_dma_data.slave_id);
+					    i2s->playback_dma_chan,
+					    sizeof(i2s->playback_dma_chan),
+					    &i2s->playback_dma_data.addr);
 	if (ret) {
 		dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret);
 		goto err_suspend;
@@ -475,8 +476,9 @@ static int tegra30_i2s_platform_probe(struct platform_device *pdev)
 	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 	i2s->capture_dma_data.maxburst = 4;
 	ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
-					    &i2s->capture_dma_data.addr,
-					    &i2s->capture_dma_data.slave_id);
+					    i2s->capture_dma_chan,
+					    sizeof(i2s->capture_dma_chan),
+					    &i2s->capture_dma_data.addr);
 	if (ret) {
 		dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret);
 		goto err_unroute_tx_fifo;
@@ -496,7 +498,9 @@ static int tegra30_i2s_platform_probe(struct platform_device *pdev)
 		goto err_unroute_rx_fifo;
 	}
 
-	ret = tegra_pcm_platform_register(&pdev->dev);
+	ret = tegra_pcm_platform_register_with_chan_names(&pdev->dev,
+				&i2s->dma_config, i2s->playback_dma_chan,
+				i2s->capture_dma_chan);
 	if (ret) {
 		dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
 		goto err_unregister_component;
diff --git a/sound/soc/tegra/tegra30_i2s.h b/sound/soc/tegra/tegra30_i2s.h
index 4d0b0a30dbfb..774fc6ad2026 100644
--- a/sound/soc/tegra/tegra30_i2s.h
+++ b/sound/soc/tegra/tegra30_i2s.h
@@ -238,11 +238,14 @@ struct tegra30_i2s {
 	struct clk *clk_i2s;
 	enum tegra30_ahub_txcif capture_i2s_cif;
 	enum tegra30_ahub_rxcif capture_fifo_cif;
+	char capture_dma_chan[8];
 	struct snd_dmaengine_dai_dma_data capture_dma_data;
 	enum tegra30_ahub_rxcif playback_i2s_cif;
 	enum tegra30_ahub_txcif playback_fifo_cif;
+	char playback_dma_chan[8];
 	struct snd_dmaengine_dai_dma_data playback_dma_data;
 	struct regmap *regmap;
+	struct snd_dmaengine_pcm_config dma_config;
 };
 
 #endif
diff --git a/sound/soc/tegra/tegra_pcm.c b/sound/soc/tegra/tegra_pcm.c
index 7b2d23ba69b3..7ce5c334a660 100644
--- a/sound/soc/tegra/tegra_pcm.c
+++ b/sound/soc/tegra/tegra_pcm.c
@@ -61,12 +61,23 @@ static const struct snd_dmaengine_pcm_config tegra_dmaengine_pcm_config = {
 
 int tegra_pcm_platform_register(struct device *dev)
 {
-	return snd_dmaengine_pcm_register(dev, &tegra_dmaengine_pcm_config,
-			SND_DMAENGINE_PCM_FLAG_NO_DT |
-			SND_DMAENGINE_PCM_FLAG_COMPAT);
+	return snd_dmaengine_pcm_register(dev, &tegra_dmaengine_pcm_config, 0);
 }
 EXPORT_SYMBOL_GPL(tegra_pcm_platform_register);
 
+int tegra_pcm_platform_register_with_chan_names(struct device *dev,
+				struct snd_dmaengine_pcm_config *config,
+				char *txdmachan, char *rxdmachan)
+{
+	*config = tegra_dmaengine_pcm_config;
+	config->dma_dev = dev->parent;
+	config->chan_names[0] = txdmachan;
+	config->chan_names[1] = rxdmachan;
+
+	return snd_dmaengine_pcm_register(dev, config, 0);
+}
+EXPORT_SYMBOL_GPL(tegra_pcm_platform_register_with_chan_names);
+
 void tegra_pcm_platform_unregister(struct device *dev)
 {
 	return snd_dmaengine_pcm_unregister(dev);
diff --git a/sound/soc/tegra/tegra_pcm.h b/sound/soc/tegra/tegra_pcm.h
index 68ad901714a9..7883dec748a3 100644
--- a/sound/soc/tegra/tegra_pcm.h
+++ b/sound/soc/tegra/tegra_pcm.h
@@ -31,7 +31,12 @@
 #ifndef __TEGRA_PCM_H__
 #define __TEGRA_PCM_H__
 
+struct snd_dmaengine_pcm_config;
+
 int tegra_pcm_platform_register(struct device *dev);
+int tegra_pcm_platform_register_with_chan_names(struct device *dev,
+				struct snd_dmaengine_pcm_config *config,
+				char *txdmachan, char *rxdmachan);
 void tegra_pcm_platform_unregister(struct device *dev);
 
 #endif
-- 
1.8.1.5

[PATCH 19/31] ASoC: tegra: convert to standard DMA DT bindings

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

By passing no flags when calling snd_dmaengine_pcm_register() from
tegra_pcm.c, we end up using dma_request_slave_channel() rather than
dmaengine_pcm_compat_request_channel(), and hence rely on the standard
DMA DT bindings and stashing the DMA slave ID away during channel
allocation. This means there's no need to use a custom DT property to
store the slave ID. So, remove all the code that parsed it.

Cc: treding at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: alsa-devel at alsa-project.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 sound/soc/tegra/tegra20_ac97.c | 11 -----------
 sound/soc/tegra/tegra20_i2s.c  | 20 +-------------------
 sound/soc/tegra/tegra30_ahub.c | 23 ++++++-----------------
 sound/soc/tegra/tegra30_ahub.h |  9 ++++-----
 sound/soc/tegra/tegra30_i2s.c  | 14 +++++++++-----
 sound/soc/tegra/tegra30_i2s.h  |  3 +++
 sound/soc/tegra/tegra_pcm.c    | 17 ++++++++++++++---
 sound/soc/tegra/tegra_pcm.h    |  5 +++++
 8 files changed, 42 insertions(+), 60 deletions(-)

diff --git a/sound/soc/tegra/tegra20_ac97.c b/sound/soc/tegra/tegra20_ac97.c
index ae27bcd586d2..d8b98d70ff41 100644
--- a/sound/soc/tegra/tegra20_ac97.c
+++ b/sound/soc/tegra/tegra20_ac97.c
@@ -313,7 +313,6 @@ static int tegra20_ac97_platform_probe(struct platform_device *pdev)
 {
 	struct tegra20_ac97 *ac97;
 	struct resource *mem;
-	u32 of_dma[2];
 	void __iomem *regs;
 	int ret = 0;
 
@@ -348,14 +347,6 @@ static int tegra20_ac97_platform_probe(struct platform_device *pdev)
 		goto err_clk_put;
 	}
 
-	if (of_property_read_u32_array(pdev->dev.of_node,
-				       "nvidia,dma-request-selector",
-				       of_dma, 2) < 0) {
-		dev_err(&pdev->dev, "No DMA resource\n");
-		ret = -ENODEV;
-		goto err_clk_put;
-	}
-
 	ac97->reset_gpio = of_get_named_gpio(pdev->dev.of_node,
 					     "nvidia,codec-reset-gpio", 0);
 	if (gpio_is_valid(ac97->reset_gpio)) {
@@ -380,12 +371,10 @@ static int tegra20_ac97_platform_probe(struct platform_device *pdev)
 	ac97->capture_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_RX1;
 	ac97->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 	ac97->capture_dma_data.maxburst = 4;
-	ac97->capture_dma_data.slave_id = of_dma[1];
 
 	ac97->playback_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_TX1;
 	ac97->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 	ac97->playback_dma_data.maxburst = 4;
-	ac97->playback_dma_data.slave_id = of_dma[1];
 
 	ret = tegra_asoc_utils_init(&ac97->util_data, &pdev->dev);
 	if (ret)
diff --git a/sound/soc/tegra/tegra20_i2s.c b/sound/soc/tegra/tegra20_i2s.c
index 364bf6a907e1..1dc869c475e7 100644
--- a/sound/soc/tegra/tegra20_i2s.c
+++ b/sound/soc/tegra/tegra20_i2s.c
@@ -339,9 +339,7 @@ static const struct regmap_config tegra20_i2s_regmap_config = {
 static int tegra20_i2s_platform_probe(struct platform_device *pdev)
 {
 	struct tegra20_i2s *i2s;
-	struct resource *mem, *memregion, *dmareq;
-	u32 of_dma[2];
-	u32 dma_ch;
+	struct resource *mem, *memregion;
 	void __iomem *regs;
 	int ret;
 
@@ -370,20 +368,6 @@ static int tegra20_i2s_platform_probe(struct platform_device *pdev)
 		goto err_clk_put;
 	}
 
-	dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
-	if (!dmareq) {
-		if (of_property_read_u32_array(pdev->dev.of_node,
-					"nvidia,dma-request-selector",
-					of_dma, 2) < 0) {
-			dev_err(&pdev->dev, "No DMA resource\n");
-			ret = -ENODEV;
-			goto err_clk_put;
-		}
-		dma_ch = of_dma[1];
-	} else {
-		dma_ch = dmareq->start;
-	}
-
 	memregion = devm_request_mem_region(&pdev->dev, mem->start,
 					    resource_size(mem), DRV_NAME);
 	if (!memregion) {
@@ -410,12 +394,10 @@ static int tegra20_i2s_platform_probe(struct platform_device *pdev)
 	i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2;
 	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 	i2s->capture_dma_data.maxburst = 4;
-	i2s->capture_dma_data.slave_id = dma_ch;
 
 	i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1;
 	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 	i2s->playback_dma_data.maxburst = 4;
-	i2s->playback_dma_data.slave_id = dma_ch;
 
 	pm_runtime_enable(&pdev->dev);
 	if (!pm_runtime_enabled(&pdev->dev)) {
diff --git a/sound/soc/tegra/tegra30_ahub.c b/sound/soc/tegra/tegra30_ahub.c
index 2f1a566dd9cc..572fab23e75f 100644
--- a/sound/soc/tegra/tegra30_ahub.c
+++ b/sound/soc/tegra/tegra30_ahub.c
@@ -96,8 +96,8 @@ static int tegra30_ahub_runtime_resume(struct device *dev)
 }
 
 int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
-				  dma_addr_t *fiforeg,
-				  unsigned int *reqsel)
+				  char *dmachan, int dmachan_len,
+				  dma_addr_t *fiforeg)
 {
 	int channel;
 	u32 reg, val;
@@ -111,9 +111,9 @@ int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
 	__set_bit(channel, ahub->rx_usage);
 
 	*rxcif = TEGRA30_AHUB_RXCIF_APBIF_RX0 + channel;
+	snprintf(dmachan, dmachan_len, "rx%d", channel);
 	*fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_RXFIFO +
 		   (channel * TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE);
-	*reqsel = ahub->dma_sel + channel;
 
 	pm_runtime_get_sync(ahub->dev);
 
@@ -198,8 +198,8 @@ int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif)
 EXPORT_SYMBOL_GPL(tegra30_ahub_free_rx_fifo);
 
 int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
-				  dma_addr_t *fiforeg,
-				  unsigned int *reqsel)
+				  char *dmachan, int dmachan_len,
+				  dma_addr_t *fiforeg)
 {
 	int channel;
 	u32 reg, val;
@@ -213,9 +213,9 @@ int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
 	__set_bit(channel, ahub->tx_usage);
 
 	*txcif = TEGRA30_AHUB_TXCIF_APBIF_TX0 + channel;
+	snprintf(dmachan, dmachan_len, "tx%d", channel);
 	*fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_TXFIFO +
 		   (channel * TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE);
-	*reqsel = ahub->dma_sel + channel;
 
 	pm_runtime_get_sync(ahub->dev);
 
@@ -511,7 +511,6 @@ static int tegra30_ahub_probe(struct platform_device *pdev)
 	struct reset_control *rst;
 	int i;
 	struct resource *res0, *res1, *region;
-	u32 of_dma[2];
 	void __iomem *regs_apbif, *regs_ahub;
 	int ret = 0;
 
@@ -574,16 +573,6 @@ static int tegra30_ahub_probe(struct platform_device *pdev)
 		goto err_clk_put_d_audio;
 	}
 
-	if (of_property_read_u32_array(pdev->dev.of_node,
-				"nvidia,dma-request-selector",
-				of_dma, 2) < 0) {
-		dev_err(&pdev->dev,
-			"Missing property nvidia,dma-request-selector\n");
-		ret = -ENODEV;
-		goto err_clk_put_d_audio;
-	}
-	ahub->dma_sel = of_dma[1];
-
 	res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res0) {
 		dev_err(&pdev->dev, "No apbif memory resource\n");
diff --git a/sound/soc/tegra/tegra30_ahub.h b/sound/soc/tegra/tegra30_ahub.h
index 1383f8cd3572..fd7ba75ed814 100644
--- a/sound/soc/tegra/tegra30_ahub.h
+++ b/sound/soc/tegra/tegra30_ahub.h
@@ -465,15 +465,15 @@ enum tegra30_ahub_rxcif {
 };
 
 extern int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
-					 dma_addr_t *fiforeg,
-					 unsigned int *reqsel);
+					 char *dmachan, int dmachan_len,
+					 dma_addr_t *fiforeg);
 extern int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif);
 extern int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif);
 extern int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif);
 
 extern int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
-					 dma_addr_t *fiforeg,
-					 unsigned int *reqsel);
+					 char *dmachan, int dmachan_len,
+					 dma_addr_t *fiforeg);
 extern int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif);
 extern int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif);
 extern int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif);
@@ -524,7 +524,6 @@ struct tegra30_ahub {
 	struct device *dev;
 	struct clk *clk_d_audio;
 	struct clk *clk_apbif;
-	int dma_sel;
 	resource_size_t apbif_addr;
 	struct regmap *regmap_apbif;
 	struct regmap *regmap_ahub;
diff --git a/sound/soc/tegra/tegra30_i2s.c b/sound/soc/tegra/tegra30_i2s.c
index 531a1ff2101d..362e8f728ddf 100644
--- a/sound/soc/tegra/tegra30_i2s.c
+++ b/sound/soc/tegra/tegra30_i2s.c
@@ -459,8 +459,9 @@ static int tegra30_i2s_platform_probe(struct platform_device *pdev)
 	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 	i2s->playback_dma_data.maxburst = 4;
 	ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
-					    &i2s->playback_dma_data.addr,
-					    &i2s->playback_dma_data.slave_id);
+					    i2s->playback_dma_chan,
+					    sizeof(i2s->playback_dma_chan),
+					    &i2s->playback_dma_data.addr);
 	if (ret) {
 		dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret);
 		goto err_suspend;
@@ -475,8 +476,9 @@ static int tegra30_i2s_platform_probe(struct platform_device *pdev)
 	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 	i2s->capture_dma_data.maxburst = 4;
 	ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
-					    &i2s->capture_dma_data.addr,
-					    &i2s->capture_dma_data.slave_id);
+					    i2s->capture_dma_chan,
+					    sizeof(i2s->capture_dma_chan),
+					    &i2s->capture_dma_data.addr);
 	if (ret) {
 		dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret);
 		goto err_unroute_tx_fifo;
@@ -496,7 +498,9 @@ static int tegra30_i2s_platform_probe(struct platform_device *pdev)
 		goto err_unroute_rx_fifo;
 	}
 
-	ret = tegra_pcm_platform_register(&pdev->dev);
+	ret = tegra_pcm_platform_register_with_chan_names(&pdev->dev,
+				&i2s->dma_config, i2s->playback_dma_chan,
+				i2s->capture_dma_chan);
 	if (ret) {
 		dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
 		goto err_unregister_component;
diff --git a/sound/soc/tegra/tegra30_i2s.h b/sound/soc/tegra/tegra30_i2s.h
index 4d0b0a30dbfb..774fc6ad2026 100644
--- a/sound/soc/tegra/tegra30_i2s.h
+++ b/sound/soc/tegra/tegra30_i2s.h
@@ -238,11 +238,14 @@ struct tegra30_i2s {
 	struct clk *clk_i2s;
 	enum tegra30_ahub_txcif capture_i2s_cif;
 	enum tegra30_ahub_rxcif capture_fifo_cif;
+	char capture_dma_chan[8];
 	struct snd_dmaengine_dai_dma_data capture_dma_data;
 	enum tegra30_ahub_rxcif playback_i2s_cif;
 	enum tegra30_ahub_txcif playback_fifo_cif;
+	char playback_dma_chan[8];
 	struct snd_dmaengine_dai_dma_data playback_dma_data;
 	struct regmap *regmap;
+	struct snd_dmaengine_pcm_config dma_config;
 };
 
 #endif
diff --git a/sound/soc/tegra/tegra_pcm.c b/sound/soc/tegra/tegra_pcm.c
index 7b2d23ba69b3..7ce5c334a660 100644
--- a/sound/soc/tegra/tegra_pcm.c
+++ b/sound/soc/tegra/tegra_pcm.c
@@ -61,12 +61,23 @@ static const struct snd_dmaengine_pcm_config tegra_dmaengine_pcm_config = {
 
 int tegra_pcm_platform_register(struct device *dev)
 {
-	return snd_dmaengine_pcm_register(dev, &tegra_dmaengine_pcm_config,
-			SND_DMAENGINE_PCM_FLAG_NO_DT |
-			SND_DMAENGINE_PCM_FLAG_COMPAT);
+	return snd_dmaengine_pcm_register(dev, &tegra_dmaengine_pcm_config, 0);
 }
 EXPORT_SYMBOL_GPL(tegra_pcm_platform_register);
 
+int tegra_pcm_platform_register_with_chan_names(struct device *dev,
+				struct snd_dmaengine_pcm_config *config,
+				char *txdmachan, char *rxdmachan)
+{
+	*config = tegra_dmaengine_pcm_config;
+	config->dma_dev = dev->parent;
+	config->chan_names[0] = txdmachan;
+	config->chan_names[1] = rxdmachan;
+
+	return snd_dmaengine_pcm_register(dev, config, 0);
+}
+EXPORT_SYMBOL_GPL(tegra_pcm_platform_register_with_chan_names);
+
 void tegra_pcm_platform_unregister(struct device *dev)
 {
 	return snd_dmaengine_pcm_unregister(dev);
diff --git a/sound/soc/tegra/tegra_pcm.h b/sound/soc/tegra/tegra_pcm.h
index 68ad901714a9..7883dec748a3 100644
--- a/sound/soc/tegra/tegra_pcm.h
+++ b/sound/soc/tegra/tegra_pcm.h
@@ -31,7 +31,12 @@
 #ifndef __TEGRA_PCM_H__
 #define __TEGRA_PCM_H__
 
+struct snd_dmaengine_pcm_config;
+
 int tegra_pcm_platform_register(struct device *dev);
+int tegra_pcm_platform_register_with_chan_names(struct device *dev,
+				struct snd_dmaengine_pcm_config *config,
+				char *txdmachan, char *rxdmachan);
 void tegra_pcm_platform_unregister(struct device *dev);
 
 #endif
-- 
1.8.1.5

Re: [PATCH 19/31] ASoC: tegra: convert to standard DMA DT bindings

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 359 bytes --]

On Fri, Nov 15, 2013 at 01:54:14PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> By passing no flags when calling snd_dmaengine_pcm_register() from
> tegra_pcm.c, we end up using dma_request_slave_channel() rather than

Acked-by: Mark Brown <broonie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

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[PATCH 19/31] ASoC: tegra: convert to standard DMA DT bindings

[Mark Brown]

On Fri, Nov 15, 2013 at 01:54:14PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> By passing no flags when calling snd_dmaengine_pcm_register() from
> tegra_pcm.c, we end up using dma_request_slave_channel() rather than

Acked-by: Mark Brown <broonie@linaro.org>
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[PATCH 20/31] i2c: tegra: use reset framework

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org>
Cc: linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/i2c/busses/i2c-tegra.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index e661edee4d0c..9704537aee3c 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -27,7 +27,7 @@
 #include <linux/slab.h>
 #include <linux/of_device.h>
 #include <linux/module.h>
-#include <linux/clk/tegra.h>
+#include <linux/reset.h>
 
 #include <asm/unaligned.h>
 
@@ -160,6 +160,7 @@ struct tegra_i2c_dev {
 	struct i2c_adapter adapter;
 	struct clk *div_clk;
 	struct clk *fast_clk;
+	struct reset_control *rst;
 	void __iomem *base;
 	int cont_id;
 	int irq;
@@ -415,9 +416,9 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 		return err;
 	}
 
-	tegra_periph_reset_assert(i2c_dev->div_clk);
+	reset_control_assert(i2c_dev->rst);
 	udelay(2);
-	tegra_periph_reset_deassert(i2c_dev->div_clk);
+	reset_control_deassert(i2c_dev->rst);
 
 	if (i2c_dev->is_dvc)
 		tegra_dvc_init(i2c_dev);
@@ -743,6 +744,12 @@ static int tegra_i2c_probe(struct platform_device *pdev)
 	i2c_dev->cont_id = pdev->id;
 	i2c_dev->dev = &pdev->dev;
 
+	i2c_dev->rst = devm_reset_control_get(&pdev->dev, "i2c");
+	if (IS_ERR(i2c_dev->rst)) {
+		dev_err(&pdev->dev, "missing controller reset");
+		return PTR_ERR(i2c_dev->rst);
+	}
+
 	ret = of_property_read_u32(i2c_dev->dev->of_node, "clock-frequency",
 					&i2c_dev->bus_clk_rate);
 	if (ret)
-- 
1.8.1.5

[PATCH 20/31] i2c: tegra: use reset framework

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: linux-i2c at vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/i2c/busses/i2c-tegra.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index e661edee4d0c..9704537aee3c 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -27,7 +27,7 @@
 #include <linux/slab.h>
 #include <linux/of_device.h>
 #include <linux/module.h>
-#include <linux/clk/tegra.h>
+#include <linux/reset.h>
 
 #include <asm/unaligned.h>
 
@@ -160,6 +160,7 @@ struct tegra_i2c_dev {
 	struct i2c_adapter adapter;
 	struct clk *div_clk;
 	struct clk *fast_clk;
+	struct reset_control *rst;
 	void __iomem *base;
 	int cont_id;
 	int irq;
@@ -415,9 +416,9 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 		return err;
 	}
 
-	tegra_periph_reset_assert(i2c_dev->div_clk);
+	reset_control_assert(i2c_dev->rst);
 	udelay(2);
-	tegra_periph_reset_deassert(i2c_dev->div_clk);
+	reset_control_deassert(i2c_dev->rst);
 
 	if (i2c_dev->is_dvc)
 		tegra_dvc_init(i2c_dev);
@@ -743,6 +744,12 @@ static int tegra_i2c_probe(struct platform_device *pdev)
 	i2c_dev->cont_id = pdev->id;
 	i2c_dev->dev = &pdev->dev;
 
+	i2c_dev->rst = devm_reset_control_get(&pdev->dev, "i2c");
+	if (IS_ERR(i2c_dev->rst)) {
+		dev_err(&pdev->dev, "missing controller reset");
+		return PTR_ERR(i2c_dev->rst);
+	}
+
 	ret = of_property_read_u32(i2c_dev->dev->of_node, "clock-frequency",
 					&i2c_dev->bus_clk_rate);
 	if (ret)
-- 
1.8.1.5

Re: [PATCH 20/31] i2c: tegra: use reset framework

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 861 bytes --]

On Fri, Nov 15, 2013 at 01:54:15PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org>
> Cc: linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Acked-by: Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org>


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[PATCH 20/31] i2c: tegra: use reset framework

[Wolfram Sang]

On Fri, Nov 15, 2013 at 01:54:15PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Wolfram Sang <wsa@the-dreams.de>
> Cc: linux-i2c at vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>

Acked-by: Wolfram Sang <wsa@the-dreams.de>

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Re: [PATCH 20/31] i2c: tegra: use reset framework

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1290 bytes --]

On Fri, Nov 15, 2013 at 01:54:15PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org>
> Cc: linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/i2c/busses/i2c-tegra.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)

Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

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[PATCH 20/31] i2c: tegra: use reset framework

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:54:15PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Wolfram Sang <wsa@the-dreams.de>
> Cc: linux-i2c at vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/i2c/busses/i2c-tegra.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)

Reviewed-by: Thierry Reding <treding@nvidia.com>
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[PATCH 21/31] staging: nvec: use reset framework

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Julian Andres Klode <jak-4HMq4SXA452hPH1hqNUYSQ@public.gmane.org>
Cc: Marc Dietrich <marvin24-Mmb7MZpHnFY@public.gmane.org>
Cc: ac100-oU9gvf+ajcQ97yFScArB1dHuzzzSOjJt@public.gmane.org
Cc: Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
Cc: devel-gWbeCf7V1WCQmaza687I9mD2FQJk+8+b@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/staging/nvec/nvec.c | 11 ++++++++---
 drivers/staging/nvec/nvec.h |  5 ++++-
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/staging/nvec/nvec.c b/drivers/staging/nvec/nvec.c
index 3066ee2e753b..9de4cd13d9ab 100644
--- a/drivers/staging/nvec/nvec.c
+++ b/drivers/staging/nvec/nvec.c
@@ -36,7 +36,6 @@
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <linux/workqueue.h>
-#include <linux/clk/tegra.h>
 
 #include "nvec.h"
 
@@ -733,9 +732,9 @@ static void tegra_init_i2c_slave(struct nvec_chip *nvec)
 
 	clk_prepare_enable(nvec->i2c_clk);
 
-	tegra_periph_reset_assert(nvec->i2c_clk);
+	reset_control_assert(nvec->rst);
 	udelay(2);
-	tegra_periph_reset_deassert(nvec->i2c_clk);
+	reset_control_deassert(nvec->rst);
 
 	val = I2C_CNFG_NEW_MASTER_SFM | I2C_CNFG_PACKET_MODE_EN |
 	    (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
@@ -836,6 +835,12 @@ static int tegra_nvec_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
+	nvec->rst = devm_reset_control_get(&pdev->dev, "i2c");
+	if (IS_ERR(nvec->rst)) {
+		dev_err(nvec->dev, "failed to get controller reset\n");
+		return PTR_ERR(nvec->rst);
+	}
+
 	nvec->base = base;
 	nvec->irq = res->start;
 	nvec->i2c_clk = i2c_clk;
diff --git a/drivers/staging/nvec/nvec.h b/drivers/staging/nvec/nvec.h
index e880518935fb..e271375053fa 100644
--- a/drivers/staging/nvec/nvec.h
+++ b/drivers/staging/nvec/nvec.h
@@ -23,6 +23,7 @@
 #include <linux/list.h>
 #include <linux/mutex.h>
 #include <linux/notifier.h>
+#include <linux/reset.h>
 #include <linux/spinlock.h>
 #include <linux/workqueue.h>
 
@@ -109,7 +110,8 @@ struct nvec_msg {
  * @irq: The IRQ of the I2C device
  * @i2c_addr: The address of the I2C slave
  * @base: The base of the memory mapped region of the I2C device
- * @clk: The clock of the I2C device
+ * @i2c_clk: The clock of the I2C device
+ * @rst: The reset of the I2C device
  * @notifier_list: Notifiers to be called on received messages, see
  *                 nvec_register_notifier()
  * @rx_data: Received messages that have to be processed
@@ -139,6 +141,7 @@ struct nvec_chip {
 	int i2c_addr;
 	void __iomem *base;
 	struct clk *i2c_clk;
+	struct reset_control *rst;
 	struct atomic_notifier_head notifier_list;
 	struct list_head rx_data, tx_data;
 	struct notifier_block nvec_status_notifier;
-- 
1.8.1.5

[PATCH 21/31] staging: nvec: use reset framework

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Julian Andres Klode <jak@jak-linux.org>
Cc: Marc Dietrich <marvin24@gmx.de>
Cc: ac100 at lists.launchpad.net
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: devel at driverdev.osuosl.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/staging/nvec/nvec.c | 11 ++++++++---
 drivers/staging/nvec/nvec.h |  5 ++++-
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/staging/nvec/nvec.c b/drivers/staging/nvec/nvec.c
index 3066ee2e753b..9de4cd13d9ab 100644
--- a/drivers/staging/nvec/nvec.c
+++ b/drivers/staging/nvec/nvec.c
@@ -36,7 +36,6 @@
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <linux/workqueue.h>
-#include <linux/clk/tegra.h>
 
 #include "nvec.h"
 
@@ -733,9 +732,9 @@ static void tegra_init_i2c_slave(struct nvec_chip *nvec)
 
 	clk_prepare_enable(nvec->i2c_clk);
 
-	tegra_periph_reset_assert(nvec->i2c_clk);
+	reset_control_assert(nvec->rst);
 	udelay(2);
-	tegra_periph_reset_deassert(nvec->i2c_clk);
+	reset_control_deassert(nvec->rst);
 
 	val = I2C_CNFG_NEW_MASTER_SFM | I2C_CNFG_PACKET_MODE_EN |
 	    (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
@@ -836,6 +835,12 @@ static int tegra_nvec_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
+	nvec->rst = devm_reset_control_get(&pdev->dev, "i2c");
+	if (IS_ERR(nvec->rst)) {
+		dev_err(nvec->dev, "failed to get controller reset\n");
+		return PTR_ERR(nvec->rst);
+	}
+
 	nvec->base = base;
 	nvec->irq = res->start;
 	nvec->i2c_clk = i2c_clk;
diff --git a/drivers/staging/nvec/nvec.h b/drivers/staging/nvec/nvec.h
index e880518935fb..e271375053fa 100644
--- a/drivers/staging/nvec/nvec.h
+++ b/drivers/staging/nvec/nvec.h
@@ -23,6 +23,7 @@
 #include <linux/list.h>
 #include <linux/mutex.h>
 #include <linux/notifier.h>
+#include <linux/reset.h>
 #include <linux/spinlock.h>
 #include <linux/workqueue.h>
 
@@ -109,7 +110,8 @@ struct nvec_msg {
  * @irq: The IRQ of the I2C device
  * @i2c_addr: The address of the I2C slave
  * @base: The base of the memory mapped region of the I2C device
- * @clk: The clock of the I2C device
+ * @i2c_clk: The clock of the I2C device
+ * @rst: The reset of the I2C device
  * @notifier_list: Notifiers to be called on received messages, see
  *                 nvec_register_notifier()
  * @rx_data: Received messages that have to be processed
@@ -139,6 +141,7 @@ struct nvec_chip {
 	int i2c_addr;
 	void __iomem *base;
 	struct clk *i2c_clk;
+	struct reset_control *rst;
 	struct atomic_notifier_head notifier_list;
 	struct list_head rx_data, tx_data;
 	struct notifier_block nvec_status_notifier;
-- 
1.8.1.5

Re: [PATCH 21/31] staging: nvec: use reset framework

[Marc Dietrich]

On Friday 15 November 2013 13:54:16 Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Julian Andres Klode <jak-4HMq4SXA452hPH1hqNUYSQ@public.gmane.org>
> Cc: Marc Dietrich <marvin24-Mmb7MZpHnFY@public.gmane.org>
> Cc: ac100-oU9gvf+ajcQ97yFScArB1dHuzzzSOjJt@public.gmane.org
> Cc: Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
> Cc: devel-gWbeCf7V1WCQmaza687I9mD2FQJk+8+b@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Acked-by: Marc Dietrich <marvin24-Mmb7MZpHnFY@public.gmane.org>

> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/staging/nvec/nvec.c | 11 ++++++++---
>  drivers/staging/nvec/nvec.h |  5 ++++-
>  2 files changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/staging/nvec/nvec.c b/drivers/staging/nvec/nvec.c
> index 3066ee2e753b..9de4cd13d9ab 100644
> --- a/drivers/staging/nvec/nvec.c
> +++ b/drivers/staging/nvec/nvec.c
> @@ -36,7 +36,6 @@
>  #include <linux/slab.h>
>  #include <linux/spinlock.h>
>  #include <linux/workqueue.h>
> -#include <linux/clk/tegra.h>
> 
>  #include "nvec.h"
> 
> @@ -733,9 +732,9 @@ static void tegra_init_i2c_slave(struct nvec_chip *nvec)
> 
>  	clk_prepare_enable(nvec->i2c_clk);
> 
> -	tegra_periph_reset_assert(nvec->i2c_clk);
> +	reset_control_assert(nvec->rst);
>  	udelay(2);
> -	tegra_periph_reset_deassert(nvec->i2c_clk);
> +	reset_control_deassert(nvec->rst);
> 
>  	val = I2C_CNFG_NEW_MASTER_SFM | I2C_CNFG_PACKET_MODE_EN |
>  	    (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
> @@ -836,6 +835,12 @@ static int tegra_nvec_probe(struct platform_device
> *pdev) return -ENODEV;
>  	}
> 
> +	nvec->rst = devm_reset_control_get(&pdev->dev, "i2c");
> +	if (IS_ERR(nvec->rst)) {
> +		dev_err(nvec->dev, "failed to get controller reset\n");
> +		return PTR_ERR(nvec->rst);
> +	}
> +
>  	nvec->base = base;
>  	nvec->irq = res->start;
>  	nvec->i2c_clk = i2c_clk;
> diff --git a/drivers/staging/nvec/nvec.h b/drivers/staging/nvec/nvec.h
> index e880518935fb..e271375053fa 100644
> --- a/drivers/staging/nvec/nvec.h
> +++ b/drivers/staging/nvec/nvec.h
> @@ -23,6 +23,7 @@
>  #include <linux/list.h>
>  #include <linux/mutex.h>
>  #include <linux/notifier.h>
> +#include <linux/reset.h>
>  #include <linux/spinlock.h>
>  #include <linux/workqueue.h>
> 
> @@ -109,7 +110,8 @@ struct nvec_msg {
>   * @irq: The IRQ of the I2C device
>   * @i2c_addr: The address of the I2C slave
>   * @base: The base of the memory mapped region of the I2C device
> - * @clk: The clock of the I2C device
> + * @i2c_clk: The clock of the I2C device
> + * @rst: The reset of the I2C device
>   * @notifier_list: Notifiers to be called on received messages, see
>   *                 nvec_register_notifier()
>   * @rx_data: Received messages that have to be processed
> @@ -139,6 +141,7 @@ struct nvec_chip {
>  	int i2c_addr;
>  	void __iomem *base;
>  	struct clk *i2c_clk;
> +	struct reset_control *rst;
>  	struct atomic_notifier_head notifier_list;
>  	struct list_head rx_data, tx_data;
>  	struct notifier_block nvec_status_notifier;

[PATCH 21/31] staging: nvec: use reset framework

[Marc Dietrich]

On Friday 15 November 2013 13:54:16 Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Julian Andres Klode <jak@jak-linux.org>
> Cc: Marc Dietrich <marvin24@gmx.de>
> Cc: ac100 at lists.launchpad.net
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: devel at driverdev.osuosl.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>

Acked-by: Marc Dietrich <marvin24@gmx.de>

> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/staging/nvec/nvec.c | 11 ++++++++---
>  drivers/staging/nvec/nvec.h |  5 ++++-
>  2 files changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/staging/nvec/nvec.c b/drivers/staging/nvec/nvec.c
> index 3066ee2e753b..9de4cd13d9ab 100644
> --- a/drivers/staging/nvec/nvec.c
> +++ b/drivers/staging/nvec/nvec.c
> @@ -36,7 +36,6 @@
>  #include <linux/slab.h>
>  #include <linux/spinlock.h>
>  #include <linux/workqueue.h>
> -#include <linux/clk/tegra.h>
> 
>  #include "nvec.h"
> 
> @@ -733,9 +732,9 @@ static void tegra_init_i2c_slave(struct nvec_chip *nvec)
> 
>  	clk_prepare_enable(nvec->i2c_clk);
> 
> -	tegra_periph_reset_assert(nvec->i2c_clk);
> +	reset_control_assert(nvec->rst);
>  	udelay(2);
> -	tegra_periph_reset_deassert(nvec->i2c_clk);
> +	reset_control_deassert(nvec->rst);
> 
>  	val = I2C_CNFG_NEW_MASTER_SFM | I2C_CNFG_PACKET_MODE_EN |
>  	    (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
> @@ -836,6 +835,12 @@ static int tegra_nvec_probe(struct platform_device
> *pdev) return -ENODEV;
>  	}
> 
> +	nvec->rst = devm_reset_control_get(&pdev->dev, "i2c");
> +	if (IS_ERR(nvec->rst)) {
> +		dev_err(nvec->dev, "failed to get controller reset\n");
> +		return PTR_ERR(nvec->rst);
> +	}
> +
>  	nvec->base = base;
>  	nvec->irq = res->start;
>  	nvec->i2c_clk = i2c_clk;
> diff --git a/drivers/staging/nvec/nvec.h b/drivers/staging/nvec/nvec.h
> index e880518935fb..e271375053fa 100644
> --- a/drivers/staging/nvec/nvec.h
> +++ b/drivers/staging/nvec/nvec.h
> @@ -23,6 +23,7 @@
>  #include <linux/list.h>
>  #include <linux/mutex.h>
>  #include <linux/notifier.h>
> +#include <linux/reset.h>
>  #include <linux/spinlock.h>
>  #include <linux/workqueue.h>
> 
> @@ -109,7 +110,8 @@ struct nvec_msg {
>   * @irq: The IRQ of the I2C device
>   * @i2c_addr: The address of the I2C slave
>   * @base: The base of the memory mapped region of the I2C device
> - * @clk: The clock of the I2C device
> + * @i2c_clk: The clock of the I2C device
> + * @rst: The reset of the I2C device
>   * @notifier_list: Notifiers to be called on received messages, see
>   *                 nvec_register_notifier()
>   * @rx_data: Received messages that have to be processed
> @@ -139,6 +141,7 @@ struct nvec_chip {
>  	int i2c_addr;
>  	void __iomem *base;
>  	struct clk *i2c_clk;
> +	struct reset_control *rst;
>  	struct atomic_notifier_head notifier_list;
>  	struct list_head rx_data, tx_data;
>  	struct notifier_block nvec_status_notifier;

Re: [PATCH 21/31] staging: nvec: use reset framework

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1551 bytes --]

On Fri, Nov 15, 2013 at 01:54:16PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Julian Andres Klode <jak-4HMq4SXA452hPH1hqNUYSQ@public.gmane.org>
> Cc: Marc Dietrich <marvin24-Mmb7MZpHnFY@public.gmane.org>
> Cc: ac100-oU9gvf+ajcQ97yFScArB1dHuzzzSOjJt@public.gmane.org
> Cc: Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
> Cc: devel-gWbeCf7V1WCQmaza687I9mD2FQJk+8+b@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/staging/nvec/nvec.c | 11 ++++++++---
>  drivers/staging/nvec/nvec.h |  5 ++++-
>  2 files changed, 12 insertions(+), 4 deletions(-)

Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]

[PATCH 21/31] staging: nvec: use reset framework

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:54:16PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Julian Andres Klode <jak@jak-linux.org>
> Cc: Marc Dietrich <marvin24@gmx.de>
> Cc: ac100 at lists.launchpad.net
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: devel at driverdev.osuosl.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/staging/nvec/nvec.c | 11 ++++++++---
>  drivers/staging/nvec/nvec.h |  5 ++++-
>  2 files changed, 12 insertions(+), 4 deletions(-)

Reviewed-by: Thierry Reding <treding@nvidia.com>
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Re: [PATCH 21/31] staging: nvec: use reset framework

[Greg Kroah-Hartman]

On Fri, Nov 15, 2013 at 01:54:16PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding@nvidia.com
> Cc: pdeschrijver@nvidia.com
> Cc: linux-tegra@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: Julian Andres Klode <jak@jak-linux.org>
> Cc: Marc Dietrich <marvin24@gmx.de>
> Cc: ac100@lists.launchpad.net
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: devel@driverdev.osuosl.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.

Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

[PATCH 21/31] staging: nvec: use reset framework

[Greg Kroah-Hartman]

On Fri, Nov 15, 2013 at 01:54:16PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Julian Andres Klode <jak@jak-linux.org>
> Cc: Marc Dietrich <marvin24@gmx.de>
> Cc: ac100 at lists.launchpad.net
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: devel at driverdev.osuosl.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.

Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

[PATCH 22/31] spi: tegra: use reset framework

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/spi/Kconfig              |  3 +++
 drivers/spi/spi-tegra114.c       | 18 +++++++++++++-----
 drivers/spi/spi-tegra20-sflash.c | 18 +++++++++++++-----
 drivers/spi/spi-tegra20-slink.c  | 18 +++++++++++++-----
 4 files changed, 42 insertions(+), 15 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index eb1f1ef5fa2e..9fc66e83c1a7 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -448,6 +448,7 @@ config SPI_MXS
 config SPI_TEGRA114
 	tristate "NVIDIA Tegra114 SPI Controller"
 	depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
+	depends on RESET_CONTROLLER
 	help
 	  SPI driver for NVIDIA Tegra114 SPI Controller interface. This controller
 	  is different than the older SoCs SPI controller and also register interface
@@ -456,6 +457,7 @@ config SPI_TEGRA114
 config SPI_TEGRA20_SFLASH
 	tristate "Nvidia Tegra20 Serial flash Controller"
 	depends on ARCH_TEGRA || COMPILE_TEST
+	depends on RESET_CONTROLLER
 	help
 	  SPI driver for Nvidia Tegra20 Serial flash Controller interface.
 	  The main usecase of this controller is to use spi flash as boot
@@ -464,6 +466,7 @@ config SPI_TEGRA20_SFLASH
 config SPI_TEGRA20_SLINK
 	tristate "Nvidia Tegra20/Tegra30 SLINK Controller"
 	depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
+	depends on RESET_CONTROLLER
 	help
 	  SPI driver for Nvidia Tegra20/Tegra30 SLINK Controller interface.
 
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index aaecfb3ebf58..f62e6e5e90e3 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -17,7 +17,6 @@
  */
 
 #include <linux/clk.h>
-#include <linux/clk/tegra.h>
 #include <linux/completion.h>
 #include <linux/delay.h>
 #include <linux/dmaengine.h>
@@ -34,6 +33,7 @@
 #include <linux/pm_runtime.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
+#include <linux/reset.h>
 #include <linux/spi/spi.h>
 
 #define SPI_COMMAND1				0x000
@@ -174,6 +174,7 @@ struct tegra_spi_data {
 	spinlock_t				lock;
 
 	struct clk				*clk;
+	struct reset_control			*rst;
 	void __iomem				*base;
 	phys_addr_t				phys;
 	unsigned				irq;
@@ -918,9 +919,9 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
 			tspi->status_reg);
 		dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
 			tspi->command1_reg, tspi->dma_control_reg);
-		tegra_periph_reset_assert(tspi->clk);
+		reset_control_assert(tspi->rst);
 		udelay(2);
-		tegra_periph_reset_deassert(tspi->clk);
+		reset_control_deassert(tspi->rst);
 		complete(&tspi->xfer_completion);
 		goto exit;
 	}
@@ -990,9 +991,9 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
 			tspi->status_reg);
 		dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
 			tspi->command1_reg, tspi->dma_control_reg);
-		tegra_periph_reset_assert(tspi->clk);
+		reset_control_assert(tspi->rst);
 		udelay(2);
-		tegra_periph_reset_deassert(tspi->clk);
+		reset_control_deassert(tspi->rst);
 		complete(&tspi->xfer_completion);
 		spin_unlock_irqrestore(&tspi->lock, flags);
 		return IRQ_HANDLED;
@@ -1127,6 +1128,13 @@ static int tegra_spi_probe(struct platform_device *pdev)
 		goto exit_free_irq;
 	}
 
+	tspi->rst = devm_reset_control_get(&pdev->dev, "spi");
+	if (IS_ERR(tspi->rst)) {
+		dev_err(&pdev->dev, "can not get reset\n");
+		ret = PTR_ERR(tspi->rst);
+		goto exit_free_irq;
+	}
+
 	tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
 	tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
 
diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c
index 4dc8e8129459..e6f382b33818 100644
--- a/drivers/spi/spi-tegra20-sflash.c
+++ b/drivers/spi/spi-tegra20-sflash.c
@@ -32,8 +32,8 @@
 #include <linux/pm_runtime.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
+#include <linux/reset.h>
 #include <linux/spi/spi.h>
-#include <linux/clk/tegra.h>
 
 #define SPI_COMMAND				0x000
 #define SPI_GO					BIT(30)
@@ -118,6 +118,7 @@ struct tegra_sflash_data {
 	spinlock_t				lock;
 
 	struct clk				*clk;
+	struct reset_control			*rst;
 	void __iomem				*base;
 	unsigned				irq;
 	u32					spi_max_frequency;
@@ -389,9 +390,9 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_sflash_data *tsd)
 		dev_err(tsd->dev,
 			"CpuXfer 0x%08x:0x%08x\n", tsd->command_reg,
 				tsd->dma_control_reg);
-		tegra_periph_reset_assert(tsd->clk);
+		reset_control_assert(tsd->rst);
 		udelay(2);
-		tegra_periph_reset_deassert(tsd->clk);
+		reset_control_deassert(tsd->rst);
 		complete(&tsd->xfer_completion);
 		goto exit;
 	}
@@ -505,6 +506,13 @@ static int tegra_sflash_probe(struct platform_device *pdev)
 		goto exit_free_irq;
 	}
 
+	tsd->rst = devm_reset_control_get(&pdev->dev, "spi");
+	if (IS_ERR(tsd->rst)) {
+		dev_err(&pdev->dev, "can not get reset\n");
+		ret = PTR_ERR(tsd->rst);
+		goto exit_free_irq;
+	}
+
 	init_completion(&tsd->xfer_completion);
 	pm_runtime_enable(&pdev->dev);
 	if (!pm_runtime_enabled(&pdev->dev)) {
@@ -520,9 +528,9 @@ static int tegra_sflash_probe(struct platform_device *pdev)
 	}
 
 	/* Reset controller */
-	tegra_periph_reset_assert(tsd->clk);
+	reset_control_assert(tsd->rst);
 	udelay(2);
-	tegra_periph_reset_deassert(tsd->clk);
+	reset_control_deassert(tsd->rst);
 
 	tsd->def_command_reg  = SPI_M_S | SPI_CS_SW;
 	tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
index e66715ba37ed..1305b8f933ba 100644
--- a/drivers/spi/spi-tegra20-slink.c
+++ b/drivers/spi/spi-tegra20-slink.c
@@ -33,8 +33,8 @@
 #include <linux/pm_runtime.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
+#include <linux/reset.h>
 #include <linux/spi/spi.h>
-#include <linux/clk/tegra.h>
 
 #define SLINK_COMMAND			0x000
 #define SLINK_BIT_LENGTH(x)		(((x) & 0x1f) << 0)
@@ -167,6 +167,7 @@ struct tegra_slink_data {
 	spinlock_t				lock;
 
 	struct clk				*clk;
+	struct reset_control			*rst;
 	void __iomem				*base;
 	phys_addr_t				phys;
 	unsigned				irq;
@@ -884,9 +885,9 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi)
 		dev_err(tspi->dev,
 			"CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
 				tspi->command2_reg, tspi->dma_control_reg);
-		tegra_periph_reset_assert(tspi->clk);
+		reset_control_assert(tspi->rst);
 		udelay(2);
-		tegra_periph_reset_deassert(tspi->clk);
+		reset_control_deassert(tspi->rst);
 		complete(&tspi->xfer_completion);
 		goto exit;
 	}
@@ -957,9 +958,9 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi)
 		dev_err(tspi->dev,
 			"DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
 				tspi->command2_reg, tspi->dma_control_reg);
-		tegra_periph_reset_assert(tspi->clk);
+		reset_control_assert(tspi->rst);
 		udelay(2);
-		tegra_periph_reset_deassert(tspi->clk);
+		reset_control_assert(tspi->rst);
 		complete(&tspi->xfer_completion);
 		spin_unlock_irqrestore(&tspi->lock, flags);
 		return IRQ_HANDLED;
@@ -1118,6 +1119,13 @@ static int tegra_slink_probe(struct platform_device *pdev)
 		goto exit_free_irq;
 	}
 
+	tspi->rst = devm_reset_control_get(&pdev->dev, "spi");
+	if (IS_ERR(tspi->rst)) {
+		dev_err(&pdev->dev, "can not get reset\n");
+		ret = PTR_ERR(tspi->rst);
+		goto exit_free_irq;
+	}
+
 	tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
 	tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
 
-- 
1.8.1.5

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[PATCH 22/31] spi: tegra: use reset framework

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-spi at vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/spi/Kconfig              |  3 +++
 drivers/spi/spi-tegra114.c       | 18 +++++++++++++-----
 drivers/spi/spi-tegra20-sflash.c | 18 +++++++++++++-----
 drivers/spi/spi-tegra20-slink.c  | 18 +++++++++++++-----
 4 files changed, 42 insertions(+), 15 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index eb1f1ef5fa2e..9fc66e83c1a7 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -448,6 +448,7 @@ config SPI_MXS
 config SPI_TEGRA114
 	tristate "NVIDIA Tegra114 SPI Controller"
 	depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
+	depends on RESET_CONTROLLER
 	help
 	  SPI driver for NVIDIA Tegra114 SPI Controller interface. This controller
 	  is different than the older SoCs SPI controller and also register interface
@@ -456,6 +457,7 @@ config SPI_TEGRA114
 config SPI_TEGRA20_SFLASH
 	tristate "Nvidia Tegra20 Serial flash Controller"
 	depends on ARCH_TEGRA || COMPILE_TEST
+	depends on RESET_CONTROLLER
 	help
 	  SPI driver for Nvidia Tegra20 Serial flash Controller interface.
 	  The main usecase of this controller is to use spi flash as boot
@@ -464,6 +466,7 @@ config SPI_TEGRA20_SFLASH
 config SPI_TEGRA20_SLINK
 	tristate "Nvidia Tegra20/Tegra30 SLINK Controller"
 	depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
+	depends on RESET_CONTROLLER
 	help
 	  SPI driver for Nvidia Tegra20/Tegra30 SLINK Controller interface.
 
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index aaecfb3ebf58..f62e6e5e90e3 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -17,7 +17,6 @@
  */
 
 #include <linux/clk.h>
-#include <linux/clk/tegra.h>
 #include <linux/completion.h>
 #include <linux/delay.h>
 #include <linux/dmaengine.h>
@@ -34,6 +33,7 @@
 #include <linux/pm_runtime.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
+#include <linux/reset.h>
 #include <linux/spi/spi.h>
 
 #define SPI_COMMAND1				0x000
@@ -174,6 +174,7 @@ struct tegra_spi_data {
 	spinlock_t				lock;
 
 	struct clk				*clk;
+	struct reset_control			*rst;
 	void __iomem				*base;
 	phys_addr_t				phys;
 	unsigned				irq;
@@ -918,9 +919,9 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
 			tspi->status_reg);
 		dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
 			tspi->command1_reg, tspi->dma_control_reg);
-		tegra_periph_reset_assert(tspi->clk);
+		reset_control_assert(tspi->rst);
 		udelay(2);
-		tegra_periph_reset_deassert(tspi->clk);
+		reset_control_deassert(tspi->rst);
 		complete(&tspi->xfer_completion);
 		goto exit;
 	}
@@ -990,9 +991,9 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
 			tspi->status_reg);
 		dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
 			tspi->command1_reg, tspi->dma_control_reg);
-		tegra_periph_reset_assert(tspi->clk);
+		reset_control_assert(tspi->rst);
 		udelay(2);
-		tegra_periph_reset_deassert(tspi->clk);
+		reset_control_deassert(tspi->rst);
 		complete(&tspi->xfer_completion);
 		spin_unlock_irqrestore(&tspi->lock, flags);
 		return IRQ_HANDLED;
@@ -1127,6 +1128,13 @@ static int tegra_spi_probe(struct platform_device *pdev)
 		goto exit_free_irq;
 	}
 
+	tspi->rst = devm_reset_control_get(&pdev->dev, "spi");
+	if (IS_ERR(tspi->rst)) {
+		dev_err(&pdev->dev, "can not get reset\n");
+		ret = PTR_ERR(tspi->rst);
+		goto exit_free_irq;
+	}
+
 	tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
 	tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
 
diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c
index 4dc8e8129459..e6f382b33818 100644
--- a/drivers/spi/spi-tegra20-sflash.c
+++ b/drivers/spi/spi-tegra20-sflash.c
@@ -32,8 +32,8 @@
 #include <linux/pm_runtime.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
+#include <linux/reset.h>
 #include <linux/spi/spi.h>
-#include <linux/clk/tegra.h>
 
 #define SPI_COMMAND				0x000
 #define SPI_GO					BIT(30)
@@ -118,6 +118,7 @@ struct tegra_sflash_data {
 	spinlock_t				lock;
 
 	struct clk				*clk;
+	struct reset_control			*rst;
 	void __iomem				*base;
 	unsigned				irq;
 	u32					spi_max_frequency;
@@ -389,9 +390,9 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_sflash_data *tsd)
 		dev_err(tsd->dev,
 			"CpuXfer 0x%08x:0x%08x\n", tsd->command_reg,
 				tsd->dma_control_reg);
-		tegra_periph_reset_assert(tsd->clk);
+		reset_control_assert(tsd->rst);
 		udelay(2);
-		tegra_periph_reset_deassert(tsd->clk);
+		reset_control_deassert(tsd->rst);
 		complete(&tsd->xfer_completion);
 		goto exit;
 	}
@@ -505,6 +506,13 @@ static int tegra_sflash_probe(struct platform_device *pdev)
 		goto exit_free_irq;
 	}
 
+	tsd->rst = devm_reset_control_get(&pdev->dev, "spi");
+	if (IS_ERR(tsd->rst)) {
+		dev_err(&pdev->dev, "can not get reset\n");
+		ret = PTR_ERR(tsd->rst);
+		goto exit_free_irq;
+	}
+
 	init_completion(&tsd->xfer_completion);
 	pm_runtime_enable(&pdev->dev);
 	if (!pm_runtime_enabled(&pdev->dev)) {
@@ -520,9 +528,9 @@ static int tegra_sflash_probe(struct platform_device *pdev)
 	}
 
 	/* Reset controller */
-	tegra_periph_reset_assert(tsd->clk);
+	reset_control_assert(tsd->rst);
 	udelay(2);
-	tegra_periph_reset_deassert(tsd->clk);
+	reset_control_deassert(tsd->rst);
 
 	tsd->def_command_reg  = SPI_M_S | SPI_CS_SW;
 	tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
index e66715ba37ed..1305b8f933ba 100644
--- a/drivers/spi/spi-tegra20-slink.c
+++ b/drivers/spi/spi-tegra20-slink.c
@@ -33,8 +33,8 @@
 #include <linux/pm_runtime.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
+#include <linux/reset.h>
 #include <linux/spi/spi.h>
-#include <linux/clk/tegra.h>
 
 #define SLINK_COMMAND			0x000
 #define SLINK_BIT_LENGTH(x)		(((x) & 0x1f) << 0)
@@ -167,6 +167,7 @@ struct tegra_slink_data {
 	spinlock_t				lock;
 
 	struct clk				*clk;
+	struct reset_control			*rst;
 	void __iomem				*base;
 	phys_addr_t				phys;
 	unsigned				irq;
@@ -884,9 +885,9 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi)
 		dev_err(tspi->dev,
 			"CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
 				tspi->command2_reg, tspi->dma_control_reg);
-		tegra_periph_reset_assert(tspi->clk);
+		reset_control_assert(tspi->rst);
 		udelay(2);
-		tegra_periph_reset_deassert(tspi->clk);
+		reset_control_deassert(tspi->rst);
 		complete(&tspi->xfer_completion);
 		goto exit;
 	}
@@ -957,9 +958,9 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi)
 		dev_err(tspi->dev,
 			"DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
 				tspi->command2_reg, tspi->dma_control_reg);
-		tegra_periph_reset_assert(tspi->clk);
+		reset_control_assert(tspi->rst);
 		udelay(2);
-		tegra_periph_reset_deassert(tspi->clk);
+		reset_control_assert(tspi->rst);
 		complete(&tspi->xfer_completion);
 		spin_unlock_irqrestore(&tspi->lock, flags);
 		return IRQ_HANDLED;
@@ -1118,6 +1119,13 @@ static int tegra_slink_probe(struct platform_device *pdev)
 		goto exit_free_irq;
 	}
 
+	tspi->rst = devm_reset_control_get(&pdev->dev, "spi");
+	if (IS_ERR(tspi->rst)) {
+		dev_err(&pdev->dev, "can not get reset\n");
+		ret = PTR_ERR(tspi->rst);
+		goto exit_free_irq;
+	}
+
 	tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
 	tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
 
-- 
1.8.1.5

Re: [PATCH 22/31] spi: tegra: use reset framework

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 345 bytes --]

On Fri, Nov 15, 2013 at 01:54:17PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.

Acked-by: Mark Brown <broonie@linaro.org>

[-- Attachment #1.2: Digital signature --]
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_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 22/31] spi: tegra: use reset framework

[Mark Brown]

On Fri, Nov 15, 2013 at 01:54:17PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.

Acked-by: Mark Brown <broonie@linaro.org>
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Re: [PATCH 22/31] spi: tegra: use reset framework

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1469 bytes --]

On Fri, Nov 15, 2013 at 01:54:17PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/spi/Kconfig              |  3 +++
>  drivers/spi/spi-tegra114.c       | 18 +++++++++++++-----
>  drivers/spi/spi-tegra20-sflash.c | 18 +++++++++++++-----
>  drivers/spi/spi-tegra20-slink.c  | 18 +++++++++++++-----
>  4 files changed, 42 insertions(+), 15 deletions(-)

Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

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[PATCH 22/31] spi: tegra: use reset framework

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:54:17PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Mark Brown <broonie@kernel.org>
> Cc: linux-spi at vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/spi/Kconfig              |  3 +++
>  drivers/spi/spi-tegra114.c       | 18 +++++++++++++-----
>  drivers/spi/spi-tegra20-sflash.c | 18 +++++++++++++-----
>  drivers/spi/spi-tegra20-slink.c  | 18 +++++++++++++-----
>  4 files changed, 42 insertions(+), 15 deletions(-)

Reviewed-by: Thierry Reding <treding@nvidia.com>
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[PATCH 23/31] spi: tegra: convert to standard DMA DT bindings

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

By using dma_request_slave_channel_or_err(), the DMA slave ID can be
looked up from standard DT properties, and squirrelled away during
channel allocation. Hence, there's no need to use a custom DT property
to store the slave ID.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/spi/spi-tegra114.c      | 48 +++++++++++++++--------------------------
 drivers/spi/spi-tegra20-slink.c | 48 +++++++++++++++--------------------------
 2 files changed, 34 insertions(+), 62 deletions(-)

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index f62e6e5e90e3..42b553b72f04 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -178,7 +178,6 @@ struct tegra_spi_data {
 	void __iomem				*base;
 	phys_addr_t				phys;
 	unsigned				irq;
-	int					dma_req_sel;
 	u32					spi_max_frequency;
 	u32					cur_speed;
 
@@ -601,15 +600,15 @@ static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
 	dma_addr_t dma_phys;
 	int ret;
 	struct dma_slave_config dma_sconfig;
-	dma_cap_mask_t mask;
 
-	dma_cap_zero(mask);
-	dma_cap_set(DMA_SLAVE, mask);
-	dma_chan = dma_request_channel(mask, NULL, NULL);
-	if (!dma_chan) {
-		dev_err(tspi->dev,
-			"Dma channel is not available, will try later\n");
-		return -EPROBE_DEFER;
+	dma_chan = dma_request_slave_channel_or_err(tspi->dev,
+					dma_to_memory ? "rx" : "tx");
+	if (IS_ERR(dma_chan)) {
+		ret = PTR_ERR(dma_chan);
+		if (ret != -EPROBE_DEFER)
+			dev_err(tspi->dev,
+				"Dma channel is not available: %d\n", ret);
+		return ret;
 	}
 
 	dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
@@ -620,7 +619,6 @@ static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
 		return -ENOMEM;
 	}
 
-	dma_sconfig.slave_id = tspi->dma_req_sel;
 	if (dma_to_memory) {
 		dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
 		dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
@@ -1055,11 +1053,6 @@ static void tegra_spi_parse_dt(struct platform_device *pdev,
 	struct tegra_spi_data *tspi)
 {
 	struct device_node *np = pdev->dev.of_node;
-	u32 of_dma[2];
-
-	if (of_property_read_u32_array(np, "nvidia,dma-request-selector",
-				of_dma, 2) >= 0)
-		tspi->dma_req_sel = of_dma[1];
 
 	if (of_property_read_u32(np, "spi-max-frequency",
 				&tspi->spi_max_frequency))
@@ -1138,22 +1131,15 @@ static int tegra_spi_probe(struct platform_device *pdev)
 	tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
 	tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
 
-	if (tspi->dma_req_sel) {
-		ret = tegra_spi_init_dma_param(tspi, true);
-		if (ret < 0) {
-			dev_err(&pdev->dev, "RxDma Init failed, err %d\n", ret);
-			goto exit_free_irq;
-		}
-
-		ret = tegra_spi_init_dma_param(tspi, false);
-		if (ret < 0) {
-			dev_err(&pdev->dev, "TxDma Init failed, err %d\n", ret);
-			goto exit_rx_dma_free;
-		}
-		tspi->max_buf_size = tspi->dma_buf_size;
-		init_completion(&tspi->tx_dma_complete);
-		init_completion(&tspi->rx_dma_complete);
-	}
+	ret = tegra_spi_init_dma_param(tspi, true);
+	if (ret < 0)
+		goto exit_free_irq;
+	ret = tegra_spi_init_dma_param(tspi, false);
+	if (ret < 0)
+		goto exit_rx_dma_free;
+	tspi->max_buf_size = tspi->dma_buf_size;
+	init_completion(&tspi->tx_dma_complete);
+	init_completion(&tspi->rx_dma_complete);
 
 	init_completion(&tspi->xfer_completion);
 
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
index 1305b8f933ba..dd6f26c05947 100644
--- a/drivers/spi/spi-tegra20-slink.c
+++ b/drivers/spi/spi-tegra20-slink.c
@@ -171,7 +171,6 @@ struct tegra_slink_data {
 	void __iomem				*base;
 	phys_addr_t				phys;
 	unsigned				irq;
-	int					dma_req_sel;
 	u32					spi_max_frequency;
 	u32					cur_speed;
 
@@ -630,15 +629,15 @@ static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi,
 	dma_addr_t dma_phys;
 	int ret;
 	struct dma_slave_config dma_sconfig;
-	dma_cap_mask_t mask;
 
-	dma_cap_zero(mask);
-	dma_cap_set(DMA_SLAVE, mask);
-	dma_chan = dma_request_channel(mask, NULL, NULL);
-	if (!dma_chan) {
-		dev_err(tspi->dev,
-			"Dma channel is not available, will try later\n");
-		return -EPROBE_DEFER;
+	dma_chan = dma_request_slave_channel(tspi->dev,
+					     dma_to_memory ? "rx" : "tx");
+	if (IS_ERR(dma_chan)) {
+		ret = PTR_ERR(dma_chan);
+		if (ret != -EPROBE_DEFER)
+			dev_err(tspi->dev,
+				"Dma channel is not available: %d\n", ret);
+		return ret;
 	}
 
 	dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
@@ -649,7 +648,6 @@ static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi,
 		return -ENOMEM;
 	}
 
-	dma_sconfig.slave_id = tspi->dma_req_sel;
 	if (dma_to_memory) {
 		dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
 		dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
@@ -1021,11 +1019,6 @@ static irqreturn_t tegra_slink_isr(int irq, void *context_data)
 static void tegra_slink_parse_dt(struct tegra_slink_data *tspi)
 {
 	struct device_node *np = tspi->dev->of_node;
-	u32 of_dma[2];
-
-	if (of_property_read_u32_array(np, "nvidia,dma-request-selector",
-				of_dma, 2) >= 0)
-		tspi->dma_req_sel = of_dma[1];
 
 	if (of_property_read_u32(np, "spi-max-frequency",
 					&tspi->spi_max_frequency))
@@ -1129,22 +1122,15 @@ static int tegra_slink_probe(struct platform_device *pdev)
 	tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
 	tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
 
-	if (tspi->dma_req_sel) {
-		ret = tegra_slink_init_dma_param(tspi, true);
-		if (ret < 0) {
-			dev_err(&pdev->dev, "RxDma Init failed, err %d\n", ret);
-			goto exit_free_irq;
-		}
-
-		ret = tegra_slink_init_dma_param(tspi, false);
-		if (ret < 0) {
-			dev_err(&pdev->dev, "TxDma Init failed, err %d\n", ret);
-			goto exit_rx_dma_free;
-		}
-		tspi->max_buf_size = tspi->dma_buf_size;
-		init_completion(&tspi->tx_dma_complete);
-		init_completion(&tspi->rx_dma_complete);
-	}
+	ret = tegra_slink_init_dma_param(tspi, true);
+	if (ret < 0)
+		goto exit_free_irq;
+	ret = tegra_slink_init_dma_param(tspi, false);
+	if (ret < 0)
+		goto exit_rx_dma_free;
+	tspi->max_buf_size = tspi->dma_buf_size;
+	init_completion(&tspi->tx_dma_complete);
+	init_completion(&tspi->rx_dma_complete);
 
 	init_completion(&tspi->xfer_completion);
 
-- 
1.8.1.5

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[PATCH 23/31] spi: tegra: convert to standard DMA DT bindings

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

By using dma_request_slave_channel_or_err(), the DMA slave ID can be
looked up from standard DT properties, and squirrelled away during
channel allocation. Hence, there's no need to use a custom DT property
to store the slave ID.

Cc: treding at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-spi at vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/spi/spi-tegra114.c      | 48 +++++++++++++++--------------------------
 drivers/spi/spi-tegra20-slink.c | 48 +++++++++++++++--------------------------
 2 files changed, 34 insertions(+), 62 deletions(-)

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index f62e6e5e90e3..42b553b72f04 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -178,7 +178,6 @@ struct tegra_spi_data {
 	void __iomem				*base;
 	phys_addr_t				phys;
 	unsigned				irq;
-	int					dma_req_sel;
 	u32					spi_max_frequency;
 	u32					cur_speed;
 
@@ -601,15 +600,15 @@ static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
 	dma_addr_t dma_phys;
 	int ret;
 	struct dma_slave_config dma_sconfig;
-	dma_cap_mask_t mask;
 
-	dma_cap_zero(mask);
-	dma_cap_set(DMA_SLAVE, mask);
-	dma_chan = dma_request_channel(mask, NULL, NULL);
-	if (!dma_chan) {
-		dev_err(tspi->dev,
-			"Dma channel is not available, will try later\n");
-		return -EPROBE_DEFER;
+	dma_chan = dma_request_slave_channel_or_err(tspi->dev,
+					dma_to_memory ? "rx" : "tx");
+	if (IS_ERR(dma_chan)) {
+		ret = PTR_ERR(dma_chan);
+		if (ret != -EPROBE_DEFER)
+			dev_err(tspi->dev,
+				"Dma channel is not available: %d\n", ret);
+		return ret;
 	}
 
 	dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
@@ -620,7 +619,6 @@ static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
 		return -ENOMEM;
 	}
 
-	dma_sconfig.slave_id = tspi->dma_req_sel;
 	if (dma_to_memory) {
 		dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
 		dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
@@ -1055,11 +1053,6 @@ static void tegra_spi_parse_dt(struct platform_device *pdev,
 	struct tegra_spi_data *tspi)
 {
 	struct device_node *np = pdev->dev.of_node;
-	u32 of_dma[2];
-
-	if (of_property_read_u32_array(np, "nvidia,dma-request-selector",
-				of_dma, 2) >= 0)
-		tspi->dma_req_sel = of_dma[1];
 
 	if (of_property_read_u32(np, "spi-max-frequency",
 				&tspi->spi_max_frequency))
@@ -1138,22 +1131,15 @@ static int tegra_spi_probe(struct platform_device *pdev)
 	tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
 	tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
 
-	if (tspi->dma_req_sel) {
-		ret = tegra_spi_init_dma_param(tspi, true);
-		if (ret < 0) {
-			dev_err(&pdev->dev, "RxDma Init failed, err %d\n", ret);
-			goto exit_free_irq;
-		}
-
-		ret = tegra_spi_init_dma_param(tspi, false);
-		if (ret < 0) {
-			dev_err(&pdev->dev, "TxDma Init failed, err %d\n", ret);
-			goto exit_rx_dma_free;
-		}
-		tspi->max_buf_size = tspi->dma_buf_size;
-		init_completion(&tspi->tx_dma_complete);
-		init_completion(&tspi->rx_dma_complete);
-	}
+	ret = tegra_spi_init_dma_param(tspi, true);
+	if (ret < 0)
+		goto exit_free_irq;
+	ret = tegra_spi_init_dma_param(tspi, false);
+	if (ret < 0)
+		goto exit_rx_dma_free;
+	tspi->max_buf_size = tspi->dma_buf_size;
+	init_completion(&tspi->tx_dma_complete);
+	init_completion(&tspi->rx_dma_complete);
 
 	init_completion(&tspi->xfer_completion);
 
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
index 1305b8f933ba..dd6f26c05947 100644
--- a/drivers/spi/spi-tegra20-slink.c
+++ b/drivers/spi/spi-tegra20-slink.c
@@ -171,7 +171,6 @@ struct tegra_slink_data {
 	void __iomem				*base;
 	phys_addr_t				phys;
 	unsigned				irq;
-	int					dma_req_sel;
 	u32					spi_max_frequency;
 	u32					cur_speed;
 
@@ -630,15 +629,15 @@ static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi,
 	dma_addr_t dma_phys;
 	int ret;
 	struct dma_slave_config dma_sconfig;
-	dma_cap_mask_t mask;
 
-	dma_cap_zero(mask);
-	dma_cap_set(DMA_SLAVE, mask);
-	dma_chan = dma_request_channel(mask, NULL, NULL);
-	if (!dma_chan) {
-		dev_err(tspi->dev,
-			"Dma channel is not available, will try later\n");
-		return -EPROBE_DEFER;
+	dma_chan = dma_request_slave_channel(tspi->dev,
+					     dma_to_memory ? "rx" : "tx");
+	if (IS_ERR(dma_chan)) {
+		ret = PTR_ERR(dma_chan);
+		if (ret != -EPROBE_DEFER)
+			dev_err(tspi->dev,
+				"Dma channel is not available: %d\n", ret);
+		return ret;
 	}
 
 	dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
@@ -649,7 +648,6 @@ static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi,
 		return -ENOMEM;
 	}
 
-	dma_sconfig.slave_id = tspi->dma_req_sel;
 	if (dma_to_memory) {
 		dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
 		dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
@@ -1021,11 +1019,6 @@ static irqreturn_t tegra_slink_isr(int irq, void *context_data)
 static void tegra_slink_parse_dt(struct tegra_slink_data *tspi)
 {
 	struct device_node *np = tspi->dev->of_node;
-	u32 of_dma[2];
-
-	if (of_property_read_u32_array(np, "nvidia,dma-request-selector",
-				of_dma, 2) >= 0)
-		tspi->dma_req_sel = of_dma[1];
 
 	if (of_property_read_u32(np, "spi-max-frequency",
 					&tspi->spi_max_frequency))
@@ -1129,22 +1122,15 @@ static int tegra_slink_probe(struct platform_device *pdev)
 	tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
 	tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
 
-	if (tspi->dma_req_sel) {
-		ret = tegra_slink_init_dma_param(tspi, true);
-		if (ret < 0) {
-			dev_err(&pdev->dev, "RxDma Init failed, err %d\n", ret);
-			goto exit_free_irq;
-		}
-
-		ret = tegra_slink_init_dma_param(tspi, false);
-		if (ret < 0) {
-			dev_err(&pdev->dev, "TxDma Init failed, err %d\n", ret);
-			goto exit_rx_dma_free;
-		}
-		tspi->max_buf_size = tspi->dma_buf_size;
-		init_completion(&tspi->tx_dma_complete);
-		init_completion(&tspi->rx_dma_complete);
-	}
+	ret = tegra_slink_init_dma_param(tspi, true);
+	if (ret < 0)
+		goto exit_free_irq;
+	ret = tegra_slink_init_dma_param(tspi, false);
+	if (ret < 0)
+		goto exit_rx_dma_free;
+	tspi->max_buf_size = tspi->dma_buf_size;
+	init_completion(&tspi->tx_dma_complete);
+	init_completion(&tspi->rx_dma_complete);
 
 	init_completion(&tspi->xfer_completion);
 
-- 
1.8.1.5

Re: [PATCH 23/31] spi: tegra: convert to standard DMA DT bindings

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 706 bytes --]

On Fri, Nov 15, 2013 at 01:54:18PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> By using dma_request_slave_channel_or_err(), the DMA slave ID can be

Acked-by: Mark Brown <broonie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

Is this function introduced earlier in the series?  One of the things
I'm looking at is trying to factor out some DMA code in the SPI
framework so perhaps using this straight off would be good.  But perhaps
the channel request stuff will all be in the drivers and it'll just pass
a handle to the framework code so there'll be no issue.

Acked-by: Mark Brown <broonie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

[-- Attachment #2: Digital signature --]
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[PATCH 23/31] spi: tegra: convert to standard DMA DT bindings

[Mark Brown]

On Fri, Nov 15, 2013 at 01:54:18PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> By using dma_request_slave_channel_or_err(), the DMA slave ID can be

Acked-by: Mark Brown <broonie@linaro.org>

Is this function introduced earlier in the series?  One of the things
I'm looking at is trying to factor out some DMA code in the SPI
framework so perhaps using this straight off would be good.  But perhaps
the channel request stuff will all be in the drivers and it'll just pass
a handle to the framework code so there'll be no issue.

Acked-by: Mark Brown <broonie@linaro.org>
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Re: [PATCH 23/31] spi: tegra: convert to standard DMA DT bindings

[Stephen Warren]

On 11/16/2013 03:14 AM, Mark Brown wrote:
> On Fri, Nov 15, 2013 at 01:54:18PM -0700, Stephen Warren wrote:
>> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
>> By using dma_request_slave_channel_or_err(), the DMA slave ID can be
> 
> Acked-by: Mark Brown <broonie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> 
> Is this function introduced earlier in the series?

Yes, patch 11/31 introduced this.

> One of the things
> I'm looking at is trying to factor out some DMA code in the SPI
> framework so perhaps using this straight off would be good.  But perhaps
> the channel request stuff will all be in the drivers and it'll just pass
> a handle to the framework code so there'll be no issue.

I think I can make a "core changes" branch that contains:

[PATCH 11/31] dma: add channel request API that supports deferred probe

[PATCH 14/31] ASoC: dmaengine: support deferred probe for DMA channels

[PATCH 15/31] ASoC: dmaengine: add custom DMA config to
snd_dmaengine_pcm_config

That could be merged into relevant subsystems alone, if they only depend
on the core changes and not any of the Tegra driver changes.

However, I suspect that the Tegra driver changes may need to be merged
into any subsystem that's doing much other work on the Tegra drivers,
especially any significant refactoring, so the subsystem would probably
have to pick up the whole series anyway. Still, I'll make sure I
re-order the branch to put the core changes first so we have as much
flexibility as possible.
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[PATCH 23/31] spi: tegra: convert to standard DMA DT bindings

[Stephen Warren]

On 11/16/2013 03:14 AM, Mark Brown wrote:
> On Fri, Nov 15, 2013 at 01:54:18PM -0700, Stephen Warren wrote:
>> From: Stephen Warren <swarren@nvidia.com>
>>
>> By using dma_request_slave_channel_or_err(), the DMA slave ID can be
> 
> Acked-by: Mark Brown <broonie@linaro.org>
> 
> Is this function introduced earlier in the series?

Yes, patch 11/31 introduced this.

> One of the things
> I'm looking at is trying to factor out some DMA code in the SPI
> framework so perhaps using this straight off would be good.  But perhaps
> the channel request stuff will all be in the drivers and it'll just pass
> a handle to the framework code so there'll be no issue.

I think I can make a "core changes" branch that contains:

[PATCH 11/31] dma: add channel request API that supports deferred probe

[PATCH 14/31] ASoC: dmaengine: support deferred probe for DMA channels

[PATCH 15/31] ASoC: dmaengine: add custom DMA config to
snd_dmaengine_pcm_config

That could be merged into relevant subsystems alone, if they only depend
on the core changes and not any of the Tegra driver changes.

However, I suspect that the Tegra driver changes may need to be merged
into any subsystem that's doing much other work on the Tegra drivers,
especially any significant refactoring, so the subsystem would probably
have to pick up the whole series anyway. Still, I'll make sure I
re-order the branch to put the core changes first so we have as much
flexibility as possible.

Re: [PATCH 23/31] spi: tegra: convert to standard DMA DT bindings

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 680 bytes --]

On Mon, Nov 18, 2013 at 10:30:35AM -0700, Stephen Warren wrote:

> However, I suspect that the Tegra driver changes may need to be merged
> into any subsystem that's doing much other work on the Tegra drivers,
> especially any significant refactoring, so the subsystem would probably
> have to pick up the whole series anyway. Still, I'll make sure I
> re-order the branch to put the core changes first so we have as much
> flexibility as possible.

At least in the ASoC case my main consideration is other drivers wanting
to use the core changes rather than changes being made to the Tegra
drivers.  Let's try to just share the core code and merge the rest over
later if needed?

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[PATCH 23/31] spi: tegra: convert to standard DMA DT bindings

[Mark Brown]

On Mon, Nov 18, 2013 at 10:30:35AM -0700, Stephen Warren wrote:

> However, I suspect that the Tegra driver changes may need to be merged
> into any subsystem that's doing much other work on the Tegra drivers,
> especially any significant refactoring, so the subsystem would probably
> have to pick up the whole series anyway. Still, I'll make sure I
> re-order the branch to put the core changes first so we have as much
> flexibility as possible.

At least in the ASoC case my main consideration is other drivers wanting
to use the core changes rather than changes being made to the Tegra
drivers.  Let's try to just share the core code and merge the rest over
later if needed?
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[PATCH 27/31] USB: EHCI: tegra: use reset framework

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
Cc: Alan Stern <stern-nwvwT67g6+6dFdvTe/nMLpVzexx5G7lz@public.gmane.org>
Cc: linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/usb/host/ehci-tegra.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index b9fd0396011e..6f7e23dd1417 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -17,7 +17,6 @@
  */
 
 #include <linux/clk.h>
-#include <linux/clk/tegra.h>
 #include <linux/dma-mapping.h>
 #include <linux/err.h>
 #include <linux/gpio.h>
@@ -29,6 +28,7 @@
 #include <linux/of_gpio.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/reset.h>
 #include <linux/slab.h>
 #include <linux/usb/ehci_def.h>
 #include <linux/usb/tegra_usb_phy.h>
@@ -62,6 +62,7 @@ static int (*orig_hub_control)(struct usb_hcd *hcd,
 struct tegra_ehci_hcd {
 	struct tegra_usb_phy *phy;
 	struct clk *clk;
+	struct reset_control *rst;
 	int port_resuming;
 	bool needs_double_reset;
 	enum tegra_usb_phy_port_speed port_speed;
@@ -385,13 +386,20 @@ static int tegra_ehci_probe(struct platform_device *pdev)
 		goto cleanup_hcd_create;
 	}
 
+	tegra->rst = devm_reset_control_get(&pdev->dev, "usb");
+	if (IS_ERR(tegra->rst)) {
+		dev_err(&pdev->dev, "Can't get ehci reset\n");
+		err = PTR_ERR(tegra->rst);
+		goto cleanup_hcd_create;
+	}
+
 	err = clk_prepare_enable(tegra->clk);
 	if (err)
 		goto cleanup_hcd_create;
 
-	tegra_periph_reset_assert(tegra->clk);
+	reset_control_assert(tegra->rst);
 	udelay(1);
-	tegra_periph_reset_deassert(tegra->clk);
+	reset_control_deassert(tegra->rst);
 
 	u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
 	if (IS_ERR(u_phy)) {
-- 
1.8.1.5

[PATCH 27/31] USB: EHCI: tegra: use reset framework

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: linux-usb at vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/usb/host/ehci-tegra.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index b9fd0396011e..6f7e23dd1417 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -17,7 +17,6 @@
  */
 
 #include <linux/clk.h>
-#include <linux/clk/tegra.h>
 #include <linux/dma-mapping.h>
 #include <linux/err.h>
 #include <linux/gpio.h>
@@ -29,6 +28,7 @@
 #include <linux/of_gpio.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/reset.h>
 #include <linux/slab.h>
 #include <linux/usb/ehci_def.h>
 #include <linux/usb/tegra_usb_phy.h>
@@ -62,6 +62,7 @@ static int (*orig_hub_control)(struct usb_hcd *hcd,
 struct tegra_ehci_hcd {
 	struct tegra_usb_phy *phy;
 	struct clk *clk;
+	struct reset_control *rst;
 	int port_resuming;
 	bool needs_double_reset;
 	enum tegra_usb_phy_port_speed port_speed;
@@ -385,13 +386,20 @@ static int tegra_ehci_probe(struct platform_device *pdev)
 		goto cleanup_hcd_create;
 	}
 
+	tegra->rst = devm_reset_control_get(&pdev->dev, "usb");
+	if (IS_ERR(tegra->rst)) {
+		dev_err(&pdev->dev, "Can't get ehci reset\n");
+		err = PTR_ERR(tegra->rst);
+		goto cleanup_hcd_create;
+	}
+
 	err = clk_prepare_enable(tegra->clk);
 	if (err)
 		goto cleanup_hcd_create;
 
-	tegra_periph_reset_assert(tegra->clk);
+	reset_control_assert(tegra->rst);
 	udelay(1);
-	tegra_periph_reset_deassert(tegra->clk);
+	reset_control_deassert(tegra->rst);
 
 	u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
 	if (IS_ERR(u_phy)) {
-- 
1.8.1.5

Re: [PATCH 27/31] USB: EHCI: tegra: use reset framework

[Alan Stern]

On Fri, 15 Nov 2013, Stephen Warren wrote:

> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
> Cc: Alan Stern <stern-nwvwT67g6+6dFdvTe/nMLpVzexx5G7lz@public.gmane.org>
> Cc: linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.

Acked-by: Alan Stern <stern-nwvwT67g6+6dFdvTe/nMLpVzexx5G7lz@public.gmane.org>

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[PATCH 27/31] USB: EHCI: tegra: use reset framework

[Alan Stern]

On Fri, 15 Nov 2013, Stephen Warren wrote:

> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: Alan Stern <stern@rowland.harvard.edu>
> Cc: linux-usb at vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.

Acked-by: Alan Stern <stern@rowland.harvard.edu>

Re: [PATCH 27/31] USB: EHCI: tegra: use reset framework

[Greg Kroah-Hartman]

On Fri, Nov 15, 2013 at 01:54:22PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
> Cc: Alan Stern <stern-nwvwT67g6+6dFdvTe/nMLpVzexx5G7lz@public.gmane.org>
> Cc: linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Acked-by: Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>

[PATCH 27/31] USB: EHCI: tegra: use reset framework

[Greg Kroah-Hartman]

On Fri, Nov 15, 2013 at 01:54:22PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: Alan Stern <stern@rowland.harvard.edu>
> Cc: linux-usb at vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>

Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Re: [PATCH 27/31] USB: EHCI: tegra: use reset framework

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1385 bytes --]

On Fri, Nov 15, 2013 at 01:54:22PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
> Cc: Alan Stern <stern-nwvwT67g6+6dFdvTe/nMLpVzexx5G7lz@public.gmane.org>
> Cc: linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/usb/host/ehci-tegra.c | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)

Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]

[PATCH 27/31] USB: EHCI: tegra: use reset framework

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:54:22PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: Alan Stern <stern@rowland.harvard.edu>
> Cc: linux-usb at vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/usb/host/ehci-tegra.c | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)

Reviewed-by: Thierry Reding <treding@nvidia.com>
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[PATCH 28/31] ARM: tegra: remove legacy clock entries from DT

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Now that all Tegra drivers have been converted to use the common reset
framework, we can remove all the legacy DT clocks/clock-names entries for
"clocks" that were only used with the old custom Tegra module reset API.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/tegra20.dtsi |  3 +--
 arch/arm/boot/dts/tegra30.dtsi | 18 +++---------------
 2 files changed, 4 insertions(+), 17 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index c53e02e08310..61d2f3868f4f 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -576,9 +576,8 @@
 
 		clocks = <&tegra_car TEGRA20_CLK_PEX>,
 			 <&tegra_car TEGRA20_CLK_AFI>,
-			 <&tegra_car TEGRA20_CLK_PCIE_XCLK>,
 			 <&tegra_car TEGRA20_CLK_PLL_E>;
-		clock-names = "pex", "afi", "pcie_xclk", "pll_e";
+		clock-names = "pex", "afi", "pll_e";
 		resets = <&tegra_car 70>,
 		         <&tegra_car 72>,
 		         <&tegra_car 74>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 0e69dd9f33e6..348b0f07f675 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -40,10 +40,9 @@
 
 		clocks = <&tegra_car TEGRA30_CLK_PCIE>,
 			 <&tegra_car TEGRA30_CLK_AFI>,
-			 <&tegra_car TEGRA30_CLK_PCIEX>,
 			 <&tegra_car TEGRA30_CLK_PLL_E>,
 			 <&tegra_car TEGRA30_CLK_CML0>;
-		clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
+		clock-names = "pex", "afi", "pll_e", "cml";
 		resets = <&tegra_car 70>,
 		         <&tegra_car 72>,
 		         <&tegra_car 74>;
@@ -641,19 +640,8 @@
 		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 1>;
 		clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
-			 <&tegra_car TEGRA30_CLK_APBIF>,
-			 <&tegra_car TEGRA30_CLK_I2S0>,
-			 <&tegra_car TEGRA30_CLK_I2S1>,
-			 <&tegra_car TEGRA30_CLK_I2S2>,
-			 <&tegra_car TEGRA30_CLK_I2S3>,
-			 <&tegra_car TEGRA30_CLK_I2S4>,
-			 <&tegra_car TEGRA30_CLK_DAM0>,
-			 <&tegra_car TEGRA30_CLK_DAM1>,
-			 <&tegra_car TEGRA30_CLK_DAM2>,
-			 <&tegra_car TEGRA30_CLK_SPDIF_IN>;
-		clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
-			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
-			      "spdif_in";
+			 <&tegra_car TEGRA30_CLK_APBIF>;
+		clock-names = "d_audio", "apbif";
 		resets = <&tegra_car 106>, /* d_audio */
 			 <&tegra_car 107>, /* apbif */
 			 <&tegra_car 30>,  /* i2s0 */
-- 
1.8.1.5

[PATCH 28/31] ARM: tegra: remove legacy clock entries from DT

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Now that all Tegra drivers have been converted to use the common reset
framework, we can remove all the legacy DT clocks/clock-names entries for
"clocks" that were only used with the old custom Tegra module reset API.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: devicetree at vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 arch/arm/boot/dts/tegra20.dtsi |  3 +--
 arch/arm/boot/dts/tegra30.dtsi | 18 +++---------------
 2 files changed, 4 insertions(+), 17 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index c53e02e08310..61d2f3868f4f 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -576,9 +576,8 @@
 
 		clocks = <&tegra_car TEGRA20_CLK_PEX>,
 			 <&tegra_car TEGRA20_CLK_AFI>,
-			 <&tegra_car TEGRA20_CLK_PCIE_XCLK>,
 			 <&tegra_car TEGRA20_CLK_PLL_E>;
-		clock-names = "pex", "afi", "pcie_xclk", "pll_e";
+		clock-names = "pex", "afi", "pll_e";
 		resets = <&tegra_car 70>,
 		         <&tegra_car 72>,
 		         <&tegra_car 74>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 0e69dd9f33e6..348b0f07f675 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -40,10 +40,9 @@
 
 		clocks = <&tegra_car TEGRA30_CLK_PCIE>,
 			 <&tegra_car TEGRA30_CLK_AFI>,
-			 <&tegra_car TEGRA30_CLK_PCIEX>,
 			 <&tegra_car TEGRA30_CLK_PLL_E>,
 			 <&tegra_car TEGRA30_CLK_CML0>;
-		clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
+		clock-names = "pex", "afi", "pll_e", "cml";
 		resets = <&tegra_car 70>,
 		         <&tegra_car 72>,
 		         <&tegra_car 74>;
@@ -641,19 +640,8 @@
 		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 1>;
 		clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
-			 <&tegra_car TEGRA30_CLK_APBIF>,
-			 <&tegra_car TEGRA30_CLK_I2S0>,
-			 <&tegra_car TEGRA30_CLK_I2S1>,
-			 <&tegra_car TEGRA30_CLK_I2S2>,
-			 <&tegra_car TEGRA30_CLK_I2S3>,
-			 <&tegra_car TEGRA30_CLK_I2S4>,
-			 <&tegra_car TEGRA30_CLK_DAM0>,
-			 <&tegra_car TEGRA30_CLK_DAM1>,
-			 <&tegra_car TEGRA30_CLK_DAM2>,
-			 <&tegra_car TEGRA30_CLK_SPDIF_IN>;
-		clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
-			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
-			      "spdif_in";
+			 <&tegra_car TEGRA30_CLK_APBIF>;
+		clock-names = "d_audio", "apbif";
 		resets = <&tegra_car 106>, /* d_audio */
 			 <&tegra_car 107>, /* apbif */
 			 <&tegra_car 30>,  /* i2s0 */
-- 
1.8.1.5

Re: [PATCH 28/31] ARM: tegra: remove legacy clock entries from DT

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1282 bytes --]

On Fri, Nov 15, 2013 at 01:54:23PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Now that all Tegra drivers have been converted to use the common reset
> framework, we can remove all the legacy DT clocks/clock-names entries for
> "clocks" that were only used with the old custom Tegra module reset API.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
> Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>  arch/arm/boot/dts/tegra20.dtsi |  3 +--
>  arch/arm/boot/dts/tegra30.dtsi | 18 +++---------------
>  2 files changed, 4 insertions(+), 17 deletions(-)

Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]

[PATCH 28/31] ARM: tegra: remove legacy clock entries from DT

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:54:23PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Now that all Tegra drivers have been converted to use the common reset
> framework, we can remove all the legacy DT clocks/clock-names entries for
> "clocks" that were only used with the old custom Tegra module reset API.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Pawel Moll <pawel.moll@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
> Cc: devicetree at vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
>  arch/arm/boot/dts/tegra20.dtsi |  3 +--
>  arch/arm/boot/dts/tegra30.dtsi | 18 +++---------------
>  2 files changed, 4 insertions(+), 17 deletions(-)

Reviewed-by: Thierry Reding <treding@nvidia.com>
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[PATCH 29/31] ARM: tegra: remove legacy DMA entries from DT

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Now that all Tegra drivers have been converted to use DMA APIs which
retrieve DMA channel information from standard DMA DT properties, we can
remove all the legacy DT DMA-related properties.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/tegra114.dtsi | 14 --------------
 arch/arm/boot/dts/tegra20.dtsi  | 13 -------------
 arch/arm/boot/dts/tegra30.dtsi  | 12 ------------
 3 files changed, 39 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index b4f2e62909a7..6d4858b2c701 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -128,7 +128,6 @@
 		reg = <0x70006000 0x40>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 8>;
 		clocks = <&tegra_car TEGRA114_CLK_UARTA>;
 		resets = <&tegra_car 6>;
 		reset-names = "serial";
@@ -142,7 +141,6 @@
 		reg = <0x70006040 0x40>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 9>;
 		clocks = <&tegra_car TEGRA114_CLK_UARTB>;
 		resets = <&tegra_car 7>;
 		reset-names = "serial";
@@ -156,7 +154,6 @@
 		reg = <0x70006200 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 10>;
 		clocks = <&tegra_car TEGRA114_CLK_UARTC>;
 		resets = <&tegra_car 55>;
 		reset-names = "serial";
@@ -170,7 +167,6 @@
 		reg = <0x70006300 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 19>;
 		clocks = <&tegra_car TEGRA114_CLK_UARTD>;
 		resets = <&tegra_car 65>;
 		reset-names = "serial";
@@ -268,7 +264,6 @@
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000d400 0x200>;
 		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC1>;
@@ -284,7 +279,6 @@
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000d600 0x200>;
 		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC2>;
@@ -300,7 +294,6 @@
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000d800 0x200>;
 		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC3>;
@@ -316,7 +309,6 @@
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000da00 0x200>;
 		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC4>;
@@ -332,7 +324,6 @@
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000dc00 0x200>;
 		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 27>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC5>;
@@ -348,7 +339,6 @@
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000de00 0x200>;
 		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 28>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC6>;
@@ -401,10 +391,6 @@
 		      <0x70080200 0x100>,
 		      <0x70081000 0x200>;
 		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>,
-			<&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>,
-			<&apbdma 12>, <&apbdma 13>, <&apbdma 14>,
-			<&apbdma 29>;
 		clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
 			 <&tegra_car TEGRA114_CLK_APBIF>,
 			 <&tegra_car TEGRA114_CLK_I2S0>,
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 61d2f3868f4f..f780f7bed7bf 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -248,7 +248,6 @@
 		compatible = "nvidia,tegra20-ac97";
 		reg = <0x70002000 0x200>;
 		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 12>;
 		clocks = <&tegra_car TEGRA20_CLK_AC97>;
 		resets = <&tegra_car 3>;
 		reset-names = "ac97";
@@ -261,7 +260,6 @@
 		compatible = "nvidia,tegra20-i2s";
 		reg = <0x70002800 0x200>;
 		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 2>;
 		clocks = <&tegra_car TEGRA20_CLK_I2S1>;
 		resets = <&tegra_car 11>;
 		reset-names = "i2s";
@@ -274,7 +272,6 @@
 		compatible = "nvidia,tegra20-i2s";
 		reg = <0x70002a00 0x200>;
 		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 1>;
 		clocks = <&tegra_car TEGRA20_CLK_I2S2>;
 		resets = <&tegra_car 18>;
 		reset-names = "i2s";
@@ -295,7 +292,6 @@
 		reg = <0x70006000 0x40>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 8>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTA>;
 		resets = <&tegra_car 6>;
 		reset-names = "serial";
@@ -309,7 +305,6 @@
 		reg = <0x70006040 0x40>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 9>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTB>;
 		resets = <&tegra_car 7>;
 		reset-names = "serial";
@@ -323,7 +318,6 @@
 		reg = <0x70006200 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 10>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTC>;
 		resets = <&tegra_car 55>;
 		reset-names = "serial";
@@ -337,7 +331,6 @@
 		reg = <0x70006300 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 19>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTD>;
 		resets = <&tegra_car 65>;
 		reset-names = "serial";
@@ -351,7 +344,6 @@
 		reg = <0x70006400 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 20>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTE>;
 		resets = <&tegra_car 66>;
 		reset-names = "serial";
@@ -397,7 +389,6 @@
 		compatible = "nvidia,tegra20-sflash";
 		reg = <0x7000c380 0x80>;
 		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 11>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SPI>;
@@ -460,7 +451,6 @@
 		compatible = "nvidia,tegra20-slink";
 		reg = <0x7000d400 0x200>;
 		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC1>;
@@ -475,7 +465,6 @@
 		compatible = "nvidia,tegra20-slink";
 		reg = <0x7000d600 0x200>;
 		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC2>;
@@ -490,7 +479,6 @@
 		compatible = "nvidia,tegra20-slink";
 		reg = <0x7000d800 0x200>;
 		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC3>;
@@ -505,7 +493,6 @@
 		compatible = "nvidia,tegra20-slink";
 		reg = <0x7000da00 0x200>;
 		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC4>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 348b0f07f675..03ec194e832f 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -345,7 +345,6 @@
 		reg = <0x70006000 0x40>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 8>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTA>;
 		resets = <&tegra_car 6>;
 		reset-names = "serial";
@@ -359,7 +358,6 @@
 		reg = <0x70006040 0x40>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 9>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTB>;
 		resets = <&tegra_car 7>;
 		reset-names = "serial";
@@ -373,7 +371,6 @@
 		reg = <0x70006200 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 10>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTC>;
 		resets = <&tegra_car 55>;
 		reset-names = "serial";
@@ -387,7 +384,6 @@
 		reg = <0x70006300 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 19>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTD>;
 		resets = <&tegra_car 65>;
 		reset-names = "serial";
@@ -401,7 +397,6 @@
 		reg = <0x70006400 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 20>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTE>;
 		resets = <&tegra_car 66>;
 		reset-names = "serial";
@@ -511,7 +506,6 @@
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000d400 0x200>;
 		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC1>;
@@ -526,7 +520,6 @@
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000d600 0x200>;
 		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC2>;
@@ -541,7 +534,6 @@
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000d800 0x200>;
 		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC3>;
@@ -556,7 +548,6 @@
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000da00 0x200>;
 		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC4>;
@@ -571,7 +562,6 @@
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000dc00 0x200>;
 		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 27>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC5>;
@@ -586,7 +576,6 @@
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000de00 0x200>;
 		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 28>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC6>;
@@ -638,7 +627,6 @@
 		reg = <0x70080000 0x200
 		       0x70080200 0x100>;
 		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 1>;
 		clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
 			 <&tegra_car TEGRA30_CLK_APBIF>;
 		clock-names = "d_audio", "apbif";
-- 
1.8.1.5

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[PATCH 29/31] ARM: tegra: remove legacy DMA entries from DT

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Now that all Tegra drivers have been converted to use DMA APIs which
retrieve DMA channel information from standard DMA DT properties, we can
remove all the legacy DT DMA-related properties.

Cc: treding at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: devicetree at vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 arch/arm/boot/dts/tegra114.dtsi | 14 --------------
 arch/arm/boot/dts/tegra20.dtsi  | 13 -------------
 arch/arm/boot/dts/tegra30.dtsi  | 12 ------------
 3 files changed, 39 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index b4f2e62909a7..6d4858b2c701 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -128,7 +128,6 @@
 		reg = <0x70006000 0x40>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 8>;
 		clocks = <&tegra_car TEGRA114_CLK_UARTA>;
 		resets = <&tegra_car 6>;
 		reset-names = "serial";
@@ -142,7 +141,6 @@
 		reg = <0x70006040 0x40>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 9>;
 		clocks = <&tegra_car TEGRA114_CLK_UARTB>;
 		resets = <&tegra_car 7>;
 		reset-names = "serial";
@@ -156,7 +154,6 @@
 		reg = <0x70006200 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 10>;
 		clocks = <&tegra_car TEGRA114_CLK_UARTC>;
 		resets = <&tegra_car 55>;
 		reset-names = "serial";
@@ -170,7 +167,6 @@
 		reg = <0x70006300 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 19>;
 		clocks = <&tegra_car TEGRA114_CLK_UARTD>;
 		resets = <&tegra_car 65>;
 		reset-names = "serial";
@@ -268,7 +264,6 @@
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000d400 0x200>;
 		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC1>;
@@ -284,7 +279,6 @@
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000d600 0x200>;
 		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC2>;
@@ -300,7 +294,6 @@
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000d800 0x200>;
 		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC3>;
@@ -316,7 +309,6 @@
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000da00 0x200>;
 		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC4>;
@@ -332,7 +324,6 @@
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000dc00 0x200>;
 		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 27>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC5>;
@@ -348,7 +339,6 @@
 		compatible = "nvidia,tegra114-spi";
 		reg = <0x7000de00 0x200>;
 		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 28>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA114_CLK_SBC6>;
@@ -401,10 +391,6 @@
 		      <0x70080200 0x100>,
 		      <0x70081000 0x200>;
 		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>,
-			<&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>,
-			<&apbdma 12>, <&apbdma 13>, <&apbdma 14>,
-			<&apbdma 29>;
 		clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
 			 <&tegra_car TEGRA114_CLK_APBIF>,
 			 <&tegra_car TEGRA114_CLK_I2S0>,
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 61d2f3868f4f..f780f7bed7bf 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -248,7 +248,6 @@
 		compatible = "nvidia,tegra20-ac97";
 		reg = <0x70002000 0x200>;
 		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 12>;
 		clocks = <&tegra_car TEGRA20_CLK_AC97>;
 		resets = <&tegra_car 3>;
 		reset-names = "ac97";
@@ -261,7 +260,6 @@
 		compatible = "nvidia,tegra20-i2s";
 		reg = <0x70002800 0x200>;
 		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 2>;
 		clocks = <&tegra_car TEGRA20_CLK_I2S1>;
 		resets = <&tegra_car 11>;
 		reset-names = "i2s";
@@ -274,7 +272,6 @@
 		compatible = "nvidia,tegra20-i2s";
 		reg = <0x70002a00 0x200>;
 		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 1>;
 		clocks = <&tegra_car TEGRA20_CLK_I2S2>;
 		resets = <&tegra_car 18>;
 		reset-names = "i2s";
@@ -295,7 +292,6 @@
 		reg = <0x70006000 0x40>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 8>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTA>;
 		resets = <&tegra_car 6>;
 		reset-names = "serial";
@@ -309,7 +305,6 @@
 		reg = <0x70006040 0x40>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 9>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTB>;
 		resets = <&tegra_car 7>;
 		reset-names = "serial";
@@ -323,7 +318,6 @@
 		reg = <0x70006200 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 10>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTC>;
 		resets = <&tegra_car 55>;
 		reset-names = "serial";
@@ -337,7 +331,6 @@
 		reg = <0x70006300 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 19>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTD>;
 		resets = <&tegra_car 65>;
 		reset-names = "serial";
@@ -351,7 +344,6 @@
 		reg = <0x70006400 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 20>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTE>;
 		resets = <&tegra_car 66>;
 		reset-names = "serial";
@@ -397,7 +389,6 @@
 		compatible = "nvidia,tegra20-sflash";
 		reg = <0x7000c380 0x80>;
 		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 11>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SPI>;
@@ -460,7 +451,6 @@
 		compatible = "nvidia,tegra20-slink";
 		reg = <0x7000d400 0x200>;
 		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC1>;
@@ -475,7 +465,6 @@
 		compatible = "nvidia,tegra20-slink";
 		reg = <0x7000d600 0x200>;
 		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC2>;
@@ -490,7 +479,6 @@
 		compatible = "nvidia,tegra20-slink";
 		reg = <0x7000d800 0x200>;
 		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC3>;
@@ -505,7 +493,6 @@
 		compatible = "nvidia,tegra20-slink";
 		reg = <0x7000da00 0x200>;
 		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC4>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 348b0f07f675..03ec194e832f 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -345,7 +345,6 @@
 		reg = <0x70006000 0x40>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 8>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTA>;
 		resets = <&tegra_car 6>;
 		reset-names = "serial";
@@ -359,7 +358,6 @@
 		reg = <0x70006040 0x40>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 9>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTB>;
 		resets = <&tegra_car 7>;
 		reset-names = "serial";
@@ -373,7 +371,6 @@
 		reg = <0x70006200 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 10>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTC>;
 		resets = <&tegra_car 55>;
 		reset-names = "serial";
@@ -387,7 +384,6 @@
 		reg = <0x70006300 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 19>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTD>;
 		resets = <&tegra_car 65>;
 		reset-names = "serial";
@@ -401,7 +397,6 @@
 		reg = <0x70006400 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 20>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTE>;
 		resets = <&tegra_car 66>;
 		reset-names = "serial";
@@ -511,7 +506,6 @@
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000d400 0x200>;
 		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC1>;
@@ -526,7 +520,6 @@
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000d600 0x200>;
 		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC2>;
@@ -541,7 +534,6 @@
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000d800 0x200>;
 		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC3>;
@@ -556,7 +548,6 @@
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000da00 0x200>;
 		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC4>;
@@ -571,7 +562,6 @@
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000dc00 0x200>;
 		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 27>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC5>;
@@ -586,7 +576,6 @@
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000de00 0x200>;
 		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 28>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA30_CLK_SBC6>;
@@ -638,7 +627,6 @@
 		reg = <0x70080000 0x200
 		       0x70080200 0x100>;
 		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 1>;
 		clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
 			 <&tegra_car TEGRA30_CLK_APBIF>;
 		clock-names = "d_audio", "apbif";
-- 
1.8.1.5

Re: [PATCH 29/31] ARM: tegra: remove legacy DMA entries from DT

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1240 bytes --]

On Fri, Nov 15, 2013 at 01:54:24PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Now that all Tegra drivers have been converted to use DMA APIs which
> retrieve DMA channel information from standard DMA DT properties, we can
> remove all the legacy DT DMA-related properties.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
> Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>  arch/arm/boot/dts/tegra114.dtsi | 14 --------------
>  arch/arm/boot/dts/tegra20.dtsi  | 13 -------------
>  arch/arm/boot/dts/tegra30.dtsi  | 12 ------------
>  3 files changed, 39 deletions(-)

Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

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[PATCH 29/31] ARM: tegra: remove legacy DMA entries from DT

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:54:24PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Now that all Tegra drivers have been converted to use DMA APIs which
> retrieve DMA channel information from standard DMA DT properties, we can
> remove all the legacy DT DMA-related properties.
> 
> Cc: treding at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Pawel Moll <pawel.moll@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
> Cc: devicetree at vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
>  arch/arm/boot/dts/tegra114.dtsi | 14 --------------
>  arch/arm/boot/dts/tegra20.dtsi  | 13 -------------
>  arch/arm/boot/dts/tegra30.dtsi  | 12 ------------
>  3 files changed, 39 deletions(-)

Reviewed-by: Thierry Reding <treding@nvidia.com>
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[PATCH 30/31] clk: tegra: remove legacy reset APIs

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Now that no code uses the custom Tegra module reset API, we can remove
its implementation.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/clk/tegra/clk-periph-gate.c | 22 --------------------
 drivers/clk/tegra/clk-periph.c      | 40 -------------------------------------
 drivers/clk/tegra/clk.h             |  1 -
 include/linux/clk/tegra.h           |  7 -------
 4 files changed, 70 deletions(-)

diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
index f38f33e3c65d..507015314827 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -36,8 +36,6 @@ static DEFINE_SPINLOCK(periph_ref_lock);
 
 #define read_rst(gate) \
 	readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
-#define write_rst_set(val, gate) \
-	writel_relaxed(val, gate->clk_base + (gate->regs->rst_set_reg))
 #define write_rst_clr(val, gate) \
 	writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
 
@@ -123,26 +121,6 @@ static void clk_periph_disable(struct clk_hw *hw)
 	spin_unlock_irqrestore(&periph_ref_lock, flags);
 }
 
-void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert)
-{
-	if (gate->flags & TEGRA_PERIPH_NO_RESET)
-		return;
-
-	if (assert) {
-		/*
-		 * If peripheral is in the APB bus then read the APB bus to
-		 * flush the write operation in apb bus. This will avoid the
-		 * peripheral access after disabling clock
-		 */
-		if (gate->flags & TEGRA_PERIPH_ON_APB)
-			tegra_read_chipid();
-
-		write_rst_set(periph_clk_to_bit(gate), gate);
-	} else {
-		write_rst_clr(periph_clk_to_bit(gate), gate);
-	}
-}
-
 const struct clk_ops tegra_clk_periph_gate_ops = {
 	.is_enabled = clk_periph_is_enabled,
 	.enable = clk_periph_enable,
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index b5feccca2f1e..d8ed9f79708b 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -111,46 +111,6 @@ static void clk_periph_disable(struct clk_hw *hw)
 	gate_ops->disable(gate_hw);
 }
 
-void tegra_periph_reset_deassert(struct clk *c)
-{
-	struct clk_hw *hw = __clk_get_hw(c);
-	struct tegra_clk_periph *periph = to_clk_periph(hw);
-	struct tegra_clk_periph_gate *gate;
-
-	if (periph->magic != TEGRA_CLK_PERIPH_MAGIC) {
-		gate = to_clk_periph_gate(hw);
-		if (gate->magic != TEGRA_CLK_PERIPH_GATE_MAGIC) {
-			WARN_ON(1);
-			return;
-		}
-	} else {
-		gate = &periph->gate;
-	}
-
-	tegra_periph_reset(gate, 0);
-}
-EXPORT_SYMBOL(tegra_periph_reset_deassert);
-
-void tegra_periph_reset_assert(struct clk *c)
-{
-	struct clk_hw *hw = __clk_get_hw(c);
-	struct tegra_clk_periph *periph = to_clk_periph(hw);
-	struct tegra_clk_periph_gate *gate;
-
-	if (periph->magic != TEGRA_CLK_PERIPH_MAGIC) {
-		gate = to_clk_periph_gate(hw);
-		if (gate->magic != TEGRA_CLK_PERIPH_GATE_MAGIC) {
-			WARN_ON(1);
-			return;
-		}
-	} else {
-		gate = &periph->gate;
-	}
-
-	tegra_periph_reset(gate, 1);
-}
-EXPORT_SYMBOL(tegra_periph_reset_assert);
-
 const struct clk_ops tegra_clk_periph_ops = {
 	.get_parent = clk_periph_get_parent,
 	.set_parent = clk_periph_set_parent,
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 39f24959daf7..57bd0d3090e3 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -392,7 +392,6 @@ struct tegra_clk_periph_gate {
 #define TEGRA_PERIPH_WAR_1005168 BIT(3)
 #define TEGRA_PERIPH_NO_DIV BIT(4)
 
-void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
 extern const struct clk_ops tegra_clk_periph_gate_ops;
 struct clk *tegra_clk_register_periph_gate(const char *name,
 		const char *parent_name, u8 gate_flags, void __iomem *clk_base,
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 23a0ceee831f..3ca9fca827a2 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -120,13 +120,6 @@ static inline void tegra_cpu_clock_resume(void)
 }
 #endif
 
-#ifdef CONFIG_ARCH_TEGRA
-void tegra_periph_reset_deassert(struct clk *c);
-void tegra_periph_reset_assert(struct clk *c);
-#else
-static inline void tegra_periph_reset_deassert(struct clk *c) {}
-static inline void tegra_periph_reset_assert(struct clk *c) {}
-#endif
 void tegra_clocks_apply_init_table(void);
 
 #endif /* __LINUX_CLK_TEGRA_H_ */
-- 
1.8.1.5

[PATCH 30/31] clk: tegra: remove legacy reset APIs

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Now that no code uses the custom Tegra module reset API, we can remove
its implementation.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/clk/tegra/clk-periph-gate.c | 22 --------------------
 drivers/clk/tegra/clk-periph.c      | 40 -------------------------------------
 drivers/clk/tegra/clk.h             |  1 -
 include/linux/clk/tegra.h           |  7 -------
 4 files changed, 70 deletions(-)

diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
index f38f33e3c65d..507015314827 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -36,8 +36,6 @@ static DEFINE_SPINLOCK(periph_ref_lock);
 
 #define read_rst(gate) \
 	readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
-#define write_rst_set(val, gate) \
-	writel_relaxed(val, gate->clk_base + (gate->regs->rst_set_reg))
 #define write_rst_clr(val, gate) \
 	writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
 
@@ -123,26 +121,6 @@ static void clk_periph_disable(struct clk_hw *hw)
 	spin_unlock_irqrestore(&periph_ref_lock, flags);
 }
 
-void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert)
-{
-	if (gate->flags & TEGRA_PERIPH_NO_RESET)
-		return;
-
-	if (assert) {
-		/*
-		 * If peripheral is in the APB bus then read the APB bus to
-		 * flush the write operation in apb bus. This will avoid the
-		 * peripheral access after disabling clock
-		 */
-		if (gate->flags & TEGRA_PERIPH_ON_APB)
-			tegra_read_chipid();
-
-		write_rst_set(periph_clk_to_bit(gate), gate);
-	} else {
-		write_rst_clr(periph_clk_to_bit(gate), gate);
-	}
-}
-
 const struct clk_ops tegra_clk_periph_gate_ops = {
 	.is_enabled = clk_periph_is_enabled,
 	.enable = clk_periph_enable,
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index b5feccca2f1e..d8ed9f79708b 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -111,46 +111,6 @@ static void clk_periph_disable(struct clk_hw *hw)
 	gate_ops->disable(gate_hw);
 }
 
-void tegra_periph_reset_deassert(struct clk *c)
-{
-	struct clk_hw *hw = __clk_get_hw(c);
-	struct tegra_clk_periph *periph = to_clk_periph(hw);
-	struct tegra_clk_periph_gate *gate;
-
-	if (periph->magic != TEGRA_CLK_PERIPH_MAGIC) {
-		gate = to_clk_periph_gate(hw);
-		if (gate->magic != TEGRA_CLK_PERIPH_GATE_MAGIC) {
-			WARN_ON(1);
-			return;
-		}
-	} else {
-		gate = &periph->gate;
-	}
-
-	tegra_periph_reset(gate, 0);
-}
-EXPORT_SYMBOL(tegra_periph_reset_deassert);
-
-void tegra_periph_reset_assert(struct clk *c)
-{
-	struct clk_hw *hw = __clk_get_hw(c);
-	struct tegra_clk_periph *periph = to_clk_periph(hw);
-	struct tegra_clk_periph_gate *gate;
-
-	if (periph->magic != TEGRA_CLK_PERIPH_MAGIC) {
-		gate = to_clk_periph_gate(hw);
-		if (gate->magic != TEGRA_CLK_PERIPH_GATE_MAGIC) {
-			WARN_ON(1);
-			return;
-		}
-	} else {
-		gate = &periph->gate;
-	}
-
-	tegra_periph_reset(gate, 1);
-}
-EXPORT_SYMBOL(tegra_periph_reset_assert);
-
 const struct clk_ops tegra_clk_periph_ops = {
 	.get_parent = clk_periph_get_parent,
 	.set_parent = clk_periph_set_parent,
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 39f24959daf7..57bd0d3090e3 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -392,7 +392,6 @@ struct tegra_clk_periph_gate {
 #define TEGRA_PERIPH_WAR_1005168 BIT(3)
 #define TEGRA_PERIPH_NO_DIV BIT(4)
 
-void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
 extern const struct clk_ops tegra_clk_periph_gate_ops;
 struct clk *tegra_clk_register_periph_gate(const char *name,
 		const char *parent_name, u8 gate_flags, void __iomem *clk_base,
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 23a0ceee831f..3ca9fca827a2 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -120,13 +120,6 @@ static inline void tegra_cpu_clock_resume(void)
 }
 #endif
 
-#ifdef CONFIG_ARCH_TEGRA
-void tegra_periph_reset_deassert(struct clk *c);
-void tegra_periph_reset_assert(struct clk *c);
-#else
-static inline void tegra_periph_reset_deassert(struct clk *c) {}
-static inline void tegra_periph_reset_assert(struct clk *c) {}
-#endif
 void tegra_clocks_apply_init_table(void);
 
 #endif /* __LINUX_CLK_TEGRA_H_ */
-- 
1.8.1.5

Re: [PATCH 30/31] clk: tegra: remove legacy reset APIs

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1346 bytes --]

On Fri, Nov 15, 2013 at 01:54:25PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Now that no code uses the custom Tegra module reset API, we can remove
> its implementation.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/clk/tegra/clk-periph-gate.c | 22 --------------------
>  drivers/clk/tegra/clk-periph.c      | 40 -------------------------------------
>  drivers/clk/tegra/clk.h             |  1 -
>  include/linux/clk/tegra.h           |  7 -------
>  4 files changed, 70 deletions(-)

Very nice!

Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]

[PATCH 30/31] clk: tegra: remove legacy reset APIs

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:54:25PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Now that no code uses the custom Tegra module reset API, we can remove
> its implementation.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Mike Turquette <mturquette@linaro.org>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/clk/tegra/clk-periph-gate.c | 22 --------------------
>  drivers/clk/tegra/clk-periph.c      | 40 -------------------------------------
>  drivers/clk/tegra/clk.h             |  1 -
>  include/linux/clk/tegra.h           |  7 -------
>  4 files changed, 70 deletions(-)

Very nice!

Reviewed-by: Thierry Reding <treding@nvidia.com>
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[PATCH 31/31] clk: tegra: remove bogus PCIE_XCLK

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

The "pcie_xclk" clock is not actually a clock at all, but rather a reset
domain. Now that the custom Tegra module reset API has been removed, we
can remove the definition of any "clocks" that existed solely to support
it.

Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/clk/tegra/clk-tegra20.c         | 6 ------
 drivers/clk/tegra/clk-tegra30.c         | 7 -------
 include/dt-bindings/clock/tegra20-car.h | 2 +-
 include/dt-bindings/clock/tegra30-car.h | 2 +-
 4 files changed, 2 insertions(+), 15 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index eeffff6c6778..69c44ccc2ab2 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -473,7 +473,6 @@ static struct tegra_devclk devclks[] __initdata = {
 	{ .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP },
 	{ .con_id = "pex", .dt_id = TEGRA20_CLK_PEX },
 	{ .con_id = "afi", .dt_id = TEGRA20_CLK_AFI },
-	{ .con_id = "pcie_xclk", .dt_id = TEGRA20_CLK_PCIE_XCLK },
 	{ .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
 	{ .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
 	{ .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
@@ -839,11 +838,6 @@ static void __init tegra20_periph_clk_init(void)
 				    periph_clk_enb_refcnt);
 	clks[TEGRA20_CLK_PEX] = clk;
 
-	/* pcie_xclk */
-	clk = tegra_clk_register_periph_gate("pcie_xclk", "clk_m", 0, clk_base,
-				    0, 74, periph_clk_enb_refcnt);
-	clks[TEGRA20_CLK_PCIE_XCLK] = clk;
-
 	/* cdev1 */
 	clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT,
 				      26000000);
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index e9b6a305be92..a0c9cc4dc6a3 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -658,7 +658,6 @@ static struct tegra_devclk devclks[] __initdata = {
 	{ .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP },
 	{ .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
 	{ .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
-	{ .con_id = "pciex", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIEX },
 	{ .con_id = "fuse", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE },
 	{ .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
 	{ .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
@@ -1159,11 +1158,6 @@ static void __init tegra30_periph_clk_init(void)
 				    periph_clk_enb_refcnt);
 	clks[TEGRA30_CLK_AFI] = clk;
 
-	/* pciex */
-	clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0,
-				    74, periph_clk_enb_refcnt);
-	clks[TEGRA30_CLK_PCIEX] = clk;
-
 	/* emc */
 	clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
 			       ARRAY_SIZE(mux_pllmcp_clkm),
@@ -1404,7 +1398,6 @@ static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
 	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "nvavp", "bsea"),
 	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),
 	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),
-	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_PCIEX, "tegra_pcie", "pciex"),
 	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),
 	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL), /* MUST be the last entry */
 };
diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h
index a1ae9a8fdd6c..9406207cfac8 100644
--- a/include/dt-bindings/clock/tegra20-car.h
+++ b/include/dt-bindings/clock/tegra20-car.h
@@ -92,7 +92,7 @@
 #define TEGRA20_CLK_OWR 71
 #define TEGRA20_CLK_AFI 72
 #define TEGRA20_CLK_CSITE 73
-#define TEGRA20_CLK_PCIE_XCLK 74
+/* 74 */
 #define TEGRA20_CLK_AVPUCQ 75
 #define TEGRA20_CLK_LA 76
 /* 77 */
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h
index 22445820a929..889e49ba0aa3 100644
--- a/include/dt-bindings/clock/tegra30-car.h
+++ b/include/dt-bindings/clock/tegra30-car.h
@@ -92,7 +92,7 @@
 #define TEGRA30_CLK_OWR 71
 #define TEGRA30_CLK_AFI 72
 #define TEGRA30_CLK_CSITE 73
-#define TEGRA30_CLK_PCIEX 74
+/* 74 */
 #define TEGRA30_CLK_AVPUCQ 75
 #define TEGRA30_CLK_LA 76
 /* 77 */
-- 
1.8.1.5

[PATCH 31/31] clk: tegra: remove bogus PCIE_XCLK

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

The "pcie_xclk" clock is not actually a clock at all, but rather a reset
domain. Now that the custom Tegra module reset API has been removed, we
can remove the definition of any "clocks" that existed solely to support
it.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/clk/tegra/clk-tegra20.c         | 6 ------
 drivers/clk/tegra/clk-tegra30.c         | 7 -------
 include/dt-bindings/clock/tegra20-car.h | 2 +-
 include/dt-bindings/clock/tegra30-car.h | 2 +-
 4 files changed, 2 insertions(+), 15 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index eeffff6c6778..69c44ccc2ab2 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -473,7 +473,6 @@ static struct tegra_devclk devclks[] __initdata = {
 	{ .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP },
 	{ .con_id = "pex", .dt_id = TEGRA20_CLK_PEX },
 	{ .con_id = "afi", .dt_id = TEGRA20_CLK_AFI },
-	{ .con_id = "pcie_xclk", .dt_id = TEGRA20_CLK_PCIE_XCLK },
 	{ .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
 	{ .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
 	{ .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
@@ -839,11 +838,6 @@ static void __init tegra20_periph_clk_init(void)
 				    periph_clk_enb_refcnt);
 	clks[TEGRA20_CLK_PEX] = clk;
 
-	/* pcie_xclk */
-	clk = tegra_clk_register_periph_gate("pcie_xclk", "clk_m", 0, clk_base,
-				    0, 74, periph_clk_enb_refcnt);
-	clks[TEGRA20_CLK_PCIE_XCLK] = clk;
-
 	/* cdev1 */
 	clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT,
 				      26000000);
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index e9b6a305be92..a0c9cc4dc6a3 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -658,7 +658,6 @@ static struct tegra_devclk devclks[] __initdata = {
 	{ .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP },
 	{ .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
 	{ .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
-	{ .con_id = "pciex", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIEX },
 	{ .con_id = "fuse", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE },
 	{ .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
 	{ .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
@@ -1159,11 +1158,6 @@ static void __init tegra30_periph_clk_init(void)
 				    periph_clk_enb_refcnt);
 	clks[TEGRA30_CLK_AFI] = clk;
 
-	/* pciex */
-	clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0,
-				    74, periph_clk_enb_refcnt);
-	clks[TEGRA30_CLK_PCIEX] = clk;
-
 	/* emc */
 	clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
 			       ARRAY_SIZE(mux_pllmcp_clkm),
@@ -1404,7 +1398,6 @@ static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
 	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "nvavp", "bsea"),
 	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),
 	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),
-	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_PCIEX, "tegra_pcie", "pciex"),
 	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),
 	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL), /* MUST be the last entry */
 };
diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h
index a1ae9a8fdd6c..9406207cfac8 100644
--- a/include/dt-bindings/clock/tegra20-car.h
+++ b/include/dt-bindings/clock/tegra20-car.h
@@ -92,7 +92,7 @@
 #define TEGRA20_CLK_OWR 71
 #define TEGRA20_CLK_AFI 72
 #define TEGRA20_CLK_CSITE 73
-#define TEGRA20_CLK_PCIE_XCLK 74
+/* 74 */
 #define TEGRA20_CLK_AVPUCQ 75
 #define TEGRA20_CLK_LA 76
 /* 77 */
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h
index 22445820a929..889e49ba0aa3 100644
--- a/include/dt-bindings/clock/tegra30-car.h
+++ b/include/dt-bindings/clock/tegra30-car.h
@@ -92,7 +92,7 @@
 #define TEGRA30_CLK_OWR 71
 #define TEGRA30_CLK_AFI 72
 #define TEGRA30_CLK_CSITE 73
-#define TEGRA30_CLK_PCIEX 74
+/* 74 */
 #define TEGRA30_CLK_AVPUCQ 75
 #define TEGRA30_CLK_LA 76
 /* 77 */
-- 
1.8.1.5

Re: [PATCH 31/31] clk: tegra: remove bogus PCIE_XCLK

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1450 bytes --]

On Fri, Nov 15, 2013 at 01:54:26PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> The "pcie_xclk" clock is not actually a clock at all, but rather a reset
> domain. Now that the custom Tegra module reset API has been removed, we
> can remove the definition of any "clocks" that existed solely to support
> it.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/clk/tegra/clk-tegra20.c         | 6 ------
>  drivers/clk/tegra/clk-tegra30.c         | 7 -------
>  include/dt-bindings/clock/tegra20-car.h | 2 +-
>  include/dt-bindings/clock/tegra30-car.h | 2 +-
>  4 files changed, 2 insertions(+), 15 deletions(-)

Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

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[PATCH 31/31] clk: tegra: remove bogus PCIE_XCLK

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:54:26PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> The "pcie_xclk" clock is not actually a clock at all, but rather a reset
> domain. Now that the custom Tegra module reset API has been removed, we
> can remove the definition of any "clocks" that existed solely to support
> it.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Mike Turquette <mturquette@linaro.org>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/clk/tegra/clk-tegra20.c         | 6 ------
>  drivers/clk/tegra/clk-tegra30.c         | 7 -------
>  include/dt-bindings/clock/tegra20-car.h | 2 +-
>  include/dt-bindings/clock/tegra30-car.h | 2 +-
>  4 files changed, 2 insertions(+), 15 deletions(-)

Reviewed-by: Thierry Reding <treding@nvidia.com>
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[PATCH 24/31] serial: tegra: use reset framework

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

Cc: treding@nvidia.com
Cc: pdeschrijver@nvidia.com
Cc: linux-tegra@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-serial@vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/tty/serial/serial-tegra.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c
index dfe79ccc4fb3..4455481a3517 100644
--- a/drivers/tty/serial/serial-tegra.c
+++ b/drivers/tty/serial/serial-tegra.c
@@ -34,6 +34,7 @@
 #include <linux/of_device.h>
 #include <linux/pagemap.h>
 #include <linux/platform_device.h>
+#include <linux/reset.h>
 #include <linux/serial.h>
 #include <linux/serial_8250.h>
 #include <linux/serial_core.h>
@@ -44,8 +45,6 @@
 #include <linux/tty.h>
 #include <linux/tty_flip.h>
 
-#include <linux/clk/tegra.h>
-
 #define TEGRA_UART_TYPE				"TEGRA_UART"
 #define TX_EMPTY_STATUS				(UART_LSR_TEMT | UART_LSR_THRE)
 #define BYTES_TO_ALIGN(x)			((unsigned long)(x) & 0x3)
@@ -103,6 +102,7 @@ struct tegra_uart_port {
 	const struct tegra_uart_chip_data	*cdata;
 
 	struct clk				*uart_clk;
+	struct reset_control			*rst;
 	unsigned int				current_baud;
 
 	/* Register shadow */
@@ -832,9 +832,9 @@ static int tegra_uart_hw_init(struct tegra_uart_port *tup)
 	clk_prepare_enable(tup->uart_clk);
 
 	/* Reset the UART controller to clear all previous status.*/
-	tegra_periph_reset_assert(tup->uart_clk);
+	reset_control_assert(tup->rst);
 	udelay(10);
-	tegra_periph_reset_deassert(tup->uart_clk);
+	reset_control_deassert(tup->rst);
 
 	tup->rx_in_progress = 0;
 	tup->tx_in_progress = 0;
@@ -1320,6 +1320,12 @@ static int tegra_uart_probe(struct platform_device *pdev)
 		return PTR_ERR(tup->uart_clk);
 	}
 
+	tup->rst = devm_reset_control_get(&pdev->dev, "serial");
+	if (IS_ERR(tup->rst)) {
+		dev_err(&pdev->dev, "Couldn't get the reset\n");
+		return PTR_ERR(tup->rst);
+	}
+
 	u->iotype = UPIO_MEM32;
 	u->irq = platform_get_irq(pdev, 0);
 	u->regshift = 2;
-- 
1.8.1.5

[PATCH 24/31] serial: tegra: use reset framework

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-serial at vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/tty/serial/serial-tegra.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c
index dfe79ccc4fb3..4455481a3517 100644
--- a/drivers/tty/serial/serial-tegra.c
+++ b/drivers/tty/serial/serial-tegra.c
@@ -34,6 +34,7 @@
 #include <linux/of_device.h>
 #include <linux/pagemap.h>
 #include <linux/platform_device.h>
+#include <linux/reset.h>
 #include <linux/serial.h>
 #include <linux/serial_8250.h>
 #include <linux/serial_core.h>
@@ -44,8 +45,6 @@
 #include <linux/tty.h>
 #include <linux/tty_flip.h>
 
-#include <linux/clk/tegra.h>
-
 #define TEGRA_UART_TYPE				"TEGRA_UART"
 #define TX_EMPTY_STATUS				(UART_LSR_TEMT | UART_LSR_THRE)
 #define BYTES_TO_ALIGN(x)			((unsigned long)(x) & 0x3)
@@ -103,6 +102,7 @@ struct tegra_uart_port {
 	const struct tegra_uart_chip_data	*cdata;
 
 	struct clk				*uart_clk;
+	struct reset_control			*rst;
 	unsigned int				current_baud;
 
 	/* Register shadow */
@@ -832,9 +832,9 @@ static int tegra_uart_hw_init(struct tegra_uart_port *tup)
 	clk_prepare_enable(tup->uart_clk);
 
 	/* Reset the UART controller to clear all previous status.*/
-	tegra_periph_reset_assert(tup->uart_clk);
+	reset_control_assert(tup->rst);
 	udelay(10);
-	tegra_periph_reset_deassert(tup->uart_clk);
+	reset_control_deassert(tup->rst);
 
 	tup->rx_in_progress = 0;
 	tup->tx_in_progress = 0;
@@ -1320,6 +1320,12 @@ static int tegra_uart_probe(struct platform_device *pdev)
 		return PTR_ERR(tup->uart_clk);
 	}
 
+	tup->rst = devm_reset_control_get(&pdev->dev, "serial");
+	if (IS_ERR(tup->rst)) {
+		dev_err(&pdev->dev, "Couldn't get the reset\n");
+		return PTR_ERR(tup->rst);
+	}
+
 	u->iotype = UPIO_MEM32;
 	u->irq = platform_get_irq(pdev, 0);
 	u->regshift = 2;
-- 
1.8.1.5

Re: [PATCH 24/31] serial: tegra: use reset framework

[Greg Kroah-Hartman]

On Fri, Nov 15, 2013 at 01:54:19PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding@nvidia.com
> Cc: pdeschrijver@nvidia.com
> Cc: linux-tegra@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: linux-serial@vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.

Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

[PATCH 24/31] serial: tegra: use reset framework

[Greg Kroah-Hartman]

On Fri, Nov 15, 2013 at 01:54:19PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: linux-serial at vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.

Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Re: [PATCH 24/31] serial: tegra: use reset framework

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1316 bytes --]

On Fri, Nov 15, 2013 at 01:54:19PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
> Cc: linux-serial-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/tty/serial/serial-tegra.c | 14 ++++++++++----
>  1 file changed, 10 insertions(+), 4 deletions(-)

Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

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[PATCH 24/31] serial: tegra: use reset framework

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:54:19PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: linux-serial at vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/tty/serial/serial-tegra.c | 14 ++++++++++----
>  1 file changed, 10 insertions(+), 4 deletions(-)

Reviewed-by: Thierry Reding <treding@nvidia.com>
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[PATCH 25/31] serial: tegra: convert to standard DMA DT bindings

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

By using dma_request_slave_channel_or_err(), the DMA slave ID can be
looked up from standard DT properties, and squirrelled away during
channel allocation. Hence, there's no need to use a custom DT property
to store the slave ID.

DMA channel allocation is moved to probe() so that deferred probe works.

Cc: treding@nvidia.com
Cc: linux-tegra@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-serial@vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/tty/serial/serial-tegra.c | 72 ++++++++++++++++-----------------------
 1 file changed, 30 insertions(+), 42 deletions(-)

diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c
index 4455481a3517..e07c8bfe7459 100644
--- a/drivers/tty/serial/serial-tegra.c
+++ b/drivers/tty/serial/serial-tegra.c
@@ -120,7 +120,6 @@ struct tegra_uart_port {
 	bool					rx_timeout;
 	int					rx_in_progress;
 	int					symb_bit;
-	int					dma_req_sel;
 
 	struct dma_chan				*rx_dma_chan;
 	struct dma_chan				*tx_dma_chan;
@@ -910,15 +909,15 @@ static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
 	dma_addr_t dma_phys;
 	int ret;
 	struct dma_slave_config dma_sconfig;
-	dma_cap_mask_t mask;
 
-	dma_cap_zero(mask);
-	dma_cap_set(DMA_SLAVE, mask);
-	dma_chan = dma_request_channel(mask, NULL, NULL);
-	if (!dma_chan) {
-		dev_err(tup->uport.dev,
-			"Dma channel is not available, will try later\n");
-		return -EPROBE_DEFER;
+	dma_chan = dma_request_slave_channel_or_err(tup->uport.dev,
+						dma_to_memory ? "rx" : "tx");
+	if (IS_ERR(dma_chan)) {
+		ret = PTR_ERR(dma_chan);
+		if (ret != -EPROBE_DEFER)
+			dev_err(tup->uport.dev,
+				"DMA channel alloc failed: %d\n", ret);
+		return ret;
 	}
 
 	if (dma_to_memory) {
@@ -938,7 +937,6 @@ static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
 		dma_buf = tup->uport.state->xmit.buf;
 	}
 
-	dma_sconfig.slave_id = tup->dma_req_sel;
 	if (dma_to_memory) {
 		dma_sconfig.src_addr = tup->uport.mapbase;
 		dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
@@ -1000,37 +998,20 @@ static int tegra_uart_startup(struct uart_port *u)
 	struct tegra_uart_port *tup = to_tegra_uport(u);
 	int ret;
 
-	ret = tegra_uart_dma_channel_allocate(tup, false);
-	if (ret < 0) {
-		dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", ret);
-		return ret;
-	}
-
-	ret = tegra_uart_dma_channel_allocate(tup, true);
-	if (ret < 0) {
-		dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", ret);
-		goto fail_rx_dma;
-	}
-
 	ret = tegra_uart_hw_init(tup);
 	if (ret < 0) {
 		dev_err(u->dev, "Uart HW init failed, err = %d\n", ret);
-		goto fail_hw_init;
+		return ret;
 	}
 
 	ret = request_irq(u->irq, tegra_uart_isr, 0,
 				dev_name(u->dev), tup);
 	if (ret < 0) {
 		dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
-		goto fail_hw_init;
+		return ret;
 	}
-	return 0;
 
-fail_hw_init:
-	tegra_uart_dma_channel_free(tup, true);
-fail_rx_dma:
-	tegra_uart_dma_channel_free(tup, false);
-	return ret;
+	return 0;
 }
 
 static void tegra_uart_shutdown(struct uart_port *u)
@@ -1042,8 +1023,6 @@ static void tegra_uart_shutdown(struct uart_port *u)
 	tup->rx_in_progress = 0;
 	tup->tx_in_progress = 0;
 
-	tegra_uart_dma_channel_free(tup, true);
-	tegra_uart_dma_channel_free(tup, false);
 	free_irq(u->irq, tup);
 }
 
@@ -1222,17 +1201,8 @@ static int tegra_uart_parse_dt(struct platform_device *pdev,
 	struct tegra_uart_port *tup)
 {
 	struct device_node *np = pdev->dev.of_node;
-	u32 of_dma[2];
 	int port;
 
-	if (of_property_read_u32_array(np, "nvidia,dma-request-selector",
-				of_dma, 2) >= 0) {
-		tup->dma_req_sel = of_dma[1];
-	} else {
-		dev_err(&pdev->dev, "missing dma requestor in device tree\n");
-		return -EINVAL;
-	}
-
 	port = of_alias_get_id(np, "serial");
 	if (port < 0) {
 		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);
@@ -1326,14 +1296,29 @@ static int tegra_uart_probe(struct platform_device *pdev)
 		return PTR_ERR(tup->rst);
 	}
 
+	ret = tegra_uart_dma_channel_allocate(tup, false);
+	if (ret < 0)
+		return ret;
+
+	ret = tegra_uart_dma_channel_allocate(tup, true);
+	if (ret < 0)
+		goto err_free_dma_tx;
+
 	u->iotype = UPIO_MEM32;
 	u->irq = platform_get_irq(pdev, 0);
 	u->regshift = 2;
 	ret = uart_add_one_port(&tegra_uart_driver, u);
 	if (ret < 0) {
 		dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret);
-		return ret;
+		goto err_free_dma_rx;
 	}
+
+	return 0;
+
+err_free_dma_tx:
+	tegra_uart_dma_channel_free(tup, false);
+err_free_dma_rx:
+	tegra_uart_dma_channel_free(tup, true);
 	return ret;
 }
 
@@ -1343,6 +1328,9 @@ static int tegra_uart_remove(struct platform_device *pdev)
 	struct uart_port *u = &tup->uport;
 
 	uart_remove_one_port(&tegra_uart_driver, u);
+	tegra_uart_dma_channel_free(tup, true);
+	tegra_uart_dma_channel_free(tup, false);
+
 	return 0;
 }
 
-- 
1.8.1.5

[PATCH 25/31] serial: tegra: convert to standard DMA DT bindings

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

By using dma_request_slave_channel_or_err(), the DMA slave ID can be
looked up from standard DT properties, and squirrelled away during
channel allocation. Hence, there's no need to use a custom DT property
to store the slave ID.

DMA channel allocation is moved to probe() so that deferred probe works.

Cc: treding at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-serial at vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/tty/serial/serial-tegra.c | 72 ++++++++++++++++-----------------------
 1 file changed, 30 insertions(+), 42 deletions(-)

diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c
index 4455481a3517..e07c8bfe7459 100644
--- a/drivers/tty/serial/serial-tegra.c
+++ b/drivers/tty/serial/serial-tegra.c
@@ -120,7 +120,6 @@ struct tegra_uart_port {
 	bool					rx_timeout;
 	int					rx_in_progress;
 	int					symb_bit;
-	int					dma_req_sel;
 
 	struct dma_chan				*rx_dma_chan;
 	struct dma_chan				*tx_dma_chan;
@@ -910,15 +909,15 @@ static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
 	dma_addr_t dma_phys;
 	int ret;
 	struct dma_slave_config dma_sconfig;
-	dma_cap_mask_t mask;
 
-	dma_cap_zero(mask);
-	dma_cap_set(DMA_SLAVE, mask);
-	dma_chan = dma_request_channel(mask, NULL, NULL);
-	if (!dma_chan) {
-		dev_err(tup->uport.dev,
-			"Dma channel is not available, will try later\n");
-		return -EPROBE_DEFER;
+	dma_chan = dma_request_slave_channel_or_err(tup->uport.dev,
+						dma_to_memory ? "rx" : "tx");
+	if (IS_ERR(dma_chan)) {
+		ret = PTR_ERR(dma_chan);
+		if (ret != -EPROBE_DEFER)
+			dev_err(tup->uport.dev,
+				"DMA channel alloc failed: %d\n", ret);
+		return ret;
 	}
 
 	if (dma_to_memory) {
@@ -938,7 +937,6 @@ static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
 		dma_buf = tup->uport.state->xmit.buf;
 	}
 
-	dma_sconfig.slave_id = tup->dma_req_sel;
 	if (dma_to_memory) {
 		dma_sconfig.src_addr = tup->uport.mapbase;
 		dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
@@ -1000,37 +998,20 @@ static int tegra_uart_startup(struct uart_port *u)
 	struct tegra_uart_port *tup = to_tegra_uport(u);
 	int ret;
 
-	ret = tegra_uart_dma_channel_allocate(tup, false);
-	if (ret < 0) {
-		dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", ret);
-		return ret;
-	}
-
-	ret = tegra_uart_dma_channel_allocate(tup, true);
-	if (ret < 0) {
-		dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", ret);
-		goto fail_rx_dma;
-	}
-
 	ret = tegra_uart_hw_init(tup);
 	if (ret < 0) {
 		dev_err(u->dev, "Uart HW init failed, err = %d\n", ret);
-		goto fail_hw_init;
+		return ret;
 	}
 
 	ret = request_irq(u->irq, tegra_uart_isr, 0,
 				dev_name(u->dev), tup);
 	if (ret < 0) {
 		dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
-		goto fail_hw_init;
+		return ret;
 	}
-	return 0;
 
-fail_hw_init:
-	tegra_uart_dma_channel_free(tup, true);
-fail_rx_dma:
-	tegra_uart_dma_channel_free(tup, false);
-	return ret;
+	return 0;
 }
 
 static void tegra_uart_shutdown(struct uart_port *u)
@@ -1042,8 +1023,6 @@ static void tegra_uart_shutdown(struct uart_port *u)
 	tup->rx_in_progress = 0;
 	tup->tx_in_progress = 0;
 
-	tegra_uart_dma_channel_free(tup, true);
-	tegra_uart_dma_channel_free(tup, false);
 	free_irq(u->irq, tup);
 }
 
@@ -1222,17 +1201,8 @@ static int tegra_uart_parse_dt(struct platform_device *pdev,
 	struct tegra_uart_port *tup)
 {
 	struct device_node *np = pdev->dev.of_node;
-	u32 of_dma[2];
 	int port;
 
-	if (of_property_read_u32_array(np, "nvidia,dma-request-selector",
-				of_dma, 2) >= 0) {
-		tup->dma_req_sel = of_dma[1];
-	} else {
-		dev_err(&pdev->dev, "missing dma requestor in device tree\n");
-		return -EINVAL;
-	}
-
 	port = of_alias_get_id(np, "serial");
 	if (port < 0) {
 		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);
@@ -1326,14 +1296,29 @@ static int tegra_uart_probe(struct platform_device *pdev)
 		return PTR_ERR(tup->rst);
 	}
 
+	ret = tegra_uart_dma_channel_allocate(tup, false);
+	if (ret < 0)
+		return ret;
+
+	ret = tegra_uart_dma_channel_allocate(tup, true);
+	if (ret < 0)
+		goto err_free_dma_tx;
+
 	u->iotype = UPIO_MEM32;
 	u->irq = platform_get_irq(pdev, 0);
 	u->regshift = 2;
 	ret = uart_add_one_port(&tegra_uart_driver, u);
 	if (ret < 0) {
 		dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret);
-		return ret;
+		goto err_free_dma_rx;
 	}
+
+	return 0;
+
+err_free_dma_tx:
+	tegra_uart_dma_channel_free(tup, false);
+err_free_dma_rx:
+	tegra_uart_dma_channel_free(tup, true);
 	return ret;
 }
 
@@ -1343,6 +1328,9 @@ static int tegra_uart_remove(struct platform_device *pdev)
 	struct uart_port *u = &tup->uport;
 
 	uart_remove_one_port(&tegra_uart_driver, u);
+	tegra_uart_dma_channel_free(tup, true);
+	tegra_uart_dma_channel_free(tup, false);
+
 	return 0;
 }
 
-- 
1.8.1.5

Re: [PATCH 25/31] serial: tegra: convert to standard DMA DT bindings

[Greg Kroah-Hartman]

On Fri, Nov 15, 2013 at 01:54:20PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> By using dma_request_slave_channel_or_err(), the DMA slave ID can be
> looked up from standard DT properties, and squirrelled away during
> channel allocation. Hence, there's no need to use a custom DT property
> to store the slave ID.
> 
> DMA channel allocation is moved to probe() so that deferred probe works.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
> Cc: linux-serial-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.

Acked-by: Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>

[PATCH 25/31] serial: tegra: convert to standard DMA DT bindings

[Greg Kroah-Hartman]

On Fri, Nov 15, 2013 at 01:54:20PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> By using dma_request_slave_channel_or_err(), the DMA slave ID can be
> looked up from standard DT properties, and squirrelled away during
> channel allocation. Hence, there's no need to use a custom DT property
> to store the slave ID.
> 
> DMA channel allocation is moved to probe() so that deferred probe works.
> 
> Cc: treding at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: linux-serial at vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.

Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

[PATCH 26/31] Input: tegra-kbc - use reset framework

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

Cc: treding@nvidia.com
Cc: pdeschrijver@nvidia.com
Cc: linux-tegra@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Dmitry Torokhov <dtor@mail.ru>
Cc: linux-input@vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/input/keyboard/tegra-kbc.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/input/keyboard/tegra-kbc.c b/drivers/input/keyboard/tegra-kbc.c
index 8508879f6faf..9757a58bc897 100644
--- a/drivers/input/keyboard/tegra-kbc.c
+++ b/drivers/input/keyboard/tegra-kbc.c
@@ -31,7 +31,7 @@
 #include <linux/clk.h>
 #include <linux/slab.h>
 #include <linux/input/matrix_keypad.h>
-#include <linux/clk/tegra.h>
+#include <linux/reset.h>
 #include <linux/err.h>
 
 #define KBC_MAX_KPENT	8
@@ -116,6 +116,7 @@ struct tegra_kbc {
 	u32 wakeup_key;
 	struct timer_list timer;
 	struct clk *clk;
+	struct reset_control *rst;
 	const struct tegra_kbc_hw_support *hw_support;
 	int max_keys;
 	int num_rows_and_columns;
@@ -373,9 +374,9 @@ static int tegra_kbc_start(struct tegra_kbc *kbc)
 	clk_prepare_enable(kbc->clk);
 
 	/* Reset the KBC controller to clear all previous status.*/
-	tegra_periph_reset_assert(kbc->clk);
+	reset_control_assert(kbc->rst);
 	udelay(100);
-	tegra_periph_reset_deassert(kbc->clk);
+	reset_control_assert(kbc->rst);
 	udelay(100);
 
 	tegra_kbc_config_pins(kbc);
@@ -663,6 +664,12 @@ static int tegra_kbc_probe(struct platform_device *pdev)
 		return PTR_ERR(kbc->clk);
 	}
 
+	kbc->rst = devm_reset_control_get(&pdev->dev, "kbc");
+	if (IS_ERR(kbc->rst)) {
+		dev_err(&pdev->dev, "failed to get keyboard reset\n");
+		return PTR_ERR(kbc->rst);
+	}
+
 	/*
 	 * The time delay between two consecutive reads of the FIFO is
 	 * the sum of the repeat time and the time taken for scanning
-- 
1.8.1.5

[PATCH 26/31] Input: tegra-kbc - use reset framework

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.

Cc: treding at nvidia.com
Cc: pdeschrijver at nvidia.com
Cc: linux-tegra at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Dmitry Torokhov <dtor@mail.ru>
Cc: linux-input at vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is part of a series with strong internal depdendencies. I'm
looking for an ack so that I can take the entire series through the Tegra
and arm-soc trees. The series will be part of a stable branch that can be
merged into other subsystems if needed to avoid/resolve dependencies.
---
 drivers/input/keyboard/tegra-kbc.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/input/keyboard/tegra-kbc.c b/drivers/input/keyboard/tegra-kbc.c
index 8508879f6faf..9757a58bc897 100644
--- a/drivers/input/keyboard/tegra-kbc.c
+++ b/drivers/input/keyboard/tegra-kbc.c
@@ -31,7 +31,7 @@
 #include <linux/clk.h>
 #include <linux/slab.h>
 #include <linux/input/matrix_keypad.h>
-#include <linux/clk/tegra.h>
+#include <linux/reset.h>
 #include <linux/err.h>
 
 #define KBC_MAX_KPENT	8
@@ -116,6 +116,7 @@ struct tegra_kbc {
 	u32 wakeup_key;
 	struct timer_list timer;
 	struct clk *clk;
+	struct reset_control *rst;
 	const struct tegra_kbc_hw_support *hw_support;
 	int max_keys;
 	int num_rows_and_columns;
@@ -373,9 +374,9 @@ static int tegra_kbc_start(struct tegra_kbc *kbc)
 	clk_prepare_enable(kbc->clk);
 
 	/* Reset the KBC controller to clear all previous status.*/
-	tegra_periph_reset_assert(kbc->clk);
+	reset_control_assert(kbc->rst);
 	udelay(100);
-	tegra_periph_reset_deassert(kbc->clk);
+	reset_control_assert(kbc->rst);
 	udelay(100);
 
 	tegra_kbc_config_pins(kbc);
@@ -663,6 +664,12 @@ static int tegra_kbc_probe(struct platform_device *pdev)
 		return PTR_ERR(kbc->clk);
 	}
 
+	kbc->rst = devm_reset_control_get(&pdev->dev, "kbc");
+	if (IS_ERR(kbc->rst)) {
+		dev_err(&pdev->dev, "failed to get keyboard reset\n");
+		return PTR_ERR(kbc->rst);
+	}
+
 	/*
 	 * The time delay between two consecutive reads of the FIFO is
 	 * the sum of the repeat time and the time taken for scanning
-- 
1.8.1.5

Re: [PATCH 26/31] Input: tegra-kbc - use reset framework

[Dmitry Torokhov]

On Fri, Nov 15, 2013 at 01:54:21PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding@nvidia.com
> Cc: pdeschrijver@nvidia.com
> Cc: linux-tegra@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
> Cc: Dmitry Torokhov <dtor@mail.ru>
> Cc: linux-input@vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>

Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>

> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/input/keyboard/tegra-kbc.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/input/keyboard/tegra-kbc.c b/drivers/input/keyboard/tegra-kbc.c
> index 8508879f6faf..9757a58bc897 100644
> --- a/drivers/input/keyboard/tegra-kbc.c
> +++ b/drivers/input/keyboard/tegra-kbc.c
> @@ -31,7 +31,7 @@
>  #include <linux/clk.h>
>  #include <linux/slab.h>
>  #include <linux/input/matrix_keypad.h>
> -#include <linux/clk/tegra.h>
> +#include <linux/reset.h>
>  #include <linux/err.h>
>  
>  #define KBC_MAX_KPENT	8
> @@ -116,6 +116,7 @@ struct tegra_kbc {
>  	u32 wakeup_key;
>  	struct timer_list timer;
>  	struct clk *clk;
> +	struct reset_control *rst;
>  	const struct tegra_kbc_hw_support *hw_support;
>  	int max_keys;
>  	int num_rows_and_columns;
> @@ -373,9 +374,9 @@ static int tegra_kbc_start(struct tegra_kbc *kbc)
>  	clk_prepare_enable(kbc->clk);
>  
>  	/* Reset the KBC controller to clear all previous status.*/
> -	tegra_periph_reset_assert(kbc->clk);
> +	reset_control_assert(kbc->rst);
>  	udelay(100);
> -	tegra_periph_reset_deassert(kbc->clk);
> +	reset_control_assert(kbc->rst);
>  	udelay(100);
>  
>  	tegra_kbc_config_pins(kbc);
> @@ -663,6 +664,12 @@ static int tegra_kbc_probe(struct platform_device *pdev)
>  		return PTR_ERR(kbc->clk);
>  	}
>  
> +	kbc->rst = devm_reset_control_get(&pdev->dev, "kbc");
> +	if (IS_ERR(kbc->rst)) {
> +		dev_err(&pdev->dev, "failed to get keyboard reset\n");
> +		return PTR_ERR(kbc->rst);
> +	}
> +
>  	/*
>  	 * The time delay between two consecutive reads of the FIFO is
>  	 * the sum of the repeat time and the time taken for scanning
> -- 
> 1.8.1.5
> 

-- 
Dmitry

[PATCH 26/31] Input: tegra-kbc - use reset framework

[Dmitry Torokhov]

On Fri, Nov 15, 2013 at 01:54:21PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
> Cc: Dmitry Torokhov <dtor@mail.ru>
> Cc: linux-input at vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>

Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>

> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/input/keyboard/tegra-kbc.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/input/keyboard/tegra-kbc.c b/drivers/input/keyboard/tegra-kbc.c
> index 8508879f6faf..9757a58bc897 100644
> --- a/drivers/input/keyboard/tegra-kbc.c
> +++ b/drivers/input/keyboard/tegra-kbc.c
> @@ -31,7 +31,7 @@
>  #include <linux/clk.h>
>  #include <linux/slab.h>
>  #include <linux/input/matrix_keypad.h>
> -#include <linux/clk/tegra.h>
> +#include <linux/reset.h>
>  #include <linux/err.h>
>  
>  #define KBC_MAX_KPENT	8
> @@ -116,6 +116,7 @@ struct tegra_kbc {
>  	u32 wakeup_key;
>  	struct timer_list timer;
>  	struct clk *clk;
> +	struct reset_control *rst;
>  	const struct tegra_kbc_hw_support *hw_support;
>  	int max_keys;
>  	int num_rows_and_columns;
> @@ -373,9 +374,9 @@ static int tegra_kbc_start(struct tegra_kbc *kbc)
>  	clk_prepare_enable(kbc->clk);
>  
>  	/* Reset the KBC controller to clear all previous status.*/
> -	tegra_periph_reset_assert(kbc->clk);
> +	reset_control_assert(kbc->rst);
>  	udelay(100);
> -	tegra_periph_reset_deassert(kbc->clk);
> +	reset_control_assert(kbc->rst);
>  	udelay(100);
>  
>  	tegra_kbc_config_pins(kbc);
> @@ -663,6 +664,12 @@ static int tegra_kbc_probe(struct platform_device *pdev)
>  		return PTR_ERR(kbc->clk);
>  	}
>  
> +	kbc->rst = devm_reset_control_get(&pdev->dev, "kbc");
> +	if (IS_ERR(kbc->rst)) {
> +		dev_err(&pdev->dev, "failed to get keyboard reset\n");
> +		return PTR_ERR(kbc->rst);
> +	}
> +
>  	/*
>  	 * The time delay between two consecutive reads of the FIFO is
>  	 * the sum of the repeat time and the time taken for scanning
> -- 
> 1.8.1.5
> 

-- 
Dmitry

Re: [PATCH 26/31] Input: tegra-kbc - use reset framework

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1370 bytes --]

On Fri, Nov 15, 2013 at 01:54:21PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
> Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: Dmitry Torokhov <dmitry.torokhov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Dmitry Torokhov <dtor-JGs/UdohzUI@public.gmane.org>
> Cc: linux-input-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/input/keyboard/tegra-kbc.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)

Reviewed-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]

[PATCH 26/31] Input: tegra-kbc - use reset framework

[Thierry Reding]

On Fri, Nov 15, 2013 at 01:54:21PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock driver now provides an implementation of the common
> reset API (include/linux/reset.h). Use this instead of the old Tegra-
> specific API; that will soon be removed.
> 
> Cc: treding at nvidia.com
> Cc: pdeschrijver at nvidia.com
> Cc: linux-tegra at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
> Cc: Dmitry Torokhov <dtor@mail.ru>
> Cc: linux-input at vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is part of a series with strong internal depdendencies. I'm
> looking for an ack so that I can take the entire series through the Tegra
> and arm-soc trees. The series will be part of a stable branch that can be
> merged into other subsystems if needed to avoid/resolve dependencies.
> ---
>  drivers/input/keyboard/tegra-kbc.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)

Reviewed-by: Thierry Reding <treding@nvidia.com>
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Re: [PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Terje Bergström]

On 15.11.2013 22:53, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> This series implements a common reset framework driver for Tegra, and
> updates all relevant Tegra drivers to use it. It also removes the custom
> DMA bindings and replaced them with the standard DMA DT bindings.
> 
> Historically, the Tegra clock driver has exported a custom API for module
> reset. This series removes that API, and transitions DT and drivers to
> the new reset framework.
> 
> The custom API used a "struct clk" to identify which module to reset, and
> consequently some DT bindings and drivers required clocks to be provided
> where they really needed just a reset identifier instead. Due to this
> known deficiency, I have always considered most Tegra bindings to be
> unstable. This series removes this excuse for instability, although I
> still consider some Tegra bindings unstable due to the need to convert to
> the common DMA bindings.
> 
> Historically, Tegra DMA channels have been represented in DT using a
> custom nvidia,dma-request-selector property. Now that standard DMA DT
> bindings exist, convert all Tegra bindings, DTs, and drivers to use the
> standard instead.
> 
> This series makes a DT-ABI-incompatible change to:
> - Require reset specifiers in DT where relevant.
> - Require standard DMA specifiers.
> - Remove clock specifiers from DT where they were only needed for reset.
> - Remove legacy DMA specifier properties.
> 
> I anticipate merging this whole series into the Tegra and arm-soc trees
> as its own branch, due to internal dependencies. This branch will be
> stable and can then be merged into any other subsystem trees should any
> conflicts arise.
> 
> This series depends on Peter's Tegra clock driver rework, available at
> git://nv-tegra.nvidia.com/user/pdeschrijver/linux tegra-clk-tegra124-0
> (or whatever version of that gets included in 3.14)

Overall, a good change. For host1x part:

Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>

This patch does not change the behavior, but we have in original code
the problem that we don't flush the MC queue when resetting an engine.
This can cause some memory writes to not hit memory. There was an
earlier discussion on that, but we seem to have lost track of the issue.

Terje

[PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Terje Bergström]

On 15.11.2013 22:53, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> This series implements a common reset framework driver for Tegra, and
> updates all relevant Tegra drivers to use it. It also removes the custom
> DMA bindings and replaced them with the standard DMA DT bindings.
> 
> Historically, the Tegra clock driver has exported a custom API for module
> reset. This series removes that API, and transitions DT and drivers to
> the new reset framework.
> 
> The custom API used a "struct clk" to identify which module to reset, and
> consequently some DT bindings and drivers required clocks to be provided
> where they really needed just a reset identifier instead. Due to this
> known deficiency, I have always considered most Tegra bindings to be
> unstable. This series removes this excuse for instability, although I
> still consider some Tegra bindings unstable due to the need to convert to
> the common DMA bindings.
> 
> Historically, Tegra DMA channels have been represented in DT using a
> custom nvidia,dma-request-selector property. Now that standard DMA DT
> bindings exist, convert all Tegra bindings, DTs, and drivers to use the
> standard instead.
> 
> This series makes a DT-ABI-incompatible change to:
> - Require reset specifiers in DT where relevant.
> - Require standard DMA specifiers.
> - Remove clock specifiers from DT where they were only needed for reset.
> - Remove legacy DMA specifier properties.
> 
> I anticipate merging this whole series into the Tegra and arm-soc trees
> as its own branch, due to internal dependencies. This branch will be
> stable and can then be merged into any other subsystem trees should any
> conflicts arise.
> 
> This series depends on Peter's Tegra clock driver rework, available at
> git://nv-tegra.nvidia.com/user/pdeschrijver/linux tegra-clk-tegra124-0
> (or whatever version of that gets included in 3.14)

Overall, a good change. For host1x part:

Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>

This patch does not change the behavior, but we have in original code
the problem that we don't flush the MC queue when resetting an engine.
This can cause some memory writes to not hit memory. There was an
earlier discussion on that, but we seem to have lost track of the issue.

Terje

Re: [PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Arnd Bergmann]

On Friday 15 November 2013, Stephen Warren wrote:
> This series implements a common reset framework driver for Tegra, and
> updates all relevant Tegra drivers to use it. It also removes the custom
> DMA bindings and replaced them with the standard DMA DT bindings.

The series is rather long, so I may have missed it, but I think you need one
more patch to the apbdma binding to document the use of #dma-cells, what
value it has, and what the format of the dma specifiers in slave drivers
needs to be.

	Arnd

[PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Arnd Bergmann]

On Friday 15 November 2013, Stephen Warren wrote:
> This series implements a common reset framework driver for Tegra, and
> updates all relevant Tegra drivers to use it. It also removes the custom
> DMA bindings and replaced them with the standard DMA DT bindings.

The series is rather long, so I may have missed it, but I think you need one
more patch to the apbdma binding to document the use of #dma-cells, what
value it has, and what the format of the dma specifiers in slave drivers
needs to be.

	Arnd

Re: [PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Arnd Bergmann]

On Friday 15 November 2013, Stephen Warren wrote:
> This series implements a common reset framework driver for Tegra, and
> updates all relevant Tegra drivers to use it. It also removes the custom
> DMA bindings and replaced them with the standard DMA DT bindings.

The series is rather long, so I may have missed it, but I think you need one
more patch to the apbdma binding to document the use of #dma-cells, what
value it has, and what the format of the dma specifiers in slave drivers
needs to be.

	Arnd

Re: [PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Stephen Warren]

On 11/20/2013 08:37 AM, Arnd Bergmann wrote:
> On Friday 15 November 2013, Stephen Warren wrote:
>> This series implements a common reset framework driver for Tegra, and
>> updates all relevant Tegra drivers to use it. It also removes the custom
>> DMA bindings and replaced them with the standard DMA DT bindings.
> 
> The series is rather long, so I may have missed it, but I think you need one
> more patch to the apbdma binding to document the use of #dma-cells, what
> value it has, and what the format of the dma specifiers in slave drivers
> needs to be.

Yes, you're right. I will fold the following into "ARM: tegra: document
use of standard DMA DT bindings":

> diff --git a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> index 0b1e577ab9d3..0b0f9498e265 100644
> --- a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> +++ b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> @@ -11,6 +11,10 @@ Required properties:
>    See ../reset/reset.txt for details.
>  - reset-names : Must include the following entries:
>    - dma
> +- #iommu-cells : Must be <1>. This dictates the length of DMA specifiers in
> +  client nodes' dmas properties. The specifier represents the DMA request
> +  select value for the peripheral. For more details, consult the Tegra TRM's
> +  documentation of the APB DMA channel control register REQ_SEL field.
>  
>  Examples:
>  
> @@ -36,4 +40,5 @@ apbdma: dma@6000a000 {
>  	clocks = <&tegra_car 34>;
>  	resets = <&tegra_car 34>;
>  	reset-names = "dma";
> +	#iommu-cells = <1>;
>  };

[PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Stephen Warren]

On 11/20/2013 08:37 AM, Arnd Bergmann wrote:
> On Friday 15 November 2013, Stephen Warren wrote:
>> This series implements a common reset framework driver for Tegra, and
>> updates all relevant Tegra drivers to use it. It also removes the custom
>> DMA bindings and replaced them with the standard DMA DT bindings.
> 
> The series is rather long, so I may have missed it, but I think you need one
> more patch to the apbdma binding to document the use of #dma-cells, what
> value it has, and what the format of the dma specifiers in slave drivers
> needs to be.

Yes, you're right. I will fold the following into "ARM: tegra: document
use of standard DMA DT bindings":

> diff --git a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> index 0b1e577ab9d3..0b0f9498e265 100644
> --- a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> +++ b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> @@ -11,6 +11,10 @@ Required properties:
>    See ../reset/reset.txt for details.
>  - reset-names : Must include the following entries:
>    - dma
> +- #iommu-cells : Must be <1>. This dictates the length of DMA specifiers in
> +  client nodes' dmas properties. The specifier represents the DMA request
> +  select value for the peripheral. For more details, consult the Tegra TRM's
> +  documentation of the APB DMA channel control register REQ_SEL field.
>  
>  Examples:
>  
> @@ -36,4 +40,5 @@ apbdma: dma at 6000a000 {
>  	clocks = <&tegra_car 34>;
>  	resets = <&tegra_car 34>;
>  	reset-names = "dma";
> +	#iommu-cells = <1>;
>  };

Re: [PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Arnd Bergmann]

On Wednesday 20 November 2013, Stephen Warren wrote:
> > +- #iommu-cells : Must be <1>. This dictates the length of DMA specifiers in
> > +  client nodes' dmas properties. The specifier represents the DMA request
> > +  select value for the peripheral. For more details, consult the Tegra TRM's
> > +  documentation of the APB DMA channel control register REQ_SEL field.
> >  
> >  Examples:
> >  
> > @@ -36,4 +40,5 @@ apbdma: dma@6000a000 {
> >       clocks = <&tegra_car 34>;
> >       resets = <&tegra_car 34>;
> >       reset-names = "dma";
> > +     #iommu-cells = <1>;


s/iommu/dma/

Otherwise looks good. The dts files are correct, so I guess it's just
a typo here.

	Arnd

[PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Arnd Bergmann]

On Wednesday 20 November 2013, Stephen Warren wrote:
> > +- #iommu-cells : Must be <1>. This dictates the length of DMA specifiers in
> > +  client nodes' dmas properties. The specifier represents the DMA request
> > +  select value for the peripheral. For more details, consult the Tegra TRM's
> > +  documentation of the APB DMA channel control register REQ_SEL field.
> >  
> >  Examples:
> >  
> > @@ -36,4 +40,5 @@ apbdma: dma at 6000a000 {
> >       clocks = <&tegra_car 34>;
> >       resets = <&tegra_car 34>;
> >       reset-names = "dma";
> > +     #iommu-cells = <1>;


s/iommu/dma/

Otherwise looks good. The dts files are correct, so I guess it's just
a typo here.

	Arnd

Re: [PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Stephen Warren]

On 11/20/2013 10:03 AM, Arnd Bergmann wrote:
> On Wednesday 20 November 2013, Stephen Warren wrote:
>>> +- #iommu-cells : Must be <1>. This dictates the length of DMA specifiers in
>>> +  client nodes' dmas properties. The specifier represents the DMA request
>>> +  select value for the peripheral. For more details, consult the Tegra TRM's
>>> +  documentation of the APB DMA channel control register REQ_SEL field.
>>>  
>>>  Examples:
>>>  
>>> @@ -36,4 +40,5 @@ apbdma: dma@6000a000 {
>>>       clocks = <&tegra_car 34>;
>>>       resets = <&tegra_car 34>;
>>>       reset-names = "dma";
>>> +     #iommu-cells = <1>;
> 
> 
> s/iommu/dma/
> 
> Otherwise looks good. The dts files are correct, so I guess it's just
> a typo here.

Thanks, fixed locally.

[PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Stephen Warren]

On 11/20/2013 10:03 AM, Arnd Bergmann wrote:
> On Wednesday 20 November 2013, Stephen Warren wrote:
>>> +- #iommu-cells : Must be <1>. This dictates the length of DMA specifiers in
>>> +  client nodes' dmas properties. The specifier represents the DMA request
>>> +  select value for the peripheral. For more details, consult the Tegra TRM's
>>> +  documentation of the APB DMA channel control register REQ_SEL field.
>>>  
>>>  Examples:
>>>  
>>> @@ -36,4 +40,5 @@ apbdma: dma at 6000a000 {
>>>       clocks = <&tegra_car 34>;
>>>       resets = <&tegra_car 34>;
>>>       reset-names = "dma";
>>> +     #iommu-cells = <1>;
> 
> 
> s/iommu/dma/
> 
> Otherwise looks good. The dts files are correct, so I guess it's just
> a typo here.

Thanks, fixed locally.

Re: [Ac100] [PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Martino Brandolini]

[-- Attachment #1.1: Type: text/plain, Size: 2260 bytes --]

Dear all,
My ac100 screen is flickering so much. I realized I'm not using it anymore.
So if anyone wants to have it for free would be for me a huge pleasure to
give it away. I'm based in milan and I'll be in London for the next week.
Maybe someone needs it.

Martino


2013/11/20 Stephen Warren <swarren@wwwdotorg.org>

> On 11/20/2013 08:37 AM, Arnd Bergmann wrote:
> > On Friday 15 November 2013, Stephen Warren wrote:
> >> This series implements a common reset framework driver for Tegra, and
> >> updates all relevant Tegra drivers to use it. It also removes the custom
> >> DMA bindings and replaced them with the standard DMA DT bindings.
> >
> > The series is rather long, so I may have missed it, but I think you need
> one
> > more patch to the apbdma binding to document the use of #dma-cells, what
> > value it has, and what the format of the dma specifiers in slave drivers
> > needs to be.
>
> Yes, you're right. I will fold the following into "ARM: tegra: document
> use of standard DMA DT bindings":
>
> > diff --git a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> > index 0b1e577ab9d3..0b0f9498e265 100644
> > --- a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> > +++ b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
> > @@ -11,6 +11,10 @@ Required properties:
> >    See ../reset/reset.txt for details.
> >  - reset-names : Must include the following entries:
> >    - dma
> > +- #iommu-cells : Must be <1>. This dictates the length of DMA
> specifiers in
> > +  client nodes' dmas properties. The specifier represents the DMA
> request
> > +  select value for the peripheral. For more details, consult the Tegra
> TRM's
> > +  documentation of the APB DMA channel control register REQ_SEL field.
> >
> >  Examples:
> >
> > @@ -36,4 +40,5 @@ apbdma: dma@6000a000 {
> >       clocks = <&tegra_car 34>;
> >       resets = <&tegra_car 34>;
> >       reset-names = "dma";
> > +     #iommu-cells = <1>;
> >  };
>
>
> _______________________________________________
> Mailing list: https://launchpad.net/~ac100
> Post to     : ac100@lists.launchpad.net
> Unsubscribe : https://launchpad.net/~ac100
> More help   : https://help.launchpad.net/ListHelp
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Re: [PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Stephen Warren]

On 11/15/2013 01:53 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> This series implements a common reset framework driver for Tegra, and
> updates all relevant Tegra drivers to use it. It also removes the custom
> DMA bindings and replaced them with the standard DMA DT bindings.
> 
> Historically, the Tegra clock driver has exported a custom API for module
> reset. This series removes that API, and transitions DT and drivers to
> the new reset framework.
> 
> The custom API used a "struct clk" to identify which module to reset, and
> consequently some DT bindings and drivers required clocks to be provided
> where they really needed just a reset identifier instead. Due to this
> known deficiency, I have always considered most Tegra bindings to be
> unstable. This series removes this excuse for instability, although I
> still consider some Tegra bindings unstable due to the need to convert to
> the common DMA bindings.
> 
> Historically, Tegra DMA channels have been represented in DT using a
> custom nvidia,dma-request-selector property. Now that standard DMA DT
> bindings exist, convert all Tegra bindings, DTs, and drivers to use the
> standard instead.
> 
> This series makes a DT-ABI-incompatible change to:
> - Require reset specifiers in DT where relevant.
> - Require standard DMA specifiers.
> - Remove clock specifiers from DT where they were only needed for reset.
> - Remove legacy DMA specifier properties.
> 
> I anticipate merging this whole series into the Tegra and arm-soc trees
> as its own branch, due to internal dependencies. This branch will be
> stable and can then be merged into any other subsystem trees should any
> conflicts arise.
> 
> This series depends on Peter's Tegra clock driver rework, available at
> git://nv-tegra.nvidia.com/user/pdeschrijver/linux tegra-clk-tegra124-0
> (or whatever version of that gets included in 3.14)

I've applied this series (and pulled in the DMA/ASoC/clk dependencies
required) to Tegra's for-3.14/dmas-resets-rework branch.

[PATCH 00/31] ARM: tegra: use common reset and DMA bindings

[Stephen Warren]

On 11/15/2013 01:53 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> This series implements a common reset framework driver for Tegra, and
> updates all relevant Tegra drivers to use it. It also removes the custom
> DMA bindings and replaced them with the standard DMA DT bindings.
> 
> Historically, the Tegra clock driver has exported a custom API for module
> reset. This series removes that API, and transitions DT and drivers to
> the new reset framework.
> 
> The custom API used a "struct clk" to identify which module to reset, and
> consequently some DT bindings and drivers required clocks to be provided
> where they really needed just a reset identifier instead. Due to this
> known deficiency, I have always considered most Tegra bindings to be
> unstable. This series removes this excuse for instability, although I
> still consider some Tegra bindings unstable due to the need to convert to
> the common DMA bindings.
> 
> Historically, Tegra DMA channels have been represented in DT using a
> custom nvidia,dma-request-selector property. Now that standard DMA DT
> bindings exist, convert all Tegra bindings, DTs, and drivers to use the
> standard instead.
> 
> This series makes a DT-ABI-incompatible change to:
> - Require reset specifiers in DT where relevant.
> - Require standard DMA specifiers.
> - Remove clock specifiers from DT where they were only needed for reset.
> - Remove legacy DMA specifier properties.
> 
> I anticipate merging this whole series into the Tegra and arm-soc trees
> as its own branch, due to internal dependencies. This branch will be
> stable and can then be merged into any other subsystem trees should any
> conflicts arise.
> 
> This series depends on Peter's Tegra clock driver rework, available at
> git://nv-tegra.nvidia.com/user/pdeschrijver/linux tegra-clk-tegra124-0
> (or whatever version of that gets included in 3.14)

I've applied this series (and pulled in the DMA/ASoC/clk dependencies
required) to Tegra's for-3.14/dmas-resets-rework branch.