* [PATCH v4] imx: add i.MX8MN DDR3L evk board support @ 2022-06-13 21:10 Heiko Thiery 2022-06-14 1:47 ` Peng Fan (OSS) 2022-06-14 6:55 ` Michael Nazzareno Trimarchi 0 siblings, 2 replies; 15+ messages in thread From: Heiko Thiery @ 2022-06-13 21:10 UTC (permalink / raw) To: u-boot Cc: Ying-Chun Liu, Peng Fan, Fabio Estevam, Heiko Thiery, Marek Vasut, Marcel Ziswiler, Tim Harvey, Sean Anderson, Thomas Schäfer, Stefano Babic, Fabio Estevam Add the support for the 8MNANOD3L-EVK board. The board has an i.MX8MNano UltraLite Quad SoC and uses 1GB DDR3L memory. U-Boot SPL 2022.07-rc4-00017-gcf594ebce1 (Jun 13 2022 - 22:40:31 +0200) Normal Boot WDT: Started watchdog@30280000 with servicing (60s timeout) Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 NOTICE: BL31: v2.6(release):v2.6-5-g9b1a4d832 NOTICE: BL31: Built : 14:03:53, May 10 2022 U-Boot 2022.07-rc4-00017-gcf594ebce1 (Jun 13 2022 - 22:40:31 +0200) CPU: Freescale i.MX8MNano UltraLite Quad rev1.0 at 1200 MHz Reset cause: WDOG Model: NXP i.MX8MNano DDR3L EVK board DRAM: 1 GiB Core: 142 devices, 19 uclasses, devicetree: separate WDT: Started watchdog@30280000 with servicing (60s timeout) MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial@30890000 Out: serial@30890000 Err: serial@30890000 Net: eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de> --- v4: - rebase on current master to fix merge conflicts - remove config options from defconfig - enable SPL_DM_SERIAL - include imx8mn-ddr4-evk-u-boot.dtsi in imx8mn-ddr3l-evk-u-boot.dtsi v3: - fix config option description in Kconfig (TARGET_IMX8MN_DDR3L_EVK) v2: - change license formatting (thanks Marcel) arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi | 34 + arch/arm/dts/imx8mn-ddr3l-evk.dts | 114 +++ arch/arm/dts/imx8mn-u-boot.dtsi | 12 + arch/arm/mach-imx/imx8m/Kconfig | 7 + board/freescale/imx8mn_evk/Kconfig | 2 +- board/freescale/imx8mn_evk/Makefile | 1 + board/freescale/imx8mn_evk/ddr3l_timing.c | 943 ++++++++++++++++++++++ board/freescale/imx8mn_evk/spl.c | 9 + configs/imx8mn_ddr3l_evk_defconfig | 95 +++ include/configs/imx8mn_evk.h | 4 + 10 files changed, 1220 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-ddr3l-evk.dts create mode 100644 board/freescale/imx8mn_evk/ddr3l_timing.c create mode 100644 configs/imx8mn_ddr3l_evk_defconfig diff --git a/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi new file mode 100644 index 0000000000..b9192515e5 --- /dev/null +++ b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "imx8mn-u-boot.dtsi" +#include "imx8mn-ddr4-evk-u-boot.dtsi" + + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; + u-boot,dm-pre-reloc; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + u-boot,dm-spl; +}; + +&wdog1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mn-ddr3l-evk.dts b/arch/arm/dts/imx8mn-ddr3l-evk.dts new file mode 100644 index 0000000000..4cdc03c8f2 --- /dev/null +++ b/arch/arm/dts/imx8mn-ddr3l-evk.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; + +#include "imx8mn.dtsi" +#include "imx8mn-evk.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "NXP i.MX8MNano DDR3L EVK board"; + compatible = "fsl,imx8mn-ddr3l-evk", "fsl,imx8mn"; +}; + +&A53_0 { + cpu-supply = <&buck1>; +}; + +&A53_1 { + cpu-supply = <&buck1>; +}; + +&A53_2 { + cpu-supply = <&buck1>; +}; + +&A53_3 { + cpu-supply = <&buck1>; +}; + +&i2c1 { + pmic: pmic@25 { + compatible = "nxp,pca9450b"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "VDD_SOC_0V9"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "NVCC_DRAM_1V35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "NVCC_SNVS_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "VDD_SNVS_0V8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "VDD_PHY_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "NVCC_SD2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index 7b591085a0..9286bdace0 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -151,6 +151,18 @@ size = <0x4000>; }; }; +#elif CONFIG_IMX8M_DDR3L +&u_boot_spl_ddr { + blob_1: blob-ext@1 { + filename = "ddr3_imem_1d.bin"; + size = <0x8000>; + }; + + blob_2: blob-ext@2 { + filename = "ddr3_dmem_1d.bin"; + size = <0x4000>; + }; +}; #else #error "no valid ddr config selected" #endif diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index ef8518c06b..aa386c8f36 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -140,6 +140,13 @@ config TARGET_IMX8MN_DDR4_EVK select FSL_CAAM select SPL_CRYPTO if SPL +config TARGET_IMX8MN_DDR3L_EVK + bool "imx8mn DDR3L EVK board" + select BINMAN + select IMX8MN + select SUPPORT_SPL + select IMX8M_DDR3L + config TARGET_IMX8MN_VENICE bool "Support Gateworks Venice iMX8M Nano module" select BINMAN diff --git a/board/freescale/imx8mn_evk/Kconfig b/board/freescale/imx8mn_evk/Kconfig index 6596fb5c6d..38312a3662 100644 --- a/board/freescale/imx8mn_evk/Kconfig +++ b/board/freescale/imx8mn_evk/Kconfig @@ -1,4 +1,4 @@ -if TARGET_IMX8MN_EVK || TARGET_IMX8MN_DDR4_EVK +if TARGET_IMX8MN_EVK || TARGET_IMX8MN_DDR4_EVK || TARGET_IMX8MN_DDR3L_EVK config SYS_BOARD default "imx8mn_evk" diff --git a/board/freescale/imx8mn_evk/Makefile b/board/freescale/imx8mn_evk/Makefile index 42d1179724..ad3ef8edd6 100644 --- a/board/freescale/imx8mn_evk/Makefile +++ b/board/freescale/imx8mn_evk/Makefile @@ -14,5 +14,6 @@ obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing_ld.o else obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o +obj-$(CONFIG_IMX8M_DDR3L) += ddr3l_timing.o endif endif diff --git a/board/freescale/imx8mn_evk/ddr3l_timing.c b/board/freescale/imx8mn_evk/ddr3l_timing.c new file mode 100644 index 0000000000..0fe1f6a42d --- /dev/null +++ b/board/freescale/imx8mn_evk/ddr3l_timing.c @@ -0,0 +1,943 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2019 NXP + * + * Generated code from MX8M_DDR_tool + * + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga + * For imx_v2019.04_5.4.x and above version: + * please replace #include <asm/arch/imx8m_ddr.h> with #include <asm/arch/ddr.h> + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x20 }, + { 0x3d400000, 0xa1040001 }, + { 0x3d400064, 0x61008c }, + { 0x3d4000d0, 0xc00200c5 }, + { 0x3d4000d4, 0x1000b }, + { 0x3d4000dc, 0x1d700004 }, + { 0x3d4000e0, 0x180000 }, + { 0x3d4000e4, 0x90000 }, + { 0x3d4000f0, 0x0 }, + { 0x3d4000f4, 0xee5 }, + { 0x3d400100, 0xc101b0e }, + { 0x3d400104, 0x30314 }, + { 0x3d400108, 0x4060509 }, + { 0x3d40010c, 0x2006 }, + { 0x3d400110, 0x6020306 }, + { 0x3d400114, 0x4040302 }, + { 0x3d400120, 0x909 }, + { 0x3d400180, 0x40800020 }, + { 0x3d400184, 0xc350 }, + { 0x3d400190, 0x3868203 }, + { 0x3d400194, 0x20303 }, + { 0x3d4001b4, 0x603 }, + { 0x3d400198, 0x7000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001a0, 0x400018 }, + { 0x3d4001a4, 0x5003c }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001c4, 0x0 }, + { 0x3d400200, 0x1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400208, 0x0 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d400240, 0x600060c }, + { 0x3d400244, 0x1323 }, + { 0x3d400400, 0x100 }, + { 0x3d400250, 0x7ab50b07 }, + { 0x3d400254, 0x22 }, + { 0x3d40025c, 0x7b00665e }, + { 0x3d400264, 0xb0000040 }, + { 0x3d40026c, 0x50000a0c }, + { 0x3d400300, 0x17 }, + { 0x3d40036c, 0x10000 }, + { 0x3d400404, 0x3051 }, + { 0x3d400408, 0x61d2 }, + { 0x3d400494, 0xe00 }, + { 0x3d400498, 0x7ff }, + { 0x3d40049c, 0xe00 }, + { 0x3d4004a0, 0x7ff }, + { 0x3d402064, 0x28003b }, + { 0x3d4020dc, 0x12200004 }, + { 0x3d4020e0, 0x0 }, + { 0x3d402100, 0x7090b07 }, + { 0x3d402104, 0x20209 }, + { 0x3d402108, 0x3030407 }, + { 0x3d40210c, 0x2006 }, + { 0x3d402110, 0x3020203 }, + { 0x3d402114, 0x3030202 }, + { 0x3d402120, 0x909 }, + { 0x3d402180, 0x40800020 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x20303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d402240, 0x6000604 }, + { 0x3d4020f4, 0xee5 }, + { 0x3d400028, 0x1 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x1005f, 0x3ff }, + { 0x1015f, 0x3ff }, + { 0x1105f, 0x3ff }, + { 0x1115f, 0x3ff }, + { 0x11005f, 0x3ff }, + { 0x11015f, 0x3ff }, + { 0x11105f, 0x3ff }, + { 0x11115f, 0x3ff }, + { 0x55, 0x3ff }, + { 0x1055, 0x3ff }, + { 0x2055, 0x3ff }, + { 0x3055, 0x3ff }, + { 0x4055, 0xff }, + { 0x5055, 0xff }, + { 0x6055, 0x3ff }, + { 0x7055, 0x3ff }, + { 0x8055, 0x3ff }, + { 0x9055, 0x3ff }, + { 0x200c5, 0xb }, + { 0x1200c5, 0x7 }, + { 0x2002e, 0x1 }, + { 0x12002e, 0x1 }, + { 0x20024, 0x0 }, + { 0x2003a, 0x0 }, + { 0x120024, 0x0 }, + { 0x2003a, 0x0 }, + { 0x20056, 0xa }, + { 0x120056, 0xa }, + { 0x1004d, 0x208 }, + { 0x1014d, 0x208 }, + { 0x1104d, 0x208 }, + { 0x1114d, 0x208 }, + { 0x11004d, 0x208 }, + { 0x11014d, 0x208 }, + { 0x11104d, 0x208 }, + { 0x11114d, 0x208 }, + { 0x10049, 0xe38 }, + { 0x10149, 0xe38 }, + { 0x11049, 0xe38 }, + { 0x11149, 0xe38 }, + { 0x110049, 0xe38 }, + { 0x110149, 0xe38 }, + { 0x111049, 0xe38 }, + { 0x111149, 0xe38 }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x1 }, + { 0x20075, 0x0 }, + { 0x20050, 0x0 }, + { 0x20008, 0x190 }, + { 0x120008, 0xa7 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x32c }, + { 0x10043, 0x581 }, + { 0x10143, 0x581 }, + { 0x11043, 0x581 }, + { 0x11143, 0x581 }, + { 0x1200b2, 0x32c }, + { 0x110043, 0x581 }, + { 0x110143, 0x581 }, + { 0x111043, 0x581 }, + { 0x111143, 0x581 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x20019, 0x5 }, + { 0x120019, 0x5 }, + { 0x200f0, 0x5555 }, + { 0x200f1, 0x5555 }, + { 0x200f2, 0x5555 }, + { 0x200f3, 0x5555 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x5555 }, + { 0x200f6, 0x5555 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x0200b2,0x0}, + {0x1200b2,0x0}, + {0x2200b2,0x0}, + {0x0200cb,0x0}, + {0x010043,0x0}, + {0x110043,0x0}, + {0x210043,0x0}, + {0x010143,0x0}, + {0x110143,0x0}, + {0x210143,0x0}, + {0x011043,0x0}, + {0x111043,0x0}, + {0x211043,0x0}, + {0x011143,0x0}, + {0x111143,0x0}, + {0x211143,0x0}, + {0x000080,0x0}, + {0x100080,0x0}, + {0x200080,0x0}, + {0x001080,0x0}, + {0x101080,0x0}, + {0x201080,0x0}, + {0x002080,0x0}, + {0x102080,0x0}, + {0x202080,0x0}, + {0x003080,0x0}, + {0x103080,0x0}, + {0x203080,0x0}, + {0x004080,0x0}, + {0x104080,0x0}, + {0x204080,0x0}, + {0x005080,0x0}, + {0x105080,0x0}, + {0x205080,0x0}, + {0x006080,0x0}, + {0x106080,0x0}, + {0x206080,0x0}, + {0x007080,0x0}, + {0x107080,0x0}, + {0x207080,0x0}, + {0x008080,0x0}, + {0x108080,0x0}, + {0x208080,0x0}, + {0x009080,0x0}, + {0x109080,0x0}, + {0x209080,0x0}, + {0x010080,0x0}, + {0x110080,0x0}, + {0x210080,0x0}, + {0x010180,0x0}, + {0x110180,0x0}, + {0x210180,0x0}, + {0x010081,0x0}, + {0x110081,0x0}, + {0x210081,0x0}, + {0x010181,0x0}, + {0x110181,0x0}, + {0x210181,0x0}, + {0x010082,0x0}, + {0x110082,0x0}, + {0x210082,0x0}, + {0x010182,0x0}, + {0x110182,0x0}, + {0x210182,0x0}, + {0x010083,0x0}, + {0x110083,0x0}, + {0x210083,0x0}, + {0x010183,0x0}, + {0x110183,0x0}, + {0x210183,0x0}, + {0x011080,0x0}, + {0x111080,0x0}, + {0x211080,0x0}, + {0x011180,0x0}, + {0x111180,0x0}, + {0x211180,0x0}, + {0x011081,0x0}, + {0x111081,0x0}, + {0x211081,0x0}, + {0x011181,0x0}, + {0x111181,0x0}, + {0x211181,0x0}, + {0x011082,0x0}, + {0x111082,0x0}, + {0x211082,0x0}, + {0x011182,0x0}, + {0x111182,0x0}, + {0x211182,0x0}, + {0x011083,0x0}, + {0x111083,0x0}, + {0x211083,0x0}, + {0x011183,0x0}, + {0x111183,0x0}, + {0x211183,0x0}, + {0x0100d0,0x0}, + {0x1100d0,0x0}, + {0x2100d0,0x0}, + {0x0101d0,0x0}, + {0x1101d0,0x0}, + {0x2101d0,0x0}, + {0x0100d1,0x0}, + {0x1100d1,0x0}, + {0x2100d1,0x0}, + {0x0101d1,0x0}, + {0x1101d1,0x0}, + {0x2101d1,0x0}, + {0x0100d2,0x0}, + {0x1100d2,0x0}, + {0x2100d2,0x0}, + {0x0101d2,0x0}, + {0x1101d2,0x0}, + {0x2101d2,0x0}, + {0x0100d3,0x0}, + {0x1100d3,0x0}, + {0x2100d3,0x0}, + {0x0101d3,0x0}, + {0x1101d3,0x0}, + {0x2101d3,0x0}, + {0x0110d0,0x0}, + {0x1110d0,0x0}, + {0x2110d0,0x0}, + {0x0111d0,0x0}, + {0x1111d0,0x0}, + {0x2111d0,0x0}, + {0x0110d1,0x0}, + {0x1110d1,0x0}, + {0x2110d1,0x0}, + {0x0111d1,0x0}, + {0x1111d1,0x0}, + {0x2111d1,0x0}, + {0x0110d2,0x0}, + {0x1110d2,0x0}, + {0x2110d2,0x0}, + {0x0111d2,0x0}, + {0x1111d2,0x0}, + {0x2111d2,0x0}, + {0x0110d3,0x0}, + {0x1110d3,0x0}, + {0x2110d3,0x0}, + {0x0111d3,0x0}, + {0x1111d3,0x0}, + {0x2111d3,0x0}, + {0x010068,0x0}, + {0x010168,0x0}, + {0x010268,0x0}, + {0x010368,0x0}, + {0x010468,0x0}, + {0x010568,0x0}, + {0x010668,0x0}, + {0x010768,0x0}, + {0x010868,0x0}, + {0x010069,0x0}, + {0x010169,0x0}, + {0x010269,0x0}, + {0x010369,0x0}, + {0x010469,0x0}, + {0x010569,0x0}, + {0x010669,0x0}, + {0x010769,0x0}, + {0x010869,0x0}, + {0x01006a,0x0}, + {0x01016a,0x0}, + {0x01026a,0x0}, + {0x01036a,0x0}, + {0x01046a,0x0}, + {0x01056a,0x0}, + {0x01066a,0x0}, + {0x01076a,0x0}, + {0x01086a,0x0}, + {0x01006b,0x0}, + {0x01016b,0x0}, + {0x01026b,0x0}, + {0x01036b,0x0}, + {0x01046b,0x0}, + {0x01056b,0x0}, + {0x01066b,0x0}, + {0x01076b,0x0}, + {0x01086b,0x0}, + {0x011068,0x0}, + {0x011168,0x0}, + {0x011268,0x0}, + {0x011368,0x0}, + {0x011468,0x0}, + {0x011568,0x0}, + {0x011668,0x0}, + {0x011768,0x0}, + {0x011868,0x0}, + {0x011069,0x0}, + {0x011169,0x0}, + {0x011269,0x0}, + {0x011369,0x0}, + {0x011469,0x0}, + {0x011569,0x0}, + {0x011669,0x0}, + {0x011769,0x0}, + {0x011869,0x0}, + {0x01106a,0x0}, + {0x01116a,0x0}, + {0x01126a,0x0}, + {0x01136a,0x0}, + {0x01146a,0x0}, + {0x01156a,0x0}, + {0x01166a,0x0}, + {0x01176a,0x0}, + {0x01186a,0x0}, + {0x01106b,0x0}, + {0x01116b,0x0}, + {0x01126b,0x0}, + {0x01136b,0x0}, + {0x01146b,0x0}, + {0x01156b,0x0}, + {0x01166b,0x0}, + {0x01176b,0x0}, + {0x01186b,0x0}, + {0x01008c,0x0}, + {0x11008c,0x0}, + {0x21008c,0x0}, + {0x01018c,0x0}, + {0x11018c,0x0}, + {0x21018c,0x0}, + {0x01008d,0x0}, + {0x11008d,0x0}, + {0x21008d,0x0}, + {0x01018d,0x0}, + {0x11018d,0x0}, + {0x21018d,0x0}, + {0x01008e,0x0}, + {0x11008e,0x0}, + {0x21008e,0x0}, + {0x01018e,0x0}, + {0x11018e,0x0}, + {0x21018e,0x0}, + {0x01008f,0x0}, + {0x11008f,0x0}, + {0x21008f,0x0}, + {0x01018f,0x0}, + {0x11018f,0x0}, + {0x21018f,0x0}, + {0x01108c,0x0}, + {0x11108c,0x0}, + {0x21108c,0x0}, + {0x01118c,0x0}, + {0x11118c,0x0}, + {0x21118c,0x0}, + {0x01108d,0x0}, + {0x11108d,0x0}, + {0x21108d,0x0}, + {0x01118d,0x0}, + {0x11118d,0x0}, + {0x21118d,0x0}, + {0x01108e,0x0}, + {0x11108e,0x0}, + {0x21108e,0x0}, + {0x01118e,0x0}, + {0x11118e,0x0}, + {0x21118e,0x0}, + {0x01108f,0x0}, + {0x11108f,0x0}, + {0x21108f,0x0}, + {0x01118f,0x0}, + {0x11118f,0x0}, + {0x21118f,0x0}, + {0x0100c0,0x0}, + {0x1100c0,0x0}, + {0x2100c0,0x0}, + {0x0101c0,0x0}, + {0x1101c0,0x0}, + {0x2101c0,0x0}, + {0x0102c0,0x0}, + {0x1102c0,0x0}, + {0x2102c0,0x0}, + {0x0103c0,0x0}, + {0x1103c0,0x0}, + {0x2103c0,0x0}, + {0x0104c0,0x0}, + {0x1104c0,0x0}, + {0x2104c0,0x0}, + {0x0105c0,0x0}, + {0x1105c0,0x0}, + {0x2105c0,0x0}, + {0x0106c0,0x0}, + {0x1106c0,0x0}, + {0x2106c0,0x0}, + {0x0107c0,0x0}, + {0x1107c0,0x0}, + {0x2107c0,0x0}, + {0x0108c0,0x0}, + {0x1108c0,0x0}, + {0x2108c0,0x0}, + {0x0100c1,0x0}, + {0x1100c1,0x0}, + {0x2100c1,0x0}, + {0x0101c1,0x0}, + {0x1101c1,0x0}, + {0x2101c1,0x0}, + {0x0102c1,0x0}, + {0x1102c1,0x0}, + {0x2102c1,0x0}, + {0x0103c1,0x0}, + {0x1103c1,0x0}, + {0x2103c1,0x0}, + {0x0104c1,0x0}, + {0x1104c1,0x0}, + {0x2104c1,0x0}, + {0x0105c1,0x0}, + {0x1105c1,0x0}, + {0x2105c1,0x0}, + {0x0106c1,0x0}, + {0x1106c1,0x0}, + {0x2106c1,0x0}, + {0x0107c1,0x0}, + {0x1107c1,0x0}, + {0x2107c1,0x0}, + {0x0108c1,0x0}, + {0x1108c1,0x0}, + {0x2108c1,0x0}, + {0x0100c2,0x0}, + {0x1100c2,0x0}, + {0x2100c2,0x0}, + {0x0101c2,0x0}, + {0x1101c2,0x0}, + {0x2101c2,0x0}, + {0x0102c2,0x0}, + {0x1102c2,0x0}, + {0x2102c2,0x0}, + {0x0103c2,0x0}, + {0x1103c2,0x0}, + {0x2103c2,0x0}, + {0x0104c2,0x0}, + {0x1104c2,0x0}, + {0x2104c2,0x0}, + {0x0105c2,0x0}, + {0x1105c2,0x0}, + {0x2105c2,0x0}, + {0x0106c2,0x0}, + {0x1106c2,0x0}, + {0x2106c2,0x0}, + {0x0107c2,0x0}, + {0x1107c2,0x0}, + {0x2107c2,0x0}, + {0x0108c2,0x0}, + {0x1108c2,0x0}, + {0x2108c2,0x0}, + {0x0100c3,0x0}, + {0x1100c3,0x0}, + {0x2100c3,0x0}, + {0x0101c3,0x0}, + {0x1101c3,0x0}, + {0x2101c3,0x0}, + {0x0102c3,0x0}, + {0x1102c3,0x0}, + {0x2102c3,0x0}, + {0x0103c3,0x0}, + {0x1103c3,0x0}, + {0x2103c3,0x0}, + {0x0104c3,0x0}, + {0x1104c3,0x0}, + {0x2104c3,0x0}, + {0x0105c3,0x0}, + {0x1105c3,0x0}, + {0x2105c3,0x0}, + {0x0106c3,0x0}, + {0x1106c3,0x0}, + {0x2106c3,0x0}, + {0x0107c3,0x0}, + {0x1107c3,0x0}, + {0x2107c3,0x0}, + {0x0108c3,0x0}, + {0x1108c3,0x0}, + {0x2108c3,0x0}, + {0x0110c0,0x0}, + {0x1110c0,0x0}, + {0x2110c0,0x0}, + {0x0111c0,0x0}, + {0x1111c0,0x0}, + {0x2111c0,0x0}, + {0x0112c0,0x0}, + {0x1112c0,0x0}, + {0x2112c0,0x0}, + {0x0113c0,0x0}, + {0x1113c0,0x0}, + {0x2113c0,0x0}, + {0x0114c0,0x0}, + {0x1114c0,0x0}, + {0x2114c0,0x0}, + {0x0115c0,0x0}, + {0x1115c0,0x0}, + {0x2115c0,0x0}, + {0x0116c0,0x0}, + {0x1116c0,0x0}, + {0x2116c0,0x0}, + {0x0117c0,0x0}, + {0x1117c0,0x0}, + {0x2117c0,0x0}, + {0x0118c0,0x0}, + {0x1118c0,0x0}, + {0x2118c0,0x0}, + {0x0110c1,0x0}, + {0x1110c1,0x0}, + {0x2110c1,0x0}, + {0x0111c1,0x0}, + {0x1111c1,0x0}, + {0x2111c1,0x0}, + {0x0112c1,0x0}, + {0x1112c1,0x0}, + {0x2112c1,0x0}, + {0x0113c1,0x0}, + {0x1113c1,0x0}, + {0x2113c1,0x0}, + {0x0114c1,0x0}, + {0x1114c1,0x0}, + {0x2114c1,0x0}, + {0x0115c1,0x0}, + {0x1115c1,0x0}, + {0x2115c1,0x0}, + {0x0116c1,0x0}, + {0x1116c1,0x0}, + {0x2116c1,0x0}, + {0x0117c1,0x0}, + {0x1117c1,0x0}, + {0x2117c1,0x0}, + {0x0118c1,0x0}, + {0x1118c1,0x0}, + {0x2118c1,0x0}, + {0x0110c2,0x0}, + {0x1110c2,0x0}, + {0x2110c2,0x0}, + {0x0111c2,0x0}, + {0x1111c2,0x0}, + {0x2111c2,0x0}, + {0x0112c2,0x0}, + {0x1112c2,0x0}, + {0x2112c2,0x0}, + {0x0113c2,0x0}, + {0x1113c2,0x0}, + {0x2113c2,0x0}, + {0x0114c2,0x0}, + {0x1114c2,0x0}, + {0x2114c2,0x0}, + {0x0115c2,0x0}, + {0x1115c2,0x0}, + {0x2115c2,0x0}, + {0x0116c2,0x0}, + {0x1116c2,0x0}, + {0x2116c2,0x0}, + {0x0117c2,0x0}, + {0x1117c2,0x0}, + {0x2117c2,0x0}, + {0x0118c2,0x0}, + {0x1118c2,0x0}, + {0x2118c2,0x0}, + {0x0110c3,0x0}, + {0x1110c3,0x0}, + {0x2110c3,0x0}, + {0x0111c3,0x0}, + {0x1111c3,0x0}, + {0x2111c3,0x0}, + {0x0112c3,0x0}, + {0x1112c3,0x0}, + {0x2112c3,0x0}, + {0x0113c3,0x0}, + {0x1113c3,0x0}, + {0x2113c3,0x0}, + {0x0114c3,0x0}, + {0x1114c3,0x0}, + {0x2114c3,0x0}, + {0x0115c3,0x0}, + {0x1115c3,0x0}, + {0x2115c3,0x0}, + {0x0116c3,0x0}, + {0x1116c3,0x0}, + {0x2116c3,0x0}, + {0x0117c3,0x0}, + {0x1117c3,0x0}, + {0x2117c3,0x0}, + {0x0118c3,0x0}, + {0x1118c3,0x0}, + {0x2118c3,0x0}, + {0x010020,0x0}, + {0x110020,0x0}, + {0x210020,0x0}, + {0x011020,0x0}, + {0x111020,0x0}, + {0x211020,0x0}, + {0x02007d,0x0}, + {0x12007d,0x0}, + {0x22007d,0x0}, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x283c }, + { 0x54006, 0x140 }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x1d70 }, + { 0x54030, 0x4 }, + { 0x54031, 0x18 }, + { 0x5403a, 0x1323 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x29c }, + { 0x54004, 0x2 }, + { 0x54005, 0x283c }, + { 0x54006, 0x140 }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x1220 }, + { 0x54030, 0x4 }, + { 0x5403a, 0x1323 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x2 }, + { 0x90033, 0x10 }, + { 0x90034, 0x139 }, + { 0x90035, 0xb }, + { 0x90036, 0x7c0 }, + { 0x90037, 0x139 }, + { 0x90038, 0x44 }, + { 0x90039, 0x633 }, + { 0x9003a, 0x159 }, + { 0x9003b, 0x14f }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x47 }, + { 0x9003f, 0x633 }, + { 0x90040, 0x149 }, + { 0x90041, 0x4f }, + { 0x90042, 0x633 }, + { 0x90043, 0x179 }, + { 0x90044, 0x8 }, + { 0x90045, 0xe0 }, + { 0x90046, 0x109 }, + { 0x90047, 0x0 }, + { 0x90048, 0x7c8 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x1 }, + { 0x9004c, 0x8 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x45a }, + { 0x9004f, 0x9 }, + { 0x90050, 0x0 }, + { 0x90051, 0x448 }, + { 0x90052, 0x109 }, + { 0x90053, 0x40 }, + { 0x90054, 0x633 }, + { 0x90055, 0x179 }, + { 0x90056, 0x1 }, + { 0x90057, 0x618 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40c0 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x149 }, + { 0x9005c, 0x8 }, + { 0x9005d, 0x4 }, + { 0x9005e, 0x48 }, + { 0x9005f, 0x4040 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x0 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x40 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x10 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x18 }, + { 0x9006b, 0x0 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x78 }, + { 0x9006e, 0x549 }, + { 0x9006f, 0x633 }, + { 0x90070, 0x159 }, + { 0x90071, 0xd49 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0x94a }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x441 }, + { 0x90078, 0x633 }, + { 0x90079, 0x149 }, + { 0x9007a, 0x42 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x1 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x0 }, + { 0x90081, 0xe0 }, + { 0x90082, 0x109 }, + { 0x90083, 0xa }, + { 0x90084, 0x10 }, + { 0x90085, 0x109 }, + { 0x90086, 0x9 }, + { 0x90087, 0x3c0 }, + { 0x90088, 0x149 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x159 }, + { 0x9008c, 0x18 }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x0 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x109 }, + { 0x90092, 0x18 }, + { 0x90093, 0x4 }, + { 0x90094, 0x48 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x58 }, + { 0x90098, 0xb }, + { 0x90099, 0x10 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x1 }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x5 }, + { 0x9009f, 0x7c0 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x0 }, + { 0x900a2, 0x8140 }, + { 0x900a3, 0x10c }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x8138 }, + { 0x900a6, 0x10c }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7c8 }, + { 0x900a9, 0x101 }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x448 }, + { 0x900ac, 0x109 }, + { 0x900ad, 0xf }, + { 0x900ae, 0x7c0 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x47 }, + { 0x900b1, 0x630 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x8 }, + { 0x900b4, 0x618 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0xe0 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x0 }, + { 0x900ba, 0x7c8 }, + { 0x900bb, 0x109 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x8140 }, + { 0x900be, 0x10c }, + { 0x900bf, 0x0 }, + { 0x900c0, 0x1 }, + { 0x900c1, 0x8 }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x8 }, + { 0x900c5, 0x8 }, + { 0x900c6, 0x7c8 }, + { 0x900c7, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x90026, 0x2b }, + { 0x2000b, 0x32 }, + { 0x2000c, 0x64 }, + { 0x2000d, 0x3e8 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x14 }, + { 0x12000c, 0x26 }, + { 0x12000d, 0x1a1 }, + { 0x12000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0xffff }, + { 0x90013, 0x6152 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 1600mts 1D */ + .drate = 1600, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 667mts 1D */ + .drate = 667, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1600, 667, }, +}; + diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c index 14cb51368f..0d9909a662 100644 --- a/board/freescale/imx8mn_evk/spl.c +++ b/board/freescale/imx8mn_evk/spl.c @@ -83,6 +83,15 @@ int power_init_board(void) #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK) + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); + + /* Disable the BUCK2 */ + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48); + + /* Set NVCC_DRAM to 1.35v */ + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E); #else /* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); diff --git a/configs/imx8mn_ddr3l_evk_defconfig b/configs/imx8mn_ddr3l_evk_defconfig new file mode 100644 index 0000000000..b69fcea0cb --- /dev/null +++ b/configs/imx8mn_ddr3l_evk_defconfig @@ -0,0 +1,95 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr3l-evk" +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_TARGET_IMX8MN_DDR3L_EVK=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SYS_LOAD_ADDR=0x42000000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr3l-evk.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +# CONFIG_SPECIFY_CONSOLE_INDEX is not set +CONFIG_DM_SERIAL=y +# CONFIG_SPL_DM_SERIAL is not set +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_WATCHDOG=y diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 805ae2a751..34278e2c84 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -73,7 +73,11 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 +#ifdef CONFIG_TARGET_IMX8MN_DDR3L_EVK +#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ +#else #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ +#endif #define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) -- 2.20.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support 2022-06-13 21:10 [PATCH v4] imx: add i.MX8MN DDR3L evk board support Heiko Thiery @ 2022-06-14 1:47 ` Peng Fan (OSS) 2022-06-14 6:55 ` Michael Nazzareno Trimarchi 1 sibling, 0 replies; 15+ messages in thread From: Peng Fan (OSS) @ 2022-06-14 1:47 UTC (permalink / raw) To: Heiko Thiery, u-boot Cc: Ying-Chun Liu, Peng Fan, Fabio Estevam, Marek Vasut, Marcel Ziswiler, tharvey, Sean Anderson, Thomas Schäfer, Stefano Babic, Fabio Estevam 在 2022/6/14 5:10, Heiko Thiery 写道: > Add the support for the 8MNANOD3L-EVK board. The board has an i.MX8MNano > UltraLite Quad SoC and uses 1GB DDR3L memory. > > U-Boot SPL 2022.07-rc4-00017-gcf594ebce1 (Jun 13 2022 - 22:40:31 +0200) > Normal Boot > WDT: Started watchdog@30280000 with servicing (60s timeout) > Trying to boot from BOOTROM > image offset 0x8000, pagesize 0x200, ivt offset 0x0 > NOTICE: BL31: v2.6(release):v2.6-5-g9b1a4d832 > NOTICE: BL31: Built : 14:03:53, May 10 2022 > > U-Boot 2022.07-rc4-00017-gcf594ebce1 (Jun 13 2022 - 22:40:31 +0200) > > CPU: Freescale i.MX8MNano UltraLite Quad rev1.0 at 1200 MHz > Reset cause: WDOG > Model: NXP i.MX8MNano DDR3L EVK board > DRAM: 1 GiB > Core: 142 devices, 19 uclasses, devicetree: separate > WDT: Started watchdog@30280000 with servicing (60s timeout) > MMC: FSL_SDHC: 1, FSL_SDHC: 2 > Loading Environment from MMC... OK > In: serial@30890000 > Out: serial@30890000 > Err: serial@30890000 > Net: eth0: ethernet@30be0000 > Hit any key to stop autoboot: 0 > > Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com> > Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> > --- > v4: > - rebase on current master to fix merge conflicts > - remove config options from defconfig > - enable SPL_DM_SERIAL > - include imx8mn-ddr4-evk-u-boot.dtsi in imx8mn-ddr3l-evk-u-boot.dtsi > v3: > - fix config option description in Kconfig (TARGET_IMX8MN_DDR3L_EVK) > v2: > - change license formatting (thanks Marcel) > > arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi | 34 + > arch/arm/dts/imx8mn-ddr3l-evk.dts | 114 +++ > arch/arm/dts/imx8mn-u-boot.dtsi | 12 + > arch/arm/mach-imx/imx8m/Kconfig | 7 + > board/freescale/imx8mn_evk/Kconfig | 2 +- > board/freescale/imx8mn_evk/Makefile | 1 + > board/freescale/imx8mn_evk/ddr3l_timing.c | 943 ++++++++++++++++++++++ > board/freescale/imx8mn_evk/spl.c | 9 + > configs/imx8mn_ddr3l_evk_defconfig | 95 +++ > include/configs/imx8mn_evk.h | 4 + > 10 files changed, 1220 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi > create mode 100644 arch/arm/dts/imx8mn-ddr3l-evk.dts > create mode 100644 board/freescale/imx8mn_evk/ddr3l_timing.c > create mode 100644 configs/imx8mn_ddr3l_evk_defconfig > > diff --git a/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi > new file mode 100644 > index 0000000000..b9192515e5 > --- /dev/null > +++ b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi > @@ -0,0 +1,34 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT > + > +#include "imx8mn-u-boot.dtsi" > +#include "imx8mn-ddr4-evk-u-boot.dtsi" > + > + > +&{/soc@0} { > + u-boot,dm-pre-reloc; > + u-boot,dm-spl; > +}; > + > +&clk { > + u-boot,dm-spl; > + u-boot,dm-pre-reloc; > + /delete-property/ assigned-clocks; > + /delete-property/ assigned-clock-parents; > + /delete-property/ assigned-clock-rates; > +}; > + > +&i2c1 { > + u-boot,dm-spl; > +}; > + > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { > + u-boot,dm-spl; > +}; > + > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { > + u-boot,dm-spl; > +}; > + > +&wdog1 { > + u-boot,dm-spl; > +}; > diff --git a/arch/arm/dts/imx8mn-ddr3l-evk.dts b/arch/arm/dts/imx8mn-ddr3l-evk.dts > new file mode 100644 > index 0000000000..4cdc03c8f2 > --- /dev/null > +++ b/arch/arm/dts/imx8mn-ddr3l-evk.dts > @@ -0,0 +1,114 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT > + > +/dts-v1/; > + > +#include "imx8mn.dtsi" > +#include "imx8mn-evk.dtsi" > +#include <dt-bindings/interrupt-controller/irq.h> > + > +/ { > + model = "NXP i.MX8MNano DDR3L EVK board"; > + compatible = "fsl,imx8mn-ddr3l-evk", "fsl,imx8mn"; > +}; > + > +&A53_0 { > + cpu-supply = <&buck1>; > +}; > + > +&A53_1 { > + cpu-supply = <&buck1>; > +}; > + > +&A53_2 { > + cpu-supply = <&buck1>; > +}; > + > +&A53_3 { > + cpu-supply = <&buck1>; > +}; > + > +&i2c1 { > + pmic: pmic@25 { > + compatible = "nxp,pca9450b"; > + reg = <0x25>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pmic>; > + interrupt-parent = <&gpio1>; > + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; > + > + regulators { > + buck1: BUCK1 { > + regulator-name = "VDD_SOC_0V9"; > + regulator-min-microvolt = <850000>; > + regulator-max-microvolt = <950000>; > + regulator-boot-on; > + regulator-always-on; > + regulator-ramp-delay = <3125>; > + }; > + > + buck4: BUCK4 { > + regulator-name = "VDD_3V3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + buck5: BUCK5 { > + regulator-name = "VDD_1V8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + buck6: BUCK6 { > + regulator-name = "NVCC_DRAM_1V35"; > + regulator-min-microvolt = <1350000>; > + regulator-max-microvolt = <1350000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo1: LDO1 { > + regulator-name = "NVCC_SNVS_1V8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo2: LDO2 { > + regulator-name = "VDD_SNVS_0V8"; > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <800000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo3: LDO3 { > + regulator-name = "VDDA_1V8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo4: LDO4 { > + regulator-name = "VDD_PHY_1V2"; > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1200000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo5: LDO5 { > + regulator-name = "NVCC_SD2"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3300000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + }; > + }; > +}; > diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi > index 7b591085a0..9286bdace0 100644 > --- a/arch/arm/dts/imx8mn-u-boot.dtsi > +++ b/arch/arm/dts/imx8mn-u-boot.dtsi > @@ -151,6 +151,18 @@ > size = <0x4000>; > }; > }; > +#elif CONFIG_IMX8M_DDR3L > +&u_boot_spl_ddr { > + blob_1: blob-ext@1 { > + filename = "ddr3_imem_1d.bin"; > + size = <0x8000>; > + }; > + > + blob_2: blob-ext@2 { > + filename = "ddr3_dmem_1d.bin"; > + size = <0x4000>; > + }; > +}; > #else > #error "no valid ddr config selected" > #endif > diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig > index ef8518c06b..aa386c8f36 100644 > --- a/arch/arm/mach-imx/imx8m/Kconfig > +++ b/arch/arm/mach-imx/imx8m/Kconfig > @@ -140,6 +140,13 @@ config TARGET_IMX8MN_DDR4_EVK > select FSL_CAAM > select SPL_CRYPTO if SPL > > +config TARGET_IMX8MN_DDR3L_EVK > + bool "imx8mn DDR3L EVK board" > + select BINMAN > + select IMX8MN > + select SUPPORT_SPL > + select IMX8M_DDR3L > + > config TARGET_IMX8MN_VENICE > bool "Support Gateworks Venice iMX8M Nano module" > select BINMAN > diff --git a/board/freescale/imx8mn_evk/Kconfig b/board/freescale/imx8mn_evk/Kconfig > index 6596fb5c6d..38312a3662 100644 > --- a/board/freescale/imx8mn_evk/Kconfig > +++ b/board/freescale/imx8mn_evk/Kconfig > @@ -1,4 +1,4 @@ > -if TARGET_IMX8MN_EVK || TARGET_IMX8MN_DDR4_EVK > +if TARGET_IMX8MN_EVK || TARGET_IMX8MN_DDR4_EVK || TARGET_IMX8MN_DDR3L_EVK > > config SYS_BOARD > default "imx8mn_evk" > diff --git a/board/freescale/imx8mn_evk/Makefile b/board/freescale/imx8mn_evk/Makefile > index 42d1179724..ad3ef8edd6 100644 > --- a/board/freescale/imx8mn_evk/Makefile > +++ b/board/freescale/imx8mn_evk/Makefile > @@ -14,5 +14,6 @@ obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing_ld.o > else > obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o > obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o > +obj-$(CONFIG_IMX8M_DDR3L) += ddr3l_timing.o > endif > endif > diff --git a/board/freescale/imx8mn_evk/ddr3l_timing.c b/board/freescale/imx8mn_evk/ddr3l_timing.c > new file mode 100644 > index 0000000000..0fe1f6a42d > --- /dev/null > +++ b/board/freescale/imx8mn_evk/ddr3l_timing.c > @@ -0,0 +1,943 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +/* > + * Copyright 2019 NXP > + * > + * Generated code from MX8M_DDR_tool > + * > + * Align with uboot version: > + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga > + * For imx_v2019.04_5.4.x and above version: > + * please replace #include <asm/arch/imx8m_ddr.h> with #include <asm/arch/ddr.h> > + */ > + > +#include <linux/kernel.h> > +#include <asm/arch/ddr.h> > + > +struct dram_cfg_param ddr_ddrc_cfg[] = { > + /** Initialize DDRC registers **/ > + { 0x3d400304, 0x1 }, > + { 0x3d400030, 0x20 }, > + { 0x3d400000, 0xa1040001 }, > + { 0x3d400064, 0x61008c }, > + { 0x3d4000d0, 0xc00200c5 }, > + { 0x3d4000d4, 0x1000b }, > + { 0x3d4000dc, 0x1d700004 }, > + { 0x3d4000e0, 0x180000 }, > + { 0x3d4000e4, 0x90000 }, > + { 0x3d4000f0, 0x0 }, > + { 0x3d4000f4, 0xee5 }, > + { 0x3d400100, 0xc101b0e }, > + { 0x3d400104, 0x30314 }, > + { 0x3d400108, 0x4060509 }, > + { 0x3d40010c, 0x2006 }, > + { 0x3d400110, 0x6020306 }, > + { 0x3d400114, 0x4040302 }, > + { 0x3d400120, 0x909 }, > + { 0x3d400180, 0x40800020 }, > + { 0x3d400184, 0xc350 }, > + { 0x3d400190, 0x3868203 }, > + { 0x3d400194, 0x20303 }, > + { 0x3d4001b4, 0x603 }, > + { 0x3d400198, 0x7000000 }, > + { 0x3d4001b0, 0x11 }, > + { 0x3d4001a0, 0x400018 }, > + { 0x3d4001a4, 0x5003c }, > + { 0x3d4001a8, 0x80000000 }, > + { 0x3d4001c4, 0x0 }, > + { 0x3d400200, 0x1f }, > + { 0x3d400204, 0x80808 }, > + { 0x3d400208, 0x0 }, > + { 0x3d40020c, 0x0 }, > + { 0x3d400210, 0x1f1f }, > + { 0x3d400214, 0x7070707 }, > + { 0x3d400218, 0x7070707 }, > + { 0x3d400240, 0x600060c }, > + { 0x3d400244, 0x1323 }, > + { 0x3d400400, 0x100 }, > + { 0x3d400250, 0x7ab50b07 }, > + { 0x3d400254, 0x22 }, > + { 0x3d40025c, 0x7b00665e }, > + { 0x3d400264, 0xb0000040 }, > + { 0x3d40026c, 0x50000a0c }, > + { 0x3d400300, 0x17 }, > + { 0x3d40036c, 0x10000 }, > + { 0x3d400404, 0x3051 }, > + { 0x3d400408, 0x61d2 }, > + { 0x3d400494, 0xe00 }, > + { 0x3d400498, 0x7ff }, > + { 0x3d40049c, 0xe00 }, > + { 0x3d4004a0, 0x7ff }, > + { 0x3d402064, 0x28003b }, > + { 0x3d4020dc, 0x12200004 }, > + { 0x3d4020e0, 0x0 }, > + { 0x3d402100, 0x7090b07 }, > + { 0x3d402104, 0x20209 }, > + { 0x3d402108, 0x3030407 }, > + { 0x3d40210c, 0x2006 }, > + { 0x3d402110, 0x3020203 }, > + { 0x3d402114, 0x3030202 }, > + { 0x3d402120, 0x909 }, > + { 0x3d402180, 0x40800020 }, > + { 0x3d402190, 0x3818200 }, > + { 0x3d402194, 0x20303 }, > + { 0x3d4021b4, 0x100 }, > + { 0x3d402240, 0x6000604 }, > + { 0x3d4020f4, 0xee5 }, > + { 0x3d400028, 0x1 }, > +}; > + > +/* PHY Initialize Configuration */ > +struct dram_cfg_param ddr_ddrphy_cfg[] = { > + { 0x1005f, 0x3ff }, > + { 0x1015f, 0x3ff }, > + { 0x1105f, 0x3ff }, > + { 0x1115f, 0x3ff }, > + { 0x11005f, 0x3ff }, > + { 0x11015f, 0x3ff }, > + { 0x11105f, 0x3ff }, > + { 0x11115f, 0x3ff }, > + { 0x55, 0x3ff }, > + { 0x1055, 0x3ff }, > + { 0x2055, 0x3ff }, > + { 0x3055, 0x3ff }, > + { 0x4055, 0xff }, > + { 0x5055, 0xff }, > + { 0x6055, 0x3ff }, > + { 0x7055, 0x3ff }, > + { 0x8055, 0x3ff }, > + { 0x9055, 0x3ff }, > + { 0x200c5, 0xb }, > + { 0x1200c5, 0x7 }, > + { 0x2002e, 0x1 }, > + { 0x12002e, 0x1 }, > + { 0x20024, 0x0 }, > + { 0x2003a, 0x0 }, > + { 0x120024, 0x0 }, > + { 0x2003a, 0x0 }, > + { 0x20056, 0xa }, > + { 0x120056, 0xa }, > + { 0x1004d, 0x208 }, > + { 0x1014d, 0x208 }, > + { 0x1104d, 0x208 }, > + { 0x1114d, 0x208 }, > + { 0x11004d, 0x208 }, > + { 0x11014d, 0x208 }, > + { 0x11104d, 0x208 }, > + { 0x11114d, 0x208 }, > + { 0x10049, 0xe38 }, > + { 0x10149, 0xe38 }, > + { 0x11049, 0xe38 }, > + { 0x11149, 0xe38 }, > + { 0x110049, 0xe38 }, > + { 0x110149, 0xe38 }, > + { 0x111049, 0xe38 }, > + { 0x111149, 0xe38 }, > + { 0x43, 0x63 }, > + { 0x1043, 0x63 }, > + { 0x2043, 0x63 }, > + { 0x3043, 0x63 }, > + { 0x4043, 0x63 }, > + { 0x5043, 0x63 }, > + { 0x6043, 0x63 }, > + { 0x7043, 0x63 }, > + { 0x8043, 0x63 }, > + { 0x9043, 0x63 }, > + { 0x20018, 0x1 }, > + { 0x20075, 0x0 }, > + { 0x20050, 0x0 }, > + { 0x20008, 0x190 }, > + { 0x120008, 0xa7 }, > + { 0x20088, 0x9 }, > + { 0x200b2, 0x32c }, > + { 0x10043, 0x581 }, > + { 0x10143, 0x581 }, > + { 0x11043, 0x581 }, > + { 0x11143, 0x581 }, > + { 0x1200b2, 0x32c }, > + { 0x110043, 0x581 }, > + { 0x110143, 0x581 }, > + { 0x111043, 0x581 }, > + { 0x111143, 0x581 }, > + { 0x200fa, 0x1 }, > + { 0x1200fa, 0x1 }, > + { 0x20019, 0x5 }, > + { 0x120019, 0x5 }, > + { 0x200f0, 0x5555 }, > + { 0x200f1, 0x5555 }, > + { 0x200f2, 0x5555 }, > + { 0x200f3, 0x5555 }, > + { 0x200f4, 0x5555 }, > + { 0x200f5, 0x5555 }, > + { 0x200f6, 0x5555 }, > + { 0x200f7, 0xf000 }, > + { 0x20025, 0x0 }, > + { 0x2007d, 0x212 }, > + { 0x12007d, 0x212 }, > + { 0x2007c, 0x61 }, > + { 0x12007c, 0x61 }, > + { 0x1004a, 0x500 }, > + { 0x1104a, 0x500 }, > + { 0x2002c, 0x0 }, > +}; > + > +/* ddr phy trained csr */ > +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { > + {0x0200b2,0x0}, > + {0x1200b2,0x0}, > + {0x2200b2,0x0}, > + {0x0200cb,0x0}, > + {0x010043,0x0}, > + {0x110043,0x0}, > + {0x210043,0x0}, > + {0x010143,0x0}, > + {0x110143,0x0}, > + {0x210143,0x0}, > + {0x011043,0x0}, > + {0x111043,0x0}, > + {0x211043,0x0}, > + {0x011143,0x0}, > + {0x111143,0x0}, > + {0x211143,0x0}, > + {0x000080,0x0}, > + {0x100080,0x0}, > + {0x200080,0x0}, > + {0x001080,0x0}, > + {0x101080,0x0}, > + {0x201080,0x0}, > + {0x002080,0x0}, > + {0x102080,0x0}, > + {0x202080,0x0}, > + {0x003080,0x0}, > + {0x103080,0x0}, > + {0x203080,0x0}, > + {0x004080,0x0}, > + {0x104080,0x0}, > + {0x204080,0x0}, > + {0x005080,0x0}, > + {0x105080,0x0}, > + {0x205080,0x0}, > + {0x006080,0x0}, > + {0x106080,0x0}, > + {0x206080,0x0}, > + {0x007080,0x0}, > + {0x107080,0x0}, > + {0x207080,0x0}, > + {0x008080,0x0}, > + {0x108080,0x0}, > + {0x208080,0x0}, > + {0x009080,0x0}, > + {0x109080,0x0}, > + {0x209080,0x0}, > + {0x010080,0x0}, > + {0x110080,0x0}, > + {0x210080,0x0}, > + {0x010180,0x0}, > + {0x110180,0x0}, > + {0x210180,0x0}, > + {0x010081,0x0}, > + {0x110081,0x0}, > + {0x210081,0x0}, > + {0x010181,0x0}, > + {0x110181,0x0}, > + {0x210181,0x0}, > + {0x010082,0x0}, > + {0x110082,0x0}, > + {0x210082,0x0}, > + {0x010182,0x0}, > + {0x110182,0x0}, > + {0x210182,0x0}, > + {0x010083,0x0}, > + {0x110083,0x0}, > + {0x210083,0x0}, > + {0x010183,0x0}, > + {0x110183,0x0}, > + {0x210183,0x0}, > + {0x011080,0x0}, > + {0x111080,0x0}, > + {0x211080,0x0}, > + {0x011180,0x0}, > + {0x111180,0x0}, > + {0x211180,0x0}, > + {0x011081,0x0}, > + {0x111081,0x0}, > + {0x211081,0x0}, > + {0x011181,0x0}, > + {0x111181,0x0}, > + {0x211181,0x0}, > + {0x011082,0x0}, > + {0x111082,0x0}, > + {0x211082,0x0}, > + {0x011182,0x0}, > + {0x111182,0x0}, > + {0x211182,0x0}, > + {0x011083,0x0}, > + {0x111083,0x0}, > + {0x211083,0x0}, > + {0x011183,0x0}, > + {0x111183,0x0}, > + {0x211183,0x0}, > + {0x0100d0,0x0}, > + {0x1100d0,0x0}, > + {0x2100d0,0x0}, > + {0x0101d0,0x0}, > + {0x1101d0,0x0}, > + {0x2101d0,0x0}, > + {0x0100d1,0x0}, > + {0x1100d1,0x0}, > + {0x2100d1,0x0}, > + {0x0101d1,0x0}, > + {0x1101d1,0x0}, > + {0x2101d1,0x0}, > + {0x0100d2,0x0}, > + {0x1100d2,0x0}, > + {0x2100d2,0x0}, > + {0x0101d2,0x0}, > + {0x1101d2,0x0}, > + {0x2101d2,0x0}, > + {0x0100d3,0x0}, > + {0x1100d3,0x0}, > + {0x2100d3,0x0}, > + {0x0101d3,0x0}, > + {0x1101d3,0x0}, > + {0x2101d3,0x0}, > + {0x0110d0,0x0}, > + {0x1110d0,0x0}, > + {0x2110d0,0x0}, > + {0x0111d0,0x0}, > + {0x1111d0,0x0}, > + {0x2111d0,0x0}, > + {0x0110d1,0x0}, > + {0x1110d1,0x0}, > + {0x2110d1,0x0}, > + {0x0111d1,0x0}, > + {0x1111d1,0x0}, > + {0x2111d1,0x0}, > + {0x0110d2,0x0}, > + {0x1110d2,0x0}, > + {0x2110d2,0x0}, > + {0x0111d2,0x0}, > + {0x1111d2,0x0}, > + {0x2111d2,0x0}, > + {0x0110d3,0x0}, > + {0x1110d3,0x0}, > + {0x2110d3,0x0}, > + {0x0111d3,0x0}, > + {0x1111d3,0x0}, > + {0x2111d3,0x0}, > + {0x010068,0x0}, > + {0x010168,0x0}, > + {0x010268,0x0}, > + {0x010368,0x0}, > + {0x010468,0x0}, > + {0x010568,0x0}, > + {0x010668,0x0}, > + {0x010768,0x0}, > + {0x010868,0x0}, > + {0x010069,0x0}, > + {0x010169,0x0}, > + {0x010269,0x0}, > + {0x010369,0x0}, > + {0x010469,0x0}, > + {0x010569,0x0}, > + {0x010669,0x0}, > + {0x010769,0x0}, > + {0x010869,0x0}, > + {0x01006a,0x0}, > + {0x01016a,0x0}, > + {0x01026a,0x0}, > + {0x01036a,0x0}, > + {0x01046a,0x0}, > + {0x01056a,0x0}, > + {0x01066a,0x0}, > + {0x01076a,0x0}, > + {0x01086a,0x0}, > + {0x01006b,0x0}, > + {0x01016b,0x0}, > + {0x01026b,0x0}, > + {0x01036b,0x0}, > + {0x01046b,0x0}, > + {0x01056b,0x0}, > + {0x01066b,0x0}, > + {0x01076b,0x0}, > + {0x01086b,0x0}, > + {0x011068,0x0}, > + {0x011168,0x0}, > + {0x011268,0x0}, > + {0x011368,0x0}, > + {0x011468,0x0}, > + {0x011568,0x0}, > + {0x011668,0x0}, > + {0x011768,0x0}, > + {0x011868,0x0}, > + {0x011069,0x0}, > + {0x011169,0x0}, > + {0x011269,0x0}, > + {0x011369,0x0}, > + {0x011469,0x0}, > + {0x011569,0x0}, > + {0x011669,0x0}, > + {0x011769,0x0}, > + {0x011869,0x0}, > + {0x01106a,0x0}, > + {0x01116a,0x0}, > + {0x01126a,0x0}, > + {0x01136a,0x0}, > + {0x01146a,0x0}, > + {0x01156a,0x0}, > + {0x01166a,0x0}, > + {0x01176a,0x0}, > + {0x01186a,0x0}, > + {0x01106b,0x0}, > + {0x01116b,0x0}, > + {0x01126b,0x0}, > + {0x01136b,0x0}, > + {0x01146b,0x0}, > + {0x01156b,0x0}, > + {0x01166b,0x0}, > + {0x01176b,0x0}, > + {0x01186b,0x0}, > + {0x01008c,0x0}, > + {0x11008c,0x0}, > + {0x21008c,0x0}, > + {0x01018c,0x0}, > + {0x11018c,0x0}, > + {0x21018c,0x0}, > + {0x01008d,0x0}, > + {0x11008d,0x0}, > + {0x21008d,0x0}, > + {0x01018d,0x0}, > + {0x11018d,0x0}, > + {0x21018d,0x0}, > + {0x01008e,0x0}, > + {0x11008e,0x0}, > + {0x21008e,0x0}, > + {0x01018e,0x0}, > + {0x11018e,0x0}, > + {0x21018e,0x0}, > + {0x01008f,0x0}, > + {0x11008f,0x0}, > + {0x21008f,0x0}, > + {0x01018f,0x0}, > + {0x11018f,0x0}, > + {0x21018f,0x0}, > + {0x01108c,0x0}, > + {0x11108c,0x0}, > + {0x21108c,0x0}, > + {0x01118c,0x0}, > + {0x11118c,0x0}, > + {0x21118c,0x0}, > + {0x01108d,0x0}, > + {0x11108d,0x0}, > + {0x21108d,0x0}, > + {0x01118d,0x0}, > + {0x11118d,0x0}, > + {0x21118d,0x0}, > + {0x01108e,0x0}, > + {0x11108e,0x0}, > + {0x21108e,0x0}, > + {0x01118e,0x0}, > + {0x11118e,0x0}, > + {0x21118e,0x0}, > + {0x01108f,0x0}, > + {0x11108f,0x0}, > + {0x21108f,0x0}, > + {0x01118f,0x0}, > + {0x11118f,0x0}, > + {0x21118f,0x0}, > + {0x0100c0,0x0}, > + {0x1100c0,0x0}, > + {0x2100c0,0x0}, > + {0x0101c0,0x0}, > + {0x1101c0,0x0}, > + {0x2101c0,0x0}, > + {0x0102c0,0x0}, > + {0x1102c0,0x0}, > + {0x2102c0,0x0}, > + {0x0103c0,0x0}, > + {0x1103c0,0x0}, > + {0x2103c0,0x0}, > + {0x0104c0,0x0}, > + {0x1104c0,0x0}, > + {0x2104c0,0x0}, > + {0x0105c0,0x0}, > + {0x1105c0,0x0}, > + {0x2105c0,0x0}, > + {0x0106c0,0x0}, > + {0x1106c0,0x0}, > + {0x2106c0,0x0}, > + {0x0107c0,0x0}, > + {0x1107c0,0x0}, > + {0x2107c0,0x0}, > + {0x0108c0,0x0}, > + {0x1108c0,0x0}, > + {0x2108c0,0x0}, > + {0x0100c1,0x0}, > + {0x1100c1,0x0}, > + {0x2100c1,0x0}, > + {0x0101c1,0x0}, > + {0x1101c1,0x0}, > + {0x2101c1,0x0}, > + {0x0102c1,0x0}, > + {0x1102c1,0x0}, > + {0x2102c1,0x0}, > + {0x0103c1,0x0}, > + {0x1103c1,0x0}, > + {0x2103c1,0x0}, > + {0x0104c1,0x0}, > + {0x1104c1,0x0}, > + {0x2104c1,0x0}, > + {0x0105c1,0x0}, > + {0x1105c1,0x0}, > + {0x2105c1,0x0}, > + {0x0106c1,0x0}, > + {0x1106c1,0x0}, > + {0x2106c1,0x0}, > + {0x0107c1,0x0}, > + {0x1107c1,0x0}, > + {0x2107c1,0x0}, > + {0x0108c1,0x0}, > + {0x1108c1,0x0}, > + {0x2108c1,0x0}, > + {0x0100c2,0x0}, > + {0x1100c2,0x0}, > + {0x2100c2,0x0}, > + {0x0101c2,0x0}, > + {0x1101c2,0x0}, > + {0x2101c2,0x0}, > + {0x0102c2,0x0}, > + {0x1102c2,0x0}, > + {0x2102c2,0x0}, > + {0x0103c2,0x0}, > + {0x1103c2,0x0}, > + {0x2103c2,0x0}, > + {0x0104c2,0x0}, > + {0x1104c2,0x0}, > + {0x2104c2,0x0}, > + {0x0105c2,0x0}, > + {0x1105c2,0x0}, > + {0x2105c2,0x0}, > + {0x0106c2,0x0}, > + {0x1106c2,0x0}, > + {0x2106c2,0x0}, > + {0x0107c2,0x0}, > + {0x1107c2,0x0}, > + {0x2107c2,0x0}, > + {0x0108c2,0x0}, > + {0x1108c2,0x0}, > + {0x2108c2,0x0}, > + {0x0100c3,0x0}, > + {0x1100c3,0x0}, > + {0x2100c3,0x0}, > + {0x0101c3,0x0}, > + {0x1101c3,0x0}, > + {0x2101c3,0x0}, > + {0x0102c3,0x0}, > + {0x1102c3,0x0}, > + {0x2102c3,0x0}, > + {0x0103c3,0x0}, > + {0x1103c3,0x0}, > + {0x2103c3,0x0}, > + {0x0104c3,0x0}, > + {0x1104c3,0x0}, > + {0x2104c3,0x0}, > + {0x0105c3,0x0}, > + {0x1105c3,0x0}, > + {0x2105c3,0x0}, > + {0x0106c3,0x0}, > + {0x1106c3,0x0}, > + {0x2106c3,0x0}, > + {0x0107c3,0x0}, > + {0x1107c3,0x0}, > + {0x2107c3,0x0}, > + {0x0108c3,0x0}, > + {0x1108c3,0x0}, > + {0x2108c3,0x0}, > + {0x0110c0,0x0}, > + {0x1110c0,0x0}, > + {0x2110c0,0x0}, > + {0x0111c0,0x0}, > + {0x1111c0,0x0}, > + {0x2111c0,0x0}, > + {0x0112c0,0x0}, > + {0x1112c0,0x0}, > + {0x2112c0,0x0}, > + {0x0113c0,0x0}, > + {0x1113c0,0x0}, > + {0x2113c0,0x0}, > + {0x0114c0,0x0}, > + {0x1114c0,0x0}, > + {0x2114c0,0x0}, > + {0x0115c0,0x0}, > + {0x1115c0,0x0}, > + {0x2115c0,0x0}, > + {0x0116c0,0x0}, > + {0x1116c0,0x0}, > + {0x2116c0,0x0}, > + {0x0117c0,0x0}, > + {0x1117c0,0x0}, > + {0x2117c0,0x0}, > + {0x0118c0,0x0}, > + {0x1118c0,0x0}, > + {0x2118c0,0x0}, > + {0x0110c1,0x0}, > + {0x1110c1,0x0}, > + {0x2110c1,0x0}, > + {0x0111c1,0x0}, > + {0x1111c1,0x0}, > + {0x2111c1,0x0}, > + {0x0112c1,0x0}, > + {0x1112c1,0x0}, > + {0x2112c1,0x0}, > + {0x0113c1,0x0}, > + {0x1113c1,0x0}, > + {0x2113c1,0x0}, > + {0x0114c1,0x0}, > + {0x1114c1,0x0}, > + {0x2114c1,0x0}, > + {0x0115c1,0x0}, > + {0x1115c1,0x0}, > + {0x2115c1,0x0}, > + {0x0116c1,0x0}, > + {0x1116c1,0x0}, > + {0x2116c1,0x0}, > + {0x0117c1,0x0}, > + {0x1117c1,0x0}, > + {0x2117c1,0x0}, > + {0x0118c1,0x0}, > + {0x1118c1,0x0}, > + {0x2118c1,0x0}, > + {0x0110c2,0x0}, > + {0x1110c2,0x0}, > + {0x2110c2,0x0}, > + {0x0111c2,0x0}, > + {0x1111c2,0x0}, > + {0x2111c2,0x0}, > + {0x0112c2,0x0}, > + {0x1112c2,0x0}, > + {0x2112c2,0x0}, > + {0x0113c2,0x0}, > + {0x1113c2,0x0}, > + {0x2113c2,0x0}, > + {0x0114c2,0x0}, > + {0x1114c2,0x0}, > + {0x2114c2,0x0}, > + {0x0115c2,0x0}, > + {0x1115c2,0x0}, > + {0x2115c2,0x0}, > + {0x0116c2,0x0}, > + {0x1116c2,0x0}, > + {0x2116c2,0x0}, > + {0x0117c2,0x0}, > + {0x1117c2,0x0}, > + {0x2117c2,0x0}, > + {0x0118c2,0x0}, > + {0x1118c2,0x0}, > + {0x2118c2,0x0}, > + {0x0110c3,0x0}, > + {0x1110c3,0x0}, > + {0x2110c3,0x0}, > + {0x0111c3,0x0}, > + {0x1111c3,0x0}, > + {0x2111c3,0x0}, > + {0x0112c3,0x0}, > + {0x1112c3,0x0}, > + {0x2112c3,0x0}, > + {0x0113c3,0x0}, > + {0x1113c3,0x0}, > + {0x2113c3,0x0}, > + {0x0114c3,0x0}, > + {0x1114c3,0x0}, > + {0x2114c3,0x0}, > + {0x0115c3,0x0}, > + {0x1115c3,0x0}, > + {0x2115c3,0x0}, > + {0x0116c3,0x0}, > + {0x1116c3,0x0}, > + {0x2116c3,0x0}, > + {0x0117c3,0x0}, > + {0x1117c3,0x0}, > + {0x2117c3,0x0}, > + {0x0118c3,0x0}, > + {0x1118c3,0x0}, > + {0x2118c3,0x0}, > + {0x010020,0x0}, > + {0x110020,0x0}, > + {0x210020,0x0}, > + {0x011020,0x0}, > + {0x111020,0x0}, > + {0x211020,0x0}, > + {0x02007d,0x0}, > + {0x12007d,0x0}, > + {0x22007d,0x0}, > +}; > + > +/* P0 message block paremeter for training firmware */ > +struct dram_cfg_param ddr_fsp0_cfg[] = { > + { 0xd0000, 0x0 }, > + { 0x54003, 0x640 }, > + { 0x54004, 0x2 }, > + { 0x54005, 0x283c }, > + { 0x54006, 0x140 }, > + { 0x54007, 0x1000 }, > + { 0x54008, 0x101 }, > + { 0x5400b, 0x31f }, > + { 0x5400c, 0xc8 }, > + { 0x54012, 0x1 }, > + { 0x5402f, 0x1d70 }, > + { 0x54030, 0x4 }, > + { 0x54031, 0x18 }, > + { 0x5403a, 0x1323 }, > + { 0xd0000, 0x1 }, > +}; > + > + > +/* P1 message block paremeter for training firmware */ > +struct dram_cfg_param ddr_fsp1_cfg[] = { > + { 0xd0000, 0x0 }, > + { 0x54002, 0x1 }, > + { 0x54003, 0x29c }, > + { 0x54004, 0x2 }, > + { 0x54005, 0x283c }, > + { 0x54006, 0x140 }, > + { 0x54007, 0x1000 }, > + { 0x54008, 0x101 }, > + { 0x5400b, 0x21f }, > + { 0x5400c, 0xc8 }, > + { 0x54012, 0x1 }, > + { 0x5402f, 0x1220 }, > + { 0x54030, 0x4 }, > + { 0x5403a, 0x1323 }, > + { 0xd0000, 0x1 }, > +}; > + > +/* DRAM PHY init engine image */ > +struct dram_cfg_param ddr_phy_pie[] = { > + { 0xd0000, 0x0 }, > + { 0x90000, 0x10 }, > + { 0x90001, 0x400 }, > + { 0x90002, 0x10e }, > + { 0x90003, 0x0 }, > + { 0x90004, 0x0 }, > + { 0x90005, 0x8 }, > + { 0x90029, 0xb }, > + { 0x9002a, 0x480 }, > + { 0x9002b, 0x109 }, > + { 0x9002c, 0x8 }, > + { 0x9002d, 0x448 }, > + { 0x9002e, 0x139 }, > + { 0x9002f, 0x8 }, > + { 0x90030, 0x478 }, > + { 0x90031, 0x109 }, > + { 0x90032, 0x2 }, > + { 0x90033, 0x10 }, > + { 0x90034, 0x139 }, > + { 0x90035, 0xb }, > + { 0x90036, 0x7c0 }, > + { 0x90037, 0x139 }, > + { 0x90038, 0x44 }, > + { 0x90039, 0x633 }, > + { 0x9003a, 0x159 }, > + { 0x9003b, 0x14f }, > + { 0x9003c, 0x630 }, > + { 0x9003d, 0x159 }, > + { 0x9003e, 0x47 }, > + { 0x9003f, 0x633 }, > + { 0x90040, 0x149 }, > + { 0x90041, 0x4f }, > + { 0x90042, 0x633 }, > + { 0x90043, 0x179 }, > + { 0x90044, 0x8 }, > + { 0x90045, 0xe0 }, > + { 0x90046, 0x109 }, > + { 0x90047, 0x0 }, > + { 0x90048, 0x7c8 }, > + { 0x90049, 0x109 }, > + { 0x9004a, 0x0 }, > + { 0x9004b, 0x1 }, > + { 0x9004c, 0x8 }, > + { 0x9004d, 0x0 }, > + { 0x9004e, 0x45a }, > + { 0x9004f, 0x9 }, > + { 0x90050, 0x0 }, > + { 0x90051, 0x448 }, > + { 0x90052, 0x109 }, > + { 0x90053, 0x40 }, > + { 0x90054, 0x633 }, > + { 0x90055, 0x179 }, > + { 0x90056, 0x1 }, > + { 0x90057, 0x618 }, > + { 0x90058, 0x109 }, > + { 0x90059, 0x40c0 }, > + { 0x9005a, 0x633 }, > + { 0x9005b, 0x149 }, > + { 0x9005c, 0x8 }, > + { 0x9005d, 0x4 }, > + { 0x9005e, 0x48 }, > + { 0x9005f, 0x4040 }, > + { 0x90060, 0x633 }, > + { 0x90061, 0x149 }, > + { 0x90062, 0x0 }, > + { 0x90063, 0x4 }, > + { 0x90064, 0x48 }, > + { 0x90065, 0x40 }, > + { 0x90066, 0x633 }, > + { 0x90067, 0x149 }, > + { 0x90068, 0x10 }, > + { 0x90069, 0x4 }, > + { 0x9006a, 0x18 }, > + { 0x9006b, 0x0 }, > + { 0x9006c, 0x4 }, > + { 0x9006d, 0x78 }, > + { 0x9006e, 0x549 }, > + { 0x9006f, 0x633 }, > + { 0x90070, 0x159 }, > + { 0x90071, 0xd49 }, > + { 0x90072, 0x633 }, > + { 0x90073, 0x159 }, > + { 0x90074, 0x94a }, > + { 0x90075, 0x633 }, > + { 0x90076, 0x159 }, > + { 0x90077, 0x441 }, > + { 0x90078, 0x633 }, > + { 0x90079, 0x149 }, > + { 0x9007a, 0x42 }, > + { 0x9007b, 0x633 }, > + { 0x9007c, 0x149 }, > + { 0x9007d, 0x1 }, > + { 0x9007e, 0x633 }, > + { 0x9007f, 0x149 }, > + { 0x90080, 0x0 }, > + { 0x90081, 0xe0 }, > + { 0x90082, 0x109 }, > + { 0x90083, 0xa }, > + { 0x90084, 0x10 }, > + { 0x90085, 0x109 }, > + { 0x90086, 0x9 }, > + { 0x90087, 0x3c0 }, > + { 0x90088, 0x149 }, > + { 0x90089, 0x9 }, > + { 0x9008a, 0x3c0 }, > + { 0x9008b, 0x159 }, > + { 0x9008c, 0x18 }, > + { 0x9008d, 0x10 }, > + { 0x9008e, 0x109 }, > + { 0x9008f, 0x0 }, > + { 0x90090, 0x3c0 }, > + { 0x90091, 0x109 }, > + { 0x90092, 0x18 }, > + { 0x90093, 0x4 }, > + { 0x90094, 0x48 }, > + { 0x90095, 0x18 }, > + { 0x90096, 0x4 }, > + { 0x90097, 0x58 }, > + { 0x90098, 0xb }, > + { 0x90099, 0x10 }, > + { 0x9009a, 0x109 }, > + { 0x9009b, 0x1 }, > + { 0x9009c, 0x10 }, > + { 0x9009d, 0x109 }, > + { 0x9009e, 0x5 }, > + { 0x9009f, 0x7c0 }, > + { 0x900a0, 0x109 }, > + { 0x900a1, 0x0 }, > + { 0x900a2, 0x8140 }, > + { 0x900a3, 0x10c }, > + { 0x900a4, 0x10 }, > + { 0x900a5, 0x8138 }, > + { 0x900a6, 0x10c }, > + { 0x900a7, 0x8 }, > + { 0x900a8, 0x7c8 }, > + { 0x900a9, 0x101 }, > + { 0x900aa, 0x8 }, > + { 0x900ab, 0x448 }, > + { 0x900ac, 0x109 }, > + { 0x900ad, 0xf }, > + { 0x900ae, 0x7c0 }, > + { 0x900af, 0x109 }, > + { 0x900b0, 0x47 }, > + { 0x900b1, 0x630 }, > + { 0x900b2, 0x109 }, > + { 0x900b3, 0x8 }, > + { 0x900b4, 0x618 }, > + { 0x900b5, 0x109 }, > + { 0x900b6, 0x8 }, > + { 0x900b7, 0xe0 }, > + { 0x900b8, 0x109 }, > + { 0x900b9, 0x0 }, > + { 0x900ba, 0x7c8 }, > + { 0x900bb, 0x109 }, > + { 0x900bc, 0x8 }, > + { 0x900bd, 0x8140 }, > + { 0x900be, 0x10c }, > + { 0x900bf, 0x0 }, > + { 0x900c0, 0x1 }, > + { 0x900c1, 0x8 }, > + { 0x900c2, 0x8 }, > + { 0x900c3, 0x4 }, > + { 0x900c4, 0x8 }, > + { 0x900c5, 0x8 }, > + { 0x900c6, 0x7c8 }, > + { 0x900c7, 0x101 }, > + { 0x90006, 0x0 }, > + { 0x90007, 0x0 }, > + { 0x90008, 0x8 }, > + { 0x90009, 0x0 }, > + { 0x9000a, 0x0 }, > + { 0x9000b, 0x0 }, > + { 0xd00e7, 0x400 }, > + { 0x90017, 0x0 }, > + { 0x90026, 0x2b }, > + { 0x2000b, 0x32 }, > + { 0x2000c, 0x64 }, > + { 0x2000d, 0x3e8 }, > + { 0x2000e, 0x2c }, > + { 0x12000b, 0x14 }, > + { 0x12000c, 0x26 }, > + { 0x12000d, 0x1a1 }, > + { 0x12000e, 0x10 }, > + { 0x9000c, 0x0 }, > + { 0x9000d, 0x173 }, > + { 0x9000e, 0x60 }, > + { 0x9000f, 0x6110 }, > + { 0x90010, 0x2152 }, > + { 0x90011, 0xdfbd }, > + { 0x90012, 0xffff }, > + { 0x90013, 0x6152 }, > + { 0x20089, 0x1 }, > + { 0x20088, 0x19 }, > + { 0xc0080, 0x0 }, > + { 0xd0000, 0x1 } > +}; > + > +struct dram_fsp_msg ddr_dram_fsp_msg[] = { > + { > + /* P0 1600mts 1D */ > + .drate = 1600, > + .fw_type = FW_1D_IMAGE, > + .fsp_cfg = ddr_fsp0_cfg, > + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), > + }, > + { > + /* P1 667mts 1D */ > + .drate = 667, > + .fw_type = FW_1D_IMAGE, > + .fsp_cfg = ddr_fsp1_cfg, > + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), > + }, > +}; > + > +/* ddr timing config params */ > +struct dram_timing_info dram_timing = { > + .ddrc_cfg = ddr_ddrc_cfg, > + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), > + .ddrphy_cfg = ddr_ddrphy_cfg, > + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), > + .fsp_msg = ddr_dram_fsp_msg, > + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), > + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, > + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), > + .ddrphy_pie = ddr_phy_pie, > + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), > + .fsp_table = { 1600, 667, }, > +}; > + > diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c > index 14cb51368f..0d9909a662 100644 > --- a/board/freescale/imx8mn_evk/spl.c > +++ b/board/freescale/imx8mn_evk/spl.c > @@ -83,6 +83,15 @@ int power_init_board(void) > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK) > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */ > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); > + > + /* Disable the BUCK2 */ > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48); > + > + /* Set NVCC_DRAM to 1.35v */ > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E); > #else > /* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */ > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); > diff --git a/configs/imx8mn_ddr3l_evk_defconfig b/configs/imx8mn_ddr3l_evk_defconfig > new file mode 100644 > index 0000000000..b69fcea0cb > --- /dev/null > +++ b/configs/imx8mn_ddr3l_evk_defconfig > @@ -0,0 +1,95 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_IMX8M=y > +CONFIG_SYS_TEXT_BASE=0x40200000 > +CONFIG_SYS_MALLOC_LEN=0x2000000 > +CONFIG_SPL_GPIO=y > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > +CONFIG_ENV_SIZE=0x1000 > +CONFIG_ENV_OFFSET=0x400000 > +CONFIG_DM_GPIO=y > +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr3l-evk" > +CONFIG_SPL_TEXT_BASE=0x912000 > +CONFIG_TARGET_IMX8MN_DDR3L_EVK=y > +CONFIG_SPL_SERIAL=y > +CONFIG_SPL_DRIVERS_MISC=y > +CONFIG_SPL=y > +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 > +CONFIG_SYS_LOAD_ADDR=0x42000000 > +CONFIG_DISTRO_DEFAULTS=y > +CONFIG_FIT=y > +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 > +CONFIG_SPL_LOAD_FIT=y > +# CONFIG_USE_SPL_FIT_GENERATOR is not set > +CONFIG_OF_SYSTEM_SETUP=y > +CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr3l-evk.dtb" > +CONFIG_ARCH_MISC_INIT=y > +CONFIG_BOARD_LATE_INIT=y > +CONFIG_SPL_BOARD_INIT=y > +CONFIG_SPL_BOOTROM_SUPPORT=y > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 > +CONFIG_SPL_I2C=y > +CONFIG_SPL_POWER=y > +CONFIG_SPL_WATCHDOG=y > +CONFIG_SYS_PROMPT="u-boot=> " > +# CONFIG_CMD_EXPORTENV is not set > +# CONFIG_CMD_IMPORTENV is not set > +CONFIG_CMD_ERASEENV=y > +# CONFIG_CMD_CRC32 is not set > +CONFIG_CMD_CLK=y > +CONFIG_CMD_FUSE=y > +CONFIG_CMD_GPIO=y > +CONFIG_CMD_I2C=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_CACHE=y > +CONFIG_CMD_REGULATOR=y > +CONFIG_CMD_EXT4_WRITE=y > +CONFIG_OF_CONTROL=y > +CONFIG_SPL_OF_CONTROL=y > +CONFIG_ENV_OVERWRITE=y > +CONFIG_ENV_IS_IN_MMC=y > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y > +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y > +CONFIG_SPL_DM=y > +CONFIG_SPL_CLK_IMX8MN=y > +CONFIG_CLK_IMX8MN=y > +CONFIG_MXC_GPIO=y > +CONFIG_DM_I2C=y > +CONFIG_SUPPORT_EMMC_BOOT=y > +CONFIG_MMC_IO_VOLTAGE=y > +CONFIG_MMC_UHS_SUPPORT=y > +CONFIG_MMC_HS400_ES_SUPPORT=y > +CONFIG_MMC_HS400_SUPPORT=y > +CONFIG_FSL_USDHC=y > +CONFIG_DM_SPI_FLASH=y > +CONFIG_SPI_FLASH_SFDP_SUPPORT=y > +CONFIG_SPI_FLASH_STMICRO=y > +CONFIG_PHYLIB=y > +CONFIG_PHY_ATHEROS=y > +CONFIG_DM_ETH=y > +CONFIG_DM_ETH_PHY=y > +CONFIG_PHY_GIGE=y > +CONFIG_FEC_MXC=y > +CONFIG_MII=y > +CONFIG_PINCTRL=y > +CONFIG_SPL_PINCTRL=y > +CONFIG_PINCTRL_IMX8M=y > +CONFIG_DM_PMIC=y > +CONFIG_SPL_DM_PMIC_PCA9450=y > +CONFIG_DM_REGULATOR=y > +CONFIG_DM_REGULATOR_FIXED=y > +CONFIG_DM_REGULATOR_GPIO=y > +# CONFIG_SPECIFY_CONSOLE_INDEX is not set > +CONFIG_DM_SERIAL=y > +# CONFIG_SPL_DM_SERIAL is not set > +CONFIG_MXC_UART=y > +CONFIG_SPI=y > +CONFIG_DM_SPI=y > +CONFIG_NXP_FSPI=y > +CONFIG_SYSRESET=y > +CONFIG_SPL_SYSRESET=y > +CONFIG_SYSRESET_PSCI=y > +CONFIG_SYSRESET_WATCHDOG=y > +CONFIG_DM_THERMAL=y > +CONFIG_IMX_WATCHDOG=y > diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h > index 805ae2a751..34278e2c84 100644 > --- a/include/configs/imx8mn_evk.h > +++ b/include/configs/imx8mn_evk.h > @@ -73,7 +73,11 @@ > > #define CONFIG_SYS_SDRAM_BASE 0x40000000 > #define PHYS_SDRAM 0x40000000 > +#ifdef CONFIG_TARGET_IMX8MN_DDR3L_EVK > +#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ > +#else > #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ > +#endif > > #define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support 2022-06-13 21:10 [PATCH v4] imx: add i.MX8MN DDR3L evk board support Heiko Thiery 2022-06-14 1:47 ` Peng Fan (OSS) @ 2022-06-14 6:55 ` Michael Nazzareno Trimarchi 2022-06-14 11:50 ` Heiko Thiery 2022-06-15 6:23 ` Heiko Thiery 1 sibling, 2 replies; 15+ messages in thread From: Michael Nazzareno Trimarchi @ 2022-06-14 6:55 UTC (permalink / raw) To: Heiko Thiery Cc: u-boot, Ying-Chun Liu, Peng Fan, Fabio Estevam, Marek Vasut, Marcel Ziswiler, Tim Harvey, Sean Anderson, Thomas Schäfer, Stefano Babic, Fabio Estevam Hi On Mon, Jun 13, 2022 at 11:10 PM Heiko Thiery <heiko.thiery@gmail.com> wrote: > > Add the support for the 8MNANOD3L-EVK board. The board has an i.MX8MNano > UltraLite Quad SoC and uses 1GB DDR3L memory. > > U-Boot SPL 2022.07-rc4-00017-gcf594ebce1 (Jun 13 2022 - 22:40:31 +0200) > Normal Boot > WDT: Started watchdog@30280000 with servicing (60s timeout) > Trying to boot from BOOTROM > image offset 0x8000, pagesize 0x200, ivt offset 0x0 > NOTICE: BL31: v2.6(release):v2.6-5-g9b1a4d832 > NOTICE: BL31: Built : 14:03:53, May 10 2022 > > U-Boot 2022.07-rc4-00017-gcf594ebce1 (Jun 13 2022 - 22:40:31 +0200) > > CPU: Freescale i.MX8MNano UltraLite Quad rev1.0 at 1200 MHz > Reset cause: WDOG > Model: NXP i.MX8MNano DDR3L EVK board > DRAM: 1 GiB > Core: 142 devices, 19 uclasses, devicetree: separate > WDT: Started watchdog@30280000 with servicing (60s timeout) > MMC: FSL_SDHC: 1, FSL_SDHC: 2 > Loading Environment from MMC... OK > In: serial@30890000 > Out: serial@30890000 > Err: serial@30890000 > Net: eth0: ethernet@30be0000 > Hit any key to stop autoboot: 0 > > Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com> > Reviewed-by: Fabio Estevam <festevam@denx.de> > --- > v4: > - rebase on current master to fix merge conflicts > - remove config options from defconfig > - enable SPL_DM_SERIAL > - include imx8mn-ddr4-evk-u-boot.dtsi in imx8mn-ddr3l-evk-u-boot.dtsi > v3: > - fix config option description in Kconfig (TARGET_IMX8MN_DDR3L_EVK) > v2: > - change license formatting (thanks Marcel) > > arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi | 34 + > arch/arm/dts/imx8mn-ddr3l-evk.dts | 114 +++ > arch/arm/dts/imx8mn-u-boot.dtsi | 12 + > arch/arm/mach-imx/imx8m/Kconfig | 7 + > board/freescale/imx8mn_evk/Kconfig | 2 +- > board/freescale/imx8mn_evk/Makefile | 1 + > board/freescale/imx8mn_evk/ddr3l_timing.c | 943 ++++++++++++++++++++++ > board/freescale/imx8mn_evk/spl.c | 9 + > configs/imx8mn_ddr3l_evk_defconfig | 95 +++ > include/configs/imx8mn_evk.h | 4 + > 10 files changed, 1220 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi > create mode 100644 arch/arm/dts/imx8mn-ddr3l-evk.dts > create mode 100644 board/freescale/imx8mn_evk/ddr3l_timing.c > create mode 100644 configs/imx8mn_ddr3l_evk_defconfig > > diff --git a/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi > new file mode 100644 > index 0000000000..b9192515e5 > --- /dev/null > +++ b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi > @@ -0,0 +1,34 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT > + > +#include "imx8mn-u-boot.dtsi" > +#include "imx8mn-ddr4-evk-u-boot.dtsi" > + > + > +&{/soc@0} { > + u-boot,dm-pre-reloc; > + u-boot,dm-spl; > +}; > + > +&clk { > + u-boot,dm-spl; > + u-boot,dm-pre-reloc; > + /delete-property/ assigned-clocks; > + /delete-property/ assigned-clock-parents; > + /delete-property/ assigned-clock-rates; > +}; > + > +&i2c1 { > + u-boot,dm-spl; > +}; > + > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { > + u-boot,dm-spl; > +}; > + > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { > + u-boot,dm-spl; > +}; > + > +&wdog1 { > + u-boot,dm-spl; > +}; > diff --git a/arch/arm/dts/imx8mn-ddr3l-evk.dts b/arch/arm/dts/imx8mn-ddr3l-evk.dts > new file mode 100644 > index 0000000000..4cdc03c8f2 > --- /dev/null > +++ b/arch/arm/dts/imx8mn-ddr3l-evk.dts > @@ -0,0 +1,114 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT > + > +/dts-v1/; > + > +#include "imx8mn.dtsi" > +#include "imx8mn-evk.dtsi" > +#include <dt-bindings/interrupt-controller/irq.h> > + > +/ { > + model = "NXP i.MX8MNano DDR3L EVK board"; > + compatible = "fsl,imx8mn-ddr3l-evk", "fsl,imx8mn"; > +}; > + > +&A53_0 { > + cpu-supply = <&buck1>; > +}; > + > +&A53_1 { > + cpu-supply = <&buck1>; > +}; > + > +&A53_2 { > + cpu-supply = <&buck1>; > +}; > + > +&A53_3 { > + cpu-supply = <&buck1>; > +}; > + > +&i2c1 { > + pmic: pmic@25 { > + compatible = "nxp,pca9450b"; > + reg = <0x25>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pmic>; > + interrupt-parent = <&gpio1>; > + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; > + > + regulators { > + buck1: BUCK1 { > + regulator-name = "VDD_SOC_0V9"; > + regulator-min-microvolt = <850000>; > + regulator-max-microvolt = <950000>; > + regulator-boot-on; > + regulator-always-on; > + regulator-ramp-delay = <3125>; > + }; > + > + buck4: BUCK4 { > + regulator-name = "VDD_3V3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + buck5: BUCK5 { > + regulator-name = "VDD_1V8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + buck6: BUCK6 { > + regulator-name = "NVCC_DRAM_1V35"; > + regulator-min-microvolt = <1350000>; > + regulator-max-microvolt = <1350000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo1: LDO1 { > + regulator-name = "NVCC_SNVS_1V8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo2: LDO2 { > + regulator-name = "VDD_SNVS_0V8"; > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <800000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo3: LDO3 { > + regulator-name = "VDDA_1V8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo4: LDO4 { > + regulator-name = "VDD_PHY_1V2"; > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1200000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo5: LDO5 { > + regulator-name = "NVCC_SD2"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3300000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + }; > + }; > +}; > diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi > index 7b591085a0..9286bdace0 100644 > --- a/arch/arm/dts/imx8mn-u-boot.dtsi > +++ b/arch/arm/dts/imx8mn-u-boot.dtsi > @@ -151,6 +151,18 @@ > size = <0x4000>; > }; > }; > +#elif CONFIG_IMX8M_DDR3L > +&u_boot_spl_ddr { > + blob_1: blob-ext@1 { > + filename = "ddr3_imem_1d.bin"; > + size = <0x8000>; > + }; > + > + blob_2: blob-ext@2 { > + filename = "ddr3_dmem_1d.bin"; > + size = <0x4000>; > + }; > +}; > #else > #error "no valid ddr config selected" > #endif > diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig > index ef8518c06b..aa386c8f36 100644 > --- a/arch/arm/mach-imx/imx8m/Kconfig > +++ b/arch/arm/mach-imx/imx8m/Kconfig > @@ -140,6 +140,13 @@ config TARGET_IMX8MN_DDR4_EVK > select FSL_CAAM > select SPL_CRYPTO if SPL > > +config TARGET_IMX8MN_DDR3L_EVK > + bool "imx8mn DDR3L EVK board" > + select BINMAN > + select IMX8MN > + select SUPPORT_SPL > + select IMX8M_DDR3L > + > config TARGET_IMX8MN_VENICE > bool "Support Gateworks Venice iMX8M Nano module" > select BINMAN > diff --git a/board/freescale/imx8mn_evk/Kconfig b/board/freescale/imx8mn_evk/Kconfig > index 6596fb5c6d..38312a3662 100644 > --- a/board/freescale/imx8mn_evk/Kconfig > +++ b/board/freescale/imx8mn_evk/Kconfig > @@ -1,4 +1,4 @@ > -if TARGET_IMX8MN_EVK || TARGET_IMX8MN_DDR4_EVK > +if TARGET_IMX8MN_EVK || TARGET_IMX8MN_DDR4_EVK || TARGET_IMX8MN_DDR3L_EVK > > config SYS_BOARD > default "imx8mn_evk" > diff --git a/board/freescale/imx8mn_evk/Makefile b/board/freescale/imx8mn_evk/Makefile > index 42d1179724..ad3ef8edd6 100644 > --- a/board/freescale/imx8mn_evk/Makefile > +++ b/board/freescale/imx8mn_evk/Makefile > @@ -14,5 +14,6 @@ obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing_ld.o > else > obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o > obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o > +obj-$(CONFIG_IMX8M_DDR3L) += ddr3l_timing.o > endif > endif > diff --git a/board/freescale/imx8mn_evk/ddr3l_timing.c b/board/freescale/imx8mn_evk/ddr3l_timing.c > new file mode 100644 > index 0000000000..0fe1f6a42d > --- /dev/null > +++ b/board/freescale/imx8mn_evk/ddr3l_timing.c > @@ -0,0 +1,943 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +/* > + * Copyright 2019 NXP > + * > + * Generated code from MX8M_DDR_tool > + * > + * Align with uboot version: > + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga > + * For imx_v2019.04_5.4.x and above version: > + * please replace #include <asm/arch/imx8m_ddr.h> with #include <asm/arch/ddr.h> > + */ > + > +#include <linux/kernel.h> > +#include <asm/arch/ddr.h> > + > +struct dram_cfg_param ddr_ddrc_cfg[] = { > + /** Initialize DDRC registers **/ > + { 0x3d400304, 0x1 }, > + { 0x3d400030, 0x20 }, > + { 0x3d400000, 0xa1040001 }, > + { 0x3d400064, 0x61008c }, > + { 0x3d4000d0, 0xc00200c5 }, > + { 0x3d4000d4, 0x1000b }, > + { 0x3d4000dc, 0x1d700004 }, > + { 0x3d4000e0, 0x180000 }, > + { 0x3d4000e4, 0x90000 }, > + { 0x3d4000f0, 0x0 }, > + { 0x3d4000f4, 0xee5 }, > + { 0x3d400100, 0xc101b0e }, > + { 0x3d400104, 0x30314 }, > + { 0x3d400108, 0x4060509 }, > + { 0x3d40010c, 0x2006 }, > + { 0x3d400110, 0x6020306 }, > + { 0x3d400114, 0x4040302 }, > + { 0x3d400120, 0x909 }, > + { 0x3d400180, 0x40800020 }, > + { 0x3d400184, 0xc350 }, > + { 0x3d400190, 0x3868203 }, > + { 0x3d400194, 0x20303 }, > + { 0x3d4001b4, 0x603 }, > + { 0x3d400198, 0x7000000 }, > + { 0x3d4001b0, 0x11 }, > + { 0x3d4001a0, 0x400018 }, > + { 0x3d4001a4, 0x5003c }, > + { 0x3d4001a8, 0x80000000 }, > + { 0x3d4001c4, 0x0 }, > + { 0x3d400200, 0x1f }, > + { 0x3d400204, 0x80808 }, > + { 0x3d400208, 0x0 }, > + { 0x3d40020c, 0x0 }, > + { 0x3d400210, 0x1f1f }, > + { 0x3d400214, 0x7070707 }, > + { 0x3d400218, 0x7070707 }, > + { 0x3d400240, 0x600060c }, > + { 0x3d400244, 0x1323 }, > + { 0x3d400400, 0x100 }, > + { 0x3d400250, 0x7ab50b07 }, > + { 0x3d400254, 0x22 }, > + { 0x3d40025c, 0x7b00665e }, > + { 0x3d400264, 0xb0000040 }, > + { 0x3d40026c, 0x50000a0c }, > + { 0x3d400300, 0x17 }, > + { 0x3d40036c, 0x10000 }, > + { 0x3d400404, 0x3051 }, > + { 0x3d400408, 0x61d2 }, > + { 0x3d400494, 0xe00 }, > + { 0x3d400498, 0x7ff }, > + { 0x3d40049c, 0xe00 }, > + { 0x3d4004a0, 0x7ff }, > + { 0x3d402064, 0x28003b }, > + { 0x3d4020dc, 0x12200004 }, > + { 0x3d4020e0, 0x0 }, > + { 0x3d402100, 0x7090b07 }, > + { 0x3d402104, 0x20209 }, > + { 0x3d402108, 0x3030407 }, > + { 0x3d40210c, 0x2006 }, > + { 0x3d402110, 0x3020203 }, > + { 0x3d402114, 0x3030202 }, > + { 0x3d402120, 0x909 }, > + { 0x3d402180, 0x40800020 }, > + { 0x3d402190, 0x3818200 }, > + { 0x3d402194, 0x20303 }, > + { 0x3d4021b4, 0x100 }, > + { 0x3d402240, 0x6000604 }, > + { 0x3d4020f4, 0xee5 }, > + { 0x3d400028, 0x1 }, > +}; > + > +/* PHY Initialize Configuration */ > +struct dram_cfg_param ddr_ddrphy_cfg[] = { > + { 0x1005f, 0x3ff }, > + { 0x1015f, 0x3ff }, > + { 0x1105f, 0x3ff }, > + { 0x1115f, 0x3ff }, > + { 0x11005f, 0x3ff }, > + { 0x11015f, 0x3ff }, > + { 0x11105f, 0x3ff }, > + { 0x11115f, 0x3ff }, > + { 0x55, 0x3ff }, > + { 0x1055, 0x3ff }, > + { 0x2055, 0x3ff }, > + { 0x3055, 0x3ff }, > + { 0x4055, 0xff }, > + { 0x5055, 0xff }, > + { 0x6055, 0x3ff }, > + { 0x7055, 0x3ff }, > + { 0x8055, 0x3ff }, > + { 0x9055, 0x3ff }, > + { 0x200c5, 0xb }, > + { 0x1200c5, 0x7 }, > + { 0x2002e, 0x1 }, > + { 0x12002e, 0x1 }, > + { 0x20024, 0x0 }, > + { 0x2003a, 0x0 }, > + { 0x120024, 0x0 }, > + { 0x2003a, 0x0 }, > + { 0x20056, 0xa }, > + { 0x120056, 0xa }, > + { 0x1004d, 0x208 }, > + { 0x1014d, 0x208 }, > + { 0x1104d, 0x208 }, > + { 0x1114d, 0x208 }, > + { 0x11004d, 0x208 }, > + { 0x11014d, 0x208 }, > + { 0x11104d, 0x208 }, > + { 0x11114d, 0x208 }, > + { 0x10049, 0xe38 }, > + { 0x10149, 0xe38 }, > + { 0x11049, 0xe38 }, > + { 0x11149, 0xe38 }, > + { 0x110049, 0xe38 }, > + { 0x110149, 0xe38 }, > + { 0x111049, 0xe38 }, > + { 0x111149, 0xe38 }, > + { 0x43, 0x63 }, > + { 0x1043, 0x63 }, > + { 0x2043, 0x63 }, > + { 0x3043, 0x63 }, > + { 0x4043, 0x63 }, > + { 0x5043, 0x63 }, > + { 0x6043, 0x63 }, > + { 0x7043, 0x63 }, > + { 0x8043, 0x63 }, > + { 0x9043, 0x63 }, > + { 0x20018, 0x1 }, > + { 0x20075, 0x0 }, > + { 0x20050, 0x0 }, > + { 0x20008, 0x190 }, > + { 0x120008, 0xa7 }, > + { 0x20088, 0x9 }, > + { 0x200b2, 0x32c }, > + { 0x10043, 0x581 }, > + { 0x10143, 0x581 }, > + { 0x11043, 0x581 }, > + { 0x11143, 0x581 }, > + { 0x1200b2, 0x32c }, > + { 0x110043, 0x581 }, > + { 0x110143, 0x581 }, > + { 0x111043, 0x581 }, > + { 0x111143, 0x581 }, > + { 0x200fa, 0x1 }, > + { 0x1200fa, 0x1 }, > + { 0x20019, 0x5 }, > + { 0x120019, 0x5 }, > + { 0x200f0, 0x5555 }, > + { 0x200f1, 0x5555 }, > + { 0x200f2, 0x5555 }, > + { 0x200f3, 0x5555 }, > + { 0x200f4, 0x5555 }, > + { 0x200f5, 0x5555 }, > + { 0x200f6, 0x5555 }, > + { 0x200f7, 0xf000 }, > + { 0x20025, 0x0 }, > + { 0x2007d, 0x212 }, > + { 0x12007d, 0x212 }, > + { 0x2007c, 0x61 }, > + { 0x12007c, 0x61 }, > + { 0x1004a, 0x500 }, > + { 0x1104a, 0x500 }, > + { 0x2002c, 0x0 }, > +}; > + > +/* ddr phy trained csr */ > +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { > + {0x0200b2,0x0}, > + {0x1200b2,0x0}, > + {0x2200b2,0x0}, > + {0x0200cb,0x0}, > + {0x010043,0x0}, > + {0x110043,0x0}, > + {0x210043,0x0}, > + {0x010143,0x0}, > + {0x110143,0x0}, > + {0x210143,0x0}, > + {0x011043,0x0}, > + {0x111043,0x0}, > + {0x211043,0x0}, > + {0x011143,0x0}, > + {0x111143,0x0}, > + {0x211143,0x0}, > + {0x000080,0x0}, > + {0x100080,0x0}, > + {0x200080,0x0}, > + {0x001080,0x0}, > + {0x101080,0x0}, > + {0x201080,0x0}, > + {0x002080,0x0}, > + {0x102080,0x0}, > + {0x202080,0x0}, > + {0x003080,0x0}, > + {0x103080,0x0}, > + {0x203080,0x0}, > + {0x004080,0x0}, > + {0x104080,0x0}, > + {0x204080,0x0}, > + {0x005080,0x0}, > + {0x105080,0x0}, > + {0x205080,0x0}, > + {0x006080,0x0}, > + {0x106080,0x0}, > + {0x206080,0x0}, > + {0x007080,0x0}, > + {0x107080,0x0}, > + {0x207080,0x0}, > + {0x008080,0x0}, > + {0x108080,0x0}, > + {0x208080,0x0}, > + {0x009080,0x0}, > + {0x109080,0x0}, > + {0x209080,0x0}, > + {0x010080,0x0}, > + {0x110080,0x0}, > + {0x210080,0x0}, > + {0x010180,0x0}, > + {0x110180,0x0}, > + {0x210180,0x0}, > + {0x010081,0x0}, > + {0x110081,0x0}, > + {0x210081,0x0}, > + {0x010181,0x0}, > + {0x110181,0x0}, > + {0x210181,0x0}, > + {0x010082,0x0}, > + {0x110082,0x0}, > + {0x210082,0x0}, > + {0x010182,0x0}, > + {0x110182,0x0}, > + {0x210182,0x0}, > + {0x010083,0x0}, > + {0x110083,0x0}, > + {0x210083,0x0}, > + {0x010183,0x0}, > + {0x110183,0x0}, > + {0x210183,0x0}, > + {0x011080,0x0}, > + {0x111080,0x0}, > + {0x211080,0x0}, > + {0x011180,0x0}, > + {0x111180,0x0}, > + {0x211180,0x0}, > + {0x011081,0x0}, > + {0x111081,0x0}, > + {0x211081,0x0}, > + {0x011181,0x0}, > + {0x111181,0x0}, > + {0x211181,0x0}, > + {0x011082,0x0}, > + {0x111082,0x0}, > + {0x211082,0x0}, > + {0x011182,0x0}, > + {0x111182,0x0}, > + {0x211182,0x0}, > + {0x011083,0x0}, > + {0x111083,0x0}, > + {0x211083,0x0}, > + {0x011183,0x0}, > + {0x111183,0x0}, > + {0x211183,0x0}, > + {0x0100d0,0x0}, > + {0x1100d0,0x0}, > + {0x2100d0,0x0}, > + {0x0101d0,0x0}, > + {0x1101d0,0x0}, > + {0x2101d0,0x0}, > + {0x0100d1,0x0}, > + {0x1100d1,0x0}, > + {0x2100d1,0x0}, > + {0x0101d1,0x0}, > + {0x1101d1,0x0}, > + {0x2101d1,0x0}, > + {0x0100d2,0x0}, > + {0x1100d2,0x0}, > + {0x2100d2,0x0}, > + {0x0101d2,0x0}, > + {0x1101d2,0x0}, > + {0x2101d2,0x0}, > + {0x0100d3,0x0}, > + {0x1100d3,0x0}, > + {0x2100d3,0x0}, > + {0x0101d3,0x0}, > + {0x1101d3,0x0}, > + {0x2101d3,0x0}, > + {0x0110d0,0x0}, > + {0x1110d0,0x0}, > + {0x2110d0,0x0}, > + {0x0111d0,0x0}, > + {0x1111d0,0x0}, > + {0x2111d0,0x0}, > + {0x0110d1,0x0}, > + {0x1110d1,0x0}, > + {0x2110d1,0x0}, > + {0x0111d1,0x0}, > + {0x1111d1,0x0}, > + {0x2111d1,0x0}, > + {0x0110d2,0x0}, > + {0x1110d2,0x0}, > + {0x2110d2,0x0}, > + {0x0111d2,0x0}, > + {0x1111d2,0x0}, > + {0x2111d2,0x0}, > + {0x0110d3,0x0}, > + {0x1110d3,0x0}, > + {0x2110d3,0x0}, > + {0x0111d3,0x0}, > + {0x1111d3,0x0}, > + {0x2111d3,0x0}, > + {0x010068,0x0}, > + {0x010168,0x0}, > + {0x010268,0x0}, > + {0x010368,0x0}, > + {0x010468,0x0}, > + {0x010568,0x0}, > + {0x010668,0x0}, > + {0x010768,0x0}, > + {0x010868,0x0}, > + {0x010069,0x0}, > + {0x010169,0x0}, > + {0x010269,0x0}, > + {0x010369,0x0}, > + {0x010469,0x0}, > + {0x010569,0x0}, > + {0x010669,0x0}, > + {0x010769,0x0}, > + {0x010869,0x0}, > + {0x01006a,0x0}, > + {0x01016a,0x0}, > + {0x01026a,0x0}, > + {0x01036a,0x0}, > + {0x01046a,0x0}, > + {0x01056a,0x0}, > + {0x01066a,0x0}, > + {0x01076a,0x0}, > + {0x01086a,0x0}, > + {0x01006b,0x0}, > + {0x01016b,0x0}, > + {0x01026b,0x0}, > + {0x01036b,0x0}, > + {0x01046b,0x0}, > + {0x01056b,0x0}, > + {0x01066b,0x0}, > + {0x01076b,0x0}, > + {0x01086b,0x0}, > + {0x011068,0x0}, > + {0x011168,0x0}, > + {0x011268,0x0}, > + {0x011368,0x0}, > + {0x011468,0x0}, > + {0x011568,0x0}, > + {0x011668,0x0}, > + {0x011768,0x0}, > + {0x011868,0x0}, > + {0x011069,0x0}, > + {0x011169,0x0}, > + {0x011269,0x0}, > + {0x011369,0x0}, > + {0x011469,0x0}, > + {0x011569,0x0}, > + {0x011669,0x0}, > + {0x011769,0x0}, > + {0x011869,0x0}, > + {0x01106a,0x0}, > + {0x01116a,0x0}, > + {0x01126a,0x0}, > + {0x01136a,0x0}, > + {0x01146a,0x0}, > + {0x01156a,0x0}, > + {0x01166a,0x0}, > + {0x01176a,0x0}, > + {0x01186a,0x0}, > + {0x01106b,0x0}, > + {0x01116b,0x0}, > + {0x01126b,0x0}, > + {0x01136b,0x0}, > + {0x01146b,0x0}, > + {0x01156b,0x0}, > + {0x01166b,0x0}, > + {0x01176b,0x0}, > + {0x01186b,0x0}, > + {0x01008c,0x0}, > + {0x11008c,0x0}, > + {0x21008c,0x0}, > + {0x01018c,0x0}, > + {0x11018c,0x0}, > + {0x21018c,0x0}, > + {0x01008d,0x0}, > + {0x11008d,0x0}, > + {0x21008d,0x0}, > + {0x01018d,0x0}, > + {0x11018d,0x0}, > + {0x21018d,0x0}, > + {0x01008e,0x0}, > + {0x11008e,0x0}, > + {0x21008e,0x0}, > + {0x01018e,0x0}, > + {0x11018e,0x0}, > + {0x21018e,0x0}, > + {0x01008f,0x0}, > + {0x11008f,0x0}, > + {0x21008f,0x0}, > + {0x01018f,0x0}, > + {0x11018f,0x0}, > + {0x21018f,0x0}, > + {0x01108c,0x0}, > + {0x11108c,0x0}, > + {0x21108c,0x0}, > + {0x01118c,0x0}, > + {0x11118c,0x0}, > + {0x21118c,0x0}, > + {0x01108d,0x0}, > + {0x11108d,0x0}, > + {0x21108d,0x0}, > + {0x01118d,0x0}, > + {0x11118d,0x0}, > + {0x21118d,0x0}, > + {0x01108e,0x0}, > + {0x11108e,0x0}, > + {0x21108e,0x0}, > + {0x01118e,0x0}, > + {0x11118e,0x0}, > + {0x21118e,0x0}, > + {0x01108f,0x0}, > + {0x11108f,0x0}, > + {0x21108f,0x0}, > + {0x01118f,0x0}, > + {0x11118f,0x0}, > + {0x21118f,0x0}, > + {0x0100c0,0x0}, > + {0x1100c0,0x0}, > + {0x2100c0,0x0}, > + {0x0101c0,0x0}, > + {0x1101c0,0x0}, > + {0x2101c0,0x0}, > + {0x0102c0,0x0}, > + {0x1102c0,0x0}, > + {0x2102c0,0x0}, > + {0x0103c0,0x0}, > + {0x1103c0,0x0}, > + {0x2103c0,0x0}, > + {0x0104c0,0x0}, > + {0x1104c0,0x0}, > + {0x2104c0,0x0}, > + {0x0105c0,0x0}, > + {0x1105c0,0x0}, > + {0x2105c0,0x0}, > + {0x0106c0,0x0}, > + {0x1106c0,0x0}, > + {0x2106c0,0x0}, > + {0x0107c0,0x0}, > + {0x1107c0,0x0}, > + {0x2107c0,0x0}, > + {0x0108c0,0x0}, > + {0x1108c0,0x0}, > + {0x2108c0,0x0}, > + {0x0100c1,0x0}, > + {0x1100c1,0x0}, > + {0x2100c1,0x0}, > + {0x0101c1,0x0}, > + {0x1101c1,0x0}, > + {0x2101c1,0x0}, > + {0x0102c1,0x0}, > + {0x1102c1,0x0}, > + {0x2102c1,0x0}, > + {0x0103c1,0x0}, > + {0x1103c1,0x0}, > + {0x2103c1,0x0}, > + {0x0104c1,0x0}, > + {0x1104c1,0x0}, > + {0x2104c1,0x0}, > + {0x0105c1,0x0}, > + {0x1105c1,0x0}, > + {0x2105c1,0x0}, > + {0x0106c1,0x0}, > + {0x1106c1,0x0}, > + {0x2106c1,0x0}, > + {0x0107c1,0x0}, > + {0x1107c1,0x0}, > + {0x2107c1,0x0}, > + {0x0108c1,0x0}, > + {0x1108c1,0x0}, > + {0x2108c1,0x0}, > + {0x0100c2,0x0}, > + {0x1100c2,0x0}, > + {0x2100c2,0x0}, > + {0x0101c2,0x0}, > + {0x1101c2,0x0}, > + {0x2101c2,0x0}, > + {0x0102c2,0x0}, > + {0x1102c2,0x0}, > + {0x2102c2,0x0}, > + {0x0103c2,0x0}, > + {0x1103c2,0x0}, > + {0x2103c2,0x0}, > + {0x0104c2,0x0}, > + {0x1104c2,0x0}, > + {0x2104c2,0x0}, > + {0x0105c2,0x0}, > + {0x1105c2,0x0}, > + {0x2105c2,0x0}, > + {0x0106c2,0x0}, > + {0x1106c2,0x0}, > + {0x2106c2,0x0}, > + {0x0107c2,0x0}, > + {0x1107c2,0x0}, > + {0x2107c2,0x0}, > + {0x0108c2,0x0}, > + {0x1108c2,0x0}, > + {0x2108c2,0x0}, > + {0x0100c3,0x0}, > + {0x1100c3,0x0}, > + {0x2100c3,0x0}, > + {0x0101c3,0x0}, > + {0x1101c3,0x0}, > + {0x2101c3,0x0}, > + {0x0102c3,0x0}, > + {0x1102c3,0x0}, > + {0x2102c3,0x0}, > + {0x0103c3,0x0}, > + {0x1103c3,0x0}, > + {0x2103c3,0x0}, > + {0x0104c3,0x0}, > + {0x1104c3,0x0}, > + {0x2104c3,0x0}, > + {0x0105c3,0x0}, > + {0x1105c3,0x0}, > + {0x2105c3,0x0}, > + {0x0106c3,0x0}, > + {0x1106c3,0x0}, > + {0x2106c3,0x0}, > + {0x0107c3,0x0}, > + {0x1107c3,0x0}, > + {0x2107c3,0x0}, > + {0x0108c3,0x0}, > + {0x1108c3,0x0}, > + {0x2108c3,0x0}, > + {0x0110c0,0x0}, > + {0x1110c0,0x0}, > + {0x2110c0,0x0}, > + {0x0111c0,0x0}, > + {0x1111c0,0x0}, > + {0x2111c0,0x0}, > + {0x0112c0,0x0}, > + {0x1112c0,0x0}, > + {0x2112c0,0x0}, > + {0x0113c0,0x0}, > + {0x1113c0,0x0}, > + {0x2113c0,0x0}, > + {0x0114c0,0x0}, > + {0x1114c0,0x0}, > + {0x2114c0,0x0}, > + {0x0115c0,0x0}, > + {0x1115c0,0x0}, > + {0x2115c0,0x0}, > + {0x0116c0,0x0}, > + {0x1116c0,0x0}, > + {0x2116c0,0x0}, > + {0x0117c0,0x0}, > + {0x1117c0,0x0}, > + {0x2117c0,0x0}, > + {0x0118c0,0x0}, > + {0x1118c0,0x0}, > + {0x2118c0,0x0}, > + {0x0110c1,0x0}, > + {0x1110c1,0x0}, > + {0x2110c1,0x0}, > + {0x0111c1,0x0}, > + {0x1111c1,0x0}, > + {0x2111c1,0x0}, > + {0x0112c1,0x0}, > + {0x1112c1,0x0}, > + {0x2112c1,0x0}, > + {0x0113c1,0x0}, > + {0x1113c1,0x0}, > + {0x2113c1,0x0}, > + {0x0114c1,0x0}, > + {0x1114c1,0x0}, > + {0x2114c1,0x0}, > + {0x0115c1,0x0}, > + {0x1115c1,0x0}, > + {0x2115c1,0x0}, > + {0x0116c1,0x0}, > + {0x1116c1,0x0}, > + {0x2116c1,0x0}, > + {0x0117c1,0x0}, > + {0x1117c1,0x0}, > + {0x2117c1,0x0}, > + {0x0118c1,0x0}, > + {0x1118c1,0x0}, > + {0x2118c1,0x0}, > + {0x0110c2,0x0}, > + {0x1110c2,0x0}, > + {0x2110c2,0x0}, > + {0x0111c2,0x0}, > + {0x1111c2,0x0}, > + {0x2111c2,0x0}, > + {0x0112c2,0x0}, > + {0x1112c2,0x0}, > + {0x2112c2,0x0}, > + {0x0113c2,0x0}, > + {0x1113c2,0x0}, > + {0x2113c2,0x0}, > + {0x0114c2,0x0}, > + {0x1114c2,0x0}, > + {0x2114c2,0x0}, > + {0x0115c2,0x0}, > + {0x1115c2,0x0}, > + {0x2115c2,0x0}, > + {0x0116c2,0x0}, > + {0x1116c2,0x0}, > + {0x2116c2,0x0}, > + {0x0117c2,0x0}, > + {0x1117c2,0x0}, > + {0x2117c2,0x0}, > + {0x0118c2,0x0}, > + {0x1118c2,0x0}, > + {0x2118c2,0x0}, > + {0x0110c3,0x0}, > + {0x1110c3,0x0}, > + {0x2110c3,0x0}, > + {0x0111c3,0x0}, > + {0x1111c3,0x0}, > + {0x2111c3,0x0}, > + {0x0112c3,0x0}, > + {0x1112c3,0x0}, > + {0x2112c3,0x0}, > + {0x0113c3,0x0}, > + {0x1113c3,0x0}, > + {0x2113c3,0x0}, > + {0x0114c3,0x0}, > + {0x1114c3,0x0}, > + {0x2114c3,0x0}, > + {0x0115c3,0x0}, > + {0x1115c3,0x0}, > + {0x2115c3,0x0}, > + {0x0116c3,0x0}, > + {0x1116c3,0x0}, > + {0x2116c3,0x0}, > + {0x0117c3,0x0}, > + {0x1117c3,0x0}, > + {0x2117c3,0x0}, > + {0x0118c3,0x0}, > + {0x1118c3,0x0}, > + {0x2118c3,0x0}, > + {0x010020,0x0}, > + {0x110020,0x0}, > + {0x210020,0x0}, > + {0x011020,0x0}, > + {0x111020,0x0}, > + {0x211020,0x0}, > + {0x02007d,0x0}, > + {0x12007d,0x0}, > + {0x22007d,0x0}, > +}; > + > +/* P0 message block paremeter for training firmware */ > +struct dram_cfg_param ddr_fsp0_cfg[] = { > + { 0xd0000, 0x0 }, > + { 0x54003, 0x640 }, > + { 0x54004, 0x2 }, > + { 0x54005, 0x283c }, > + { 0x54006, 0x140 }, > + { 0x54007, 0x1000 }, > + { 0x54008, 0x101 }, > + { 0x5400b, 0x31f }, > + { 0x5400c, 0xc8 }, > + { 0x54012, 0x1 }, > + { 0x5402f, 0x1d70 }, > + { 0x54030, 0x4 }, > + { 0x54031, 0x18 }, > + { 0x5403a, 0x1323 }, > + { 0xd0000, 0x1 }, > +}; > + > + > +/* P1 message block paremeter for training firmware */ > +struct dram_cfg_param ddr_fsp1_cfg[] = { > + { 0xd0000, 0x0 }, > + { 0x54002, 0x1 }, > + { 0x54003, 0x29c }, > + { 0x54004, 0x2 }, > + { 0x54005, 0x283c }, > + { 0x54006, 0x140 }, > + { 0x54007, 0x1000 }, > + { 0x54008, 0x101 }, > + { 0x5400b, 0x21f }, > + { 0x5400c, 0xc8 }, > + { 0x54012, 0x1 }, > + { 0x5402f, 0x1220 }, > + { 0x54030, 0x4 }, > + { 0x5403a, 0x1323 }, > + { 0xd0000, 0x1 }, > +}; > + > +/* DRAM PHY init engine image */ > +struct dram_cfg_param ddr_phy_pie[] = { > + { 0xd0000, 0x0 }, > + { 0x90000, 0x10 }, > + { 0x90001, 0x400 }, > + { 0x90002, 0x10e }, > + { 0x90003, 0x0 }, > + { 0x90004, 0x0 }, > + { 0x90005, 0x8 }, > + { 0x90029, 0xb }, > + { 0x9002a, 0x480 }, > + { 0x9002b, 0x109 }, > + { 0x9002c, 0x8 }, > + { 0x9002d, 0x448 }, > + { 0x9002e, 0x139 }, > + { 0x9002f, 0x8 }, > + { 0x90030, 0x478 }, > + { 0x90031, 0x109 }, > + { 0x90032, 0x2 }, > + { 0x90033, 0x10 }, > + { 0x90034, 0x139 }, > + { 0x90035, 0xb }, > + { 0x90036, 0x7c0 }, > + { 0x90037, 0x139 }, > + { 0x90038, 0x44 }, > + { 0x90039, 0x633 }, > + { 0x9003a, 0x159 }, > + { 0x9003b, 0x14f }, > + { 0x9003c, 0x630 }, > + { 0x9003d, 0x159 }, > + { 0x9003e, 0x47 }, > + { 0x9003f, 0x633 }, > + { 0x90040, 0x149 }, > + { 0x90041, 0x4f }, > + { 0x90042, 0x633 }, > + { 0x90043, 0x179 }, > + { 0x90044, 0x8 }, > + { 0x90045, 0xe0 }, > + { 0x90046, 0x109 }, > + { 0x90047, 0x0 }, > + { 0x90048, 0x7c8 }, > + { 0x90049, 0x109 }, > + { 0x9004a, 0x0 }, > + { 0x9004b, 0x1 }, > + { 0x9004c, 0x8 }, > + { 0x9004d, 0x0 }, > + { 0x9004e, 0x45a }, > + { 0x9004f, 0x9 }, > + { 0x90050, 0x0 }, > + { 0x90051, 0x448 }, > + { 0x90052, 0x109 }, > + { 0x90053, 0x40 }, > + { 0x90054, 0x633 }, > + { 0x90055, 0x179 }, > + { 0x90056, 0x1 }, > + { 0x90057, 0x618 }, > + { 0x90058, 0x109 }, > + { 0x90059, 0x40c0 }, > + { 0x9005a, 0x633 }, > + { 0x9005b, 0x149 }, > + { 0x9005c, 0x8 }, > + { 0x9005d, 0x4 }, > + { 0x9005e, 0x48 }, > + { 0x9005f, 0x4040 }, > + { 0x90060, 0x633 }, > + { 0x90061, 0x149 }, > + { 0x90062, 0x0 }, > + { 0x90063, 0x4 }, > + { 0x90064, 0x48 }, > + { 0x90065, 0x40 }, > + { 0x90066, 0x633 }, > + { 0x90067, 0x149 }, > + { 0x90068, 0x10 }, > + { 0x90069, 0x4 }, > + { 0x9006a, 0x18 }, > + { 0x9006b, 0x0 }, > + { 0x9006c, 0x4 }, > + { 0x9006d, 0x78 }, > + { 0x9006e, 0x549 }, > + { 0x9006f, 0x633 }, > + { 0x90070, 0x159 }, > + { 0x90071, 0xd49 }, > + { 0x90072, 0x633 }, > + { 0x90073, 0x159 }, > + { 0x90074, 0x94a }, > + { 0x90075, 0x633 }, > + { 0x90076, 0x159 }, > + { 0x90077, 0x441 }, > + { 0x90078, 0x633 }, > + { 0x90079, 0x149 }, > + { 0x9007a, 0x42 }, > + { 0x9007b, 0x633 }, > + { 0x9007c, 0x149 }, > + { 0x9007d, 0x1 }, > + { 0x9007e, 0x633 }, > + { 0x9007f, 0x149 }, > + { 0x90080, 0x0 }, > + { 0x90081, 0xe0 }, > + { 0x90082, 0x109 }, > + { 0x90083, 0xa }, > + { 0x90084, 0x10 }, > + { 0x90085, 0x109 }, > + { 0x90086, 0x9 }, > + { 0x90087, 0x3c0 }, > + { 0x90088, 0x149 }, > + { 0x90089, 0x9 }, > + { 0x9008a, 0x3c0 }, > + { 0x9008b, 0x159 }, > + { 0x9008c, 0x18 }, > + { 0x9008d, 0x10 }, > + { 0x9008e, 0x109 }, > + { 0x9008f, 0x0 }, > + { 0x90090, 0x3c0 }, > + { 0x90091, 0x109 }, > + { 0x90092, 0x18 }, > + { 0x90093, 0x4 }, > + { 0x90094, 0x48 }, > + { 0x90095, 0x18 }, > + { 0x90096, 0x4 }, > + { 0x90097, 0x58 }, > + { 0x90098, 0xb }, > + { 0x90099, 0x10 }, > + { 0x9009a, 0x109 }, > + { 0x9009b, 0x1 }, > + { 0x9009c, 0x10 }, > + { 0x9009d, 0x109 }, > + { 0x9009e, 0x5 }, > + { 0x9009f, 0x7c0 }, > + { 0x900a0, 0x109 }, > + { 0x900a1, 0x0 }, > + { 0x900a2, 0x8140 }, > + { 0x900a3, 0x10c }, > + { 0x900a4, 0x10 }, > + { 0x900a5, 0x8138 }, > + { 0x900a6, 0x10c }, > + { 0x900a7, 0x8 }, > + { 0x900a8, 0x7c8 }, > + { 0x900a9, 0x101 }, > + { 0x900aa, 0x8 }, > + { 0x900ab, 0x448 }, > + { 0x900ac, 0x109 }, > + { 0x900ad, 0xf }, > + { 0x900ae, 0x7c0 }, > + { 0x900af, 0x109 }, > + { 0x900b0, 0x47 }, > + { 0x900b1, 0x630 }, > + { 0x900b2, 0x109 }, > + { 0x900b3, 0x8 }, > + { 0x900b4, 0x618 }, > + { 0x900b5, 0x109 }, > + { 0x900b6, 0x8 }, > + { 0x900b7, 0xe0 }, > + { 0x900b8, 0x109 }, > + { 0x900b9, 0x0 }, > + { 0x900ba, 0x7c8 }, > + { 0x900bb, 0x109 }, > + { 0x900bc, 0x8 }, > + { 0x900bd, 0x8140 }, > + { 0x900be, 0x10c }, > + { 0x900bf, 0x0 }, > + { 0x900c0, 0x1 }, > + { 0x900c1, 0x8 }, > + { 0x900c2, 0x8 }, > + { 0x900c3, 0x4 }, > + { 0x900c4, 0x8 }, > + { 0x900c5, 0x8 }, > + { 0x900c6, 0x7c8 }, > + { 0x900c7, 0x101 }, > + { 0x90006, 0x0 }, > + { 0x90007, 0x0 }, > + { 0x90008, 0x8 }, > + { 0x90009, 0x0 }, > + { 0x9000a, 0x0 }, > + { 0x9000b, 0x0 }, > + { 0xd00e7, 0x400 }, > + { 0x90017, 0x0 }, > + { 0x90026, 0x2b }, > + { 0x2000b, 0x32 }, > + { 0x2000c, 0x64 }, > + { 0x2000d, 0x3e8 }, > + { 0x2000e, 0x2c }, > + { 0x12000b, 0x14 }, > + { 0x12000c, 0x26 }, > + { 0x12000d, 0x1a1 }, > + { 0x12000e, 0x10 }, > + { 0x9000c, 0x0 }, > + { 0x9000d, 0x173 }, > + { 0x9000e, 0x60 }, > + { 0x9000f, 0x6110 }, > + { 0x90010, 0x2152 }, > + { 0x90011, 0xdfbd }, > + { 0x90012, 0xffff }, > + { 0x90013, 0x6152 }, > + { 0x20089, 0x1 }, > + { 0x20088, 0x19 }, > + { 0xc0080, 0x0 }, > + { 0xd0000, 0x1 } > +}; > + > +struct dram_fsp_msg ddr_dram_fsp_msg[] = { > + { > + /* P0 1600mts 1D */ > + .drate = 1600, > + .fw_type = FW_1D_IMAGE, > + .fsp_cfg = ddr_fsp0_cfg, > + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), > + }, > + { > + /* P1 667mts 1D */ > + .drate = 667, > + .fw_type = FW_1D_IMAGE, > + .fsp_cfg = ddr_fsp1_cfg, > + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), > + }, > +}; > + > +/* ddr timing config params */ > +struct dram_timing_info dram_timing = { > + .ddrc_cfg = ddr_ddrc_cfg, > + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), > + .ddrphy_cfg = ddr_ddrphy_cfg, > + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), > + .fsp_msg = ddr_dram_fsp_msg, > + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), > + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, > + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), > + .ddrphy_pie = ddr_phy_pie, > + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), > + .fsp_table = { 1600, 667, }, > +}; > + > diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c > index 14cb51368f..0d9909a662 100644 > --- a/board/freescale/imx8mn_evk/spl.c > +++ b/board/freescale/imx8mn_evk/spl.c > @@ -83,6 +83,15 @@ int power_init_board(void) > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK) > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */ > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); > + > + /* Disable the BUCK2 */ > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48); > + > + /* Set NVCC_DRAM to 1.35v */ > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E); > #else All this part is not done by the spl pmic driver? Michael > /* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */ > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); > diff --git a/configs/imx8mn_ddr3l_evk_defconfig b/configs/imx8mn_ddr3l_evk_defconfig > new file mode 100644 > index 0000000000..b69fcea0cb > --- /dev/null > +++ b/configs/imx8mn_ddr3l_evk_defconfig > @@ -0,0 +1,95 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_IMX8M=y > +CONFIG_SYS_TEXT_BASE=0x40200000 > +CONFIG_SYS_MALLOC_LEN=0x2000000 > +CONFIG_SPL_GPIO=y > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > +CONFIG_ENV_SIZE=0x1000 > +CONFIG_ENV_OFFSET=0x400000 > +CONFIG_DM_GPIO=y > +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr3l-evk" > +CONFIG_SPL_TEXT_BASE=0x912000 > +CONFIG_TARGET_IMX8MN_DDR3L_EVK=y > +CONFIG_SPL_SERIAL=y > +CONFIG_SPL_DRIVERS_MISC=y > +CONFIG_SPL=y > +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 > +CONFIG_SYS_LOAD_ADDR=0x42000000 > +CONFIG_DISTRO_DEFAULTS=y > +CONFIG_FIT=y > +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 > +CONFIG_SPL_LOAD_FIT=y > +# CONFIG_USE_SPL_FIT_GENERATOR is not set > +CONFIG_OF_SYSTEM_SETUP=y > +CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr3l-evk.dtb" > +CONFIG_ARCH_MISC_INIT=y > +CONFIG_BOARD_LATE_INIT=y > +CONFIG_SPL_BOARD_INIT=y > +CONFIG_SPL_BOOTROM_SUPPORT=y > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 > +CONFIG_SPL_I2C=y > +CONFIG_SPL_POWER=y > +CONFIG_SPL_WATCHDOG=y > +CONFIG_SYS_PROMPT="u-boot=> " > +# CONFIG_CMD_EXPORTENV is not set > +# CONFIG_CMD_IMPORTENV is not set > +CONFIG_CMD_ERASEENV=y > +# CONFIG_CMD_CRC32 is not set > +CONFIG_CMD_CLK=y > +CONFIG_CMD_FUSE=y > +CONFIG_CMD_GPIO=y > +CONFIG_CMD_I2C=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_CACHE=y > +CONFIG_CMD_REGULATOR=y > +CONFIG_CMD_EXT4_WRITE=y > +CONFIG_OF_CONTROL=y > +CONFIG_SPL_OF_CONTROL=y > +CONFIG_ENV_OVERWRITE=y > +CONFIG_ENV_IS_IN_MMC=y > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y > +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y > +CONFIG_SPL_DM=y > +CONFIG_SPL_CLK_IMX8MN=y > +CONFIG_CLK_IMX8MN=y > +CONFIG_MXC_GPIO=y > +CONFIG_DM_I2C=y > +CONFIG_SUPPORT_EMMC_BOOT=y > +CONFIG_MMC_IO_VOLTAGE=y > +CONFIG_MMC_UHS_SUPPORT=y > +CONFIG_MMC_HS400_ES_SUPPORT=y > +CONFIG_MMC_HS400_SUPPORT=y > +CONFIG_FSL_USDHC=y > +CONFIG_DM_SPI_FLASH=y > +CONFIG_SPI_FLASH_SFDP_SUPPORT=y > +CONFIG_SPI_FLASH_STMICRO=y > +CONFIG_PHYLIB=y > +CONFIG_PHY_ATHEROS=y > +CONFIG_DM_ETH=y > +CONFIG_DM_ETH_PHY=y > +CONFIG_PHY_GIGE=y > +CONFIG_FEC_MXC=y > +CONFIG_MII=y > +CONFIG_PINCTRL=y > +CONFIG_SPL_PINCTRL=y > +CONFIG_PINCTRL_IMX8M=y > +CONFIG_DM_PMIC=y > +CONFIG_SPL_DM_PMIC_PCA9450=y > +CONFIG_DM_REGULATOR=y > +CONFIG_DM_REGULATOR_FIXED=y > +CONFIG_DM_REGULATOR_GPIO=y > +# CONFIG_SPECIFY_CONSOLE_INDEX is not set > +CONFIG_DM_SERIAL=y > +# CONFIG_SPL_DM_SERIAL is not set > +CONFIG_MXC_UART=y > +CONFIG_SPI=y > +CONFIG_DM_SPI=y > +CONFIG_NXP_FSPI=y > +CONFIG_SYSRESET=y > +CONFIG_SPL_SYSRESET=y > +CONFIG_SYSRESET_PSCI=y > +CONFIG_SYSRESET_WATCHDOG=y > +CONFIG_DM_THERMAL=y > +CONFIG_IMX_WATCHDOG=y > diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h > index 805ae2a751..34278e2c84 100644 > --- a/include/configs/imx8mn_evk.h > +++ b/include/configs/imx8mn_evk.h > @@ -73,7 +73,11 @@ > > #define CONFIG_SYS_SDRAM_BASE 0x40000000 > #define PHYS_SDRAM 0x40000000 > +#ifdef CONFIG_TARGET_IMX8MN_DDR3L_EVK > +#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ > +#else > #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ > +#endif > > #define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) > > -- > 2.20.1 > -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 michael@amarulasolutions.com __________________________________ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 info@amarulasolutions.com www.amarulasolutions.com ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support 2022-06-14 6:55 ` Michael Nazzareno Trimarchi @ 2022-06-14 11:50 ` Heiko Thiery 2022-06-15 6:23 ` Heiko Thiery 1 sibling, 0 replies; 15+ messages in thread From: Heiko Thiery @ 2022-06-14 11:50 UTC (permalink / raw) To: Michael Nazzareno Trimarchi Cc: u-boot, Ying-Chun Liu, Peng Fan, Fabio Estevam, Marek Vasut, Marcel Ziswiler, Tim Harvey, Sean Anderson, Thomas Schäfer, Stefano Babic, Fabio Estevam Hi Michael, Am Di., 14. Juni 2022 um 08:56 Uhr schrieb Michael Nazzareno Trimarchi <michael@amarulasolutions.com>: > > Hi > > On Mon, Jun 13, 2022 at 11:10 PM Heiko Thiery <heiko.thiery@gmail.com> wrote: > > > > Add the support for the 8MNANOD3L-EVK board. The board has an i.MX8MNano > > UltraLite Quad SoC and uses 1GB DDR3L memory. > > > > U-Boot SPL 2022.07-rc4-00017-gcf594ebce1 (Jun 13 2022 - 22:40:31 +0200) > > Normal Boot > > WDT: Started watchdog@30280000 with servicing (60s timeout) > > Trying to boot from BOOTROM > > image offset 0x8000, pagesize 0x200, ivt offset 0x0 > > NOTICE: BL31: v2.6(release):v2.6-5-g9b1a4d832 > > NOTICE: BL31: Built : 14:03:53, May 10 2022 > > > > U-Boot 2022.07-rc4-00017-gcf594ebce1 (Jun 13 2022 - 22:40:31 +0200) > > > > CPU: Freescale i.MX8MNano UltraLite Quad rev1.0 at 1200 MHz > > Reset cause: WDOG > > Model: NXP i.MX8MNano DDR3L EVK board > > DRAM: 1 GiB > > Core: 142 devices, 19 uclasses, devicetree: separate > > WDT: Started watchdog@30280000 with servicing (60s timeout) > > MMC: FSL_SDHC: 1, FSL_SDHC: 2 > > Loading Environment from MMC... OK > > In: serial@30890000 > > Out: serial@30890000 > > Err: serial@30890000 > > Net: eth0: ethernet@30be0000 > > Hit any key to stop autoboot: 0 > > > > Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com> > > Reviewed-by: Fabio Estevam <festevam@denx.de> > > --- > > v4: > > - rebase on current master to fix merge conflicts > > - remove config options from defconfig > > - enable SPL_DM_SERIAL > > - include imx8mn-ddr4-evk-u-boot.dtsi in imx8mn-ddr3l-evk-u-boot.dtsi > > v3: > > - fix config option description in Kconfig (TARGET_IMX8MN_DDR3L_EVK) > > v2: > > - change license formatting (thanks Marcel) > > > > arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi | 34 + > > arch/arm/dts/imx8mn-ddr3l-evk.dts | 114 +++ > > arch/arm/dts/imx8mn-u-boot.dtsi | 12 + > > arch/arm/mach-imx/imx8m/Kconfig | 7 + > > board/freescale/imx8mn_evk/Kconfig | 2 +- > > board/freescale/imx8mn_evk/Makefile | 1 + > > board/freescale/imx8mn_evk/ddr3l_timing.c | 943 ++++++++++++++++++++++ > > board/freescale/imx8mn_evk/spl.c | 9 + > > configs/imx8mn_ddr3l_evk_defconfig | 95 +++ > > include/configs/imx8mn_evk.h | 4 + > > 10 files changed, 1220 insertions(+), 1 deletion(-) > > create mode 100644 arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi > > create mode 100644 arch/arm/dts/imx8mn-ddr3l-evk.dts > > create mode 100644 board/freescale/imx8mn_evk/ddr3l_timing.c > > create mode 100644 configs/imx8mn_ddr3l_evk_defconfig > > > > diff --git a/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi > > new file mode 100644 > > index 0000000000..b9192515e5 > > --- /dev/null > > +++ b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi > > @@ -0,0 +1,34 @@ > > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT > > + > > +#include "imx8mn-u-boot.dtsi" > > +#include "imx8mn-ddr4-evk-u-boot.dtsi" > > + > > + > > +&{/soc@0} { > > + u-boot,dm-pre-reloc; > > + u-boot,dm-spl; > > +}; > > + > > +&clk { > > + u-boot,dm-spl; > > + u-boot,dm-pre-reloc; > > + /delete-property/ assigned-clocks; > > + /delete-property/ assigned-clock-parents; > > + /delete-property/ assigned-clock-rates; > > +}; > > + > > +&i2c1 { > > + u-boot,dm-spl; > > +}; > > + > > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { > > + u-boot,dm-spl; > > +}; > > + > > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { > > + u-boot,dm-spl; > > +}; > > + > > +&wdog1 { > > + u-boot,dm-spl; > > +}; > > diff --git a/arch/arm/dts/imx8mn-ddr3l-evk.dts b/arch/arm/dts/imx8mn-ddr3l-evk.dts > > new file mode 100644 > > index 0000000000..4cdc03c8f2 > > --- /dev/null > > +++ b/arch/arm/dts/imx8mn-ddr3l-evk.dts > > @@ -0,0 +1,114 @@ > > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT > > + > > +/dts-v1/; > > + > > +#include "imx8mn.dtsi" > > +#include "imx8mn-evk.dtsi" > > +#include <dt-bindings/interrupt-controller/irq.h> > > + > > +/ { > > + model = "NXP i.MX8MNano DDR3L EVK board"; > > + compatible = "fsl,imx8mn-ddr3l-evk", "fsl,imx8mn"; > > +}; > > + > > +&A53_0 { > > + cpu-supply = <&buck1>; > > +}; > > + > > +&A53_1 { > > + cpu-supply = <&buck1>; > > +}; > > + > > +&A53_2 { > > + cpu-supply = <&buck1>; > > +}; > > + > > +&A53_3 { > > + cpu-supply = <&buck1>; > > +}; > > + > > +&i2c1 { > > + pmic: pmic@25 { > > + compatible = "nxp,pca9450b"; > > + reg = <0x25>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_pmic>; > > + interrupt-parent = <&gpio1>; > > + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; > > + > > + regulators { > > + buck1: BUCK1 { > > + regulator-name = "VDD_SOC_0V9"; > > + regulator-min-microvolt = <850000>; > > + regulator-max-microvolt = <950000>; > > + regulator-boot-on; > > + regulator-always-on; > > + regulator-ramp-delay = <3125>; > > + }; > > + > > + buck4: BUCK4 { > > + regulator-name = "VDD_3V3"; > > + regulator-min-microvolt = <3300000>; > > + regulator-max-microvolt = <3300000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + buck5: BUCK5 { > > + regulator-name = "VDD_1V8"; > > + regulator-min-microvolt = <1800000>; > > + regulator-max-microvolt = <1800000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + buck6: BUCK6 { > > + regulator-name = "NVCC_DRAM_1V35"; > > + regulator-min-microvolt = <1350000>; > > + regulator-max-microvolt = <1350000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + ldo1: LDO1 { > > + regulator-name = "NVCC_SNVS_1V8"; > > + regulator-min-microvolt = <1800000>; > > + regulator-max-microvolt = <1800000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + ldo2: LDO2 { > > + regulator-name = "VDD_SNVS_0V8"; > > + regulator-min-microvolt = <800000>; > > + regulator-max-microvolt = <800000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + ldo3: LDO3 { > > + regulator-name = "VDDA_1V8"; > > + regulator-min-microvolt = <1800000>; > > + regulator-max-microvolt = <1800000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + ldo4: LDO4 { > > + regulator-name = "VDD_PHY_1V2"; > > + regulator-min-microvolt = <1200000>; > > + regulator-max-microvolt = <1200000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + ldo5: LDO5 { > > + regulator-name = "NVCC_SD2"; > > + regulator-min-microvolt = <1800000>; > > + regulator-max-microvolt = <3300000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + }; > > + }; > > +}; > > diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi > > index 7b591085a0..9286bdace0 100644 > > --- a/arch/arm/dts/imx8mn-u-boot.dtsi > > +++ b/arch/arm/dts/imx8mn-u-boot.dtsi > > @@ -151,6 +151,18 @@ > > size = <0x4000>; > > }; > > }; > > +#elif CONFIG_IMX8M_DDR3L > > +&u_boot_spl_ddr { > > + blob_1: blob-ext@1 { > > + filename = "ddr3_imem_1d.bin"; > > + size = <0x8000>; > > + }; > > + > > + blob_2: blob-ext@2 { > > + filename = "ddr3_dmem_1d.bin"; > > + size = <0x4000>; > > + }; > > +}; > > #else > > #error "no valid ddr config selected" > > #endif > > diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig > > index ef8518c06b..aa386c8f36 100644 > > --- a/arch/arm/mach-imx/imx8m/Kconfig > > +++ b/arch/arm/mach-imx/imx8m/Kconfig > > @@ -140,6 +140,13 @@ config TARGET_IMX8MN_DDR4_EVK > > select FSL_CAAM > > select SPL_CRYPTO if SPL > > > > +config TARGET_IMX8MN_DDR3L_EVK > > + bool "imx8mn DDR3L EVK board" > > + select BINMAN > > + select IMX8MN > > + select SUPPORT_SPL > > + select IMX8M_DDR3L > > + > > config TARGET_IMX8MN_VENICE > > bool "Support Gateworks Venice iMX8M Nano module" > > select BINMAN > > diff --git a/board/freescale/imx8mn_evk/Kconfig b/board/freescale/imx8mn_evk/Kconfig > > index 6596fb5c6d..38312a3662 100644 > > --- a/board/freescale/imx8mn_evk/Kconfig > > +++ b/board/freescale/imx8mn_evk/Kconfig > > @@ -1,4 +1,4 @@ > > -if TARGET_IMX8MN_EVK || TARGET_IMX8MN_DDR4_EVK > > +if TARGET_IMX8MN_EVK || TARGET_IMX8MN_DDR4_EVK || TARGET_IMX8MN_DDR3L_EVK > > > > config SYS_BOARD > > default "imx8mn_evk" > > diff --git a/board/freescale/imx8mn_evk/Makefile b/board/freescale/imx8mn_evk/Makefile > > index 42d1179724..ad3ef8edd6 100644 > > --- a/board/freescale/imx8mn_evk/Makefile > > +++ b/board/freescale/imx8mn_evk/Makefile > > @@ -14,5 +14,6 @@ obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing_ld.o > > else > > obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o > > obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o > > +obj-$(CONFIG_IMX8M_DDR3L) += ddr3l_timing.o > > endif > > endif > > diff --git a/board/freescale/imx8mn_evk/ddr3l_timing.c b/board/freescale/imx8mn_evk/ddr3l_timing.c > > new file mode 100644 > > index 0000000000..0fe1f6a42d > > --- /dev/null > > +++ b/board/freescale/imx8mn_evk/ddr3l_timing.c > > @@ -0,0 +1,943 @@ > > +// SPDX-License-Identifier: GPL-2.0-or-later > > +/* > > + * Copyright 2019 NXP > > + * > > + * Generated code from MX8M_DDR_tool > > + * > > + * Align with uboot version: > > + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga > > + * For imx_v2019.04_5.4.x and above version: > > + * please replace #include <asm/arch/imx8m_ddr.h> with #include <asm/arch/ddr.h> > > + */ > > + > > +#include <linux/kernel.h> > > +#include <asm/arch/ddr.h> > > + > > +struct dram_cfg_param ddr_ddrc_cfg[] = { > > + /** Initialize DDRC registers **/ > > + { 0x3d400304, 0x1 }, > > + { 0x3d400030, 0x20 }, > > + { 0x3d400000, 0xa1040001 }, > > + { 0x3d400064, 0x61008c }, > > + { 0x3d4000d0, 0xc00200c5 }, > > + { 0x3d4000d4, 0x1000b }, > > + { 0x3d4000dc, 0x1d700004 }, > > + { 0x3d4000e0, 0x180000 }, > > + { 0x3d4000e4, 0x90000 }, > > + { 0x3d4000f0, 0x0 }, > > + { 0x3d4000f4, 0xee5 }, > > + { 0x3d400100, 0xc101b0e }, > > + { 0x3d400104, 0x30314 }, > > + { 0x3d400108, 0x4060509 }, > > + { 0x3d40010c, 0x2006 }, > > + { 0x3d400110, 0x6020306 }, > > + { 0x3d400114, 0x4040302 }, > > + { 0x3d400120, 0x909 }, > > + { 0x3d400180, 0x40800020 }, > > + { 0x3d400184, 0xc350 }, > > + { 0x3d400190, 0x3868203 }, > > + { 0x3d400194, 0x20303 }, > > + { 0x3d4001b4, 0x603 }, > > + { 0x3d400198, 0x7000000 }, > > + { 0x3d4001b0, 0x11 }, > > + { 0x3d4001a0, 0x400018 }, > > + { 0x3d4001a4, 0x5003c }, > > + { 0x3d4001a8, 0x80000000 }, > > + { 0x3d4001c4, 0x0 }, > > + { 0x3d400200, 0x1f }, > > + { 0x3d400204, 0x80808 }, > > + { 0x3d400208, 0x0 }, > > + { 0x3d40020c, 0x0 }, > > + { 0x3d400210, 0x1f1f }, > > + { 0x3d400214, 0x7070707 }, > > + { 0x3d400218, 0x7070707 }, > > + { 0x3d400240, 0x600060c }, > > + { 0x3d400244, 0x1323 }, > > + { 0x3d400400, 0x100 }, > > + { 0x3d400250, 0x7ab50b07 }, > > + { 0x3d400254, 0x22 }, > > + { 0x3d40025c, 0x7b00665e }, > > + { 0x3d400264, 0xb0000040 }, > > + { 0x3d40026c, 0x50000a0c }, > > + { 0x3d400300, 0x17 }, > > + { 0x3d40036c, 0x10000 }, > > + { 0x3d400404, 0x3051 }, > > + { 0x3d400408, 0x61d2 }, > > + { 0x3d400494, 0xe00 }, > > + { 0x3d400498, 0x7ff }, > > + { 0x3d40049c, 0xe00 }, > > + { 0x3d4004a0, 0x7ff }, > > + { 0x3d402064, 0x28003b }, > > + { 0x3d4020dc, 0x12200004 }, > > + { 0x3d4020e0, 0x0 }, > > + { 0x3d402100, 0x7090b07 }, > > + { 0x3d402104, 0x20209 }, > > + { 0x3d402108, 0x3030407 }, > > + { 0x3d40210c, 0x2006 }, > > + { 0x3d402110, 0x3020203 }, > > + { 0x3d402114, 0x3030202 }, > > + { 0x3d402120, 0x909 }, > > + { 0x3d402180, 0x40800020 }, > > + { 0x3d402190, 0x3818200 }, > > + { 0x3d402194, 0x20303 }, > > + { 0x3d4021b4, 0x100 }, > > + { 0x3d402240, 0x6000604 }, > > + { 0x3d4020f4, 0xee5 }, > > + { 0x3d400028, 0x1 }, > > +}; > > + > > +/* PHY Initialize Configuration */ > > +struct dram_cfg_param ddr_ddrphy_cfg[] = { > > + { 0x1005f, 0x3ff }, > > + { 0x1015f, 0x3ff }, > > + { 0x1105f, 0x3ff }, > > + { 0x1115f, 0x3ff }, > > + { 0x11005f, 0x3ff }, > > + { 0x11015f, 0x3ff }, > > + { 0x11105f, 0x3ff }, > > + { 0x11115f, 0x3ff }, > > + { 0x55, 0x3ff }, > > + { 0x1055, 0x3ff }, > > + { 0x2055, 0x3ff }, > > + { 0x3055, 0x3ff }, > > + { 0x4055, 0xff }, > > + { 0x5055, 0xff }, > > + { 0x6055, 0x3ff }, > > + { 0x7055, 0x3ff }, > > + { 0x8055, 0x3ff }, > > + { 0x9055, 0x3ff }, > > + { 0x200c5, 0xb }, > > + { 0x1200c5, 0x7 }, > > + { 0x2002e, 0x1 }, > > + { 0x12002e, 0x1 }, > > + { 0x20024, 0x0 }, > > + { 0x2003a, 0x0 }, > > + { 0x120024, 0x0 }, > > + { 0x2003a, 0x0 }, > > + { 0x20056, 0xa }, > > + { 0x120056, 0xa }, > > + { 0x1004d, 0x208 }, > > + { 0x1014d, 0x208 }, > > + { 0x1104d, 0x208 }, > > + { 0x1114d, 0x208 }, > > + { 0x11004d, 0x208 }, > > + { 0x11014d, 0x208 }, > > + { 0x11104d, 0x208 }, > > + { 0x11114d, 0x208 }, > > + { 0x10049, 0xe38 }, > > + { 0x10149, 0xe38 }, > > + { 0x11049, 0xe38 }, > > + { 0x11149, 0xe38 }, > > + { 0x110049, 0xe38 }, > > + { 0x110149, 0xe38 }, > > + { 0x111049, 0xe38 }, > > + { 0x111149, 0xe38 }, > > + { 0x43, 0x63 }, > > + { 0x1043, 0x63 }, > > + { 0x2043, 0x63 }, > > + { 0x3043, 0x63 }, > > + { 0x4043, 0x63 }, > > + { 0x5043, 0x63 }, > > + { 0x6043, 0x63 }, > > + { 0x7043, 0x63 }, > > + { 0x8043, 0x63 }, > > + { 0x9043, 0x63 }, > > + { 0x20018, 0x1 }, > > + { 0x20075, 0x0 }, > > + { 0x20050, 0x0 }, > > + { 0x20008, 0x190 }, > > + { 0x120008, 0xa7 }, > > + { 0x20088, 0x9 }, > > + { 0x200b2, 0x32c }, > > + { 0x10043, 0x581 }, > > + { 0x10143, 0x581 }, > > + { 0x11043, 0x581 }, > > + { 0x11143, 0x581 }, > > + { 0x1200b2, 0x32c }, > > + { 0x110043, 0x581 }, > > + { 0x110143, 0x581 }, > > + { 0x111043, 0x581 }, > > + { 0x111143, 0x581 }, > > + { 0x200fa, 0x1 }, > > + { 0x1200fa, 0x1 }, > > + { 0x20019, 0x5 }, > > + { 0x120019, 0x5 }, > > + { 0x200f0, 0x5555 }, > > + { 0x200f1, 0x5555 }, > > + { 0x200f2, 0x5555 }, > > + { 0x200f3, 0x5555 }, > > + { 0x200f4, 0x5555 }, > > + { 0x200f5, 0x5555 }, > > + { 0x200f6, 0x5555 }, > > + { 0x200f7, 0xf000 }, > > + { 0x20025, 0x0 }, > > + { 0x2007d, 0x212 }, > > + { 0x12007d, 0x212 }, > > + { 0x2007c, 0x61 }, > > + { 0x12007c, 0x61 }, > > + { 0x1004a, 0x500 }, > > + { 0x1104a, 0x500 }, > > + { 0x2002c, 0x0 }, > > +}; > > + > > +/* ddr phy trained csr */ > > +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { > > + {0x0200b2,0x0}, > > + {0x1200b2,0x0}, > > + {0x2200b2,0x0}, > > + {0x0200cb,0x0}, > > + {0x010043,0x0}, > > + {0x110043,0x0}, > > + {0x210043,0x0}, > > + {0x010143,0x0}, > > + {0x110143,0x0}, > > + {0x210143,0x0}, > > + {0x011043,0x0}, > > + {0x111043,0x0}, > > + {0x211043,0x0}, > > + {0x011143,0x0}, > > + {0x111143,0x0}, > > + {0x211143,0x0}, > > + {0x000080,0x0}, > > + {0x100080,0x0}, > > + {0x200080,0x0}, > > + {0x001080,0x0}, > > + {0x101080,0x0}, > > + {0x201080,0x0}, > > + {0x002080,0x0}, > > + {0x102080,0x0}, > > + {0x202080,0x0}, > > + {0x003080,0x0}, > > + {0x103080,0x0}, > > + {0x203080,0x0}, > > + {0x004080,0x0}, > > + {0x104080,0x0}, > > + {0x204080,0x0}, > > + {0x005080,0x0}, > > + {0x105080,0x0}, > > + {0x205080,0x0}, > > + {0x006080,0x0}, > > + {0x106080,0x0}, > > + {0x206080,0x0}, > > + {0x007080,0x0}, > > + {0x107080,0x0}, > > + {0x207080,0x0}, > > + {0x008080,0x0}, > > + {0x108080,0x0}, > > + {0x208080,0x0}, > > + {0x009080,0x0}, > > + {0x109080,0x0}, > > + {0x209080,0x0}, > > + {0x010080,0x0}, > > + {0x110080,0x0}, > > + {0x210080,0x0}, > > + {0x010180,0x0}, > > + {0x110180,0x0}, > > + {0x210180,0x0}, > > + {0x010081,0x0}, > > + {0x110081,0x0}, > > + {0x210081,0x0}, > > + {0x010181,0x0}, > > + {0x110181,0x0}, > > + {0x210181,0x0}, > > + {0x010082,0x0}, > > + {0x110082,0x0}, > > + {0x210082,0x0}, > > + {0x010182,0x0}, > > + {0x110182,0x0}, > > + {0x210182,0x0}, > > + {0x010083,0x0}, > > + {0x110083,0x0}, > > + {0x210083,0x0}, > > + {0x010183,0x0}, > > + {0x110183,0x0}, > > + {0x210183,0x0}, > > + {0x011080,0x0}, > > + {0x111080,0x0}, > > + {0x211080,0x0}, > > + {0x011180,0x0}, > > + {0x111180,0x0}, > > + {0x211180,0x0}, > > + {0x011081,0x0}, > > + {0x111081,0x0}, > > + {0x211081,0x0}, > > + {0x011181,0x0}, > > + {0x111181,0x0}, > > + {0x211181,0x0}, > > + {0x011082,0x0}, > > + {0x111082,0x0}, > > + {0x211082,0x0}, > > + {0x011182,0x0}, > > + {0x111182,0x0}, > > + {0x211182,0x0}, > > + {0x011083,0x0}, > > + {0x111083,0x0}, > > + {0x211083,0x0}, > > + {0x011183,0x0}, > > + {0x111183,0x0}, > > + {0x211183,0x0}, > > + {0x0100d0,0x0}, > > + {0x1100d0,0x0}, > > + {0x2100d0,0x0}, > > + {0x0101d0,0x0}, > > + {0x1101d0,0x0}, > > + {0x2101d0,0x0}, > > + {0x0100d1,0x0}, > > + {0x1100d1,0x0}, > > + {0x2100d1,0x0}, > > + {0x0101d1,0x0}, > > + {0x1101d1,0x0}, > > + {0x2101d1,0x0}, > > + {0x0100d2,0x0}, > > + {0x1100d2,0x0}, > > + {0x2100d2,0x0}, > > + {0x0101d2,0x0}, > > + {0x1101d2,0x0}, > > + {0x2101d2,0x0}, > > + {0x0100d3,0x0}, > > + {0x1100d3,0x0}, > > + {0x2100d3,0x0}, > > + {0x0101d3,0x0}, > > + {0x1101d3,0x0}, > > + {0x2101d3,0x0}, > > + {0x0110d0,0x0}, > > + {0x1110d0,0x0}, > > + {0x2110d0,0x0}, > > + {0x0111d0,0x0}, > > + {0x1111d0,0x0}, > > + {0x2111d0,0x0}, > > + {0x0110d1,0x0}, > > + {0x1110d1,0x0}, > > + {0x2110d1,0x0}, > > + {0x0111d1,0x0}, > > + {0x1111d1,0x0}, > > + {0x2111d1,0x0}, > > + {0x0110d2,0x0}, > > + {0x1110d2,0x0}, > > + {0x2110d2,0x0}, > > + {0x0111d2,0x0}, > > + {0x1111d2,0x0}, > > + {0x2111d2,0x0}, > > + {0x0110d3,0x0}, > > + {0x1110d3,0x0}, > > + {0x2110d3,0x0}, > > + {0x0111d3,0x0}, > > + {0x1111d3,0x0}, > > + {0x2111d3,0x0}, > > + {0x010068,0x0}, > > + {0x010168,0x0}, > > + {0x010268,0x0}, > > + {0x010368,0x0}, > > + {0x010468,0x0}, > > + {0x010568,0x0}, > > + {0x010668,0x0}, > > + {0x010768,0x0}, > > + {0x010868,0x0}, > > + {0x010069,0x0}, > > + {0x010169,0x0}, > > + {0x010269,0x0}, > > + {0x010369,0x0}, > > + {0x010469,0x0}, > > + {0x010569,0x0}, > > + {0x010669,0x0}, > > + {0x010769,0x0}, > > + {0x010869,0x0}, > > + {0x01006a,0x0}, > > + {0x01016a,0x0}, > > + {0x01026a,0x0}, > > + {0x01036a,0x0}, > > + {0x01046a,0x0}, > > + {0x01056a,0x0}, > > + {0x01066a,0x0}, > > + {0x01076a,0x0}, > > + {0x01086a,0x0}, > > + {0x01006b,0x0}, > > + {0x01016b,0x0}, > > + {0x01026b,0x0}, > > + {0x01036b,0x0}, > > + {0x01046b,0x0}, > > + {0x01056b,0x0}, > > + {0x01066b,0x0}, > > + {0x01076b,0x0}, > > + {0x01086b,0x0}, > > + {0x011068,0x0}, > > + {0x011168,0x0}, > > + {0x011268,0x0}, > > + {0x011368,0x0}, > > + {0x011468,0x0}, > > + {0x011568,0x0}, > > + {0x011668,0x0}, > > + {0x011768,0x0}, > > + {0x011868,0x0}, > > + {0x011069,0x0}, > > + {0x011169,0x0}, > > + {0x011269,0x0}, > > + {0x011369,0x0}, > > + {0x011469,0x0}, > > + {0x011569,0x0}, > > + {0x011669,0x0}, > > + {0x011769,0x0}, > > + {0x011869,0x0}, > > + {0x01106a,0x0}, > > + {0x01116a,0x0}, > > + {0x01126a,0x0}, > > + {0x01136a,0x0}, > > + {0x01146a,0x0}, > > + {0x01156a,0x0}, > > + {0x01166a,0x0}, > > + {0x01176a,0x0}, > > + {0x01186a,0x0}, > > + {0x01106b,0x0}, > > + {0x01116b,0x0}, > > + {0x01126b,0x0}, > > + {0x01136b,0x0}, > > + {0x01146b,0x0}, > > + {0x01156b,0x0}, > > + {0x01166b,0x0}, > > + {0x01176b,0x0}, > > + {0x01186b,0x0}, > > + {0x01008c,0x0}, > > + {0x11008c,0x0}, > > + {0x21008c,0x0}, > > + {0x01018c,0x0}, > > + {0x11018c,0x0}, > > + {0x21018c,0x0}, > > + {0x01008d,0x0}, > > + {0x11008d,0x0}, > > + {0x21008d,0x0}, > > + {0x01018d,0x0}, > > + {0x11018d,0x0}, > > + {0x21018d,0x0}, > > + {0x01008e,0x0}, > > + {0x11008e,0x0}, > > + {0x21008e,0x0}, > > + {0x01018e,0x0}, > > + {0x11018e,0x0}, > > + {0x21018e,0x0}, > > + {0x01008f,0x0}, > > + {0x11008f,0x0}, > > + {0x21008f,0x0}, > > + {0x01018f,0x0}, > > + {0x11018f,0x0}, > > + {0x21018f,0x0}, > > + {0x01108c,0x0}, > > + {0x11108c,0x0}, > > + {0x21108c,0x0}, > > + {0x01118c,0x0}, > > + {0x11118c,0x0}, > > + {0x21118c,0x0}, > > + {0x01108d,0x0}, > > + {0x11108d,0x0}, > > + {0x21108d,0x0}, > > + {0x01118d,0x0}, > > + {0x11118d,0x0}, > > + {0x21118d,0x0}, > > + {0x01108e,0x0}, > > + {0x11108e,0x0}, > > + {0x21108e,0x0}, > > + {0x01118e,0x0}, > > + {0x11118e,0x0}, > > + {0x21118e,0x0}, > > + {0x01108f,0x0}, > > + {0x11108f,0x0}, > > + {0x21108f,0x0}, > > + {0x01118f,0x0}, > > + {0x11118f,0x0}, > > + {0x21118f,0x0}, > > + {0x0100c0,0x0}, > > + {0x1100c0,0x0}, > > + {0x2100c0,0x0}, > > + {0x0101c0,0x0}, > > + {0x1101c0,0x0}, > > + {0x2101c0,0x0}, > > + {0x0102c0,0x0}, > > + {0x1102c0,0x0}, > > + {0x2102c0,0x0}, > > + {0x0103c0,0x0}, > > + {0x1103c0,0x0}, > > + {0x2103c0,0x0}, > > + {0x0104c0,0x0}, > > + {0x1104c0,0x0}, > > + {0x2104c0,0x0}, > > + {0x0105c0,0x0}, > > + {0x1105c0,0x0}, > > + {0x2105c0,0x0}, > > + {0x0106c0,0x0}, > > + {0x1106c0,0x0}, > > + {0x2106c0,0x0}, > > + {0x0107c0,0x0}, > > + {0x1107c0,0x0}, > > + {0x2107c0,0x0}, > > + {0x0108c0,0x0}, > > + {0x1108c0,0x0}, > > + {0x2108c0,0x0}, > > + {0x0100c1,0x0}, > > + {0x1100c1,0x0}, > > + {0x2100c1,0x0}, > > + {0x0101c1,0x0}, > > + {0x1101c1,0x0}, > > + {0x2101c1,0x0}, > > + {0x0102c1,0x0}, > > + {0x1102c1,0x0}, > > + {0x2102c1,0x0}, > > + {0x0103c1,0x0}, > > + {0x1103c1,0x0}, > > + {0x2103c1,0x0}, > > + {0x0104c1,0x0}, > > + {0x1104c1,0x0}, > > + {0x2104c1,0x0}, > > + {0x0105c1,0x0}, > > + {0x1105c1,0x0}, > > + {0x2105c1,0x0}, > > + {0x0106c1,0x0}, > > + {0x1106c1,0x0}, > > + {0x2106c1,0x0}, > > + {0x0107c1,0x0}, > > + {0x1107c1,0x0}, > > + {0x2107c1,0x0}, > > + {0x0108c1,0x0}, > > + {0x1108c1,0x0}, > > + {0x2108c1,0x0}, > > + {0x0100c2,0x0}, > > + {0x1100c2,0x0}, > > + {0x2100c2,0x0}, > > + {0x0101c2,0x0}, > > + {0x1101c2,0x0}, > > + {0x2101c2,0x0}, > > + {0x0102c2,0x0}, > > + {0x1102c2,0x0}, > > + {0x2102c2,0x0}, > > + {0x0103c2,0x0}, > > + {0x1103c2,0x0}, > > + {0x2103c2,0x0}, > > + {0x0104c2,0x0}, > > + {0x1104c2,0x0}, > > + {0x2104c2,0x0}, > > + {0x0105c2,0x0}, > > + {0x1105c2,0x0}, > > + {0x2105c2,0x0}, > > + {0x0106c2,0x0}, > > + {0x1106c2,0x0}, > > + {0x2106c2,0x0}, > > + {0x0107c2,0x0}, > > + {0x1107c2,0x0}, > > + {0x2107c2,0x0}, > > + {0x0108c2,0x0}, > > + {0x1108c2,0x0}, > > + {0x2108c2,0x0}, > > + {0x0100c3,0x0}, > > + {0x1100c3,0x0}, > > + {0x2100c3,0x0}, > > + {0x0101c3,0x0}, > > + {0x1101c3,0x0}, > > + {0x2101c3,0x0}, > > + {0x0102c3,0x0}, > > + {0x1102c3,0x0}, > > + {0x2102c3,0x0}, > > + {0x0103c3,0x0}, > > + {0x1103c3,0x0}, > > + {0x2103c3,0x0}, > > + {0x0104c3,0x0}, > > + {0x1104c3,0x0}, > > + {0x2104c3,0x0}, > > + {0x0105c3,0x0}, > > + {0x1105c3,0x0}, > > + {0x2105c3,0x0}, > > + {0x0106c3,0x0}, > > + {0x1106c3,0x0}, > > + {0x2106c3,0x0}, > > + {0x0107c3,0x0}, > > + {0x1107c3,0x0}, > > + {0x2107c3,0x0}, > > + {0x0108c3,0x0}, > > + {0x1108c3,0x0}, > > + {0x2108c3,0x0}, > > + {0x0110c0,0x0}, > > + {0x1110c0,0x0}, > > + {0x2110c0,0x0}, > > + {0x0111c0,0x0}, > > + {0x1111c0,0x0}, > > + {0x2111c0,0x0}, > > + {0x0112c0,0x0}, > > + {0x1112c0,0x0}, > > + {0x2112c0,0x0}, > > + {0x0113c0,0x0}, > > + {0x1113c0,0x0}, > > + {0x2113c0,0x0}, > > + {0x0114c0,0x0}, > > + {0x1114c0,0x0}, > > + {0x2114c0,0x0}, > > + {0x0115c0,0x0}, > > + {0x1115c0,0x0}, > > + {0x2115c0,0x0}, > > + {0x0116c0,0x0}, > > + {0x1116c0,0x0}, > > + {0x2116c0,0x0}, > > + {0x0117c0,0x0}, > > + {0x1117c0,0x0}, > > + {0x2117c0,0x0}, > > + {0x0118c0,0x0}, > > + {0x1118c0,0x0}, > > + {0x2118c0,0x0}, > > + {0x0110c1,0x0}, > > + {0x1110c1,0x0}, > > + {0x2110c1,0x0}, > > + {0x0111c1,0x0}, > > + {0x1111c1,0x0}, > > + {0x2111c1,0x0}, > > + {0x0112c1,0x0}, > > + {0x1112c1,0x0}, > > + {0x2112c1,0x0}, > > + {0x0113c1,0x0}, > > + {0x1113c1,0x0}, > > + {0x2113c1,0x0}, > > + {0x0114c1,0x0}, > > + {0x1114c1,0x0}, > > + {0x2114c1,0x0}, > > + {0x0115c1,0x0}, > > + {0x1115c1,0x0}, > > + {0x2115c1,0x0}, > > + {0x0116c1,0x0}, > > + {0x1116c1,0x0}, > > + {0x2116c1,0x0}, > > + {0x0117c1,0x0}, > > + {0x1117c1,0x0}, > > + {0x2117c1,0x0}, > > + {0x0118c1,0x0}, > > + {0x1118c1,0x0}, > > + {0x2118c1,0x0}, > > + {0x0110c2,0x0}, > > + {0x1110c2,0x0}, > > + {0x2110c2,0x0}, > > + {0x0111c2,0x0}, > > + {0x1111c2,0x0}, > > + {0x2111c2,0x0}, > > + {0x0112c2,0x0}, > > + {0x1112c2,0x0}, > > + {0x2112c2,0x0}, > > + {0x0113c2,0x0}, > > + {0x1113c2,0x0}, > > + {0x2113c2,0x0}, > > + {0x0114c2,0x0}, > > + {0x1114c2,0x0}, > > + {0x2114c2,0x0}, > > + {0x0115c2,0x0}, > > + {0x1115c2,0x0}, > > + {0x2115c2,0x0}, > > + {0x0116c2,0x0}, > > + {0x1116c2,0x0}, > > + {0x2116c2,0x0}, > > + {0x0117c2,0x0}, > > + {0x1117c2,0x0}, > > + {0x2117c2,0x0}, > > + {0x0118c2,0x0}, > > + {0x1118c2,0x0}, > > + {0x2118c2,0x0}, > > + {0x0110c3,0x0}, > > + {0x1110c3,0x0}, > > + {0x2110c3,0x0}, > > + {0x0111c3,0x0}, > > + {0x1111c3,0x0}, > > + {0x2111c3,0x0}, > > + {0x0112c3,0x0}, > > + {0x1112c3,0x0}, > > + {0x2112c3,0x0}, > > + {0x0113c3,0x0}, > > + {0x1113c3,0x0}, > > + {0x2113c3,0x0}, > > + {0x0114c3,0x0}, > > + {0x1114c3,0x0}, > > + {0x2114c3,0x0}, > > + {0x0115c3,0x0}, > > + {0x1115c3,0x0}, > > + {0x2115c3,0x0}, > > + {0x0116c3,0x0}, > > + {0x1116c3,0x0}, > > + {0x2116c3,0x0}, > > + {0x0117c3,0x0}, > > + {0x1117c3,0x0}, > > + {0x2117c3,0x0}, > > + {0x0118c3,0x0}, > > + {0x1118c3,0x0}, > > + {0x2118c3,0x0}, > > + {0x010020,0x0}, > > + {0x110020,0x0}, > > + {0x210020,0x0}, > > + {0x011020,0x0}, > > + {0x111020,0x0}, > > + {0x211020,0x0}, > > + {0x02007d,0x0}, > > + {0x12007d,0x0}, > > + {0x22007d,0x0}, > > +}; > > + > > +/* P0 message block paremeter for training firmware */ > > +struct dram_cfg_param ddr_fsp0_cfg[] = { > > + { 0xd0000, 0x0 }, > > + { 0x54003, 0x640 }, > > + { 0x54004, 0x2 }, > > + { 0x54005, 0x283c }, > > + { 0x54006, 0x140 }, > > + { 0x54007, 0x1000 }, > > + { 0x54008, 0x101 }, > > + { 0x5400b, 0x31f }, > > + { 0x5400c, 0xc8 }, > > + { 0x54012, 0x1 }, > > + { 0x5402f, 0x1d70 }, > > + { 0x54030, 0x4 }, > > + { 0x54031, 0x18 }, > > + { 0x5403a, 0x1323 }, > > + { 0xd0000, 0x1 }, > > +}; > > + > > + > > +/* P1 message block paremeter for training firmware */ > > +struct dram_cfg_param ddr_fsp1_cfg[] = { > > + { 0xd0000, 0x0 }, > > + { 0x54002, 0x1 }, > > + { 0x54003, 0x29c }, > > + { 0x54004, 0x2 }, > > + { 0x54005, 0x283c }, > > + { 0x54006, 0x140 }, > > + { 0x54007, 0x1000 }, > > + { 0x54008, 0x101 }, > > + { 0x5400b, 0x21f }, > > + { 0x5400c, 0xc8 }, > > + { 0x54012, 0x1 }, > > + { 0x5402f, 0x1220 }, > > + { 0x54030, 0x4 }, > > + { 0x5403a, 0x1323 }, > > + { 0xd0000, 0x1 }, > > +}; > > + > > +/* DRAM PHY init engine image */ > > +struct dram_cfg_param ddr_phy_pie[] = { > > + { 0xd0000, 0x0 }, > > + { 0x90000, 0x10 }, > > + { 0x90001, 0x400 }, > > + { 0x90002, 0x10e }, > > + { 0x90003, 0x0 }, > > + { 0x90004, 0x0 }, > > + { 0x90005, 0x8 }, > > + { 0x90029, 0xb }, > > + { 0x9002a, 0x480 }, > > + { 0x9002b, 0x109 }, > > + { 0x9002c, 0x8 }, > > + { 0x9002d, 0x448 }, > > + { 0x9002e, 0x139 }, > > + { 0x9002f, 0x8 }, > > + { 0x90030, 0x478 }, > > + { 0x90031, 0x109 }, > > + { 0x90032, 0x2 }, > > + { 0x90033, 0x10 }, > > + { 0x90034, 0x139 }, > > + { 0x90035, 0xb }, > > + { 0x90036, 0x7c0 }, > > + { 0x90037, 0x139 }, > > + { 0x90038, 0x44 }, > > + { 0x90039, 0x633 }, > > + { 0x9003a, 0x159 }, > > + { 0x9003b, 0x14f }, > > + { 0x9003c, 0x630 }, > > + { 0x9003d, 0x159 }, > > + { 0x9003e, 0x47 }, > > + { 0x9003f, 0x633 }, > > + { 0x90040, 0x149 }, > > + { 0x90041, 0x4f }, > > + { 0x90042, 0x633 }, > > + { 0x90043, 0x179 }, > > + { 0x90044, 0x8 }, > > + { 0x90045, 0xe0 }, > > + { 0x90046, 0x109 }, > > + { 0x90047, 0x0 }, > > + { 0x90048, 0x7c8 }, > > + { 0x90049, 0x109 }, > > + { 0x9004a, 0x0 }, > > + { 0x9004b, 0x1 }, > > + { 0x9004c, 0x8 }, > > + { 0x9004d, 0x0 }, > > + { 0x9004e, 0x45a }, > > + { 0x9004f, 0x9 }, > > + { 0x90050, 0x0 }, > > + { 0x90051, 0x448 }, > > + { 0x90052, 0x109 }, > > + { 0x90053, 0x40 }, > > + { 0x90054, 0x633 }, > > + { 0x90055, 0x179 }, > > + { 0x90056, 0x1 }, > > + { 0x90057, 0x618 }, > > + { 0x90058, 0x109 }, > > + { 0x90059, 0x40c0 }, > > + { 0x9005a, 0x633 }, > > + { 0x9005b, 0x149 }, > > + { 0x9005c, 0x8 }, > > + { 0x9005d, 0x4 }, > > + { 0x9005e, 0x48 }, > > + { 0x9005f, 0x4040 }, > > + { 0x90060, 0x633 }, > > + { 0x90061, 0x149 }, > > + { 0x90062, 0x0 }, > > + { 0x90063, 0x4 }, > > + { 0x90064, 0x48 }, > > + { 0x90065, 0x40 }, > > + { 0x90066, 0x633 }, > > + { 0x90067, 0x149 }, > > + { 0x90068, 0x10 }, > > + { 0x90069, 0x4 }, > > + { 0x9006a, 0x18 }, > > + { 0x9006b, 0x0 }, > > + { 0x9006c, 0x4 }, > > + { 0x9006d, 0x78 }, > > + { 0x9006e, 0x549 }, > > + { 0x9006f, 0x633 }, > > + { 0x90070, 0x159 }, > > + { 0x90071, 0xd49 }, > > + { 0x90072, 0x633 }, > > + { 0x90073, 0x159 }, > > + { 0x90074, 0x94a }, > > + { 0x90075, 0x633 }, > > + { 0x90076, 0x159 }, > > + { 0x90077, 0x441 }, > > + { 0x90078, 0x633 }, > > + { 0x90079, 0x149 }, > > + { 0x9007a, 0x42 }, > > + { 0x9007b, 0x633 }, > > + { 0x9007c, 0x149 }, > > + { 0x9007d, 0x1 }, > > + { 0x9007e, 0x633 }, > > + { 0x9007f, 0x149 }, > > + { 0x90080, 0x0 }, > > + { 0x90081, 0xe0 }, > > + { 0x90082, 0x109 }, > > + { 0x90083, 0xa }, > > + { 0x90084, 0x10 }, > > + { 0x90085, 0x109 }, > > + { 0x90086, 0x9 }, > > + { 0x90087, 0x3c0 }, > > + { 0x90088, 0x149 }, > > + { 0x90089, 0x9 }, > > + { 0x9008a, 0x3c0 }, > > + { 0x9008b, 0x159 }, > > + { 0x9008c, 0x18 }, > > + { 0x9008d, 0x10 }, > > + { 0x9008e, 0x109 }, > > + { 0x9008f, 0x0 }, > > + { 0x90090, 0x3c0 }, > > + { 0x90091, 0x109 }, > > + { 0x90092, 0x18 }, > > + { 0x90093, 0x4 }, > > + { 0x90094, 0x48 }, > > + { 0x90095, 0x18 }, > > + { 0x90096, 0x4 }, > > + { 0x90097, 0x58 }, > > + { 0x90098, 0xb }, > > + { 0x90099, 0x10 }, > > + { 0x9009a, 0x109 }, > > + { 0x9009b, 0x1 }, > > + { 0x9009c, 0x10 }, > > + { 0x9009d, 0x109 }, > > + { 0x9009e, 0x5 }, > > + { 0x9009f, 0x7c0 }, > > + { 0x900a0, 0x109 }, > > + { 0x900a1, 0x0 }, > > + { 0x900a2, 0x8140 }, > > + { 0x900a3, 0x10c }, > > + { 0x900a4, 0x10 }, > > + { 0x900a5, 0x8138 }, > > + { 0x900a6, 0x10c }, > > + { 0x900a7, 0x8 }, > > + { 0x900a8, 0x7c8 }, > > + { 0x900a9, 0x101 }, > > + { 0x900aa, 0x8 }, > > + { 0x900ab, 0x448 }, > > + { 0x900ac, 0x109 }, > > + { 0x900ad, 0xf }, > > + { 0x900ae, 0x7c0 }, > > + { 0x900af, 0x109 }, > > + { 0x900b0, 0x47 }, > > + { 0x900b1, 0x630 }, > > + { 0x900b2, 0x109 }, > > + { 0x900b3, 0x8 }, > > + { 0x900b4, 0x618 }, > > + { 0x900b5, 0x109 }, > > + { 0x900b6, 0x8 }, > > + { 0x900b7, 0xe0 }, > > + { 0x900b8, 0x109 }, > > + { 0x900b9, 0x0 }, > > + { 0x900ba, 0x7c8 }, > > + { 0x900bb, 0x109 }, > > + { 0x900bc, 0x8 }, > > + { 0x900bd, 0x8140 }, > > + { 0x900be, 0x10c }, > > + { 0x900bf, 0x0 }, > > + { 0x900c0, 0x1 }, > > + { 0x900c1, 0x8 }, > > + { 0x900c2, 0x8 }, > > + { 0x900c3, 0x4 }, > > + { 0x900c4, 0x8 }, > > + { 0x900c5, 0x8 }, > > + { 0x900c6, 0x7c8 }, > > + { 0x900c7, 0x101 }, > > + { 0x90006, 0x0 }, > > + { 0x90007, 0x0 }, > > + { 0x90008, 0x8 }, > > + { 0x90009, 0x0 }, > > + { 0x9000a, 0x0 }, > > + { 0x9000b, 0x0 }, > > + { 0xd00e7, 0x400 }, > > + { 0x90017, 0x0 }, > > + { 0x90026, 0x2b }, > > + { 0x2000b, 0x32 }, > > + { 0x2000c, 0x64 }, > > + { 0x2000d, 0x3e8 }, > > + { 0x2000e, 0x2c }, > > + { 0x12000b, 0x14 }, > > + { 0x12000c, 0x26 }, > > + { 0x12000d, 0x1a1 }, > > + { 0x12000e, 0x10 }, > > + { 0x9000c, 0x0 }, > > + { 0x9000d, 0x173 }, > > + { 0x9000e, 0x60 }, > > + { 0x9000f, 0x6110 }, > > + { 0x90010, 0x2152 }, > > + { 0x90011, 0xdfbd }, > > + { 0x90012, 0xffff }, > > + { 0x90013, 0x6152 }, > > + { 0x20089, 0x1 }, > > + { 0x20088, 0x19 }, > > + { 0xc0080, 0x0 }, > > + { 0xd0000, 0x1 } > > +}; > > + > > +struct dram_fsp_msg ddr_dram_fsp_msg[] = { > > + { > > + /* P0 1600mts 1D */ > > + .drate = 1600, > > + .fw_type = FW_1D_IMAGE, > > + .fsp_cfg = ddr_fsp0_cfg, > > + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), > > + }, > > + { > > + /* P1 667mts 1D */ > > + .drate = 667, > > + .fw_type = FW_1D_IMAGE, > > + .fsp_cfg = ddr_fsp1_cfg, > > + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), > > + }, > > +}; > > + > > +/* ddr timing config params */ > > +struct dram_timing_info dram_timing = { > > + .ddrc_cfg = ddr_ddrc_cfg, > > + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), > > + .ddrphy_cfg = ddr_ddrphy_cfg, > > + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), > > + .fsp_msg = ddr_dram_fsp_msg, > > + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), > > + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, > > + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), > > + .ddrphy_pie = ddr_phy_pie, > > + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), > > + .fsp_table = { 1600, 667, }, > > +}; > > + > > diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c > > index 14cb51368f..0d9909a662 100644 > > --- a/board/freescale/imx8mn_evk/spl.c > > +++ b/board/freescale/imx8mn_evk/spl.c > > @@ -83,6 +83,15 @@ int power_init_board(void) > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK) > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */ > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); > > + > > + /* Disable the BUCK2 */ > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48); > > + > > + /* Set NVCC_DRAM to 1.35v */ > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E); > > #else > > All this part is not done by the spl pmic driver? I have to admit I just borrowed this from the NXP downstream code. -- Heiko > > Michael > > > /* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */ > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); > > diff --git a/configs/imx8mn_ddr3l_evk_defconfig b/configs/imx8mn_ddr3l_evk_defconfig > > new file mode 100644 > > index 0000000000..b69fcea0cb > > --- /dev/null > > +++ b/configs/imx8mn_ddr3l_evk_defconfig > > @@ -0,0 +1,95 @@ > > +CONFIG_ARM=y > > +CONFIG_ARCH_IMX8M=y > > +CONFIG_SYS_TEXT_BASE=0x40200000 > > +CONFIG_SYS_MALLOC_LEN=0x2000000 > > +CONFIG_SPL_GPIO=y > > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > > +CONFIG_ENV_SIZE=0x1000 > > +CONFIG_ENV_OFFSET=0x400000 > > +CONFIG_DM_GPIO=y > > +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr3l-evk" > > +CONFIG_SPL_TEXT_BASE=0x912000 > > +CONFIG_TARGET_IMX8MN_DDR3L_EVK=y > > +CONFIG_SPL_SERIAL=y > > +CONFIG_SPL_DRIVERS_MISC=y > > +CONFIG_SPL=y > > +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 > > +CONFIG_SYS_LOAD_ADDR=0x42000000 > > +CONFIG_DISTRO_DEFAULTS=y > > +CONFIG_FIT=y > > +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 > > +CONFIG_SPL_LOAD_FIT=y > > +# CONFIG_USE_SPL_FIT_GENERATOR is not set > > +CONFIG_OF_SYSTEM_SETUP=y > > +CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr3l-evk.dtb" > > +CONFIG_ARCH_MISC_INIT=y > > +CONFIG_BOARD_LATE_INIT=y > > +CONFIG_SPL_BOARD_INIT=y > > +CONFIG_SPL_BOOTROM_SUPPORT=y > > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y > > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 > > +CONFIG_SPL_I2C=y > > +CONFIG_SPL_POWER=y > > +CONFIG_SPL_WATCHDOG=y > > +CONFIG_SYS_PROMPT="u-boot=> " > > +# CONFIG_CMD_EXPORTENV is not set > > +# CONFIG_CMD_IMPORTENV is not set > > +CONFIG_CMD_ERASEENV=y > > +# CONFIG_CMD_CRC32 is not set > > +CONFIG_CMD_CLK=y > > +CONFIG_CMD_FUSE=y > > +CONFIG_CMD_GPIO=y > > +CONFIG_CMD_I2C=y > > +CONFIG_CMD_MMC=y > > +CONFIG_CMD_CACHE=y > > +CONFIG_CMD_REGULATOR=y > > +CONFIG_CMD_EXT4_WRITE=y > > +CONFIG_OF_CONTROL=y > > +CONFIG_SPL_OF_CONTROL=y > > +CONFIG_ENV_OVERWRITE=y > > +CONFIG_ENV_IS_IN_MMC=y > > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y > > +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y > > +CONFIG_SPL_DM=y > > +CONFIG_SPL_CLK_IMX8MN=y > > +CONFIG_CLK_IMX8MN=y > > +CONFIG_MXC_GPIO=y > > +CONFIG_DM_I2C=y > > +CONFIG_SUPPORT_EMMC_BOOT=y > > +CONFIG_MMC_IO_VOLTAGE=y > > +CONFIG_MMC_UHS_SUPPORT=y > > +CONFIG_MMC_HS400_ES_SUPPORT=y > > +CONFIG_MMC_HS400_SUPPORT=y > > +CONFIG_FSL_USDHC=y > > +CONFIG_DM_SPI_FLASH=y > > +CONFIG_SPI_FLASH_SFDP_SUPPORT=y > > +CONFIG_SPI_FLASH_STMICRO=y > > +CONFIG_PHYLIB=y > > +CONFIG_PHY_ATHEROS=y > > +CONFIG_DM_ETH=y > > +CONFIG_DM_ETH_PHY=y > > +CONFIG_PHY_GIGE=y > > +CONFIG_FEC_MXC=y > > +CONFIG_MII=y > > +CONFIG_PINCTRL=y > > +CONFIG_SPL_PINCTRL=y > > +CONFIG_PINCTRL_IMX8M=y > > +CONFIG_DM_PMIC=y > > +CONFIG_SPL_DM_PMIC_PCA9450=y > > +CONFIG_DM_REGULATOR=y > > +CONFIG_DM_REGULATOR_FIXED=y > > +CONFIG_DM_REGULATOR_GPIO=y > > +# CONFIG_SPECIFY_CONSOLE_INDEX is not set > > +CONFIG_DM_SERIAL=y > > +# CONFIG_SPL_DM_SERIAL is not set > > +CONFIG_MXC_UART=y > > +CONFIG_SPI=y > > +CONFIG_DM_SPI=y > > +CONFIG_NXP_FSPI=y > > +CONFIG_SYSRESET=y > > +CONFIG_SPL_SYSRESET=y > > +CONFIG_SYSRESET_PSCI=y > > +CONFIG_SYSRESET_WATCHDOG=y > > +CONFIG_DM_THERMAL=y > > +CONFIG_IMX_WATCHDOG=y > > diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h > > index 805ae2a751..34278e2c84 100644 > > --- a/include/configs/imx8mn_evk.h > > +++ b/include/configs/imx8mn_evk.h > > @@ -73,7 +73,11 @@ > > > > #define CONFIG_SYS_SDRAM_BASE 0x40000000 > > #define PHYS_SDRAM 0x40000000 > > +#ifdef CONFIG_TARGET_IMX8MN_DDR3L_EVK > > +#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ > > +#else > > #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ > > +#endif > > > > #define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) > > > > -- > > 2.20.1 > > > > > -- > Michael Nazzareno Trimarchi > Co-Founder & Chief Executive Officer > M. +39 347 913 2170 > michael@amarulasolutions.com > __________________________________ > > Amarula Solutions BV > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > T. +31 (0)85 111 9172 > info@amarulasolutions.com > www.amarulasolutions.com ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support 2022-06-14 6:55 ` Michael Nazzareno Trimarchi 2022-06-14 11:50 ` Heiko Thiery @ 2022-06-15 6:23 ` Heiko Thiery 2022-06-15 6:43 ` Michael Nazzareno Trimarchi 1 sibling, 1 reply; 15+ messages in thread From: Heiko Thiery @ 2022-06-15 6:23 UTC (permalink / raw) To: Michael Nazzareno Trimarchi, Marek Vasut Cc: u-boot, Ying-Chun Liu, Peng Fan, Fabio Estevam, Marcel Ziswiler, Tim Harvey, Sean Anderson, Thomas Schäfer, Stefano Babic, Fabio Estevam Hi Marek, [SNIP] > > diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c > > index 14cb51368f..0d9909a662 100644 > > --- a/board/freescale/imx8mn_evk/spl.c > > +++ b/board/freescale/imx8mn_evk/spl.c > > @@ -83,6 +83,15 @@ int power_init_board(void) > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK) > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */ > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); > > + > > + /* Disable the BUCK2 */ > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48); > > + > > + /* Set NVCC_DRAM to 1.35v */ > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E); > > #else > > All this part is not done by the spl pmic driver? I saw that you added the PCA9450 driver. Do you know if this initialization can be done by the driver when CONFIG_SPL_DM_REGULATOR is enabled? If I see this correctly, it can't be done. Is that correct? -- Heiko ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support 2022-06-15 6:23 ` Heiko Thiery @ 2022-06-15 6:43 ` Michael Nazzareno Trimarchi 2022-06-18 21:56 ` Heiko Thiery 0 siblings, 1 reply; 15+ messages in thread From: Michael Nazzareno Trimarchi @ 2022-06-15 6:43 UTC (permalink / raw) To: Heiko Thiery Cc: Marek Vasut, u-boot, Ying-Chun Liu, Peng Fan, Fabio Estevam, Marcel Ziswiler, Tim Harvey, Sean Anderson, Thomas Schäfer, Stefano Babic, Fabio Estevam Hi Heiko On Wed, Jun 15, 2022 at 8:23 AM Heiko Thiery <heiko.thiery@gmail.com> wrote: > > Hi Marek, > > [SNIP] > > > > diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c > > > index 14cb51368f..0d9909a662 100644 > > > --- a/board/freescale/imx8mn_evk/spl.c > > > +++ b/board/freescale/imx8mn_evk/spl.c > > > @@ -83,6 +83,15 @@ int power_init_board(void) > > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE > > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ > > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); > > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK) > > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */ > > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); > > > + > > > + /* Disable the BUCK2 */ > > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48); > > > + > > > + /* Set NVCC_DRAM to 1.35v */ > > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E); > > > #else > > > > All this part is not done by the spl pmic driver? > > I saw that you added the PCA9450 driver. Do you know if this > initialization can be done by the driver when CONFIG_SPL_DM_REGULATOR > is enabled? If I see this correctly, it can't be done. Is that > correct? +&i2c1 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + Maybe something like this should work. Now question is about should be done in pre-reloc or not Michael > > -- > Heiko -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 michael@amarulasolutions.com __________________________________ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 info@amarulasolutions.com www.amarulasolutions.com ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support 2022-06-15 6:43 ` Michael Nazzareno Trimarchi @ 2022-06-18 21:56 ` Heiko Thiery 2022-06-19 5:58 ` Michael Nazzareno Trimarchi 0 siblings, 1 reply; 15+ messages in thread From: Heiko Thiery @ 2022-06-18 21:56 UTC (permalink / raw) To: Michael Nazzareno Trimarchi, Marek Vasut Cc: u-boot, Ying-Chun Liu, Peng Fan, Fabio Estevam, Marcel Ziswiler, Tim Harvey, Sean Anderson, Thomas Schäfer, Stefano Babic, Fabio Estevam Hi Michael, Hi Marek, Am Mi., 15. Juni 2022 um 08:43 Uhr schrieb Michael Nazzareno Trimarchi <michael@amarulasolutions.com>: > > Hi Heiko > > On Wed, Jun 15, 2022 at 8:23 AM Heiko Thiery <heiko.thiery@gmail.com> wrote: > > > > Hi Marek, > > > > [SNIP] > > > > > > diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c > > > > index 14cb51368f..0d9909a662 100644 > > > > --- a/board/freescale/imx8mn_evk/spl.c > > > > +++ b/board/freescale/imx8mn_evk/spl.c > > > > @@ -83,6 +83,15 @@ int power_init_board(void) > > > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE > > > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ > > > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); > > > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK) > > > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */ > > > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); > > > > + > > > > + /* Disable the BUCK2 */ > > > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48); > > > > + > > > > + /* Set NVCC_DRAM to 1.35v */ > > > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E); > > > > #else > > > > > > All this part is not done by the spl pmic driver? > > > > I saw that you added the PCA9450 driver. Do you know if this > > initialization can be done by the driver when CONFIG_SPL_DM_REGULATOR > > is enabled? If I see this correctly, it can't be done. Is that > > correct? > > +&i2c1 { > + u-boot,dm-spl; > +}; > + > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { > + u-boot,dm-spl; > +}; > + > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { > + u-boot,dm-spl; > +}; > + > +&pinctrl_i2c1 { > + u-boot,dm-spl; > +}; > + > +&pinctrl_pmic { > + u-boot,dm-spl; > +}; > + > > Maybe something like this should work. Now question is about should be > done in pre-reloc or not It took me a little while to understand what was meant by this. In the meantime I could change the PMIC/Regulator initialization to DT/DM and can make the setting so. What is not clear to me yet is at which point this should be done (regulators_enable_boot_on()). Currently I do it in the board/spl specific board_init_f(). Do any of you have any advice here? Thanks -- Heiko > Michael > > > > -- > > Heiko > > > > -- > Michael Nazzareno Trimarchi > Co-Founder & Chief Executive Officer > M. +39 347 913 2170 > michael@amarulasolutions.com > __________________________________ > > Amarula Solutions BV > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > T. +31 (0)85 111 9172 > info@amarulasolutions.com > www.amarulasolutions.com ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support 2022-06-18 21:56 ` Heiko Thiery @ 2022-06-19 5:58 ` Michael Nazzareno Trimarchi 2022-06-19 6:11 ` Heiko Thiery 0 siblings, 1 reply; 15+ messages in thread From: Michael Nazzareno Trimarchi @ 2022-06-19 5:58 UTC (permalink / raw) To: Heiko Thiery Cc: Marek Vasut, U-Boot-Denx, Ying-Chun Liu, Peng Fan, Fabio Estevam, Marcel Ziswiler, Tim Harvey, Sean Anderson, Thomas Schäfer, Stefano Babic, Fabio Estevam Hi Il sab 18 giu 2022, 23:56 Heiko Thiery <heiko.thiery@gmail.com> ha scritto: > Hi Michael, Hi Marek, > > Am Mi., 15. Juni 2022 um 08:43 Uhr schrieb Michael Nazzareno Trimarchi > <michael@amarulasolutions.com>: > > > > Hi Heiko > > > > On Wed, Jun 15, 2022 at 8:23 AM Heiko Thiery <heiko.thiery@gmail.com> > wrote: > > > > > > Hi Marek, > > > > > > [SNIP] > > > > > > > > diff --git a/board/freescale/imx8mn_evk/spl.c > b/board/freescale/imx8mn_evk/spl.c > > > > > index 14cb51368f..0d9909a662 100644 > > > > > --- a/board/freescale/imx8mn_evk/spl.c > > > > > +++ b/board/freescale/imx8mn_evk/spl.c > > > > > @@ -83,6 +83,15 @@ int power_init_board(void) > > > > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE > > > > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ > > > > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); > > > > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK) > > > > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */ > > > > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); > > > > > + > > > > > + /* Disable the BUCK2 */ > > > > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48); > > > > > + > > > > > + /* Set NVCC_DRAM to 1.35v */ > > > > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E); > > > > > #else > > > > > > > > All this part is not done by the spl pmic driver? > > > > > > I saw that you added the PCA9450 driver. Do you know if this > > > initialization can be done by the driver when CONFIG_SPL_DM_REGULATOR > > > is enabled? If I see this correctly, it can't be done. Is that > > > correct? > > > > +&i2c1 { > > + u-boot,dm-spl; > > +}; > > + > > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { > > + u-boot,dm-spl; > > +}; > > + > > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { > > + u-boot,dm-spl; > > +}; > > + > > +&pinctrl_i2c1 { > > + u-boot,dm-spl; > > +}; > > + > > +&pinctrl_pmic { > > + u-boot,dm-spl; > > +}; > > + > > > > Maybe something like this should work. Now question is about should be > > done in pre-reloc or not > > It took me a little while to understand what was meant by this. In the > meantime I could > change the PMIC/Regulator initialization to DT/DM and can make the setting > so. > What is not clear to me yet is at which point this should be done > (regulators_enable_boot_on()). Currently I do it in the board/spl > specific board_init_f(). > > Do any of you have any advice here? > After having a discussion with you, i found that maybe i have some problem and some of the setting should be done before ddr inizialization. I will take a look on it on afternoon. I know marek was working on some way to probe driver during binding and we need even to be sure that this can happen before memory training. Michael > > Thanks > -- > Heiko > > > Michael > > > > > > -- > > > Heiko > > > > > > > > -- > > Michael Nazzareno Trimarchi > > Co-Founder & Chief Executive Officer > > M. +39 347 913 2170 > > michael@amarulasolutions.com > > __________________________________ > > > > Amarula Solutions BV > > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > > T. +31 (0)85 111 9172 > > info@amarulasolutions.com > > www.amarulasolutions.com > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support 2022-06-19 5:58 ` Michael Nazzareno Trimarchi @ 2022-06-19 6:11 ` Heiko Thiery 2022-06-19 14:40 ` Michael Nazzareno Trimarchi 0 siblings, 1 reply; 15+ messages in thread From: Heiko Thiery @ 2022-06-19 6:11 UTC (permalink / raw) To: Michael Nazzareno Trimarchi Cc: Marek Vasut, U-Boot-Denx, Ying-Chun Liu, Peng Fan, Fabio Estevam, Marcel Ziswiler, Tim Harvey, Sean Anderson, Thomas Schäfer, Stefano Babic, Fabio Estevam Hi, Am So., 19. Juni 2022 um 07:59 Uhr schrieb Michael Nazzareno Trimarchi <michael@amarulasolutions.com>: > > Hi > > Il sab 18 giu 2022, 23:56 Heiko Thiery <heiko.thiery@gmail.com> ha scritto: >> >> Hi Michael, Hi Marek, >> >> Am Mi., 15. Juni 2022 um 08:43 Uhr schrieb Michael Nazzareno Trimarchi >> <michael@amarulasolutions.com>: >> > >> > Hi Heiko >> > >> > On Wed, Jun 15, 2022 at 8:23 AM Heiko Thiery <heiko.thiery@gmail.com> wrote: >> > > >> > > Hi Marek, >> > > >> > > [SNIP] >> > > >> > > > > diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c >> > > > > index 14cb51368f..0d9909a662 100644 >> > > > > --- a/board/freescale/imx8mn_evk/spl.c >> > > > > +++ b/board/freescale/imx8mn_evk/spl.c >> > > > > @@ -83,6 +83,15 @@ int power_init_board(void) >> > > > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE >> > > > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ >> > > > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); >> > > > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK) >> > > > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */ >> > > > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); >> > > > > + >> > > > > + /* Disable the BUCK2 */ >> > > > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48); >> > > > > + >> > > > > + /* Set NVCC_DRAM to 1.35v */ >> > > > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E); >> > > > > #else >> > > > >> > > > All this part is not done by the spl pmic driver? >> > > >> > > I saw that you added the PCA9450 driver. Do you know if this >> > > initialization can be done by the driver when CONFIG_SPL_DM_REGULATOR >> > > is enabled? If I see this correctly, it can't be done. Is that >> > > correct? >> > >> > +&i2c1 { >> > + u-boot,dm-spl; >> > +}; >> > + >> > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { >> > + u-boot,dm-spl; >> > +}; >> > + >> > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { >> > + u-boot,dm-spl; >> > +}; >> > + >> > +&pinctrl_i2c1 { >> > + u-boot,dm-spl; >> > +}; >> > + >> > +&pinctrl_pmic { >> > + u-boot,dm-spl; >> > +}; >> > + >> > >> > Maybe something like this should work. Now question is about should be >> > done in pre-reloc or not >> >> It took me a little while to understand what was meant by this. In the >> meantime I could >> change the PMIC/Regulator initialization to DT/DM and can make the setting so. >> What is not clear to me yet is at which point this should be done >> (regulators_enable_boot_on()). Currently I do it in the board/spl >> specific board_init_f(). >> >> Do any of you have any advice here? > > > After having a discussion with you, i found that maybe i have some problem and some of the setting should be done before ddr inizialization. I will take a look on it on afternoon. I know marek was working on some way to probe driver during binding and we need even to be sure that this can happen before memory training. > Currently I added it in board_init_f() right before spl_dram_init() [1] and it works. I also tried to put it in power_init_board() [2] but this does not work. [1] https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L162 [2] https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L62 -- Heiko > Michael >> >> >> Thanks >> -- >> Heiko >> >> > Michael >> > > >> > > -- >> > > Heiko >> > >> > >> > >> > -- >> > Michael Nazzareno Trimarchi >> > Co-Founder & Chief Executive Officer >> > M. +39 347 913 2170 >> > michael@amarulasolutions.com >> > __________________________________ >> > >> > Amarula Solutions BV >> > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL >> > T. +31 (0)85 111 9172 >> > info@amarulasolutions.com >> > www.amarulasolutions.com ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support 2022-06-19 6:11 ` Heiko Thiery @ 2022-06-19 14:40 ` Michael Nazzareno Trimarchi 2022-06-19 14:47 ` Heiko Thiery 0 siblings, 1 reply; 15+ messages in thread From: Michael Nazzareno Trimarchi @ 2022-06-19 14:40 UTC (permalink / raw) To: Heiko Thiery Cc: Marek Vasut, U-Boot-Denx, Ying-Chun Liu, Peng Fan, Fabio Estevam, Marcel Ziswiler, Tim Harvey, Sean Anderson, Thomas Schäfer, Stefano Babic, Fabio Estevam Hi Heiko On Sun, Jun 19, 2022 at 8:12 AM Heiko Thiery <heiko.thiery@gmail.com> wrote: > > Hi, > > Am So., 19. Juni 2022 um 07:59 Uhr schrieb Michael Nazzareno Trimarchi > <michael@amarulasolutions.com>: > > > > Hi > > > > Il sab 18 giu 2022, 23:56 Heiko Thiery <heiko.thiery@gmail.com> ha scritto: > >> > >> Hi Michael, Hi Marek, > >> > >> Am Mi., 15. Juni 2022 um 08:43 Uhr schrieb Michael Nazzareno Trimarchi > >> <michael@amarulasolutions.com>: > >> > > >> > Hi Heiko > >> > > >> > On Wed, Jun 15, 2022 at 8:23 AM Heiko Thiery <heiko.thiery@gmail.com> wrote: > >> > > > >> > > Hi Marek, > >> > > > >> > > [SNIP] > >> > > > >> > > > > diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c > >> > > > > index 14cb51368f..0d9909a662 100644 > >> > > > > --- a/board/freescale/imx8mn_evk/spl.c > >> > > > > +++ b/board/freescale/imx8mn_evk/spl.c > >> > > > > @@ -83,6 +83,15 @@ int power_init_board(void) > >> > > > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE > >> > > > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ > >> > > > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); > >> > > > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK) > >> > > > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */ > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); > >> > > > > + > >> > > > > + /* Disable the BUCK2 */ > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48); > >> > > > > + > >> > > > > + /* Set NVCC_DRAM to 1.35v */ > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E); > >> > > > > #else > >> > > > > >> > > > All this part is not done by the spl pmic driver? > >> > > > >> > > I saw that you added the PCA9450 driver. Do you know if this > >> > > initialization can be done by the driver when CONFIG_SPL_DM_REGULATOR > >> > > is enabled? If I see this correctly, it can't be done. Is that > >> > > correct? > >> > > >> > +&i2c1 { > >> > + u-boot,dm-spl; > >> > +}; > >> > + > >> > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { > >> > + u-boot,dm-spl; > >> > +}; > >> > + > >> > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { > >> > + u-boot,dm-spl; > >> > +}; > >> > + > >> > +&pinctrl_i2c1 { > >> > + u-boot,dm-spl; > >> > +}; > >> > + > >> > +&pinctrl_pmic { > >> > + u-boot,dm-spl; > >> > +}; > >> > + > >> > > >> > Maybe something like this should work. Now question is about should be > >> > done in pre-reloc or not > >> > >> It took me a little while to understand what was meant by this. In the > >> meantime I could > >> change the PMIC/Regulator initialization to DT/DM and can make the setting so. > >> What is not clear to me yet is at which point this should be done > >> (regulators_enable_boot_on()). Currently I do it in the board/spl > >> specific board_init_f(). > >> > >> Do any of you have any advice here? > > > > > > After having a discussion with you, i found that maybe i have some problem and some of the setting should be done before ddr inizialization. I will take a look on it on afternoon. I know marek was working on some way to probe driver during binding and we need even to be sure that this can happen before memory training. > > > > Currently I added it in board_init_f() right before spl_dram_init() > [1] and it works. I also tried to put it in power_init_board() [2] but > this does not work. > > [1] https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L162 > [2] https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L62 Does it work if you mark pre-reoloc, pmic, i2c, and pinctrl? Michael > > -- > Heiko > > > Michael > >> > >> > >> Thanks > >> -- > >> Heiko > >> > >> > Michael > >> > > > >> > > -- > >> > > Heiko > >> > > >> > > >> > > >> > -- > >> > Michael Nazzareno Trimarchi > >> > Co-Founder & Chief Executive Officer > >> > M. +39 347 913 2170 > >> > michael@amarulasolutions.com > >> > __________________________________ > >> > > >> > Amarula Solutions BV > >> > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > >> > T. +31 (0)85 111 9172 > >> > info@amarulasolutions.com > >> > www.amarulasolutions.com -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 michael@amarulasolutions.com __________________________________ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 info@amarulasolutions.com www.amarulasolutions.com ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support 2022-06-19 14:40 ` Michael Nazzareno Trimarchi @ 2022-06-19 14:47 ` Heiko Thiery 2022-06-19 14:50 ` Heiko Thiery 2022-06-19 14:50 ` Michael Nazzareno Trimarchi 0 siblings, 2 replies; 15+ messages in thread From: Heiko Thiery @ 2022-06-19 14:47 UTC (permalink / raw) To: Michael Nazzareno Trimarchi Cc: Marek Vasut, U-Boot-Denx, Ying-Chun Liu, Peng Fan, Fabio Estevam, Marcel Ziswiler, Tim Harvey, Sean Anderson, Thomas Schäfer, Stefano Babic, Fabio Estevam Hi, Am So., 19. Juni 2022 um 16:40 Uhr schrieb Michael Nazzareno Trimarchi <michael@amarulasolutions.com>: > > Hi Heiko > > On Sun, Jun 19, 2022 at 8:12 AM Heiko Thiery <heiko.thiery@gmail.com> wrote: > > > > Hi, > > > > Am So., 19. Juni 2022 um 07:59 Uhr schrieb Michael Nazzareno Trimarchi > > <michael@amarulasolutions.com>: > > > > > > Hi > > > > > > Il sab 18 giu 2022, 23:56 Heiko Thiery <heiko.thiery@gmail.com> ha scritto: > > >> > > >> Hi Michael, Hi Marek, > > >> > > >> Am Mi., 15. Juni 2022 um 08:43 Uhr schrieb Michael Nazzareno Trimarchi > > >> <michael@amarulasolutions.com>: > > >> > > > >> > Hi Heiko > > >> > > > >> > On Wed, Jun 15, 2022 at 8:23 AM Heiko Thiery <heiko.thiery@gmail.com> wrote: > > >> > > > > >> > > Hi Marek, > > >> > > > > >> > > [SNIP] > > >> > > > > >> > > > > diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c > > >> > > > > index 14cb51368f..0d9909a662 100644 > > >> > > > > --- a/board/freescale/imx8mn_evk/spl.c > > >> > > > > +++ b/board/freescale/imx8mn_evk/spl.c > > >> > > > > @@ -83,6 +83,15 @@ int power_init_board(void) > > >> > > > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE > > >> > > > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ > > >> > > > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); > > >> > > > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK) > > >> > > > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */ > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); > > >> > > > > + > > >> > > > > + /* Disable the BUCK2 */ > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48); > > >> > > > > + > > >> > > > > + /* Set NVCC_DRAM to 1.35v */ > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E); > > >> > > > > #else > > >> > > > > > >> > > > All this part is not done by the spl pmic driver? > > >> > > > > >> > > I saw that you added the PCA9450 driver. Do you know if this > > >> > > initialization can be done by the driver when CONFIG_SPL_DM_REGULATOR > > >> > > is enabled? If I see this correctly, it can't be done. Is that > > >> > > correct? > > >> > > > >> > +&i2c1 { > > >> > + u-boot,dm-spl; > > >> > +}; > > >> > + > > >> > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { > > >> > + u-boot,dm-spl; > > >> > +}; > > >> > + > > >> > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { > > >> > + u-boot,dm-spl; > > >> > +}; > > >> > + > > >> > +&pinctrl_i2c1 { > > >> > + u-boot,dm-spl; > > >> > +}; > > >> > + > > >> > +&pinctrl_pmic { > > >> > + u-boot,dm-spl; > > >> > +}; > > >> > + > > >> > > > >> > Maybe something like this should work. Now question is about should be > > >> > done in pre-reloc or not > > >> > > >> It took me a little while to understand what was meant by this. In the > > >> meantime I could > > >> change the PMIC/Regulator initialization to DT/DM and can make the setting so. > > >> What is not clear to me yet is at which point this should be done > > >> (regulators_enable_boot_on()). Currently I do it in the board/spl > > >> specific board_init_f(). > > >> > > >> Do any of you have any advice here? > > > > > > > > > After having a discussion with you, i found that maybe i have some problem and some of the setting should be done before ddr inizialization. I will take a look on it on afternoon. I know marek was working on some way to probe driver during binding and we need even to be sure that this can happen before memory training. > > > > > > > Currently I added it in board_init_f() right before spl_dram_init() > > [1] and it works. I also tried to put it in power_init_board() [2] but > > this does not work. > > > > [1] https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L162 > > [2] https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L62 > > Does it work if you mark pre-reoloc, pmic, i2c, and pinctrl? I added on all nodes the u-boot,dm-pre-reloc but this does not help when trying to do the init in power_init_board(). > > Michael > > > > > -- > > Heiko > > > > > Michael > > >> > > >> > > >> Thanks > > >> -- > > >> Heiko > > >> > > >> > Michael > > >> > > > > >> > > -- > > >> > > Heiko > > >> > > > >> > > > >> > > > >> > -- > > >> > Michael Nazzareno Trimarchi > > >> > Co-Founder & Chief Executive Officer > > >> > M. +39 347 913 2170 > > >> > michael@amarulasolutions.com > > >> > __________________________________ > > >> > > > >> > Amarula Solutions BV > > >> > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > > >> > T. +31 (0)85 111 9172 > > >> > info@amarulasolutions.com > > >> > www.amarulasolutions.com > > > > -- > Michael Nazzareno Trimarchi > Co-Founder & Chief Executive Officer > M. +39 347 913 2170 > michael@amarulasolutions.com > __________________________________ > > Amarula Solutions BV > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > T. +31 (0)85 111 9172 > info@amarulasolutions.com > www.amarulasolutions.com ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support 2022-06-19 14:47 ` Heiko Thiery @ 2022-06-19 14:50 ` Heiko Thiery 2022-06-19 14:50 ` Michael Nazzareno Trimarchi 1 sibling, 0 replies; 15+ messages in thread From: Heiko Thiery @ 2022-06-19 14:50 UTC (permalink / raw) To: Michael Nazzareno Trimarchi Cc: Marek Vasut, U-Boot-Denx, Ying-Chun Liu, Peng Fan, Fabio Estevam, Marcel Ziswiler, Tim Harvey, Sean Anderson, Thomas Schäfer, Stefano Babic, Fabio Estevam Hi [snip] > > > >> > Maybe something like this should work. Now question is about should be > > > >> > done in pre-reloc or not > > > >> > > > >> It took me a little while to understand what was meant by this. In the > > > >> meantime I could > > > >> change the PMIC/Regulator initialization to DT/DM and can make the setting so. > > > >> What is not clear to me yet is at which point this should be done > > > >> (regulators_enable_boot_on()). Currently I do it in the board/spl > > > >> specific board_init_f(). > > > >> > > > >> Do any of you have any advice here? > > > > > > > > > > > > After having a discussion with you, i found that maybe i have some problem and some of the setting should be done before ddr inizialization. I will take a look on it on afternoon. I know marek was working on some way to probe driver during binding and we need even to be sure that this can happen before memory training. > > > > > > > > > > Currently I added it in board_init_f() right before spl_dram_init() > > > [1] and it works. I also tried to put it in power_init_board() [2] but > > > this does not work. > > > > > > [1] https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L162 > > > [2] https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L62 > > > > Does it work if you mark pre-reoloc, pmic, i2c, and pinctrl? > > I added on all nodes the u-boot,dm-pre-reloc but this does not help > when trying to do the init in power_init_board(). This is how the dtsi looks like: // SPDX-License-Identifier: GPL-2.0-or-later OR MIT #include "imx8mn-u-boot.dtsi" #include "imx8mn-ddr4-evk-u-boot.dtsi" &i2c1 { u-boot,dm-spl; u-boot,dm-pre-reloc; }; &{/soc@0/bus@30800000} { u-boot,dm-spl; u-boot,dm-pre-reloc; }; &{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { u-boot,dm-spl; u-boot,dm-pre-reloc; }; &{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { u-boot,dm-spl; u-boot,dm-pre-reloc; BUCK1 { u-boot,dm-spl; u-boot,dm-pre-reloc; }; BUCK4 { u-boot,dm-spl; u-boot,dm-pre-reloc; }; BUCK5 { u-boot,dm-spl; u-boot,dm-pre-reloc; }; BUCK6 { u-boot,dm-spl; u-boot,dm-pre-reloc; }; LDO1 { u-boot,dm-spl; u-boot,dm-pre-reloc; }; LDO2 { u-boot,dm-spl; u-boot,dm-pre-reloc; }; LDO3 { u-boot,dm-spl; u-boot,dm-pre-reloc; }; LDO4 { u-boot,dm-spl; u-boot,dm-pre-reloc; }; LDO5 { u-boot,dm-spl; u-boot,dm-pre-reloc; }; }; &pinctrl_i2c1 { u-boot,dm-spl; u-boot,dm-pre-reloc; }; &pinctrl_pmic { u-boot,dm-spl; u-boot,dm-pre-reloc; }; &wdog1 { u-boot,dm-spl; }; ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support 2022-06-19 14:47 ` Heiko Thiery 2022-06-19 14:50 ` Heiko Thiery @ 2022-06-19 14:50 ` Michael Nazzareno Trimarchi 2022-06-19 14:53 ` Heiko Thiery 1 sibling, 1 reply; 15+ messages in thread From: Michael Nazzareno Trimarchi @ 2022-06-19 14:50 UTC (permalink / raw) To: Heiko Thiery Cc: Marek Vasut, U-Boot-Denx, Ying-Chun Liu, Peng Fan, Fabio Estevam, Marcel Ziswiler, Tim Harvey, Sean Anderson, Thomas Schäfer, Stefano Babic, Fabio Estevam Hi Il dom 19 giu 2022, 16:47 Heiko Thiery <heiko.thiery@gmail.com> ha scritto: > Hi, > > Am So., 19. Juni 2022 um 16:40 Uhr schrieb Michael Nazzareno Trimarchi > <michael@amarulasolutions.com>: > > > > Hi Heiko > > > > On Sun, Jun 19, 2022 at 8:12 AM Heiko Thiery <heiko.thiery@gmail.com> > wrote: > > > > > > Hi, > > > > > > Am So., 19. Juni 2022 um 07:59 Uhr schrieb Michael Nazzareno Trimarchi > > > <michael@amarulasolutions.com>: > > > > > > > > Hi > > > > > > > > Il sab 18 giu 2022, 23:56 Heiko Thiery <heiko.thiery@gmail.com> ha > scritto: > > > >> > > > >> Hi Michael, Hi Marek, > > > >> > > > >> Am Mi., 15. Juni 2022 um 08:43 Uhr schrieb Michael Nazzareno > Trimarchi > > > >> <michael@amarulasolutions.com>: > > > >> > > > > >> > Hi Heiko > > > >> > > > > >> > On Wed, Jun 15, 2022 at 8:23 AM Heiko Thiery < > heiko.thiery@gmail.com> wrote: > > > >> > > > > > >> > > Hi Marek, > > > >> > > > > > >> > > [SNIP] > > > >> > > > > > >> > > > > diff --git a/board/freescale/imx8mn_evk/spl.c > b/board/freescale/imx8mn_evk/spl.c > > > >> > > > > index 14cb51368f..0d9909a662 100644 > > > >> > > > > --- a/board/freescale/imx8mn_evk/spl.c > > > >> > > > > +++ b/board/freescale/imx8mn_evk/spl.c > > > >> > > > > @@ -83,6 +83,15 @@ int power_init_board(void) > > > >> > > > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE > > > >> > > > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode > */ > > > >> > > > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); > > > >> > > > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK) > > > >> > > > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */ > > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); > > > >> > > > > + > > > >> > > > > + /* Disable the BUCK2 */ > > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48); > > > >> > > > > + > > > >> > > > > + /* Set NVCC_DRAM to 1.35v */ > > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E); > > > >> > > > > #else > > > >> > > > > > > >> > > > All this part is not done by the spl pmic driver? > > > >> > > > > > >> > > I saw that you added the PCA9450 driver. Do you know if this > > > >> > > initialization can be done by the driver when > CONFIG_SPL_DM_REGULATOR > > > >> > > is enabled? If I see this correctly, it can't be done. Is that > > > >> > > correct? > > > >> > > > > >> > +&i2c1 { > > > >> > + u-boot,dm-spl; > > > >> > +}; > > > >> > + > > > >> > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { > > > >> > + u-boot,dm-spl; > > > >> > +}; > > > >> > + > > > >> > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { > > > >> > + u-boot,dm-spl; > > > >> > +}; > > > >> > + > > > >> > +&pinctrl_i2c1 { > > > >> > + u-boot,dm-spl; > > > >> > +}; > > > >> > + > > > >> > +&pinctrl_pmic { > > > >> > + u-boot,dm-spl; > > > >> > +}; > > > >> > + > > > >> > > > > >> > Maybe something like this should work. Now question is about > should be > > > >> > done in pre-reloc or not > > > >> > > > >> It took me a little while to understand what was meant by this. In > the > > > >> meantime I could > > > >> change the PMIC/Regulator initialization to DT/DM and can make the > setting so. > > > >> What is not clear to me yet is at which point this should be done > > > >> (regulators_enable_boot_on()). Currently I do it in the board/spl > > > >> specific board_init_f(). > > > >> > > > >> Do any of you have any advice here? > > > > > > > > > > > > After having a discussion with you, i found that maybe i have some > problem and some of the setting should be done before ddr inizialization. I > will take a look on it on afternoon. I know marek was working on some way > to probe driver during binding and we need even to be sure that this can > happen before memory training. > > > > > > > > > > Currently I added it in board_init_f() right before spl_dram_init() > > > [1] and it works. I also tried to put it in power_init_board() [2] but > > > this does not work. > > > > > > [1] > https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L162 > > > [2] > https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L62 > > > > Does it work if you mark pre-reoloc, pmic, i2c, and pinctrl? > > I added on all nodes the u-boot,dm-pre-reloc but this does not help > when trying to do the init in power_init_board(). > From code I navigate spl_early_init should bind the driver in pre-reloc Michael > > > > > Michael > > > > > > > > -- > > > Heiko > > > > > > > Michael > > > >> > > > >> > > > >> Thanks > > > >> -- > > > >> Heiko > > > >> > > > >> > Michael > > > >> > > > > > >> > > -- > > > >> > > Heiko > > > >> > > > > >> > > > > >> > > > > >> > -- > > > >> > Michael Nazzareno Trimarchi > > > >> > Co-Founder & Chief Executive Officer > > > >> > M. +39 347 913 2170 > > > >> > michael@amarulasolutions.com > > > >> > __________________________________ > > > >> > > > > >> > Amarula Solutions BV > > > >> > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > > > >> > T. +31 (0)85 111 9172 > > > >> > info@amarulasolutions.com > > > >> > www.amarulasolutions.com > > > > > > > > -- > > Michael Nazzareno Trimarchi > > Co-Founder & Chief Executive Officer > > M. +39 347 913 2170 > > michael@amarulasolutions.com > > __________________________________ > > > > Amarula Solutions BV > > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > > T. +31 (0)85 111 9172 > > info@amarulasolutions.com > > www.amarulasolutions.com > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support 2022-06-19 14:50 ` Michael Nazzareno Trimarchi @ 2022-06-19 14:53 ` Heiko Thiery 2022-08-22 11:42 ` Michael Nazzareno Trimarchi 0 siblings, 1 reply; 15+ messages in thread From: Heiko Thiery @ 2022-06-19 14:53 UTC (permalink / raw) To: Michael Nazzareno Trimarchi Cc: Marek Vasut, U-Boot-Denx, Ying-Chun Liu, Peng Fan, Fabio Estevam, Marcel Ziswiler, Tim Harvey, Sean Anderson, Thomas Schäfer, Stefano Babic, Fabio Estevam Hi, Am So., 19. Juni 2022 um 16:51 Uhr schrieb Michael Nazzareno Trimarchi <michael@amarulasolutions.com>: > > Hi > > Il dom 19 giu 2022, 16:47 Heiko Thiery <heiko.thiery@gmail.com> ha scritto: >> >> Hi, >> >> Am So., 19. Juni 2022 um 16:40 Uhr schrieb Michael Nazzareno Trimarchi >> <michael@amarulasolutions.com>: >> > >> > Hi Heiko >> > >> > On Sun, Jun 19, 2022 at 8:12 AM Heiko Thiery <heiko.thiery@gmail.com> wrote: >> > > >> > > Hi, >> > > >> > > Am So., 19. Juni 2022 um 07:59 Uhr schrieb Michael Nazzareno Trimarchi >> > > <michael@amarulasolutions.com>: >> > > > >> > > > Hi >> > > > >> > > > Il sab 18 giu 2022, 23:56 Heiko Thiery <heiko.thiery@gmail.com> ha scritto: >> > > >> >> > > >> Hi Michael, Hi Marek, >> > > >> >> > > >> Am Mi., 15. Juni 2022 um 08:43 Uhr schrieb Michael Nazzareno Trimarchi >> > > >> <michael@amarulasolutions.com>: >> > > >> > >> > > >> > Hi Heiko >> > > >> > >> > > >> > On Wed, Jun 15, 2022 at 8:23 AM Heiko Thiery <heiko.thiery@gmail.com> wrote: >> > > >> > > >> > > >> > > Hi Marek, >> > > >> > > >> > > >> > > [SNIP] >> > > >> > > >> > > >> > > > > diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c >> > > >> > > > > index 14cb51368f..0d9909a662 100644 >> > > >> > > > > --- a/board/freescale/imx8mn_evk/spl.c >> > > >> > > > > +++ b/board/freescale/imx8mn_evk/spl.c >> > > >> > > > > @@ -83,6 +83,15 @@ int power_init_board(void) >> > > >> > > > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE >> > > >> > > > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ >> > > >> > > > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); >> > > >> > > > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK) >> > > >> > > > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */ >> > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); >> > > >> > > > > + >> > > >> > > > > + /* Disable the BUCK2 */ >> > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48); >> > > >> > > > > + >> > > >> > > > > + /* Set NVCC_DRAM to 1.35v */ >> > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E); >> > > >> > > > > #else >> > > >> > > > >> > > >> > > > All this part is not done by the spl pmic driver? >> > > >> > > >> > > >> > > I saw that you added the PCA9450 driver. Do you know if this >> > > >> > > initialization can be done by the driver when CONFIG_SPL_DM_REGULATOR >> > > >> > > is enabled? If I see this correctly, it can't be done. Is that >> > > >> > > correct? >> > > >> > >> > > >> > +&i2c1 { >> > > >> > + u-boot,dm-spl; >> > > >> > +}; >> > > >> > + >> > > >> > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { >> > > >> > + u-boot,dm-spl; >> > > >> > +}; >> > > >> > + >> > > >> > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { >> > > >> > + u-boot,dm-spl; >> > > >> > +}; >> > > >> > + >> > > >> > +&pinctrl_i2c1 { >> > > >> > + u-boot,dm-spl; >> > > >> > +}; >> > > >> > + >> > > >> > +&pinctrl_pmic { >> > > >> > + u-boot,dm-spl; >> > > >> > +}; >> > > >> > + >> > > >> > >> > > >> > Maybe something like this should work. Now question is about should be >> > > >> > done in pre-reloc or not >> > > >> >> > > >> It took me a little while to understand what was meant by this. In the >> > > >> meantime I could >> > > >> change the PMIC/Regulator initialization to DT/DM and can make the setting so. >> > > >> What is not clear to me yet is at which point this should be done >> > > >> (regulators_enable_boot_on()). Currently I do it in the board/spl >> > > >> specific board_init_f(). >> > > >> >> > > >> Do any of you have any advice here? >> > > > >> > > > >> > > > After having a discussion with you, i found that maybe i have some problem and some of the setting should be done before ddr inizialization. I will take a look on it on afternoon. I know marek was working on some way to probe driver during binding and we need even to be sure that this can happen before memory training. >> > > > >> > > >> > > Currently I added it in board_init_f() right before spl_dram_init() >> > > [1] and it works. I also tried to put it in power_init_board() [2] but >> > > this does not work. >> > > >> > > [1] https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L162 >> > > [2] https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L62 >> > >> > Does it work if you mark pre-reoloc, pmic, i2c, and pinctrl? >> >> I added on all nodes the u-boot,dm-pre-reloc but this does not help >> when trying to do the init in power_init_board(). > > > From code I navigate spl_early_init should bind the driver in pre-reloc What function should be called to probe the driver? Currently I use regulators_enable_boot_on(). > Michael >> >> >> > >> > Michael >> > >> > > >> > > -- >> > > Heiko >> > > >> > > > Michael >> > > >> >> > > >> >> > > >> Thanks >> > > >> -- >> > > >> Heiko >> > > >> >> > > >> > Michael >> > > >> > > >> > > >> > > -- >> > > >> > > Heiko >> > > >> > >> > > >> > >> > > >> > >> > > >> > -- >> > > >> > Michael Nazzareno Trimarchi >> > > >> > Co-Founder & Chief Executive Officer >> > > >> > M. +39 347 913 2170 >> > > >> > michael@amarulasolutions.com >> > > >> > __________________________________ >> > > >> > >> > > >> > Amarula Solutions BV >> > > >> > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL >> > > >> > T. +31 (0)85 111 9172 >> > > >> > info@amarulasolutions.com >> > > >> > www.amarulasolutions.com >> > >> > >> > >> > -- >> > Michael Nazzareno Trimarchi >> > Co-Founder & Chief Executive Officer >> > M. +39 347 913 2170 >> > michael@amarulasolutions.com >> > __________________________________ >> > >> > Amarula Solutions BV >> > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL >> > T. +31 (0)85 111 9172 >> > info@amarulasolutions.com >> > www.amarulasolutions.com ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support 2022-06-19 14:53 ` Heiko Thiery @ 2022-08-22 11:42 ` Michael Nazzareno Trimarchi 0 siblings, 0 replies; 15+ messages in thread From: Michael Nazzareno Trimarchi @ 2022-08-22 11:42 UTC (permalink / raw) To: Heiko Thiery Cc: Marek Vasut, U-Boot-Denx, Ying-Chun Liu, Peng Fan, Fabio Estevam, Marcel Ziswiler, Tim Harvey, Sean Anderson, Thomas Schäfer, Stefano Babic, Fabio Estevam Hi Heiko Did you solve it after your patch on regulator? Michael On Sun, Jun 19, 2022 at 4:54 PM Heiko Thiery <heiko.thiery@gmail.com> wrote: > > Hi, > > Am So., 19. Juni 2022 um 16:51 Uhr schrieb Michael Nazzareno Trimarchi > <michael@amarulasolutions.com>: > > > > Hi > > > > Il dom 19 giu 2022, 16:47 Heiko Thiery <heiko.thiery@gmail.com> ha scritto: > >> > >> Hi, > >> > >> Am So., 19. Juni 2022 um 16:40 Uhr schrieb Michael Nazzareno Trimarchi > >> <michael@amarulasolutions.com>: > >> > > >> > Hi Heiko > >> > > >> > On Sun, Jun 19, 2022 at 8:12 AM Heiko Thiery <heiko.thiery@gmail.com> wrote: > >> > > > >> > > Hi, > >> > > > >> > > Am So., 19. Juni 2022 um 07:59 Uhr schrieb Michael Nazzareno Trimarchi > >> > > <michael@amarulasolutions.com>: > >> > > > > >> > > > Hi > >> > > > > >> > > > Il sab 18 giu 2022, 23:56 Heiko Thiery <heiko.thiery@gmail.com> ha scritto: > >> > > >> > >> > > >> Hi Michael, Hi Marek, > >> > > >> > >> > > >> Am Mi., 15. Juni 2022 um 08:43 Uhr schrieb Michael Nazzareno Trimarchi > >> > > >> <michael@amarulasolutions.com>: > >> > > >> > > >> > > >> > Hi Heiko > >> > > >> > > >> > > >> > On Wed, Jun 15, 2022 at 8:23 AM Heiko Thiery <heiko.thiery@gmail.com> wrote: > >> > > >> > > > >> > > >> > > Hi Marek, > >> > > >> > > > >> > > >> > > [SNIP] > >> > > >> > > > >> > > >> > > > > diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c > >> > > >> > > > > index 14cb51368f..0d9909a662 100644 > >> > > >> > > > > --- a/board/freescale/imx8mn_evk/spl.c > >> > > >> > > > > +++ b/board/freescale/imx8mn_evk/spl.c > >> > > >> > > > > @@ -83,6 +83,15 @@ int power_init_board(void) > >> > > >> > > > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE > >> > > >> > > > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ > >> > > >> > > > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); > >> > > >> > > > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK) > >> > > >> > > > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */ > >> > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); > >> > > >> > > > > + > >> > > >> > > > > + /* Disable the BUCK2 */ > >> > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48); > >> > > >> > > > > + > >> > > >> > > > > + /* Set NVCC_DRAM to 1.35v */ > >> > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E); > >> > > >> > > > > #else > >> > > >> > > > > >> > > >> > > > All this part is not done by the spl pmic driver? > >> > > >> > > > >> > > >> > > I saw that you added the PCA9450 driver. Do you know if this > >> > > >> > > initialization can be done by the driver when CONFIG_SPL_DM_REGULATOR > >> > > >> > > is enabled? If I see this correctly, it can't be done. Is that > >> > > >> > > correct? > >> > > >> > > >> > > >> > +&i2c1 { > >> > > >> > + u-boot,dm-spl; > >> > > >> > +}; > >> > > >> > + > >> > > >> > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { > >> > > >> > + u-boot,dm-spl; > >> > > >> > +}; > >> > > >> > + > >> > > >> > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { > >> > > >> > + u-boot,dm-spl; > >> > > >> > +}; > >> > > >> > + > >> > > >> > +&pinctrl_i2c1 { > >> > > >> > + u-boot,dm-spl; > >> > > >> > +}; > >> > > >> > + > >> > > >> > +&pinctrl_pmic { > >> > > >> > + u-boot,dm-spl; > >> > > >> > +}; > >> > > >> > + > >> > > >> > > >> > > >> > Maybe something like this should work. Now question is about should be > >> > > >> > done in pre-reloc or not > >> > > >> > >> > > >> It took me a little while to understand what was meant by this. In the > >> > > >> meantime I could > >> > > >> change the PMIC/Regulator initialization to DT/DM and can make the setting so. > >> > > >> What is not clear to me yet is at which point this should be done > >> > > >> (regulators_enable_boot_on()). Currently I do it in the board/spl > >> > > >> specific board_init_f(). > >> > > >> > >> > > >> Do any of you have any advice here? > >> > > > > >> > > > > >> > > > After having a discussion with you, i found that maybe i have some problem and some of the setting should be done before ddr inizialization. I will take a look on it on afternoon. I know marek was working on some way to probe driver during binding and we need even to be sure that this can happen before memory training. > >> > > > > >> > > > >> > > Currently I added it in board_init_f() right before spl_dram_init() > >> > > [1] and it works. I also tried to put it in power_init_board() [2] but > >> > > this does not work. > >> > > > >> > > [1] https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L162 > >> > > [2] https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8mn_evk/spl.c#L62 > >> > > >> > Does it work if you mark pre-reoloc, pmic, i2c, and pinctrl? > >> > >> I added on all nodes the u-boot,dm-pre-reloc but this does not help > >> when trying to do the init in power_init_board(). > > > > > > From code I navigate spl_early_init should bind the driver in pre-reloc > > What function should be called to probe the driver? Currently I use > regulators_enable_boot_on(). > > > Michael > >> > >> > >> > > >> > Michael > >> > > >> > > > >> > > -- > >> > > Heiko > >> > > > >> > > > Michael > >> > > >> > >> > > >> > >> > > >> Thanks > >> > > >> -- > >> > > >> Heiko > >> > > >> > >> > > >> > Michael > >> > > >> > > > >> > > >> > > -- > >> > > >> > > Heiko > >> > > >> > > >> > > >> > > >> > > >> > > >> > > >> > -- > >> > > >> > Michael Nazzareno Trimarchi > >> > > >> > Co-Founder & Chief Executive Officer > >> > > >> > M. +39 347 913 2170 > >> > > >> > michael@amarulasolutions.com > >> > > >> > __________________________________ > >> > > >> > > >> > > >> > Amarula Solutions BV > >> > > >> > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > >> > > >> > T. +31 (0)85 111 9172 > >> > > >> > info@amarulasolutions.com > >> > > >> > www.amarulasolutions.com > >> > > >> > > >> > > >> > -- > >> > Michael Nazzareno Trimarchi > >> > Co-Founder & Chief Executive Officer > >> > M. +39 347 913 2170 > >> > michael@amarulasolutions.com > >> > __________________________________ > >> > > >> > Amarula Solutions BV > >> > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > >> > T. +31 (0)85 111 9172 > >> > info@amarulasolutions.com > >> > www.amarulasolutions.com -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 michael@amarulasolutions.com __________________________________ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 info@amarulasolutions.com www.amarulasolutions.com ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2022-08-22 11:43 UTC | newest] Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-06-13 21:10 [PATCH v4] imx: add i.MX8MN DDR3L evk board support Heiko Thiery 2022-06-14 1:47 ` Peng Fan (OSS) 2022-06-14 6:55 ` Michael Nazzareno Trimarchi 2022-06-14 11:50 ` Heiko Thiery 2022-06-15 6:23 ` Heiko Thiery 2022-06-15 6:43 ` Michael Nazzareno Trimarchi 2022-06-18 21:56 ` Heiko Thiery 2022-06-19 5:58 ` Michael Nazzareno Trimarchi 2022-06-19 6:11 ` Heiko Thiery 2022-06-19 14:40 ` Michael Nazzareno Trimarchi 2022-06-19 14:47 ` Heiko Thiery 2022-06-19 14:50 ` Heiko Thiery 2022-06-19 14:50 ` Michael Nazzareno Trimarchi 2022-06-19 14:53 ` Heiko Thiery 2022-08-22 11:42 ` Michael Nazzareno Trimarchi
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