[PATCH 0/2] STM32VLDISCOVERY Machine Model

[PATCH 0/2] STM32VLDISCOVERY Machine Model

[Alexandre Iooss]

This patch series adds the STM32VLDISCOVERY Machine to QEMU

Information on the board is available at:
https://www.st.com/en/evaluation-tools/stm32vldiscovery.html

Alexandre Iooss (2):
  stm32f100: Add the stm32f100 SoC
  stm32vldiscovery: Add the STM32VLDISCOVERY Machine

 MAINTAINERS                             |  12 ++
 default-configs/devices/arm-softmmu.mak |   1 +
 hw/arm/Kconfig                          |  10 ++
 hw/arm/meson.build                      |   2 +
 hw/arm/stm32f100_soc.c                  | 182 ++++++++++++++++++++++++
 hw/arm/stm32vldiscovery.c               |  66 +++++++++
 include/hw/arm/stm32f100_soc.h          |  58 ++++++++
 7 files changed, 331 insertions(+)
 create mode 100644 hw/arm/stm32f100_soc.c
 create mode 100644 hw/arm/stm32vldiscovery.c
 create mode 100644 include/hw/arm/stm32f100_soc.h

-- 
2.25.1

[PATCH 1/2] stm32f100: Add the stm32f100 SoC

[Alexandre Iooss]

This SoC is similar to stm32f205 SoC.
This will be used by the STM32VLDISCOVERY to create a machine.

Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
---
 MAINTAINERS                    |   6 ++
 hw/arm/Kconfig                 |   6 ++
 hw/arm/meson.build             |   1 +
 hw/arm/stm32f100_soc.c         | 182 +++++++++++++++++++++++++++++++++
 include/hw/arm/stm32f100_soc.h |  58 +++++++++++
 5 files changed, 253 insertions(+)
 create mode 100644 hw/arm/stm32f100_soc.c
 create mode 100644 include/hw/arm/stm32f100_soc.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 7d9cd29042..62dfa31800 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -946,6 +946,12 @@ L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/virt-acpi-build.c
 
+STM32F100
+M: Alexandre Iooss <erdnaxe@crans.org>
+L: qemu-arm@nongnu.org
+S: Maintained
+F: hw/arm/stm32f100_soc.c
+
 STM32F205
 M: Alistair Francis <alistair@alistair23.me>
 M: Peter Maydell <peter.maydell@linaro.org>
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 67723d9ea6..0bc3ee3e91 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -326,6 +326,12 @@ config RASPI
     select SDHCI
     select USB_DWC2
 
+config STM32F100_SOC
+    bool
+    select ARM_V7M
+    select STM32F2XX_USART
+    select STM32F2XX_SPI
+
 config STM32F205_SOC
     bool
     select ARM_V7M
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index be39117b9b..0e637e6a9e 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -39,6 +39,7 @@ arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))
 arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
 arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
 arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c'))
+arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
 arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c'))
 arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c'))
 arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c'))
diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
new file mode 100644
index 0000000000..4655aaf05a
--- /dev/null
+++ b/hw/arm/stm32f100_soc.c
@@ -0,0 +1,182 @@
+/*
+ * STM32F100 SoC
+ *
+ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/module.h"
+#include "hw/arm/boot.h"
+#include "exec/address-spaces.h"
+#include "hw/arm/stm32f100_soc.h"
+#include "hw/qdev-properties.h"
+#include "hw/misc/unimp.h"
+#include "sysemu/sysemu.h"
+
+/* stm32f100_soc implementation is derived from stm32f205_soc */
+
+static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400,
+    0x40004800 };
+static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 };
+
+static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39};
+static const int spi_irq[STM_NUM_SPIS] = {35, 36};
+
+static void stm32f100_soc_initfn(Object *obj)
+{
+    STM32F100State *s = STM32F100_SOC(obj);
+    int i;
+
+    object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
+
+    for (i = 0; i < STM_NUM_USARTS; i++) {
+        object_initialize_child(obj, "usart[*]", &s->usart[i],
+                                TYPE_STM32F2XX_USART);
+    }
+
+    for (i = 0; i < STM_NUM_SPIS; i++) {
+        object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
+    }
+}
+
+static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
+{
+    STM32F100State *s = STM32F100_SOC(dev_soc);
+    DeviceState *dev, *armv7m;
+    SysBusDevice *busdev;
+    int i;
+
+    MemoryRegion *system_memory = get_system_memory();
+    MemoryRegion *sram = g_new(MemoryRegion, 1);
+    MemoryRegion *flash = g_new(MemoryRegion, 1);
+    MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
+
+    /*
+     * Init flash region
+     * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0
+     */
+    memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash",
+                           FLASH_SIZE, &error_fatal);
+    memory_region_init_alias(flash_alias, OBJECT(dev_soc),
+                             "STM32F100.flash.alias", flash, 0, FLASH_SIZE);
+    memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
+    memory_region_add_subregion(system_memory, 0, flash_alias);
+
+    /* Init SRAM region */
+    memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE,
+                           &error_fatal);
+    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
+
+    /* Init ARMv7m */
+    armv7m = DEVICE(&s->armv7m);
+    qdev_prop_set_uint32(armv7m, "num-irq", 96);
+    qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
+    qdev_prop_set_bit(armv7m, "enable-bitband", true);
+    object_property_set_link(OBJECT(&s->armv7m), "memory",
+                             OBJECT(get_system_memory()), &error_abort);
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
+        return;
+    }
+
+    /* Attach UART (uses USART registers) and USART controllers */
+    for (i = 0; i < STM_NUM_USARTS; i++) {
+        dev = DEVICE(&(s->usart[i]));
+        qdev_prop_set_chr(dev, "chardev", serial_hd(i));
+        if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, usart_addr[i]);
+        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
+    }
+
+    /* SPI 1 and 2 */
+    for (i = 0; i < STM_NUM_SPIS; i++) {
+        dev = DEVICE(&(s->spi[i]));
+        if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, spi_addr[i]);
+        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
+    }
+
+    create_unimplemented_device("timer[2]",  0x40000000, 0x400);
+    create_unimplemented_device("timer[3]",  0x40000400, 0x400);
+    create_unimplemented_device("timer[4]",  0x40000800, 0x400);
+    create_unimplemented_device("timer[6]",  0x40001000, 0x400);
+    create_unimplemented_device("timer[7]",  0x40001400, 0x400);
+    create_unimplemented_device("RTC",       0x40002800, 0x400);
+    create_unimplemented_device("WWDG",      0x40002C00, 0x400);
+    create_unimplemented_device("IWDG",      0x40003000, 0x400);
+    create_unimplemented_device("I2C1",      0x40005400, 0x400);
+    create_unimplemented_device("I2C2",      0x40005800, 0x400);
+    create_unimplemented_device("BKP",       0x40006C00, 0x400);
+    create_unimplemented_device("PWR",       0x40007000, 0x400);
+    create_unimplemented_device("DAC",       0x40007400, 0x400);
+    create_unimplemented_device("CEC",       0x40007800, 0x400);
+    create_unimplemented_device("AFIO",      0x40010000, 0x400);
+    create_unimplemented_device("EXTI",      0x40010400, 0x400);
+    create_unimplemented_device("GPIOA",     0x40010800, 0x400);
+    create_unimplemented_device("GPIOB",     0x40010C00, 0x400);
+    create_unimplemented_device("GPIOC",     0x40011000, 0x400);
+    create_unimplemented_device("GPIOD",     0x40011400, 0x400);
+    create_unimplemented_device("GPIOE",     0x40011800, 0x400);
+    create_unimplemented_device("ADC1",      0x40012400, 0x400);
+    create_unimplemented_device("timer[1]",  0x40012C00, 0x400);
+    create_unimplemented_device("timer[15]", 0x40014000, 0x400);
+    create_unimplemented_device("timer[16]", 0x40014400, 0x400);
+    create_unimplemented_device("timer[17]", 0x40014800, 0x400);
+    create_unimplemented_device("DMA",       0x40020000, 0x400);
+    create_unimplemented_device("RCC",       0x40021000, 0x400);
+    create_unimplemented_device("Flash Int", 0x40022000, 0x400);
+    create_unimplemented_device("CRC",       0x40023000, 0x400);
+}
+
+static Property stm32f100_soc_properties[] = {
+    DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void stm32f100_soc_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = stm32f100_soc_realize;
+    device_class_set_props(dc, stm32f100_soc_properties);
+}
+
+static const TypeInfo stm32f100_soc_info = {
+    .name          = TYPE_STM32F100_SOC,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(STM32F100State),
+    .instance_init = stm32f100_soc_initfn,
+    .class_init    = stm32f100_soc_class_init,
+};
+
+static void stm32f100_soc_types(void)
+{
+    type_register_static(&stm32f100_soc_info);
+}
+
+type_init(stm32f100_soc_types)
diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h
new file mode 100644
index 0000000000..c55f7774fa
--- /dev/null
+++ b/include/hw/arm/stm32f100_soc.h
@@ -0,0 +1,58 @@
+/*
+ * STM32F100 SoC
+ *
+ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_ARM_STM32F100_SOC_H
+#define HW_ARM_STM32F100_SOC_H
+
+#include "hw/char/stm32f2xx_usart.h"
+#include "hw/ssi/stm32f2xx_spi.h"
+#include "hw/arm/armv7m.h"
+#include "qom/object.h"
+
+#define TYPE_STM32F100_SOC "stm32f100-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)
+
+#define STM_NUM_USARTS 3
+#define STM_NUM_SPIS 2
+
+#define FLASH_BASE_ADDRESS 0x08000000
+#define FLASH_SIZE (128 * 1024)
+#define SRAM_BASE_ADDRESS 0x20000000
+#define SRAM_SIZE (8 * 1024)
+
+struct STM32F100State {
+    /*< private >*/
+    SysBusDevice parent_obj;
+
+    /*< public >*/
+    char *cpu_type;
+
+    ARMv7MState armv7m;
+
+    STM32F2XXUsartState usart[STM_NUM_USARTS];
+    STM32F2XXSPIState spi[STM_NUM_SPIS];
+};
+
+#endif
+
-- 
2.25.1

Re: [PATCH 1/2] stm32f100: Add the stm32f100 SoC

[Peter Maydell]

On Tue, 8 Jun 2021 at 17:10, Alexandre Iooss <erdnaxe@crans.org> wrote:
>
> This SoC is similar to stm32f205 SoC.
> This will be used by the STM32VLDISCOVERY to create a machine.
>
> Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
> ---
>  MAINTAINERS                    |   6 ++
>  hw/arm/Kconfig                 |   6 ++
>  hw/arm/meson.build             |   1 +
>  hw/arm/stm32f100_soc.c         | 182 +++++++++++++++++++++++++++++++++
>  include/hw/arm/stm32f100_soc.h |  58 +++++++++++
>  5 files changed, 253 insertions(+)
>  create mode 100644 hw/arm/stm32f100_soc.c
>  create mode 100644 include/hw/arm/stm32f100_soc.h

> +    /* Init ARMv7m */
> +    armv7m = DEVICE(&s->armv7m);
> +    qdev_prop_set_uint32(armv7m, "num-irq", 96);

Is this definitely right? The STM32F00 datasheet I found
thinks it only has 61 external interrupts.

Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linar.org>

thanks
-- PMM

Re: [PATCH 1/2] stm32f100: Add the stm32f100 SoC

[Alexandre IOOSS]

[-- Attachment #1.1: Type: text/plain, Size: 460 bytes --]

On 6/14/21 6:04 PM, Peter Maydell wrote:
> Is this definitely right? The STM32F00 datasheet I found
> thinks it only has 61 external interrupts.

Yes you are right, I don't really known what I have done here. I will 
fix this in next patchset version.

To double-check, it is described page 131 of 
https://www.st.com/resource/en/reference_manual/cd00246267-stm32f100xx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf

Thanks,
-- Alexandre


[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 840 bytes --]

Re: [PATCH 1/2] stm32f100: Add the stm32f100 SoC

[Alistair Francis]

On Wed, Jun 9, 2021 at 2:12 AM Alexandre Iooss <erdnaxe@crans.org> wrote:
>
> This SoC is similar to stm32f205 SoC.
> This will be used by the STM32VLDISCOVERY to create a machine.
>
> Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
> ---
>  MAINTAINERS                    |   6 ++
>  hw/arm/Kconfig                 |   6 ++
>  hw/arm/meson.build             |   1 +
>  hw/arm/stm32f100_soc.c         | 182 +++++++++++++++++++++++++++++++++
>  include/hw/arm/stm32f100_soc.h |  58 +++++++++++
>  5 files changed, 253 insertions(+)
>  create mode 100644 hw/arm/stm32f100_soc.c
>  create mode 100644 include/hw/arm/stm32f100_soc.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7d9cd29042..62dfa31800 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -946,6 +946,12 @@ L: qemu-arm@nongnu.org
>  S: Maintained
>  F: hw/arm/virt-acpi-build.c
>
> +STM32F100
> +M: Alexandre Iooss <erdnaxe@crans.org>
> +L: qemu-arm@nongnu.org
> +S: Maintained
> +F: hw/arm/stm32f100_soc.c
> +
>  STM32F205
>  M: Alistair Francis <alistair@alistair23.me>
>  M: Peter Maydell <peter.maydell@linaro.org>
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 67723d9ea6..0bc3ee3e91 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -326,6 +326,12 @@ config RASPI
>      select SDHCI
>      select USB_DWC2
>
> +config STM32F100_SOC
> +    bool
> +    select ARM_V7M
> +    select STM32F2XX_USART
> +    select STM32F2XX_SPI
> +
>  config STM32F205_SOC
>      bool
>      select ARM_V7M
> diff --git a/hw/arm/meson.build b/hw/arm/meson.build
> index be39117b9b..0e637e6a9e 100644
> --- a/hw/arm/meson.build
> +++ b/hw/arm/meson.build
> @@ -39,6 +39,7 @@ arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))
>  arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
>  arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
>  arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c'))
> +arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
>  arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c'))
>  arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c'))
>  arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c'))
> diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
> new file mode 100644
> index 0000000000..4655aaf05a
> --- /dev/null
> +++ b/hw/arm/stm32f100_soc.c
> @@ -0,0 +1,182 @@
> +/*
> + * STM32F100 SoC
> + *
> + * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
> + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "qemu/module.h"
> +#include "hw/arm/boot.h"
> +#include "exec/address-spaces.h"
> +#include "hw/arm/stm32f100_soc.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/misc/unimp.h"
> +#include "sysemu/sysemu.h"
> +
> +/* stm32f100_soc implementation is derived from stm32f205_soc */
> +
> +static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400,
> +    0x40004800 };
> +static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 };
> +
> +static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39};
> +static const int spi_irq[STM_NUM_SPIS] = {35, 36};
> +
> +static void stm32f100_soc_initfn(Object *obj)
> +{
> +    STM32F100State *s = STM32F100_SOC(obj);
> +    int i;
> +
> +    object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
> +
> +    for (i = 0; i < STM_NUM_USARTS; i++) {
> +        object_initialize_child(obj, "usart[*]", &s->usart[i],
> +                                TYPE_STM32F2XX_USART);
> +    }
> +
> +    for (i = 0; i < STM_NUM_SPIS; i++) {
> +        object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
> +    }
> +}
> +
> +static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
> +{
> +    STM32F100State *s = STM32F100_SOC(dev_soc);
> +    DeviceState *dev, *armv7m;
> +    SysBusDevice *busdev;
> +    int i;
> +
> +    MemoryRegion *system_memory = get_system_memory();
> +    MemoryRegion *sram = g_new(MemoryRegion, 1);
> +    MemoryRegion *flash = g_new(MemoryRegion, 1);
> +    MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
> +
> +    /*
> +     * Init flash region
> +     * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0
> +     */
> +    memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash",
> +                           FLASH_SIZE, &error_fatal);
> +    memory_region_init_alias(flash_alias, OBJECT(dev_soc),
> +                             "STM32F100.flash.alias", flash, 0, FLASH_SIZE);
> +    memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
> +    memory_region_add_subregion(system_memory, 0, flash_alias);
> +
> +    /* Init SRAM region */
> +    memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE,
> +                           &error_fatal);
> +    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
> +
> +    /* Init ARMv7m */
> +    armv7m = DEVICE(&s->armv7m);
> +    qdev_prop_set_uint32(armv7m, "num-irq", 96);
> +    qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
> +    qdev_prop_set_bit(armv7m, "enable-bitband", true);
> +    object_property_set_link(OBJECT(&s->armv7m), "memory",
> +                             OBJECT(get_system_memory()), &error_abort);
> +    if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
> +        return;
> +    }
> +
> +    /* Attach UART (uses USART registers) and USART controllers */
> +    for (i = 0; i < STM_NUM_USARTS; i++) {
> +        dev = DEVICE(&(s->usart[i]));
> +        qdev_prop_set_chr(dev, "chardev", serial_hd(i));
> +        if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {
> +            return;
> +        }
> +        busdev = SYS_BUS_DEVICE(dev);
> +        sysbus_mmio_map(busdev, 0, usart_addr[i]);
> +        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
> +    }
> +
> +    /* SPI 1 and 2 */
> +    for (i = 0; i < STM_NUM_SPIS; i++) {
> +        dev = DEVICE(&(s->spi[i]));
> +        if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
> +            return;
> +        }
> +        busdev = SYS_BUS_DEVICE(dev);
> +        sysbus_mmio_map(busdev, 0, spi_addr[i]);
> +        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
> +    }
> +
> +    create_unimplemented_device("timer[2]",  0x40000000, 0x400);
> +    create_unimplemented_device("timer[3]",  0x40000400, 0x400);
> +    create_unimplemented_device("timer[4]",  0x40000800, 0x400);
> +    create_unimplemented_device("timer[6]",  0x40001000, 0x400);
> +    create_unimplemented_device("timer[7]",  0x40001400, 0x400);
> +    create_unimplemented_device("RTC",       0x40002800, 0x400);
> +    create_unimplemented_device("WWDG",      0x40002C00, 0x400);
> +    create_unimplemented_device("IWDG",      0x40003000, 0x400);
> +    create_unimplemented_device("I2C1",      0x40005400, 0x400);
> +    create_unimplemented_device("I2C2",      0x40005800, 0x400);
> +    create_unimplemented_device("BKP",       0x40006C00, 0x400);
> +    create_unimplemented_device("PWR",       0x40007000, 0x400);
> +    create_unimplemented_device("DAC",       0x40007400, 0x400);
> +    create_unimplemented_device("CEC",       0x40007800, 0x400);
> +    create_unimplemented_device("AFIO",      0x40010000, 0x400);
> +    create_unimplemented_device("EXTI",      0x40010400, 0x400);
> +    create_unimplemented_device("GPIOA",     0x40010800, 0x400);
> +    create_unimplemented_device("GPIOB",     0x40010C00, 0x400);
> +    create_unimplemented_device("GPIOC",     0x40011000, 0x400);
> +    create_unimplemented_device("GPIOD",     0x40011400, 0x400);
> +    create_unimplemented_device("GPIOE",     0x40011800, 0x400);
> +    create_unimplemented_device("ADC1",      0x40012400, 0x400);
> +    create_unimplemented_device("timer[1]",  0x40012C00, 0x400);
> +    create_unimplemented_device("timer[15]", 0x40014000, 0x400);
> +    create_unimplemented_device("timer[16]", 0x40014400, 0x400);
> +    create_unimplemented_device("timer[17]", 0x40014800, 0x400);
> +    create_unimplemented_device("DMA",       0x40020000, 0x400);
> +    create_unimplemented_device("RCC",       0x40021000, 0x400);
> +    create_unimplemented_device("Flash Int", 0x40022000, 0x400);
> +    create_unimplemented_device("CRC",       0x40023000, 0x400);

Aren't you missing some timers, like timer[5] 0x4000_0C00?

Alistair

> +}
> +
> +static Property stm32f100_soc_properties[] = {
> +    DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type),
> +    DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void stm32f100_soc_class_init(ObjectClass *klass, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(klass);
> +
> +    dc->realize = stm32f100_soc_realize;
> +    device_class_set_props(dc, stm32f100_soc_properties);
> +}
> +
> +static const TypeInfo stm32f100_soc_info = {
> +    .name          = TYPE_STM32F100_SOC,
> +    .parent        = TYPE_SYS_BUS_DEVICE,
> +    .instance_size = sizeof(STM32F100State),
> +    .instance_init = stm32f100_soc_initfn,
> +    .class_init    = stm32f100_soc_class_init,
> +};
> +
> +static void stm32f100_soc_types(void)
> +{
> +    type_register_static(&stm32f100_soc_info);
> +}
> +
> +type_init(stm32f100_soc_types)
> diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h
> new file mode 100644
> index 0000000000..c55f7774fa
> --- /dev/null
> +++ b/include/hw/arm/stm32f100_soc.h
> @@ -0,0 +1,58 @@
> +/*
> + * STM32F100 SoC
> + *
> + * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_ARM_STM32F100_SOC_H
> +#define HW_ARM_STM32F100_SOC_H
> +
> +#include "hw/char/stm32f2xx_usart.h"
> +#include "hw/ssi/stm32f2xx_spi.h"
> +#include "hw/arm/armv7m.h"
> +#include "qom/object.h"
> +
> +#define TYPE_STM32F100_SOC "stm32f100-soc"
> +OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)
> +
> +#define STM_NUM_USARTS 3
> +#define STM_NUM_SPIS 2
> +
> +#define FLASH_BASE_ADDRESS 0x08000000
> +#define FLASH_SIZE (128 * 1024)
> +#define SRAM_BASE_ADDRESS 0x20000000
> +#define SRAM_SIZE (8 * 1024)
> +
> +struct STM32F100State {
> +    /*< private >*/
> +    SysBusDevice parent_obj;
> +
> +    /*< public >*/
> +    char *cpu_type;
> +
> +    ARMv7MState armv7m;
> +
> +    STM32F2XXUsartState usart[STM_NUM_USARTS];
> +    STM32F2XXSPIState spi[STM_NUM_SPIS];
> +};
> +
> +#endif
> +
> --
> 2.25.1
>
>

Re: [PATCH 1/2] stm32f100: Add the stm32f100 SoC

[Alexandre IOOSS]

[-- Attachment #1.1: Type: text/plain, Size: 576 bytes --]

On 6/15/21 9:41 AM, Alistair Francis wrote:
> Aren't you missing some timers, like timer[5] 0x4000_0C00?
> 
> Alistair

I double-checked using the reference manual and the datasheet and there 
is not timer[5]:
- page 36 of 
https://www.st.com/resource/en/reference_manual/cd00246267-stm32f100xx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf
- page 30 of https://www.st.com/resource/en/datasheet/stm32f100cb.pdf

I believe ST is skipping numbers to guarantee that timer[n] will have a 
consistent address on different STM32 SoC.

Thanks,
-- Alexandre


[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 840 bytes --]

Re: [PATCH 1/2] stm32f100: Add the stm32f100 SoC

[Alistair Francis]

On Tue, Jun 15, 2021 at 5:50 PM Alexandre IOOSS <erdnaxe@crans.org> wrote:
>
> On 6/15/21 9:41 AM, Alistair Francis wrote:
> > Aren't you missing some timers, like timer[5] 0x4000_0C00?
> >
> > Alistair
>
> I double-checked using the reference manual and the datasheet and there
> is not timer[5]:
> - page 36 of
> https://www.st.com/resource/en/reference_manual/cd00246267-stm32f100xx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf

Strange, https://www.st.com/resource/en/datasheet/stm32f100rc.pdf
describes Timer 5 and page 282 of the document you linked talks about
timer 5 as well.

Alistair

> - page 30 of https://www.st.com/resource/en/datasheet/stm32f100cb.pdf
>
> I believe ST is skipping numbers to guarantee that timer[n] will have a
> consistent address on different STM32 SoC.
>
> Thanks,
> -- Alexandre
>

Re: [PATCH 1/2] stm32f100: Add the stm32f100 SoC

[Alexandre IOOSS]

[-- Attachment #1.1: Type: text/plain, Size: 1867 bytes --]



On 6/15/21 10:04 AM, Alistair Francis wrote:
> On Tue, Jun 15, 2021 at 5:50 PM Alexandre IOOSS <erdnaxe@crans.org> wrote:
>>
>> On 6/15/21 9:41 AM, Alistair Francis wrote:
>>> Aren't you missing some timers, like timer[5] 0x4000_0C00?
>>>
>>> Alistair
>>
>> I double-checked using the reference manual and the datasheet and there
>> is not timer[5]:
>> - page 36 of
>> https://www.st.com/resource/en/reference_manual/cd00246267-stm32f100xx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf
> 
> Strange, https://www.st.com/resource/en/datasheet/stm32f100rc.pdf
> describes Timer 5 and page 282 of the document you linked talks about
> timer 5 as well.
> 
> Alistair
> 
>> - page 30 of https://www.st.com/resource/en/datasheet/stm32f100cb.pdf
>>
>> I believe ST is skipping numbers to guarantee that timer[n] will have a
>> consistent address on different STM32 SoC.
>>
>> Thanks,
>> -- Alexandre
>>

 From what I understand from other STM32F100xx reference manuals:
I am implementing all peripherals in the STM32F100xx reference manual 
which match with what is actually in the STM32F100RB SoC (used in the 
STM32VLDISCOVERY).

STM32F100RC SoC implements more peripherals (more USART, more 
timers...). Adding these peripherals in stm32f100.c means that the 
STM32VLDISCOVERY machine would have peripherals that does not exist on 
the real target. Do we want to avoid that?

Should we keep stm32f100.c with the common subset of peripherals and 
extend it when a machine is using a variant with more peripherals?

I believe this issue is also linked with what Philippe proposed: we 
could abstract STM32 SoC in the same way ATMEGA is abstracted. This 
would make a lot of sense since the STM32 family has a lot of 
similarities and we don't want to bloat QEMU with N times the same code.

Thanks,
-- Alexandre


[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 840 bytes --]

Re: [PATCH 1/2] stm32f100: Add the stm32f100 SoC

[Alistair Francis]

On Tue, Jun 15, 2021 at 7:15 PM Alexandre IOOSS <erdnaxe@crans.org> wrote:
>
>
>
> On 6/15/21 10:04 AM, Alistair Francis wrote:
> > On Tue, Jun 15, 2021 at 5:50 PM Alexandre IOOSS <erdnaxe@crans.org> wrote:
> >>
> >> On 6/15/21 9:41 AM, Alistair Francis wrote:
> >>> Aren't you missing some timers, like timer[5] 0x4000_0C00?
> >>>
> >>> Alistair
> >>
> >> I double-checked using the reference manual and the datasheet and there
> >> is not timer[5]:
> >> - page 36 of
> >> https://www.st.com/resource/en/reference_manual/cd00246267-stm32f100xx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf
> >
> > Strange, https://www.st.com/resource/en/datasheet/stm32f100rc.pdf
> > describes Timer 5 and page 282 of the document you linked talks about
> > timer 5 as well.
> >
> > Alistair
> >
> >> - page 30 of https://www.st.com/resource/en/datasheet/stm32f100cb.pdf
> >>
> >> I believe ST is skipping numbers to guarantee that timer[n] will have a
> >> consistent address on different STM32 SoC.
> >>
> >> Thanks,
> >> -- Alexandre
> >>
>
>  From what I understand from other STM32F100xx reference manuals:
> I am implementing all peripherals in the STM32F100xx reference manual
> which match with what is actually in the STM32F100RB SoC (used in the
> STM32VLDISCOVERY).

Ah, my mistake. The STM numbering always confuses me.

>
> STM32F100RC SoC implements more peripherals (more USART, more
> timers...). Adding these peripherals in stm32f100.c means that the
> STM32VLDISCOVERY machine would have peripherals that does not exist on
> the real target. Do we want to avoid that?

Yep, this is fine as is.

>
> Should we keep stm32f100.c with the common subset of peripherals and
> extend it when a machine is using a variant with more peripherals?
>
> I believe this issue is also linked with what Philippe proposed: we
> could abstract STM32 SoC in the same way ATMEGA is abstracted. This
> would make a lot of sense since the STM32 family has a lot of
> similarities and we don't want to bloat QEMU with N times the same code.

I agree. That's the best way forward and I think it's a good goal. We
don't have to block this series on that though. If you would like to
work on a shared abstraction that would be great :)

Once the IRQs are fixed:

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
> Thanks,
> -- Alexandre
>

[PATCH 2/2] stm32vldiscovery: Add the STM32VLDISCOVERY Machine

[Alexandre Iooss]

This is a Cortex-M3 based machine. Information can be found at:
https://www.st.com/en/evaluation-tools/stm32vldiscovery.html

Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
---
 MAINTAINERS                             |  6 +++
 default-configs/devices/arm-softmmu.mak |  1 +
 hw/arm/Kconfig                          |  4 ++
 hw/arm/meson.build                      |  1 +
 hw/arm/stm32vldiscovery.c               | 66 +++++++++++++++++++++++++
 5 files changed, 78 insertions(+)
 create mode 100644 hw/arm/stm32vldiscovery.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 62dfa31800..0aa8016936 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -891,6 +891,12 @@ F: hw/*/stellaris*
 F: include/hw/input/gamepad.h
 F: docs/system/arm/stellaris.rst
 
+STM32VLDISCOVERY
+M: Alexandre Iooss <erdnaxe@crans.org>
+L: qemu-arm@nongnu.org
+S: Maintained
+F: hw/arm/stm32vldiscovery.c
+
 Versatile Express
 M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak
index 0500156a0c..cdc0e97f9d 100644
--- a/default-configs/devices/arm-softmmu.mak
+++ b/default-configs/devices/arm-softmmu.mak
@@ -18,6 +18,7 @@ CONFIG_CHEETAH=y
 CONFIG_SX1=y
 CONFIG_NSERIES=y
 CONFIG_STELLARIS=y
+CONFIG_STM32VLDISCOVERY=y
 CONFIG_REALVIEW=y
 CONFIG_VERSATILE=y
 CONFIG_VEXPRESS=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 0bc3ee3e91..dc4e47b721 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -239,6 +239,10 @@ config STELLARIS
     select STELLARIS_ENET # ethernet
     select UNIMP
 
+config STM32VLDISCOVERY
+    bool
+    select STM32F100_SOC
+
 config STRONGARM
     bool
     select PXA2XX
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 0e637e6a9e..721a8eb8be 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -24,6 +24,7 @@ arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c'))
 arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
 arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
 arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
+arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c'))
 arm_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c'))
 arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c'))
 arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
new file mode 100644
index 0000000000..ab9297bc38
--- /dev/null
+++ b/hw/arm/stm32vldiscovery.c
@@ -0,0 +1,66 @@
+/*
+ * ST STM32VLDISCOVERY machine
+ *
+ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/qdev-properties.h"
+#include "qemu/error-report.h"
+#include "hw/arm/stm32f100_soc.h"
+#include "hw/arm/boot.h"
+
+/* stm32vldiscovery implementation is derived from netduinoplus2 */
+
+/* Main SYSCLK frequency in Hz (24MHz) */
+#define SYSCLK_FRQ 24000000ULL
+
+static void stm32vldiscovery_init(MachineState *machine)
+{
+    DeviceState *dev;
+
+    /*
+     * TODO: ideally we would model the SoC RCC and let it handle
+     * system_clock_scale, including its ability to define different
+     * possible SYSCLK sources.
+     */
+    system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
+
+    dev = qdev_new(TYPE_STM32F100_SOC);
+    qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
+    armv7m_load_kernel(ARM_CPU(first_cpu),
+                       machine->kernel_filename,
+                       FLASH_SIZE);
+}
+
+static void stm32vldiscovery_machine_init(MachineClass *mc)
+{
+    mc->desc = "ST STM32VLDISCOVERY (Cortex-M4)";
+    mc->init = stm32vldiscovery_init;
+}
+
+DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init)
+
-- 
2.25.1

Re: [PATCH 2/2] stm32vldiscovery: Add the STM32VLDISCOVERY Machine

[Peter Maydell]

On Tue, 8 Jun 2021 at 17:10, Alexandre Iooss <erdnaxe@crans.org> wrote:
>
> This is a Cortex-M3 based machine. Information can be found at:
> https://www.st.com/en/evaluation-tools/stm32vldiscovery.html
>
> Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>

The commit message says this is Cortex-M3 based, but the
code gives it a Cortex-M4. Which is correct?

> ---
>  MAINTAINERS                             |  6 +++
>  default-configs/devices/arm-softmmu.mak |  1 +
>  hw/arm/Kconfig                          |  4 ++
>  hw/arm/meson.build                      |  1 +
>  hw/arm/stm32vldiscovery.c               | 66 +++++++++++++++++++++++++
>  5 files changed, 78 insertions(+)
>  create mode 100644 hw/arm/stm32vldiscovery.c

Could you add some documentation for the new board, please?
This lives in docs/system/arm. Commit c9f8511ea8d2b807 gives
an example of adding docs for a board.

thanks
-- PMM

Re: [PATCH 2/2] stm32vldiscovery: Add the STM32VLDISCOVERY Machine

[Alexandre IOOSS]

[-- Attachment #1.1: Type: text/plain, Size: 1676 bytes --]

On 6/14/21 5:52 PM, Peter Maydell wrote:
> On Tue, 8 Jun 2021 at 17:10, Alexandre Iooss <erdnaxe@crans.org> wrote:
>>
>> This is a Cortex-M3 based machine. Information can be found at:
>> https://www.st.com/en/evaluation-tools/stm32vldiscovery.html
>>
>> Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
> 
> The commit message says this is Cortex-M3 based, but the
> code gives it a Cortex-M4. Which is correct?

This is an typo. The board is Cortex-M3 so I will fix the machine code 
in next version of this patchset.

>> ---
>>   MAINTAINERS                             |  6 +++
>>   default-configs/devices/arm-softmmu.mak |  1 +
>>   hw/arm/Kconfig                          |  4 ++
>>   hw/arm/meson.build                      |  1 +
>>   hw/arm/stm32vldiscovery.c               | 66 +++++++++++++++++++++++++
>>   5 files changed, 78 insertions(+)
>>   create mode 100644 hw/arm/stm32vldiscovery.c
> 
> Could you add some documentation for the new board, please?
> This lives in docs/system/arm. Commit c9f8511ea8d2b807 gives
> an example of adding docs for a board.
> 
> thanks
> -- PMM
> 

Should I rather:
1. Add `docs/system/arm/stm32vldiscovery.rst` to document only this new 
machine?
2. Add `docs/system/arm/stm32discovery.rst` to document this new machine 
and future STM32 Discovery boards?
3. Add `docs/system/arm/stm32.rst` to document all STM32-based boards?

STM32 boards share a lot in common so I believe option 3 is more 
appropriate, what is your opinion?
If we go with option 3, I can also try to document the Netduino Plus 2 
(maybe in another commit, or another patchset later).

Thanks,
-- Alexandre


[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 840 bytes --]

Re: [PATCH 2/2] stm32vldiscovery: Add the STM32VLDISCOVERY Machine

[Alistair Francis]

On Tue, Jun 15, 2021 at 5:17 PM Alexandre IOOSS <erdnaxe@crans.org> wrote:
>
> On 6/14/21 5:52 PM, Peter Maydell wrote:
> > On Tue, 8 Jun 2021 at 17:10, Alexandre Iooss <erdnaxe@crans.org> wrote:
> >>
> >> This is a Cortex-M3 based machine. Information can be found at:
> >> https://www.st.com/en/evaluation-tools/stm32vldiscovery.html
> >>
> >> Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
> >
> > The commit message says this is Cortex-M3 based, but the
> > code gives it a Cortex-M4. Which is correct?
>
> This is an typo. The board is Cortex-M3 so I will fix the machine code
> in next version of this patchset.
>
> >> ---
> >>   MAINTAINERS                             |  6 +++
> >>   default-configs/devices/arm-softmmu.mak |  1 +
> >>   hw/arm/Kconfig                          |  4 ++
> >>   hw/arm/meson.build                      |  1 +
> >>   hw/arm/stm32vldiscovery.c               | 66 +++++++++++++++++++++++++
> >>   5 files changed, 78 insertions(+)
> >>   create mode 100644 hw/arm/stm32vldiscovery.c
> >
> > Could you add some documentation for the new board, please?
> > This lives in docs/system/arm. Commit c9f8511ea8d2b807 gives
> > an example of adding docs for a board.
> >
> > thanks
> > -- PMM
> >
>
> Should I rather:
> 1. Add `docs/system/arm/stm32vldiscovery.rst` to document only this new
> machine?
> 2. Add `docs/system/arm/stm32discovery.rst` to document this new machine
> and future STM32 Discovery boards?
> 3. Add `docs/system/arm/stm32.rst` to document all STM32-based boards?
>
> STM32 boards share a lot in common so I believe option 3 is more
> appropriate, what is your opinion?
> If we go with option 3, I can also try to document the Netduino Plus 2
> (maybe in another commit, or another patchset later).

Looking at the existing `nuvoton.rst` file I would say option 3 is the
best bet here.

Alistair

>
> Thanks,
> -- Alexandre
>

Re: [PATCH 2/2] stm32vldiscovery: Add the STM32VLDISCOVERY Machine

[Peter Maydell]

On Tue, 15 Jun 2021 at 08:16, Alexandre IOOSS <erdnaxe@crans.org> wrote:
>
> On 6/14/21 5:52 PM, Peter Maydell wrote:
> > Could you add some documentation for the new board, please?
> > This lives in docs/system/arm. Commit c9f8511ea8d2b807 gives
> > an example of adding docs for a board.

> Should I rather:
> 1. Add `docs/system/arm/stm32vldiscovery.rst` to document only this new
> machine?
> 2. Add `docs/system/arm/stm32discovery.rst` to document this new machine
> and future STM32 Discovery boards?
> 3. Add `docs/system/arm/stm32.rst` to document all STM32-based boards?
>
> STM32 boards share a lot in common so I believe option 3 is more
> appropriate, what is your opinion?
> If we go with option 3, I can also try to document the Netduino Plus 2
> (maybe in another commit, or another patchset later).

Yes, I think that a shared stm32.rst is probably the best thing.
If you want to document the netduino boards too that would be
great, but I don't insist on it.

thanks
-- PMM

Re: [PATCH 0/2] STM32VLDISCOVERY Machine Model

[Peter Maydell]

On Tue, 8 Jun 2021 at 17:10, Alexandre Iooss <erdnaxe@crans.org> wrote:
>
> This patch series adds the STM32VLDISCOVERY Machine to QEMU
>
> Information on the board is available at:
> https://www.st.com/en/evaluation-tools/stm32vldiscovery.html
>
> Alexandre Iooss (2):
>   stm32f100: Add the stm32f100 SoC
>   stm32vldiscovery: Add the STM32VLDISCOVERY Machine
>
>  MAINTAINERS                             |  12 ++
>  default-configs/devices/arm-softmmu.mak |   1 +
>  hw/arm/Kconfig                          |  10 ++
>  hw/arm/meson.build                      |   2 +
>  hw/arm/stm32f100_soc.c                  | 182 ++++++++++++++++++++++++
>  hw/arm/stm32vldiscovery.c               |  66 +++++++++
>  include/hw/arm/stm32f100_soc.h          |  58 ++++++++
>  7 files changed, 331 insertions(+)
>  create mode 100644 hw/arm/stm32f100_soc.c
>  create mode 100644 hw/arm/stm32vldiscovery.c
>  create mode 100644 include/hw/arm/stm32f100_soc.h

Looks generally OK to me, but cc'ing Alistair who wrote the
STM32F405 model in case he wants to have a look at it.

thanks
-- PMM

Re: [PATCH 0/2] STM32VLDISCOVERY Machine Model

[Philippe Mathieu-Daudé]

On 6/14/21 6:05 PM, Peter Maydell wrote:
> On Tue, 8 Jun 2021 at 17:10, Alexandre Iooss <erdnaxe@crans.org> wrote:
>>
>> This patch series adds the STM32VLDISCOVERY Machine to QEMU
>>
>> Information on the board is available at:
>> https://www.st.com/en/evaluation-tools/stm32vldiscovery.html
>>
>> Alexandre Iooss (2):
>>   stm32f100: Add the stm32f100 SoC
>>   stm32vldiscovery: Add the STM32VLDISCOVERY Machine
>>
>>  MAINTAINERS                             |  12 ++
>>  default-configs/devices/arm-softmmu.mak |   1 +
>>  hw/arm/Kconfig                          |  10 ++
>>  hw/arm/meson.build                      |   2 +
>>  hw/arm/stm32f100_soc.c                  | 182 ++++++++++++++++++++++++
>>  hw/arm/stm32vldiscovery.c               |  66 +++++++++
>>  include/hw/arm/stm32f100_soc.h          |  58 ++++++++
>>  7 files changed, 331 insertions(+)
>>  create mode 100644 hw/arm/stm32f100_soc.c
>>  create mode 100644 hw/arm/stm32vldiscovery.c
>>  create mode 100644 include/hw/arm/stm32f100_soc.h
> 
> Looks generally OK to me, but cc'ing Alistair who wrote the
> STM32F405 model in case he wants to have a look at it.

The SoC in the STM32Fxxx family seems very similar.

Maybe OK for this one but next machines should consider reuse
components. Alexandre, if you plan to add more SoC, you might
want to look at how the abstract TYPE_ATMEGA_MCU handles multiples
MCU of the same family.

Regards,

Phil.