* [U-Boot] [PATCH 01/10 V6] EXYNOS5: Create a common board file
2013-10-29 7:23 [U-Boot] [PATCH 00/10 V6] EXYNOS5420: Add SMDK5420 board support Rajeshwari S Shinde
@ 2013-10-29 7:23 ` Rajeshwari S Shinde
2013-11-08 8:13 ` Przemyslaw Marczak
2013-10-29 7:23 ` [U-Boot] [PATCH 02/10 V6] Exynos5420: Add base addresses for 5420 Rajeshwari S Shinde
` (9 subsequent siblings)
10 siblings, 1 reply; 37+ messages in thread
From: Rajeshwari S Shinde @ 2013-10-29 7:23 UTC (permalink / raw)
To: u-boot
Create a common board.c file for all functions which are common across
all EXYNOS5 platforms.
exynos_init function is provided for platform specific code.
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Added check for the compilation of MAX77686 pmic.
Changes in V5:
- Moved board_eth_init and board_mmc_init in case of
device tree support
Changes in V6:
- None.
arch/arm/include/asm/arch-exynos/board.h | 17 ++
board/samsung/common/Makefile | 4 +
board/samsung/common/board.c | 405 +++++++++++++++++++++++++++++++
board/samsung/smdk5250/exynos5-dt.c | 361 +--------------------------
board/samsung/smdk5250/smdk5250.c | 182 +-------------
include/configs/exynos5250-dt.h | 2 +
6 files changed, 435 insertions(+), 536 deletions(-)
create mode 100644 arch/arm/include/asm/arch-exynos/board.h
create mode 100644 board/samsung/common/board.c
diff --git a/arch/arm/include/asm/arch-exynos/board.h b/arch/arm/include/asm/arch-exynos/board.h
new file mode 100644
index 0000000..243fb12
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/board.h
@@ -0,0 +1,17 @@
+/*
+ * (C) Copyright 2013 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _EXYNOS_BOARD_H
+#define _EXYNOS_BOARD_H
+
+/*
+ * Exynos baord specific changes for
+ * board_init
+ */
+int exynos_init(void);
+
+#endif /* EXYNOS_BOARD_H */
diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile
index 9e48a7b..eab8ab2 100644
--- a/board/samsung/common/Makefile
+++ b/board/samsung/common/Makefile
@@ -11,6 +11,10 @@ LIB = $(obj)libsamsung.o
COBJS-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o
+ifeq ($(CONFIG_SPL_BUILD),)
+COBJS-$(CONFIG_BOARD_COMMON) += board.o
+endif
+
SRCS := $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
new file mode 100644
index 0000000..9ebfc42
--- /dev/null
+++ b/board/samsung/common/board.c
@@ -0,0 +1,405 @@
+/*
+ * (C) Copyright 2013 SAMSUNG Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cros_ec.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <spi.h>
+#include <tmu.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/board.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
+#include <power/pmic.h>
+#include <asm/arch/sromc.h>
+#include <power/max77686_pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct local_info {
+ struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */
+ int cros_ec_err; /* Error for cros_ec, 0 if ok */
+};
+
+static struct local_info local;
+
+#if defined CONFIG_EXYNOS_TMU
+/*
+ * Boot Time Thermal Analysis for SoC temperature threshold breach
+ */
+static void boot_temp_check(void)
+{
+ int temp;
+
+ switch (tmu_monitor(&temp)) {
+ case TMU_STATUS_NORMAL:
+ break;
+ /* Status TRIPPED ans WARNING means corresponding threshold breach */
+ case TMU_STATUS_TRIPPED:
+ puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
+ set_ps_hold_ctrl();
+ hang();
+ break;
+ case TMU_STATUS_WARNING:
+ puts("EXYNOS_TMU: WARNING! Temperature very high\n");
+ break;
+ /*
+ * TMU_STATUS_INIT means something is wrong with temperature sensing
+ * and TMU status was changed back from NORMAL to INIT.
+ */
+ case TMU_STATUS_INIT:
+ default:
+ debug("EXYNOS_TMU: Unknown TMU state\n");
+ }
+}
+#endif
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+#if defined CONFIG_EXYNOS_TMU
+ if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
+ debug("%s: Failed to init TMU\n", __func__);
+ return -1;
+ }
+ boot_temp_check();
+#endif
+
+#ifdef CONFIG_EXYNOS_SPI
+ spi_init();
+#endif
+ return exynos_init();
+}
+
+int dram_init(void)
+{
+ int i;
+ u32 addr;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+ }
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ int i;
+ u32 addr, size;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+
+ gd->bd->bi_dram[i].start = addr;
+ gd->bd->bi_dram[i].size = size;
+ }
+}
+
+static int board_uart_init(void)
+{
+ int err, uart_id, ret = 0;
+
+ for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
+ err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
+ if (err) {
+ debug("UART%d not configured\n",
+ (uart_id - PERIPH_ID_UART0));
+ ret |= err;
+ }
+ }
+ return ret;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ int err;
+ err = board_uart_init();
+ if (err) {
+ debug("UART init failed\n");
+ return err;
+ }
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+ board_i2c_init(gd->fdt_blob);
+#endif
+ return err;
+}
+#endif
+
+struct cros_ec_dev *board_get_cros_ec_dev(void)
+{
+ return local.cros_ec_dev;
+}
+
+static int board_init_cros_ec_devices(const void *blob)
+{
+ local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
+ if (local.cros_ec_err)
+ return -1; /* Will report in board_late_init() */
+
+ return 0;
+}
+
+#if defined(CONFIG_POWER)
+#ifdef CONFIG_POWER_MAX77686
+static int pmic_reg_update(struct pmic *p, int reg, uint regval)
+{
+ u32 val;
+ int ret = 0;
+
+ ret = pmic_reg_read(p, reg, &val);
+ if (ret) {
+ debug("%s: PMIC %d register read failed\n", __func__, reg);
+ return -1;
+ }
+ val |= regval;
+ ret = pmic_reg_write(p, reg, val);
+ if (ret) {
+ debug("%s: PMIC %d register write failed\n", __func__, reg);
+ return -1;
+ }
+ return 0;
+}
+
+static int max77686_init(void)
+{
+ struct pmic *p;
+
+ if (pmic_init(I2C_PMIC))
+ return -1;
+
+ p = pmic_get("MAX77686_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ if (pmic_probe(p))
+ return -1;
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
+ return -1;
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
+ MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
+ return -1;
+
+ /* VDD_MIF */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
+ MAX77686_BUCK1OUT_1V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK1OUT);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
+ MAX77686_BUCK1CTRL_EN))
+ return -1;
+
+ /* VDD_ARM */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
+ MAX77686_BUCK2DVS1_1_3V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK2DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
+ MAX77686_BUCK2CTRL_ON))
+ return -1;
+
+ /* VDD_INT */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
+ MAX77686_BUCK3DVS1_1_0125V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK3DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
+ MAX77686_BUCK3CTRL_ON))
+ return -1;
+
+ /* VDD_G3D */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
+ MAX77686_BUCK4DVS1_1_2V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK4DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
+ MAX77686_BUCK3CTRL_ON))
+ return -1;
+
+ /* VDD_LDO2 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
+ MAX77686_LD02CTRL1_1_5V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO3 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
+ MAX77686_LD03CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO5 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
+ MAX77686_LD05CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO10 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
+ MAX77686_LD10CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ return 0;
+}
+#endif
+
+int power_init_board(void)
+{
+ int ret = 0;
+
+ set_ps_hold_ctrl();
+
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+#ifdef CONFIG_POWER_MAX77686
+ ret = max77686_init();
+#endif
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_OF_CONTROL
+static int decode_sromc(const void *blob, struct fdt_sromc *config)
+{
+ int err;
+ int node;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
+ if (node < 0) {
+ debug("Could not find SROMC node\n");
+ return node;
+ }
+
+ config->bank = fdtdec_get_int(blob, node, "bank", 0);
+ config->width = fdtdec_get_int(blob, node, "width", 2);
+
+ err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
+ FDT_SROM_TIMING_COUNT);
+ if (err < 0) {
+ debug("Could not decode SROMC configuration Error: %s\n",
+ fdt_strerror(err));
+ return -FDT_ERR_NOTFOUND;
+ }
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SMC911X
+ u32 smc_bw_conf, smc_bc_conf;
+ struct fdt_sromc config;
+ fdt_addr_t base_addr;
+ int node;
+
+ node = decode_sromc(gd->fdt_blob, &config);
+ if (node < 0) {
+ debug("%s: Could not find sromc configuration\n", __func__);
+ return 0;
+ }
+ node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
+ if (node < 0) {
+ debug("%s: Could not find lan9215 configuration\n", __func__);
+ return 0;
+ }
+
+ /* We now have a node, so any problems from now on are errors */
+ base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
+ if (base_addr == FDT_ADDR_T_NONE) {
+ debug("%s: Could not find lan9215 address\n", __func__);
+ return -1;
+ }
+
+ /* Ethernet needs data bus width of 16 bits */
+ if (config.width != 2) {
+ debug("%s: Unsupported bus width %d\n", __func__,
+ config.width);
+ return -1;
+ }
+ smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
+ | SROMC_BYTE_ENABLE(config.bank);
+
+ smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |
+ SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
+ SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
+ SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
+ SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |
+ SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
+ SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
+
+ /* Select and configure the SROMC bank */
+ exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
+ s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
+ return smc911x_initialize(0, base_addr);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ /* dwmmc initializattion for available channels */
+ ret = exynos_dwmmc_init(gd->fdt_blob);
+ if (ret)
+ debug("dwmmc init failed\n");
+
+ return ret;
+}
+#endif
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ stdio_print_current_devices();
+
+ if (local.cros_ec_err) {
+ /* Force console on */
+ gd->flags &= ~GD_FLG_SILENT;
+
+ printf("cros-ec communications failure %d\n",
+ local.cros_ec_err);
+ puts("\nPlease reset with Power+Refresh\n\n");
+ panic("Cannot init cros-ec device");
+ return -1;
+ }
+ return 0;
+}
+#endif
+
+int arch_early_init_r(void)
+{
+#ifdef CONFIG_CROS_EC
+ if (board_init_cros_ec_devices(gd->fdt_blob)) {
+ printf("%s: Failed to init EC\n", __func__);
+ return 0;
+ }
+#endif
+
+ return 0;
+}
diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c
index bb4a82f..9add861 100644
--- a/board/samsung/smdk5250/exynos5-dt.c
+++ b/board/samsung/smdk5250/exynos5-dt.c
@@ -10,59 +10,20 @@
#include <asm/io.h>
#include <errno.h>
#include <i2c.h>
-#include <netdev.h>
#include <spi.h>
#include <asm/arch/cpu.h>
-#include <asm/arch/dwmmc.h>
+#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/mmc.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/power.h>
-#include <asm/arch/sromc.h>
#include <power/pmic.h>
#include <power/max77686_pmic.h>
#include <tmu.h>
DECLARE_GLOBAL_DATA_PTR;
-#if defined CONFIG_EXYNOS_TMU
-/*
- * Boot Time Thermal Analysis for SoC temperature threshold breach
- */
-static void boot_temp_check(void)
-{
- int temp;
-
- switch (tmu_monitor(&temp)) {
- /* Status TRIPPED ans WARNING means corresponding threshold breach */
- case TMU_STATUS_TRIPPED:
- puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
- set_ps_hold_ctrl();
- hang();
- break;
- case TMU_STATUS_WARNING:
- puts("EXYNOS_TMU: WARNING! Temperature very high\n");
- break;
- /*
- * TMU_STATUS_INIT means something is wrong with temperature sensing
- * and TMU status was changed back from NORMAL to INIT.
- */
- case TMU_STATUS_INIT:
- default:
- debug("EXYNOS_TMU: Unknown TMU state\n");
- }
-}
-#endif
-
-struct local_info {
- struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */
- int cros_ec_err; /* Error for cros_ec, 0 if ok */
-};
-
-static struct local_info local;
-
#ifdef CONFIG_USB_EHCI_EXYNOS
-int board_usb_vbus_init(void)
+static void board_usb_vbus_init(void)
{
struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
samsung_get_base_gpio_part1();
@@ -72,13 +33,11 @@ int board_usb_vbus_init(void)
/* VBUS turn ON time */
mdelay(3);
-
- return 0;
}
#endif
#ifdef CONFIG_SOUND_MAX98095
-static void board_enable_audio_codec(void)
+static void board_enable_audio_codec(void)
{
struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
samsung_get_base_gpio_part1();
@@ -89,39 +48,8 @@ static void board_enable_audio_codec(void)
}
#endif
-struct cros_ec_dev *board_get_cros_ec_dev(void)
-{
- return local.cros_ec_dev;
-}
-
-static int board_init_cros_ec_devices(const void *blob)
+int exynos_init(void)
{
- local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
- if (local.cros_ec_err)
- return -1; /* Will report in board_late_init() */
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
-
-#if defined CONFIG_EXYNOS_TMU
- if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
- debug("%s: Failed to init TMU\n", __func__);
- return -1;
- }
- boot_temp_check();
-#endif
-
-#ifdef CONFIG_EXYNOS_SPI
- spi_init();
-#endif
-
- if (board_init_cros_ec_devices(gd->fdt_blob))
- return -1;
-
#ifdef CONFIG_USB_EHCI_EXYNOS
board_usb_vbus_init();
#endif
@@ -131,224 +59,6 @@ int board_init(void)
return 0;
}
-int dram_init(void)
-{
- int i;
- u32 addr;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
- gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
- }
- return 0;
-}
-
-#if defined(CONFIG_POWER)
-static int pmic_reg_update(struct pmic *p, int reg, uint regval)
-{
- u32 val;
- int ret = 0;
-
- ret = pmic_reg_read(p, reg, &val);
- if (ret) {
- debug("%s: PMIC %d register read failed\n", __func__, reg);
- return -1;
- }
- val |= regval;
- ret = pmic_reg_write(p, reg, val);
- if (ret) {
- debug("%s: PMIC %d register write failed\n", __func__, reg);
- return -1;
- }
- return 0;
-}
-
-int power_init_board(void)
-{
- struct pmic *p;
-
- set_ps_hold_ctrl();
-
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
- if (pmic_init(I2C_PMIC))
- return -1;
-
- p = pmic_get("MAX77686_PMIC");
- if (!p)
- return -ENODEV;
-
- if (pmic_probe(p))
- return -1;
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
- return -1;
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
- MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
- return -1;
-
- /* VDD_MIF */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
- MAX77686_BUCK1OUT_1V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK1OUT);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
- MAX77686_BUCK1CTRL_EN))
- return -1;
-
- /* VDD_ARM */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
- MAX77686_BUCK2DVS1_1_3V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK2DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
- MAX77686_BUCK2CTRL_ON))
- return -1;
-
- /* VDD_INT */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
- MAX77686_BUCK3DVS1_1_0125V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK3DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
- MAX77686_BUCK3CTRL_ON))
- return -1;
-
- /* VDD_G3D */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
- MAX77686_BUCK4DVS1_1_2V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK4DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
- MAX77686_BUCK3CTRL_ON))
- return -1;
-
- /* VDD_LDO2 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
- MAX77686_LD02CTRL1_1_5V | EN_LDO))
- return -1;
-
- /* VDD_LDO3 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
- MAX77686_LD03CTRL1_1_8V | EN_LDO))
- return -1;
-
- /* VDD_LDO5 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
- MAX77686_LD05CTRL1_1_8V | EN_LDO))
- return -1;
-
- /* VDD_LDO10 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
- MAX77686_LD10CTRL1_1_8V | EN_LDO))
- return -1;
-
- return 0;
-}
-#endif
-
-void dram_init_banksize(void)
-{
- int i;
- u32 addr, size;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
- size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
-
- gd->bd->bi_dram[i].start = addr;
- gd->bd->bi_dram[i].size = size;
- }
-}
-
-static int decode_sromc(const void *blob, struct fdt_sromc *config)
-{
- int err;
- int node;
-
- node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
- if (node < 0) {
- debug("Could not find SROMC node\n");
- return node;
- }
-
- config->bank = fdtdec_get_int(blob, node, "bank", 0);
- config->width = fdtdec_get_int(blob, node, "width", 2);
-
- err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
- FDT_SROM_TIMING_COUNT);
- if (err < 0) {
- debug("Could not decode SROMC configuration Error: %s\n",
- fdt_strerror(err));
- return -FDT_ERR_NOTFOUND;
- }
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_SMC911X
- u32 smc_bw_conf, smc_bc_conf;
- struct fdt_sromc config;
- fdt_addr_t base_addr;
- int node;
-
- node = decode_sromc(gd->fdt_blob, &config);
- if (node < 0) {
- debug("%s: Could not find sromc configuration\n", __func__);
- return 0;
- }
- node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
- if (node < 0) {
- debug("%s: Could not find lan9215 configuration\n", __func__);
- return 0;
- }
-
- /* We now have a node, so any problems from now on are errors */
- base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
- if (base_addr == FDT_ADDR_T_NONE) {
- debug("%s: Could not find lan9215 address\n", __func__);
- return -1;
- }
-
- /* Ethernet needs data bus width of 16 bits */
- if (config.width != 2) {
- debug("%s: Unsupported bus width %d\n", __func__,
- config.width);
- return -1;
- }
- smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
- | SROMC_BYTE_ENABLE(config.bank);
-
- smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |
- SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
- SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
- SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
- SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |
- SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
- SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
-
- /* Select and configure the SROMC bank */
- exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
- s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
- return smc911x_initialize(0, base_addr);
-#endif
- return 0;
-}
-
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
@@ -364,50 +74,6 @@ int checkboard(void)
}
#endif
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
- int ret;
- /* dwmmc initializattion for available channels */
- ret = exynos_dwmmc_init(gd->fdt_blob);
- if (ret)
- debug("dwmmc init failed\n");
-
- return ret;
-}
-#endif
-
-static int board_uart_init(void)
-{
- int err, uart_id, ret = 0;
-
- for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
- err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
- if (err) {
- debug("UART%d not configured\n",
- (uart_id - PERIPH_ID_UART0));
- ret |= err;
- }
- }
- return ret;
-}
-
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-int board_early_init_f(void)
-{
- int err;
- err = board_uart_init();
- if (err) {
- debug("UART init failed\n");
- return err;
- }
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
- board_i2c_init(gd->fdt_blob);
-#endif
- return err;
-}
-#endif
-
#ifdef CONFIG_LCD
void exynos_cfg_lcd_gpio(void)
{
@@ -431,22 +97,3 @@ void exynos_set_dp_phy(unsigned int onoff)
set_dp_phy_ctrl(onoff);
}
#endif
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
- stdio_print_current_devices();
-
- if (local.cros_ec_err) {
- /* Force console on */
- gd->flags &= ~GD_FLG_SILENT;
-
- printf("cros-ec communications failure %d\n",
- local.cros_ec_err);
- puts("\nPlease reset with Power+Refresh\n\n");
- panic("Cannot init cros-ec device");
- return -1;
- }
- return 0;
-}
-#endif
diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c
index 97fe0ad..943c29a 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <cros_ec.h>
#include <fdtdec.h>
#include <asm/io.h>
#include <errno.h>
@@ -26,7 +27,7 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_USB_EHCI_EXYNOS
-int board_usb_vbus_init(void)
+static int board_usb_vbus_init(void)
{
struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
samsung_get_base_gpio_part1();
@@ -53,13 +54,8 @@ static void board_enable_audio_codec(void)
}
#endif
-int board_init(void)
+int exynos_init(void)
{
- gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
-
-#ifdef CONFIG_EXYNOS_SPI
- spi_init();
-#endif
#ifdef CONFIG_USB_EHCI_EXYNOS
board_usb_vbus_init();
#endif
@@ -69,147 +65,6 @@ int board_init(void)
return 0;
}
-int dram_init(void)
-{
- int i;
- u32 addr;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
- gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
- }
- return 0;
-}
-
-#if defined(CONFIG_POWER)
-static int pmic_reg_update(struct pmic *p, int reg, uint regval)
-{
- u32 val;
- int ret = 0;
-
- ret = pmic_reg_read(p, reg, &val);
- if (ret) {
- debug("%s: PMIC %d register read failed\n", __func__, reg);
- return -1;
- }
- val |= regval;
- ret = pmic_reg_write(p, reg, val);
- if (ret) {
- debug("%s: PMIC %d register write failed\n", __func__, reg);
- return -1;
- }
- return 0;
-}
-
-int power_init_board(void)
-{
- struct pmic *p;
-
- set_ps_hold_ctrl();
-
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
- if (pmic_init(I2C_PMIC))
- return -1;
-
- p = pmic_get("MAX77686_PMIC");
- if (!p)
- return -ENODEV;
-
- if (pmic_probe(p))
- return -1;
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
- return -1;
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
- MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
- return -1;
-
- /* VDD_MIF */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
- MAX77686_BUCK1OUT_1_05V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK1OUT);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
- MAX77686_BUCK1CTRL_EN))
- return -1;
-
- /* VDD_ARM */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
- MAX77686_BUCK2DVS1_1_3V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK2DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
- MAX77686_BUCK2CTRL_ON))
- return -1;
-
- /* VDD_INT */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
- MAX77686_BUCK3DVS1_1_0125V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK3DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
- MAX77686_BUCK3CTRL_ON))
- return -1;
-
- /* VDD_G3D */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
- MAX77686_BUCK4DVS1_1_2V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK4DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
- MAX77686_BUCK3CTRL_ON))
- return -1;
-
- /* VDD_LDO2 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
- MAX77686_LD02CTRL1_1_5V | EN_LDO))
- return -1;
-
- /* VDD_LDO3 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
- MAX77686_LD03CTRL1_1_8V | EN_LDO))
- return -1;
-
- /* VDD_LDO5 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
- MAX77686_LD05CTRL1_1_8V | EN_LDO))
- return -1;
-
- /* VDD_LDO10 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
- MAX77686_LD10CTRL1_1_8V | EN_LDO))
- return -1;
-
- return 0;
-}
-#endif
-
-void dram_init_banksize(void)
-{
- int i;
- u32 addr, size;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
- size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
- gd->bd->bi_dram[i].start = addr;
- gd->bd->bi_dram[i].size = size;
- }
-}
-
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_SMC911X
@@ -301,21 +156,6 @@ int board_mmc_init(bd_t *bis)
}
#endif
-static int board_uart_init(void)
-{
- int err, uart_id, ret = 0;
-
- for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
- err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
- if (err) {
- debug("UART%d not configured\n",
- (uart_id - PERIPH_ID_UART0));
- ret |= err;
- }
- }
- return ret;
-}
-
void board_i2c_init(const void *blob)
{
int i;
@@ -326,22 +166,6 @@ void board_i2c_init(const void *blob)
}
}
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-int board_early_init_f(void)
-{
- int err;
- err = board_uart_init();
- if (err) {
- debug("UART init failed\n");
- return err;
- }
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
- board_i2c_init(NULL);
-#endif
- return err;
-}
-#endif
-
#ifdef CONFIG_LCD
void exynos_cfg_lcd_gpio(void)
{
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 8c21909..3736ea8 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -21,6 +21,8 @@
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_COMMON
+#define CONFIG_ARCH_EARLY_INIT_R
/* Enable fdt support for Exynos5250 */
#define CONFIG_OF_CONTROL
--
1.7.12.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [U-Boot] [PATCH 01/10 V6] EXYNOS5: Create a common board file
2013-10-29 7:23 ` [U-Boot] [PATCH 01/10 V6] EXYNOS5: Create a common board file Rajeshwari S Shinde
@ 2013-11-08 8:13 ` Przemyslaw Marczak
2013-11-08 8:37 ` Rajeshwari Birje
0 siblings, 1 reply; 37+ messages in thread
From: Przemyslaw Marczak @ 2013-11-08 8:13 UTC (permalink / raw)
To: u-boot
Hello Rajeshwari,
On 10/29/2013 08:23 AM, Rajeshwari S Shinde wrote:
> Create a common board.c file for all functions which are common across
> all EXYNOS5 platforms.
>
> exynos_init function is provided for platform specific code.
>
> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
> Changes in V2:
> - None
> Changes in V3:
> - None
> Changes in V4:
> - Added check for the compilation of MAX77686 pmic.
> Changes in V5:
> - Moved board_eth_init and board_mmc_init in case of
> device tree support
> Changes in V6:
> - None.
> arch/arm/include/asm/arch-exynos/board.h | 17 ++
> board/samsung/common/Makefile | 4 +
> board/samsung/common/board.c | 405 +++++++++++++++++++++++++++++++
> board/samsung/smdk5250/exynos5-dt.c | 361 +--------------------------
> board/samsung/smdk5250/smdk5250.c | 182 +-------------
> include/configs/exynos5250-dt.h | 2 +
> 6 files changed, 435 insertions(+), 536 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-exynos/board.h
> create mode 100644 board/samsung/common/board.c
>
The name of exynos5 common file can't be just "board.c" since it is
common only for Exynos5 boards and is placed in Samsung common.
We have few Exynos4 boards in u-boot and in future we can introduce
common board file for them too.
So it is better to add some additional word to this file name. This also
needs to change config name or add checking SOC version in common Makefile.
Thank you,
--
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com
^ permalink raw reply [flat|nested] 37+ messages in thread
* [U-Boot] [PATCH 01/10 V6] EXYNOS5: Create a common board file
2013-11-08 8:13 ` Przemyslaw Marczak
@ 2013-11-08 8:37 ` Rajeshwari Birje
2013-11-08 9:03 ` Przemyslaw Marczak
0 siblings, 1 reply; 37+ messages in thread
From: Rajeshwari Birje @ 2013-11-08 8:37 UTC (permalink / raw)
To: u-boot
Hi Przemyslaw
On Fri, Nov 8, 2013 at 1:43 PM, Przemyslaw Marczak
<p.marczak@samsung.com> wrote:
> Hello Rajeshwari,
>
>
> On 10/29/2013 08:23 AM, Rajeshwari S Shinde wrote:
>>
>> Create a common board.c file for all functions which are common across
>> all EXYNOS5 platforms.
>>
>> exynos_init function is provided for platform specific code.
>>
>> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
>> Acked-by: Simon Glass <sjg@chromium.org>
>> ---
>> Changes in V2:
>> - None
>> Changes in V3:
>> - None
>> Changes in V4:
>> - Added check for the compilation of MAX77686 pmic.
>> Changes in V5:
>> - Moved board_eth_init and board_mmc_init in case of
>> device tree support
>> Changes in V6:
>> - None.
>> arch/arm/include/asm/arch-exynos/board.h | 17 ++
>> board/samsung/common/Makefile | 4 +
>> board/samsung/common/board.c | 405
>> +++++++++++++++++++++++++++++++
>> board/samsung/smdk5250/exynos5-dt.c | 361
>> +--------------------------
>> board/samsung/smdk5250/smdk5250.c | 182 +-------------
>> include/configs/exynos5250-dt.h | 2 +
>> 6 files changed, 435 insertions(+), 536 deletions(-)
>> create mode 100644 arch/arm/include/asm/arch-exynos/board.h
>> create mode 100644 board/samsung/common/board.c
>>
>
> The name of exynos5 common file can't be just "board.c" since it is common
> only for Exynos5 boards and is placed in Samsung common.
> We have few Exynos4 boards in u-boot and in future we can introduce common
> board file for them too.
> So it is better to add some additional word to this file name. This also
> needs to change config name or add checking SOC version in common Makefile.
>
Cannot we use the same file even for exynos4 boards.
--
Regards,
Rajeshwari Shinde
> Thank you,
> --
> Przemyslaw Marczak
> Samsung R&D Institute Poland
> Samsung Electronics
> p.marczak at samsung.com
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
^ permalink raw reply [flat|nested] 37+ messages in thread
* [U-Boot] [PATCH 01/10 V6] EXYNOS5: Create a common board file
2013-11-08 8:37 ` Rajeshwari Birje
@ 2013-11-08 9:03 ` Przemyslaw Marczak
2013-11-08 9:27 ` Rajeshwari Birje
0 siblings, 1 reply; 37+ messages in thread
From: Przemyslaw Marczak @ 2013-11-08 9:03 UTC (permalink / raw)
To: u-boot
Hi,
On 11/08/2013 09:37 AM, Rajeshwari Birje wrote:
> Hi Przemyslaw
>
> On Fri, Nov 8, 2013 at 1:43 PM, Przemyslaw Marczak
> <p.marczak@samsung.com> wrote:
>> Hello Rajeshwari,
>>
>>
>> On 10/29/2013 08:23 AM, Rajeshwari S Shinde wrote:
>>>
>>> Create a common board.c file for all functions which are common across
>>> all EXYNOS5 platforms.
>>>
>>> exynos_init function is provided for platform specific code.
>>>
>>> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
>>> Acked-by: Simon Glass <sjg@chromium.org>
>>> ---
>>> Changes in V2:
>>> - None
>>> Changes in V3:
>>> - None
>>> Changes in V4:
>>> - Added check for the compilation of MAX77686 pmic.
>>> Changes in V5:
>>> - Moved board_eth_init and board_mmc_init in case of
>>> device tree support
>>> Changes in V6:
>>> - None.
>>> arch/arm/include/asm/arch-exynos/board.h | 17 ++
>>> board/samsung/common/Makefile | 4 +
>>> board/samsung/common/board.c | 405
>>> +++++++++++++++++++++++++++++++
>>> board/samsung/smdk5250/exynos5-dt.c | 361
>>> +--------------------------
>>> board/samsung/smdk5250/smdk5250.c | 182 +-------------
>>> include/configs/exynos5250-dt.h | 2 +
>>> 6 files changed, 435 insertions(+), 536 deletions(-)
>>> create mode 100644 arch/arm/include/asm/arch-exynos/board.h
>>> create mode 100644 board/samsung/common/board.c
>>>
>>
>> The name of exynos5 common file can't be just "board.c" since it is common
>> only for Exynos5 boards and is placed in Samsung common.
>> We have few Exynos4 boards in u-boot and in future we can introduce common
>> board file for them too.
>> So it is better to add some additional word to this file name. This also
>> needs to change config name or add checking SOC version in common Makefile.
>>
> Cannot we use the same file even for exynos4 boards.
>
I'm not sure that you understand my intention.
You want to introduce:
board/samsung/common/board.c - with only Exynos5 code
I mean that it should looks like this, e.g:
"board/samsung/common/board_exynos4.c" - common code for all Exynos 4
"board/samsung/common/board_exynos5.c" - common code for all Exynos 5
since there is some duplicated code in Exynos4 boards that can be moved
to one common file in the future.
Do you understand my intention now?
Regards
--
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com
^ permalink raw reply [flat|nested] 37+ messages in thread
* [U-Boot] [PATCH 01/10 V6] EXYNOS5: Create a common board file
2013-11-08 9:03 ` Przemyslaw Marczak
@ 2013-11-08 9:27 ` Rajeshwari Birje
2013-11-08 9:46 ` Przemyslaw Marczak
0 siblings, 1 reply; 37+ messages in thread
From: Rajeshwari Birje @ 2013-11-08 9:27 UTC (permalink / raw)
To: u-boot
Hi,
On Fri, Nov 8, 2013 at 2:33 PM, Przemyslaw Marczak
<p.marczak@samsung.com> wrote:
> Hi,
>
>
> On 11/08/2013 09:37 AM, Rajeshwari Birje wrote:
>>
>> Hi Przemyslaw
>>
>> On Fri, Nov 8, 2013 at 1:43 PM, Przemyslaw Marczak
>> <p.marczak@samsung.com> wrote:
>>>
>>> Hello Rajeshwari,
>>>
>>>
>>> On 10/29/2013 08:23 AM, Rajeshwari S Shinde wrote:
>>>>
>>>>
>>>> Create a common board.c file for all functions which are common across
>>>> all EXYNOS5 platforms.
>>>>
>>>> exynos_init function is provided for platform specific code.
>>>>
>>>> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
>>>> Acked-by: Simon Glass <sjg@chromium.org>
>>>> ---
>>>> Changes in V2:
>>>> - None
>>>> Changes in V3:
>>>> - None
>>>> Changes in V4:
>>>> - Added check for the compilation of MAX77686 pmic.
>>>> Changes in V5:--
Regards,
Rajeshwari Shind
>>>> - Moved board_eth_init and board_mmc_init in case of
>>>> device tree support
>>>> Changes in V6:
>>>> - None.
>>>> arch/arm/include/asm/arch-exynos/board.h | 17 ++
>>>> board/samsung/common/Makefile | 4 +
>>>> board/samsung/common/board.c | 405
>>>> +++++++++++++++++++++++++++++++
>>>> board/samsung/smdk5250/exynos5-dt.c | 361
>>>> +--------------------------
>>>> board/samsung/smdk5250/smdk5250.c | 182 +-------------
>>>> include/configs/exynos5250-dt.h | 2 +
>>>> 6 files changed, 435 insertions(+), 536 deletions(-)
>>>> create mode 100644 arch/arm/include/asm/arch-exynos/board.h
>>>> create mode 100644 board/samsung/common/board.c
>>>>
>>>
>>> The name of exynos5 common file can't be just "board.c" since it is
>>> common
>>> only for Exynos5 boards and is placed in Samsung common.
>>> We have few Exynos4 boards in u-boot and in future we can introduce
>>> common
>>> board file for them too.
>>> So it is better to add some additional word to this file name. This also
>>> needs to change config name or add checking SOC version in common
>>> Makefile.
>>>
>> Cannot we use the same file even for exynos4 boards.
>>
>
> I'm not sure that you understand my intention.
>
> You want to introduce:
> board/samsung/common/board.c - with only Exynos5 code
>
> I mean that it should looks like this, e.g:
> "board/samsung/common/board_exynos4.c" - common code for all Exynos 4
> "board/samsung/common/board_exynos5.c" - common code for all Exynos 5
> since there is some duplicated code in Exynos4 boards that can be moved to
> one common file in the future.
> Do you understand my intention now?
>
Yes I understood your intention, but had a question cannot we use the
same file board.c for exynos4 and exynos5 too.
Since both have most of functions similar like board_init, dram_init,
board_uart_init and so on.
If u still feel that exynos4 and exynos5 have lots of functions
different in board/samsung we can create a seperate file. I was hoping
the same board.c could be reused for exynos4 also.
--
Regards,
Rajeshwari Shind
> Regards
>
>
> --
> Przemyslaw Marczak
> Samsung R&D Institute Poland
> Samsung Electronics
> p.marczak at samsung.com
^ permalink raw reply [flat|nested] 37+ messages in thread
* [U-Boot] [PATCH 01/10 V6] EXYNOS5: Create a common board file
2013-11-08 9:27 ` Rajeshwari Birje
@ 2013-11-08 9:46 ` Przemyslaw Marczak
2013-11-08 9:52 ` Rajeshwari Birje
0 siblings, 1 reply; 37+ messages in thread
From: Przemyslaw Marczak @ 2013-11-08 9:46 UTC (permalink / raw)
To: u-boot
Hi,
On 11/08/2013 10:27 AM, Rajeshwari Birje wrote:
> Hi,
>
>
> On Fri, Nov 8, 2013 at 2:33 PM, Przemyslaw Marczak
> <p.marczak@samsung.com> wrote:
>> Hi,
>>
>>
>> On 11/08/2013 09:37 AM, Rajeshwari Birje wrote:
>>>
>>> Hi Przemyslaw
>>>
>>> On Fri, Nov 8, 2013 at 1:43 PM, Przemyslaw Marczak
>>> <p.marczak@samsung.com> wrote:
>>>>
>>>> Hello Rajeshwari,
>>>>
>>>>
>>>> On 10/29/2013 08:23 AM, Rajeshwari S Shinde wrote:
>>>>>
>>>>>
>>>>> Create a common board.c file for all functions which are common across
>>>>> all EXYNOS5 platforms.
>>>>>
>>>>> exynos_init function is provided for platform specific code.
>>>>>
>>>>> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
>>>>> Acked-by: Simon Glass <sjg@chromium.org>
>>>>> ---
>>>>> Changes in V2:
>>>>> - None
>>>>> Changes in V3:
>>>>> - None
>>>>> Changes in V4:
>>>>> - Added check for the compilation of MAX77686 pmic.
>>>>> Changes in V5:--
> Regards,
> Rajeshwari Shind
>>>>> - Moved board_eth_init and board_mmc_init in case of
>>>>> device tree support
>>>>> Changes in V6:
>>>>> - None.
>>>>> arch/arm/include/asm/arch-exynos/board.h | 17 ++
>>>>> board/samsung/common/Makefile | 4 +
>>>>> board/samsung/common/board.c | 405
>>>>> +++++++++++++++++++++++++++++++
>>>>> board/samsung/smdk5250/exynos5-dt.c | 361
>>>>> +--------------------------
>>>>> board/samsung/smdk5250/smdk5250.c | 182 +-------------
>>>>> include/configs/exynos5250-dt.h | 2 +
>>>>> 6 files changed, 435 insertions(+), 536 deletions(-)
>>>>> create mode 100644 arch/arm/include/asm/arch-exynos/board.h
>>>>> create mode 100644 board/samsung/common/board.c
>>>>>
>>>>
>>>> The name of exynos5 common file can't be just "board.c" since it is
>>>> common
>>>> only for Exynos5 boards and is placed in Samsung common.
>>>> We have few Exynos4 boards in u-boot and in future we can introduce
>>>> common
>>>> board file for them too.
>>>> So it is better to add some additional word to this file name. This also
>>>> needs to change config name or add checking SOC version in common
>>>> Makefile.
>>>>
>>> Cannot we use the same file even for exynos4 boards.
>>>
>>
>> I'm not sure that you understand my intention.
>>
>> You want to introduce:
>> board/samsung/common/board.c - with only Exynos5 code
>>
>> I mean that it should looks like this, e.g:
>> "board/samsung/common/board_exynos4.c" - common code for all Exynos 4
>> "board/samsung/common/board_exynos5.c" - common code for all Exynos 5
>> since there is some duplicated code in Exynos4 boards that can be moved to
>> one common file in the future.
>> Do you understand my intention now?
>>
> Yes I understood your intention, but had a question cannot we use the
> same file board.c for exynos4 and exynos5 too.
> Since both have most of functions similar like board_init, dram_init,
> board_uart_init and so on.
>
> If u still feel that exynos4 and exynos5 have lots of functions
> different in board/samsung we can create a seperate file. I was hoping
> the same board.c could be reused for exynos4 also.
>
Ah, ok. This is good idea with the one common file. Then we will have
board files with strict board dependent functions. So I don't have any
objections jet.
Regards,
--
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com
^ permalink raw reply [flat|nested] 37+ messages in thread
* [U-Boot] [PATCH 01/10 V6] EXYNOS5: Create a common board file
2013-11-08 9:46 ` Przemyslaw Marczak
@ 2013-11-08 9:52 ` Rajeshwari Birje
0 siblings, 0 replies; 37+ messages in thread
From: Rajeshwari Birje @ 2013-11-08 9:52 UTC (permalink / raw)
To: u-boot
Hi,
On Fri, Nov 8, 2013 at 3:16 PM, Przemyslaw Marczak
<p.marczak@samsung.com> wrote:
> Hi,
>
>
> On 11/08/2013 10:27 AM, Rajeshwari Birje wrote:
>>
>> Hi,
>>
>>
>> On Fri, Nov 8, 2013 at 2:33 PM, Przemyslaw Marczak
>> <p.marczak@samsung.com> wrote:
>>>
>>> Hi,
>>>
>>>
>>> On 11/08/2013 09:37 AM, Rajeshwari Birje wrote:
>>>>
>>>>
>>>> Hi Przemyslaw
>>>>
>>>> On Fri, Nov 8, 2013 at 1:43 PM, Przemyslaw Marczak
>>>> <p.marczak@samsung.com> wrote:
>>>>>
>>>>>
>>>>> Hello Rajeshwari,
>>>>>
>>>>>
>>>>> On 10/29/2013 08:23 AM, Rajeshwari S Shinde wrote:
>>>>>>
>>>>>>
>>>>>>
>>>>>> Create a common board.c file for all functions which are common across
>>>>>> all EXYNOS5 platforms.
>>>>>>
>>>>>> exynos_init function is provided for platform specific code.
>>>>>>
>>>>>> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
>>>>>> Acked-by: Simon Glass <sjg@chromium.org>
>>>>>> ---
>>>>>> Changes in V2:
>>>>>> - None
>>>>>> Changes in V3:
>>>>>> - None
>>>>>> Changes in V4:
>>>>>> - Added check for the compilation of MAX77686 pmic.
>>>>>> Changes in V5:--
>>
>> Regards,
>> Rajeshwari Shind
>>>>>>
>>>>>> - Moved board_eth_init and board_mmc_init in case of
>>>>>> device tree support
>>>>>> Changes in V6:
>>>>>> - None.
>>>>>> arch/arm/include/asm/arch-exynos/board.h | 17 ++
>>>>>> board/samsung/common/Makefile | 4 +
>>>>>> board/samsung/common/board.c | 405
>>>>>> +++++++++++++++++++++++++++++++
>>>>>> board/samsung/smdk5250/exynos5-dt.c | 361
>>>>>> +--------------------------
>>>>>> board/samsung/smdk5250/smdk5250.c | 182 +-------------
>>>>>> include/configs/exynos5250-dt.h | 2 +
>>>>>> 6 files changed, 435 insertions(+), 536 deletions(-)
>>>>>> create mode 100644 arch/arm/include/asm/arch-exynos/board.h
>>>>>> create mode 100644 board/samsung/common/board.c
>>>>>>
>>>>>
>>>>> The name of exynos5 common file can't be just "board.c" since it is
>>>>> common
>>>>> only for Exynos5 boards and is placed in Samsung common.
>>>>> We have few Exynos4 boards in u-boot and in future we can introduce
>>>>> common
>>>>> board file for them too.
>>>>> So it is better to add some additional word to this file name. This
>>>>> also
>>>>> needs to change config name or add checking SOC version in common
>>>>> Makefile.
>>>>>
>>>> Cannot we use the same file even for exynos4 boards.
>>>>
>>>
>>> I'm not sure that you understand my intention.
>>>
>>> You want to introduce:
>>> board/samsung/common/board.c - with only Exynos5 code
>>>
>>> I mean that it should looks like this, e.g:
>>> "board/samsung/common/board_exynos4.c" - common code for all Exynos 4
>>> "board/samsung/common/board_exynos5.c" - common code for all Exynos 5
>>> since there is some duplicated code in Exynos4 boards that can be moved
>>> to
>>> one common file in the future.
>>> Do you understand my intention now?
>>>
>> Yes I understood your intention, but had a question cannot we use the
>> same file board.c for exynos4 and exynos5 too.
>> Since both have most of functions similar like board_init, dram_init,
>> board_uart_init and so on.
>>
>> If u still feel that exynos4 and exynos5 have lots of functions
>> different in board/samsung we can create a seperate file. I was hoping
>> the same board.c could be reused for exynos4 also.
>>
> Ah, ok. This is good idea with the one common file. Then we will have board
> files with strict board dependent functions. So I don't have any objections
> jet.
> Regards,
Ok Thank you.
--
Regards,
Rajeshwari Shinde
>
>
> --
> Przemyslaw Marczak
> Samsung R&D Institute Poland
> Samsung Electronics
> p.marczak at samsung.com
^ permalink raw reply [flat|nested] 37+ messages in thread
* [U-Boot] [PATCH 02/10 V6] Exynos5420: Add base addresses for 5420
2013-10-29 7:23 [U-Boot] [PATCH 00/10 V6] EXYNOS5420: Add SMDK5420 board support Rajeshwari S Shinde
2013-10-29 7:23 ` [U-Boot] [PATCH 01/10 V6] EXYNOS5: Create a common board file Rajeshwari S Shinde
@ 2013-10-29 7:23 ` Rajeshwari S Shinde
2013-11-13 3:20 ` Minkyu Kang
2013-10-29 7:23 ` [U-Boot] [PATCH 03/10 V6] Exynos5420: Add clock initialization " Rajeshwari S Shinde
` (8 subsequent siblings)
10 siblings, 1 reply; 37+ messages in thread
From: Rajeshwari S Shinde @ 2013-10-29 7:23 UTC (permalink / raw)
To: u-boot
Adds base addresses of various IPs and controllers required for
Exynos5420.
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Added base address for TZPC.
Changes in V5:
- None
Chnages in V6:
- Rebased on latest samsung mainline branch.
arch/arm/include/asm/arch-exynos/cpu.h | 49 +++++++++++++++++++++++++++++++++-
1 file changed, 48 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index 4b67191..10a2ac3 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -88,7 +88,7 @@
#define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
-/* EXYNOS5 Common*/
+/* EXYNOS5 */
#define EXYNOS5_I2C_SPACING 0x10000
#define EXYNOS5_AUDIOSS_BASE 0x03810000
@@ -124,6 +124,46 @@
#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
+/* EXYNOS5420 Common */
+#define EXYNOS5420_I2C_SPACING 0x10000
+
+#define EXYNOS5420_AUDIOSS_BASE 0x03810000
+#define EXYNOS5420_GPIO_PART5_BASE 0x03860000
+#define EXYNOS5420_PRO_ID 0x10000000
+#define EXYNOS5420_CLOCK_BASE 0x10010000
+#define EXYNOS5420_POWER_BASE 0x10040000
+#define EXYNOS5420_SWRESET 0x10040400
+#define EXYNOS5420_SYSREG_BASE 0x10050000
+#define EXYNOS5420_TZPC_BASE 0x100E0000
+#define EXYNOS5420_WATCHDOG_BASE 0x101D0000
+#define EXYNOS5420_ACE_SFR_BASE 0x10830000
+#define EXYNOS5420_DMC_PHY_BASE 0x10C00000
+#define EXYNOS5420_DMC_CTRL_BASE 0x10C20000
+#define EXYNOS5420_DMC_TZASC0_BASE 0x10D40000
+#define EXYNOS5420_DMC_TZASC1_BASE 0x10D50000
+#define EXYNOS5420_USB_HOST_EHCI_BASE 0x12110000
+#define EXYNOS5420_MMC_BASE 0x12200000
+#define EXYNOS5420_SROMC_BASE 0x12250000
+#define EXYNOS5420_UART_BASE 0x12C00000
+#define EXYNOS5420_I2C_BASE 0x12C60000
+#define EXYNOS5420_I2C_8910_BASE 0x12E00000
+#define EXYNOS5420_SPI_BASE 0x12D20000
+#define EXYNOS5420_I2S_BASE 0x12D60000
+#define EXYNOS5420_PWMTIMER_BASE 0x12DD0000
+#define EXYNOS5420_SPI_ISP_BASE 0x131A0000
+#define EXYNOS5420_GPIO_PART2_BASE 0x13400000
+#define EXYNOS5420_GPIO_PART3_BASE 0x13410000
+#define EXYNOS5420_GPIO_PART4_BASE 0x14000000
+#define EXYNOS5420_GPIO_PART1_BASE 0x14010000
+#define EXYNOS5420_MIPI_DSIM_BASE 0x14500000
+#define EXYNOS5420_DP_BASE 0x145B0000
+
+#define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_FIMD_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_ADC_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE
+
#ifndef __ASSEMBLY__
#include <asm/io.h>
/* CPU detection macros */
@@ -157,6 +197,10 @@ static inline void s5p_set_cpu_id(void)
/* Exynos5250 */
s5p_cpu_id = 0x5250;
break;
+ case 0x420:
+ /* Exynos5420 */
+ s5p_cpu_id = 0x5420;
+ break;
}
}
@@ -184,6 +228,7 @@ static inline int __attribute__((no_instrument_function)) \
IS_EXYNOS_TYPE(exynos4210, 0x4210)
IS_EXYNOS_TYPE(exynos4412, 0x4412)
IS_EXYNOS_TYPE(exynos5250, 0x5250)
+IS_EXYNOS_TYPE(exynos5420, 0x5420)
#define SAMSUNG_BASE(device, base) \
static inline unsigned int __attribute__((no_instrument_function)) \
@@ -194,6 +239,8 @@ static inline unsigned int __attribute__((no_instrument_function)) \
return EXYNOS4X12_##base; \
return EXYNOS4_##base; \
} else if (cpu_is_exynos5()) { \
+ if (proid_is_exynos5420()) \
+ return EXYNOS5420_##base; \
return EXYNOS5_##base; \
} \
return 0; \
--
1.7.12.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [U-Boot] [PATCH 02/10 V6] Exynos5420: Add base addresses for 5420
2013-10-29 7:23 ` [U-Boot] [PATCH 02/10 V6] Exynos5420: Add base addresses for 5420 Rajeshwari S Shinde
@ 2013-11-13 3:20 ` Minkyu Kang
0 siblings, 0 replies; 37+ messages in thread
From: Minkyu Kang @ 2013-11-13 3:20 UTC (permalink / raw)
To: u-boot
Dear Rajeshwari S Shinde,
On 29 October 2013 16:23, Rajeshwari S Shinde <rajeshwari.s@samsung.com>wrote:
> Adds base addresses of various IPs and controllers required for
> Exynos5420.
>
> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
> Changes in V2:
> - None
> Changes in V3:
> - None
> Changes in V4:
> - Added base address for TZPC.
> Changes in V5:
> - None
> Chnages in V6:
> - Rebased on latest samsung mainline branch.
> arch/arm/include/asm/arch-exynos/cpu.h | 49
> +++++++++++++++++++++++++++++++++-
> 1 file changed, 48 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
> b/arch/arm/include/asm/arch-exynos/cpu.h
> index 4b67191..10a2ac3 100644
> --- a/arch/arm/include/asm/arch-exynos/cpu.h
> +++ b/arch/arm/include/asm/arch-exynos/cpu.h
> @@ -88,7 +88,7 @@
> #define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
> #define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
>
> -/* EXYNOS5 Common*/
> +/* EXYNOS5 */
>
maybe it was wrong change.
> #define EXYNOS5_I2C_SPACING 0x10000
>
> #define EXYNOS5_AUDIOSS_BASE 0x03810000
> @@ -124,6 +124,46 @@
> #define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE
> #define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
>
> +/* EXYNOS5420 Common */
>
It was not common.
> +#define EXYNOS5420_I2C_SPACING 0x10000
> +
> +#define EXYNOS5420_AUDIOSS_BASE 0x03810000
> +#define EXYNOS5420_GPIO_PART5_BASE 0x03860000
> +#define EXYNOS5420_PRO_ID 0x10000000
> +#define EXYNOS5420_CLOCK_BASE 0x10010000
> +#define EXYNOS5420_POWER_BASE 0x10040000
> +#define EXYNOS5420_SWRESET 0x10040400
> +#define EXYNOS5420_SYSREG_BASE 0x10050000
> +#define EXYNOS5420_TZPC_BASE 0x100E0000
> +#define EXYNOS5420_WATCHDOG_BASE 0x101D0000
> +#define EXYNOS5420_ACE_SFR_BASE 0x10830000
> +#define EXYNOS5420_DMC_PHY_BASE 0x10C00000
> +#define EXYNOS5420_DMC_CTRL_BASE 0x10C20000
> +#define EXYNOS5420_DMC_TZASC0_BASE 0x10D40000
> +#define EXYNOS5420_DMC_TZASC1_BASE 0x10D50000
> +#define EXYNOS5420_USB_HOST_EHCI_BASE 0x12110000
> +#define EXYNOS5420_MMC_BASE 0x12200000
> +#define EXYNOS5420_SROMC_BASE 0x12250000
> +#define EXYNOS5420_UART_BASE 0x12C00000
> +#define EXYNOS5420_I2C_BASE 0x12C60000
> +#define EXYNOS5420_I2C_8910_BASE 0x12E00000
> +#define EXYNOS5420_SPI_BASE 0x12D20000
> +#define EXYNOS5420_I2S_BASE 0x12D60000
> +#define EXYNOS5420_PWMTIMER_BASE 0x12DD0000
> +#define EXYNOS5420_SPI_ISP_BASE 0x131A0000
> +#define EXYNOS5420_GPIO_PART2_BASE 0x13400000
> +#define EXYNOS5420_GPIO_PART3_BASE 0x13410000
> +#define EXYNOS5420_GPIO_PART4_BASE 0x14000000
> +#define EXYNOS5420_GPIO_PART1_BASE 0x14010000
> +#define EXYNOS5420_MIPI_DSIM_BASE 0x14500000
> +#define EXYNOS5420_DP_BASE 0x145B0000
> +
> +#define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE
> +#define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE
> +#define EXYNOS5420_FIMD_BASE DEVICE_NOT_AVAILABLE
> +#define EXYNOS5420_ADC_BASE DEVICE_NOT_AVAILABLE
> +#define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE
> +
> #ifndef __ASSEMBLY__
> #include <asm/io.h>
> /* CPU detection macros */
> @@ -157,6 +197,10 @@ static inline void s5p_set_cpu_id(void)
> /* Exynos5250 */
> s5p_cpu_id = 0x5250;
> break;
> + case 0x420:
> + /* Exynos5420 */
> + s5p_cpu_id = 0x5420;
> + break;
> }
> }
>
> @@ -184,6 +228,7 @@ static inline int
> __attribute__((no_instrument_function)) \
> IS_EXYNOS_TYPE(exynos4210, 0x4210)
> IS_EXYNOS_TYPE(exynos4412, 0x4412)
> IS_EXYNOS_TYPE(exynos5250, 0x5250)
> +IS_EXYNOS_TYPE(exynos5420, 0x5420)
>
> #define SAMSUNG_BASE(device, base) \
> static inline unsigned int __attribute__((no_instrument_function)) \
> @@ -194,6 +239,8 @@ static inline unsigned int
> __attribute__((no_instrument_function)) \
> return EXYNOS4X12_##base; \
> return EXYNOS4_##base; \
> } else if (cpu_is_exynos5()) { \
> + if (proid_is_exynos5420()) \
> + return EXYNOS5420_##base; \
> return EXYNOS5_##base; \
> } \
> return 0; \
> --
> 1.7.12.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
Thanks,
Minkyu Kang.
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 37+ messages in thread
* [U-Boot] [PATCH 03/10 V6] Exynos5420: Add clock initialization for 5420
2013-10-29 7:23 [U-Boot] [PATCH 00/10 V6] EXYNOS5420: Add SMDK5420 board support Rajeshwari S Shinde
2013-10-29 7:23 ` [U-Boot] [PATCH 01/10 V6] EXYNOS5: Create a common board file Rajeshwari S Shinde
2013-10-29 7:23 ` [U-Boot] [PATCH 02/10 V6] Exynos5420: Add base addresses for 5420 Rajeshwari S Shinde
@ 2013-10-29 7:23 ` Rajeshwari S Shinde
2013-11-13 2:45 ` Minkyu Kang
2013-10-29 7:23 ` [U-Boot] [PATCH 04/10 V6] Exynos5420: Add DDR3 " Rajeshwari S Shinde
` (7 subsequent siblings)
10 siblings, 1 reply; 37+ messages in thread
From: Rajeshwari S Shinde @ 2013-10-29 7:23 UTC (permalink / raw)
To: u-boot
This patch adds code for clock initialization and clock settings
of various IP's and controllers, required for Exynos5420
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Corrected the multiline commenting style
Changes in V5:
- None
Changes in V6:
- None
arch/arm/cpu/armv7/exynos/clock.c | 270 ++++++++-
arch/arm/cpu/armv7/exynos/clock_init.h | 17 +
arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 352 +++++++++++-
arch/arm/cpu/armv7/exynos/exynos5_setup.h | 740 +++++++++++++++++++------
arch/arm/include/asm/arch-exynos/clk.h | 1 +
arch/arm/include/asm/arch-exynos/clock.h | 494 +++++++++++++++++
6 files changed, 1673 insertions(+), 201 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 36fedd6..b52e61a 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -96,7 +96,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
freq = CONFIG_SYS_CLK_FREQ;
- if (pllreg == EPLL) {
+ if (pllreg == EPLL || pllreg == RPLL) {
k = k & 0xffff;
/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
@@ -117,7 +117,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
div = PLL_DIV_1024;
else if (proid_is_exynos4412())
div = PLL_DIV_65535;
- else if (proid_is_exynos5250())
+ else if (cpu_is_exynos5())
div = PLL_DIV_65536;
else
return 0;
@@ -362,6 +362,43 @@ unsigned long clock_get_periph_rate(int peripheral)
return 0;
}
+/* exynos5420: return pll clock frequency */
+static unsigned long exynos5420_get_pll_clk(int pllreg)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned long r, k = 0;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con0);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con0);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con0);
+ k = readl(&clk->epll_con1);
+ break;
+ case VPLL:
+ r = readl(&clk->vpll_con0);
+ k = readl(&clk->vpll_con1);
+ break;
+ case BPLL:
+ r = readl(&clk->bpll_con0);
+ break;
+ case RPLL:
+ r = readl(&clk->rpll_con0);
+ k = readl(&clk->rpll_con1);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ return exynos_get_pll_clk(pllreg, r, k);
+}
+
/* exynos4: return ARM clock frequency */
static unsigned long exynos4_get_arm_clk(void)
{
@@ -485,6 +522,27 @@ static unsigned long exynos4x12_get_pwm_clk(void)
return pclk;
}
+/* exynos5420: return pwm clock frequency */
+static unsigned long exynos5420_get_pwm_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned long pclk, sclk;
+ unsigned int ratio;
+
+ /*
+ * CLK_DIV_PERIC3
+ * PWM_RATIO [3:0]
+ */
+ ratio = readl(&clk->div_peric0);
+ ratio = (ratio >> 28) & 0xf;
+ sclk = get_pll_clk(MPLL);
+
+ pclk = sclk / (ratio + 1);
+
+ return pclk;
+}
+
/* exynos4: return uart clock frequency */
static unsigned long exynos4_get_uart_clk(int dev_index)
{
@@ -624,6 +682,53 @@ static unsigned long exynos5_get_uart_clk(int dev_index)
return uclk;
}
+/* exynos5420: return uart clock frequency */
+static unsigned long exynos5420_get_uart_clk(int dev_index)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned long uclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+ * CLK_SRC_PERIC0
+ * UART0_SEL [3:0]
+ * UART1_SEL [7:4]
+ * UART2_SEL [8:11]
+ * UART3_SEL [12:15]
+ * UART4_SEL [16:19]
+ * UART5_SEL [23:20]
+ */
+ sel = readl(&clk->src_peric0);
+ sel = (sel >> ((dev_index * 4) + 4)) & 0x7;
+
+ if (sel == 0x3)
+ sclk = get_pll_clk(MPLL);
+ else if (sel == 0x6)
+ sclk = get_pll_clk(EPLL);
+ else if (sel == 0x7)
+ sclk = get_pll_clk(RPLL);
+ else
+ return 0;
+
+ /*
+ * CLK_DIV_PERIC0
+ * UART0_RATIO [3:0]
+ * UART1_RATIO [7:4]
+ * UART2_RATIO [8:11]
+ * UART3_RATIO [12:15]
+ * UART4_RATIO [16:19]
+ * UART5_RATIO [23:20]
+ */
+ ratio = readl(&clk->div_peric0);
+ ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf;
+
+ uclk = sclk / (ratio + 1);
+
+ return uclk;
+}
+
static unsigned long exynos4_get_mmc_clk(int dev_index)
{
struct exynos4_clock *clk =
@@ -718,6 +823,34 @@ static unsigned long exynos5_get_mmc_clk(int dev_index)
return uclk;
}
+static unsigned long exynos5420_get_mmc_clk(int dev_index)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned long uclk, sclk;
+ unsigned int sel, ratio;
+ int shift = 0;
+
+ sel = readl(&clk->src_fsys);
+ sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
+
+ if (sel == 0x3)
+ sclk = get_pll_clk(MPLL);
+ else if (sel == 0x6)
+ sclk = get_pll_clk(EPLL);
+ else
+ return 0;
+
+ ratio = readl(&clk->div_fsys1);
+
+ shift = dev_index * 10;
+
+ ratio = (ratio >> shift) & 0x3ff;
+ uclk = (sclk / (ratio + 1));
+
+ return uclk;
+}
+
/* exynos4: set the mmc clock */
static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
{
@@ -804,6 +937,23 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
writel(val, addr);
}
+/* exynos5: set the mmc clock */
+static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned int addr;
+ unsigned int val, shift;
+
+ addr = (unsigned int)&clk->div_fsys1;
+ shift = dev_index * 10;
+
+ val = readl(addr);
+ val &= ~(0x3ff << shift);
+ val |= (div & 0x3ff) << shift;
+ writel(val, addr);
+}
+
/* get_lcd_clk: return lcd clock frequency */
static unsigned long exynos4_get_lcd_clk(void)
{
@@ -1324,6 +1474,84 @@ static int exynos5_set_spi_clk(enum periph_id periph_id,
return 0;
}
+static int exynos5420_set_spi_clk(enum periph_id periph_id,
+ unsigned int rate)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ int main;
+ unsigned int fine, val;
+ unsigned shift, pre_shift;
+ unsigned div_mask = 0xf, pre_div_mask = 0xff;
+
+ main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
+ if (main < 0) {
+ debug("%s: Cannot set clock rate for periph %d",
+ __func__, periph_id);
+ return -1;
+ }
+ main = main - 1;
+ fine = fine - 1;
+
+ switch (periph_id) {
+ case PERIPH_ID_SPI0:
+ val = readl(&clk->div_peric1);
+ val &= ~(div_mask << 20);
+ val |= (main << 20);
+ writel(val, &clk->div_peric1);
+
+ val = readl(&clk->div_peric4);
+ val &= ~(pre_div_mask << 8);
+ val |= (fine << 8);
+ writel(val, &clk->div_peric4);
+ break;
+ case PERIPH_ID_SPI1:
+ val = readl(&clk->div_peric1);
+ val &= ~(div_mask << 24);
+ val |= (main << 24);
+ writel(val, &clk->div_peric1);
+
+ val = readl(&clk->div_peric4);
+ val &= ~(pre_div_mask << 16);
+ val |= (fine << 16);
+ writel(val, &clk->div_peric4);
+ break;
+ case PERIPH_ID_SPI2:
+ val = readl(&clk->div_peric1);
+ val &= ~(div_mask << 28);
+ val |= (main << 28);
+ writel(val, &clk->div_peric1);
+
+ val = readl(&clk->div_peric4);
+ val &= ~(pre_div_mask << 24);
+ val |= (fine << 24);
+ writel(val, &clk->div_peric4);
+ break;
+ case PERIPH_ID_SPI3:
+ shift = 16;
+ pre_shift = 0;
+ clrsetbits_le32(&clk->div_isp1, div_mask << shift,
+ (main & div_mask) << shift);
+ clrsetbits_le32(&clk->div_isp1, pre_div_mask << pre_shift,
+ (fine & pre_div_mask) << pre_shift);
+ break;
+ case PERIPH_ID_SPI4:
+ shift = 20;
+ pre_shift = 8;
+ clrsetbits_le32(&clk->div_isp1, div_mask << shift,
+ (main & div_mask) << shift);
+ clrsetbits_le32(&clk->div_isp1, pre_div_mask << pre_shift,
+ (fine & pre_div_mask) << pre_shift);
+ break;
+ default:
+ debug("%s: Unsupported peripheral ID %d\n", __func__,
+ periph_id);
+ return -1;
+ }
+
+ return 0;
+}
+
static unsigned long exynos4_get_i2c_clk(void)
{
struct exynos4_clock *clk =
@@ -1341,9 +1569,11 @@ static unsigned long exynos4_get_i2c_clk(void)
unsigned long get_pll_clk(int pllreg)
{
- if (cpu_is_exynos5())
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420())
+ return exynos5420_get_pll_clk(pllreg);
return exynos5_get_pll_clk(pllreg);
- else {
+ } else {
if (proid_is_exynos4412())
return exynos4x12_get_pll_clk(pllreg);
return exynos4_get_pll_clk(pllreg);
@@ -1375,9 +1605,11 @@ unsigned long get_i2c_clk(void)
unsigned long get_pwm_clk(void)
{
- if (cpu_is_exynos5())
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420())
+ return exynos5420_get_pwm_clk();
return clock_get_periph_rate(PERIPH_ID_PWM0);
- else {
+ } else {
if (proid_is_exynos4412())
return exynos4x12_get_pwm_clk();
return exynos4_get_pwm_clk();
@@ -1386,9 +1618,11 @@ unsigned long get_pwm_clk(void)
unsigned long get_uart_clk(int dev_index)
{
- if (cpu_is_exynos5())
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420())
+ return exynos5420_get_uart_clk(dev_index);
return exynos5_get_uart_clk(dev_index);
- else {
+ } else {
if (proid_is_exynos4412())
return exynos4x12_get_uart_clk(dev_index);
return exynos4_get_uart_clk(dev_index);
@@ -1397,17 +1631,22 @@ unsigned long get_uart_clk(int dev_index)
unsigned long get_mmc_clk(int dev_index)
{
- if (cpu_is_exynos5())
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420())
+ return exynos5420_get_mmc_clk(dev_index);
return exynos5_get_mmc_clk(dev_index);
- else
+ } else {
return exynos4_get_mmc_clk(dev_index);
+ }
}
void set_mmc_clk(int dev_index, unsigned int div)
{
- if (cpu_is_exynos5())
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420())
+ return exynos5420_set_mmc_clk(dev_index, div);
exynos5_set_mmc_clk(dev_index, div);
- else {
+ } else {
if (proid_is_exynos4412())
exynos4x12_set_mmc_clk(dev_index, div);
exynos4_set_mmc_clk(dev_index, div);
@@ -1438,10 +1677,13 @@ void set_mipi_clk(void)
int set_spi_clk(int periph_id, unsigned int rate)
{
- if (cpu_is_exynos5())
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420())
+ return exynos5420_set_spi_clk(periph_id, rate);
return exynos5_set_spi_clk(periph_id, rate);
- else
+ } else {
return 0;
+ }
}
int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,
diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h b/arch/arm/cpu/armv7/exynos/clock_init.h
index c28ff3a..a875d0b 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init.h
+++ b/arch/arm/cpu/armv7/exynos/clock_init.h
@@ -10,7 +10,11 @@
#define __EXYNOS_CLOCK_INIT_H
enum {
+#ifdef CONFIG_EXYNOS5420
+ MEM_TIMINGS_MSR_COUNT = 5,
+#else
MEM_TIMINGS_MSR_COUNT = 4,
+#endif
};
/* These are the ratio's for configuring ARM clock */
@@ -59,6 +63,18 @@ struct mem_timings {
unsigned bpll_mdiv;
unsigned bpll_pdiv;
unsigned bpll_sdiv;
+ unsigned kpll_mdiv;
+ unsigned kpll_pdiv;
+ unsigned kpll_sdiv;
+ unsigned dpll_mdiv;
+ unsigned dpll_pdiv;
+ unsigned dpll_sdiv;
+ unsigned ipll_mdiv;
+ unsigned ipll_pdiv;
+ unsigned ipll_sdiv;
+ unsigned spll_mdiv;
+ unsigned spll_pdiv;
+ unsigned spll_sdiv;
unsigned pclk_cdrex_ratio;
unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
@@ -115,6 +131,7 @@ struct mem_timings {
uint8_t send_zq_init; /* 1 to send this command */
unsigned impedance; /* drive strength impedeance */
uint8_t gate_leveling_enable; /* check gate leveling is enabled */
+ uint8_t read_leveling_enable; /* check h/w read leveling is enabled */
};
/**
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
index a24c2f3..e7f1496 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
+++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
@@ -24,6 +24,24 @@
DECLARE_GLOBAL_DATA_PTR;
struct arm_clk_ratios arm_clk_ratios[] = {
+#ifdef CONFIG_EXYNOS5420
+ {
+ .arm_freq_mhz = 900,
+
+ .apll_mdiv = 0x96,
+ .apll_pdiv = 0x2,
+ .apll_sdiv = 0x1,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x3,
+ .pclk_dbg_ratio = 0x6,
+ .atb_ratio = 0x6,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x0,
+ .cpud_ratio = 0x2,
+ .arm_ratio = 0x0,
+ }
+#else
{
.arm_freq_mhz = 600,
@@ -115,8 +133,133 @@ struct arm_clk_ratios arm_clk_ratios[] = {
.cpud_ratio = 0x3,
.arm_ratio = 0x0,
}
+#endif
};
+
struct mem_timings mem_timings[] = {
+#ifdef CONFIG_EXYNOS5420
+ {
+ .mem_manuf = MEM_MANUF_SAMSUNG,
+ .mem_type = DDR_MODE_DDR3,
+ .frequency_mhz = 800,
+
+ /* MPLL @800MHz*/
+ .mpll_mdiv = 0xc8,
+ .mpll_pdiv = 0x3,
+ .mpll_sdiv = 0x1,
+ /* CPLL @666MHz */
+ .cpll_mdiv = 0xde,
+ .cpll_pdiv = 0x4,
+ .cpll_sdiv = 0x1,
+ /* EPLL @600MHz */
+ .epll_mdiv = 0x64,
+ .epll_pdiv = 0x2,
+ .epll_sdiv = 0x1,
+ /* VPLL @430MHz */
+ .vpll_mdiv = 0xd7,
+ .vpll_pdiv = 0x3,
+ .vpll_sdiv = 0x2,
+ /* BPLL @800MHz */
+ .bpll_mdiv = 0xc8,
+ .bpll_pdiv = 0x3,
+ .bpll_sdiv = 0x1,
+ /* KPLL @600MHz */
+ .kpll_mdiv = 0x190,
+ .kpll_pdiv = 0x4,
+ .kpll_sdiv = 0x2,
+ /* DPLL @600MHz */
+ .dpll_mdiv = 0x190,
+ .dpll_pdiv = 0x4,
+ .dpll_sdiv = 0x2,
+ /* IPLL @370MHz */
+ .ipll_mdiv = 0xb9,
+ .ipll_pdiv = 0x3,
+ .ipll_sdiv = 0x2,
+ /* SPLL @400MHz */
+ .spll_mdiv = 0xc8,
+ .spll_pdiv = 0x3,
+ .spll_sdiv = 0x2,
+
+ .direct_cmd_msr = {
+ 0x00020018, 0x00030000, 0x00010046, 0x00000d70,
+ 0x00000c70
+ },
+ .timing_ref = 0x000000bb,
+ .timing_row = 0x6836650f,
+ .timing_data = 0x3630580b,
+ .timing_power = 0x41000a26,
+ .phy0_dqs = 0x08080808,
+ .phy1_dqs = 0x08080808,
+ .phy0_dq = 0x08080808,
+ .phy1_dq = 0x08080808,
+ .phy0_tFS = 0x8,
+ .phy1_tFS = 0x8,
+ .phy0_pulld_dqs = 0xf,
+ .phy1_pulld_dqs = 0xf,
+
+ .lpddr3_ctrl_phy_reset = 0x1,
+ .ctrl_start_point = 0x10,
+ .ctrl_inc = 0x10,
+ .ctrl_start = 0x1,
+ .ctrl_dll_on = 0x1,
+ .ctrl_ref = 0x8,
+
+ .ctrl_force = 0x1a,
+ .ctrl_rdlat = 0x0b,
+ .ctrl_bstlen = 0x08,
+
+ .fp_resync = 0x8,
+ .iv_size = 0x7,
+ .dfi_init_start = 1,
+ .aref_en = 1,
+
+ .rd_fetch = 0x3,
+
+ .zq_mode_dds = 0x7,
+ .zq_mode_term = 0x1,
+ .zq_mode_noterm = 1,
+
+ /*
+ * Dynamic Clock: Always Running
+ * Memory Burst length: 8
+ * Number of chips: 1
+ * Memory Bus width: 32 bit
+ * Memory Type: DDR3
+ * Additional Latancy for PLL: 0 Cycle
+ */
+ .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
+ DMC_MEMCONTROL_DPWRDN_DISABLE |
+ DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
+ DMC_MEMCONTROL_TP_DISABLE |
+ DMC_MEMCONTROL_DSREF_DISABLE |
+ DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
+ DMC_MEMCONTROL_MEM_TYPE_DDR3 |
+ DMC_MEMCONTROL_MEM_WIDTH_32BIT |
+ DMC_MEMCONTROL_NUM_CHIP_1 |
+ DMC_MEMCONTROL_BL_8 |
+ DMC_MEMCONTROL_PZQ_DISABLE |
+ DMC_MEMCONTROL_MRR_BYTE_7_0,
+ .memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
+ DMC_MEMCONFIGX_CHIP_COL_10 |
+ DMC_MEMCONFIGX_CHIP_ROW_15 |
+ DMC_MEMCONFIGX_CHIP_BANK_8,
+ .prechconfig_tp_cnt = 0xff,
+ .dpwrdn_cyc = 0xff,
+ .dsref_cyc = 0xffff,
+ .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
+ DMC_CONCONTROL_TIMEOUT_LEVEL0 |
+ DMC_CONCONTROL_RD_FETCH_DISABLE |
+ DMC_CONCONTROL_EMPTY_DISABLE |
+ DMC_CONCONTROL_AREF_EN_DISABLE |
+ DMC_CONCONTROL_IO_PD_CON_DISABLE,
+ .dmc_channels = 1,
+ .chips_per_channel = 1,
+ .chips_to_configure = 1,
+ .send_zq_init = 1,
+ .gate_leveling_enable = 1,
+ .read_leveling_enable = 0,
+ }
+#else
{
.mem_manuf = MEM_MANUF_ELPIDA,
.mem_type = DDR_MODE_DDR3,
@@ -324,6 +467,7 @@ struct mem_timings mem_timings[] = {
.impedance = IMP_OUTPUT_DRV_40_OHM,
.gate_leveling_enable = 1,
}
+#endif
};
/**
@@ -399,7 +543,7 @@ struct mem_timings *clock_get_mem_timings(void)
return NULL;
}
-void system_clock_init()
+static void exynos5250_system_clock_init(void)
{
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
@@ -436,19 +580,13 @@ void system_clock_init()
} while ((val | MUX_BPLL_SEL_MASK) != val);
/* PLL locktime */
- writel(APLL_LOCK_VAL, &clk->apll_lock);
-
- writel(MPLL_LOCK_VAL, &clk->mpll_lock);
-
- writel(BPLL_LOCK_VAL, &clk->bpll_lock);
-
- writel(CPLL_LOCK_VAL, &clk->cpll_lock);
-
- writel(GPLL_LOCK_VAL, &clk->gpll_lock);
-
- writel(EPLL_LOCK_VAL, &clk->epll_lock);
-
- writel(VPLL_LOCK_VAL, &clk->vpll_lock);
+ writel(mem->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
+ writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
+ writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
+ writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
+ writel(mem->gpll_pdiv * PLL_X_LOCK_FACTOR, &clk->gpll_lock);
+ writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
+ writel(mem->vpll_pdiv * PLL_X_LOCK_FACTOR, &clk->vpll_lock);
writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
@@ -640,6 +778,192 @@ void system_clock_init()
writel(val, &clk->div_fsys2);
}
+static void exynos5420_system_clock_init(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)EXYNOS5_CLOCK_BASE;
+ struct mem_timings *mem;
+ struct arm_clk_ratios *arm_clk_ratio;
+ u32 val;
+
+ mem = clock_get_mem_timings();
+ arm_clk_ratio = get_arm_ratios();
+
+ /* PLL locktime */
+ writel(arm_clk_ratio->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
+ writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
+ writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
+ writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
+ writel(mem->dpll_pdiv * PLL_LOCK_FACTOR, &clk->dpll_lock);
+ writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
+ writel(mem->vpll_pdiv * PLL_LOCK_FACTOR, &clk->vpll_lock);
+ writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
+ writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
+ writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
+
+ setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
+
+ writel(0, &clk->src_top6);
+
+ writel(0, &clk->src_cdrex);
+ writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
+ writel(HPM_RATIO, &clk->div_cpu1);
+ writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
+
+ /* switch A15 clock source to OSC clock before changing APLL */
+ clrbits_le32(&clk->src_cpu, APLL_FOUT);
+
+ /* Set APLL */
+ writel(APLL_CON1_VAL, &clk->apll_con1);
+ val = set_pll(arm_clk_ratio->apll_mdiv,
+ arm_clk_ratio->apll_pdiv,
+ arm_clk_ratio->apll_sdiv);
+ writel(val, &clk->apll_con0);
+ while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ /* now it is safe to switch to APLL */
+ setbits_le32(&clk->src_cpu, APLL_FOUT);
+
+ writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
+ writel(CLK_DIV_KFC_VAL, &clk->div_kfc0);
+
+ /* switch A7 clock source to OSC clock before changing KPLL */
+ clrbits_le32(&clk->src_kfc, KPLL_FOUT);
+
+ /* Set KPLL*/
+ writel(KPLL_CON1_VAL, &clk->kpll_con1);
+ val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv);
+ writel(val, &clk->kpll_con0);
+ while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ /* now it is safe to switch to KPLL */
+ setbits_le32(&clk->src_kfc, KPLL_FOUT);
+
+ /* Set MPLL */
+ writel(MPLL_CON1_VAL, &clk->mpll_con1);
+ val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
+ writel(val, &clk->mpll_con0);
+ while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ /* Set DPLL */
+ writel(DPLL_CON1_VAL, &clk->dpll_con1);
+ val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv);
+ writel(val, &clk->dpll_con0);
+ while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ /* Set EPLL */
+ writel(EPLL_CON2_VAL, &clk->epll_con2);
+ writel(EPLL_CON1_VAL, &clk->epll_con1);
+ val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
+ writel(val, &clk->epll_con0);
+ while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ /* Set CPLL */
+ writel(CPLL_CON1_VAL, &clk->cpll_con1);
+ val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
+ writel(val, &clk->cpll_con0);
+ while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ /* Set IPLL */
+ writel(IPLL_CON1_VAL, &clk->ipll_con1);
+ val = set_pll(mem->ipll_mdiv, mem->ipll_pdiv, mem->ipll_sdiv);
+ writel(val, &clk->ipll_con0);
+ while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ /* Set VPLL */
+ writel(VPLL_CON1_VAL, &clk->vpll_con1);
+ val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
+ writel(val, &clk->vpll_con0);
+ while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ /* Set BPLL */
+ writel(BPLL_CON1_VAL, &clk->bpll_con1);
+ val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
+ writel(val, &clk->bpll_con0);
+ while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ /* Set SPLL */
+ writel(SPLL_CON1_VAL, &clk->spll_con1);
+ val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv);
+ writel(val, &clk->spll_con0);
+ while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
+ writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
+
+ writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+ writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+ writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
+ writel(CLK_SRC_TOP7_VAL, &clk->src_top7);
+
+ writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
+ writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
+ writel(CLK_DIV_TOP2_VAL, &clk->div_top2);
+
+ writel(0, &clk->src_top10);
+ writel(0, &clk->src_top11);
+ writel(0, &clk->src_top12);
+
+ writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
+ writel(CLK_SRC_TOP4_VAL, &clk->src_top4);
+ writel(CLK_SRC_TOP5_VAL, &clk->src_top5);
+
+ /* DISP1 BLK CLK SELECTION */
+ writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10);
+ writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10);
+
+ /* AUDIO BLK */
+ writel(AUDIO0_SEL_EPLL, &clk->src_mau);
+ writel(DIV_MAU_VAL, &clk->div_mau);
+
+ /* FSYS */
+ writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
+ writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
+ writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
+ writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
+
+ writel(CLK_SRC_ISP_VAL, &clk->src_isp);
+ writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
+ writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
+
+ writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
+ writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
+
+ writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
+ writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
+ writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
+ writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
+ writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4);
+
+ writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1);
+
+ writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
+ writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
+ writel(CLK_DIV_G2D, &clk->div_g2d);
+
+ writel(CLK_SRC_TOP6_VAL, &clk->src_top6);
+ writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
+ writel(CLK_SRC_KFC_VAL, &clk->src_kfc);
+}
+
+void system_clock_init(void)
+{
+ if (proid_is_exynos5420())
+ exynos5420_system_clock_init();
+ else
+ exynos5250_system_clock_init();
+}
+
void clock_init_dp_clock(void)
{
struct exynos5_clock *clk =
diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
index 696b386..8e05a00 100644
--- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
+++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
@@ -12,42 +12,16 @@
#include <config.h>
#include <asm/arch/dmc.h>
-/* APLL_CON1 */
-#define APLL_CON1_VAL (0x00203800)
-
-/* MPLL_CON1 */
-#define MPLL_CON1_VAL (0x00203800)
-
-/* CPLL_CON1 */
-#define CPLL_CON1_VAL (0x00203800)
-
-/* GPLL_CON1 */
-#define GPLL_CON1_VAL (0x00203800)
-
-/* EPLL_CON1, CON2 */
-#define EPLL_CON1_VAL 0x00000000
-#define EPLL_CON2_VAL 0x00000080
-
-/* VPLL_CON1, CON2 */
-#define VPLL_CON1_VAL 0x00000000
-#define VPLL_CON2_VAL 0x00000080
+#define NOT_AVAILABLE 0
+#define DATA_MASK 0xFFFFF
-/* BPLL_CON1 */
-#define BPLL_CON1_VAL 0x00203800
+#define ENABLE_BIT 0x1
+#define DISABLE_BIT 0x0
+#define CA_SWAP_EN (1 << 0)
/* Set PLL */
#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
-/* CLK_SRC_CPU */
-/* 0 = MOUTAPLL, 1 = SCLKMPLL */
-#define MUX_HPM_SEL 0
-#define MUX_CPU_SEL 0
-#define MUX_APLL_SEL 1
-
-#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
- | (MUX_CPU_SEL << 16) \
- | (MUX_APLL_SEL))
-
/* MEMCONTROL register bit fields */
#define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
#define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
@@ -78,6 +52,7 @@
/* MEMCONFIG0 register bit fields */
#define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED (1 << 12)
+#define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12)
#define DMC_MEMCONFIGX_CHIP_COL_10 (3 << 8)
#define DMC_MEMCONFIGX_CHIP_ROW_14 (2 << 4)
#define DMC_MEMCONFIGX_CHIP_ROW_15 (3 << 4)
@@ -90,6 +65,16 @@
DMC_MEMBASECONFIGX_CHIP_MASK(0x780) \
)
+/* As we use channel interleaving, therefore value of the base address
+ * register must be set as half of the bus base address
+ * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
+ * we need to set half 0x10 to the membaseconfigx registers
+ * see exynos5420 UM section 17.17.3.21 for more
+ */
+#define DMC_CHIP_BASE_0 0x10
+#define DMC_CHIP_BASE_1 0x50
+#define DMC_CHIP_MASK 0x7C0
+
#define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
#define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
@@ -113,29 +98,24 @@
/* COJCONTROL register bit fields */
#define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
+#define DMC_CONCONTROL_IO_PD_CON_ENABLE (1 << 3)
#define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
+#define DMC_CONCONTROL_AREF_EN_ENABLE (1 << 5)
#define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8)
#define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8)
#define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
#define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
#define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
-/* CLK_DIV_CPU0_VAL */
-#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \
- | (APLL_RATIO << 24) \
- | (PCLK_DBG_RATIO << 20) \
- | (ATB_RATIO << 16) \
- | (PERIPH_RATIO << 12) \
- | (ACP_RATIO << 8) \
- | (CPUD_RATIO << 4) \
- | (ARM_RATIO))
+#define DMC_CONCONTROL_VAL 0x1FFF2101
+#define DREX_CONCONTROL_VAL DMC_CONCONTROL_VAL \
+ | DMC_CONCONTROL_AREF_EN_ENABLE \
+ | DMC_CONCONTROL_IO_PD_CON_ENABLE
-/* CLK_FSYS */
-#define CLK_SRC_FSYS0_VAL 0x66666
-#define CLK_DIV_FSYS0_VAL 0x0BB00000
+#define DMC_CONCONTROL_IO_PD_CON(x) (x << 6)
-/* CLK_DIV_CPU1 */
+/* CLK_DIV_CPU1 */
#define HPM_RATIO 0x2
#define COPY_RATIO 0x0
@@ -164,10 +144,370 @@
/* CLK_DIV_SYSLFT */
#define CLK_DIV_SYSLFT_VAL 0x00000311
+#define MUX_APLL_SEL_MASK (1 << 0)
+#define MUX_MPLL_SEL_MASK (1 << 8)
+#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
+#define MUX_CPLL_SEL_MASK (1 << 8)
+#define MUX_EPLL_SEL_MASK (1 << 12)
+#define MUX_VPLL_SEL_MASK (1 << 16)
+#define MUX_GPLL_SEL_MASK (1 << 28)
+#define MUX_BPLL_SEL_MASK (1 << 0)
+#define MUX_HPM_SEL_MASK (1 << 20)
+#define HPM_SEL_SCLK_MPLL (1 << 21)
+#define PLL_LOCKED (1 << 29)
+#define APLL_CON0_LOCKED (1 << 29)
+#define MPLL_CON0_LOCKED (1 << 29)
+#define BPLL_CON0_LOCKED (1 << 29)
+#define CPLL_CON0_LOCKED (1 << 29)
+#define EPLL_CON0_LOCKED (1 << 29)
+#define GPLL_CON0_LOCKED (1 << 29)
+#define VPLL_CON0_LOCKED (1 << 29)
+#define CLK_REG_DISABLE 0x0
+#define TOP2_VAL 0x0110000
+
+/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
+#define SPI0_ISP_SEL 6
+#define SPI1_ISP_SEL 6
+#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
+ | (SPI0_ISP_SEL << 0)
+
+/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
+#define SPI0_ISP_RATIO 0xf
+#define SPI1_ISP_RATIO 0xf
+#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
+ | (SPI0_ISP_RATIO << 0)
+
+/* CLK_DIV_FSYS2 */
+#define MMC2_RATIO_MASK 0xf
+#define MMC2_RATIO_VAL 0x3
+#define MMC2_RATIO_OFFSET 0
+
+#define MMC2_PRE_RATIO_MASK 0xff
+#define MMC2_PRE_RATIO_VAL 0x9
+#define MMC2_PRE_RATIO_OFFSET 8
+
+#define MMC3_RATIO_MASK 0xf
+#define MMC3_RATIO_VAL 0x1
+#define MMC3_RATIO_OFFSET 16
+
+#define MMC3_PRE_RATIO_MASK 0xff
+#define MMC3_PRE_RATIO_VAL 0x0
+#define MMC3_PRE_RATIO_OFFSET 24
+
+/* CLK_SRC_LEX */
+#define CLK_SRC_LEX_VAL 0x0
+
+/* CLK_DIV_LEX */
+#define CLK_DIV_LEX_VAL 0x10
+
+/* CLK_DIV_R0X */
+#define CLK_DIV_R0X_VAL 0x10
+
+/* CLK_DIV_L0X */
+#define CLK_DIV_R1X_VAL 0x10
+
+/* CLK_DIV_ISP2 */
+#define CLK_DIV_ISP2_VAL 0x1
+
+/* CLK_SRC_KFC */
+#define SRC_KFC_HPM_SEL (1 << 15)
+
+/* CLK_SRC_KFC */
+#define CLK_SRC_KFC_VAL 0x00008001
+
+/* CLK_DIV_KFC */
+#define CLK_DIV_KFC_VAL 0x03300110
+
+/* CLK_DIV2_RATIO */
+#define CLK_DIV2_RATIO 0x10111150
+
+/* CLK_DIV4_RATIO */
+#define CLK_DIV4_RATIO 0x00000003
+
+/* CLK_DIV_G2D */
+#define CLK_DIV_G2D 0x00000010
+
+/*
+ * DIV_DISP1_0
+ * For DP, divisor should be 2
+ */
+#define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
+
+/* CLK_GATE_IP_DISP1 */
+#define CLK_GATE_DP1_ALLOW (1 << 4)
+
+/* AUDIO CLK SEL */
+#define AUDIO0_SEL_EPLL (0x6 << 28)
+#define AUDIO0_RATIO 0x5
+#define PCM0_RATIO 0x3
+#define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20)
+
+
+/* CLK_SRC_CDREX */
+#define MUX_MCLK_CDR_MSPLL (1 << 4)
+#define MUX_BPLL_SEL_FOUTBPLL (1 << 0)
+#define BPLL_SEL_MASK 0x7
+#define FOUTBPLL 2
+
+#define DDR3PHY_CTRL_PHY_RESET (1 << 0)
+#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
+
+#define PHY_CON0_RESET_VAL 0x17020a40
+#define P0_CMD_EN (1 << 14)
+#define BYTE_RDLVL_EN (1 << 13)
+#define CTRL_SHGATE (1 << 8)
+
+#define PHY_CON1_RESET_VAL 0x09210100
+#define RDLVL_PASS_ADJ_VAL 0x6
+#define RDLVL_PASS_ADJ_OFFSET 16
+#define CTRL_GATEDURADJ_MASK (0xf << 20)
+#define READ_LEVELLING_DDR3 0x0100
+
+#define PHY_CON2_RESET_VAL 0x00010004
+#define INIT_DESKEW_EN (1 << 6)
+#define DLL_DESKEW_EN (1 << 12)
+#define RDLVL_GATE_EN (1 << 24)
+#define RDLVL_EN (1 << 25)
+#define RDLVL_INCR_ADJ (0x1 << 16)
+
+/* DREX_PAUSE */
+#define DREX_PAUSE_EN (1 << 0)
+
+#define BYPASS_EN (1 << 22)
+
+/********-----MEMMORY VAL----------***/
+#define PHY_CON0_VAL 0x17021A00
+
+#define PHY_CON12_RESET_VAL 0x10100070
+#define PHY_CON12_VAL 0x10107F50
+#define CTRL_START (1 << 6)
+#define CTRL_DLL_ON (1 << 5)
+#define CTRL_FORCE_MASK (0x7F << 8)
+#define CTRL_LOCK_COARSE_MASK (0x7F << 10)
+
+
+#define CTRL_OFFSETD_RESET_VAL 0x8
+#define CTRL_OFFSETD_VAL 0x7F
+
+#define CTRL_OFFSETR0 0x7F
+#define CTRL_OFFSETR1 0x7F
+#define CTRL_OFFSETR2 0x7F
+#define CTRL_OFFSETR3 0x7F
+#define PHY_CON4_VAL (CTRL_OFFSETR0 << 0 | \
+ CTRL_OFFSETR1 << 8 | \
+ CTRL_OFFSETR2 << 16 | \
+ CTRL_OFFSETR3 << 24)
+#define PHY_CON4_RESET_VAL 0x08080808
+
+#define CTRL_OFFSETW0 0x7F
+#define CTRL_OFFSETW1 0x7F
+#define CTRL_OFFSETW2 0x7F
+#define CTRL_OFFSETW3 0x7F
+#define PHY_CON6_VAL (CTRL_OFFSETW0 << 0 | \
+ CTRL_OFFSETW1 << 8 | \
+ CTRL_OFFSETW2 << 16 | \
+ CTRL_OFFSETW3 << 24)
+#define PHY_CON6_RESET_VAL 0x08080808
+
+#define PHY_CON14_RESET_VAL 0x001F0000
+#define CTRL_PULLD_DQS 0xF
+#define CTRL_PULLD_DQS_OFFSET 0
+
+/*ZQ Configurations */
+#define PHY_CON16_RESET_VAL 0x08000304
+
+#define ZQ_CLK_EN (1 << 27)
+#define ZQ_CLK_DIV_EN (1 << 18)
+#define ZQ_MANUAL_STR (1 << 1)
+#define ZQ_DONE (1 << 0)
+#define ZQ_MODE_DDS_OFFSET 24
+
+#define CTRL_RDLVL_GATE_ENABLE 1
+#define CTRL_RDLVL_GATE_DISABLE 0
+#define CTRL_RDLVL_DATA_ENABLE 2
+
+/* Direct Command */
+#define DIRECT_CMD_NOP 0x07000000
+#define DIRECT_CMD_PALL 0x01000000
+#define DIRECT_CMD_ZQINIT 0x0a000000
+#define DIRECT_CMD_CHANNEL_SHIFT 28
+#define DIRECT_CMD_CHIP_SHIFT 20
+#define DIRECT_CMD_BANK_SHIFT 16
+#define DIRECT_CMD_REFA (5 << 24)
+#define DIRECT_CMD_MRS1 0x71C00
+#define DIRECT_CMD_MRS2 0x10BFC
+#define DIRECT_CMD_MRS3 0x0050C
+#define DIRECT_CMD_MRS4 0x00868
+#define DIRECT_CMD_MRS5 0x00C04
+
+/* Drive Strength */
+#define IMPEDANCE_48_OHM 4
+#define IMPEDANCE_40_OHM 5
+#define IMPEDANCE_34_OHM 6
+#define IMPEDANCE_30_OHM 7
+#define PHY_CON39_VAL_48_OHM 0x09240924
+#define PHY_CON39_VAL_40_OHM 0x0B6D0B6D
+#define PHY_CON39_VAL_34_OHM 0x0DB60DB6
+#define PHY_CON39_VAL_30_OHM 0x0FFF0FFF
+
+
+#define CTRL_BSTLEN_OFFSET 8
+#define CTRL_RDLAT_OFFSET 0
+
+#define CMD_DEFAULT_LPDDR3 0xF
+#define CMD_DEFUALT_OFFSET 0
+#define T_WRDATA_EN 0x7
+#define T_WRDATA_EN_DDR3 0x8
+#define T_WRDATA_EN_OFFSET 16
+#define T_WRDATA_EN_MASK 0x1f
+
+#define PHY_CON31_VAL 0x0C183060
+#define PHY_CON32_VAL 0x60C18306
+#define PHY_CON33_VAL 0x00000030
+
+#define PHY_CON31_RESET_VAL 0x0
+#define PHY_CON32_RESET_VAL 0x0
+#define PHY_CON33_RESET_VAL 0x0
+
+#define SL_DLL_DYN_CON_EN (1 << 1)
+#define FP_RESYNC (1 << 3)
+#define CTRL_START (1 << 6)
+
+#define DMC_AREF_EN (1 << 5)
+#define DMC_CONCONTROL_EMPTY (1 << 8)
+#define DFI_INIT_START (1 << 28)
+
+#define DMC_MEMCONTROL_VAL 0x00312700
+#define CLK_STOP_EN (1 << 0)
+#define DPWRDN_EN (1 << 1)
+#define DSREF_EN (1 << 5)
+
+#define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0
+#define MEMBASECONFIG_CHIP_MASK_OFFSET 0
+#define MEMBASECONFIG0_CHIP_BASE_VAL 0x20
+#define MEMBASECONFIG1_CHIP_BASE_VAL 0x40
+#define CHIP_BASE_OFFSET 16
+
+#define MEMCONFIG_VAL 0x1323
+#define PRECHCONFIG_DEFAULT_VAL 0xFF000000
+#define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF
+
+#define TIMINGAREF_VAL 0x5d
+#define TIMINGROW_VAL 0x345A8692
+#define TIMINGDATA_VAL 0x3630065C
+#define TIMINGPOWER_VAL 0x50380336
+#define DFI_INIT_COMPLETE (1 << 3)
+
+#define BRBRSVCONTROL_VAL 0x00000033
+#define BRBRSVCONFIG_VAL 0x88778877
+
+/* Clock Gating Control (CGCONTROL) register */
+#define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */
+#define SCG_CG_EN (1 << 2) /* Scheduler clock gating */
+#define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */
+#define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */
+#define DMC_INTERNAL_CG (MEMIF_CG_EN | SCG_CG_EN | \
+ BUSIF_WR_CG_EN | BUSIF_RD_CG_EN)
+
+/* DMC PHY Control0 register */
+#define PHY_CONTROL0_RESET_VAL 0x0
+#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
+#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
+#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
+#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
+
+/* Driver strength for CK, CKE, CS & CA */
+#define IMP_OUTPUT_DRV_40_OHM 0x5
+#define IMP_OUTPUT_DRV_30_OHM 0x7
+#define DA_3_DS_OFFSET 25
+#define DA_2_DS_OFFSET 22
+#define DA_1_DS_OFFSET 19
+#define DA_0_DS_OFFSET 16
+#define CA_CK_DRVR_DS_OFFSET 9
+#define CA_CKE_DRVR_DS_OFFSET 6
+#define CA_CS_DRVR_DS_OFFSET 3
+#define CA_ADR_DRVR_DS_OFFSET 0
+
+#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
+#define PHY_CON42_CTRL_RDLAT_SHIFT 0
+
+/*
+ * Definitions that differ with SoC's.
+ * Below is the part defining macros for smdk5250.
+ * Else part introduces macros for smdk5420.
+ */
+#ifndef CONFIG_SMDK5420
+
+/* APLL_CON1 */
+#define APLL_CON1_VAL (0x00203800)
+
+/* MPLL_CON1 */
+#define MPLL_CON1_VAL (0x00203800)
+
+/* CPLL_CON1 */
+#define CPLL_CON1_VAL (0x00203800)
+
+/* DPLL_CON1 */
+#define DPLL_CON1_VAL (NOT_AVAILABLE)
+
+/* GPLL_CON1 */
+#define GPLL_CON1_VAL (0x00203800)
+
+/* EPLL_CON1, CON2 */
+#define EPLL_CON1_VAL 0x00000000
+#define EPLL_CON2_VAL 0x00000080
+
+/* VPLL_CON1, CON2 */
+#define VPLL_CON1_VAL 0x00000000
+#define VPLL_CON2_VAL 0x00000080
+
+/* RPLL_CON1, CON2 */
+#define RPLL_CON1_VAL NOT_AVAILABLE
+#define RPLL_CON2_VAL NOT_AVAILABLE
+
+/* BPLL_CON1 */
+#define BPLL_CON1_VAL 0x00203800
+
+/* SPLL_CON1 */
+#define SPLL_CON1_VAL NOT_AVAILABLE
+
+/* IPLL_CON1 */
+#define IPLL_CON1_VAL NOT_AVAILABLE
+
+/* KPLL_CON1 */
+#define KPLL_CON1_VAL NOT_AVAILABLE
+
+/* CLK_SRC_ISP */
+#define CLK_SRC_ISP_VAL NOT_AVAILABLE
+#define CLK_DIV_ISP0_VAL 0x31
+#define CLK_DIV_ISP1_VAL 0x0
+
+/* CLK_FSYS */
+#define CLK_SRC_FSYS0_VAL 0x66666
+#define CLK_DIV_FSYS0_VAL 0x0BB00000
+#define CLK_DIV_FSYS1_VAL NOT_AVAILABLE
+#define CLK_DIV_FSYS2_VAL NOT_AVAILABLE
+
+/* CLK_SRC_CPU */
+/* 0 = MOUTAPLL, 1 = SCLKMPLL */
+#define MUX_HPM_SEL 0
+#define MUX_CPU_SEL 0
+#define MUX_APLL_SEL 1
+
+#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
+ | (MUX_CPU_SEL << 16) \
+ | (MUX_APLL_SEL))
+
/* CLK_SRC_CDREX */
#define CLK_SRC_CDREX_VAL 0x1
/* CLK_DIV_CDREX */
+#define CLK_DIV_CDREX0_VAL NOT_AVAILABLE
+#define CLK_DIV_CDREX1_VAL NOT_AVAILABLE
+
+/* CLK_DIV_CPU0_VAL */
+#define CLK_DIV_CPU0_VAL NOT_AVAILABLE
+
#define MCLK_CDREX2_RATIO 0x0
#define ACLK_EFCON_RATIO 0x1
#define MCLK_DPHY_RATIO 0x1
@@ -247,6 +587,11 @@
| (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
| (MUX_ACLK_200_DISP1_SUB_SEL << 4))
+#define CLK_SRC_TOP4_VAL NOT_AVAILABLE
+#define CLK_SRC_TOP5_VAL NOT_AVAILABLE
+#define CLK_SRC_TOP6_VAL NOT_AVAILABLE
+#define CLK_SRC_TOP7_VAL NOT_AVAILABLE
+
/* CLK_DIV_TOP0 */
#define ACLK_300_DISP1_RATIO 0x2
#define ACLK_400_G3D_RATIO 0x0
@@ -279,40 +624,11 @@
| (ACLK_400_IOP_RATIO << 16) \
| (ACLK_300_GSCL_RATIO << 12))
-/* APLL_LOCK */
-#define APLL_LOCK_VAL (0x546)
-/* MPLL_LOCK */
-#define MPLL_LOCK_VAL (0x546)
-/* CPLL_LOCK */
-#define CPLL_LOCK_VAL (0x546)
-/* GPLL_LOCK */
-#define GPLL_LOCK_VAL (0x546)
-/* EPLL_LOCK */
-#define EPLL_LOCK_VAL (0x3A98)
-/* VPLL_LOCK */
-#define VPLL_LOCK_VAL (0x3A98)
-/* BPLL_LOCK */
-#define BPLL_LOCK_VAL (0x546)
+#define CLK_DIV_TOP2_VAL NOT_AVAILABLE
-#define MUX_APLL_SEL_MASK (1 << 0)
-#define MUX_MPLL_SEL_MASK (1 << 8)
-#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
-#define MUX_CPLL_SEL_MASK (1 << 8)
-#define MUX_EPLL_SEL_MASK (1 << 12)
-#define MUX_VPLL_SEL_MASK (1 << 16)
-#define MUX_GPLL_SEL_MASK (1 << 28)
-#define MUX_BPLL_SEL_MASK (1 << 0)
-#define MUX_HPM_SEL_MASK (1 << 20)
-#define HPM_SEL_SCLK_MPLL (1 << 21)
-#define APLL_CON0_LOCKED (1 << 29)
-#define MPLL_CON0_LOCKED (1 << 29)
-#define BPLL_CON0_LOCKED (1 << 29)
-#define CPLL_CON0_LOCKED (1 << 29)
-#define EPLL_CON0_LOCKED (1 << 29)
-#define GPLL_CON0_LOCKED (1 << 29)
-#define VPLL_CON0_LOCKED (1 << 29)
-#define CLK_REG_DISABLE 0x0
-#define TOP2_VAL 0x0110000
+/* PLL Lock Value Factor */
+#define PLL_LOCK_FACTOR 250
+#define PLL_X_LOCK_FACTOR 3000
/* CLK_SRC_PERIC0 */
#define PWM_SEL 6
@@ -336,18 +652,6 @@
| (SPI1_SEL << 20) \
| (SPI0_SEL << 16))
-/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
-#define SPI0_ISP_SEL 6
-#define SPI1_ISP_SEL 6
-#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
- | (SPI0_ISP_SEL << 0)
-
-/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
-#define SPI0_ISP_RATIO 0xf
-#define SPI1_ISP_RATIO 0xf
-#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
- | (SPI0_ISP_RATIO << 0)
-
/* CLK_DIV_PERIL0 */
#define UART5_RATIO 7
#define UART4_RATIO 7
@@ -380,105 +684,200 @@
#define PWM_RATIO 8
#define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
-/* CLK_DIV_FSYS2 */
-#define MMC2_RATIO_MASK 0xf
-#define MMC2_RATIO_VAL 0x3
-#define MMC2_RATIO_OFFSET 0
-#define MMC2_PRE_RATIO_MASK 0xff
-#define MMC2_PRE_RATIO_VAL 0x9
-#define MMC2_PRE_RATIO_OFFSET 8
+/* CLK_DIV_PERIC4 */
+#define CLK_DIV_PERIC4_VAL NOT_AVAILABLE
-#define MMC3_RATIO_MASK 0xf
-#define MMC3_RATIO_VAL 0x1
-#define MMC3_RATIO_OFFSET 16
+/* CLK_SRC_DISP1_0 */
+#define CLK_SRC_DISP1_0_VAL 0x6
+#define CLK_DIV_DISP1_0_VAL NOT_AVAILABLE
-#define MMC3_PRE_RATIO_MASK 0xff
-#define MMC3_PRE_RATIO_VAL 0x0
-#define MMC3_PRE_RATIO_OFFSET 24
+#define APLL_FOUT (1 << 0)
+#define KPLL_FOUT NOT_AVAILABLE
-/* CLK_SRC_LEX */
-#define CLK_SRC_LEX_VAL 0x0
+#define CLK_DIV_CPERI1_VAL NOT_AVAILABLE
-/* CLK_DIV_LEX */
-#define CLK_DIV_LEX_VAL 0x10
+#else
-/* CLK_DIV_R0X */
-#define CLK_DIV_R0X_VAL 0x10
+/* APLL_CON1 */
+#define APLL_CON1_VAL (0x0020F300)
-/* CLK_DIV_L0X */
-#define CLK_DIV_R1X_VAL 0x10
+/* MPLL_CON1 */
+#define MPLL_CON1_VAL (0x0020F300)
-/* CLK_DIV_ISP0 */
-#define CLK_DIV_ISP0_VAL 0x31
-/* CLK_DIV_ISP1 */
-#define CLK_DIV_ISP1_VAL 0x0
+/* CPLL_CON1 */
+#define CPLL_CON1_VAL 0x0020f300
-/* CLK_DIV_ISP2 */
-#define CLK_DIV_ISP2_VAL 0x1
+/* DPLL_CON1 */
+#define DPLL_CON1_VAL (0x0020F300)
-/* CLK_SRC_DISP1_0 */
-#define CLK_SRC_DISP1_0_VAL 0x6
+/* GPLL_CON1 */
+#define GPLL_CON1_VAL (NOT_AVAILABLE)
-/*
- * DIV_DISP1_0
- * For DP, divisor should be 2
- */
-#define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
-/* CLK_GATE_IP_DISP1 */
-#define CLK_GATE_DP1_ALLOW (1 << 4)
+/* EPLL_CON1, CON2 */
+#define EPLL_CON1_VAL 0x00000000
+#define EPLL_CON2_VAL 0x00000080
-#define DDR3PHY_CTRL_PHY_RESET (1 << 0)
-#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
+/* VPLL_CON1, CON2 */
+#define VPLL_CON1_VAL 0x0020f300
+#define VPLL_CON2_VAL NOT_AVAILABLE
-#define PHY_CON0_RESET_VAL 0x17020a40
-#define P0_CMD_EN (1 << 14)
-#define BYTE_RDLVL_EN (1 << 13)
-#define CTRL_SHGATE (1 << 8)
+/* RPLL_CON1, CON2 */
+#define RPLL_CON1_VAL 0x00000000
+#define RPLL_CON2_VAL 0x00000080
-#define PHY_CON1_RESET_VAL 0x09210100
-#define CTRL_GATEDURADJ_MASK (0xf << 20)
+/* BPLL_CON1 */
+#define BPLL_CON1_VAL 0x0020f300
-#define PHY_CON2_RESET_VAL 0x00010004
-#define INIT_DESKEW_EN (1 << 6)
-#define RDLVL_GATE_EN (1 << 24)
+/* SPLL_CON1 */
+#define SPLL_CON1_VAL 0x0020f300
-/*ZQ Configurations */
-#define PHY_CON16_RESET_VAL 0x08000304
+/* IPLL_CON1 */
+#define IPLL_CON1_VAL 0x00000080
-#define ZQ_CLK_DIV_EN (1 << 18)
-#define ZQ_MANUAL_STR (1 << 1)
-#define ZQ_DONE (1 << 0)
+/* KPLL_CON1 */
+#define KPLL_CON1_VAL 0x200000
-#define CTRL_RDLVL_GATE_ENABLE 1
-#define CTRL_RDLVL_GATE_DISABLE 1
+/* CLK_SRC_ISP */
+#define CLK_SRC_ISP_VAL 0x33366000
+#define CLK_DIV_ISP0_VAL 0x13131300
+#define CLK_DIV_ISP1_VAL 0xbb110202
-/* Direct Command */
-#define DIRECT_CMD_NOP 0x07000000
-#define DIRECT_CMD_PALL 0x01000000
-#define DIRECT_CMD_ZQINIT 0x0a000000
-#define DIRECT_CMD_CHANNEL_SHIFT 28
-#define DIRECT_CMD_CHIP_SHIFT 20
-/* DMC PHY Control0 register */
-#define PHY_CONTROL0_RESET_VAL 0x0
-#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
-#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
-#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
-#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
+/* CLK_FSYS */
+#define CLK_SRC_FSYS0_VAL 0x33033300
+#define CLK_DIV_FSYS0_VAL 0x0
+#define CLK_DIV_FSYS1_VAL 0x04f13c4f
+#define CLK_DIV_FSYS2_VAL 0x041d0000
+
+/* CLK_SRC_CPU */
+/* 0 = MOUTAPLL, 1 = SCLKMPLL */
+#define MUX_HPM_SEL 1
+#define MUX_CPU_SEL 0
+#define MUX_APLL_SEL 1
-/* Driver strength for CK, CKE, CS & CA */
-#define IMP_OUTPUT_DRV_40_OHM 0x5
-#define IMP_OUTPUT_DRV_30_OHM 0x7
-#define CA_CK_DRVR_DS_OFFSET 9
-#define CA_CKE_DRVR_DS_OFFSET 6
-#define CA_CS_DRVR_DS_OFFSET 3
-#define CA_ADR_DRVR_DS_OFFSET 0
+#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
+ | (MUX_CPU_SEL << 16) \
+ | (MUX_APLL_SEL))
-#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
-#define PHY_CON42_CTRL_RDLAT_SHIFT 0
+/* CLK_SRC_CDREX */
+#define CLK_SRC_CDREX_VAL 0x00000011
+
+/* CLK_DIV_CDREX */
+#define CLK_DIV_CDREX0_VAL 0x30010100
+#define CLK_DIV_CDREX1_VAL 0x300
+
+#define CLK_DIV_CDREX_VAL 0x17010100
+
+/* CLK_DIV_CPU0_VAL */
+#define CLK_DIV_CPU0_VAL 0x01440020
+
+/* CLK_SRC_TOP */
+#define CLK_SRC_TOP0_VAL 0x12221222
+#define CLK_SRC_TOP1_VAL 0x00100200
+#define CLK_SRC_TOP2_VAL 0x11101000
+#define CLK_SRC_TOP3_VAL 0x11111111
+#define CLK_SRC_TOP4_VAL 0x11110111
+#define CLK_SRC_TOP5_VAL 0x11111100
+#define CLK_SRC_TOP6_VAL 0x11110111
+#define CLK_SRC_TOP7_VAL 0x00022200
+
+/* CLK_DIV_TOP */
+#define CLK_DIV_TOP0_VAL 0x23712311
+#define CLK_DIV_TOP1_VAL 0x13100B00
+#define CLK_DIV_TOP2_VAL 0x11101100
+
+/* PLL Lock Value Factor */
+#define PLL_LOCK_FACTOR 200
+#define PLL_X_LOCK_FACTOR 3000
+
+/* CLK_SRC_PERIC0 */
+#define SPDIF_SEL 1
+#define PWM_SEL 3
+#define UART4_SEL 3
+#define UART3_SEL 3
+#define UART2_SEL 3
+#define UART1_SEL 3
+#define UART0_SEL 3
+/* SRC_CLOCK = SCLK_RPLL */
+#define CLK_SRC_PERIC0_VAL ((SPDIF_SEL << 28) \
+ | (PWM_SEL << 24) \
+ | (UART4_SEL << 20) \
+ | (UART3_SEL << 16) \
+ | (UART2_SEL << 12) \
+ | (UART1_SEL << 8) \
+ | (UART0_SEL << 4))
+
+/* CLK_SRC_PERIC1 */
+/* SRC_CLOCK = SCLK_EPLL */
+#define SPI0_SEL 6
+#define SPI1_SEL 6
+#define SPI2_SEL 6
+#define AUDIO0_SEL 6
+#define AUDIO1_SEL 6
+#define AUDIO2_SEL 6
+#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 28) \
+ | (SPI1_SEL << 24) \
+ | (SPI0_SEL << 20) \
+ | (AUDIO2_SEL << 16) \
+ | (AUDIO2_SEL << 12) \
+ | (AUDIO2_SEL << 8))
+
+/* CLK_DIV_PERIC0 */
+#define PWM_RATIO 8
+#define UART4_RATIO 9
+#define UART3_RATIO 9
+#define UART2_RATIO 9
+#define UART1_RATIO 9
+#define UART0_RATIO 9
+
+#define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \
+ | (UART4_RATIO << 24) \
+ | (UART3_RATIO << 20) \
+ | (UART2_RATIO << 16) \
+ | (UART1_RATIO << 12) \
+ | (UART0_RATIO << 8))
+/* CLK_DIV_PERIC1 */
+#define SPI2_RATIO 0x1
+#define SPI1_RATIO 0x1
+#define SPI0_RATIO 0x1
+#define CLK_DIV_PERIC1_VAL ((SPI2_RATIO << 28) \
+ | (SPI1_RATIO << 24) \
+ | (SPI0_RATIO << 20))
+
+/* CLK_DIV_PERIC2 */
+#define PCM2_RATIO 0x3
+#define PCM1_RATIO 0x3
+#define CLK_DIV_PERIC2_VAL ((PCM2_RATIO << 24) \
+ | (PCM1_RATIO << 16))
+
+/* CLK_DIV_PERIC3 */
+#define AUDIO2_RATIO 0x5
+#define AUDIO1_RATIO 0x5
+#define AUDIO0_RATIO 0x5
+#define CLK_DIV_PERIC3_VAL ((AUDIO2_RATIO << 28) \
+ | (AUDIO1_RATIO << 24) \
+ | (AUDIO0_RATIO << 20))
+
+/* CLK_DIV_PERIC4 */
+#define SPI2_PRE_RATIO 0x2
+#define SPI1_PRE_RATIO 0x2
+#define SPI0_PRE_RATIO 0x2
+#define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \
+ | (SPI1_PRE_RATIO << 16) \
+ | (SPI0_PRE_RATIO << 8))
+
+/* CLK_SRC_DISP1_0 */
+#define CLK_SRC_DISP1_0_VAL 0x10666600
+#define CLK_DIV_DISP1_0_VAL 0x01050211
+
+#define APLL_FOUT (1 << 0)
+#define KPLL_FOUT (1 << 0)
+
+#define CLK_DIV_CPERI1_VAL 0x3f3f0000
+#endif
struct mem_timings;
@@ -490,7 +889,7 @@ enum {
};
/*
- * Memory variant specific initialization code
+ * Memory variant specific initialization code for DDR3
*
* @param mem Memory timings for this memory type.
* @param mem_iv_size Memory interleaving size is a configurable parameter
@@ -503,6 +902,9 @@ enum {
int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
int reset);
+/* Memory variant specific initialization code for LPDDR3 */
+void lpddr3_mem_ctrl_init(void);
+
/*
* Configure ZQ I/O interface
*
@@ -532,14 +934,6 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc);
void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc);
/*
- * Configure the memconfig and membaseconfig registers
- *
- * @param mem Memory timings for this memory type.
- * @param exynos5_dmc Pointer to struct of DMC registers
- */
-void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc);
-
-/*
* Reset the DLL. This function is common between DDR3 and LPDDR2.
* However, the reset value is different. So we are passing a flag
* ddr_mode to distinguish between LPDDR2 and DDR3.
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h
index 1d6fa93..cdeef32 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -14,6 +14,7 @@
#define HPLL 3
#define VPLL 4
#define BPLL 5
+#define RPLL 6
enum pll_src_bit {
EXYNOS_SRC_MPLL = 6,
diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h
index cf26eef..8259b92 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -858,6 +858,500 @@ struct exynos5_clock {
unsigned char res123[0xf5d8];
};
+struct exynos5420_clock {
+ unsigned int apll_lock; /* 0x10010000 */
+ unsigned char res1[0xfc];
+ unsigned int apll_con0;
+ unsigned int apll_con1;
+ unsigned char res2[0xf8];
+ unsigned int src_cpu;
+ unsigned char res3[0x1fc];
+ unsigned int mux_stat_cpu;
+ unsigned char res4[0xfc];
+ unsigned int div_cpu0; /* 0x10010500 */
+ unsigned int div_cpu1;
+ unsigned char res5[0xf8];
+ unsigned int div_stat_cpu0;
+ unsigned int div_stat_cpu1;
+ unsigned char res6[0xf8];
+ unsigned int gate_bus_cpu;
+ unsigned char res7[0xfc];
+ unsigned int gate_sclk_cpu;
+ unsigned char res8[0x1fc];
+ unsigned int clkout_cmu_cpu; /* 0x10010a00 */
+ unsigned int clkout_cmu_cpu_div_stat;
+ unsigned char res9[0x5f8];
+ unsigned int armclk_stopctrl;
+ unsigned char res10[0x4];
+ unsigned int arm_ema_ctrl;
+ unsigned int arm_ema_status;
+ unsigned char res11[0x10];
+ unsigned int pwr_ctrl;
+ unsigned int pwr_ctrl2;
+ unsigned char res12[0xd8];
+ unsigned int apll_con0_l8; /* 0x1001100 */
+ unsigned int apll_con0_l7;
+ unsigned int apll_con0_l6;
+ unsigned int apll_con0_l5;
+ unsigned int apll_con0_l4;
+ unsigned int apll_con0_l3;
+ unsigned int apll_con0_l2;
+ unsigned int apll_con0_l1;
+ unsigned int iem_control;
+ unsigned char res13[0xdc];
+ unsigned int apll_con1_l8; /* 0x10011200 */
+ unsigned int apll_con1_l7;
+ unsigned int apll_con1_l6;
+ unsigned int apll_con1_l5;
+ unsigned int apll_con1_l4;
+ unsigned int apll_con1_l3;
+ unsigned int apll_con1_l2;
+ unsigned int apll_con1_l1;
+ unsigned char res14[0xe0];
+ unsigned int clkdiv_iem_l8;
+ unsigned int clkdiv_iem_l7; /* 0x10011304 */
+ unsigned int clkdiv_iem_l6;
+ unsigned int clkdiv_iem_l5;
+ unsigned int clkdiv_iem_l4;
+ unsigned int clkdiv_iem_l3;
+ unsigned int clkdiv_iem_l2;
+ unsigned int clkdiv_iem_l1;
+ unsigned char res15[0xe0];
+ unsigned int l2_status;
+ unsigned char res16[0x0c];
+ unsigned int cpu_status; /* 0x10011410 */
+ unsigned char res17[0x0c];
+ unsigned int ptm_status;
+ unsigned char res18[0xbdc];
+ unsigned int cmu_cpu_spare0;
+ unsigned int cmu_cpu_spare1;
+ unsigned int cmu_cpu_spare2;
+ unsigned int cmu_cpu_spare3;
+ unsigned int cmu_cpu_spare4;
+ unsigned char res19[0x1fdc];
+ unsigned int cmu_cpu_version;
+ unsigned char res20[0x20c];
+ unsigned int src_cperi0; /* 0x10014200 */
+ unsigned int src_cperi1;
+ unsigned char res21[0xf8];
+ unsigned int src_mask_cperi;
+ unsigned char res22[0x100];
+ unsigned int mux_stat_cperi1;
+ unsigned char res23[0xfc];
+ unsigned int div_cperi1;
+ unsigned char res24[0xfc];
+ unsigned int div_stat_cperi1;
+ unsigned char res25[0xf8];
+ unsigned int gate_bus_cperi0; /* 0x10014700 */
+ unsigned int gate_bus_cperi1;
+ unsigned char res26[0xf8];
+ unsigned int gate_sclk_cperi;
+ unsigned char res27[0xfc];
+ unsigned int gate_ip_cperi;
+ unsigned char res28[0xfc];
+ unsigned int clkout_cmu_cperi;
+ unsigned int clkout_cmu_cperi_div_stat;
+ unsigned char res29[0x5f8];
+ unsigned int dcgidx_map0; /* 0x10015000 */
+ unsigned int dcgidx_map1;
+ unsigned int dcgidx_map2;
+ unsigned char res30[0x14];
+ unsigned int dcgperf_map0;
+ unsigned int dcgperf_map1;
+ unsigned char res31[0x18];
+ unsigned int dvcidx_map;
+ unsigned char res32[0x1c];
+ unsigned int freq_cpu;
+ unsigned int freq_dpm;
+ unsigned char res33[0x18];
+ unsigned int dvsemclk_en; /* 0x10015080 */
+ unsigned int maxperf;
+ unsigned char res34[0x2e78];
+ unsigned int cmu_cperi_spare0;
+ unsigned int cmu_cperi_spare1;
+ unsigned int cmu_cperi_spare2;
+ unsigned int cmu_cperi_spare3;
+ unsigned int cmu_cperi_spare4;
+ unsigned int cmu_cperi_spare5;
+ unsigned int cmu_cperi_spare6;
+ unsigned int cmu_cperi_spare7;
+ unsigned int cmu_cperi_spare8;
+ unsigned char res35[0xcc];
+ unsigned int cmu_cperi_version; /* 0x10017ff0 */
+ unsigned char res36[0x50c];
+ unsigned int div_g2d;
+ unsigned char res37[0xfc];
+ unsigned int div_stat_g2d;
+ unsigned char res38[0xfc];
+ unsigned int gate_bus_g2d;
+ unsigned char res39[0xfc];
+ unsigned int gate_ip_g2d;
+ unsigned char res40[0x1fc];
+ unsigned int clkout_cmu_g2d;
+ unsigned int clkout_cmu_g2d_div_stat; /* 0x10018a04 */
+ unsigned char res41[0xf8];
+ unsigned int cmu_g2d_spare0;
+ unsigned int cmu_g2d_spare1;
+ unsigned int cmu_g2d_spare2;
+ unsigned int cmu_g2d_spare3;
+ unsigned int cmu_g2d_spare4;
+ unsigned char res42[0x34dc];
+ unsigned int cmu_g2d_version;
+ unsigned char res43[0x30c];
+ unsigned int div_cmu_isp0;
+ unsigned int div_cmu_isp1;
+ unsigned int div_isp2; /* 0x1001c308 */
+ unsigned char res44[0xf4];
+ unsigned int div_stat_cmu_isp0;
+ unsigned int div_stat_cmu_isp1;
+ unsigned int div_stat_isp2;
+ unsigned char res45[0x2f4];
+ unsigned int gate_bus_isp0;
+ unsigned int gate_bus_isp1;
+ unsigned int gate_bus_isp2;
+ unsigned int gate_bus_isp3;
+ unsigned char res46[0xf0];
+ unsigned int gate_ip_isp0;
+ unsigned int gate_ip_isp1;
+ unsigned char res47[0xf8];
+ unsigned int gate_sclk_isp;
+ unsigned char res48[0x0c];
+ unsigned int mcuisp_pwr_ctrl; /* 0x1001c910 */
+ unsigned char res49[0x0ec];
+ unsigned int clkout_cmu_isp;
+ unsigned int clkout_cmu_isp_div_stat;
+ unsigned char res50[0xf8];
+ unsigned int cmu_isp_spare0;
+ unsigned int cmu_isp_spare1;
+ unsigned int cmu_isp_spare2;
+ unsigned int cmu_isp_spare3;
+ unsigned char res51[0x34e0];
+ unsigned int cmu_isp_version;
+ unsigned char res52[0x2c];
+ unsigned int cpll_lock; /* 10020020 */
+ unsigned char res53[0xc];
+ unsigned int dpll_lock;
+ unsigned char res54[0xc];
+ unsigned int epll_lock;
+ unsigned char res55[0xc];
+ unsigned int rpll_lock;
+ unsigned char res56[0xc];
+ unsigned int ipll_lock;
+ unsigned char res57[0xc];
+ unsigned int spll_lock;
+ unsigned char res58[0xc];
+ unsigned int vpll_lock;
+ unsigned char res59[0xc];
+ unsigned int mpll_lock;
+ unsigned char res60[0x8c];
+ unsigned int cpll_con0; /* 10020120 */
+ unsigned int cpll_con1;
+ unsigned int dpll_con0;
+ unsigned int dpll_con1;
+ unsigned int epll_con0;
+ unsigned int epll_con1;
+ unsigned int epll_con2;
+ unsigned char res601[0x4];
+ unsigned int rpll_con0;
+ unsigned int rpll_con1;
+ unsigned int rpll_con2;
+ unsigned char res602[0x4];
+ unsigned int ipll_con0;
+ unsigned int ipll_con1;
+ unsigned char res61[0x8];
+ unsigned int spll_con0;
+ unsigned int spll_con1;
+ unsigned char res62[0x8];
+ unsigned int vpll_con0;
+ unsigned int vpll_con1;
+ unsigned char res63[0x8];
+ unsigned int mpll_con0;
+ unsigned int mpll_con1;
+ unsigned char res64[0x78];
+ unsigned int src_top0; /* 0x10020200 */
+ unsigned int src_top1;
+ unsigned int src_top2;
+ unsigned int src_top3;
+ unsigned int src_top4;
+ unsigned int src_top5;
+ unsigned int src_top6;
+ unsigned int src_top7;
+ unsigned char res65[0xc];
+ unsigned int src_disp10; /* 0x1002022c */
+ unsigned char res66[0x10];
+ unsigned int src_mau;
+ unsigned int src_fsys;
+ unsigned char res67[0x8];
+ unsigned int src_peric0;
+ unsigned int src_peric1;
+ unsigned char res68[0x18];
+ unsigned int src_isp;
+ unsigned char res69[0x0c];
+ unsigned int src_top10;
+ unsigned int src_top11;
+ unsigned int src_top12;
+ unsigned char res70[0x74];
+ unsigned int src_mask_top0;
+ unsigned int src_mask_top1;
+ unsigned int src_mask_top2;
+ unsigned char res71[0x10];
+ unsigned int src_mask_top7;
+ unsigned char res72[0xc];
+ unsigned int src_mask_disp10; /* 0x1002032c */
+ unsigned char res73[0x4];
+ unsigned int src_mask_mau;
+ unsigned char res74[0x8];
+ unsigned int src_mask_fsys;
+ unsigned char res75[0xc];
+ unsigned int src_mask_peric0;
+ unsigned int src_mask_peric1;
+ unsigned char res76[0x18];
+ unsigned int src_mask_isp;
+ unsigned char res77[0x8c];
+ unsigned int mux_stat_top0; /* 0x10020400 */
+ unsigned int mux_stat_top1;
+ unsigned int mux_stat_top2;
+ unsigned int mux_stat_top3;
+ unsigned int mux_stat_top4;
+ unsigned int mux_stat_top5;
+ unsigned int mux_stat_top6;
+ unsigned int mux_stat_top7;
+ unsigned char res78[0x60];
+ unsigned int mux_stat_top10;
+ unsigned int mux_stat_top11;
+ unsigned int mux_stat_top12;
+ unsigned char res79[0x74];
+ unsigned int div_top0; /* 0x10020500 */
+ unsigned int div_top1;
+ unsigned int div_top2;
+ unsigned char res80[0x20];
+ unsigned int div_disp10;
+ unsigned char res81[0x14];
+ unsigned int div_mau;
+ unsigned int div_fsys0;
+ unsigned int div_fsys1;
+ unsigned int div_fsys2;
+ unsigned char res82[0x4];
+ unsigned int div_peric0;
+ unsigned int div_peric1;
+ unsigned int div_peric2;
+ unsigned int div_peric3;
+ unsigned int div_peric4; /* 0x10020568 */
+ unsigned char res83[0x14];
+ unsigned int div_isp0;
+ unsigned int div_isp1;
+ unsigned char res84[0x8];
+ unsigned int clkdiv2_ratio;
+ unsigned char res850[0xc];
+ unsigned int clkdiv4_ratio;
+ unsigned char res85[0x5c];
+ unsigned int div_stat_top0;
+ unsigned int div_stat_top1;
+ unsigned int div_stat_top2;
+ unsigned char res86[0x20];
+ unsigned int div_stat_disp10;
+ unsigned char res87[0x14];
+ unsigned int div_stat_mau; /* 0x10020644 */
+ unsigned int div_stat_fsys0;
+ unsigned int div_stat_fsys1;
+ unsigned int div_stat_fsys2;
+ unsigned char res88[0x4];
+ unsigned int div_stat_peric0;
+ unsigned int div_stat_peric1;
+ unsigned int div_stat_peric2;
+ unsigned int div_stat_peric3;
+ unsigned int div_stat_peric4;
+ unsigned char res89[0x14];
+ unsigned int div_stat_isp0;
+ unsigned int div_stat_isp1;
+ unsigned char res90[0x8];
+ unsigned int clkdiv2_stat0;
+ unsigned char res91[0xc];
+ unsigned int clkdiv4_stat;
+ unsigned char res92[0x5c];
+ unsigned int gate_bus_top; /* 0x10020700 */
+ unsigned char res93[0xc];
+ unsigned int gate_bus_gscl0;
+ unsigned char res94[0xc];
+ unsigned int gate_bus_gscl1;
+ unsigned char res95[0x4];
+ unsigned int gate_bus_disp1;
+ unsigned char res96[0x4];
+ unsigned int gate_bus_wcore;
+ unsigned int gate_bus_mfc;
+ unsigned int gate_bus_g3d;
+ unsigned int gate_bus_gen;
+ unsigned int gate_bus_fsys0;
+ unsigned int gate_bus_fsys1;
+ unsigned int gate_bus_fsys2;
+ unsigned int gate_bus_mscl;
+ unsigned int gate_bus_peric;
+ unsigned int gate_bus_peric1;
+ unsigned char res97[0x8];
+ unsigned int gate_bus_peris0;
+ unsigned int gate_bus_peris1; /* 0x10020764 */
+ unsigned char res98[0x8];
+ unsigned int gate_bus_noc;
+ unsigned char res99[0xac];
+ unsigned int gate_top_sclk_gscl;
+ unsigned char res1000[0x4];
+ unsigned int gate_top_sclk_disp1;
+ unsigned char res100[0x10];
+ unsigned int gate_top_sclk_mau;
+ unsigned int gate_top_sclk_fsys;
+ unsigned char res101[0xc];
+ unsigned int gate_top_sclk_peric;
+ unsigned char res102[0xc];
+ unsigned int gate_top_sclk_cperi;
+ unsigned char res103[0xc];
+ unsigned int gate_top_sclk_isp;
+ unsigned char res104[0x9c];
+ unsigned int gate_ip_gscl0;
+ unsigned char res105[0xc];
+ unsigned int gate_ip_gscl1;
+ unsigned char res106[0x4];
+ unsigned int gate_ip_disp1;
+ unsigned int gate_ip_mfc;
+ unsigned int gate_ip_g3d;
+ unsigned int gate_ip_gen; /* 0x10020934 */
+ unsigned char res107[0xc];
+ unsigned int gate_ip_fsys;
+ unsigned char res108[0x8];
+ unsigned int gate_ip_peric;
+ unsigned char res109[0xc];
+ unsigned int gate_ip_peris;
+ unsigned char res110[0xc];
+ unsigned int gate_ip_mscl;
+ unsigned char res111[0xc];
+ unsigned int gate_ip_block;
+ unsigned char res112[0xc];
+ unsigned int bypass;
+ unsigned char res113[0x6c];
+ unsigned int clkout_cmu_top;
+ unsigned int clkout_cmu_top_div_stat;
+ unsigned char res114[0xf8];
+ unsigned int clkout_top_spare0;
+ unsigned int clkout_top_spare1;
+ unsigned int clkout_top_spare2;
+ unsigned int clkout_top_spare3;
+ unsigned char res115[0x34e0];
+ unsigned int clkout_top_version;
+ unsigned char res116[0xc01c];
+ unsigned int bpll_lock; /* 0x10030010 */
+ unsigned char res117[0xfc];
+ unsigned int bpll_con0;
+ unsigned int bpll_con1;
+ unsigned char res118[0xe8];
+ unsigned int src_cdrex;
+ unsigned char res119[0x1fc];
+ unsigned int mux_stat_cdrex;
+ unsigned char res120[0xfc];
+ unsigned int div_cdrex0;
+ unsigned int div_cdrex1;
+ unsigned char res121[0xf8];
+ unsigned int div_stat_cdrex;
+ unsigned char res1211[0xfc];
+ unsigned int gate_bus_cdrex;
+ unsigned int gate_bus_cdrex1;
+ unsigned char res122[0x1f8];
+ unsigned int gate_ip_cdrex;
+ unsigned char res123[0x10];
+ unsigned int dmc_freq_ctrl; /* 0x10030914 */
+ unsigned char res124[0x4];
+ unsigned int pause;
+ unsigned int ddrphy_lock_ctrl;
+ unsigned char res125[0xdc];
+ unsigned int clkout_cmu_cdrex;
+ unsigned int clkout_cmu_cdrex_div_stat;
+ unsigned char res126[0x8];
+ unsigned int lpddr3phy_ctrl;
+ unsigned int lpddr3phy_con0;
+ unsigned int lpddr3phy_con1;
+ unsigned int lpddr3phy_con2;
+ unsigned int lpddr3phy_con3;
+ unsigned int lpddr3phy_con4;
+ unsigned int lpddr3phy_con5; /* 0x10030a28 */
+ unsigned int pll_div2_sel;
+ unsigned char res127[0xd0];
+ unsigned int cmu_cdrex_spare0;
+ unsigned int cmu_cdrex_spare1;
+ unsigned int cmu_cdrex_spare2;
+ unsigned int cmu_cdrex_spare3;
+ unsigned int cmu_cdrex_spare4;
+ unsigned char res128[0x34dc];
+ unsigned int cmu_cdrex_version; /* 0x10033ff0 */
+ unsigned char res129[0x400c];
+ unsigned int kpll_lock;
+ unsigned char res130[0xfc];
+ unsigned int kpll_con0;
+ unsigned int kpll_con1;
+ unsigned char res131[0xf8];
+ unsigned int src_kfc;
+ unsigned char res132[0x1fc];
+ unsigned int mux_stat_kfc; /* 0x10038400 */
+ unsigned char res133[0xfc];
+ unsigned int div_kfc0;
+ unsigned char res134[0xfc];
+ unsigned int div_stat_kfc0;
+ unsigned char res135[0xfc];
+ unsigned int gate_bus_cpu_kfc;
+ unsigned char res136[0xfc];
+ unsigned int gate_sclk_cpu_kfc;
+ unsigned char res137[0x1fc];
+ unsigned int clkout_cmu_kfc;
+ unsigned int clkout_cmu_kfc_div_stat; /* 0x10038a04 */
+ unsigned char res138[0x5f8];
+ unsigned int armclk_stopctrl_kfc;
+ unsigned char res139[0x4];
+ unsigned int armclk_ema_ctrl_kfc;
+ unsigned int armclk_ema_status_kfc;
+ unsigned char res140[0x10];
+ unsigned int pwr_ctrl_kfc;
+ unsigned int pwr_ctrl2_kfc;
+ unsigned char res141[0xd8];
+ unsigned int kpll_con0_l8;
+ unsigned int kpll_con0_l7;
+ unsigned int kpll_con0_l6;
+ unsigned int kpll_con0_l5;
+ unsigned int kpll_con0_l4;
+ unsigned int kpll_con0_l3;
+ unsigned int kpll_con0_l2;
+ unsigned int kpll_con0_l1;
+ unsigned int iem_control_kfc; /* 0x10039120 */
+ unsigned char res142[0xdc];
+ unsigned int kpll_con1_l8;
+ unsigned int kpll_con1_l7;
+ unsigned int kpll_con1_l6;
+ unsigned int kpll_con1_l5;
+ unsigned int kpll_con1_l4;
+ unsigned int kpll_con1_l3;
+ unsigned int kpll_con1_l2;
+ unsigned int kpll_con1_l1;
+ unsigned char res143[0xe0];
+ unsigned int clkdiv_iem_l8_kfc; /* 0x10039300 */
+ unsigned int clkdiv_iem_l7_kfc;
+ unsigned int clkdiv_iem_l6_kfc;
+ unsigned int clkdiv_iem_l5_kfc;
+ unsigned int clkdiv_iem_l4_kfc;
+ unsigned int clkdiv_iem_l3_kfc;
+ unsigned int clkdiv_iem_l2_kfc;
+ unsigned int clkdiv_iem_l1_kfc;
+ unsigned char res144[0xe0];
+ unsigned int l2_status_kfc;
+ unsigned char res145[0xc];
+ unsigned int cpu_status_kfc; /* 0x10039410 */
+ unsigned char res146[0xc];
+ unsigned int ptm_status_kfc;
+ unsigned char res147[0xbdc];
+ unsigned int cmu_kfc_spare0;
+ unsigned int cmu_kfc_spare1;
+ unsigned int cmu_kfc_spare2;
+ unsigned int cmu_kfc_spare3;
+ unsigned int cmu_kfc_spare4;
+ unsigned char res148[0x1fdc];
+ unsigned int cmu_kfc_version; /* 0x1003bff0 */
+};
+
/* structure for epll configuration used in audio clock configuration */
struct set_epll_con_val {
unsigned int freq_out; /* frequency out */
--
1.7.12.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [U-Boot] [PATCH 03/10 V6] Exynos5420: Add clock initialization for 5420
2013-10-29 7:23 ` [U-Boot] [PATCH 03/10 V6] Exynos5420: Add clock initialization " Rajeshwari S Shinde
@ 2013-11-13 2:45 ` Minkyu Kang
2013-11-13 11:17 ` Rajeshwari Birje
0 siblings, 1 reply; 37+ messages in thread
From: Minkyu Kang @ 2013-11-13 2:45 UTC (permalink / raw)
To: u-boot
Dear Rajeshwari S Shinde,
On 29 October 2013 16:23, Rajeshwari S Shinde <rajeshwari.s@samsung.com>wrote:
> This patch adds code for clock initialization and clock settings
> of various IP's and controllers, required for Exynos5420
>
> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
> Changes in V2:
> - None
> Changes in V3:
> - None
> Changes in V4:
> - Corrected the multiline commenting style
> Changes in V5:
> - None
> Changes in V6:
> - None
> arch/arm/cpu/armv7/exynos/clock.c | 270 ++++++++-
> arch/arm/cpu/armv7/exynos/clock_init.h | 17 +
> arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 352 +++++++++++-
> arch/arm/cpu/armv7/exynos/exynos5_setup.h | 740
> +++++++++++++++++++------
> arch/arm/include/asm/arch-exynos/clk.h | 1 +
> arch/arm/include/asm/arch-exynos/clock.h | 494 +++++++++++++++++
> 6 files changed, 1673 insertions(+), 201 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
> b/arch/arm/cpu/armv7/exynos/clock.c
> index 36fedd6..b52e61a 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -96,7 +96,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int
> r, unsigned int k)
>
> freq = CONFIG_SYS_CLK_FREQ;
>
> - if (pllreg == EPLL) {
> + if (pllreg == EPLL || pllreg == RPLL) {
> k = k & 0xffff;
> /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
> fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
> @@ -117,7 +117,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int
> r, unsigned int k)
> div = PLL_DIV_1024;
> else if (proid_is_exynos4412())
> div = PLL_DIV_65535;
> - else if (proid_is_exynos5250())
> + else if (cpu_is_exynos5())
>
please don't mix proid_is... and cpu_is...
> div = PLL_DIV_65536;
> else
> return 0;
> @@ -362,6 +362,43 @@ unsigned long clock_get_periph_rate(int peripheral)
> return 0;
> }
>
> +/* exynos5420: return pll clock frequency */
> +static unsigned long exynos5420_get_pll_clk(int pllreg)
> +{
> + struct exynos5420_clock *clk =
> + (struct exynos5420_clock *)samsung_get_base_clock();
> + unsigned long r, k = 0;
> +
> + switch (pllreg) {
> + case APLL:
> + r = readl(&clk->apll_con0);
> + break;
> + case MPLL:
> + r = readl(&clk->mpll_con0);
> + break;
> + case EPLL:
> + r = readl(&clk->epll_con0);
> + k = readl(&clk->epll_con1);
> + break;
> + case VPLL:
> + r = readl(&clk->vpll_con0);
> + k = readl(&clk->vpll_con1);
> + break;
> + case BPLL:
> + r = readl(&clk->bpll_con0);
> + break;
> + case RPLL:
> + r = readl(&clk->rpll_con0);
> + k = readl(&clk->rpll_con1);
> + break;
> + default:
> + printf("Unsupported PLL (%d)\n", pllreg);
> + return 0;
> + }
> +
> + return exynos_get_pll_clk(pllreg, r, k);
> +}
> +
> /* exynos4: return ARM clock frequency */
> static unsigned long exynos4_get_arm_clk(void)
> {
> @@ -485,6 +522,27 @@ static unsigned long exynos4x12_get_pwm_clk(void)
> return pclk;
> }
>
> +/* exynos5420: return pwm clock frequency */
> +static unsigned long exynos5420_get_pwm_clk(void)
> +{
> + struct exynos5420_clock *clk =
> + (struct exynos5420_clock *)samsung_get_base_clock();
> + unsigned long pclk, sclk;
> + unsigned int ratio;
> +
> + /*
> + * CLK_DIV_PERIC3
> + * PWM_RATIO [3:0]
> + */
> + ratio = readl(&clk->div_peric0);
> + ratio = (ratio >> 28) & 0xf;
> + sclk = get_pll_clk(MPLL);
> +
> + pclk = sclk / (ratio + 1);
> +
> + return pclk;
> +}
> +
> /* exynos4: return uart clock frequency */
> static unsigned long exynos4_get_uart_clk(int dev_index)
> {
> @@ -624,6 +682,53 @@ static unsigned long exynos5_get_uart_clk(int
> dev_index)
> return uclk;
> }
>
> +/* exynos5420: return uart clock frequency */
> +static unsigned long exynos5420_get_uart_clk(int dev_index)
> +{
> + struct exynos5420_clock *clk =
> + (struct exynos5420_clock *)samsung_get_base_clock();
> + unsigned long uclk, sclk;
> + unsigned int sel;
> + unsigned int ratio;
> +
> + /*
> + * CLK_SRC_PERIC0
> + * UART0_SEL [3:0]
> + * UART1_SEL [7:4]
> + * UART2_SEL [8:11]
> + * UART3_SEL [12:15]
> + * UART4_SEL [16:19]
> + * UART5_SEL [23:20]
> + */
> + sel = readl(&clk->src_peric0);
> + sel = (sel >> ((dev_index * 4) + 4)) & 0x7;
> +
> + if (sel == 0x3)
> + sclk = get_pll_clk(MPLL);
> + else if (sel == 0x6)
> + sclk = get_pll_clk(EPLL);
> + else if (sel == 0x7)
> + sclk = get_pll_clk(RPLL);
> + else
> + return 0;
> +
> + /*
> + * CLK_DIV_PERIC0
> + * UART0_RATIO [3:0]
> + * UART1_RATIO [7:4]
> + * UART2_RATIO [8:11]
> + * UART3_RATIO [12:15]
> + * UART4_RATIO [16:19]
> + * UART5_RATIO [23:20]
> + */
> + ratio = readl(&clk->div_peric0);
> + ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf;
> +
> + uclk = sclk / (ratio + 1);
> +
> + return uclk;
> +}
> +
> static unsigned long exynos4_get_mmc_clk(int dev_index)
> {
> struct exynos4_clock *clk =
> @@ -718,6 +823,34 @@ static unsigned long exynos5_get_mmc_clk(int
> dev_index)
> return uclk;
> }
>
> +static unsigned long exynos5420_get_mmc_clk(int dev_index)
> +{
> + struct exynos5420_clock *clk =
> + (struct exynos5420_clock *)samsung_get_base_clock();
> + unsigned long uclk, sclk;
> + unsigned int sel, ratio;
> + int shift = 0;
> +
> + sel = readl(&clk->src_fsys);
> + sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
> +
> + if (sel == 0x3)
> + sclk = get_pll_clk(MPLL);
> + else if (sel == 0x6)
> + sclk = get_pll_clk(EPLL);
> + else
> + return 0;
> +
> + ratio = readl(&clk->div_fsys1);
> +
> + shift = dev_index * 10;
> +
> + ratio = (ratio >> shift) & 0x3ff;
> + uclk = (sclk / (ratio + 1));
> +
> + return uclk;
> +}
> +
> /* exynos4: set the mmc clock */
> static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
> {
> @@ -804,6 +937,23 @@ static void exynos5_set_mmc_clk(int dev_index,
> unsigned int div)
> writel(val, addr);
> }
>
> +/* exynos5: set the mmc clock */
> +static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
> +{
> + struct exynos5420_clock *clk =
> + (struct exynos5420_clock *)samsung_get_base_clock();
> + unsigned int addr;
> + unsigned int val, shift;
> +
> + addr = (unsigned int)&clk->div_fsys1;
> + shift = dev_index * 10;
> +
> + val = readl(addr);
> + val &= ~(0x3ff << shift);
> + val |= (div & 0x3ff) << shift;
> + writel(val, addr);
> +}
> +
> /* get_lcd_clk: return lcd clock frequency */
> static unsigned long exynos4_get_lcd_clk(void)
> {
> @@ -1324,6 +1474,84 @@ static int exynos5_set_spi_clk(enum periph_id
> periph_id,
> return 0;
> }
>
> +static int exynos5420_set_spi_clk(enum periph_id periph_id,
> + unsigned int rate)
> +{
> + struct exynos5420_clock *clk =
> + (struct exynos5420_clock *)samsung_get_base_clock();
> + int main;
> + unsigned int fine, val;
> + unsigned shift, pre_shift;
> + unsigned div_mask = 0xf, pre_div_mask = 0xff;
> +
> + main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
> + if (main < 0) {
> + debug("%s: Cannot set clock rate for periph %d",
> + __func__, periph_id);
> + return -1;
> + }
> + main = main - 1;
> + fine = fine - 1;
> +
> + switch (periph_id) {
> + case PERIPH_ID_SPI0:
> + val = readl(&clk->div_peric1);
> + val &= ~(div_mask << 20);
> + val |= (main << 20);
> + writel(val, &clk->div_peric1);
> +
> + val = readl(&clk->div_peric4);
> + val &= ~(pre_div_mask << 8);
> + val |= (fine << 8);
> + writel(val, &clk->div_peric4);
> + break;
> + case PERIPH_ID_SPI1:
> + val = readl(&clk->div_peric1);
> + val &= ~(div_mask << 24);
> + val |= (main << 24);
> + writel(val, &clk->div_peric1);
> +
> + val = readl(&clk->div_peric4);
> + val &= ~(pre_div_mask << 16);
> + val |= (fine << 16);
> + writel(val, &clk->div_peric4);
> + break;
> + case PERIPH_ID_SPI2:
> + val = readl(&clk->div_peric1);
> + val &= ~(div_mask << 28);
> + val |= (main << 28);
> + writel(val, &clk->div_peric1);
> +
> + val = readl(&clk->div_peric4);
> + val &= ~(pre_div_mask << 24);
> + val |= (fine << 24);
> + writel(val, &clk->div_peric4);
> + break;
>
I think we can use same code for SPI0/1/2.
> + case PERIPH_ID_SPI3:
> + shift = 16;
> + pre_shift = 0;
> + clrsetbits_le32(&clk->div_isp1, div_mask << shift,
> + (main & div_mask) << shift);
> + clrsetbits_le32(&clk->div_isp1, pre_div_mask << pre_shift,
> + (fine & pre_div_mask) << pre_shift);
> + break;
> + case PERIPH_ID_SPI4:
> + shift = 20;
> + pre_shift = 8;
> + clrsetbits_le32(&clk->div_isp1, div_mask << shift,
> + (main & div_mask) << shift);
> + clrsetbits_le32(&clk->div_isp1, pre_div_mask << pre_shift,
> + (fine & pre_div_mask) << pre_shift);
> + break;
> + default:
> + debug("%s: Unsupported peripheral ID %d\n", __func__,
> + periph_id);
> + return -1;
> + }
> +
> + return 0;
> +}
> +
> static unsigned long exynos4_get_i2c_clk(void)
> {
> struct exynos4_clock *clk =
> @@ -1341,9 +1569,11 @@ static unsigned long exynos4_get_i2c_clk(void)
>
> unsigned long get_pll_clk(int pllreg)
> {
> - if (cpu_is_exynos5())
> + if (cpu_is_exynos5()) {
> + if (proid_is_exynos5420())
> + return exynos5420_get_pll_clk(pllreg);
> return exynos5_get_pll_clk(pllreg);
> - else {
> + } else {
> if (proid_is_exynos4412())
> return exynos4x12_get_pll_clk(pllreg);
> return exynos4_get_pll_clk(pllreg);
> @@ -1375,9 +1605,11 @@ unsigned long get_i2c_clk(void)
>
> unsigned long get_pwm_clk(void)
> {
> - if (cpu_is_exynos5())
> + if (cpu_is_exynos5()) {
> + if (proid_is_exynos5420())
> + return exynos5420_get_pwm_clk();
> return clock_get_periph_rate(PERIPH_ID_PWM0);
> - else {
> + } else {
> if (proid_is_exynos4412())
> return exynos4x12_get_pwm_clk();
> return exynos4_get_pwm_clk();
> @@ -1386,9 +1618,11 @@ unsigned long get_pwm_clk(void)
>
> unsigned long get_uart_clk(int dev_index)
> {
> - if (cpu_is_exynos5())
> + if (cpu_is_exynos5()) {
> + if (proid_is_exynos5420())
> + return exynos5420_get_uart_clk(dev_index);
> return exynos5_get_uart_clk(dev_index);
> - else {
> + } else {
> if (proid_is_exynos4412())
> return exynos4x12_get_uart_clk(dev_index);
> return exynos4_get_uart_clk(dev_index);
> @@ -1397,17 +1631,22 @@ unsigned long get_uart_clk(int dev_index)
>
> unsigned long get_mmc_clk(int dev_index)
> {
> - if (cpu_is_exynos5())
> + if (cpu_is_exynos5()) {
> + if (proid_is_exynos5420())
> + return exynos5420_get_mmc_clk(dev_index);
> return exynos5_get_mmc_clk(dev_index);
> - else
> + } else {
> return exynos4_get_mmc_clk(dev_index);
> + }
> }
>
> void set_mmc_clk(int dev_index, unsigned int div)
> {
> - if (cpu_is_exynos5())
> + if (cpu_is_exynos5()) {
> + if (proid_is_exynos5420())
> + return exynos5420_set_mmc_clk(dev_index, div);
> exynos5_set_mmc_clk(dev_index, div);
> - else {
> + } else {
> if (proid_is_exynos4412())
> exynos4x12_set_mmc_clk(dev_index, div);
> exynos4_set_mmc_clk(dev_index, div);
> @@ -1438,10 +1677,13 @@ void set_mipi_clk(void)
>
> int set_spi_clk(int periph_id, unsigned int rate)
> {
> - if (cpu_is_exynos5())
> + if (cpu_is_exynos5()) {
> + if (proid_is_exynos5420())
> + return exynos5420_set_spi_clk(periph_id, rate);
> return exynos5_set_spi_clk(periph_id, rate);
> - else
> + } else {
> return 0;
> + }
> }
>
> int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,
> diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h
> b/arch/arm/cpu/armv7/exynos/clock_init.h
> index c28ff3a..a875d0b 100644
> --- a/arch/arm/cpu/armv7/exynos/clock_init.h
> +++ b/arch/arm/cpu/armv7/exynos/clock_init.h
> @@ -10,7 +10,11 @@
> #define __EXYNOS_CLOCK_INIT_H
>
> enum {
> +#ifdef CONFIG_EXYNOS5420
> + MEM_TIMINGS_MSR_COUNT = 5,
> +#else
> MEM_TIMINGS_MSR_COUNT = 4,
> +#endif
> };
>
> /* These are the ratio's for configuring ARM clock */
> @@ -59,6 +63,18 @@ struct mem_timings {
> unsigned bpll_mdiv;
> unsigned bpll_pdiv;
> unsigned bpll_sdiv;
> + unsigned kpll_mdiv;
> + unsigned kpll_pdiv;
> + unsigned kpll_sdiv;
> + unsigned dpll_mdiv;
> + unsigned dpll_pdiv;
> + unsigned dpll_sdiv;
> + unsigned ipll_mdiv;
> + unsigned ipll_pdiv;
> + unsigned ipll_sdiv;
> + unsigned spll_mdiv;
> + unsigned spll_pdiv;
> + unsigned spll_sdiv;
> unsigned pclk_cdrex_ratio;
> unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
>
> @@ -115,6 +131,7 @@ struct mem_timings {
> uint8_t send_zq_init; /* 1 to send this command */
> unsigned impedance; /* drive strength impedeance */
> uint8_t gate_leveling_enable; /* check gate leveling is enabled
> */
> + uint8_t read_leveling_enable; /* check h/w read leveling is
> enabled */
> };
>
> /**
> diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
> b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
> index a24c2f3..e7f1496 100644
> --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
> +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
> @@ -24,6 +24,24 @@
> DECLARE_GLOBAL_DATA_PTR;
>
> struct arm_clk_ratios arm_clk_ratios[] = {
> +#ifdef CONFIG_EXYNOS5420
> + {
> + .arm_freq_mhz = 900,
> +
> + .apll_mdiv = 0x96,
> + .apll_pdiv = 0x2,
> + .apll_sdiv = 0x1,
> +
> + .arm2_ratio = 0x0,
> + .apll_ratio = 0x3,
> + .pclk_dbg_ratio = 0x6,
> + .atb_ratio = 0x6,
> + .periph_ratio = 0x7,
> + .acp_ratio = 0x0,
> + .cpud_ratio = 0x2,
> + .arm_ratio = 0x0,
> + }
> +#else
> {
> .arm_freq_mhz = 600,
>
> @@ -115,8 +133,133 @@ struct arm_clk_ratios arm_clk_ratios[] = {
> .cpud_ratio = 0x3,
> .arm_ratio = 0x0,
> }
> +#endif
> };
> +
> struct mem_timings mem_timings[] = {
> +#ifdef CONFIG_EXYNOS5420
> + {
> + .mem_manuf = MEM_MANUF_SAMSUNG,
> + .mem_type = DDR_MODE_DDR3,
> + .frequency_mhz = 800,
> +
> + /* MPLL @800MHz*/
> + .mpll_mdiv = 0xc8,
> + .mpll_pdiv = 0x3,
> + .mpll_sdiv = 0x1,
> + /* CPLL @666MHz */
> + .cpll_mdiv = 0xde,
> + .cpll_pdiv = 0x4,
> + .cpll_sdiv = 0x1,
> + /* EPLL @600MHz */
> + .epll_mdiv = 0x64,
> + .epll_pdiv = 0x2,
> + .epll_sdiv = 0x1,
> + /* VPLL @430MHz */
> + .vpll_mdiv = 0xd7,
> + .vpll_pdiv = 0x3,
> + .vpll_sdiv = 0x2,
> + /* BPLL @800MHz */
> + .bpll_mdiv = 0xc8,
> + .bpll_pdiv = 0x3,
> + .bpll_sdiv = 0x1,
> + /* KPLL @600MHz */
> + .kpll_mdiv = 0x190,
> + .kpll_pdiv = 0x4,
> + .kpll_sdiv = 0x2,
> + /* DPLL @600MHz */
> + .dpll_mdiv = 0x190,
> + .dpll_pdiv = 0x4,
> + .dpll_sdiv = 0x2,
> + /* IPLL @370MHz */
> + .ipll_mdiv = 0xb9,
> + .ipll_pdiv = 0x3,
> + .ipll_sdiv = 0x2,
> + /* SPLL @400MHz */
> + .spll_mdiv = 0xc8,
> + .spll_pdiv = 0x3,
> + .spll_sdiv = 0x2,
> +
> + .direct_cmd_msr = {
> + 0x00020018, 0x00030000, 0x00010046, 0x00000d70,
> + 0x00000c70
> + },
> + .timing_ref = 0x000000bb,
> + .timing_row = 0x6836650f,
> + .timing_data = 0x3630580b,
> + .timing_power = 0x41000a26,
> + .phy0_dqs = 0x08080808,
> + .phy1_dqs = 0x08080808,
> + .phy0_dq = 0x08080808,
> + .phy1_dq = 0x08080808,
> + .phy0_tFS = 0x8,
> + .phy1_tFS = 0x8,
> + .phy0_pulld_dqs = 0xf,
> + .phy1_pulld_dqs = 0xf,
> +
> + .lpddr3_ctrl_phy_reset = 0x1,
> + .ctrl_start_point = 0x10,
> + .ctrl_inc = 0x10,
> + .ctrl_start = 0x1,
> + .ctrl_dll_on = 0x1,
> + .ctrl_ref = 0x8,
> +
> + .ctrl_force = 0x1a,
> + .ctrl_rdlat = 0x0b,
> + .ctrl_bstlen = 0x08,
> +
> + .fp_resync = 0x8,
> + .iv_size = 0x7,
> + .dfi_init_start = 1,
> + .aref_en = 1,
> +
> + .rd_fetch = 0x3,
> +
> + .zq_mode_dds = 0x7,
> + .zq_mode_term = 0x1,
> + .zq_mode_noterm = 1,
> +
> + /*
> + * Dynamic Clock: Always Running
> + * Memory Burst length: 8
> + * Number of chips: 1
> + * Memory Bus width: 32 bit
> + * Memory Type: DDR3
> + * Additional Latancy for PLL: 0 Cycle
> + */
> + .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
> + DMC_MEMCONTROL_DPWRDN_DISABLE |
> + DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
> + DMC_MEMCONTROL_TP_DISABLE |
> + DMC_MEMCONTROL_DSREF_DISABLE |
> + DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
> + DMC_MEMCONTROL_MEM_TYPE_DDR3 |
> + DMC_MEMCONTROL_MEM_WIDTH_32BIT |
> + DMC_MEMCONTROL_NUM_CHIP_1 |
> + DMC_MEMCONTROL_BL_8 |
> + DMC_MEMCONTROL_PZQ_DISABLE |
> + DMC_MEMCONTROL_MRR_BYTE_7_0,
> + .memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
> + DMC_MEMCONFIGX_CHIP_COL_10 |
> + DMC_MEMCONFIGX_CHIP_ROW_15 |
> + DMC_MEMCONFIGX_CHIP_BANK_8,
> + .prechconfig_tp_cnt = 0xff,
> + .dpwrdn_cyc = 0xff,
> + .dsref_cyc = 0xffff,
> + .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
> + DMC_CONCONTROL_TIMEOUT_LEVEL0 |
> + DMC_CONCONTROL_RD_FETCH_DISABLE |
> + DMC_CONCONTROL_EMPTY_DISABLE |
> + DMC_CONCONTROL_AREF_EN_DISABLE |
> + DMC_CONCONTROL_IO_PD_CON_DISABLE,
> + .dmc_channels = 1,
> + .chips_per_channel = 1,
> + .chips_to_configure = 1,
> + .send_zq_init = 1,
> + .gate_leveling_enable = 1,
> + .read_leveling_enable = 0,
> + }
> +#else
> {
> .mem_manuf = MEM_MANUF_ELPIDA,
> .mem_type = DDR_MODE_DDR3,
> @@ -324,6 +467,7 @@ struct mem_timings mem_timings[] = {
> .impedance = IMP_OUTPUT_DRV_40_OHM,
> .gate_leveling_enable = 1,
> }
> +#endif
> };
>
> /**
> @@ -399,7 +543,7 @@ struct mem_timings *clock_get_mem_timings(void)
> return NULL;
> }
>
> -void system_clock_init()
> +static void exynos5250_system_clock_init(void)
> {
> struct exynos5_clock *clk =
> (struct exynos5_clock *)samsung_get_base_clock();
> @@ -436,19 +580,13 @@ void system_clock_init()
> } while ((val | MUX_BPLL_SEL_MASK) != val);
>
> /* PLL locktime */
> - writel(APLL_LOCK_VAL, &clk->apll_lock);
> -
> - writel(MPLL_LOCK_VAL, &clk->mpll_lock);
> -
> - writel(BPLL_LOCK_VAL, &clk->bpll_lock);
> -
> - writel(CPLL_LOCK_VAL, &clk->cpll_lock);
> -
> - writel(GPLL_LOCK_VAL, &clk->gpll_lock);
> -
> - writel(EPLL_LOCK_VAL, &clk->epll_lock);
> -
> - writel(VPLL_LOCK_VAL, &clk->vpll_lock);
> + writel(mem->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
> + writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
> + writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
> + writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
> + writel(mem->gpll_pdiv * PLL_X_LOCK_FACTOR, &clk->gpll_lock);
> + writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
> + writel(mem->vpll_pdiv * PLL_X_LOCK_FACTOR, &clk->vpll_lock);
>
> writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
>
> @@ -640,6 +778,192 @@ void system_clock_init()
> writel(val, &clk->div_fsys2);
> }
>
> +static void exynos5420_system_clock_init(void)
> +{
> + struct exynos5420_clock *clk =
> + (struct exynos5420_clock *)EXYNOS5_CLOCK_BASE;
> + struct mem_timings *mem;
> + struct arm_clk_ratios *arm_clk_ratio;
> + u32 val;
> +
> + mem = clock_get_mem_timings();
> + arm_clk_ratio = get_arm_ratios();
> +
> + /* PLL locktime */
> + writel(arm_clk_ratio->apll_pdiv * PLL_LOCK_FACTOR,
> &clk->apll_lock);
> + writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
> + writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
> + writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
> + writel(mem->dpll_pdiv * PLL_LOCK_FACTOR, &clk->dpll_lock);
> + writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
> + writel(mem->vpll_pdiv * PLL_LOCK_FACTOR, &clk->vpll_lock);
> + writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
> + writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
> + writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
> +
> + setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
> +
> + writel(0, &clk->src_top6);
> +
> + writel(0, &clk->src_cdrex);
> + writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
> + writel(HPM_RATIO, &clk->div_cpu1);
> + writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
> +
> + /* switch A15 clock source to OSC clock before changing APLL */
> + clrbits_le32(&clk->src_cpu, APLL_FOUT);
> +
> + /* Set APLL */
> + writel(APLL_CON1_VAL, &clk->apll_con1);
> + val = set_pll(arm_clk_ratio->apll_mdiv,
> + arm_clk_ratio->apll_pdiv,
> + arm_clk_ratio->apll_sdiv);
> + writel(val, &clk->apll_con0);
> + while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0)
> + ;
> +
> + /* now it is safe to switch to APLL */
> + setbits_le32(&clk->src_cpu, APLL_FOUT);
> +
> + writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
> + writel(CLK_DIV_KFC_VAL, &clk->div_kfc0);
> +
> + /* switch A7 clock source to OSC clock before changing KPLL */
> + clrbits_le32(&clk->src_kfc, KPLL_FOUT);
> +
> + /* Set KPLL*/
> + writel(KPLL_CON1_VAL, &clk->kpll_con1);
> + val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv);
> + writel(val, &clk->kpll_con0);
> + while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
> + ;
> +
> + /* now it is safe to switch to KPLL */
> + setbits_le32(&clk->src_kfc, KPLL_FOUT);
> +
> + /* Set MPLL */
> + writel(MPLL_CON1_VAL, &clk->mpll_con1);
> + val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
> + writel(val, &clk->mpll_con0);
> + while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0)
> + ;
> +
> + /* Set DPLL */
> + writel(DPLL_CON1_VAL, &clk->dpll_con1);
> + val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv);
> + writel(val, &clk->dpll_con0);
> + while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0)
> + ;
> +
> + /* Set EPLL */
> + writel(EPLL_CON2_VAL, &clk->epll_con2);
> + writel(EPLL_CON1_VAL, &clk->epll_con1);
> + val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
> + writel(val, &clk->epll_con0);
> + while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0)
> + ;
> +
> + /* Set CPLL */
> + writel(CPLL_CON1_VAL, &clk->cpll_con1);
> + val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
> + writel(val, &clk->cpll_con0);
> + while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0)
> + ;
> +
> + /* Set IPLL */
> + writel(IPLL_CON1_VAL, &clk->ipll_con1);
> + val = set_pll(mem->ipll_mdiv, mem->ipll_pdiv, mem->ipll_sdiv);
> + writel(val, &clk->ipll_con0);
> + while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0)
> + ;
> +
> + /* Set VPLL */
> + writel(VPLL_CON1_VAL, &clk->vpll_con1);
> + val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
> + writel(val, &clk->vpll_con0);
> + while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0)
> + ;
> +
> + /* Set BPLL */
> + writel(BPLL_CON1_VAL, &clk->bpll_con1);
> + val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
> + writel(val, &clk->bpll_con0);
> + while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0)
> + ;
> +
> + /* Set SPLL */
> + writel(SPLL_CON1_VAL, &clk->spll_con1);
> + val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv);
> + writel(val, &clk->spll_con0);
> + while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
> + ;
> +
> + writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
> + writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
> +
> + writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
> + writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
> + writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
> + writel(CLK_SRC_TOP7_VAL, &clk->src_top7);
> +
> + writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
> + writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
> + writel(CLK_DIV_TOP2_VAL, &clk->div_top2);
> +
> + writel(0, &clk->src_top10);
> + writel(0, &clk->src_top11);
> + writel(0, &clk->src_top12);
> +
> + writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
> + writel(CLK_SRC_TOP4_VAL, &clk->src_top4);
> + writel(CLK_SRC_TOP5_VAL, &clk->src_top5);
> +
> + /* DISP1 BLK CLK SELECTION */
> + writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10);
> + writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10);
> +
> + /* AUDIO BLK */
> + writel(AUDIO0_SEL_EPLL, &clk->src_mau);
> + writel(DIV_MAU_VAL, &clk->div_mau);
> +
> + /* FSYS */
> + writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
> + writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
> + writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
> + writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
> +
> + writel(CLK_SRC_ISP_VAL, &clk->src_isp);
> + writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
> + writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
> +
> + writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
> + writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
> +
> + writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
> + writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
> + writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
> + writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
> + writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4);
> +
> + writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1);
> +
> + writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
> + writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
> + writel(CLK_DIV_G2D, &clk->div_g2d);
> +
> + writel(CLK_SRC_TOP6_VAL, &clk->src_top6);
> + writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
> + writel(CLK_SRC_KFC_VAL, &clk->src_kfc);
> +}
> +
> +void system_clock_init(void)
> +{
> + if (proid_is_exynos5420())
> + exynos5420_system_clock_init();
> + else
> + exynos5250_system_clock_init();
> +}
> +
> void clock_init_dp_clock(void)
> {
> struct exynos5_clock *clk =
> diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
> b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
> index 696b386..8e05a00 100644
> --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
> +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
> @@ -12,42 +12,16 @@
> #include <config.h>
> #include <asm/arch/dmc.h>
>
> -/* APLL_CON1 */
> -#define APLL_CON1_VAL (0x00203800)
> -
> -/* MPLL_CON1 */
> -#define MPLL_CON1_VAL (0x00203800)
> -
> -/* CPLL_CON1 */
> -#define CPLL_CON1_VAL (0x00203800)
> -
> -/* GPLL_CON1 */
> -#define GPLL_CON1_VAL (0x00203800)
> -
> -/* EPLL_CON1, CON2 */
> -#define EPLL_CON1_VAL 0x00000000
> -#define EPLL_CON2_VAL 0x00000080
> -
> -/* VPLL_CON1, CON2 */
> -#define VPLL_CON1_VAL 0x00000000
> -#define VPLL_CON2_VAL 0x00000080
> +#define NOT_AVAILABLE 0
> +#define DATA_MASK 0xFFFFF
>
> -/* BPLL_CON1 */
> -#define BPLL_CON1_VAL 0x00203800
> +#define ENABLE_BIT 0x1
> +#define DISABLE_BIT 0x0
> +#define CA_SWAP_EN (1 << 0)
>
> /* Set PLL */
> #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
>
> -/* CLK_SRC_CPU */
> -/* 0 = MOUTAPLL, 1 = SCLKMPLL */
> -#define MUX_HPM_SEL 0
> -#define MUX_CPU_SEL 0
> -#define MUX_APLL_SEL 1
> -
> -#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
> - | (MUX_CPU_SEL << 16) \
> - | (MUX_APLL_SEL))
> -
> /* MEMCONTROL register bit fields */
> #define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
> #define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
> @@ -78,6 +52,7 @@
>
> /* MEMCONFIG0 register bit fields */
> #define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED (1 << 12)
> +#define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12)
> #define DMC_MEMCONFIGX_CHIP_COL_10 (3 << 8)
> #define DMC_MEMCONFIGX_CHIP_ROW_14 (2 << 4)
> #define DMC_MEMCONFIGX_CHIP_ROW_15 (3 << 4)
> @@ -90,6 +65,16 @@
> DMC_MEMBASECONFIGX_CHIP_MASK(0x780) \
> )
>
> +/* As we use channel interleaving, therefore value of the base address
> + * register must be set as half of the bus base address
> + * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
> + * we need to set half 0x10 to the membaseconfigx registers
> + * see exynos5420 UM section 17.17.3.21 for more
> + */
>
please fix this multiline comment.
> +#define DMC_CHIP_BASE_0 0x10
> +#define DMC_CHIP_BASE_1 0x50
> +#define DMC_CHIP_MASK 0x7C0
> +
> #define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
> #define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
>
> @@ -113,29 +98,24 @@
>
> /* COJCONTROL register bit fields */
> #define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
> +#define DMC_CONCONTROL_IO_PD_CON_ENABLE (1 << 3)
> #define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
> +#define DMC_CONCONTROL_AREF_EN_ENABLE (1 << 5)
> #define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8)
> #define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8)
> #define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
> #define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
> #define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
>
> -/* CLK_DIV_CPU0_VAL */
> -#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \
> - | (APLL_RATIO << 24) \
> - | (PCLK_DBG_RATIO << 20) \
> - | (ATB_RATIO << 16) \
> - | (PERIPH_RATIO << 12) \
> - | (ACP_RATIO << 8) \
> - | (CPUD_RATIO << 4) \
> - | (ARM_RATIO))
> +#define DMC_CONCONTROL_VAL 0x1FFF2101
>
> +#define DREX_CONCONTROL_VAL DMC_CONCONTROL_VAL \
> + | DMC_CONCONTROL_AREF_EN_ENABLE \
> + | DMC_CONCONTROL_IO_PD_CON_ENABLE
>
> -/* CLK_FSYS */
> -#define CLK_SRC_FSYS0_VAL 0x66666
> -#define CLK_DIV_FSYS0_VAL 0x0BB00000
> +#define DMC_CONCONTROL_IO_PD_CON(x) (x << 6)
>
> -/* CLK_DIV_CPU1 */
> +/* CLK_DIV_CPU1 */
> #define HPM_RATIO 0x2
> #define COPY_RATIO 0x0
>
> @@ -164,10 +144,370 @@
> /* CLK_DIV_SYSLFT */
> #define CLK_DIV_SYSLFT_VAL 0x00000311
>
> +#define MUX_APLL_SEL_MASK (1 << 0)
> +#define MUX_MPLL_SEL_MASK (1 << 8)
> +#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
> +#define MUX_CPLL_SEL_MASK (1 << 8)
> +#define MUX_EPLL_SEL_MASK (1 << 12)
> +#define MUX_VPLL_SEL_MASK (1 << 16)
> +#define MUX_GPLL_SEL_MASK (1 << 28)
> +#define MUX_BPLL_SEL_MASK (1 << 0)
> +#define MUX_HPM_SEL_MASK (1 << 20)
> +#define HPM_SEL_SCLK_MPLL (1 << 21)
> +#define PLL_LOCKED (1 << 29)
> +#define APLL_CON0_LOCKED (1 << 29)
> +#define MPLL_CON0_LOCKED (1 << 29)
> +#define BPLL_CON0_LOCKED (1 << 29)
> +#define CPLL_CON0_LOCKED (1 << 29)
> +#define EPLL_CON0_LOCKED (1 << 29)
> +#define GPLL_CON0_LOCKED (1 << 29)
> +#define VPLL_CON0_LOCKED (1 << 29)
> +#define CLK_REG_DISABLE 0x0
> +#define TOP2_VAL 0x0110000
> +
> +/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
> +#define SPI0_ISP_SEL 6
> +#define SPI1_ISP_SEL 6
> +#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
> + | (SPI0_ISP_SEL << 0)
> +
> +/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
> +#define SPI0_ISP_RATIO 0xf
> +#define SPI1_ISP_RATIO 0xf
> +#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
> + | (SPI0_ISP_RATIO << 0)
> +
> +/* CLK_DIV_FSYS2 */
> +#define MMC2_RATIO_MASK 0xf
> +#define MMC2_RATIO_VAL 0x3
> +#define MMC2_RATIO_OFFSET 0
> +
> +#define MMC2_PRE_RATIO_MASK 0xff
> +#define MMC2_PRE_RATIO_VAL 0x9
> +#define MMC2_PRE_RATIO_OFFSET 8
> +
> +#define MMC3_RATIO_MASK 0xf
> +#define MMC3_RATIO_VAL 0x1
> +#define MMC3_RATIO_OFFSET 16
> +
> +#define MMC3_PRE_RATIO_MASK 0xff
> +#define MMC3_PRE_RATIO_VAL 0x0
> +#define MMC3_PRE_RATIO_OFFSET 24
> +
> +/* CLK_SRC_LEX */
> +#define CLK_SRC_LEX_VAL 0x0
> +
> +/* CLK_DIV_LEX */
> +#define CLK_DIV_LEX_VAL 0x10
> +
> +/* CLK_DIV_R0X */
> +#define CLK_DIV_R0X_VAL 0x10
> +
> +/* CLK_DIV_L0X */
> +#define CLK_DIV_R1X_VAL 0x10
> +
> +/* CLK_DIV_ISP2 */
> +#define CLK_DIV_ISP2_VAL 0x1
> +
> +/* CLK_SRC_KFC */
> +#define SRC_KFC_HPM_SEL (1 << 15)
> +
> +/* CLK_SRC_KFC */
> +#define CLK_SRC_KFC_VAL 0x00008001
> +
> +/* CLK_DIV_KFC */
> +#define CLK_DIV_KFC_VAL 0x03300110
> +
> +/* CLK_DIV2_RATIO */
> +#define CLK_DIV2_RATIO 0x10111150
> +
> +/* CLK_DIV4_RATIO */
> +#define CLK_DIV4_RATIO 0x00000003
> +
> +/* CLK_DIV_G2D */
> +#define CLK_DIV_G2D 0x00000010
> +
> +/*
> + * DIV_DISP1_0
> + * For DP, divisor should be 2
> + */
> +#define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
> +
> +/* CLK_GATE_IP_DISP1 */
> +#define CLK_GATE_DP1_ALLOW (1 << 4)
> +
> +/* AUDIO CLK SEL */
> +#define AUDIO0_SEL_EPLL (0x6 << 28)
> +#define AUDIO0_RATIO 0x5
> +#define PCM0_RATIO 0x3
> +#define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20)
> +
>
please remove blank line.
> +
> +/* CLK_SRC_CDREX */
> +#define MUX_MCLK_CDR_MSPLL (1 << 4)
> +#define MUX_BPLL_SEL_FOUTBPLL (1 << 0)
> +#define BPLL_SEL_MASK 0x7
> +#define FOUTBPLL 2
> +
> +#define DDR3PHY_CTRL_PHY_RESET (1 << 0)
> +#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
> +
> +#define PHY_CON0_RESET_VAL 0x17020a40
> +#define P0_CMD_EN (1 << 14)
> +#define BYTE_RDLVL_EN (1 << 13)
> +#define CTRL_SHGATE (1 << 8)
> +
> +#define PHY_CON1_RESET_VAL 0x09210100
> +#define RDLVL_PASS_ADJ_VAL 0x6
> +#define RDLVL_PASS_ADJ_OFFSET 16
> +#define CTRL_GATEDURADJ_MASK (0xf << 20)
> +#define READ_LEVELLING_DDR3 0x0100
> +
> +#define PHY_CON2_RESET_VAL 0x00010004
> +#define INIT_DESKEW_EN (1 << 6)
> +#define DLL_DESKEW_EN (1 << 12)
> +#define RDLVL_GATE_EN (1 << 24)
> +#define RDLVL_EN (1 << 25)
> +#define RDLVL_INCR_ADJ (0x1 << 16)
> +
> +/* DREX_PAUSE */
> +#define DREX_PAUSE_EN (1 << 0)
> +
> +#define BYPASS_EN (1 << 22)
> +
> +/********-----MEMMORY VAL----------***/
>
/* MEMORY VAL */
> +#define PHY_CON0_VAL 0x17021A00
> +
> +#define PHY_CON12_RESET_VAL 0x10100070
> +#define PHY_CON12_VAL 0x10107F50
> +#define CTRL_START (1 << 6)
> +#define CTRL_DLL_ON (1 << 5)
> +#define CTRL_FORCE_MASK (0x7F << 8)
> +#define CTRL_LOCK_COARSE_MASK (0x7F << 10)
> +
>
please remove blank line.
> +
> +#define CTRL_OFFSETD_RESET_VAL 0x8
> +#define CTRL_OFFSETD_VAL 0x7F
> +
> +#define CTRL_OFFSETR0 0x7F
> +#define CTRL_OFFSETR1 0x7F
> +#define CTRL_OFFSETR2 0x7F
> +#define CTRL_OFFSETR3 0x7F
> +#define PHY_CON4_VAL (CTRL_OFFSETR0 << 0 | \
> + CTRL_OFFSETR1 << 8 | \
> + CTRL_OFFSETR2 << 16 | \
> + CTRL_OFFSETR3 << 24)
> +#define PHY_CON4_RESET_VAL 0x08080808
> +
> +#define CTRL_OFFSETW0 0x7F
> +#define CTRL_OFFSETW1 0x7F
> +#define CTRL_OFFSETW2 0x7F
> +#define CTRL_OFFSETW3 0x7F
> +#define PHY_CON6_VAL (CTRL_OFFSETW0 << 0 | \
> + CTRL_OFFSETW1 << 8 | \
> + CTRL_OFFSETW2 << 16 | \
> + CTRL_OFFSETW3 << 24)
> +#define PHY_CON6_RESET_VAL 0x08080808
> +
> +#define PHY_CON14_RESET_VAL 0x001F0000
> +#define CTRL_PULLD_DQS 0xF
> +#define CTRL_PULLD_DQS_OFFSET 0
> +
> +/*ZQ Configurations */
>
please add space before ZQ.
> +#define PHY_CON16_RESET_VAL 0x08000304
> +
> +#define ZQ_CLK_EN (1 << 27)
> +#define ZQ_CLK_DIV_EN (1 << 18)
> +#define ZQ_MANUAL_STR (1 << 1)
> +#define ZQ_DONE (1 << 0)
> +#define ZQ_MODE_DDS_OFFSET 24
> +
> +#define CTRL_RDLVL_GATE_ENABLE 1
> +#define CTRL_RDLVL_GATE_DISABLE 0
> +#define CTRL_RDLVL_DATA_ENABLE 2
> +
> +/* Direct Command */
> +#define DIRECT_CMD_NOP 0x07000000
> +#define DIRECT_CMD_PALL 0x01000000
> +#define DIRECT_CMD_ZQINIT 0x0a000000
> +#define DIRECT_CMD_CHANNEL_SHIFT 28
> +#define DIRECT_CMD_CHIP_SHIFT 20
> +#define DIRECT_CMD_BANK_SHIFT 16
> +#define DIRECT_CMD_REFA (5 << 24)
> +#define DIRECT_CMD_MRS1 0x71C00
> +#define DIRECT_CMD_MRS2 0x10BFC
> +#define DIRECT_CMD_MRS3 0x0050C
> +#define DIRECT_CMD_MRS4 0x00868
> +#define DIRECT_CMD_MRS5 0x00C04
> +
> +/* Drive Strength */
> +#define IMPEDANCE_48_OHM 4
> +#define IMPEDANCE_40_OHM 5
> +#define IMPEDANCE_34_OHM 6
> +#define IMPEDANCE_30_OHM 7
> +#define PHY_CON39_VAL_48_OHM 0x09240924
> +#define PHY_CON39_VAL_40_OHM 0x0B6D0B6D
> +#define PHY_CON39_VAL_34_OHM 0x0DB60DB6
> +#define PHY_CON39_VAL_30_OHM 0x0FFF0FFF
> +
>
please remove blank line.
> +
> +#define CTRL_BSTLEN_OFFSET 8
> +#define CTRL_RDLAT_OFFSET 0
> +
> +#define CMD_DEFAULT_LPDDR3 0xF
> +#define CMD_DEFUALT_OFFSET 0
> +#define T_WRDATA_EN 0x7
> +#define T_WRDATA_EN_DDR3 0x8
> +#define T_WRDATA_EN_OFFSET 16
> +#define T_WRDATA_EN_MASK 0x1f
> +
> +#define PHY_CON31_VAL 0x0C183060
> +#define PHY_CON32_VAL 0x60C18306
> +#define PHY_CON33_VAL 0x00000030
> +
> +#define PHY_CON31_RESET_VAL 0x0
> +#define PHY_CON32_RESET_VAL 0x0
> +#define PHY_CON33_RESET_VAL 0x0
> +
> +#define SL_DLL_DYN_CON_EN (1 << 1)
> +#define FP_RESYNC (1 << 3)
> +#define CTRL_START (1 << 6)
> +
> +#define DMC_AREF_EN (1 << 5)
> +#define DMC_CONCONTROL_EMPTY (1 << 8)
> +#define DFI_INIT_START (1 << 28)
> +
> +#define DMC_MEMCONTROL_VAL 0x00312700
> +#define CLK_STOP_EN (1 << 0)
> +#define DPWRDN_EN (1 << 1)
> +#define DSREF_EN (1 << 5)
> +
> +#define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0
> +#define MEMBASECONFIG_CHIP_MASK_OFFSET 0
> +#define MEMBASECONFIG0_CHIP_BASE_VAL 0x20
> +#define MEMBASECONFIG1_CHIP_BASE_VAL 0x40
> +#define CHIP_BASE_OFFSET 16
> +
> +#define MEMCONFIG_VAL 0x1323
> +#define PRECHCONFIG_DEFAULT_VAL 0xFF000000
> +#define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF
> +
> +#define TIMINGAREF_VAL 0x5d
> +#define TIMINGROW_VAL 0x345A8692
> +#define TIMINGDATA_VAL 0x3630065C
> +#define TIMINGPOWER_VAL 0x50380336
> +#define DFI_INIT_COMPLETE (1 << 3)
> +
> +#define BRBRSVCONTROL_VAL 0x00000033
> +#define BRBRSVCONFIG_VAL 0x88778877
> +
> +/* Clock Gating Control (CGCONTROL) register */
> +#define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */
> +#define SCG_CG_EN (1 << 2) /* Scheduler clock gating */
> +#define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock
> gating */
> +#define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock
> gating */
> +#define DMC_INTERNAL_CG (MEMIF_CG_EN | SCG_CG_EN | \
> + BUSIF_WR_CG_EN | BUSIF_RD_CG_EN)
> +
> +/* DMC PHY Control0 register */
> +#define PHY_CONTROL0_RESET_VAL 0x0
> +#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
> +#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
> +#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating
> signal */
> +#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
> +
> +/* Driver strength for CK, CKE, CS & CA */
> +#define IMP_OUTPUT_DRV_40_OHM 0x5
> +#define IMP_OUTPUT_DRV_30_OHM 0x7
> +#define DA_3_DS_OFFSET 25
> +#define DA_2_DS_OFFSET 22
> +#define DA_1_DS_OFFSET 19
> +#define DA_0_DS_OFFSET 16
> +#define CA_CK_DRVR_DS_OFFSET 9
> +#define CA_CKE_DRVR_DS_OFFSET 6
> +#define CA_CS_DRVR_DS_OFFSET 3
> +#define CA_ADR_DRVR_DS_OFFSET 0
> +
> +#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
> +#define PHY_CON42_CTRL_RDLAT_SHIFT 0
> +
> +/*
> + * Definitions that differ with SoC's.
> + * Below is the part defining macros for smdk5250.
> + * Else part introduces macros for smdk5420.
> + */
> +#ifndef CONFIG_SMDK5420
> +
> +/* APLL_CON1 */
> +#define APLL_CON1_VAL (0x00203800)
> +
> +/* MPLL_CON1 */
> +#define MPLL_CON1_VAL (0x00203800)
> +
> +/* CPLL_CON1 */
> +#define CPLL_CON1_VAL (0x00203800)
> +
> +/* DPLL_CON1 */
> +#define DPLL_CON1_VAL (NOT_AVAILABLE)
> +
> +/* GPLL_CON1 */
> +#define GPLL_CON1_VAL (0x00203800)
> +
> +/* EPLL_CON1, CON2 */
> +#define EPLL_CON1_VAL 0x00000000
> +#define EPLL_CON2_VAL 0x00000080
> +
> +/* VPLL_CON1, CON2 */
> +#define VPLL_CON1_VAL 0x00000000
> +#define VPLL_CON2_VAL 0x00000080
> +
> +/* RPLL_CON1, CON2 */
> +#define RPLL_CON1_VAL NOT_AVAILABLE
> +#define RPLL_CON2_VAL NOT_AVAILABLE
> +
> +/* BPLL_CON1 */
> +#define BPLL_CON1_VAL 0x00203800
> +
> +/* SPLL_CON1 */
> +#define SPLL_CON1_VAL NOT_AVAILABLE
> +
> +/* IPLL_CON1 */
> +#define IPLL_CON1_VAL NOT_AVAILABLE
> +
> +/* KPLL_CON1 */
> +#define KPLL_CON1_VAL NOT_AVAILABLE
> +
> +/* CLK_SRC_ISP */
> +#define CLK_SRC_ISP_VAL NOT_AVAILABLE
> +#define CLK_DIV_ISP0_VAL 0x31
> +#define CLK_DIV_ISP1_VAL 0x0
> +
> +/* CLK_FSYS */
> +#define CLK_SRC_FSYS0_VAL 0x66666
> +#define CLK_DIV_FSYS0_VAL 0x0BB00000
> +#define CLK_DIV_FSYS1_VAL NOT_AVAILABLE
> +#define CLK_DIV_FSYS2_VAL NOT_AVAILABLE
> +
> +/* CLK_SRC_CPU */
> +/* 0 = MOUTAPLL, 1 = SCLKMPLL */
> +#define MUX_HPM_SEL 0
> +#define MUX_CPU_SEL 0
> +#define MUX_APLL_SEL 1
> +
> +#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
> + | (MUX_CPU_SEL << 16) \
> + | (MUX_APLL_SEL))
> +
> /* CLK_SRC_CDREX */
> #define CLK_SRC_CDREX_VAL 0x1
>
> /* CLK_DIV_CDREX */
> +#define CLK_DIV_CDREX0_VAL NOT_AVAILABLE
> +#define CLK_DIV_CDREX1_VAL NOT_AVAILABLE
> +
> +/* CLK_DIV_CPU0_VAL */
> +#define CLK_DIV_CPU0_VAL NOT_AVAILABLE
> +
> #define MCLK_CDREX2_RATIO 0x0
> #define ACLK_EFCON_RATIO 0x1
> #define MCLK_DPHY_RATIO 0x1
> @@ -247,6 +587,11 @@
> | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
> | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
>
> +#define CLK_SRC_TOP4_VAL NOT_AVAILABLE
> +#define CLK_SRC_TOP5_VAL NOT_AVAILABLE
> +#define CLK_SRC_TOP6_VAL NOT_AVAILABLE
> +#define CLK_SRC_TOP7_VAL NOT_AVAILABLE
> +
> /* CLK_DIV_TOP0 */
> #define ACLK_300_DISP1_RATIO 0x2
> #define ACLK_400_G3D_RATIO 0x0
> @@ -279,40 +624,11 @@
> | (ACLK_400_IOP_RATIO << 16) \
> | (ACLK_300_GSCL_RATIO << 12))
>
> -/* APLL_LOCK */
> -#define APLL_LOCK_VAL (0x546)
> -/* MPLL_LOCK */
> -#define MPLL_LOCK_VAL (0x546)
> -/* CPLL_LOCK */
> -#define CPLL_LOCK_VAL (0x546)
> -/* GPLL_LOCK */
> -#define GPLL_LOCK_VAL (0x546)
> -/* EPLL_LOCK */
> -#define EPLL_LOCK_VAL (0x3A98)
> -/* VPLL_LOCK */
> -#define VPLL_LOCK_VAL (0x3A98)
> -/* BPLL_LOCK */
> -#define BPLL_LOCK_VAL (0x546)
> +#define CLK_DIV_TOP2_VAL NOT_AVAILABLE
>
> -#define MUX_APLL_SEL_MASK (1 << 0)
> -#define MUX_MPLL_SEL_MASK (1 << 8)
> -#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
> -#define MUX_CPLL_SEL_MASK (1 << 8)
> -#define MUX_EPLL_SEL_MASK (1 << 12)
> -#define MUX_VPLL_SEL_MASK (1 << 16)
> -#define MUX_GPLL_SEL_MASK (1 << 28)
> -#define MUX_BPLL_SEL_MASK (1 << 0)
> -#define MUX_HPM_SEL_MASK (1 << 20)
> -#define HPM_SEL_SCLK_MPLL (1 << 21)
> -#define APLL_CON0_LOCKED (1 << 29)
> -#define MPLL_CON0_LOCKED (1 << 29)
> -#define BPLL_CON0_LOCKED (1 << 29)
> -#define CPLL_CON0_LOCKED (1 << 29)
> -#define EPLL_CON0_LOCKED (1 << 29)
> -#define GPLL_CON0_LOCKED (1 << 29)
> -#define VPLL_CON0_LOCKED (1 << 29)
> -#define CLK_REG_DISABLE 0x0
> -#define TOP2_VAL 0x0110000
> +/* PLL Lock Value Factor */
> +#define PLL_LOCK_FACTOR 250
> +#define PLL_X_LOCK_FACTOR 3000
>
> /* CLK_SRC_PERIC0 */
> #define PWM_SEL 6
> @@ -336,18 +652,6 @@
> | (SPI1_SEL << 20) \
> | (SPI0_SEL << 16))
>
> -/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
> -#define SPI0_ISP_SEL 6
> -#define SPI1_ISP_SEL 6
> -#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
> - | (SPI0_ISP_SEL << 0)
> -
> -/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
> -#define SPI0_ISP_RATIO 0xf
> -#define SPI1_ISP_RATIO 0xf
> -#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
> - | (SPI0_ISP_RATIO << 0)
> -
> /* CLK_DIV_PERIL0 */
> #define UART5_RATIO 7
> #define UART4_RATIO 7
> @@ -380,105 +684,200 @@
> #define PWM_RATIO 8
> #define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
>
> -/* CLK_DIV_FSYS2 */
> -#define MMC2_RATIO_MASK 0xf
> -#define MMC2_RATIO_VAL 0x3
> -#define MMC2_RATIO_OFFSET 0
>
> -#define MMC2_PRE_RATIO_MASK 0xff
> -#define MMC2_PRE_RATIO_VAL 0x9
> -#define MMC2_PRE_RATIO_OFFSET 8
> +/* CLK_DIV_PERIC4 */
> +#define CLK_DIV_PERIC4_VAL NOT_AVAILABLE
>
> -#define MMC3_RATIO_MASK 0xf
> -#define MMC3_RATIO_VAL 0x1
> -#define MMC3_RATIO_OFFSET 16
> +/* CLK_SRC_DISP1_0 */
> +#define CLK_SRC_DISP1_0_VAL 0x6
> +#define CLK_DIV_DISP1_0_VAL NOT_AVAILABLE
>
> -#define MMC3_PRE_RATIO_MASK 0xff
> -#define MMC3_PRE_RATIO_VAL 0x0
> -#define MMC3_PRE_RATIO_OFFSET 24
> +#define APLL_FOUT (1 << 0)
> +#define KPLL_FOUT NOT_AVAILABLE
>
> -/* CLK_SRC_LEX */
> -#define CLK_SRC_LEX_VAL 0x0
> +#define CLK_DIV_CPERI1_VAL NOT_AVAILABLE
>
> -/* CLK_DIV_LEX */
> -#define CLK_DIV_LEX_VAL 0x10
> +#else
>
> -/* CLK_DIV_R0X */
> -#define CLK_DIV_R0X_VAL 0x10
> +/* APLL_CON1 */
> +#define APLL_CON1_VAL (0x0020F300)
>
> -/* CLK_DIV_L0X */
> -#define CLK_DIV_R1X_VAL 0x10
> +/* MPLL_CON1 */
> +#define MPLL_CON1_VAL (0x0020F300)
>
> -/* CLK_DIV_ISP0 */
> -#define CLK_DIV_ISP0_VAL 0x31
>
> -/* CLK_DIV_ISP1 */
> -#define CLK_DIV_ISP1_VAL 0x0
> +/* CPLL_CON1 */
> +#define CPLL_CON1_VAL 0x0020f300
>
> -/* CLK_DIV_ISP2 */
> -#define CLK_DIV_ISP2_VAL 0x1
> +/* DPLL_CON1 */
> +#define DPLL_CON1_VAL (0x0020F300)
>
> -/* CLK_SRC_DISP1_0 */
> -#define CLK_SRC_DISP1_0_VAL 0x6
> +/* GPLL_CON1 */
> +#define GPLL_CON1_VAL (NOT_AVAILABLE)
>
> -/*
> - * DIV_DISP1_0
> - * For DP, divisor should be 2
> - */
> -#define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
>
> -/* CLK_GATE_IP_DISP1 */
> -#define CLK_GATE_DP1_ALLOW (1 << 4)
> +/* EPLL_CON1, CON2 */
> +#define EPLL_CON1_VAL 0x00000000
> +#define EPLL_CON2_VAL 0x00000080
>
> -#define DDR3PHY_CTRL_PHY_RESET (1 << 0)
> -#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
> +/* VPLL_CON1, CON2 */
> +#define VPLL_CON1_VAL 0x0020f300
> +#define VPLL_CON2_VAL NOT_AVAILABLE
>
> -#define PHY_CON0_RESET_VAL 0x17020a40
> -#define P0_CMD_EN (1 << 14)
> -#define BYTE_RDLVL_EN (1 << 13)
> -#define CTRL_SHGATE (1 << 8)
> +/* RPLL_CON1, CON2 */
> +#define RPLL_CON1_VAL 0x00000000
> +#define RPLL_CON2_VAL 0x00000080
>
> -#define PHY_CON1_RESET_VAL 0x09210100
> -#define CTRL_GATEDURADJ_MASK (0xf << 20)
> +/* BPLL_CON1 */
> +#define BPLL_CON1_VAL 0x0020f300
>
> -#define PHY_CON2_RESET_VAL 0x00010004
> -#define INIT_DESKEW_EN (1 << 6)
> -#define RDLVL_GATE_EN (1 << 24)
> +/* SPLL_CON1 */
> +#define SPLL_CON1_VAL 0x0020f300
>
> -/*ZQ Configurations */
> -#define PHY_CON16_RESET_VAL 0x08000304
> +/* IPLL_CON1 */
> +#define IPLL_CON1_VAL 0x00000080
>
> -#define ZQ_CLK_DIV_EN (1 << 18)
> -#define ZQ_MANUAL_STR (1 << 1)
> -#define ZQ_DONE (1 << 0)
> +/* KPLL_CON1 */
> +#define KPLL_CON1_VAL 0x200000
>
> -#define CTRL_RDLVL_GATE_ENABLE 1
> -#define CTRL_RDLVL_GATE_DISABLE 1
> +/* CLK_SRC_ISP */
> +#define CLK_SRC_ISP_VAL 0x33366000
> +#define CLK_DIV_ISP0_VAL 0x13131300
> +#define CLK_DIV_ISP1_VAL 0xbb110202
>
> -/* Direct Command */
> -#define DIRECT_CMD_NOP 0x07000000
> -#define DIRECT_CMD_PALL 0x01000000
> -#define DIRECT_CMD_ZQINIT 0x0a000000
> -#define DIRECT_CMD_CHANNEL_SHIFT 28
> -#define DIRECT_CMD_CHIP_SHIFT 20
>
> -/* DMC PHY Control0 register */
> -#define PHY_CONTROL0_RESET_VAL 0x0
> -#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
> -#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
> -#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating
> signal */
> -#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
> +/* CLK_FSYS */
> +#define CLK_SRC_FSYS0_VAL 0x33033300
> +#define CLK_DIV_FSYS0_VAL 0x0
> +#define CLK_DIV_FSYS1_VAL 0x04f13c4f
> +#define CLK_DIV_FSYS2_VAL 0x041d0000
> +
> +/* CLK_SRC_CPU */
> +/* 0 = MOUTAPLL, 1 = SCLKMPLL */
> +#define MUX_HPM_SEL 1
> +#define MUX_CPU_SEL 0
> +#define MUX_APLL_SEL 1
>
> -/* Driver strength for CK, CKE, CS & CA */
> -#define IMP_OUTPUT_DRV_40_OHM 0x5
> -#define IMP_OUTPUT_DRV_30_OHM 0x7
> -#define CA_CK_DRVR_DS_OFFSET 9
> -#define CA_CKE_DRVR_DS_OFFSET 6
> -#define CA_CS_DRVR_DS_OFFSET 3
> -#define CA_ADR_DRVR_DS_OFFSET 0
> +#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
> + | (MUX_CPU_SEL << 16) \
> + | (MUX_APLL_SEL))
>
> -#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
> -#define PHY_CON42_CTRL_RDLAT_SHIFT 0
> +/* CLK_SRC_CDREX */
> +#define CLK_SRC_CDREX_VAL 0x00000011
> +
> +/* CLK_DIV_CDREX */
> +#define CLK_DIV_CDREX0_VAL 0x30010100
> +#define CLK_DIV_CDREX1_VAL 0x300
> +
> +#define CLK_DIV_CDREX_VAL 0x17010100
> +
> +/* CLK_DIV_CPU0_VAL */
> +#define CLK_DIV_CPU0_VAL 0x01440020
> +
> +/* CLK_SRC_TOP */
> +#define CLK_SRC_TOP0_VAL 0x12221222
> +#define CLK_SRC_TOP1_VAL 0x00100200
> +#define CLK_SRC_TOP2_VAL 0x11101000
> +#define CLK_SRC_TOP3_VAL 0x11111111
> +#define CLK_SRC_TOP4_VAL 0x11110111
> +#define CLK_SRC_TOP5_VAL 0x11111100
> +#define CLK_SRC_TOP6_VAL 0x11110111
> +#define CLK_SRC_TOP7_VAL 0x00022200
> +
> +/* CLK_DIV_TOP */
> +#define CLK_DIV_TOP0_VAL 0x23712311
> +#define CLK_DIV_TOP1_VAL 0x13100B00
> +#define CLK_DIV_TOP2_VAL 0x11101100
> +
> +/* PLL Lock Value Factor */
> +#define PLL_LOCK_FACTOR 200
> +#define PLL_X_LOCK_FACTOR 3000
> +
> +/* CLK_SRC_PERIC0 */
> +#define SPDIF_SEL 1
> +#define PWM_SEL 3
> +#define UART4_SEL 3
> +#define UART3_SEL 3
> +#define UART2_SEL 3
> +#define UART1_SEL 3
> +#define UART0_SEL 3
> +/* SRC_CLOCK = SCLK_RPLL */
> +#define CLK_SRC_PERIC0_VAL ((SPDIF_SEL << 28) \
> + | (PWM_SEL << 24) \
> + | (UART4_SEL << 20) \
> + | (UART3_SEL << 16) \
> + | (UART2_SEL << 12) \
> + | (UART1_SEL << 8) \
> + | (UART0_SEL << 4))
> +
> +/* CLK_SRC_PERIC1 */
> +/* SRC_CLOCK = SCLK_EPLL */
> +#define SPI0_SEL 6
> +#define SPI1_SEL 6
> +#define SPI2_SEL 6
> +#define AUDIO0_SEL 6
> +#define AUDIO1_SEL 6
> +#define AUDIO2_SEL 6
> +#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 28) \
> + | (SPI1_SEL << 24) \
> + | (SPI0_SEL << 20) \
> + | (AUDIO2_SEL << 16) \
> + | (AUDIO2_SEL << 12) \
> + | (AUDIO2_SEL << 8))
> +
> +/* CLK_DIV_PERIC0 */
> +#define PWM_RATIO 8
> +#define UART4_RATIO 9
> +#define UART3_RATIO 9
> +#define UART2_RATIO 9
> +#define UART1_RATIO 9
> +#define UART0_RATIO 9
> +
> +#define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \
> + | (UART4_RATIO << 24) \
> + | (UART3_RATIO << 20) \
> + | (UART2_RATIO << 16) \
> + | (UART1_RATIO << 12) \
> + | (UART0_RATIO << 8))
> +/* CLK_DIV_PERIC1 */
> +#define SPI2_RATIO 0x1
> +#define SPI1_RATIO 0x1
> +#define SPI0_RATIO 0x1
> +#define CLK_DIV_PERIC1_VAL ((SPI2_RATIO << 28) \
> + | (SPI1_RATIO << 24) \
> + | (SPI0_RATIO << 20))
> +
> +/* CLK_DIV_PERIC2 */
> +#define PCM2_RATIO 0x3
> +#define PCM1_RATIO 0x3
> +#define CLK_DIV_PERIC2_VAL ((PCM2_RATIO << 24) \
> + | (PCM1_RATIO << 16))
> +
> +/* CLK_DIV_PERIC3 */
> +#define AUDIO2_RATIO 0x5
> +#define AUDIO1_RATIO 0x5
> +#define AUDIO0_RATIO 0x5
> +#define CLK_DIV_PERIC3_VAL ((AUDIO2_RATIO << 28) \
> + | (AUDIO1_RATIO << 24) \
> + | (AUDIO0_RATIO << 20))
> +
> +/* CLK_DIV_PERIC4 */
> +#define SPI2_PRE_RATIO 0x2
> +#define SPI1_PRE_RATIO 0x2
> +#define SPI0_PRE_RATIO 0x2
> +#define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \
> + | (SPI1_PRE_RATIO << 16) \
> + | (SPI0_PRE_RATIO << 8))
> +
> +/* CLK_SRC_DISP1_0 */
> +#define CLK_SRC_DISP1_0_VAL 0x10666600
> +#define CLK_DIV_DISP1_0_VAL 0x01050211
> +
> +#define APLL_FOUT (1 << 0)
> +#define KPLL_FOUT (1 << 0)
> +
> +#define CLK_DIV_CPERI1_VAL 0x3f3f0000
> +#endif
>
> struct mem_timings;
>
> @@ -490,7 +889,7 @@ enum {
> };
>
> /*
> - * Memory variant specific initialization code
> + * Memory variant specific initialization code for DDR3
> *
> * @param mem Memory timings for this memory type.
> * @param mem_iv_size Memory interleaving size is a configurable
> parameter
> @@ -503,6 +902,9 @@ enum {
> int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
> int reset);
>
> +/* Memory variant specific initialization code for LPDDR3 */
> +void lpddr3_mem_ctrl_init(void);
> +
> /*
> * Configure ZQ I/O interface
> *
> @@ -532,14 +934,6 @@ void dmc_config_mrs(struct mem_timings *mem, struct
> exynos5_dmc *dmc);
> void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc);
>
> /*
> - * Configure the memconfig and membaseconfig registers
> - *
> - * @param mem Memory timings for this memory type.
> - * @param exynos5_dmc Pointer to struct of DMC registers
> - */
> -void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc);
> -
> -/*
> * Reset the DLL. This function is common between DDR3 and LPDDR2.
> * However, the reset value is different. So we are passing a flag
> * ddr_mode to distinguish between LPDDR2 and DDR3.
> diff --git a/arch/arm/include/asm/arch-exynos/clk.h
> b/arch/arm/include/asm/arch-exynos/clk.h
> index 1d6fa93..cdeef32 100644
> --- a/arch/arm/include/asm/arch-exynos/clk.h
> +++ b/arch/arm/include/asm/arch-exynos/clk.h
> @@ -14,6 +14,7 @@
> #define HPLL 3
> #define VPLL 4
> #define BPLL 5
> +#define RPLL 6
>
> enum pll_src_bit {
> EXYNOS_SRC_MPLL = 6,
> --
> 1.7.12.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 37+ messages in thread* [U-Boot] [PATCH 03/10 V6] Exynos5420: Add clock initialization for 5420
2013-11-13 2:45 ` Minkyu Kang
@ 2013-11-13 11:17 ` Rajeshwari Birje
2013-11-14 1:56 ` Minkyu Kang
0 siblings, 1 reply; 37+ messages in thread
From: Rajeshwari Birje @ 2013-11-13 11:17 UTC (permalink / raw)
To: u-boot
Hi Minkyu Kang,
Thank you for comments,
On Wed, Nov 13, 2013 at 8:15 AM, Minkyu Kang <promsoft@gmail.com> wrote:
> Dear Rajeshwari S Shinde,
>
>
> On 29 October 2013 16:23, Rajeshwari S Shinde <rajeshwari.s@samsung.com>wrote:
>
>> This patch adds code for clock initialization and clock settings
>> of various IP's and controllers, required for Exynos5420
>>
>> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
>> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
>> Acked-by: Simon Glass <sjg@chromium.org>
>> ---
>> Changes in V2:
>> - None
>> Changes in V3:
>> - None
>> Changes in V4:
>> - Corrected the multiline commenting style
>> Changes in V5:
>> - None
>> Changes in V6:
>> - None
>> arch/arm/cpu/armv7/exynos/clock.c | 270 ++++++++-
>> arch/arm/cpu/armv7/exynos/clock_init.h | 17 +
>> arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 352 +++++++++++-
>> arch/arm/cpu/armv7/exynos/exynos5_setup.h | 740
>> +++++++++++++++++++------
>> arch/arm/include/asm/arch-exynos/clk.h | 1 +
>> arch/arm/include/asm/arch-exynos/clock.h | 494 +++++++++++++++++
>> 6 files changed, 1673 insertions(+), 201 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
>> b/arch/arm/cpu/armv7/exynos/clock.c
>> index 36fedd6..b52e61a 100644
>> --- a/arch/arm/cpu/armv7/exynos/clock.c
>> +++ b/arch/arm/cpu/armv7/exynos/clock.c
>> @@ -96,7 +96,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int
>> r, unsigned int k)
>>
>> freq = CONFIG_SYS_CLK_FREQ;
>>
>> - if (pllreg == EPLL) {
>> + if (pllreg == EPLL || pllreg == RPLL) {
>> k = k & 0xffff;
>> /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
>> fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
>> @@ -117,7 +117,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int
>> r, unsigned int k)
>> div = PLL_DIV_1024;
>> else if (proid_is_exynos4412())
>> div = PLL_DIV_65535;
>> - else if (proid_is_exynos5250())
>> + else if (cpu_is_exynos5())
>>
>
> please don't mix proid_is... and cpu_is...
Since both 5420 and 5250 need same value added cpu_is_exynos5(),
instead of doing a or of both.
>
>
>> div = PLL_DIV_65536;
>> else
>> return 0;
>> @@ -362,6 +362,43 @@ unsigned long clock_get_periph_rate(int peripheral)
>> return 0;
>> }
>>
>> +/* exynos5420: return pll clock frequency */
>> +static unsigned long exynos5420_get_pll_clk(int pllreg)
>> +{
>> + struct exynos5420_clock *clk =
>> + (struct exynos5420_clock *)samsung_get_base_clock();
>> + unsigned long r, k = 0;
>> +
>> + switch (pllreg) {
>> + case APLL:
>> + r = readl(&clk->apll_con0);
>> + break;
>> + case MPLL:
>> + r = readl(&clk->mpll_con0);
>> + break;
>> + case EPLL:
>> + r = readl(&clk->epll_con0);
>> + k = readl(&clk->epll_con1);
>> + break;
>> + case VPLL:
>> + r = readl(&clk->vpll_con0);
>> + k = readl(&clk->vpll_con1);
>> + break;
>> + case BPLL:
>> + r = readl(&clk->bpll_con0);
>> + break;
>> + case RPLL:
>> + r = readl(&clk->rpll_con0);
>> + k = readl(&clk->rpll_con1);
>> + break;
>> + default:
>> + printf("Unsupported PLL (%d)\n", pllreg);
>> + return 0;
>> + }
>> +
>> + return exynos_get_pll_clk(pllreg, r, k);
>> +}
>> +
>> /* exynos4: return ARM clock frequency */
>> static unsigned long exynos4_get_arm_clk(void)
>> {
>> @@ -485,6 +522,27 @@ static unsigned long exynos4x12_get_pwm_clk(void)
>> return pclk;
>> }
>>
>> +/* exynos5420: return pwm clock frequency */
>> +static unsigned long exynos5420_get_pwm_clk(void)
>> +{
>> + struct exynos5420_clock *clk =
>> + (struct exynos5420_clock *)samsung_get_base_clock();
>> + unsigned long pclk, sclk;
>> + unsigned int ratio;
>> +
>> + /*
>> + * CLK_DIV_PERIC3
>> + * PWM_RATIO [3:0]
>> + */
>> + ratio = readl(&clk->div_peric0);
>> + ratio = (ratio >> 28) & 0xf;
>> + sclk = get_pll_clk(MPLL);
>> +
>> + pclk = sclk / (ratio + 1);
>> +
>> + return pclk;
>> +}
>> +
>> /* exynos4: return uart clock frequency */
>> static unsigned long exynos4_get_uart_clk(int dev_index)
>> {
>> @@ -624,6 +682,53 @@ static unsigned long exynos5_get_uart_clk(int
>> dev_index)
>> return uclk;
>> }
>>
>> +/* exynos5420: return uart clock frequency */
>> +static unsigned long exynos5420_get_uart_clk(int dev_index)
>> +{
>> + struct exynos5420_clock *clk =
>> + (struct exynos5420_clock *)samsung_get_base_clock();
>> + unsigned long uclk, sclk;
>> + unsigned int sel;
>> + unsigned int ratio;
>> +
>> + /*
>> + * CLK_SRC_PERIC0
>> + * UART0_SEL [3:0]
>> + * UART1_SEL [7:4]
>> + * UART2_SEL [8:11]
>> + * UART3_SEL [12:15]
>> + * UART4_SEL [16:19]
>> + * UART5_SEL [23:20]
>> + */
>> + sel = readl(&clk->src_peric0);
>> + sel = (sel >> ((dev_index * 4) + 4)) & 0x7;
>> +
>> + if (sel == 0x3)
>> + sclk = get_pll_clk(MPLL);
>> + else if (sel == 0x6)
>> + sclk = get_pll_clk(EPLL);
>> + else if (sel == 0x7)
>> + sclk = get_pll_clk(RPLL);
>> + else
>> + return 0;
>> +
>> + /*
>> + * CLK_DIV_PERIC0
>> + * UART0_RATIO [3:0]
>> + * UART1_RATIO [7:4]
>> + * UART2_RATIO [8:11]
>> + * UART3_RATIO [12:15]
>> + * UART4_RATIO [16:19]
>> + * UART5_RATIO [23:20]
>> + */
>> + ratio = readl(&clk->div_peric0);
>> + ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf;
>> +
>> + uclk = sclk / (ratio + 1);
>> +
>> + return uclk;
>> +}
>> +
>> static unsigned long exynos4_get_mmc_clk(int dev_index)
>> {
>> struct exynos4_clock *clk =
>> @@ -718,6 +823,34 @@ static unsigned long exynos5_get_mmc_clk(int
>> dev_index)
>> return uclk;
>> }
>>
>> +static unsigned long exynos5420_get_mmc_clk(int dev_index)
>> +{
>> + struct exynos5420_clock *clk =
>> + (struct exynos5420_clock *)samsung_get_base_clock();
>> + unsigned long uclk, sclk;
>> + unsigned int sel, ratio;
>> + int shift = 0;
>> +
>> + sel = readl(&clk->src_fsys);
>> + sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
>> +
>> + if (sel == 0x3)
>> + sclk = get_pll_clk(MPLL);
>> + else if (sel == 0x6)
>> + sclk = get_pll_clk(EPLL);
>> + else
>> + return 0;
>> +
>> + ratio = readl(&clk->div_fsys1);
>> +
>> + shift = dev_index * 10;
>> +
>> + ratio = (ratio >> shift) & 0x3ff;
>> + uclk = (sclk / (ratio + 1));
>> +
>> + return uclk;
>> +}
>> +
>> /* exynos4: set the mmc clock */
>> static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
>> {
>> @@ -804,6 +937,23 @@ static void exynos5_set_mmc_clk(int dev_index,
>> unsigned int div)
>> writel(val, addr);
>> }
>>
>> +/* exynos5: set the mmc clock */
>> +static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
>> +{
>> + struct exynos5420_clock *clk =
>> + (struct exynos5420_clock *)samsung_get_base_clock();
>> + unsigned int addr;
>> + unsigned int val, shift;
>> +
>> + addr = (unsigned int)&clk->div_fsys1;
>> + shift = dev_index * 10;
>> +
>> + val = readl(addr);
>> + val &= ~(0x3ff << shift);
>> + val |= (div & 0x3ff) << shift;
>> + writel(val, addr);
>> +}
>> +
>> /* get_lcd_clk: return lcd clock frequency */
>> static unsigned long exynos4_get_lcd_clk(void)
>> {
>> @@ -1324,6 +1474,84 @@ static int exynos5_set_spi_clk(enum periph_id
>> periph_id,
>> return 0;
>> }
>>
>> +static int exynos5420_set_spi_clk(enum periph_id periph_id,
>> + unsigned int rate)
>> +{
>> + struct exynos5420_clock *clk =
>> + (struct exynos5420_clock *)samsung_get_base_clock();
>> + int main;
>> + unsigned int fine, val;
>> + unsigned shift, pre_shift;
>> + unsigned div_mask = 0xf, pre_div_mask = 0xff;
>> +
>> + main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
>> + if (main < 0) {
>> + debug("%s: Cannot set clock rate for periph %d",
>> + __func__, periph_id);
>> + return -1;
>> + }
>> + main = main - 1;
>> + fine = fine - 1;
>> +
>> + switch (periph_id) {
>> + case PERIPH_ID_SPI0:
>> + val = readl(&clk->div_peric1);
>> + val &= ~(div_mask << 20);
>> + val |= (main << 20);
>> + writel(val, &clk->div_peric1);
>> +
>> + val = readl(&clk->div_peric4);
>> + val &= ~(pre_div_mask << 8);
>> + val |= (fine << 8);
>> + writel(val, &clk->div_peric4);
>> + break;
>> + case PERIPH_ID_SPI1:
>> + val = readl(&clk->div_peric1);
>> + val &= ~(div_mask << 24);
>> + val |= (main << 24);
>> + writel(val, &clk->div_peric1);
>> +
>> + val = readl(&clk->div_peric4);
>> + val &= ~(pre_div_mask << 16);
>> + val |= (fine << 16);
>> + writel(val, &clk->div_peric4);
>> + break;
>> + case PERIPH_ID_SPI2:
>> + val = readl(&clk->div_peric1);
>> + val &= ~(div_mask << 28);
>> + val |= (main << 28);
>> + writel(val, &clk->div_peric1);
>> +
>> + val = readl(&clk->div_peric4);
>> + val &= ~(pre_div_mask << 24);
>> + val |= (fine << 24);
>> + writel(val, &clk->div_peric4);
>> + break;
>>
>
> I think we can use same code for SPI0/1/2.
will correct this.
>
>
>> + case PERIPH_ID_SPI3:
>> + shift = 16;
>> + pre_shift = 0;
>> + clrsetbits_le32(&clk->div_isp1, div_mask << shift,
>> + (main & div_mask) << shift);
>> + clrsetbits_le32(&clk->div_isp1, pre_div_mask << pre_shift,
>> + (fine & pre_div_mask) << pre_shift);
>> + break;
>> + case PERIPH_ID_SPI4:
>> + shift = 20;
>> + pre_shift = 8;
>> + clrsetbits_le32(&clk->div_isp1, div_mask << shift,
>> + (main & div_mask) << shift);
>> + clrsetbits_le32(&clk->div_isp1, pre_div_mask << pre_shift,
>> + (fine & pre_div_mask) << pre_shift);
>> + break;
>> + default:
>> + debug("%s: Unsupported peripheral ID %d\n", __func__,
>> + periph_id);
>> + return -1;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> static unsigned long exynos4_get_i2c_clk(void)
>> {
>> struct exynos4_clock *clk =
>> @@ -1341,9 +1569,11 @@ static unsigned long exynos4_get_i2c_clk(void)
>>
>> unsigned long get_pll_clk(int pllreg)
>> {
>> - if (cpu_is_exynos5())
>> + if (cpu_is_exynos5()) {
>> + if (proid_is_exynos5420())
>> + return exynos5420_get_pll_clk(pllreg);
>> return exynos5_get_pll_clk(pllreg);
>> - else {
>> + } else {
>> if (proid_is_exynos4412())
>> return exynos4x12_get_pll_clk(pllreg);
>> return exynos4_get_pll_clk(pllreg);
>> @@ -1375,9 +1605,11 @@ unsigned long get_i2c_clk(void)
>>
>> unsigned long get_pwm_clk(void)
>> {
>> - if (cpu_is_exynos5())
>> + if (cpu_is_exynos5()) {
>> + if (proid_is_exynos5420())
>> + return exynos5420_get_pwm_clk();
>> return clock_get_periph_rate(PERIPH_ID_PWM0);
>> - else {
>> + } else {
>> if (proid_is_exynos4412())
>> return exynos4x12_get_pwm_clk();
>> return exynos4_get_pwm_clk();
>> @@ -1386,9 +1618,11 @@ unsigned long get_pwm_clk(void)
>>
>> unsigned long get_uart_clk(int dev_index)
>> {
>> - if (cpu_is_exynos5())
>> + if (cpu_is_exynos5()) {
>> + if (proid_is_exynos5420())
>> + return exynos5420_get_uart_clk(dev_index);
>> return exynos5_get_uart_clk(dev_index);
>> - else {
>> + } else {
>> if (proid_is_exynos4412())
>> return exynos4x12_get_uart_clk(dev_index);
>> return exynos4_get_uart_clk(dev_index);
>> @@ -1397,17 +1631,22 @@ unsigned long get_uart_clk(int dev_index)
>>
>> unsigned long get_mmc_clk(int dev_index)
>> {
>> - if (cpu_is_exynos5())
>> + if (cpu_is_exynos5()) {
>> + if (proid_is_exynos5420())
>> + return exynos5420_get_mmc_clk(dev_index);
>> return exynos5_get_mmc_clk(dev_index);
>> - else
>> + } else {
>> return exynos4_get_mmc_clk(dev_index);
>> + }
>> }
>>
>> void set_mmc_clk(int dev_index, unsigned int div)
>> {
>> - if (cpu_is_exynos5())
>> + if (cpu_is_exynos5()) {
>> + if (proid_is_exynos5420())
>> + return exynos5420_set_mmc_clk(dev_index, div);
>> exynos5_set_mmc_clk(dev_index, div);
>> - else {
>> + } else {
>> if (proid_is_exynos4412())
>> exynos4x12_set_mmc_clk(dev_index, div);
>> exynos4_set_mmc_clk(dev_index, div);
>> @@ -1438,10 +1677,13 @@ void set_mipi_clk(void)
>>
>> int set_spi_clk(int periph_id, unsigned int rate)
>> {
>> - if (cpu_is_exynos5())
>> + if (cpu_is_exynos5()) {
>> + if (proid_is_exynos5420())
>> + return exynos5420_set_spi_clk(periph_id, rate);
>> return exynos5_set_spi_clk(periph_id, rate);
>> - else
>> + } else {
>> return 0;
>> + }
>> }
>>
>> int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,
>> diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h
>> b/arch/arm/cpu/armv7/exynos/clock_init.h
>> index c28ff3a..a875d0b 100644
>> --- a/arch/arm/cpu/armv7/exynos/clock_init.h
>> +++ b/arch/arm/cpu/armv7/exynos/clock_init.h
>> @@ -10,7 +10,11 @@
>> #define __EXYNOS_CLOCK_INIT_H
>>
>> enum {
>> +#ifdef CONFIG_EXYNOS5420
>> + MEM_TIMINGS_MSR_COUNT = 5,
>> +#else
>> MEM_TIMINGS_MSR_COUNT = 4,
>> +#endif
>> };
>>
>> /* These are the ratio's for configuring ARM clock */
>> @@ -59,6 +63,18 @@ struct mem_timings {
>> unsigned bpll_mdiv;
>> unsigned bpll_pdiv;
>> unsigned bpll_sdiv;
>> + unsigned kpll_mdiv;
>> + unsigned kpll_pdiv;
>> + unsigned kpll_sdiv;
>> + unsigned dpll_mdiv;
>> + unsigned dpll_pdiv;
>> + unsigned dpll_sdiv;
>> + unsigned ipll_mdiv;
>> + unsigned ipll_pdiv;
>> + unsigned ipll_sdiv;
>> + unsigned spll_mdiv;
>> + unsigned spll_pdiv;
>> + unsigned spll_sdiv;
>> unsigned pclk_cdrex_ratio;
>> unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
>>
>> @@ -115,6 +131,7 @@ struct mem_timings {
>> uint8_t send_zq_init; /* 1 to send this command */
>> unsigned impedance; /* drive strength impedeance */
>> uint8_t gate_leveling_enable; /* check gate leveling is enabled
>> */
>> + uint8_t read_leveling_enable; /* check h/w read leveling is
>> enabled */
>> };
>>
>> /**
>> diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
>> b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
>> index a24c2f3..e7f1496 100644
>> --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
>> +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
>> @@ -24,6 +24,24 @@
>> DECLARE_GLOBAL_DATA_PTR;
>>
>> struct arm_clk_ratios arm_clk_ratios[] = {
>> +#ifdef CONFIG_EXYNOS5420
>> + {
>> + .arm_freq_mhz = 900,
>> +
>> + .apll_mdiv = 0x96,
>> + .apll_pdiv = 0x2,
>> + .apll_sdiv = 0x1,
>> +
>> + .arm2_ratio = 0x0,
>> + .apll_ratio = 0x3,
>> + .pclk_dbg_ratio = 0x6,
>> + .atb_ratio = 0x6,
>> + .periph_ratio = 0x7,
>> + .acp_ratio = 0x0,
>> + .cpud_ratio = 0x2,
>> + .arm_ratio = 0x0,
>> + }
>> +#else
>> {
>> .arm_freq_mhz = 600,
>>
>> @@ -115,8 +133,133 @@ struct arm_clk_ratios arm_clk_ratios[] = {
>> .cpud_ratio = 0x3,
>> .arm_ratio = 0x0,
>> }
>> +#endif
>> };
>> +
>> struct mem_timings mem_timings[] = {
>> +#ifdef CONFIG_EXYNOS5420
>> + {
>> + .mem_manuf = MEM_MANUF_SAMSUNG,
>> + .mem_type = DDR_MODE_DDR3,
>> + .frequency_mhz = 800,
>> +
>> + /* MPLL @800MHz*/
>> + .mpll_mdiv = 0xc8,
>> + .mpll_pdiv = 0x3,
>> + .mpll_sdiv = 0x1,
>> + /* CPLL @666MHz */
>> + .cpll_mdiv = 0xde,
>> + .cpll_pdiv = 0x4,
>> + .cpll_sdiv = 0x1,
>> + /* EPLL @600MHz */
>> + .epll_mdiv = 0x64,
>> + .epll_pdiv = 0x2,
>> + .epll_sdiv = 0x1,
>> + /* VPLL @430MHz */
>> + .vpll_mdiv = 0xd7,
>> + .vpll_pdiv = 0x3,
>> + .vpll_sdiv = 0x2,
>> + /* BPLL @800MHz */
>> + .bpll_mdiv = 0xc8,
>> + .bpll_pdiv = 0x3,
>> + .bpll_sdiv = 0x1,
>> + /* KPLL @600MHz */
>> + .kpll_mdiv = 0x190,
>> + .kpll_pdiv = 0x4,
>> + .kpll_sdiv = 0x2,
>> + /* DPLL @600MHz */
>> + .dpll_mdiv = 0x190,
>> + .dpll_pdiv = 0x4,
>> + .dpll_sdiv = 0x2,
>> + /* IPLL @370MHz */
>> + .ipll_mdiv = 0xb9,
>> + .ipll_pdiv = 0x3,
>> + .ipll_sdiv = 0x2,
>> + /* SPLL @400MHz */
>> + .spll_mdiv = 0xc8,
>> + .spll_pdiv = 0x3,
>> + .spll_sdiv = 0x2,
>> +
>> + .direct_cmd_msr = {
>> + 0x00020018, 0x00030000, 0x00010046, 0x00000d70,
>> + 0x00000c70
>> + },
>> + .timing_ref = 0x000000bb,
>> + .timing_row = 0x6836650f,
>> + .timing_data = 0x3630580b,
>> + .timing_power = 0x41000a26,
>> + .phy0_dqs = 0x08080808,
>> + .phy1_dqs = 0x08080808,
>> + .phy0_dq = 0x08080808,
>> + .phy1_dq = 0x08080808,
>> + .phy0_tFS = 0x8,
>> + .phy1_tFS = 0x8,
>> + .phy0_pulld_dqs = 0xf,
>> + .phy1_pulld_dqs = 0xf,
>> +
>> + .lpddr3_ctrl_phy_reset = 0x1,
>> + .ctrl_start_point = 0x10,
>> + .ctrl_inc = 0x10,
>> + .ctrl_start = 0x1,
>> + .ctrl_dll_on = 0x1,
>> + .ctrl_ref = 0x8,
>> +
>> + .ctrl_force = 0x1a,
>> + .ctrl_rdlat = 0x0b,
>> + .ctrl_bstlen = 0x08,
>> +
>> + .fp_resync = 0x8,
>> + .iv_size = 0x7,
>> + .dfi_init_start = 1,
>> + .aref_en = 1,
>> +
>> + .rd_fetch = 0x3,
>> +
>> + .zq_mode_dds = 0x7,
>> + .zq_mode_term = 0x1,
>> + .zq_mode_noterm = 1,
>> +
>> + /*
>> + * Dynamic Clock: Always Running
>> + * Memory Burst length: 8
>> + * Number of chips: 1
>> + * Memory Bus width: 32 bit
>> + * Memory Type: DDR3
>> + * Additional Latancy for PLL: 0 Cycle
>> + */
>> + .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
>> + DMC_MEMCONTROL_DPWRDN_DISABLE |
>> + DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
>> + DMC_MEMCONTROL_TP_DISABLE |
>> + DMC_MEMCONTROL_DSREF_DISABLE |
>> + DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
>> + DMC_MEMCONTROL_MEM_TYPE_DDR3 |
>> + DMC_MEMCONTROL_MEM_WIDTH_32BIT |
>> + DMC_MEMCONTROL_NUM_CHIP_1 |
>> + DMC_MEMCONTROL_BL_8 |
>> + DMC_MEMCONTROL_PZQ_DISABLE |
>> + DMC_MEMCONTROL_MRR_BYTE_7_0,
>> + .memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
>> + DMC_MEMCONFIGX_CHIP_COL_10 |
>> + DMC_MEMCONFIGX_CHIP_ROW_15 |
>> + DMC_MEMCONFIGX_CHIP_BANK_8,
>> + .prechconfig_tp_cnt = 0xff,
>> + .dpwrdn_cyc = 0xff,
>> + .dsref_cyc = 0xffff,
>> + .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
>> + DMC_CONCONTROL_TIMEOUT_LEVEL0 |
>> + DMC_CONCONTROL_RD_FETCH_DISABLE |
>> + DMC_CONCONTROL_EMPTY_DISABLE |
>> + DMC_CONCONTROL_AREF_EN_DISABLE |
>> + DMC_CONCONTROL_IO_PD_CON_DISABLE,
>> + .dmc_channels = 1,
>> + .chips_per_channel = 1,
>> + .chips_to_configure = 1,
>> + .send_zq_init = 1,
>> + .gate_leveling_enable = 1,
>> + .read_leveling_enable = 0,
>> + }
>> +#else
>> {
>> .mem_manuf = MEM_MANUF_ELPIDA,
>> .mem_type = DDR_MODE_DDR3,
>> @@ -324,6 +467,7 @@ struct mem_timings mem_timings[] = {
>> .impedance = IMP_OUTPUT_DRV_40_OHM,
>> .gate_leveling_enable = 1,
>> }
>> +#endif
>> };
>>
>> /**
>> @@ -399,7 +543,7 @@ struct mem_timings *clock_get_mem_timings(void)
>> return NULL;
>> }
>>
>> -void system_clock_init()
>> +static void exynos5250_system_clock_init(void)
>> {
>> struct exynos5_clock *clk =
>> (struct exynos5_clock *)samsung_get_base_clock();
>> @@ -436,19 +580,13 @@ void system_clock_init()
>> } while ((val | MUX_BPLL_SEL_MASK) != val);
>>
>> /* PLL locktime */
>> - writel(APLL_LOCK_VAL, &clk->apll_lock);
>> -
>> - writel(MPLL_LOCK_VAL, &clk->mpll_lock);
>> -
>> - writel(BPLL_LOCK_VAL, &clk->bpll_lock);
>> -
>> - writel(CPLL_LOCK_VAL, &clk->cpll_lock);
>> -
>> - writel(GPLL_LOCK_VAL, &clk->gpll_lock);
>> -
>> - writel(EPLL_LOCK_VAL, &clk->epll_lock);
>> -
>> - writel(VPLL_LOCK_VAL, &clk->vpll_lock);
>> + writel(mem->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
>> + writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
>> + writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
>> + writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
>> + writel(mem->gpll_pdiv * PLL_X_LOCK_FACTOR, &clk->gpll_lock);
>> + writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
>> + writel(mem->vpll_pdiv * PLL_X_LOCK_FACTOR, &clk->vpll_lock);
>>
>> writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
>>
>> @@ -640,6 +778,192 @@ void system_clock_init()
>> writel(val, &clk->div_fsys2);
>> }
>>
>> +static void exynos5420_system_clock_init(void)
>> +{
>> + struct exynos5420_clock *clk =
>> + (struct exynos5420_clock *)EXYNOS5_CLOCK_BASE;
>> + struct mem_timings *mem;
>> + struct arm_clk_ratios *arm_clk_ratio;
>> + u32 val;
>> +
>> + mem = clock_get_mem_timings();
>> + arm_clk_ratio = get_arm_ratios();
>> +
>> + /* PLL locktime */
>> + writel(arm_clk_ratio->apll_pdiv * PLL_LOCK_FACTOR,
>> &clk->apll_lock);
>> + writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
>> + writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
>> + writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
>> + writel(mem->dpll_pdiv * PLL_LOCK_FACTOR, &clk->dpll_lock);
>> + writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
>> + writel(mem->vpll_pdiv * PLL_LOCK_FACTOR, &clk->vpll_lock);
>> + writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
>> + writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
>> + writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
>> +
>> + setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
>> +
>> + writel(0, &clk->src_top6);
>> +
>> + writel(0, &clk->src_cdrex);
>> + writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
>> + writel(HPM_RATIO, &clk->div_cpu1);
>> + writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
>> +
>> + /* switch A15 clock source to OSC clock before changing APLL */
>> + clrbits_le32(&clk->src_cpu, APLL_FOUT);
>> +
>> + /* Set APLL */
>> + writel(APLL_CON1_VAL, &clk->apll_con1);
>> + val = set_pll(arm_clk_ratio->apll_mdiv,
>> + arm_clk_ratio->apll_pdiv,
>> + arm_clk_ratio->apll_sdiv);
>> + writel(val, &clk->apll_con0);
>> + while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0)
>> + ;
>> +
>> + /* now it is safe to switch to APLL */
>> + setbits_le32(&clk->src_cpu, APLL_FOUT);
>> +
>> + writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
>> + writel(CLK_DIV_KFC_VAL, &clk->div_kfc0);
>> +
>> + /* switch A7 clock source to OSC clock before changing KPLL */
>> + clrbits_le32(&clk->src_kfc, KPLL_FOUT);
>> +
>> + /* Set KPLL*/
>> + writel(KPLL_CON1_VAL, &clk->kpll_con1);
>> + val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv);
>> + writel(val, &clk->kpll_con0);
>> + while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
>> + ;
>> +
>> + /* now it is safe to switch to KPLL */
>> + setbits_le32(&clk->src_kfc, KPLL_FOUT);
>> +
>> + /* Set MPLL */
>> + writel(MPLL_CON1_VAL, &clk->mpll_con1);
>> + val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
>> + writel(val, &clk->mpll_con0);
>> + while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0)
>> + ;
>> +
>> + /* Set DPLL */
>> + writel(DPLL_CON1_VAL, &clk->dpll_con1);
>> + val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv);
>> + writel(val, &clk->dpll_con0);
>> + while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0)
>> + ;
>> +
>> + /* Set EPLL */
>> + writel(EPLL_CON2_VAL, &clk->epll_con2);
>> + writel(EPLL_CON1_VAL, &clk->epll_con1);
>> + val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
>> + writel(val, &clk->epll_con0);
>> + while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0)
>> + ;
>> +
>> + /* Set CPLL */
>> + writel(CPLL_CON1_VAL, &clk->cpll_con1);
>> + val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
>> + writel(val, &clk->cpll_con0);
>> + while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0)
>> + ;
>> +
>> + /* Set IPLL */
>> + writel(IPLL_CON1_VAL, &clk->ipll_con1);
>> + val = set_pll(mem->ipll_mdiv, mem->ipll_pdiv, mem->ipll_sdiv);
>> + writel(val, &clk->ipll_con0);
>> + while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0)
>> + ;
>> +
>> + /* Set VPLL */
>> + writel(VPLL_CON1_VAL, &clk->vpll_con1);
>> + val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
>> + writel(val, &clk->vpll_con0);
>> + while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0)
>> + ;
>> +
>> + /* Set BPLL */
>> + writel(BPLL_CON1_VAL, &clk->bpll_con1);
>> + val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
>> + writel(val, &clk->bpll_con0);
>> + while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0)
>> + ;
>> +
>> + /* Set SPLL */
>> + writel(SPLL_CON1_VAL, &clk->spll_con1);
>> + val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv);
>> + writel(val, &clk->spll_con0);
>> + while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
>> + ;
>> +
>> + writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
>> + writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
>> +
>> + writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
>> + writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
>> + writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
>> + writel(CLK_SRC_TOP7_VAL, &clk->src_top7);
>> +
>> + writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
>> + writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
>> + writel(CLK_DIV_TOP2_VAL, &clk->div_top2);
>> +
>> + writel(0, &clk->src_top10);
>> + writel(0, &clk->src_top11);
>> + writel(0, &clk->src_top12);
>> +
>> + writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
>> + writel(CLK_SRC_TOP4_VAL, &clk->src_top4);
>> + writel(CLK_SRC_TOP5_VAL, &clk->src_top5);
>> +
>> + /* DISP1 BLK CLK SELECTION */
>> + writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10);
>> + writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10);
>> +
>> + /* AUDIO BLK */
>> + writel(AUDIO0_SEL_EPLL, &clk->src_mau);
>> + writel(DIV_MAU_VAL, &clk->div_mau);
>> +
>> + /* FSYS */
>> + writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
>> + writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
>> + writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
>> + writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
>> +
>> + writel(CLK_SRC_ISP_VAL, &clk->src_isp);
>> + writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
>> + writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
>> +
>> + writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
>> + writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
>> +
>> + writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
>> + writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
>> + writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
>> + writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
>> + writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4);
>> +
>> + writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1);
>> +
>> + writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
>> + writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
>> + writel(CLK_DIV_G2D, &clk->div_g2d);
>> +
>> + writel(CLK_SRC_TOP6_VAL, &clk->src_top6);
>> + writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
>> + writel(CLK_SRC_KFC_VAL, &clk->src_kfc);
>> +}
>> +
>> +void system_clock_init(void)
>> +{
>> + if (proid_is_exynos5420())
>> + exynos5420_system_clock_init();
>> + else
>> + exynos5250_system_clock_init();
>> +}
>> +
>> void clock_init_dp_clock(void)
>> {
>> struct exynos5_clock *clk =
>> diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
>> b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
>> index 696b386..8e05a00 100644
>> --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
>> +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
>> @@ -12,42 +12,16 @@
>> #include <config.h>
>> #include <asm/arch/dmc.h>
>>
>> -/* APLL_CON1 */
>> -#define APLL_CON1_VAL (0x00203800)
>> -
>> -/* MPLL_CON1 */
>> -#define MPLL_CON1_VAL (0x00203800)
>> -
>> -/* CPLL_CON1 */
>> -#define CPLL_CON1_VAL (0x00203800)
>> -
>> -/* GPLL_CON1 */
>> -#define GPLL_CON1_VAL (0x00203800)
>> -
>> -/* EPLL_CON1, CON2 */
>> -#define EPLL_CON1_VAL 0x00000000
>> -#define EPLL_CON2_VAL 0x00000080
>> -
>> -/* VPLL_CON1, CON2 */
>> -#define VPLL_CON1_VAL 0x00000000
>> -#define VPLL_CON2_VAL 0x00000080
>> +#define NOT_AVAILABLE 0
>> +#define DATA_MASK 0xFFFFF
>>
>> -/* BPLL_CON1 */
>> -#define BPLL_CON1_VAL 0x00203800
>> +#define ENABLE_BIT 0x1
>> +#define DISABLE_BIT 0x0
>> +#define CA_SWAP_EN (1 << 0)
>>
>> /* Set PLL */
>> #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
>>
>> -/* CLK_SRC_CPU */
>> -/* 0 = MOUTAPLL, 1 = SCLKMPLL */
>> -#define MUX_HPM_SEL 0
>> -#define MUX_CPU_SEL 0
>> -#define MUX_APLL_SEL 1
>> -
>> -#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
>> - | (MUX_CPU_SEL << 16) \
>> - | (MUX_APLL_SEL))
>> -
>> /* MEMCONTROL register bit fields */
>> #define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
>> #define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
>> @@ -78,6 +52,7 @@
>>
>> /* MEMCONFIG0 register bit fields */
>> #define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED (1 << 12)
>> +#define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12)
>> #define DMC_MEMCONFIGX_CHIP_COL_10 (3 << 8)
>> #define DMC_MEMCONFIGX_CHIP_ROW_14 (2 << 4)
>> #define DMC_MEMCONFIGX_CHIP_ROW_15 (3 << 4)
>> @@ -90,6 +65,16 @@
>> DMC_MEMBASECONFIGX_CHIP_MASK(0x780) \
>> )
>>
>> +/* As we use channel interleaving, therefore value of the base address
>> + * register must be set as half of the bus base address
>> + * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
>> + * we need to set half 0x10 to the membaseconfigx registers
>> + * see exynos5420 UM section 17.17.3.21 for more
>> + */
>>
>
> please fix this multiline comment.
Will correct this
>
>
>> +#define DMC_CHIP_BASE_0 0x10
>> +#define DMC_CHIP_BASE_1 0x50
>> +#define DMC_CHIP_MASK 0x7C0
>> +
>> #define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
>> #define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
>>
>> @@ -113,29 +98,24 @@
>>
>> /* COJCONTROL register bit fields */
>> #define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
>> +#define DMC_CONCONTROL_IO_PD_CON_ENABLE (1 << 3)
>> #define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
>> +#define DMC_CONCONTROL_AREF_EN_ENABLE (1 << 5)
>> #define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8)
>> #define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8)
>> #define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
>> #define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
>> #define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
>>
>> -/* CLK_DIV_CPU0_VAL */
>> -#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \
>> - | (APLL_RATIO << 24) \
>> - | (PCLK_DBG_RATIO << 20) \
>> - | (ATB_RATIO << 16) \
>> - | (PERIPH_RATIO << 12) \
>> - | (ACP_RATIO << 8) \
>> - | (CPUD_RATIO << 4) \
>> - | (ARM_RATIO))
>> +#define DMC_CONCONTROL_VAL 0x1FFF2101
>>
>> +#define DREX_CONCONTROL_VAL DMC_CONCONTROL_VAL \
>> + | DMC_CONCONTROL_AREF_EN_ENABLE \
>> + | DMC_CONCONTROL_IO_PD_CON_ENABLE
>>
>> -/* CLK_FSYS */
>> -#define CLK_SRC_FSYS0_VAL 0x66666
>> -#define CLK_DIV_FSYS0_VAL 0x0BB00000
>> +#define DMC_CONCONTROL_IO_PD_CON(x) (x << 6)
>>
>> -/* CLK_DIV_CPU1 */
>> +/* CLK_DIV_CPU1 */
>> #define HPM_RATIO 0x2
>> #define COPY_RATIO 0x0
>>
>> @@ -164,10 +144,370 @@
>> /* CLK_DIV_SYSLFT */
>> #define CLK_DIV_SYSLFT_VAL 0x00000311
>>
>> +#define MUX_APLL_SEL_MASK (1 << 0)
>> +#define MUX_MPLL_SEL_MASK (1 << 8)
>> +#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
>> +#define MUX_CPLL_SEL_MASK (1 << 8)
>> +#define MUX_EPLL_SEL_MASK (1 << 12)
>> +#define MUX_VPLL_SEL_MASK (1 << 16)
>> +#define MUX_GPLL_SEL_MASK (1 << 28)
>> +#define MUX_BPLL_SEL_MASK (1 << 0)
>> +#define MUX_HPM_SEL_MASK (1 << 20)
>> +#define HPM_SEL_SCLK_MPLL (1 << 21)
>> +#define PLL_LOCKED (1 << 29)
>> +#define APLL_CON0_LOCKED (1 << 29)
>> +#define MPLL_CON0_LOCKED (1 << 29)
>> +#define BPLL_CON0_LOCKED (1 << 29)
>> +#define CPLL_CON0_LOCKED (1 << 29)
>> +#define EPLL_CON0_LOCKED (1 << 29)
>> +#define GPLL_CON0_LOCKED (1 << 29)
>> +#define VPLL_CON0_LOCKED (1 << 29)
>> +#define CLK_REG_DISABLE 0x0
>> +#define TOP2_VAL 0x0110000
>> +
>> +/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
>> +#define SPI0_ISP_SEL 6
>> +#define SPI1_ISP_SEL 6
>> +#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
>> + | (SPI0_ISP_SEL << 0)
>> +
>> +/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
>> +#define SPI0_ISP_RATIO 0xf
>> +#define SPI1_ISP_RATIO 0xf
>> +#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
>> + | (SPI0_ISP_RATIO << 0)
>> +
>> +/* CLK_DIV_FSYS2 */
>> +#define MMC2_RATIO_MASK 0xf
>> +#define MMC2_RATIO_VAL 0x3
>> +#define MMC2_RATIO_OFFSET 0
>> +
>> +#define MMC2_PRE_RATIO_MASK 0xff
>> +#define MMC2_PRE_RATIO_VAL 0x9
>> +#define MMC2_PRE_RATIO_OFFSET 8
>> +
>> +#define MMC3_RATIO_MASK 0xf
>> +#define MMC3_RATIO_VAL 0x1
>> +#define MMC3_RATIO_OFFSET 16
>> +
>> +#define MMC3_PRE_RATIO_MASK 0xff
>> +#define MMC3_PRE_RATIO_VAL 0x0
>> +#define MMC3_PRE_RATIO_OFFSET 24
>> +
>> +/* CLK_SRC_LEX */
>> +#define CLK_SRC_LEX_VAL 0x0
>> +
>> +/* CLK_DIV_LEX */
>> +#define CLK_DIV_LEX_VAL 0x10
>> +
>> +/* CLK_DIV_R0X */
>> +#define CLK_DIV_R0X_VAL 0x10
>> +
>> +/* CLK_DIV_L0X */
>> +#define CLK_DIV_R1X_VAL 0x10
>> +
>> +/* CLK_DIV_ISP2 */
>> +#define CLK_DIV_ISP2_VAL 0x1
>> +
>> +/* CLK_SRC_KFC */
>> +#define SRC_KFC_HPM_SEL (1 << 15)
>> +
>> +/* CLK_SRC_KFC */
>> +#define CLK_SRC_KFC_VAL 0x00008001
>> +
>> +/* CLK_DIV_KFC */
>> +#define CLK_DIV_KFC_VAL 0x03300110
>> +
>> +/* CLK_DIV2_RATIO */
>> +#define CLK_DIV2_RATIO 0x10111150
>> +
>> +/* CLK_DIV4_RATIO */
>> +#define CLK_DIV4_RATIO 0x00000003
>> +
>> +/* CLK_DIV_G2D */
>> +#define CLK_DIV_G2D 0x00000010
>> +
>> +/*
>> + * DIV_DISP1_0
>> + * For DP, divisor should be 2
>> + */
>> +#define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
>> +
>> +/* CLK_GATE_IP_DISP1 */
>> +#define CLK_GATE_DP1_ALLOW (1 << 4)
>> +
>> +/* AUDIO CLK SEL */
>> +#define AUDIO0_SEL_EPLL (0x6 << 28)
>> +#define AUDIO0_RATIO 0x5
>> +#define PCM0_RATIO 0x3
>> +#define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20)
>> +
>>
>
> please remove blank line.
>
>
>> +
>> +/* CLK_SRC_CDREX */
>> +#define MUX_MCLK_CDR_MSPLL (1 << 4)
>> +#define MUX_BPLL_SEL_FOUTBPLL (1 << 0)
>> +#define BPLL_SEL_MASK 0x7
>> +#define FOUTBPLL 2
>> +
>> +#define DDR3PHY_CTRL_PHY_RESET (1 << 0)
>> +#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
>> +
>> +#define PHY_CON0_RESET_VAL 0x17020a40
>> +#define P0_CMD_EN (1 << 14)
>> +#define BYTE_RDLVL_EN (1 << 13)
>> +#define CTRL_SHGATE (1 << 8)
>> +
>> +#define PHY_CON1_RESET_VAL 0x09210100
>> +#define RDLVL_PASS_ADJ_VAL 0x6
>> +#define RDLVL_PASS_ADJ_OFFSET 16
>> +#define CTRL_GATEDURADJ_MASK (0xf << 20)
>> +#define READ_LEVELLING_DDR3 0x0100
>> +
>> +#define PHY_CON2_RESET_VAL 0x00010004
>> +#define INIT_DESKEW_EN (1 << 6)
>> +#define DLL_DESKEW_EN (1 << 12)
>> +#define RDLVL_GATE_EN (1 << 24)
>> +#define RDLVL_EN (1 << 25)
>> +#define RDLVL_INCR_ADJ (0x1 << 16)
>> +
>> +/* DREX_PAUSE */
>> +#define DREX_PAUSE_EN (1 << 0)
>> +
>> +#define BYPASS_EN (1 << 22)
>> +
>> +/********-----MEMMORY VAL----------***/
>>
>
> /* MEMORY VAL */
>
>
>> +#define PHY_CON0_VAL 0x17021A00
>> +
>> +#define PHY_CON12_RESET_VAL 0x10100070
>> +#define PHY_CON12_VAL 0x10107F50
>> +#define CTRL_START (1 << 6)
>> +#define CTRL_DLL_ON (1 << 5)
>> +#define CTRL_FORCE_MASK (0x7F << 8)
>> +#define CTRL_LOCK_COARSE_MASK (0x7F << 10)
>> +
>>
>
> please remove blank line.
Will correct this
>
>
>> +
>> +#define CTRL_OFFSETD_RESET_VAL 0x8
>> +#define CTRL_OFFSETD_VAL 0x7F
>> +
>> +#define CTRL_OFFSETR0 0x7F
>> +#define CTRL_OFFSETR1 0x7F
>> +#define CTRL_OFFSETR2 0x7F
>> +#define CTRL_OFFSETR3 0x7F
>> +#define PHY_CON4_VAL (CTRL_OFFSETR0 << 0 | \
>> + CTRL_OFFSETR1 << 8 | \
>> + CTRL_OFFSETR2 << 16 | \
>> + CTRL_OFFSETR3 << 24)
>> +#define PHY_CON4_RESET_VAL 0x08080808
>> +
>> +#define CTRL_OFFSETW0 0x7F
>> +#define CTRL_OFFSETW1 0x7F
>> +#define CTRL_OFFSETW2 0x7F
>> +#define CTRL_OFFSETW3 0x7F
>> +#define PHY_CON6_VAL (CTRL_OFFSETW0 << 0 | \
>> + CTRL_OFFSETW1 << 8 | \
>> + CTRL_OFFSETW2 << 16 | \
>> + CTRL_OFFSETW3 << 24)
>> +#define PHY_CON6_RESET_VAL 0x08080808
>> +
>> +#define PHY_CON14_RESET_VAL 0x001F0000
>> +#define CTRL_PULLD_DQS 0xF
>> +#define CTRL_PULLD_DQS_OFFSET 0
>> +
>> +/*ZQ Configurations */
>>
>
> please add space before ZQ.
>
>
>> +#define PHY_CON16_RESET_VAL 0x08000304
>> +
>> +#define ZQ_CLK_EN (1 << 27)
>> +#define ZQ_CLK_DIV_EN (1 << 18)
>> +#define ZQ_MANUAL_STR (1 << 1)
>> +#define ZQ_DONE (1 << 0)
>> +#define ZQ_MODE_DDS_OFFSET 24
>> +
>> +#define CTRL_RDLVL_GATE_ENABLE 1
>> +#define CTRL_RDLVL_GATE_DISABLE 0
>> +#define CTRL_RDLVL_DATA_ENABLE 2
>> +
>> +/* Direct Command */
>> +#define DIRECT_CMD_NOP 0x07000000
>> +#define DIRECT_CMD_PALL 0x01000000
>> +#define DIRECT_CMD_ZQINIT 0x0a000000
>> +#define DIRECT_CMD_CHANNEL_SHIFT 28
>> +#define DIRECT_CMD_CHIP_SHIFT 20
>> +#define DIRECT_CMD_BANK_SHIFT 16
>> +#define DIRECT_CMD_REFA (5 << 24)
>> +#define DIRECT_CMD_MRS1 0x71C00
>> +#define DIRECT_CMD_MRS2 0x10BFC
>> +#define DIRECT_CMD_MRS3 0x0050C
>> +#define DIRECT_CMD_MRS4 0x00868
>> +#define DIRECT_CMD_MRS5 0x00C04
>> +
>> +/* Drive Strength */
>> +#define IMPEDANCE_48_OHM 4
>> +#define IMPEDANCE_40_OHM 5
>> +#define IMPEDANCE_34_OHM 6
>> +#define IMPEDANCE_30_OHM 7
>> +#define PHY_CON39_VAL_48_OHM 0x09240924
>> +#define PHY_CON39_VAL_40_OHM 0x0B6D0B6D
>> +#define PHY_CON39_VAL_34_OHM 0x0DB60DB6
>> +#define PHY_CON39_VAL_30_OHM 0x0FFF0FFF
>> +
>>
>
> please remove blank line.
Will correct this
>
>
>> +
>> +#define CTRL_BSTLEN_OFFSET 8
>> +#define CTRL_RDLAT_OFFSET 0
>> +
>> +#define CMD_DEFAULT_LPDDR3 0xF
>> +#define CMD_DEFUALT_OFFSET 0
>> +#define T_WRDATA_EN 0x7
>> +#define T_WRDATA_EN_DDR3 0x8
>> +#define T_WRDATA_EN_OFFSET 16
>> +#define T_WRDATA_EN_MASK 0x1f
>> +
>> +#define PHY_CON31_VAL 0x0C183060
>> +#define PHY_CON32_VAL 0x60C18306
>> +#define PHY_CON33_VAL 0x00000030
>> +
>> +#define PHY_CON31_RESET_VAL 0x0
>> +#define PHY_CON32_RESET_VAL 0x0
>> +#define PHY_CON33_RESET_VAL 0x0
>> +
>> +#define SL_DLL_DYN_CON_EN (1 << 1)
>> +#define FP_RESYNC (1 << 3)
>> +#define CTRL_START (1 << 6)
>> +
>> +#define DMC_AREF_EN (1 << 5)
>> +#define DMC_CONCONTROL_EMPTY (1 << 8)
>> +#define DFI_INIT_START (1 << 28)
>> +
>> +#define DMC_MEMCONTROL_VAL 0x00312700
>> +#define CLK_STOP_EN (1 << 0)
>> +#define DPWRDN_EN (1 << 1)
>> +#define DSREF_EN (1 << 5)
>> +
>> +#define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0
>> +#define MEMBASECONFIG_CHIP_MASK_OFFSET 0
>> +#define MEMBASECONFIG0_CHIP_BASE_VAL 0x20
>> +#define MEMBASECONFIG1_CHIP_BASE_VAL 0x40
>> +#define CHIP_BASE_OFFSET 16
>> +
>> +#define MEMCONFIG_VAL 0x1323
>> +#define PRECHCONFIG_DEFAULT_VAL 0xFF000000
>> +#define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF
>> +
>> +#define TIMINGAREF_VAL 0x5d
>> +#define TIMINGROW_VAL 0x345A8692
>> +#define TIMINGDATA_VAL 0x3630065C
>> +#define TIMINGPOWER_VAL 0x50380336
>> +#define DFI_INIT_COMPLETE (1 << 3)
>> +
>> +#define BRBRSVCONTROL_VAL 0x00000033
>> +#define BRBRSVCONFIG_VAL 0x88778877
>> +
>> +/* Clock Gating Control (CGCONTROL) register */
>> +#define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */
>> +#define SCG_CG_EN (1 << 2) /* Scheduler clock gating */
>> +#define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock
>> gating */
>> +#define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock
>> gating */
>> +#define DMC_INTERNAL_CG (MEMIF_CG_EN | SCG_CG_EN | \
>> + BUSIF_WR_CG_EN | BUSIF_RD_CG_EN)
>> +
>> +/* DMC PHY Control0 register */
>> +#define PHY_CONTROL0_RESET_VAL 0x0
>> +#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
>> +#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
>> +#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating
>> signal */
>> +#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
>> +
>> +/* Driver strength for CK, CKE, CS & CA */
>> +#define IMP_OUTPUT_DRV_40_OHM 0x5
>> +#define IMP_OUTPUT_DRV_30_OHM 0x7
>> +#define DA_3_DS_OFFSET 25
>> +#define DA_2_DS_OFFSET 22
>> +#define DA_1_DS_OFFSET 19
>> +#define DA_0_DS_OFFSET 16
>> +#define CA_CK_DRVR_DS_OFFSET 9
>> +#define CA_CKE_DRVR_DS_OFFSET 6
>> +#define CA_CS_DRVR_DS_OFFSET 3
>> +#define CA_ADR_DRVR_DS_OFFSET 0
>> +
>> +#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
>> +#define PHY_CON42_CTRL_RDLAT_SHIFT 0
>> +
>> +/*
>> + * Definitions that differ with SoC's.
>> + * Below is the part defining macros for smdk5250.
>> + * Else part introduces macros for smdk5420.
>> + */
>> +#ifndef CONFIG_SMDK5420
>> +
>> +/* APLL_CON1 */
>> +#define APLL_CON1_VAL (0x00203800)
>> +
>> +/* MPLL_CON1 */
>> +#define MPLL_CON1_VAL (0x00203800)
>> +
>> +/* CPLL_CON1 */
>> +#define CPLL_CON1_VAL (0x00203800)
>> +
>> +/* DPLL_CON1 */
>> +#define DPLL_CON1_VAL (NOT_AVAILABLE)
>> +
>> +/* GPLL_CON1 */
>> +#define GPLL_CON1_VAL (0x00203800)
>> +
>> +/* EPLL_CON1, CON2 */
>> +#define EPLL_CON1_VAL 0x00000000
>> +#define EPLL_CON2_VAL 0x00000080
>> +
>> +/* VPLL_CON1, CON2 */
>> +#define VPLL_CON1_VAL 0x00000000
>> +#define VPLL_CON2_VAL 0x00000080
>> +
>> +/* RPLL_CON1, CON2 */
>> +#define RPLL_CON1_VAL NOT_AVAILABLE
>> +#define RPLL_CON2_VAL NOT_AVAILABLE
>> +
>> +/* BPLL_CON1 */
>> +#define BPLL_CON1_VAL 0x00203800
>> +
>> +/* SPLL_CON1 */
>> +#define SPLL_CON1_VAL NOT_AVAILABLE
>> +
>> +/* IPLL_CON1 */
>> +#define IPLL_CON1_VAL NOT_AVAILABLE
>> +
>> +/* KPLL_CON1 */
>> +#define KPLL_CON1_VAL NOT_AVAILABLE
>> +
>> +/* CLK_SRC_ISP */
>> +#define CLK_SRC_ISP_VAL NOT_AVAILABLE
>> +#define CLK_DIV_ISP0_VAL 0x31
>> +#define CLK_DIV_ISP1_VAL 0x0
>> +
>> +/* CLK_FSYS */
>> +#define CLK_SRC_FSYS0_VAL 0x66666
>> +#define CLK_DIV_FSYS0_VAL 0x0BB00000
>> +#define CLK_DIV_FSYS1_VAL NOT_AVAILABLE
>> +#define CLK_DIV_FSYS2_VAL NOT_AVAILABLE
>> +
>> +/* CLK_SRC_CPU */
>> +/* 0 = MOUTAPLL, 1 = SCLKMPLL */
>> +#define MUX_HPM_SEL 0
>> +#define MUX_CPU_SEL 0
>> +#define MUX_APLL_SEL 1
>> +
>> +#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
>> + | (MUX_CPU_SEL << 16) \
>> + | (MUX_APLL_SEL))
>> +
>> /* CLK_SRC_CDREX */
>> #define CLK_SRC_CDREX_VAL 0x1
>>
>> /* CLK_DIV_CDREX */
>> +#define CLK_DIV_CDREX0_VAL NOT_AVAILABLE
>> +#define CLK_DIV_CDREX1_VAL NOT_AVAILABLE
>> +
>> +/* CLK_DIV_CPU0_VAL */
>> +#define CLK_DIV_CPU0_VAL NOT_AVAILABLE
>> +
>> #define MCLK_CDREX2_RATIO 0x0
>> #define ACLK_EFCON_RATIO 0x1
>> #define MCLK_DPHY_RATIO 0x1
>> @@ -247,6 +587,11 @@
>> | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
>> | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
>>
>> +#define CLK_SRC_TOP4_VAL NOT_AVAILABLE
>> +#define CLK_SRC_TOP5_VAL NOT_AVAILABLE
>> +#define CLK_SRC_TOP6_VAL NOT_AVAILABLE
>> +#define CLK_SRC_TOP7_VAL NOT_AVAILABLE
>> +
>> /* CLK_DIV_TOP0 */
>> #define ACLK_300_DISP1_RATIO 0x2
>> #define ACLK_400_G3D_RATIO 0x0
>> @@ -279,40 +624,11 @@
>> | (ACLK_400_IOP_RATIO << 16) \
>> | (ACLK_300_GSCL_RATIO << 12))
>>
>> -/* APLL_LOCK */
>> -#define APLL_LOCK_VAL (0x546)
>> -/* MPLL_LOCK */
>> -#define MPLL_LOCK_VAL (0x546)
>> -/* CPLL_LOCK */
>> -#define CPLL_LOCK_VAL (0x546)
>> -/* GPLL_LOCK */
>> -#define GPLL_LOCK_VAL (0x546)
>> -/* EPLL_LOCK */
>> -#define EPLL_LOCK_VAL (0x3A98)
>> -/* VPLL_LOCK */
>> -#define VPLL_LOCK_VAL (0x3A98)
>> -/* BPLL_LOCK */
>> -#define BPLL_LOCK_VAL (0x546)
>> +#define CLK_DIV_TOP2_VAL NOT_AVAILABLE
>>
>> -#define MUX_APLL_SEL_MASK (1 << 0)
>> -#define MUX_MPLL_SEL_MASK (1 << 8)
>> -#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
>> -#define MUX_CPLL_SEL_MASK (1 << 8)
>> -#define MUX_EPLL_SEL_MASK (1 << 12)
>> -#define MUX_VPLL_SEL_MASK (1 << 16)
>> -#define MUX_GPLL_SEL_MASK (1 << 28)
>> -#define MUX_BPLL_SEL_MASK (1 << 0)
>> -#define MUX_HPM_SEL_MASK (1 << 20)
>> -#define HPM_SEL_SCLK_MPLL (1 << 21)
>> -#define APLL_CON0_LOCKED (1 << 29)
>> -#define MPLL_CON0_LOCKED (1 << 29)
>> -#define BPLL_CON0_LOCKED (1 << 29)
>> -#define CPLL_CON0_LOCKED (1 << 29)
>> -#define EPLL_CON0_LOCKED (1 << 29)
>> -#define GPLL_CON0_LOCKED (1 << 29)
>> -#define VPLL_CON0_LOCKED (1 << 29)
>> -#define CLK_REG_DISABLE 0x0
>> -#define TOP2_VAL 0x0110000
>> +/* PLL Lock Value Factor */
>> +#define PLL_LOCK_FACTOR 250
>> +#define PLL_X_LOCK_FACTOR 3000
>>
>> /* CLK_SRC_PERIC0 */
>> #define PWM_SEL 6
>> @@ -336,18 +652,6 @@
>> | (SPI1_SEL << 20) \
>> | (SPI0_SEL << 16))
>>
>> -/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
>> -#define SPI0_ISP_SEL 6
>> -#define SPI1_ISP_SEL 6
>> -#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
>> - | (SPI0_ISP_SEL << 0)
>> -
>> -/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
>> -#define SPI0_ISP_RATIO 0xf
>> -#define SPI1_ISP_RATIO 0xf
>> -#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
>> - | (SPI0_ISP_RATIO << 0)
>> -
>> /* CLK_DIV_PERIL0 */
>> #define UART5_RATIO 7
>> #define UART4_RATIO 7
>> @@ -380,105 +684,200 @@
>> #define PWM_RATIO 8
>> #define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
>>
>> -/* CLK_DIV_FSYS2 */
>> -#define MMC2_RATIO_MASK 0xf
>> -#define MMC2_RATIO_VAL 0x3
>> -#define MMC2_RATIO_OFFSET 0
>>
>> -#define MMC2_PRE_RATIO_MASK 0xff
>> -#define MMC2_PRE_RATIO_VAL 0x9
>> -#define MMC2_PRE_RATIO_OFFSET 8
>> +/* CLK_DIV_PERIC4 */
>> +#define CLK_DIV_PERIC4_VAL NOT_AVAILABLE
>>
>> -#define MMC3_RATIO_MASK 0xf
>> -#define MMC3_RATIO_VAL 0x1
>> -#define MMC3_RATIO_OFFSET 16
>> +/* CLK_SRC_DISP1_0 */
>> +#define CLK_SRC_DISP1_0_VAL 0x6
>> +#define CLK_DIV_DISP1_0_VAL NOT_AVAILABLE
>>
>> -#define MMC3_PRE_RATIO_MASK 0xff
>> -#define MMC3_PRE_RATIO_VAL 0x0
>> -#define MMC3_PRE_RATIO_OFFSET 24
>> +#define APLL_FOUT (1 << 0)
>> +#define KPLL_FOUT NOT_AVAILABLE
>>
>> -/* CLK_SRC_LEX */
>> -#define CLK_SRC_LEX_VAL 0x0
>> +#define CLK_DIV_CPERI1_VAL NOT_AVAILABLE
>>
>> -/* CLK_DIV_LEX */
>> -#define CLK_DIV_LEX_VAL 0x10
>> +#else
>>
>> -/* CLK_DIV_R0X */
>> -#define CLK_DIV_R0X_VAL 0x10
>> +/* APLL_CON1 */
>> +#define APLL_CON1_VAL (0x0020F300)
>>
>> -/* CLK_DIV_L0X */
>> -#define CLK_DIV_R1X_VAL 0x10
>> +/* MPLL_CON1 */
>> +#define MPLL_CON1_VAL (0x0020F300)
>>
>> -/* CLK_DIV_ISP0 */
>> -#define CLK_DIV_ISP0_VAL 0x31
>>
>> -/* CLK_DIV_ISP1 */
>> -#define CLK_DIV_ISP1_VAL 0x0
>> +/* CPLL_CON1 */
>> +#define CPLL_CON1_VAL 0x0020f300
>>
>> -/* CLK_DIV_ISP2 */
>> -#define CLK_DIV_ISP2_VAL 0x1
>> +/* DPLL_CON1 */
>> +#define DPLL_CON1_VAL (0x0020F300)
>>
>> -/* CLK_SRC_DISP1_0 */
>> -#define CLK_SRC_DISP1_0_VAL 0x6
>> +/* GPLL_CON1 */
>> +#define GPLL_CON1_VAL (NOT_AVAILABLE)
>>
>> -/*
>> - * DIV_DISP1_0
>> - * For DP, divisor should be 2
>> - */
>> -#define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
>>
>> -/* CLK_GATE_IP_DISP1 */
>> -#define CLK_GATE_DP1_ALLOW (1 << 4)
>> +/* EPLL_CON1, CON2 */
>> +#define EPLL_CON1_VAL 0x00000000
>> +#define EPLL_CON2_VAL 0x00000080
>>
>> -#define DDR3PHY_CTRL_PHY_RESET (1 << 0)
>> -#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
>> +/* VPLL_CON1, CON2 */
>> +#define VPLL_CON1_VAL 0x0020f300
>> +#define VPLL_CON2_VAL NOT_AVAILABLE
>>
>> -#define PHY_CON0_RESET_VAL 0x17020a40
>> -#define P0_CMD_EN (1 << 14)
>> -#define BYTE_RDLVL_EN (1 << 13)
>> -#define CTRL_SHGATE (1 << 8)
>> +/* RPLL_CON1, CON2 */
>> +#define RPLL_CON1_VAL 0x00000000
>> +#define RPLL_CON2_VAL 0x00000080
>>
>> -#define PHY_CON1_RESET_VAL 0x09210100
>> -#define CTRL_GATEDURADJ_MASK (0xf << 20)
>> +/* BPLL_CON1 */
>> +#define BPLL_CON1_VAL 0x0020f300
>>
>> -#define PHY_CON2_RESET_VAL 0x00010004
>> -#define INIT_DESKEW_EN (1 << 6)
>> -#define RDLVL_GATE_EN (1 << 24)
>> +/* SPLL_CON1 */
>> +#define SPLL_CON1_VAL 0x0020f300
>>
>> -/*ZQ Configurations */
>> -#define PHY_CON16_RESET_VAL 0x08000304
>> +/* IPLL_CON1 */
>> +#define IPLL_CON1_VAL 0x00000080
>>
>> -#define ZQ_CLK_DIV_EN (1 << 18)
>> -#define ZQ_MANUAL_STR (1 << 1)
>> -#define ZQ_DONE (1 << 0)
>> +/* KPLL_CON1 */
>> +#define KPLL_CON1_VAL 0x200000
>>
>> -#define CTRL_RDLVL_GATE_ENABLE 1
>> -#define CTRL_RDLVL_GATE_DISABLE 1
>> +/* CLK_SRC_ISP */
>> +#define CLK_SRC_ISP_VAL 0x33366000
>> +#define CLK_DIV_ISP0_VAL 0x13131300
>> +#define CLK_DIV_ISP1_VAL 0xbb110202
>>
>> -/* Direct Command */
>> -#define DIRECT_CMD_NOP 0x07000000
>> -#define DIRECT_CMD_PALL 0x01000000
>> -#define DIRECT_CMD_ZQINIT 0x0a000000
>> -#define DIRECT_CMD_CHANNEL_SHIFT 28
>> -#define DIRECT_CMD_CHIP_SHIFT 20
>>
>> -/* DMC PHY Control0 register */
>> -#define PHY_CONTROL0_RESET_VAL 0x0
>> -#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
>> -#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
>> -#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating
>> signal */
>> -#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
>> +/* CLK_FSYS */
>> +#define CLK_SRC_FSYS0_VAL 0x33033300
>> +#define CLK_DIV_FSYS0_VAL 0x0
>> +#define CLK_DIV_FSYS1_VAL 0x04f13c4f
>> +#define CLK_DIV_FSYS2_VAL 0x041d0000
>> +
>> +/* CLK_SRC_CPU */
>> +/* 0 = MOUTAPLL, 1 = SCLKMPLL */
>> +#define MUX_HPM_SEL 1
>> +#define MUX_CPU_SEL 0
>> +#define MUX_APLL_SEL 1
>>
>> -/* Driver strength for CK, CKE, CS & CA */
>> -#define IMP_OUTPUT_DRV_40_OHM 0x5
>> -#define IMP_OUTPUT_DRV_30_OHM 0x7
>> -#define CA_CK_DRVR_DS_OFFSET 9
>> -#define CA_CKE_DRVR_DS_OFFSET 6
>> -#define CA_CS_DRVR_DS_OFFSET 3
>> -#define CA_ADR_DRVR_DS_OFFSET 0
>> +#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
>> + | (MUX_CPU_SEL << 16) \
>> + | (MUX_APLL_SEL))
>>
>> -#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
>> -#define PHY_CON42_CTRL_RDLAT_SHIFT 0
>> +/* CLK_SRC_CDREX */
>> +#define CLK_SRC_CDREX_VAL 0x00000011
>> +
>> +/* CLK_DIV_CDREX */
>> +#define CLK_DIV_CDREX0_VAL 0x30010100
>> +#define CLK_DIV_CDREX1_VAL 0x300
>> +
>> +#define CLK_DIV_CDREX_VAL 0x17010100
>> +
>> +/* CLK_DIV_CPU0_VAL */
>> +#define CLK_DIV_CPU0_VAL 0x01440020
>> +
>> +/* CLK_SRC_TOP */
>> +#define CLK_SRC_TOP0_VAL 0x12221222
>> +#define CLK_SRC_TOP1_VAL 0x00100200
>> +#define CLK_SRC_TOP2_VAL 0x11101000
>> +#define CLK_SRC_TOP3_VAL 0x11111111
>> +#define CLK_SRC_TOP4_VAL 0x11110111
>> +#define CLK_SRC_TOP5_VAL 0x11111100
>> +#define CLK_SRC_TOP6_VAL 0x11110111
>> +#define CLK_SRC_TOP7_VAL 0x00022200
>> +
>> +/* CLK_DIV_TOP */
>> +#define CLK_DIV_TOP0_VAL 0x23712311
>> +#define CLK_DIV_TOP1_VAL 0x13100B00
>> +#define CLK_DIV_TOP2_VAL 0x11101100
>> +
>> +/* PLL Lock Value Factor */
>> +#define PLL_LOCK_FACTOR 200
>> +#define PLL_X_LOCK_FACTOR 3000
>> +
>> +/* CLK_SRC_PERIC0 */
>> +#define SPDIF_SEL 1
>> +#define PWM_SEL 3
>> +#define UART4_SEL 3
>> +#define UART3_SEL 3
>> +#define UART2_SEL 3
>> +#define UART1_SEL 3
>> +#define UART0_SEL 3
>> +/* SRC_CLOCK = SCLK_RPLL */
>> +#define CLK_SRC_PERIC0_VAL ((SPDIF_SEL << 28) \
>> + | (PWM_SEL << 24) \
>> + | (UART4_SEL << 20) \
>> + | (UART3_SEL << 16) \
>> + | (UART2_SEL << 12) \
>> + | (UART1_SEL << 8) \
>> + | (UART0_SEL << 4))
>> +
>> +/* CLK_SRC_PERIC1 */
>> +/* SRC_CLOCK = SCLK_EPLL */
>> +#define SPI0_SEL 6
>> +#define SPI1_SEL 6
>> +#define SPI2_SEL 6
>> +#define AUDIO0_SEL 6
>> +#define AUDIO1_SEL 6
>> +#define AUDIO2_SEL 6
>> +#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 28) \
>> + | (SPI1_SEL << 24) \
>> + | (SPI0_SEL << 20) \
>> + | (AUDIO2_SEL << 16) \
>> + | (AUDIO2_SEL << 12) \
>> + | (AUDIO2_SEL << 8))
>> +
>> +/* CLK_DIV_PERIC0 */
>> +#define PWM_RATIO 8
>> +#define UART4_RATIO 9
>> +#define UART3_RATIO 9
>> +#define UART2_RATIO 9
>> +#define UART1_RATIO 9
>> +#define UART0_RATIO 9
>> +
>> +#define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \
>> + | (UART4_RATIO << 24) \
>> + | (UART3_RATIO << 20) \
>> + | (UART2_RATIO << 16) \
>> + | (UART1_RATIO << 12) \
>> + | (UART0_RATIO << 8))
>> +/* CLK_DIV_PERIC1 */
>> +#define SPI2_RATIO 0x1
>> +#define SPI1_RATIO 0x1
>> +#define SPI0_RATIO 0x1
>> +#define CLK_DIV_PERIC1_VAL ((SPI2_RATIO << 28) \
>> + | (SPI1_RATIO << 24) \
>> + | (SPI0_RATIO << 20))
>> +
>> +/* CLK_DIV_PERIC2 */
>> +#define PCM2_RATIO 0x3
>> +#define PCM1_RATIO 0x3
>> +#define CLK_DIV_PERIC2_VAL ((PCM2_RATIO << 24) \
>> + | (PCM1_RATIO << 16))
>> +
>> +/* CLK_DIV_PERIC3 */
>> +#define AUDIO2_RATIO 0x5
>> +#define AUDIO1_RATIO 0x5
>> +#define AUDIO0_RATIO 0x5
>> +#define CLK_DIV_PERIC3_VAL ((AUDIO2_RATIO << 28) \
>> + | (AUDIO1_RATIO << 24) \
>> + | (AUDIO0_RATIO << 20))
>> +
>> +/* CLK_DIV_PERIC4 */
>> +#define SPI2_PRE_RATIO 0x2
>> +#define SPI1_PRE_RATIO 0x2
>> +#define SPI0_PRE_RATIO 0x2
>> +#define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \
>> + | (SPI1_PRE_RATIO << 16) \
>> + | (SPI0_PRE_RATIO << 8))
>> +
>> +/* CLK_SRC_DISP1_0 */
>> +#define CLK_SRC_DISP1_0_VAL 0x10666600
>> +#define CLK_DIV_DISP1_0_VAL 0x01050211
>> +
>> +#define APLL_FOUT (1 << 0)
>> +#define KPLL_FOUT (1 << 0)
>> +
>> +#define CLK_DIV_CPERI1_VAL 0x3f3f0000
>> +#endif
>>
>> struct mem_timings;
>>
>> @@ -490,7 +889,7 @@ enum {
>> };
>>
>> /*
>> - * Memory variant specific initialization code
>> + * Memory variant specific initialization code for DDR3
>> *
>> * @param mem Memory timings for this memory type.
>> * @param mem_iv_size Memory interleaving size is a configurable
>> parameter
>> @@ -503,6 +902,9 @@ enum {
>> int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
>> int reset);
>>
>> +/* Memory variant specific initialization code for LPDDR3 */
>> +void lpddr3_mem_ctrl_init(void);
>> +
>> /*
>> * Configure ZQ I/O interface
>> *
>> @@ -532,14 +934,6 @@ void dmc_config_mrs(struct mem_timings *mem, struct
>> exynos5_dmc *dmc);
>> void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc);
>>
>> /*
>> - * Configure the memconfig and membaseconfig registers
>> - *
>> - * @param mem Memory timings for this memory type.
>> - * @param exynos5_dmc Pointer to struct of DMC registers
>> - */
>> -void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc);
>> -
>> -/*
>> * Reset the DLL. This function is common between DDR3 and LPDDR2.
>> * However, the reset value is different. So we are passing a flag
>> * ddr_mode to distinguish between LPDDR2 and DDR3.
>> diff --git a/arch/arm/include/asm/arch-exynos/clk.h
>> b/arch/arm/include/asm/arch-exynos/clk.h
>> index 1d6fa93..cdeef32 100644
>> --- a/arch/arm/include/asm/arch-exynos/clk.h
>> +++ b/arch/arm/include/asm/arch-exynos/clk.h
>> @@ -14,6 +14,7 @@
>> #define HPLL 3
>> #define VPLL 4
>> #define BPLL 5
>> +#define RPLL 6
>>
>> enum pll_src_bit {
>> EXYNOS_SRC_MPLL = 6,
>> --
>> 1.7.12.4
>>
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
>>
>
>
>
> --
> from. prom.
> www.promsoft.net
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
--
Regards,
Rajeshwari Shinde
^ permalink raw reply [flat|nested] 37+ messages in thread* [U-Boot] [PATCH 03/10 V6] Exynos5420: Add clock initialization for 5420
2013-11-13 11:17 ` Rajeshwari Birje
@ 2013-11-14 1:56 ` Minkyu Kang
0 siblings, 0 replies; 37+ messages in thread
From: Minkyu Kang @ 2013-11-14 1:56 UTC (permalink / raw)
To: u-boot
Dear Rajeshwari,
On 13 November 2013 20:17, Rajeshwari Birje <rajeshwari.birje@gmail.com>wrote:
> Hi Minkyu Kang,
>
> Thank you for comments,
>
> On Wed, Nov 13, 2013 at 8:15 AM, Minkyu Kang <promsoft@gmail.com> wrote:
> > Dear Rajeshwari S Shinde,
> >
> >
> > On 29 October 2013 16:23, Rajeshwari S Shinde <rajeshwari.s@samsung.com
> >wrote:
> >
> >> This patch adds code for clock initialization and clock settings
> >> of various IP's and controllers, required for Exynos5420
> >>
> >> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
> >> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
> >> Acked-by: Simon Glass <sjg@chromium.org>
> >> ---
> >> Changes in V2:
> >> - None
> >> Changes in V3:
> >> - None
> >> Changes in V4:
> >> - Corrected the multiline commenting style
> >> Changes in V5:
> >> - None
> >> Changes in V6:
> >> - None
> >> arch/arm/cpu/armv7/exynos/clock.c | 270 ++++++++-
> >> arch/arm/cpu/armv7/exynos/clock_init.h | 17 +
> >> arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 352 +++++++++++-
> >> arch/arm/cpu/armv7/exynos/exynos5_setup.h | 740
> >> +++++++++++++++++++------
> >> arch/arm/include/asm/arch-exynos/clk.h | 1 +
> >> arch/arm/include/asm/arch-exynos/clock.h | 494 +++++++++++++++++
> >> 6 files changed, 1673 insertions(+), 201 deletions(-)
> >>
> >> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
> >> b/arch/arm/cpu/armv7/exynos/clock.c
> >> index 36fedd6..b52e61a 100644
> >> --- a/arch/arm/cpu/armv7/exynos/clock.c
> >> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> >> @@ -96,7 +96,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int
> >> r, unsigned int k)
> >>
> >> freq = CONFIG_SYS_CLK_FREQ;
> >>
> >> - if (pllreg == EPLL) {
> >> + if (pllreg == EPLL || pllreg == RPLL) {
> >> k = k & 0xffff;
> >> /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
> >> fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 <<
> s)));
> >> @@ -117,7 +117,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned
> int
> >> r, unsigned int k)
> >> div = PLL_DIV_1024;
> >> else if (proid_is_exynos4412())
> >> div = PLL_DIV_65535;
> >> - else if (proid_is_exynos5250())
> >> + else if (cpu_is_exynos5())
> >>
> >
> > please don't mix proid_is... and cpu_is...
> Since both 5420 and 5250 need same value added cpu_is_exynos5(),
> instead of doing a or of both.
>
I know, but this if statement for proid..
then, you should use same statement.
you can do this.
else if (proid_is_exynos5250() || prois_is_exynos5420())
or
if (cpu_is_exynos4()) {
if (proid_is....) {
} else if (proid_is....) {
}
} else if (cpu_is_exynos5()) {
.....
}
Thanks,
Minkyu Kang.
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 37+ messages in thread
* [U-Boot] [PATCH 04/10 V6] Exynos5420: Add DDR3 initialization for 5420
2013-10-29 7:23 [U-Boot] [PATCH 00/10 V6] EXYNOS5420: Add SMDK5420 board support Rajeshwari S Shinde
` (2 preceding siblings ...)
2013-10-29 7:23 ` [U-Boot] [PATCH 03/10 V6] Exynos5420: Add clock initialization " Rajeshwari S Shinde
@ 2013-10-29 7:23 ` Rajeshwari S Shinde
2013-11-13 3:24 ` Minkyu Kang
2013-10-29 7:23 ` [U-Boot] [PATCH 05/10 V6] Exynos5420: Add support for 5420 in pinmux and gpio Rajeshwari S Shinde
` (6 subsequent siblings)
10 siblings, 1 reply; 37+ messages in thread
From: Rajeshwari S Shinde @ 2013-10-29 7:23 UTC (permalink / raw)
To: u-boot
This patch intends to add DDR3 initialization code for Exynos5420.
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in V2:
- Corrected a compilation issue for SMDK5250.
Changes in V3:
- None
Changes in V4:
- None
Changes in V5:
- None
Changes in V6:
- None
arch/arm/cpu/armv7/exynos/dmc_common.c | 10 +-
arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 421 +++++++++++++++++++++++++++++-
arch/arm/include/asm/arch-exynos/cpu.h | 4 +
arch/arm/include/asm/arch-exynos/dmc.h | 121 ++++++---
4 files changed, 511 insertions(+), 45 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/dmc_common.c b/arch/arm/cpu/armv7/exynos/dmc_common.c
index 53cfe6e..9e432c2 100644
--- a/arch/arm/cpu/armv7/exynos/dmc_common.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_common.c
@@ -1,5 +1,5 @@
/*
- * Mem setup common file for different types of DDR present on SMDK5250 boards.
+ * Mem setup common file for different types of DDR present on Exynos boards.
*
* Copyright (C) 2012 Samsung Electronics
*
@@ -152,14 +152,6 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc)
}
}
-void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)
-{
- writel(mem->memconfig, &dmc->memconfig0);
- writel(mem->memconfig, &dmc->memconfig1);
- writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0);
- writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
-}
-
void mem_ctrl_init(int reset)
{
struct spl_machine_param *param = spl_get_machine_params();
diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
index 5f5914e..3fab50b 100644
--- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
@@ -1,5 +1,5 @@
/*
- * DDR3 mem setup file for SMDK5250 board based on EXYNOS5
+ * DDR3 mem setup file for board based on EXYNOS5
*
* Copyright (C) 2012 Samsung Electronics
*
@@ -15,8 +15,9 @@
#include "exynos5_setup.h"
#include "clock_init.h"
-#define RDLVL_COMPLETE_TIMEOUT 10000
+#define TIMEOUT 10000
+#ifdef CONFIG_EXYNOS5250
static void reset_phy_ctrl(void)
{
struct exynos5_clock *clk =
@@ -108,7 +109,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
/* Precharge Configuration */
writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
- &dmc->prechconfig);
+ &dmc->prechconfig0);
/* Power Down mode Configuration */
writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
@@ -174,7 +175,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
writel(val, &phy1_ctrl->phy_con1);
writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
- i = RDLVL_COMPLETE_TIMEOUT;
+ i = TIMEOUT;
while ((readl(&dmc->phystatus) &
(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
@@ -215,3 +216,415 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
| (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);
return 0;
}
+#endif
+
+#ifdef CONFIG_EXYNOS5420
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+ int reset)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)EXYNOS5_CLOCK_BASE;
+ struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
+ struct exynos5_dmc *drex0, *drex1;
+ struct exynos5_tzasc *tzasc0, *tzasc1;
+ uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1;
+ int chip;
+ int i;
+
+ phy0_ctrl = (struct exynos5_phy_control *)samsung_get_base_dmc_phy();
+ phy1_ctrl = (struct exynos5_phy_control *)(samsung_get_base_dmc_phy()
+ + DMC_OFFSET);
+ drex0 = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl();
+ drex1 = (struct exynos5_dmc *)(samsung_get_base_dmc_ctrl()
+ + DMC_OFFSET);
+ tzasc0 = (struct exynos5_tzasc *)EXYNOS5420_DMC_TZASC0_BASE;
+ tzasc1 = (struct exynos5_tzasc *)EXYNOS5420_DMC_TZASC1_BASE;
+
+ /* Enable PAUSE for DREX */
+ setbits_le32(&clk->pause, ENABLE_BIT);
+
+ /* Enable BYPASS mode */
+ setbits_le32(&clk->bpll_con1, BYPASS_EN);
+
+ writel(MUX_BPLL_SEL_FOUTBPLL, &clk->src_cdrex);
+ do {
+ val = readl(&clk->mux_stat_cdrex);
+ val &= BPLL_SEL_MASK;
+ } while (val != FOUTBPLL);
+
+ clrbits_le32(&clk->bpll_con1, BYPASS_EN);
+
+ /* Specify the DDR memory type as DDR3 */
+ val = readl(&phy0_ctrl->phy_con0);
+ val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
+ val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
+ writel(val, &phy0_ctrl->phy_con0);
+
+ val = readl(&phy1_ctrl->phy_con0);
+ val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
+ val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
+ writel(val, &phy1_ctrl->phy_con0);
+
+ /* Set Read Latency and Burst Length for PHY0 and PHY1 */
+ val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
+ (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
+ writel(val, &phy0_ctrl->phy_con42);
+ writel(val, &phy1_ctrl->phy_con42);
+
+ val = readl(&phy0_ctrl->phy_con26);
+ val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
+ val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
+ writel(val, &phy0_ctrl->phy_con26);
+
+ val = readl(&phy1_ctrl->phy_con26);
+ val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
+ val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
+ writel(val, &phy1_ctrl->phy_con26);
+
+ /*
+ * Set Driver strength for CK, CKE, CS & CA to 0x7
+ * Set Driver strength for Data Slice 0~3 to 0x7
+ */
+ val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 << CA_CKE_DRVR_DS_OFFSET) |
+ (0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET);
+ val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) |
+ (0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET);
+ writel(val, &phy0_ctrl->phy_con39);
+ writel(val, &phy1_ctrl->phy_con39);
+
+ /* ZQ Calibration */
+ if (dmc_config_zq(mem, phy0_ctrl, phy1_ctrl))
+ return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
+
+ clrbits_le32(&phy0_ctrl->phy_con16, ZQ_CLK_DIV_EN);
+ clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN);
+
+ /* DQ Signal */
+ val = readl(&phy0_ctrl->phy_con14);
+ val |= mem->phy0_pulld_dqs;
+ writel(val, &phy0_ctrl->phy_con14);
+ val = readl(&phy1_ctrl->phy_con14);
+ val |= mem->phy1_pulld_dqs;
+ writel(val, &phy1_ctrl->phy_con14);
+
+ val = MEM_TERM_EN | PHY_TERM_EN;
+ writel(val, &drex0->phycontrol0);
+ writel(val, &drex1->phycontrol0);
+
+ writel(mem->concontrol |
+ (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
+ (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
+ &drex0->concontrol);
+ writel(mem->concontrol |
+ (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
+ (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
+ &drex1->concontrol);
+
+ do {
+ val = readl(&drex0->phystatus);
+ } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
+ do {
+ val = readl(&drex1->phystatus);
+ } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
+
+ clrbits_le32(&drex0->concontrol, DFI_INIT_START);
+ clrbits_le32(&drex1->concontrol, DFI_INIT_START);
+
+ update_reset_dll(drex0, DDR_MODE_DDR3);
+ update_reset_dll(drex1, DDR_MODE_DDR3);
+
+ /*
+ * Set Base Address:
+ * 0x2000_0000 ~ 0x5FFF_FFFF
+ * 0x6000_0000 ~ 0x9FFF_FFFF
+ */
+ /* MEMBASECONFIG0 */
+ val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_0) |
+ DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
+ writel(val, &tzasc0->membaseconfig0);
+ writel(val, &tzasc1->membaseconfig0);
+
+ /* MEMBASECONFIG1 */
+ val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_1) |
+ DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
+ writel(val, &tzasc0->membaseconfig1);
+ writel(val, &tzasc1->membaseconfig1);
+
+ /*
+ * Memory Channel Inteleaving Size
+ * Ares Channel interleaving = 128 bytes
+ */
+ /* MEMCONFIG0/1 */
+ writel(mem->memconfig, &tzasc0->memconfig0);
+ writel(mem->memconfig, &tzasc1->memconfig0);
+ writel(mem->memconfig, &tzasc0->memconfig1);
+ writel(mem->memconfig, &tzasc1->memconfig1);
+
+ /* Precharge Configuration */
+ writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
+ &drex0->prechconfig0);
+ writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
+ &drex1->prechconfig0);
+
+ /*
+ * TimingRow, TimingData, TimingPower and Timingaref
+ * values as per Memory AC parameters
+ */
+ writel(mem->timing_ref, &drex0->timingref);
+ writel(mem->timing_ref, &drex1->timingref);
+ writel(mem->timing_row, &drex0->timingrow);
+ writel(mem->timing_row, &drex1->timingrow);
+ writel(mem->timing_data, &drex0->timingdata);
+ writel(mem->timing_data, &drex1->timingdata);
+ writel(mem->timing_power, &drex0->timingpower);
+ writel(mem->timing_power, &drex1->timingpower);
+
+ if (reset) {
+ /*
+ * Send NOP, MRS and ZQINIT commands
+ * Sending MRS command will reset the DRAM. We should not be
+ * reseting the DRAM after resume, this will lead to memory
+ * corruption as DRAM content is lost after DRAM reset
+ */
+ dmc_config_mrs(mem, drex0);
+ dmc_config_mrs(mem, drex1);
+ } else {
+ /*
+ * During Suspend-Resume & S/W-Reset, as soon as PMU releases
+ * pad retention, CKE goes high. This causes memory contents
+ * not to be retained during DRAM initialization. Therfore,
+ * there is a new control register(0x100431e8[28]) which lets us
+ * release pad retention and retain the memory content until the
+ * initialization is complete.
+ */
+ writel(PAD_RETENTION_DRAM_COREBLK_VAL,
+ PAD_RETENTION_DRAM_COREBLK_OPTION);
+ do {
+ val = readl(PAD_RETENTION_DRAM_STATUS);
+ } while (val != 0x1);
+
+ /*
+ * CKE PAD retention disables DRAM self-refresh mode.
+ * Send auto refresh command for DRAM refresh.
+ */
+ for (i = 0; i < 128; i++) {
+ for (chip = 0; chip < mem->chips_to_configure; chip++) {
+ writel(DIRECT_CMD_REFA |
+ (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex0->directcmd);
+ writel(DIRECT_CMD_REFA |
+ (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex1->directcmd);
+ }
+ }
+ }
+
+ if (mem->gate_leveling_enable) {
+ writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0);
+ writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0);
+
+ setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN);
+ setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN);
+
+ val = PHY_CON2_RESET_VAL;
+ val |= INIT_DESKEW_EN;
+ writel(val, &phy0_ctrl->phy_con2);
+ writel(val, &phy1_ctrl->phy_con2);
+
+ val = readl(&phy0_ctrl->phy_con1);
+ val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
+ writel(val, &phy0_ctrl->phy_con1);
+
+ val = readl(&phy1_ctrl->phy_con1);
+ val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
+ writel(val, &phy1_ctrl->phy_con1);
+
+ n_lock_r = readl(&phy0_ctrl->phy_con13);
+ n_lock_w_phy0 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2;
+ n_lock_r = readl(&phy0_ctrl->phy_con12);
+ n_lock_r &= ~CTRL_DLL_ON;
+ n_lock_r |= n_lock_w_phy0;
+ writel(n_lock_r, &phy0_ctrl->phy_con12);
+
+ n_lock_r = readl(&phy1_ctrl->phy_con13);
+ n_lock_w_phy1 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2;
+ n_lock_r = readl(&phy1_ctrl->phy_con12);
+ n_lock_r &= ~CTRL_DLL_ON;
+ n_lock_r |= n_lock_w_phy1;
+ writel(n_lock_r, &phy1_ctrl->phy_con12);
+
+ val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
+ for (chip = 0; chip < mem->chips_to_configure; chip++) {
+ writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex0->directcmd);
+ writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex1->directcmd);
+ }
+
+ setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN);
+ setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN);
+
+ setbits_le32(&phy0_ctrl->phy_con0, CTRL_SHGATE);
+ setbits_le32(&phy1_ctrl->phy_con0, CTRL_SHGATE);
+
+ val = readl(&phy0_ctrl->phy_con1);
+ val &= ~(CTRL_GATEDURADJ_MASK);
+ writel(val, &phy0_ctrl->phy_con1);
+
+ val = readl(&phy1_ctrl->phy_con1);
+ val &= ~(CTRL_GATEDURADJ_MASK);
+ writel(val, &phy1_ctrl->phy_con1);
+
+ writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config);
+ i = TIMEOUT;
+ while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) !=
+ RDLVL_COMPLETE_CHO) && (i > 0)) {
+ /*
+ * TODO(waihong): Comment on how long this take to
+ * timeout
+ */
+ sdelay(100);
+ i--;
+ }
+ if (!i)
+ return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
+ writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config);
+
+ writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config);
+ i = TIMEOUT;
+ while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) !=
+ RDLVL_COMPLETE_CHO) && (i > 0)) {
+ /*
+ * TODO(waihong): Comment on how long this take to
+ * timeout
+ */
+ sdelay(100);
+ i--;
+ }
+ if (!i)
+ return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
+ writel(CTRL_RDLVL_GATE_DISABLE, &drex1->rdlvl_config);
+
+ writel(0, &phy0_ctrl->phy_con14);
+ writel(0, &phy1_ctrl->phy_con14);
+
+ val = (0x3 << DIRECT_CMD_BANK_SHIFT);
+ for (chip = 0; chip < mem->chips_to_configure; chip++) {
+ writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex0->directcmd);
+ writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex1->directcmd);
+ }
+
+ if (mem->read_leveling_enable) {
+ /* Set Read DQ Calibration */
+ val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
+ for (chip = 0; chip < mem->chips_to_configure; chip++) {
+ writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex0->directcmd);
+ writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex1->directcmd);
+ }
+
+ val = readl(&phy0_ctrl->phy_con1);
+ val |= READ_LEVELLING_DDR3;
+ writel(val, &phy0_ctrl->phy_con1);
+ val = readl(&phy1_ctrl->phy_con1);
+ val |= READ_LEVELLING_DDR3;
+ writel(val, &phy1_ctrl->phy_con1);
+
+ val = readl(&phy0_ctrl->phy_con2);
+ val |= (RDLVL_EN | RDLVL_INCR_ADJ);
+ writel(val, &phy0_ctrl->phy_con2);
+ val = readl(&phy1_ctrl->phy_con2);
+ val |= (RDLVL_EN | RDLVL_INCR_ADJ);
+ writel(val, &phy1_ctrl->phy_con2);
+
+ setbits_le32(&drex0->rdlvl_config,
+ CTRL_RDLVL_DATA_ENABLE);
+ i = TIMEOUT;
+ while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO)
+ != RDLVL_COMPLETE_CHO) && (i > 0)) {
+ /*
+ * TODO(waihong): Comment on how long this take
+ * to timeout
+ */
+ sdelay(100);
+ i--;
+ }
+ if (!i)
+ return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
+
+ clrbits_le32(&drex0->rdlvl_config,
+ CTRL_RDLVL_DATA_ENABLE);
+ setbits_le32(&drex1->rdlvl_config,
+ CTRL_RDLVL_DATA_ENABLE);
+ i = TIMEOUT;
+ while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO)
+ != RDLVL_COMPLETE_CHO) && (i > 0)) {
+ /*
+ * TODO(waihong): Comment on how long this take
+ * to timeout
+ */
+ sdelay(100);
+ i--;
+ }
+ if (!i)
+ return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
+
+ clrbits_le32(&drex1->rdlvl_config,
+ CTRL_RDLVL_DATA_ENABLE);
+
+ val = (0x3 << DIRECT_CMD_BANK_SHIFT);
+ for (chip = 0; chip < mem->chips_to_configure; chip++) {
+ writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex0->directcmd);
+ writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex1->directcmd);
+ }
+
+ update_reset_dll(drex0, DDR_MODE_DDR3);
+ update_reset_dll(drex1, DDR_MODE_DDR3);
+ }
+
+ /* Common Settings for Leveling */
+ val = PHY_CON12_RESET_VAL;
+ writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12);
+ writel((val + n_lock_w_phy1), &phy1_ctrl->phy_con12);
+
+ setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN);
+ setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN);
+ }
+
+ /* Send PALL command */
+ dmc_config_prech(mem, drex0);
+ dmc_config_prech(mem, drex1);
+
+ writel(mem->memcontrol, &drex0->memcontrol);
+ writel(mem->memcontrol, &drex1->memcontrol);
+
+ /*
+ * Set DMC Concontrol: Enable auto-refresh counter, provide
+ * read data fetch cycles and enable DREX auto set powerdown
+ * for input buffer of I/O in none read memory state.
+ */
+ writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
+ (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
+ DMC_CONCONTROL_IO_PD_CON(0x2),
+ &drex0->concontrol);
+ writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
+ (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
+ DMC_CONCONTROL_IO_PD_CON(0x2),
+ &drex1->concontrol);
+
+ /*
+ * Enable Clock Gating Control for DMC
+ * this saves around 25 mw dmc power as compared to the power
+ * consumption without these bits enabled
+ */
+ setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
+ setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index 10a2ac3..a75dccf 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -164,6 +164,10 @@
#define EXYNOS5420_ADC_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE
+#define PAD_RETENTION_DRAM_STATUS (EXYNOS5420_POWER_BASE + 0x3004)
+#define PAD_RETENTION_DRAM_COREBLK_OPTION (EXYNOS5420_POWER_BASE + 0x31E8)
+#define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000
+
#ifndef __ASSEMBLY__
#include <asm/io.h>
/* CPU detection macros */
diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h
index f65c676..b947de1 100644
--- a/arch/arm/include/asm/arch-exynos/dmc.h
+++ b/arch/arm/include/asm/arch-exynos/dmc.h
@@ -114,13 +114,22 @@ struct exynos4_dmc {
struct exynos5_dmc {
unsigned int concontrol;
unsigned int memcontrol;
+
+/* Between 5250 and 5420, the DMC Register differs only at 0x8 offset.
+ * So to use the same structure and simplify the code put a define to
+ * distinguish between memconfig0 and cgcontrol register */
+#ifdef CONFIG_EXYNOS5250
unsigned int memconfig0;
+#else
+ unsigned int cgcontrol;
+#endif
unsigned int memconfig1;
unsigned int directcmd;
- unsigned int prechconfig;
+ unsigned int prechconfig0;
unsigned int phycontrol0;
- unsigned char res1[0xc];
- unsigned int pwrdnconfig;
+ unsigned int prechconfig1;
+ unsigned char res1[0x8];
+ unsigned int pwrdnconfig; /* 0x0028*/
unsigned int timingpzq;
unsigned int timingref;
unsigned int timingrow;
@@ -128,12 +137,12 @@ struct exynos5_dmc {
unsigned int timingpower;
unsigned int phystatus;
unsigned char res2[0x4];
- unsigned int chipstatus_ch0;
+ unsigned int chipstatus_ch0; /* 0x0048 */
unsigned int chipstatus_ch1;
unsigned char res3[0x4];
unsigned int mrstatus;
unsigned char res4[0x8];
- unsigned int qoscontrol0;
+ unsigned int qoscontrol0; /* 0x0060 */
unsigned char resr5[0x4];
unsigned int qoscontrol1;
unsigned char res6[0x4];
@@ -164,45 +173,83 @@ struct exynos5_dmc {
unsigned int qoscontrol14;
unsigned char res19[0x4];
unsigned int qoscontrol15;
- unsigned char res20[0x14];
+ unsigned char res20[0x4];
+ unsigned int timing_set_sw; /* 0x00e0 */
+ unsigned int timingrow1;
+ unsigned int timingdata1;
+ unsigned int timingpower1;
unsigned int ivcontrol;
unsigned int wrtra_config;
unsigned int rdlvl_config;
- unsigned char res21[0x8];
+ unsigned char res21[0x4];
+ unsigned int brbrsvcontrol; /* 0x0100*/
unsigned int brbrsvconfig;
unsigned int brbqosconfig;
unsigned int membaseconfig0;
- unsigned int membaseconfig1;
+ unsigned int membaseconfig1; /* 0x0110 */
unsigned char res22[0xc];
- unsigned int wrlvl_config;
- unsigned char res23[0xc];
- unsigned int perevcontrol;
+ unsigned int wrlvl_config0; /* 0x0120 */
+ unsigned int wrlvl_config1;
+ unsigned int wrlvl_status;
+ unsigned char res23[0x4];
+ unsigned int perevcontrol; /* 0x0130 */
unsigned int perev0config;
unsigned int perev1config;
unsigned int perev2config;
unsigned int perev3config;
- unsigned char res24[0xdebc];
- unsigned int pmnc_ppc_a;
- unsigned char res25[0xc];
- unsigned int cntens_ppc_a;
- unsigned char res26[0xc];
- unsigned int cntenc_ppc_a;
- unsigned char res27[0xc];
- unsigned int intens_ppc_a;
- unsigned char res28[0xc];
- unsigned int intenc_ppc_a;
- unsigned char res29[0xc];
- unsigned int flag_ppc_a;
- unsigned char res30[0xac];
- unsigned int ccnt_ppc_a;
- unsigned char res31[0xc];
- unsigned int pmcnt0_ppc_a;
+ unsigned char res22a[0xc];
+ unsigned int ctrl_io_rdata_ch0;
+ unsigned int ctrl_io_rdata_ch1;
+ unsigned char res23a[0x8];
+ unsigned int cacal_config0;
+ unsigned int cacal_config1;
+ unsigned int cacal_status;
+ unsigned char res24[0x94];
+ unsigned int emergent_config0; /* 0x0200 */
+ unsigned int emergent_config1;
+ unsigned char res25[0x8];
+ unsigned int bp_control0;
+ unsigned int bp_control0_r;
+ unsigned int bp_control0_w;
+ unsigned char res26[0x4];
+ unsigned int bp_control1;
+ unsigned int bp_control1_r;
+ unsigned int bp_control1_w;
+ unsigned char res27[0x4];
+ unsigned int bp_control2;
+ unsigned int bp_control2_r;
+ unsigned int bp_control2_w;
+ unsigned char res28[0x4];
+ unsigned int bp_control3;
+ unsigned int bp_control3_r;
+ unsigned int bp_control3_w;
+ unsigned char res29[0xb4];
+ unsigned int winconfig_odt_w; /* 0x0300 */
+ unsigned char res30[0x4];
+ unsigned int winconfig_ctrl_read;
+ unsigned int winconfig_ctrl_gate;
+ unsigned char res31[0xdcf0];
+ unsigned int pmnc_ppc;
unsigned char res32[0xc];
- unsigned int pmcnt1_ppc_a;
+ unsigned int cntens_ppc;
unsigned char res33[0xc];
- unsigned int pmcnt2_ppc_a;
+ unsigned int cntenc_ppc;
unsigned char res34[0xc];
- unsigned int pmcnt3_ppc_a;
+ unsigned int intens_ppc;
+ unsigned char res35[0xc];
+ unsigned int intenc_ppc;
+ unsigned char res36[0xc];
+ unsigned int flag_ppc; /* 0xe050 */
+ unsigned char res37[0xac];
+ unsigned int ccnt_ppc;
+ unsigned char res38[0xc];
+ unsigned int pmcnt0_ppc;
+ unsigned char res39[0xc];
+ unsigned int pmcnt1_ppc;
+ unsigned char res40[0xc];
+ unsigned int pmcnt2_ppc;
+ unsigned char res41[0xc];
+ unsigned int pmcnt3_ppc; /* 0xe140 */
};
struct exynos5_phy_control {
@@ -211,13 +258,13 @@ struct exynos5_phy_control {
unsigned int phy_con2;
unsigned int phy_con3;
unsigned int phy_con4;
- unsigned char res1[4];
+ unsigned int phy_con5;
unsigned int phy_con6;
unsigned char res2[4];
unsigned int phy_con8;
unsigned int phy_con9;
unsigned int phy_con10;
- unsigned char res3[4];
+ unsigned int phy_con11;
unsigned int phy_con12;
unsigned int phy_con13;
unsigned int phy_con14;
@@ -252,6 +299,15 @@ struct exynos5_phy_control {
unsigned int phy_con42;
};
+struct exynos5_tzasc {
+ unsigned char res1[0xf00];
+ unsigned int membaseconfig0;
+ unsigned int membaseconfig1;
+ unsigned char res2[0x8];
+ unsigned int memconfig0;
+ unsigned int memconfig1;
+};
+
enum ddr_mode {
DDR_MODE_DDR2,
DDR_MODE_DDR3,
@@ -286,6 +342,7 @@ enum mem_manuf {
#define PHY_CON0_T_WRRDCMD_SHIFT 17
#define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11
+#define PHY_CON0_CTRL_DDR_MODE_MASK 0x3
/* PHY_CON1 register fields */
#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0
--
1.7.12.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [U-Boot] [PATCH 04/10 V6] Exynos5420: Add DDR3 initialization for 5420
2013-10-29 7:23 ` [U-Boot] [PATCH 04/10 V6] Exynos5420: Add DDR3 " Rajeshwari S Shinde
@ 2013-11-13 3:24 ` Minkyu Kang
0 siblings, 0 replies; 37+ messages in thread
From: Minkyu Kang @ 2013-11-13 3:24 UTC (permalink / raw)
To: u-boot
Dear Rajeshwari S Shinde,
On 29 October 2013 16:23, Rajeshwari S Shinde <rajeshwari.s@samsung.com>wrote:
> This patch intends to add DDR3 initialization code for Exynos5420.
>
> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
> Changes in V2:
> - Corrected a compilation issue for SMDK5250.
> Changes in V3:
> - None
> Changes in V4:
> - None
> Changes in V5:
> - None
> Changes in V6:
> - None
> arch/arm/cpu/armv7/exynos/dmc_common.c | 10 +-
> arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 421
> +++++++++++++++++++++++++++++-
> arch/arm/include/asm/arch-exynos/cpu.h | 4 +
> arch/arm/include/asm/arch-exynos/dmc.h | 121 ++++++---
> 4 files changed, 511 insertions(+), 45 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/dmc_common.c
> b/arch/arm/cpu/armv7/exynos/dmc_common.c
> index 53cfe6e..9e432c2 100644
> --- a/arch/arm/cpu/armv7/exynos/dmc_common.c
> +++ b/arch/arm/cpu/armv7/exynos/dmc_common.c
> @@ -1,5 +1,5 @@
> /*
> - * Mem setup common file for different types of DDR present on SMDK5250
> boards.
> + * Mem setup common file for different types of DDR present on Exynos
> boards.
> *
> * Copyright (C) 2012 Samsung Electronics
> *
> @@ -152,14 +152,6 @@ void dmc_config_prech(struct mem_timings *mem, struct
> exynos5_dmc *dmc)
> }
> }
>
> -void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)
> -{
> - writel(mem->memconfig, &dmc->memconfig0);
> - writel(mem->memconfig, &dmc->memconfig1);
> - writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0);
> - writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
> -}
> -
> void mem_ctrl_init(int reset)
> {
> struct spl_machine_param *param = spl_get_machine_params();
> diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
> b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
> index 5f5914e..3fab50b 100644
> --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
> +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
> @@ -1,5 +1,5 @@
> /*
> - * DDR3 mem setup file for SMDK5250 board based on EXYNOS5
> + * DDR3 mem setup file for board based on EXYNOS5
> *
> * Copyright (C) 2012 Samsung Electronics
> *
> @@ -15,8 +15,9 @@
> #include "exynos5_setup.h"
> #include "clock_init.h"
>
> -#define RDLVL_COMPLETE_TIMEOUT 10000
> +#define TIMEOUT 10000
>
> +#ifdef CONFIG_EXYNOS5250
> static void reset_phy_ctrl(void)
> {
> struct exynos5_clock *clk =
> @@ -108,7 +109,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem,
> unsigned long mem_iv_size,
>
> /* Precharge Configuration */
> writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
> - &dmc->prechconfig);
> + &dmc->prechconfig0);
>
> /* Power Down mode Configuration */
> writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
> @@ -174,7 +175,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem,
> unsigned long mem_iv_size,
> writel(val, &phy1_ctrl->phy_con1);
>
> writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
> - i = RDLVL_COMPLETE_TIMEOUT;
> + i = TIMEOUT;
> while ((readl(&dmc->phystatus) &
> (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
> (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i >
> 0) {
> @@ -215,3 +216,415 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem,
> unsigned long mem_iv_size,
> | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT),
> &dmc->concontrol);
> return 0;
> }
> +#endif
> +
> +#ifdef CONFIG_EXYNOS5420
> +int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
> + int reset)
> +{
> + struct exynos5420_clock *clk =
> + (struct exynos5420_clock *)EXYNOS5_CLOCK_BASE;
> + struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
> + struct exynos5_dmc *drex0, *drex1;
> + struct exynos5_tzasc *tzasc0, *tzasc1;
> + uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1;
> + int chip;
> + int i;
> +
> + phy0_ctrl = (struct exynos5_phy_control
> *)samsung_get_base_dmc_phy();
> + phy1_ctrl = (struct exynos5_phy_control
> *)(samsung_get_base_dmc_phy()
> + + DMC_OFFSET);
> + drex0 = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl();
> + drex1 = (struct exynos5_dmc *)(samsung_get_base_dmc_ctrl()
> + + DMC_OFFSET);
> + tzasc0 = (struct exynos5_tzasc *)EXYNOS5420_DMC_TZASC0_BASE;
> + tzasc1 = (struct exynos5_tzasc *)EXYNOS5420_DMC_TZASC1_BASE;
> +
> + /* Enable PAUSE for DREX */
> + setbits_le32(&clk->pause, ENABLE_BIT);
> +
> + /* Enable BYPASS mode */
> + setbits_le32(&clk->bpll_con1, BYPASS_EN);
> +
> + writel(MUX_BPLL_SEL_FOUTBPLL, &clk->src_cdrex);
> + do {
> + val = readl(&clk->mux_stat_cdrex);
> + val &= BPLL_SEL_MASK;
> + } while (val != FOUTBPLL);
> +
> + clrbits_le32(&clk->bpll_con1, BYPASS_EN);
> +
> + /* Specify the DDR memory type as DDR3 */
> + val = readl(&phy0_ctrl->phy_con0);
> + val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK <<
> PHY_CON0_CTRL_DDR_MODE_SHIFT);
> + val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
> + writel(val, &phy0_ctrl->phy_con0);
> +
> + val = readl(&phy1_ctrl->phy_con0);
> + val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK <<
> PHY_CON0_CTRL_DDR_MODE_SHIFT);
> + val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
> + writel(val, &phy1_ctrl->phy_con0);
> +
> + /* Set Read Latency and Burst Length for PHY0 and PHY1 */
> + val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
> + (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
> + writel(val, &phy0_ctrl->phy_con42);
> + writel(val, &phy1_ctrl->phy_con42);
> +
> + val = readl(&phy0_ctrl->phy_con26);
> + val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
> + val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
> + writel(val, &phy0_ctrl->phy_con26);
> +
> + val = readl(&phy1_ctrl->phy_con26);
> + val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
> + val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
> + writel(val, &phy1_ctrl->phy_con26);
> +
> + /*
> + * Set Driver strength for CK, CKE, CS & CA to 0x7
> + * Set Driver strength for Data Slice 0~3 to 0x7
> + */
> + val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 <<
> CA_CKE_DRVR_DS_OFFSET) |
> + (0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 <<
> CA_ADR_DRVR_DS_OFFSET);
> + val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) |
> + (0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET);
> + writel(val, &phy0_ctrl->phy_con39);
> + writel(val, &phy1_ctrl->phy_con39);
> +
> + /* ZQ Calibration */
> + if (dmc_config_zq(mem, phy0_ctrl, phy1_ctrl))
> + return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
> +
> + clrbits_le32(&phy0_ctrl->phy_con16, ZQ_CLK_DIV_EN);
> + clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN);
> +
> + /* DQ Signal */
> + val = readl(&phy0_ctrl->phy_con14);
> + val |= mem->phy0_pulld_dqs;
> + writel(val, &phy0_ctrl->phy_con14);
> + val = readl(&phy1_ctrl->phy_con14);
> + val |= mem->phy1_pulld_dqs;
> + writel(val, &phy1_ctrl->phy_con14);
> +
> + val = MEM_TERM_EN | PHY_TERM_EN;
> + writel(val, &drex0->phycontrol0);
> + writel(val, &drex1->phycontrol0);
> +
> + writel(mem->concontrol |
> + (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
> + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
> + &drex0->concontrol);
> + writel(mem->concontrol |
> + (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
> + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
> + &drex1->concontrol);
> +
> + do {
> + val = readl(&drex0->phystatus);
> + } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
> + do {
> + val = readl(&drex1->phystatus);
> + } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
> +
> + clrbits_le32(&drex0->concontrol, DFI_INIT_START);
> + clrbits_le32(&drex1->concontrol, DFI_INIT_START);
> +
> + update_reset_dll(drex0, DDR_MODE_DDR3);
> + update_reset_dll(drex1, DDR_MODE_DDR3);
> +
> + /*
> + * Set Base Address:
> + * 0x2000_0000 ~ 0x5FFF_FFFF
> + * 0x6000_0000 ~ 0x9FFF_FFFF
> + */
> + /* MEMBASECONFIG0 */
> + val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_0) |
> + DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
> + writel(val, &tzasc0->membaseconfig0);
> + writel(val, &tzasc1->membaseconfig0);
> +
> + /* MEMBASECONFIG1 */
> + val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_1) |
> + DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
> + writel(val, &tzasc0->membaseconfig1);
> + writel(val, &tzasc1->membaseconfig1);
> +
> + /*
> + * Memory Channel Inteleaving Size
> + * Ares Channel interleaving = 128 bytes
> + */
> + /* MEMCONFIG0/1 */
> + writel(mem->memconfig, &tzasc0->memconfig0);
> + writel(mem->memconfig, &tzasc1->memconfig0);
> + writel(mem->memconfig, &tzasc0->memconfig1);
> + writel(mem->memconfig, &tzasc1->memconfig1);
> +
> + /* Precharge Configuration */
> + writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
> + &drex0->prechconfig0);
> + writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
> + &drex1->prechconfig0);
> +
> + /*
> + * TimingRow, TimingData, TimingPower and Timingaref
> + * values as per Memory AC parameters
> + */
> + writel(mem->timing_ref, &drex0->timingref);
> + writel(mem->timing_ref, &drex1->timingref);
> + writel(mem->timing_row, &drex0->timingrow);
> + writel(mem->timing_row, &drex1->timingrow);
> + writel(mem->timing_data, &drex0->timingdata);
> + writel(mem->timing_data, &drex1->timingdata);
> + writel(mem->timing_power, &drex0->timingpower);
> + writel(mem->timing_power, &drex1->timingpower);
> +
> + if (reset) {
> + /*
> + * Send NOP, MRS and ZQINIT commands
> + * Sending MRS command will reset the DRAM. We should not
> be
> + * reseting the DRAM after resume, this will lead to memory
> + * corruption as DRAM content is lost after DRAM reset
> + */
> + dmc_config_mrs(mem, drex0);
> + dmc_config_mrs(mem, drex1);
> + } else {
> + /*
> + * During Suspend-Resume & S/W-Reset, as soon as PMU
> releases
> + * pad retention, CKE goes high. This causes memory
> contents
> + * not to be retained during DRAM initialization. Therfore,
> + * there is a new control register(0x100431e8[28]) which
> lets us
> + * release pad retention and retain the memory content
> until the
> + * initialization is complete.
> + */
> + writel(PAD_RETENTION_DRAM_COREBLK_VAL,
> + PAD_RETENTION_DRAM_COREBLK_OPTION);
> + do {
> + val = readl(PAD_RETENTION_DRAM_STATUS);
> + } while (val != 0x1);
> +
> + /*
> + * CKE PAD retention disables DRAM self-refresh mode.
> + * Send auto refresh command for DRAM refresh.
> + */
> + for (i = 0; i < 128; i++) {
> + for (chip = 0; chip < mem->chips_to_configure;
> chip++) {
> + writel(DIRECT_CMD_REFA |
> + (chip << DIRECT_CMD_CHIP_SHIFT),
> + &drex0->directcmd);
> + writel(DIRECT_CMD_REFA |
> + (chip << DIRECT_CMD_CHIP_SHIFT),
> + &drex1->directcmd);
> + }
> + }
> + }
> +
> + if (mem->gate_leveling_enable) {
> + writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0);
> + writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0);
> +
> + setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN);
> + setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN);
> +
> + val = PHY_CON2_RESET_VAL;
> + val |= INIT_DESKEW_EN;
> + writel(val, &phy0_ctrl->phy_con2);
> + writel(val, &phy1_ctrl->phy_con2);
> +
> + val = readl(&phy0_ctrl->phy_con1);
> + val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
> + writel(val, &phy0_ctrl->phy_con1);
> +
> + val = readl(&phy1_ctrl->phy_con1);
> + val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
> + writel(val, &phy1_ctrl->phy_con1);
> +
> + n_lock_r = readl(&phy0_ctrl->phy_con13);
> + n_lock_w_phy0 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2;
> + n_lock_r = readl(&phy0_ctrl->phy_con12);
> + n_lock_r &= ~CTRL_DLL_ON;
> + n_lock_r |= n_lock_w_phy0;
> + writel(n_lock_r, &phy0_ctrl->phy_con12);
> +
> + n_lock_r = readl(&phy1_ctrl->phy_con13);
> + n_lock_w_phy1 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2;
> + n_lock_r = readl(&phy1_ctrl->phy_con12);
> + n_lock_r &= ~CTRL_DLL_ON;
> + n_lock_r |= n_lock_w_phy1;
> + writel(n_lock_r, &phy1_ctrl->phy_con12);
> +
> + val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
> + for (chip = 0; chip < mem->chips_to_configure; chip++) {
> + writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
> + &drex0->directcmd);
> + writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
> + &drex1->directcmd);
> + }
> +
> + setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN);
> + setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN);
> +
> + setbits_le32(&phy0_ctrl->phy_con0, CTRL_SHGATE);
> + setbits_le32(&phy1_ctrl->phy_con0, CTRL_SHGATE);
> +
> + val = readl(&phy0_ctrl->phy_con1);
> + val &= ~(CTRL_GATEDURADJ_MASK);
> + writel(val, &phy0_ctrl->phy_con1);
> +
> + val = readl(&phy1_ctrl->phy_con1);
> + val &= ~(CTRL_GATEDURADJ_MASK);
> + writel(val, &phy1_ctrl->phy_con1);
> +
> + writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config);
> + i = TIMEOUT;
> + while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) !=
> + RDLVL_COMPLETE_CHO) && (i > 0)) {
> + /*
> + * TODO(waihong): Comment on how long this take to
> + * timeout
> + */
> + sdelay(100);
> + i--;
> + }
> + if (!i)
> + return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
> + writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config);
> +
> + writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config);
> + i = TIMEOUT;
> + while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) !=
> + RDLVL_COMPLETE_CHO) && (i > 0)) {
> + /*
> + * TODO(waihong): Comment on how long this take to
> + * timeout
> + */
> + sdelay(100);
> + i--;
> + }
> + if (!i)
> + return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
> + writel(CTRL_RDLVL_GATE_DISABLE, &drex1->rdlvl_config);
> +
> + writel(0, &phy0_ctrl->phy_con14);
> + writel(0, &phy1_ctrl->phy_con14);
> +
> + val = (0x3 << DIRECT_CMD_BANK_SHIFT);
> + for (chip = 0; chip < mem->chips_to_configure; chip++) {
> + writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
> + &drex0->directcmd);
> + writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
> + &drex1->directcmd);
> + }
> +
> + if (mem->read_leveling_enable) {
> + /* Set Read DQ Calibration */
> + val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
> + for (chip = 0; chip < mem->chips_to_configure;
> chip++) {
> + writel(val | (chip <<
> DIRECT_CMD_CHIP_SHIFT),
> + &drex0->directcmd);
> + writel(val | (chip <<
> DIRECT_CMD_CHIP_SHIFT),
> + &drex1->directcmd);
> + }
> +
> + val = readl(&phy0_ctrl->phy_con1);
> + val |= READ_LEVELLING_DDR3;
> + writel(val, &phy0_ctrl->phy_con1);
> + val = readl(&phy1_ctrl->phy_con1);
> + val |= READ_LEVELLING_DDR3;
> + writel(val, &phy1_ctrl->phy_con1);
> +
> + val = readl(&phy0_ctrl->phy_con2);
> + val |= (RDLVL_EN | RDLVL_INCR_ADJ);
> + writel(val, &phy0_ctrl->phy_con2);
> + val = readl(&phy1_ctrl->phy_con2);
> + val |= (RDLVL_EN | RDLVL_INCR_ADJ);
> + writel(val, &phy1_ctrl->phy_con2);
> +
> + setbits_le32(&drex0->rdlvl_config,
> + CTRL_RDLVL_DATA_ENABLE);
> + i = TIMEOUT;
> + while (((readl(&drex0->phystatus) &
> RDLVL_COMPLETE_CHO)
> + != RDLVL_COMPLETE_CHO) && (i > 0)) {
> + /*
> + * TODO(waihong): Comment on how long this
> take
> + * to timeout
> + */
> + sdelay(100);
> + i--;
> + }
> + if (!i)
> + return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
> +
> + clrbits_le32(&drex0->rdlvl_config,
> + CTRL_RDLVL_DATA_ENABLE);
> + setbits_le32(&drex1->rdlvl_config,
> + CTRL_RDLVL_DATA_ENABLE);
> + i = TIMEOUT;
> + while (((readl(&drex1->phystatus) &
> RDLVL_COMPLETE_CHO)
> + != RDLVL_COMPLETE_CHO) && (i > 0)) {
> + /*
> + * TODO(waihong): Comment on how long this
> take
> + * to timeout
> + */
> + sdelay(100);
> + i--;
> + }
> + if (!i)
> + return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
> +
> + clrbits_le32(&drex1->rdlvl_config,
> + CTRL_RDLVL_DATA_ENABLE);
> +
> + val = (0x3 << DIRECT_CMD_BANK_SHIFT);
> + for (chip = 0; chip < mem->chips_to_configure;
> chip++) {
> + writel(val | (chip <<
> DIRECT_CMD_CHIP_SHIFT),
> + &drex0->directcmd);
> + writel(val | (chip <<
> DIRECT_CMD_CHIP_SHIFT),
> + &drex1->directcmd);
> + }
> +
> + update_reset_dll(drex0, DDR_MODE_DDR3);
> + update_reset_dll(drex1, DDR_MODE_DDR3);
> + }
> +
> + /* Common Settings for Leveling */
> + val = PHY_CON12_RESET_VAL;
> + writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12);
> + writel((val + n_lock_w_phy1), &phy1_ctrl->phy_con12);
> +
> + setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN);
> + setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN);
> + }
> +
> + /* Send PALL command */
> + dmc_config_prech(mem, drex0);
> + dmc_config_prech(mem, drex1);
> +
> + writel(mem->memcontrol, &drex0->memcontrol);
> + writel(mem->memcontrol, &drex1->memcontrol);
> +
> + /*
> + * Set DMC Concontrol: Enable auto-refresh counter, provide
> + * read data fetch cycles and enable DREX auto set powerdown
> + * for input buffer of I/O in none read memory state.
> + */
> + writel(mem->concontrol | (mem->aref_en <<
> CONCONTROL_AREF_EN_SHIFT) |
> + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
> + DMC_CONCONTROL_IO_PD_CON(0x2),
> + &drex0->concontrol);
> + writel(mem->concontrol | (mem->aref_en <<
> CONCONTROL_AREF_EN_SHIFT) |
> + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
> + DMC_CONCONTROL_IO_PD_CON(0x2),
> + &drex1->concontrol);
> +
> + /*
> + * Enable Clock Gating Control for DMC
> + * this saves around 25 mw dmc power as compared to the power
> + * consumption without these bits enabled
> + */
> + setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
> + setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
> +
> + return 0;
> +}
> +#endif
> diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
> b/arch/arm/include/asm/arch-exynos/cpu.h
> index 10a2ac3..a75dccf 100644
> --- a/arch/arm/include/asm/arch-exynos/cpu.h
> +++ b/arch/arm/include/asm/arch-exynos/cpu.h
> @@ -164,6 +164,10 @@
> #define EXYNOS5420_ADC_BASE DEVICE_NOT_AVAILABLE
> #define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE
>
> +#define PAD_RETENTION_DRAM_STATUS (EXYNOS5420_POWER_BASE + 0x3004)
> +#define PAD_RETENTION_DRAM_COREBLK_OPTION (EXYNOS5420_POWER_BASE +
> 0x31E8)
> +#define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000
> +
> #ifndef __ASSEMBLY__
> #include <asm/io.h>
> /* CPU detection macros */
> diff --git a/arch/arm/include/asm/arch-exynos/dmc.h
> b/arch/arm/include/asm/arch-exynos/dmc.h
> index f65c676..b947de1 100644
> --- a/arch/arm/include/asm/arch-exynos/dmc.h
> +++ b/arch/arm/include/asm/arch-exynos/dmc.h
> @@ -114,13 +114,22 @@ struct exynos4_dmc {
> struct exynos5_dmc {
> unsigned int concontrol;
> unsigned int memcontrol;
> +
> +/* Between 5250 and 5420, the DMC Register differs only at 0x8 offset.
> + * So to use the same structure and simplify the code put a define to
> + * distinguish between memconfig0 and cgcontrol register */
>
please fix multiline comment.
> +#ifdef CONFIG_EXYNOS5250
> unsigned int memconfig0;
> +#else
> + unsigned int cgcontrol;
> +#endif
> unsigned int memconfig1;
> unsigned int directcmd;
> - unsigned int prechconfig;
> + unsigned int prechconfig0;
> unsigned int phycontrol0;
> - unsigned char res1[0xc];
> - unsigned int pwrdnconfig;
> + unsigned int prechconfig1;
> + unsigned char res1[0x8];
> + unsigned int pwrdnconfig; /* 0x0028*/
> unsigned int timingpzq;
> unsigned int timingref;
> unsigned int timingrow;
> @@ -128,12 +137,12 @@ struct exynos5_dmc {
> unsigned int timingpower;
> unsigned int phystatus;
> unsigned char res2[0x4];
> - unsigned int chipstatus_ch0;
> + unsigned int chipstatus_ch0; /* 0x0048 */
> unsigned int chipstatus_ch1;
> unsigned char res3[0x4];
> unsigned int mrstatus;
> unsigned char res4[0x8];
> - unsigned int qoscontrol0;
> + unsigned int qoscontrol0; /* 0x0060 */
> unsigned char resr5[0x4];
> unsigned int qoscontrol1;
> unsigned char res6[0x4];
> @@ -164,45 +173,83 @@ struct exynos5_dmc {
> unsigned int qoscontrol14;
> unsigned char res19[0x4];
> unsigned int qoscontrol15;
> - unsigned char res20[0x14];
> + unsigned char res20[0x4];
> + unsigned int timing_set_sw; /* 0x00e0 */
> + unsigned int timingrow1;
> + unsigned int timingdata1;
> + unsigned int timingpower1;
> unsigned int ivcontrol;
> unsigned int wrtra_config;
> unsigned int rdlvl_config;
> - unsigned char res21[0x8];
> + unsigned char res21[0x4];
> + unsigned int brbrsvcontrol; /* 0x0100*/
> unsigned int brbrsvconfig;
> unsigned int brbqosconfig;
> unsigned int membaseconfig0;
> - unsigned int membaseconfig1;
> + unsigned int membaseconfig1; /* 0x0110 */
> unsigned char res22[0xc];
> - unsigned int wrlvl_config;
> - unsigned char res23[0xc];
> - unsigned int perevcontrol;
> + unsigned int wrlvl_config0; /* 0x0120 */
> + unsigned int wrlvl_config1;
> + unsigned int wrlvl_status;
> + unsigned char res23[0x4];
> + unsigned int perevcontrol; /* 0x0130 */
> unsigned int perev0config;
> unsigned int perev1config;
> unsigned int perev2config;
> unsigned int perev3config;
> - unsigned char res24[0xdebc];
> - unsigned int pmnc_ppc_a;
> - unsigned char res25[0xc];
> - unsigned int cntens_ppc_a;
> - unsigned char res26[0xc];
> - unsigned int cntenc_ppc_a;
> - unsigned char res27[0xc];
> - unsigned int intens_ppc_a;
> - unsigned char res28[0xc];
> - unsigned int intenc_ppc_a;
> - unsigned char res29[0xc];
> - unsigned int flag_ppc_a;
> - unsigned char res30[0xac];
> - unsigned int ccnt_ppc_a;
> - unsigned char res31[0xc];
> - unsigned int pmcnt0_ppc_a;
> + unsigned char res22a[0xc];
> + unsigned int ctrl_io_rdata_ch0;
> + unsigned int ctrl_io_rdata_ch1;
> + unsigned char res23a[0x8];
> + unsigned int cacal_config0;
> + unsigned int cacal_config1;
> + unsigned int cacal_status;
> + unsigned char res24[0x94];
> + unsigned int emergent_config0; /* 0x0200 */
> + unsigned int emergent_config1;
> + unsigned char res25[0x8];
> + unsigned int bp_control0;
> + unsigned int bp_control0_r;
> + unsigned int bp_control0_w;
> + unsigned char res26[0x4];
> + unsigned int bp_control1;
> + unsigned int bp_control1_r;
> + unsigned int bp_control1_w;
> + unsigned char res27[0x4];
> + unsigned int bp_control2;
> + unsigned int bp_control2_r;
> + unsigned int bp_control2_w;
> + unsigned char res28[0x4];
> + unsigned int bp_control3;
> + unsigned int bp_control3_r;
> + unsigned int bp_control3_w;
> + unsigned char res29[0xb4];
> + unsigned int winconfig_odt_w; /* 0x0300 */
> + unsigned char res30[0x4];
> + unsigned int winconfig_ctrl_read;
> + unsigned int winconfig_ctrl_gate;
> + unsigned char res31[0xdcf0];
> + unsigned int pmnc_ppc;
> unsigned char res32[0xc];
> - unsigned int pmcnt1_ppc_a;
> + unsigned int cntens_ppc;
> unsigned char res33[0xc];
> - unsigned int pmcnt2_ppc_a;
> + unsigned int cntenc_ppc;
> unsigned char res34[0xc];
> - unsigned int pmcnt3_ppc_a;
> + unsigned int intens_ppc;
> + unsigned char res35[0xc];
> + unsigned int intenc_ppc;
> + unsigned char res36[0xc];
> + unsigned int flag_ppc; /* 0xe050 */
> + unsigned char res37[0xac];
> + unsigned int ccnt_ppc;
> + unsigned char res38[0xc];
> + unsigned int pmcnt0_ppc;
> + unsigned char res39[0xc];
> + unsigned int pmcnt1_ppc;
> + unsigned char res40[0xc];
> + unsigned int pmcnt2_ppc;
> + unsigned char res41[0xc];
> + unsigned int pmcnt3_ppc; /* 0xe140 */
> };
>
> struct exynos5_phy_control {
> @@ -211,13 +258,13 @@ struct exynos5_phy_control {
> unsigned int phy_con2;
> unsigned int phy_con3;
> unsigned int phy_con4;
> - unsigned char res1[4];
> + unsigned int phy_con5;
> unsigned int phy_con6;
> unsigned char res2[4];
> unsigned int phy_con8;
> unsigned int phy_con9;
> unsigned int phy_con10;
> - unsigned char res3[4];
> + unsigned int phy_con11;
> unsigned int phy_con12;
> unsigned int phy_con13;
> unsigned int phy_con14;
> @@ -252,6 +299,15 @@ struct exynos5_phy_control {
> unsigned int phy_con42;
> };
>
> +struct exynos5_tzasc {
> + unsigned char res1[0xf00];
> + unsigned int membaseconfig0;
> + unsigned int membaseconfig1;
> + unsigned char res2[0x8];
> + unsigned int memconfig0;
> + unsigned int memconfig1;
> +};
> +
> enum ddr_mode {
> DDR_MODE_DDR2,
> DDR_MODE_DDR3,
> @@ -286,6 +342,7 @@ enum mem_manuf {
> #define PHY_CON0_T_WRRDCMD_SHIFT 17
> #define PHY_CON0_T_WRRDCMD_MASK (0x7 <<
> PHY_CON0_T_WRRDCMD_SHIFT)
> #define PHY_CON0_CTRL_DDR_MODE_SHIFT 11
> +#define PHY_CON0_CTRL_DDR_MODE_MASK 0x3
>
> /* PHY_CON1 register fields */
> #define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0
> --
> 1.7.12.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 37+ messages in thread
* [U-Boot] [PATCH 05/10 V6] Exynos5420: Add support for 5420 in pinmux and gpio
2013-10-29 7:23 [U-Boot] [PATCH 00/10 V6] EXYNOS5420: Add SMDK5420 board support Rajeshwari S Shinde
` (3 preceding siblings ...)
2013-10-29 7:23 ` [U-Boot] [PATCH 04/10 V6] Exynos5420: Add DDR3 " Rajeshwari S Shinde
@ 2013-10-29 7:23 ` Rajeshwari S Shinde
2013-11-13 3:01 ` Minkyu Kang
2013-10-29 7:23 ` [U-Boot] [PATCH 06/10 V6] Exynos5420: Add base patch for SMDK5420 Rajeshwari S Shinde
` (5 subsequent siblings)
10 siblings, 1 reply; 37+ messages in thread
From: Rajeshwari S Shinde @ 2013-10-29 7:23 UTC (permalink / raw)
To: u-boot
Adds code in pinmux and gpio framework to support Exynos5420.
Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Added correct calculation of gpio based addresses.
Changes in V5:
- None
Changes in V6:
- None
arch/arm/cpu/armv7/exynos/pinmux.c | 241 +++++++++++++++++++++++++++++-
arch/arm/include/asm/arch-exynos/gpio.h | 143 ++++++++++++++++--
arch/arm/include/asm/arch-exynos/periph.h | 3 +
3 files changed, 372 insertions(+), 15 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index 8002bce..417ecae 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -46,6 +46,41 @@ static void exynos5_uart_config(int peripheral)
}
}
+static void exynos5420_uart_config(int peripheral)
+{
+ struct exynos5420_gpio_part1 *gpio1 =
+ (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
+ struct s5p_gpio_bank *bank;
+ int i, start, count;
+
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ bank = &gpio1->a0;
+ start = 0;
+ count = 4;
+ break;
+ case PERIPH_ID_UART1:
+ bank = &gpio1->a0;
+ start = 4;
+ count = 4;
+ break;
+ case PERIPH_ID_UART2:
+ bank = &gpio1->a1;
+ start = 0;
+ count = 4;
+ break;
+ case PERIPH_ID_UART3:
+ bank = &gpio1->a1;
+ start = 4;
+ count = 2;
+ break;
+ }
+ for (i = start; i < start + count; i++) {
+ s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+ s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ }
+}
+
static int exynos5_mmc_config(int peripheral, int flags)
{
struct exynos5_gpio_part1 *gpio1 =
@@ -101,6 +136,70 @@ static int exynos5_mmc_config(int peripheral, int flags)
return 0;
}
+static int exynos5420_mmc_config(int peripheral, int flags)
+{
+ struct exynos5420_gpio_part3 *gpio3 =
+ (struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3();
+ struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL;
+ int i, start = 0, gpio_func = 0;
+
+ switch (peripheral) {
+ case PERIPH_ID_SDMMC0:
+ bank = &gpio3->c0;
+ bank_ext = &gpio3->c3;
+ start = 0;
+ gpio_func = GPIO_FUNC(0x2);
+ break;
+ case PERIPH_ID_SDMMC1:
+ bank = &gpio3->c1;
+ bank_ext = &gpio3->d1;
+ start = 4;
+ gpio_func = GPIO_FUNC(0x2);
+ break;
+ case PERIPH_ID_SDMMC2:
+ bank = &gpio3->c2;
+ bank_ext = NULL;
+ gpio_func = GPIO_FUNC(0x2);
+ break;
+ }
+ if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+ debug("SDMMC device %d does not support 8bit mode",
+ peripheral);
+ return -1;
+ }
+ if (flags & PINMUX_FLAG_8BIT_MODE) {
+ for (i = start; i <= (start + 3); i++) {
+ s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
+ s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
+ s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+ }
+ }
+ for (i = 0; i < 3; i++) {
+ /*
+ * MMC0 is intended to be used for eMMC. The
+ * card detect pin is used as a VDDEN signal to
+ * power on the eMMC. The 5420 iROM makes
+ * this same assumption.
+ */
+ if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) {
+ s5p_gpio_set_value(bank, i, 1);
+ s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT);
+ } else {
+ s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ }
+ s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+ s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+ }
+
+ for (i = 3; i <= 6; i++) {
+ s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
+ s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+ }
+
+ return 0;
+}
+
static void exynos5_sromc_config(int flags)
{
struct exynos5_gpio_part1 *gpio1 =
@@ -216,6 +315,59 @@ static void exynos5_i2c_config(int peripheral, int flags)
}
}
+static void exynos5420_i2c_config(int peripheral)
+{
+ struct exynos5420_gpio_part1 *gpio1 =
+ (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
+
+ switch (peripheral) {
+ case PERIPH_ID_I2C0:
+ s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C1:
+ s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C2:
+ s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C3:
+ s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C4:
+ s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C5:
+ s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C6:
+ s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
+ s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
+ break;
+ case PERIPH_ID_I2C7:
+ s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C8:
+ s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C9:
+ s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C10:
+ s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2));
+ break;
+ }
+}
+
static void exynos5_i2s_config(int peripheral)
{
int i;
@@ -279,6 +431,49 @@ void exynos5_spi_config(int peripheral)
}
}
+void exynos5420_spi_config(int peripheral)
+{
+ int cfg = 0, pin = 0, i;
+ struct s5p_gpio_bank *bank = NULL;
+ struct exynos5420_gpio_part1 *gpio1 =
+ (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
+ struct exynos5420_gpio_part4 *gpio4 =
+ (struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4();
+
+ switch (peripheral) {
+ case PERIPH_ID_SPI0:
+ bank = &gpio1->a2;
+ cfg = GPIO_FUNC(0x2);
+ pin = 0;
+ break;
+ case PERIPH_ID_SPI1:
+ bank = &gpio1->a2;
+ cfg = GPIO_FUNC(0x2);
+ pin = 4;
+ break;
+ case PERIPH_ID_SPI2:
+ bank = &gpio1->b1;
+ cfg = GPIO_FUNC(0x5);
+ pin = 1;
+ break;
+ case PERIPH_ID_SPI3:
+ bank = &gpio4->f1;
+ cfg = GPIO_FUNC(0x2);
+ pin = 0;
+ break;
+ case PERIPH_ID_SPI4:
+ for (i = 0; i < 2; i++) {
+ s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4));
+ s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4));
+ }
+ break;
+ }
+ if (peripheral != PERIPH_ID_SPI4) {
+ for (i = pin; i < pin + 4; i++)
+ s5p_gpio_cfg_pin(bank, i, cfg);
+ }
+}
+
static int exynos5_pinmux_config(int peripheral, int flags)
{
switch (peripheral) {
@@ -325,6 +520,48 @@ static int exynos5_pinmux_config(int peripheral, int flags)
return 0;
}
+static int exynos5420_pinmux_config(int peripheral, int flags)
+{
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ exynos5420_uart_config(peripheral);
+ break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC1:
+ case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC3:
+ return exynos5420_mmc_config(peripheral, flags);
+ case PERIPH_ID_SPI0:
+ case PERIPH_ID_SPI1:
+ case PERIPH_ID_SPI2:
+ case PERIPH_ID_SPI3:
+ case PERIPH_ID_SPI4:
+ exynos5420_spi_config(peripheral);
+ break;
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
+ case PERIPH_ID_I2C8:
+ case PERIPH_ID_I2C9:
+ case PERIPH_ID_I2C10:
+ exynos5420_i2c_config(peripheral);
+ break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ }
+
+ return 0;
+}
+
static void exynos4_i2c_config(int peripheral, int flags)
{
struct exynos4_gpio_part1 *gpio1 =
@@ -474,7 +711,9 @@ static int exynos4_pinmux_config(int peripheral, int flags)
int exynos_pinmux_config(int peripheral, int flags)
{
- if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420()) {
+ return exynos5420_pinmux_config(peripheral, flags);
+ } else if (proid_is_exynos5250()) {
return exynos5_pinmux_config(peripheral, flags);
} else if (cpu_is_exynos4()) {
return exynos4_pinmux_config(peripheral, flags);
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index a1a7439..2a19852 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -127,6 +127,58 @@ struct exynos4x12_gpio_part4 {
struct s5p_gpio_bank v4;
};
+struct exynos5420_gpio_part1 {
+ struct s5p_gpio_bank a0;
+ struct s5p_gpio_bank a1;
+ struct s5p_gpio_bank a2;
+ struct s5p_gpio_bank b0;
+ struct s5p_gpio_bank b1;
+ struct s5p_gpio_bank b2;
+ struct s5p_gpio_bank b3;
+ struct s5p_gpio_bank b4;
+ struct s5p_gpio_bank h0;
+};
+
+struct exynos5420_gpio_part2 {
+ struct s5p_gpio_bank y7; /* 0x1340_0000 */
+ struct s5p_gpio_bank res[0x5f]; /* */
+ struct s5p_gpio_bank x0; /* 0x1340_0C00 */
+ struct s5p_gpio_bank x1; /* 0x1340_0C20 */
+ struct s5p_gpio_bank x2; /* 0x1340_0C40 */
+ struct s5p_gpio_bank x3; /* 0x1340_0C60 */
+};
+
+struct exynos5420_gpio_part3 {
+ struct s5p_gpio_bank c0;
+ struct s5p_gpio_bank c1;
+ struct s5p_gpio_bank c2;
+ struct s5p_gpio_bank c3;
+ struct s5p_gpio_bank c4;
+ struct s5p_gpio_bank d1;
+ struct s5p_gpio_bank y0;
+ struct s5p_gpio_bank y1;
+ struct s5p_gpio_bank y2;
+ struct s5p_gpio_bank y3;
+ struct s5p_gpio_bank y4;
+ struct s5p_gpio_bank y5;
+ struct s5p_gpio_bank y6;
+};
+
+struct exynos5420_gpio_part4 {
+ struct s5p_gpio_bank e0; /* 0x1400_0000 */
+ struct s5p_gpio_bank e1; /* 0x1400_0020 */
+ struct s5p_gpio_bank f0; /* 0x1400_0040 */
+ struct s5p_gpio_bank f1; /* 0x1400_0060 */
+ struct s5p_gpio_bank g0; /* 0x1400_0080 */
+ struct s5p_gpio_bank g1; /* 0x1400_00A0 */
+ struct s5p_gpio_bank g2; /* 0x1400_00C0 */
+ struct s5p_gpio_bank j4; /* 0x1400_00E0 */
+};
+
+struct exynos5420_gpio_part5 {
+ struct s5p_gpio_bank z0; /* 0x0386_0000 */
+};
+
struct exynos5_gpio_part1 {
struct s5p_gpio_bank a0;
struct s5p_gpio_bank a1;
@@ -259,16 +311,67 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
- EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX)
+
+/* EXYNOS5420 */
+#define exynos5420_gpio_part1_get_nr(bank, pin) \
+ ((((((unsigned int) &(((struct exynos5420_gpio_part1 *)\
+ EXYNOS5420_GPIO_PART1_BASE)->bank)) \
+ - EXYNOS5420_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin)
+
+#define EXYNOS5420_GPIO_PART1_MAX ((sizeof(struct exynos5420_gpio_part1) \
+ / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define exynos5420_gpio_part2_get_nr(bank, pin) \
+ (((((((unsigned int) &(((struct exynos5420_gpio_part2 *)\
+ EXYNOS5420_GPIO_PART2_BASE)->bank)) \
+ - EXYNOS5420_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART1_MAX)
+
+#define EXYNOS5420_GPIO_PART2_MAX ((sizeof(struct exynos5420_gpio_part2) \
+ / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define exynos5420_gpio_part3_get_nr(bank, pin) \
+ (((((((unsigned int) &(((struct exynos5420_gpio_part3 *)\
+ EXYNOS5420_GPIO_PART3_BASE)->bank)) \
+ - EXYNOS5420_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART2_MAX)
+
+#define EXYNOS5420_GPIO_PART3_MAX ((sizeof(struct exynos5420_gpio_part3) \
+ / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define exynos5420_gpio_part4_get_nr(bank, pin) \
+ (((((((unsigned int) &(((struct exynos5420_gpio_part4 *)\
+ EXYNOS5420_GPIO_PART4_BASE)->bank)) \
+ - EXYNOS5420_GPIO_PART4_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART3_MAX)
+
+#define EXYNOS5420_GPIO_PART4_MAX ((sizeof(struct exynos5420_gpio_part4) \
+ / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define EXYNOS5420_GPIO_PART5_MAX ((sizeof(struct exynos5420_gpio_part5) \
+ / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
static inline unsigned int s5p_gpio_base(int nr)
{
if (cpu_is_exynos5()) {
- if (nr < EXYNOS5_GPIO_PART1_MAX)
- return EXYNOS5_GPIO_PART1_BASE;
- else if (nr < EXYNOS5_GPIO_PART2_MAX)
- return EXYNOS5_GPIO_PART2_BASE;
- else
- return EXYNOS5_GPIO_PART3_BASE;
-
+ if (proid_is_exynos5420()) {
+ if (nr < EXYNOS5420_GPIO_PART1_MAX)
+ return EXYNOS5420_GPIO_PART1_BASE;
+ else if (nr < EXYNOS5420_GPIO_PART2_MAX)
+ return EXYNOS5420_GPIO_PART2_BASE;
+ else if (nr < EXYNOS5420_GPIO_PART3_MAX)
+ return EXYNOS5420_GPIO_PART3_BASE;
+ else
+ return EXYNOS5420_GPIO_PART4_BASE;
+ } else {
+ if (nr < EXYNOS5_GPIO_PART1_MAX)
+ return EXYNOS5_GPIO_PART1_BASE;
+ else if (nr < EXYNOS5_GPIO_PART2_MAX)
+ return EXYNOS5_GPIO_PART2_BASE;
+ else
+ return EXYNOS5_GPIO_PART3_BASE;
+ }
} else if (cpu_is_exynos4()) {
if (nr < EXYNOS4_GPIO_PART1_MAX)
return EXYNOS4_GPIO_PART1_BASE;
@@ -282,13 +385,25 @@ static inline unsigned int s5p_gpio_base(int nr)
static inline unsigned int s5p_gpio_part_max(int nr)
{
if (cpu_is_exynos5()) {
- if (nr < EXYNOS5_GPIO_PART1_MAX)
- return 0;
- else if (nr < EXYNOS5_GPIO_PART2_MAX)
- return EXYNOS5_GPIO_PART1_MAX;
- else
- return EXYNOS5_GPIO_PART2_MAX;
-
+ if (proid_is_exynos5420()) {
+ if (nr < EXYNOS5420_GPIO_PART1_MAX)
+ return 0;
+ else if (nr < EXYNOS5420_GPIO_PART2_MAX)
+ return EXYNOS5420_GPIO_PART1_MAX;
+ else if (nr < EXYNOS5420_GPIO_PART3_MAX)
+ return EXYNOS5420_GPIO_PART2_MAX;
+ else if (nr < EXYNOS5420_GPIO_PART4_MAX)
+ return EXYNOS5420_GPIO_PART3_MAX;
+ else
+ return EXYNOS5420_GPIO_PART4_MAX;
+ } else {
+ if (nr < EXYNOS5_GPIO_PART1_MAX)
+ return 0;
+ else if (nr < EXYNOS5_GPIO_PART2_MAX)
+ return EXYNOS5_GPIO_PART1_MAX;
+ else
+ return EXYNOS5_GPIO_PART2_MAX;
+ }
} else if (cpu_is_exynos4()) {
if (proid_is_exynos4412()) {
if (nr < EXYNOS4X12_GPIO_PART1_MAX)
diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h
index 64bd8b7..30c7f18 100644
--- a/arch/arm/include/asm/arch-exynos/periph.h
+++ b/arch/arm/include/asm/arch-exynos/periph.h
@@ -34,6 +34,9 @@ enum periph_id {
PERIPH_ID_SDMMC1,
PERIPH_ID_SDMMC2,
PERIPH_ID_SDMMC3,
+ PERIPH_ID_I2C8 = 87,
+ PERIPH_ID_I2C9,
+ PERIPH_ID_I2C10 = 203,
PERIPH_ID_I2S0 = 98,
PERIPH_ID_I2S1 = 99,
--
1.7.12.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [U-Boot] [PATCH 05/10 V6] Exynos5420: Add support for 5420 in pinmux and gpio
2013-10-29 7:23 ` [U-Boot] [PATCH 05/10 V6] Exynos5420: Add support for 5420 in pinmux and gpio Rajeshwari S Shinde
@ 2013-11-13 3:01 ` Minkyu Kang
2013-11-13 6:04 ` Rajeshwari Birje
0 siblings, 1 reply; 37+ messages in thread
From: Minkyu Kang @ 2013-11-13 3:01 UTC (permalink / raw)
To: u-boot
Dear Rajeshwari S Shinde,
On 29 October 2013 16:23, Rajeshwari S Shinde <rajeshwari.s@samsung.com>wrote:
> Adds code in pinmux and gpio framework to support Exynos5420.
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
> Changes in V2:
> - None
> Changes in V3:
> - None
> Changes in V4:
> - Added correct calculation of gpio based addresses.
> Changes in V5:
> - None
> Changes in V6:
> - None
> arch/arm/cpu/armv7/exynos/pinmux.c | 241
> +++++++++++++++++++++++++++++-
> arch/arm/include/asm/arch-exynos/gpio.h | 143 ++++++++++++++++--
> arch/arm/include/asm/arch-exynos/periph.h | 3 +
> 3 files changed, 372 insertions(+), 15 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
> b/arch/arm/cpu/armv7/exynos/pinmux.c
> index 8002bce..417ecae 100644
> --- a/arch/arm/cpu/armv7/exynos/pinmux.c
> +++ b/arch/arm/cpu/armv7/exynos/pinmux.c
> @@ -46,6 +46,41 @@ static void exynos5_uart_config(int peripheral)
> }
> }
>
> +static void exynos5420_uart_config(int peripheral)
> +{
> + struct exynos5420_gpio_part1 *gpio1 =
> + (struct exynos5420_gpio_part1
> *)samsung_get_base_gpio_part1();
> + struct s5p_gpio_bank *bank;
> + int i, start, count;
> +
> + switch (peripheral) {
> + case PERIPH_ID_UART0:
> + bank = &gpio1->a0;
> + start = 0;
> + count = 4;
> + break;
> + case PERIPH_ID_UART1:
> + bank = &gpio1->a0;
> + start = 4;
> + count = 4;
> + break;
> + case PERIPH_ID_UART2:
> + bank = &gpio1->a1;
> + start = 0;
> + count = 4;
> + break;
> + case PERIPH_ID_UART3:
> + bank = &gpio1->a1;
> + start = 4;
> + count = 2;
> + break;
+ }
>
please add blank line.
> + for (i = start; i < start + count; i++) {
> + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
> + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
> + }
> +}
> +
> static int exynos5_mmc_config(int peripheral, int flags)
> {
> struct exynos5_gpio_part1 *gpio1 =
> @@ -101,6 +136,70 @@ static int exynos5_mmc_config(int peripheral, int
> flags)
> return 0;
> }
>
> +static int exynos5420_mmc_config(int peripheral, int flags)
> +{
> + struct exynos5420_gpio_part3 *gpio3 =
> + (struct exynos5420_gpio_part3
> *)samsung_get_base_gpio_part3();
> + struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL;
> + int i, start = 0, gpio_func = 0;
>
I think we don' have to set to 0 to start and gpio_func.
> +
> + switch (peripheral) {
> + case PERIPH_ID_SDMMC0:
> + bank = &gpio3->c0;
> + bank_ext = &gpio3->c3;
> + start = 0;
> + gpio_func = GPIO_FUNC(0x2);
> + break;
> + case PERIPH_ID_SDMMC1:
> + bank = &gpio3->c1;
> + bank_ext = &gpio3->d1;
> + start = 4;
> + gpio_func = GPIO_FUNC(0x2);
> + break;
> + case PERIPH_ID_SDMMC2:
> + bank = &gpio3->c2;
> + bank_ext = NULL;
> + gpio_func = GPIO_FUNC(0x2);
> + break;
+ }
>
please add blank line.
> + if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
> + debug("SDMMC device %d does not support 8bit mode",
> + peripheral);
> + return -1;
> + }
>
please add blank line.
> + if (flags & PINMUX_FLAG_8BIT_MODE) {
> + for (i = start; i <= (start + 3); i++) {
> + s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
>
gpio_func is always GPIO_FUNC(0x2).
I think gpio_func is unnecessary.
> + s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
> + s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
> + }
> + }
>
please add blank line.
> + for (i = 0; i < 3; i++) {
> + /*
> + * MMC0 is intended to be used for eMMC. The
> + * card detect pin is used as a VDDEN signal to
> + * power on the eMMC. The 5420 iROM makes
> + * this same assumption.
> + */
> + if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) {
> + s5p_gpio_set_value(bank, i, 1);
> + s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT);
> + } else {
> + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
> + }
> + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
> + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
> + }
> +
> + for (i = 3; i <= 6; i++) {
> + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
> + s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
> + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
> + }
> +
> + return 0;
> +}
> +
> static void exynos5_sromc_config(int flags)
> {
> struct exynos5_gpio_part1 *gpio1 =
> @@ -216,6 +315,59 @@ static void exynos5_i2c_config(int peripheral, int
> flags)
> }
> }
>
> +static void exynos5420_i2c_config(int peripheral)
> +{
> + struct exynos5420_gpio_part1 *gpio1 =
> + (struct exynos5420_gpio_part1
> *)samsung_get_base_gpio_part1();
> +
> + switch (peripheral) {
> + case PERIPH_ID_I2C0:
> + s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
> + s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
> + break;
> + case PERIPH_ID_I2C1:
> + s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
> + s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
> + break;
> + case PERIPH_ID_I2C2:
> + s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
> + s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
> + break;
> + case PERIPH_ID_I2C3:
> + s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
> + s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
> + break;
> + case PERIPH_ID_I2C4:
> + s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
> + s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
> + break;
> + case PERIPH_ID_I2C5:
> + s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
> + s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
> + break;
> + case PERIPH_ID_I2C6:
> + s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
> + s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
> + break;
> + case PERIPH_ID_I2C7:
> + s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
> + s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
> + break;
> + case PERIPH_ID_I2C8:
> + s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2));
> + s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2));
> + break;
> + case PERIPH_ID_I2C9:
> + s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2));
> + s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2));
> + break;
> + case PERIPH_ID_I2C10:
> + s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2));
> + s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2));
> + break;
> + }
> +}
> +
> static void exynos5_i2s_config(int peripheral)
> {
> int i;
> @@ -279,6 +431,49 @@ void exynos5_spi_config(int peripheral)
> }
> }
>
> +void exynos5420_spi_config(int peripheral)
> +{
> + int cfg = 0, pin = 0, i;
>
please don't set to 0 at here.
We should set some values at switch..case.
> + struct s5p_gpio_bank *bank = NULL;
> + struct exynos5420_gpio_part1 *gpio1 =
> + (struct exynos5420_gpio_part1
> *)samsung_get_base_gpio_part1();
> + struct exynos5420_gpio_part4 *gpio4 =
> + (struct exynos5420_gpio_part4
> *)samsung_get_base_gpio_part4();
> +
> + switch (peripheral) {
> + case PERIPH_ID_SPI0:
> + bank = &gpio1->a2;
> + cfg = GPIO_FUNC(0x2);
> + pin = 0;
> + break;
> + case PERIPH_ID_SPI1:
> + bank = &gpio1->a2;
> + cfg = GPIO_FUNC(0x2);
> + pin = 4;
> + break;
> + case PERIPH_ID_SPI2:
> + bank = &gpio1->b1;
> + cfg = GPIO_FUNC(0x5);
> + pin = 1;
> + break;
> + case PERIPH_ID_SPI3:
> + bank = &gpio4->f1;
> + cfg = GPIO_FUNC(0x2);
> + pin = 0;
> + break;
> + case PERIPH_ID_SPI4:
> + for (i = 0; i < 2; i++) {
> + s5p_gpio_cfg_pin(&gpio4->f0, i + 2,
> GPIO_FUNC(0x4));
> + s5p_gpio_cfg_pin(&gpio4->e0, i + 4,
> GPIO_FUNC(0x4));
> + }
>
OK. I understood SPI4 is different with other SPIs.
but, it was another context.
just break and move it to out of this switch..case.
> + break;
+ }
>
please add blank line.
> + if (peripheral != PERIPH_ID_SPI4) {
> + for (i = pin; i < pin + 4; i++)
> + s5p_gpio_cfg_pin(bank, i, cfg);
> + }
> +}
> +
> static int exynos5_pinmux_config(int peripheral, int flags)
> {
> switch (peripheral) {
> @@ -325,6 +520,48 @@ static int exynos5_pinmux_config(int peripheral, int
> flags)
> return 0;
> }
>
> +static int exynos5420_pinmux_config(int peripheral, int flags)
> +{
> + switch (peripheral) {
> + case PERIPH_ID_UART0:
> + case PERIPH_ID_UART1:
> + case PERIPH_ID_UART2:
> + case PERIPH_ID_UART3:
> + exynos5420_uart_config(peripheral);
> + break;
> + case PERIPH_ID_SDMMC0:
> + case PERIPH_ID_SDMMC1:
> + case PERIPH_ID_SDMMC2:
> + case PERIPH_ID_SDMMC3:
> + return exynos5420_mmc_config(peripheral, flags);
> + case PERIPH_ID_SPI0:
> + case PERIPH_ID_SPI1:
> + case PERIPH_ID_SPI2:
> + case PERIPH_ID_SPI3:
> + case PERIPH_ID_SPI4:
> + exynos5420_spi_config(peripheral);
> + break;
> + case PERIPH_ID_I2C0:
> + case PERIPH_ID_I2C1:
> + case PERIPH_ID_I2C2:
> + case PERIPH_ID_I2C3:
> + case PERIPH_ID_I2C4:
> + case PERIPH_ID_I2C5:
> + case PERIPH_ID_I2C6:
> + case PERIPH_ID_I2C7:
> + case PERIPH_ID_I2C8:
> + case PERIPH_ID_I2C9:
> + case PERIPH_ID_I2C10:
> + exynos5420_i2c_config(peripheral);
> + break;
> + default:
> + debug("%s: invalid peripheral %d", __func__, peripheral);
> + return -1;
> + }
> +
> + return 0;
> +}
> +
> static void exynos4_i2c_config(int peripheral, int flags)
> {
> struct exynos4_gpio_part1 *gpio1 =
> @@ -474,7 +711,9 @@ static int exynos4_pinmux_config(int peripheral, int
> flags)
>
> int exynos_pinmux_config(int peripheral, int flags)
> {
> - if (cpu_is_exynos5()) {
> + if (proid_is_exynos5420()) {
> + return exynos5420_pinmux_config(peripheral, flags);
> + } else if (proid_is_exynos5250()) {
>
please don't mix cpu_is.. and proid_is..
> return exynos5_pinmux_config(peripheral, flags);
> } else if (cpu_is_exynos4()) {
> return exynos4_pinmux_config(peripheral, flags);
> diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
> b/arch/arm/include/asm/arch-exynos/gpio.h
> index a1a7439..2a19852 100644
> --- a/arch/arm/include/asm/arch-exynos/gpio.h
> +++ b/arch/arm/include/asm/arch-exynos/gpio.h
> @@ -127,6 +127,58 @@ struct exynos4x12_gpio_part4 {
> struct s5p_gpio_bank v4;
> };
>
> +struct exynos5420_gpio_part1 {
> + struct s5p_gpio_bank a0;
> + struct s5p_gpio_bank a1;
> + struct s5p_gpio_bank a2;
> + struct s5p_gpio_bank b0;
> + struct s5p_gpio_bank b1;
> + struct s5p_gpio_bank b2;
> + struct s5p_gpio_bank b3;
> + struct s5p_gpio_bank b4;
> + struct s5p_gpio_bank h0;
> +};
> +
> +struct exynos5420_gpio_part2 {
> + struct s5p_gpio_bank y7; /* 0x1340_0000 */
> + struct s5p_gpio_bank res[0x5f]; /* */
> + struct s5p_gpio_bank x0; /* 0x1340_0C00 */
> + struct s5p_gpio_bank x1; /* 0x1340_0C20 */
> + struct s5p_gpio_bank x2; /* 0x1340_0C40 */
> + struct s5p_gpio_bank x3; /* 0x1340_0C60 */
> +};
> +
> +struct exynos5420_gpio_part3 {
> + struct s5p_gpio_bank c0;
> + struct s5p_gpio_bank c1;
> + struct s5p_gpio_bank c2;
> + struct s5p_gpio_bank c3;
> + struct s5p_gpio_bank c4;
> + struct s5p_gpio_bank d1;
> + struct s5p_gpio_bank y0;
> + struct s5p_gpio_bank y1;
> + struct s5p_gpio_bank y2;
> + struct s5p_gpio_bank y3;
> + struct s5p_gpio_bank y4;
> + struct s5p_gpio_bank y5;
> + struct s5p_gpio_bank y6;
> +};
> +
> +struct exynos5420_gpio_part4 {
> + struct s5p_gpio_bank e0; /* 0x1400_0000 */
> + struct s5p_gpio_bank e1; /* 0x1400_0020 */
> + struct s5p_gpio_bank f0; /* 0x1400_0040 */
> + struct s5p_gpio_bank f1; /* 0x1400_0060 */
> + struct s5p_gpio_bank g0; /* 0x1400_0080 */
> + struct s5p_gpio_bank g1; /* 0x1400_00A0 */
> + struct s5p_gpio_bank g2; /* 0x1400_00C0 */
> + struct s5p_gpio_bank j4; /* 0x1400_00E0 */
> +};
> +
> +struct exynos5420_gpio_part5 {
> + struct s5p_gpio_bank z0; /* 0x0386_0000 */
> +};
> +
> struct exynos5_gpio_part1 {
> struct s5p_gpio_bank a0;
> struct s5p_gpio_bank a1;
> @@ -259,16 +311,67 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank,
> int gpio, int mode);
> - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
> * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX)
>
> +
> +/* EXYNOS5420 */
> +#define exynos5420_gpio_part1_get_nr(bank, pin) \
> + ((((((unsigned int) &(((struct exynos5420_gpio_part1 *)\
> + EXYNOS5420_GPIO_PART1_BASE)->bank)) \
> + - EXYNOS5420_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
> + * GPIO_PER_BANK) + pin)
> +
> +#define EXYNOS5420_GPIO_PART1_MAX ((sizeof(struct exynos5420_gpio_part1) \
> + / sizeof(struct s5p_gpio_bank)) *
> GPIO_PER_BANK)
> +
> +#define exynos5420_gpio_part2_get_nr(bank, pin) \
> + (((((((unsigned int) &(((struct exynos5420_gpio_part2 *)\
> + EXYNOS5420_GPIO_PART2_BASE)->bank)) \
> + - EXYNOS5420_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
> + * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART1_MAX)
> +
> +#define EXYNOS5420_GPIO_PART2_MAX ((sizeof(struct exynos5420_gpio_part2) \
> + / sizeof(struct s5p_gpio_bank)) *
> GPIO_PER_BANK)
> +
> +#define exynos5420_gpio_part3_get_nr(bank, pin) \
> + (((((((unsigned int) &(((struct exynos5420_gpio_part3 *)\
> + EXYNOS5420_GPIO_PART3_BASE)->bank)) \
> + - EXYNOS5420_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
> + * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART2_MAX)
> +
> +#define EXYNOS5420_GPIO_PART3_MAX ((sizeof(struct exynos5420_gpio_part3) \
> + / sizeof(struct s5p_gpio_bank)) *
> GPIO_PER_BANK)
> +
> +#define exynos5420_gpio_part4_get_nr(bank, pin) \
> + (((((((unsigned int) &(((struct exynos5420_gpio_part4 *)\
> + EXYNOS5420_GPIO_PART4_BASE)->bank)) \
> + - EXYNOS5420_GPIO_PART4_BASE) / sizeof(struct s5p_gpio_bank)) \
> + * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART3_MAX)
> +
> +#define EXYNOS5420_GPIO_PART4_MAX ((sizeof(struct exynos5420_gpio_part4) \
> + / sizeof(struct s5p_gpio_bank)) *
> GPIO_PER_BANK)
> +
> +#define EXYNOS5420_GPIO_PART5_MAX ((sizeof(struct exynos5420_gpio_part5) \
> + / sizeof(struct s5p_gpio_bank)) *
> GPIO_PER_BANK)
> +
> static inline unsigned int s5p_gpio_base(int nr)
> {
> if (cpu_is_exynos5()) {
> - if (nr < EXYNOS5_GPIO_PART1_MAX)
> - return EXYNOS5_GPIO_PART1_BASE;
> - else if (nr < EXYNOS5_GPIO_PART2_MAX)
> - return EXYNOS5_GPIO_PART2_BASE;
> - else
> - return EXYNOS5_GPIO_PART3_BASE;
> -
> + if (proid_is_exynos5420()) {
> + if (nr < EXYNOS5420_GPIO_PART1_MAX)
> + return EXYNOS5420_GPIO_PART1_BASE;
> + else if (nr < EXYNOS5420_GPIO_PART2_MAX)
> + return EXYNOS5420_GPIO_PART2_BASE;
> + else if (nr < EXYNOS5420_GPIO_PART3_MAX)
> + return EXYNOS5420_GPIO_PART3_BASE;
> + else
> + return EXYNOS5420_GPIO_PART4_BASE;
> + } else {
> + if (nr < EXYNOS5_GPIO_PART1_MAX)
> + return EXYNOS5_GPIO_PART1_BASE;
> + else if (nr < EXYNOS5_GPIO_PART2_MAX)
> + return EXYNOS5_GPIO_PART2_BASE;
> + else
> + return EXYNOS5_GPIO_PART3_BASE;
> + }
> } else if (cpu_is_exynos4()) {
> if (nr < EXYNOS4_GPIO_PART1_MAX)
> return EXYNOS4_GPIO_PART1_BASE;
> @@ -282,13 +385,25 @@ static inline unsigned int s5p_gpio_base(int nr)
> static inline unsigned int s5p_gpio_part_max(int nr)
> {
> if (cpu_is_exynos5()) {
> - if (nr < EXYNOS5_GPIO_PART1_MAX)
> - return 0;
> - else if (nr < EXYNOS5_GPIO_PART2_MAX)
> - return EXYNOS5_GPIO_PART1_MAX;
> - else
> - return EXYNOS5_GPIO_PART2_MAX;
> -
> + if (proid_is_exynos5420()) {
> + if (nr < EXYNOS5420_GPIO_PART1_MAX)
> + return 0;
> + else if (nr < EXYNOS5420_GPIO_PART2_MAX)
> + return EXYNOS5420_GPIO_PART1_MAX;
> + else if (nr < EXYNOS5420_GPIO_PART3_MAX)
> + return EXYNOS5420_GPIO_PART2_MAX;
> + else if (nr < EXYNOS5420_GPIO_PART4_MAX)
> + return EXYNOS5420_GPIO_PART3_MAX;
> + else
> + return EXYNOS5420_GPIO_PART4_MAX;
> + } else {
> + if (nr < EXYNOS5_GPIO_PART1_MAX)
> + return 0;
> + else if (nr < EXYNOS5_GPIO_PART2_MAX)
> + return EXYNOS5_GPIO_PART1_MAX;
> + else
> + return EXYNOS5_GPIO_PART2_MAX;
> + }
> } else if (cpu_is_exynos4()) {
> if (proid_is_exynos4412()) {
> if (nr < EXYNOS4X12_GPIO_PART1_MAX)
> diff --git a/arch/arm/include/asm/arch-exynos/periph.h
> b/arch/arm/include/asm/arch-exynos/periph.h
> index 64bd8b7..30c7f18 100644
> --- a/arch/arm/include/asm/arch-exynos/periph.h
> +++ b/arch/arm/include/asm/arch-exynos/periph.h
> @@ -34,6 +34,9 @@ enum periph_id {
> PERIPH_ID_SDMMC1,
> PERIPH_ID_SDMMC2,
> PERIPH_ID_SDMMC3,
> + PERIPH_ID_I2C8 = 87,
> + PERIPH_ID_I2C9,
> + PERIPH_ID_I2C10 = 203,
> PERIPH_ID_I2S0 = 98,
> PERIPH_ID_I2S1 = 99,
>
> --
> 1.7.12.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
Thanks,
Minkyu Kang.
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 37+ messages in thread* [U-Boot] [PATCH 05/10 V6] Exynos5420: Add support for 5420 in pinmux and gpio
2013-11-13 3:01 ` Minkyu Kang
@ 2013-11-13 6:04 ` Rajeshwari Birje
2013-11-13 6:08 ` Rajeshwari Birje
2013-11-14 2:46 ` Minkyu Kang
0 siblings, 2 replies; 37+ messages in thread
From: Rajeshwari Birje @ 2013-11-13 6:04 UTC (permalink / raw)
To: u-boot
Hi Minkyu Kang,
Thank you for comments.
On Wed, Nov 13, 2013 at 8:31 AM, Minkyu Kang <promsoft@gmail.com> wrote:
> Dear Rajeshwari S Shinde,
>
>
> On 29 October 2013 16:23, Rajeshwari S Shinde <rajeshwari.s@samsung.com>wrote:
>
>> Adds code in pinmux and gpio framework to support Exynos5420.
>>
>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
>> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
>> Acked-by: Simon Glass <sjg@chromium.org>
>> ---
>> Changes in V2:
>> - None
>> Changes in V3:
>> - None
>> Changes in V4:
>> - Added correct calculation of gpio based addresses.
>> Changes in V5:
>> - None
>> Changes in V6:
>> - None
>> arch/arm/cpu/armv7/exynos/pinmux.c | 241
>> +++++++++++++++++++++++++++++-
>> arch/arm/include/asm/arch-exynos/gpio.h | 143 ++++++++++++++++--
>> arch/arm/include/asm/arch-exynos/periph.h | 3 +
>> 3 files changed, 372 insertions(+), 15 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
>> b/arch/arm/cpu/armv7/exynos/pinmux.c
>> index 8002bce..417ecae 100644
>> --- a/arch/arm/cpu/armv7/exynos/pinmux.c
>> +++ b/arch/arm/cpu/armv7/exynos/pinmux.c
>> @@ -46,6 +46,41 @@ static void exynos5_uart_config(int peripheral)
>> }
>> }
>>
>> +static void exynos5420_uart_config(int peripheral)
>> +{
>> + struct exynos5420_gpio_part1 *gpio1 =
>> + (struct exynos5420_gpio_part1
>> *)samsung_get_base_gpio_part1();
>> + struct s5p_gpio_bank *bank;
>> + int i, start, count;
>> +
>> + switch (peripheral) {
>> + case PERIPH_ID_UART0:
>> + bank = &gpio1->a0;
>> + start = 0;
>> + count = 4;
>> + break;
>> + case PERIPH_ID_UART1:
>> + bank = &gpio1->a0;
>> + start = 4;
>> + count = 4;
>> + break;
>> + case PERIPH_ID_UART2:
>> + bank = &gpio1->a1;
>> + start = 0;
>> + count = 4;
>> + break;
>> + case PERIPH_ID_UART3:
>> + bank = &gpio1->a1;
>> + start = 4;
>> + count = 2;
>> + break;
>
> + }
>>
>
> please add blank line.
will correct this
>
>
>> + for (i = start; i < start + count; i++) {
>> + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
>> + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
>> + }
>> +}
>> +
>> static int exynos5_mmc_config(int peripheral, int flags)
>> {
>> struct exynos5_gpio_part1 *gpio1 =
>> @@ -101,6 +136,70 @@ static int exynos5_mmc_config(int peripheral, int
>> flags)
>> return 0;
>> }
>>
>> +static int exynos5420_mmc_config(int peripheral, int flags)
>> +{
>> + struct exynos5420_gpio_part3 *gpio3 =
>> + (struct exynos5420_gpio_part3
>> *)samsung_get_base_gpio_part3();
>> + struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL;
>> + int i, start = 0, gpio_func = 0;
>>
>
> I think we don' have to set to 0 to start and gpio_func.
Will remove gpio_func, but if I dont set start to 0 I get following error:
pinmux.c: In function ?exynos_pinmux_config?:
pinmux.c:173:20: warning: ?start? may be used uninitialized in this
function [-Wmaybe-uninitialized]
pinmux.c:145:9: note: ?start? was declared here
>
>
>> +
>> + switch (peripheral) {
>> + case PERIPH_ID_SDMMC0:
>> + bank = &gpio3->c0;
>> + bank_ext = &gpio3->c3;
>> + start = 0;
>> + gpio_func = GPIO_FUNC(0x2);
>> + break;
>> + case PERIPH_ID_SDMMC1:
>> + bank = &gpio3->c1;
>> + bank_ext = &gpio3->d1;
>> + start = 4;
>> + gpio_func = GPIO_FUNC(0x2);
>> + break;
>> + case PERIPH_ID_SDMMC2:
>> + bank = &gpio3->c2;
>> + bank_ext = NULL;
>> + gpio_func = GPIO_FUNC(0x2);
>> + break;
>
> + }
>>
>
> please add blank line.
Will correct this
>
>
>> + if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
>> + debug("SDMMC device %d does not support 8bit mode",
>> + peripheral);
>> + return -1;
>> + }
>>
>
> please add blank line.
Will correct this
>
>
>> + if (flags & PINMUX_FLAG_8BIT_MODE) {
>> + for (i = start; i <= (start + 3); i++) {
>> + s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
>>
>
> gpio_func is always GPIO_FUNC(0x2).
> I think gpio_func is unnecessary.
will remove this
>
>
>> + s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
>> + s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
>> + }
>> + }
>>
>
> please add blank line.
Will correct this
>
>
>> + for (i = 0; i < 3; i++) {
>> + /*
>> + * MMC0 is intended to be used for eMMC. The
>> + * card detect pin is used as a VDDEN signal to
>> + * power on the eMMC. The 5420 iROM makes
>> + * this same assumption.
>> + */
>> + if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) {
>> + s5p_gpio_set_value(bank, i, 1);
>> + s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT);
>> + } else {
>> + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
>> + }
>> + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
>> + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
>> + }
>> +
>> + for (i = 3; i <= 6; i++) {
>> + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
>> + s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
>> + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> static void exynos5_sromc_config(int flags)
>> {
>> struct exynos5_gpio_part1 *gpio1 =
>> @@ -216,6 +315,59 @@ static void exynos5_i2c_config(int peripheral, int
>> flags)
>> }
>> }
>>
>> +static void exynos5420_i2c_config(int peripheral)
>> +{
>> + struct exynos5420_gpio_part1 *gpio1 =
>> + (struct exynos5420_gpio_part1
>> *)samsung_get_base_gpio_part1();
>> +
>> + switch (peripheral) {
>> + case PERIPH_ID_I2C0:
>> + s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
>> + s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
>> + break;
>> + case PERIPH_ID_I2C1:
>> + s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
>> + s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
>> + break;
>> + case PERIPH_ID_I2C2:
>> + s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
>> + s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
>> + break;
>> + case PERIPH_ID_I2C3:
>> + s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
>> + s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
>> + break;
>> + case PERIPH_ID_I2C4:
>> + s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
>> + s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
>> + break;
>> + case PERIPH_ID_I2C5:
>> + s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
>> + s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
>> + break;
>> + case PERIPH_ID_I2C6:
>> + s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
>> + s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
>> + break;
>> + case PERIPH_ID_I2C7:
>> + s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
>> + s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
>> + break;
>> + case PERIPH_ID_I2C8:
>> + s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2));
>> + s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2));
>> + break;
>> + case PERIPH_ID_I2C9:
>> + s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2));
>> + s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2));
>> + break;
>> + case PERIPH_ID_I2C10:
>> + s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2));
>> + s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2));
>> + break;
>> + }
>> +}
>> +
>> static void exynos5_i2s_config(int peripheral)
>> {
>> int i;
>> @@ -279,6 +431,49 @@ void exynos5_spi_config(int peripheral)
>> }
>> }
>>
>> +void exynos5420_spi_config(int peripheral)
>> +{
>> + int cfg = 0, pin = 0, i;
>>
>
> please don't set to 0 at here.
> We should set some values at switch..case.
Get the following warning:
pinmux.c: In function ?exynos5420_spi_config?:
pinmux.c:471:3: warning: ?pin? may be used uninitialized in this
function [-Wmaybe-uninitialized]
pinmux.c:472:20: warning: ?cfg? may be used uninitialized in this
function [-Wmaybe-uninitialized]
>
>> + struct s5p_gpio_bank *bank = NULL;
>> + struct exynos5420_gpio_part1 *gpio1 =
>> + (struct exynos5420_gpio_part1
>> *)samsung_get_base_gpio_part1();
>> + struct exynos5420_gpio_part4 *gpio4 =
>> + (struct exynos5420_gpio_part4
>> *)samsung_get_base_gpio_part4();
>> +
>> + switch (peripheral) {
>> + case PERIPH_ID_SPI0:
>> + bank = &gpio1->a2;
>> + cfg = GPIO_FUNC(0x2);
>> + pin = 0;
>> + break;
>> + case PERIPH_ID_SPI1:
>> + bank = &gpio1->a2;
>> + cfg = GPIO_FUNC(0x2);
>> + pin = 4;
>> + break;
>> + case PERIPH_ID_SPI2:
>> + bank = &gpio1->b1;
>> + cfg = GPIO_FUNC(0x5);
>> + pin = 1;
>> + break;
>> + case PERIPH_ID_SPI3:
>> + bank = &gpio4->f1;
>> + cfg = GPIO_FUNC(0x2);
>> + pin = 0;
>> + break;
>> + case PERIPH_ID_SPI4:
>> + for (i = 0; i < 2; i++) {
>> + s5p_gpio_cfg_pin(&gpio4->f0, i + 2,
>> GPIO_FUNC(0x4));
>> + s5p_gpio_cfg_pin(&gpio4->e0, i + 4,
>> GPIO_FUNC(0x4));
>> + }
>>
>
> OK. I understood SPI4 is different with other SPIs.
> but, it was another context.
> just break and move it to out of this switch..case.
>
>
>> + break;
>
> + }
>>
>
> please add blank line.
>
>
>> + if (peripheral != PERIPH_ID_SPI4) {
>> + for (i = pin; i < pin + 4; i++)
>> + s5p_gpio_cfg_pin(bank, i, cfg);
>> + }
>> +}
>> +
>> static int exynos5_pinmux_config(int peripheral, int flags)
>> {
>> switch (peripheral) {
>> @@ -325,6 +520,48 @@ static int exynos5_pinmux_config(int peripheral, int
>> flags)
>> return 0;
>> }
>>
>> +static int exynos5420_pinmux_config(int peripheral, int flags)
>> +{
>> + switch (peripheral) {
>> + case PERIPH_ID_UART0:
>> + case PERIPH_ID_UART1:
>> + case PERIPH_ID_UART2:
>> + case PERIPH_ID_UART3:
>> + exynos5420_uart_config(peripheral);
>> + break;
>> + case PERIPH_ID_SDMMC0:
>> + case PERIPH_ID_SDMMC1:
>> + case PERIPH_ID_SDMMC2:
>> + case PERIPH_ID_SDMMC3:
>> + return exynos5420_mmc_config(peripheral, flags);
>> + case PERIPH_ID_SPI0:
>> + case PERIPH_ID_SPI1:
>> + case PERIPH_ID_SPI2:
>> + case PERIPH_ID_SPI3:
>> + case PERIPH_ID_SPI4:
>> + exynos5420_spi_config(peripheral);
>> + break;
>> + case PERIPH_ID_I2C0:
>> + case PERIPH_ID_I2C1:
>> + case PERIPH_ID_I2C2:
>> + case PERIPH_ID_I2C3:
>> + case PERIPH_ID_I2C4:
>> + case PERIPH_ID_I2C5:
>> + case PERIPH_ID_I2C6:
>> + case PERIPH_ID_I2C7:
>> + case PERIPH_ID_I2C8:
>> + case PERIPH_ID_I2C9:
>> + case PERIPH_ID_I2C10:
>> + exynos5420_i2c_config(peripheral);
>> + break;
>> + default:
>> + debug("%s: invalid peripheral %d", __func__, peripheral);
>> + return -1;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> static void exynos4_i2c_config(int peripheral, int flags)
>> {
>> struct exynos4_gpio_part1 *gpio1 =
>> @@ -474,7 +711,9 @@ static int exynos4_pinmux_config(int peripheral, int
>> flags)
>>
>> int exynos_pinmux_config(int peripheral, int flags)
>> {
>> - if (cpu_is_exynos5()) {
>> + if (proid_is_exynos5420()) {
>> + return exynos5420_pinmux_config(peripheral, flags);
>> + } else if (proid_is_exynos5250()) {
>>
>
> please don't mix cpu_is.. and proid_is..
Will correct this.
>
>
>> return exynos5_pinmux_config(peripheral, flags);
>> } else if (cpu_is_exynos4()) {
>> return exynos4_pinmux_config(peripheral, flags);
>> diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
>> b/arch/arm/include/asm/arch-exynos/gpio.h
>> index a1a7439..2a19852 100644
>> --- a/arch/arm/include/asm/arch-exynos/gpio.h
>> +++ b/arch/arm/include/asm/arch-exynos/gpio.h
>> @@ -127,6 +127,58 @@ struct exynos4x12_gpio_part4 {
>> struct s5p_gpio_bank v4;
>> };
>>
>> +struct exynos5420_gpio_part1 {
>> + struct s5p_gpio_bank a0;
>> + struct s5p_gpio_bank a1;
>> + struct s5p_gpio_bank a2;
>> + struct s5p_gpio_bank b0;
>> + struct s5p_gpio_bank b1;
>> + struct s5p_gpio_bank b2;
>> + struct s5p_gpio_bank b3;
>> + struct s5p_gpio_bank b4;
>> + struct s5p_gpio_bank h0;
>> +};
>> +
>> +struct exynos5420_gpio_part2 {
>> + struct s5p_gpio_bank y7; /* 0x1340_0000 */
>> + struct s5p_gpio_bank res[0x5f]; /* */
>> + struct s5p_gpio_bank x0; /* 0x1340_0C00 */
>> + struct s5p_gpio_bank x1; /* 0x1340_0C20 */
>> + struct s5p_gpio_bank x2; /* 0x1340_0C40 */
>> + struct s5p_gpio_bank x3; /* 0x1340_0C60 */
>> +};
>> +
>> +struct exynos5420_gpio_part3 {
>> + struct s5p_gpio_bank c0;
>> + struct s5p_gpio_bank c1;
>> + struct s5p_gpio_bank c2;
>> + struct s5p_gpio_bank c3;
>> + struct s5p_gpio_bank c4;
>> + struct s5p_gpio_bank d1;
>> + struct s5p_gpio_bank y0;
>> + struct s5p_gpio_bank y1;
>> + struct s5p_gpio_bank y2;
>> + struct s5p_gpio_bank y3;
>> + struct s5p_gpio_bank y4;
>> + struct s5p_gpio_bank y5;
>> + struct s5p_gpio_bank y6;
>> +};
>> +
>> +struct exynos5420_gpio_part4 {
>> + struct s5p_gpio_bank e0; /* 0x1400_0000 */
>> + struct s5p_gpio_bank e1; /* 0x1400_0020 */
>> + struct s5p_gpio_bank f0; /* 0x1400_0040 */
>> + struct s5p_gpio_bank f1; /* 0x1400_0060 */
>> + struct s5p_gpio_bank g0; /* 0x1400_0080 */
>> + struct s5p_gpio_bank g1; /* 0x1400_00A0 */
>> + struct s5p_gpio_bank g2; /* 0x1400_00C0 */
>> + struct s5p_gpio_bank j4; /* 0x1400_00E0 */
>> +};
>> +
>> +struct exynos5420_gpio_part5 {
>> + struct s5p_gpio_bank z0; /* 0x0386_0000 */
>> +};
>> +
>> struct exynos5_gpio_part1 {
>> struct s5p_gpio_bank a0;
>> struct s5p_gpio_bank a1;
>> @@ -259,16 +311,67 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank,
>> int gpio, int mode);
>> - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
>> * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX)
>>
>> +
>> +/* EXYNOS5420 */
>> +#define exynos5420_gpio_part1_get_nr(bank, pin) \
>> + ((((((unsigned int) &(((struct exynos5420_gpio_part1 *)\
>> + EXYNOS5420_GPIO_PART1_BASE)->bank)) \
>> + - EXYNOS5420_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
>> + * GPIO_PER_BANK) + pin)
>> +
>> +#define EXYNOS5420_GPIO_PART1_MAX ((sizeof(struct exynos5420_gpio_part1) \
>> + / sizeof(struct s5p_gpio_bank)) *
>> GPIO_PER_BANK)
>> +
>> +#define exynos5420_gpio_part2_get_nr(bank, pin) \
>> + (((((((unsigned int) &(((struct exynos5420_gpio_part2 *)\
>> + EXYNOS5420_GPIO_PART2_BASE)->bank)) \
>> + - EXYNOS5420_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
>> + * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART1_MAX)
>> +
>> +#define EXYNOS5420_GPIO_PART2_MAX ((sizeof(struct exynos5420_gpio_part2) \
>> + / sizeof(struct s5p_gpio_bank)) *
>> GPIO_PER_BANK)
>> +
>> +#define exynos5420_gpio_part3_get_nr(bank, pin) \
>> + (((((((unsigned int) &(((struct exynos5420_gpio_part3 *)\
>> + EXYNOS5420_GPIO_PART3_BASE)->bank)) \
>> + - EXYNOS5420_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
>> + * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART2_MAX)
>> +
>> +#define EXYNOS5420_GPIO_PART3_MAX ((sizeof(struct exynos5420_gpio_part3) \
>> + / sizeof(struct s5p_gpio_bank)) *
>> GPIO_PER_BANK)
>> +
>> +#define exynos5420_gpio_part4_get_nr(bank, pin) \
>> + (((((((unsigned int) &(((struct exynos5420_gpio_part4 *)\
>> + EXYNOS5420_GPIO_PART4_BASE)->bank)) \
>> + - EXYNOS5420_GPIO_PART4_BASE) / sizeof(struct s5p_gpio_bank)) \
>> + * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART3_MAX)
>> +
>> +#define EXYNOS5420_GPIO_PART4_MAX ((sizeof(struct exynos5420_gpio_part4) \
>> + / sizeof(struct s5p_gpio_bank)) *
>> GPIO_PER_BANK)
>> +
>> +#define EXYNOS5420_GPIO_PART5_MAX ((sizeof(struct exynos5420_gpio_part5) \
>> + / sizeof(struct s5p_gpio_bank)) *
>> GPIO_PER_BANK)
>> +
>> static inline unsigned int s5p_gpio_base(int nr)
>> {
>> if (cpu_is_exynos5()) {
>> - if (nr < EXYNOS5_GPIO_PART1_MAX)
>> - return EXYNOS5_GPIO_PART1_BASE;
>> - else if (nr < EXYNOS5_GPIO_PART2_MAX)
>> - return EXYNOS5_GPIO_PART2_BASE;
>> - else
>> - return EXYNOS5_GPIO_PART3_BASE;
>> -
>> + if (proid_is_exynos5420()) {
>> + if (nr < EXYNOS5420_GPIO_PART1_MAX)
>> + return EXYNOS5420_GPIO_PART1_BASE;
>> + else if (nr < EXYNOS5420_GPIO_PART2_MAX)
>> + return EXYNOS5420_GPIO_PART2_BASE;
>> + else if (nr < EXYNOS5420_GPIO_PART3_MAX)
>> + return EXYNOS5420_GPIO_PART3_BASE;
>> + else
>> + return EXYNOS5420_GPIO_PART4_BASE;
>> + } else {
>> + if (nr < EXYNOS5_GPIO_PART1_MAX)
>> + return EXYNOS5_GPIO_PART1_BASE;
>> + else if (nr < EXYNOS5_GPIO_PART2_MAX)
>> + return EXYNOS5_GPIO_PART2_BASE;
>> + else
>> + return EXYNOS5_GPIO_PART3_BASE;
>> + }
>> } else if (cpu_is_exynos4()) {
>> if (nr < EXYNOS4_GPIO_PART1_MAX)
>> return EXYNOS4_GPIO_PART1_BASE;
>> @@ -282,13 +385,25 @@ static inline unsigned int s5p_gpio_base(int nr)
>> static inline unsigned int s5p_gpio_part_max(int nr)
>> {
>> if (cpu_is_exynos5()) {
>> - if (nr < EXYNOS5_GPIO_PART1_MAX)
>> - return 0;
>> - else if (nr < EXYNOS5_GPIO_PART2_MAX)
>> - return EXYNOS5_GPIO_PART1_MAX;
>> - else
>> - return EXYNOS5_GPIO_PART2_MAX;
>> -
>> + if (proid_is_exynos5420()) {
>> + if (nr < EXYNOS5420_GPIO_PART1_MAX)
>> + return 0;
>> + else if (nr < EXYNOS5420_GPIO_PART2_MAX)
>> + return EXYNOS5420_GPIO_PART1_MAX;
>> + else if (nr < EXYNOS5420_GPIO_PART3_MAX)
>> + return EXYNOS5420_GPIO_PART2_MAX;
>> + else if (nr < EXYNOS5420_GPIO_PART4_MAX)
>> + return EXYNOS5420_GPIO_PART3_MAX;
>> + else
>> + return EXYNOS5420_GPIO_PART4_MAX;
>> + } else {
>> + if (nr < EXYNOS5_GPIO_PART1_MAX)
>> + return 0;
>> + else if (nr < EXYNOS5_GPIO_PART2_MAX)
>> + return EXYNOS5_GPIO_PART1_MAX;
>> + else
>> + return EXYNOS5_GPIO_PART2_MAX;
>> + }
>> } else if (cpu_is_exynos4()) {
>> if (proid_is_exynos4412()) {
>> if (nr < EXYNOS4X12_GPIO_PART1_MAX)
>> diff --git a/arch/arm/include/asm/arch-exynos/periph.h
>> b/arch/arm/include/asm/arch-exynos/periph.h
>> index 64bd8b7..30c7f18 100644
>> --- a/arch/arm/include/asm/arch-exynos/periph.h
>> +++ b/arch/arm/include/asm/arch-exynos/periph.h
>> @@ -34,6 +34,9 @@ enum periph_id {
>> PERIPH_ID_SDMMC1,
>> PERIPH_ID_SDMMC2,
>> PERIPH_ID_SDMMC3,
>> + PERIPH_ID_I2C8 = 87,
>> + PERIPH_ID_I2C9,
>> + PERIPH_ID_I2C10 = 203,
>> PERIPH_ID_I2S0 = 98,
>> PERIPH_ID_I2S1 = 99,
>>
>> --
>> 1.7.12.4
>>
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
>>
>
> Thanks,
> Minkyu Kang.
> --
> from. prom.
> www.promsoft.net
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
--
Regards,
Rajeshwari Shinde
^ permalink raw reply [flat|nested] 37+ messages in thread* [U-Boot] [PATCH 05/10 V6] Exynos5420: Add support for 5420 in pinmux and gpio
2013-11-13 6:04 ` Rajeshwari Birje
@ 2013-11-13 6:08 ` Rajeshwari Birje
2013-11-14 2:46 ` Minkyu Kang
1 sibling, 0 replies; 37+ messages in thread
From: Rajeshwari Birje @ 2013-11-13 6:08 UTC (permalink / raw)
To: u-boot
Hi Minkyu Kang,
On Wed, Nov 13, 2013 at 11:34 AM, Rajeshwari Birje
<rajeshwari.birje@gmail.com> wrote:
> Hi Minkyu Kang,
>
> Thank you for comments.
>
> On Wed, Nov 13, 2013 at 8:31 AM, Minkyu Kang <promsoft@gmail.com> wrote:
>> Dear Rajeshwari S Shinde,
>>
>>
>> On 29 October 2013 16:23, Rajeshwari S Shinde <rajeshwari.s@samsung.com>wrote:
>>
>>> Adds code in pinmux and gpio framework to support Exynos5420.
>>>
>>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>>> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
>>> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
>>> Acked-by: Simon Glass <sjg@chromium.org>
>>> ---
>>> Changes in V2:
>>> - None
>>> Changes in V3:
>>> - None
>>> Changes in V4:
>>> - Added correct calculation of gpio based addresses.
>>> Changes in V5:
>>> - None
>>> Changes in V6:
>>> - None
>>> arch/arm/cpu/armv7/exynos/pinmux.c | 241
>>> +++++++++++++++++++++++++++++-
>>> arch/arm/include/asm/arch-exynos/gpio.h | 143 ++++++++++++++++--
>>> arch/arm/include/asm/arch-exynos/periph.h | 3 +
>>> 3 files changed, 372 insertions(+), 15 deletions(-)
>>>
>>> diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
>>> b/arch/arm/cpu/armv7/exynos/pinmux.c
>>> index 8002bce..417ecae 100644
>>> --- a/arch/arm/cpu/armv7/exynos/pinmux.c
>>> +++ b/arch/arm/cpu/armv7/exynos/pinmux.c
>>> @@ -46,6 +46,41 @@ static void exynos5_uart_config(int peripheral)
>>> }
>>> }
>>>
>>> +static void exynos5420_uart_config(int peripheral)
>>> +{
>>> + struct exynos5420_gpio_part1 *gpio1 =
>>> + (struct exynos5420_gpio_part1
>>> *)samsung_get_base_gpio_part1();
>>> + struct s5p_gpio_bank *bank;
>>> + int i, start, count;
>>> +
>>> + switch (peripheral) {
>>> + case PERIPH_ID_UART0:
>>> + bank = &gpio1->a0;
>>> + start = 0;
>>> + count = 4;
>>> + break;
>>> + case PERIPH_ID_UART1:
>>> + bank = &gpio1->a0;
>>> + start = 4;
>>> + count = 4;
>>> + break;
>>> + case PERIPH_ID_UART2:
>>> + bank = &gpio1->a1;
>>> + start = 0;
>>> + count = 4;
>>> + break;
>>> + case PERIPH_ID_UART3:
>>> + bank = &gpio1->a1;
>>> + start = 4;
>>> + count = 2;
>>> + break;
>>
>> + }
>>>
>>
>> please add blank line.
> will correct this
>>
>>
>>> + for (i = start; i < start + count; i++) {
>>> + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
>>> + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
>>> + }
>>> +}
>>> +
>>> static int exynos5_mmc_config(int peripheral, int flags)
>>> {
>>> struct exynos5_gpio_part1 *gpio1 =
>>> @@ -101,6 +136,70 @@ static int exynos5_mmc_config(int peripheral, int
>>> flags)
>>> return 0;
>>> }
>>>
>>> +static int exynos5420_mmc_config(int peripheral, int flags)
>>> +{
>>> + struct exynos5420_gpio_part3 *gpio3 =
>>> + (struct exynos5420_gpio_part3
>>> *)samsung_get_base_gpio_part3();
>>> + struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL;
>>> + int i, start = 0, gpio_func = 0;
>>>
>>
>> I think we don' have to set to 0 to start and gpio_func.
> Will remove gpio_func, but if I dont set start to 0 I get following error:
>
> pinmux.c: In function ?exynos_pinmux_config?:
> pinmux.c:173:20: warning: ?start? may be used uninitialized in this
> function [-Wmaybe-uninitialized]
> pinmux.c:145:9: note: ?start? was declared here
>>
>>
>>> +
>>> + switch (peripheral) {
>>> + case PERIPH_ID_SDMMC0:
>>> + bank = &gpio3->c0;
>>> + bank_ext = &gpio3->c3;
>>> + start = 0;
>>> + gpio_func = GPIO_FUNC(0x2);
>>> + break;
>>> + case PERIPH_ID_SDMMC1:
>>> + bank = &gpio3->c1;
>>> + bank_ext = &gpio3->d1;
>>> + start = 4;
>>> + gpio_func = GPIO_FUNC(0x2);
>>> + break;
>>> + case PERIPH_ID_SDMMC2:
>>> + bank = &gpio3->c2;
>>> + bank_ext = NULL;
>>> + gpio_func = GPIO_FUNC(0x2);
>>> + break;
>>
>> + }
>>>
>>
>> please add blank line.
> Will correct this
>>
>>
>>> + if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
>>> + debug("SDMMC device %d does not support 8bit mode",
>>> + peripheral);
>>> + return -1;
>>> + }
>>>
>>
>> please add blank line.
> Will correct this
>>
>>
>>> + if (flags & PINMUX_FLAG_8BIT_MODE) {
>>> + for (i = start; i <= (start + 3); i++) {
>>> + s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
>>>
>>
>> gpio_func is always GPIO_FUNC(0x2).
>> I think gpio_func is unnecessary.
> will remove this
>>
>>
>>> + s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
>>> + s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
>>> + }
>>> + }
>>>
>>
>> please add blank line.
> Will correct this
>>
>>
>>> + for (i = 0; i < 3; i++) {
>>> + /*
>>> + * MMC0 is intended to be used for eMMC. The
>>> + * card detect pin is used as a VDDEN signal to
>>> + * power on the eMMC. The 5420 iROM makes
>>> + * this same assumption.
>>> + */
>>> + if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) {
>>> + s5p_gpio_set_value(bank, i, 1);
>>> + s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT);
>>> + } else {
>>> + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
>>> + }
>>> + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
>>> + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
>>> + }
>>> +
>>> + for (i = 3; i <= 6; i++) {
>>> + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
>>> + s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
>>> + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +
>>> static void exynos5_sromc_config(int flags)
>>> {
>>> struct exynos5_gpio_part1 *gpio1 =
>>> @@ -216,6 +315,59 @@ static void exynos5_i2c_config(int peripheral, int
>>> flags)
>>> }
>>> }
>>>
>>> +static void exynos5420_i2c_config(int peripheral)
>>> +{
>>> + struct exynos5420_gpio_part1 *gpio1 =
>>> + (struct exynos5420_gpio_part1
>>> *)samsung_get_base_gpio_part1();
>>> +
>>> + switch (peripheral) {
>>> + case PERIPH_ID_I2C0:
>>> + s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
>>> + s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
>>> + break;
>>> + case PERIPH_ID_I2C1:
>>> + s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
>>> + s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
>>> + break;
>>> + case PERIPH_ID_I2C2:
>>> + s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
>>> + s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
>>> + break;
>>> + case PERIPH_ID_I2C3:
>>> + s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
>>> + s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
>>> + break;
>>> + case PERIPH_ID_I2C4:
>>> + s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
>>> + s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
>>> + break;
>>> + case PERIPH_ID_I2C5:
>>> + s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
>>> + s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
>>> + break;
>>> + case PERIPH_ID_I2C6:
>>> + s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
>>> + s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
>>> + break;
>>> + case PERIPH_ID_I2C7:
>>> + s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
>>> + s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
>>> + break;
>>> + case PERIPH_ID_I2C8:
>>> + s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2));
>>> + s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2));
>>> + break;
>>> + case PERIPH_ID_I2C9:
>>> + s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2));
>>> + s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2));
>>> + break;
>>> + case PERIPH_ID_I2C10:
>>> + s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2));
>>> + s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2));
>>> + break;
>>> + }
>>> +}
>>> +
>>> static void exynos5_i2s_config(int peripheral)
>>> {
>>> int i;
>>> @@ -279,6 +431,49 @@ void exynos5_spi_config(int peripheral)
>>> }
>>> }
>>>
>>> +void exynos5420_spi_config(int peripheral)
>>> +{
>>> + int cfg = 0, pin = 0, i;
>>>
>>
>> please don't set to 0 at here.
>> We should set some values at switch..case.
> Get the following warning:
> pinmux.c: In function ?exynos5420_spi_config?:
> pinmux.c:471:3: warning: ?pin? may be used uninitialized in this
> function [-Wmaybe-uninitialized]
> pinmux.c:472:20: warning: ?cfg? may be used uninitialized in this
> function [-Wmaybe-uninitialized]
>>
>>> + struct s5p_gpio_bank *bank = NULL;
>>> + struct exynos5420_gpio_part1 *gpio1 =
>>> + (struct exynos5420_gpio_part1
>>> *)samsung_get_base_gpio_part1();
>>> + struct exynos5420_gpio_part4 *gpio4 =
>>> + (struct exynos5420_gpio_part4
>>> *)samsung_get_base_gpio_part4();
>>> +
>>> + switch (peripheral) {
>>> + case PERIPH_ID_SPI0:
>>> + bank = &gpio1->a2;
>>> + cfg = GPIO_FUNC(0x2);
>>> + pin = 0;
>>> + break;
>>> + case PERIPH_ID_SPI1:
>>> + bank = &gpio1->a2;
>>> + cfg = GPIO_FUNC(0x2);
>>> + pin = 4;
>>> + break;
>>> + case PERIPH_ID_SPI2:
>>> + bank = &gpio1->b1;
>>> + cfg = GPIO_FUNC(0x5);
>>> + pin = 1;
>>> + break;
>>> + case PERIPH_ID_SPI3:
>>> + bank = &gpio4->f1;
>>> + cfg = GPIO_FUNC(0x2);
>>> + pin = 0;
>>> + break;
>>> + case PERIPH_ID_SPI4:
>>> + for (i = 0; i < 2; i++) {
>>> + s5p_gpio_cfg_pin(&gpio4->f0, i + 2,
>>> GPIO_FUNC(0x4));
>>> + s5p_gpio_cfg_pin(&gpio4->e0, i + 4,
>>> GPIO_FUNC(0x4));
>>> + }
>>>
>>
>> OK. I understood SPI4 is different with other SPIs.
>> but, it was another context.
>> just break and move it to out of this switch..case.
>>
>>
>>> + break;
>>
>> + }
>>>
>>
>> please add blank line.
>>
>>
>>> + if (peripheral != PERIPH_ID_SPI4) {
>>> + for (i = pin; i < pin + 4; i++)
>>> + s5p_gpio_cfg_pin(bank, i, cfg);
>>> + }
>>> +}
>>> +
>>> static int exynos5_pinmux_config(int peripheral, int flags)
>>> {
>>> switch (peripheral) {
>>> @@ -325,6 +520,48 @@ static int exynos5_pinmux_config(int peripheral, int
>>> flags)
>>> return 0;
>>> }
>>>
>>> +static int exynos5420_pinmux_config(int peripheral, int flags)
>>> +{
>>> + switch (peripheral) {
>>> + case PERIPH_ID_UART0:
>>> + case PERIPH_ID_UART1:
>>> + case PERIPH_ID_UART2:
>>> + case PERIPH_ID_UART3:
>>> + exynos5420_uart_config(peripheral);
>>> + break;
>>> + case PERIPH_ID_SDMMC0:
>>> + case PERIPH_ID_SDMMC1:
>>> + case PERIPH_ID_SDMMC2:
>>> + case PERIPH_ID_SDMMC3:
>>> + return exynos5420_mmc_config(peripheral, flags);
>>> + case PERIPH_ID_SPI0:
>>> + case PERIPH_ID_SPI1:
>>> + case PERIPH_ID_SPI2:
>>> + case PERIPH_ID_SPI3:
>>> + case PERIPH_ID_SPI4:
>>> + exynos5420_spi_config(peripheral);
>>> + break;
>>> + case PERIPH_ID_I2C0:
>>> + case PERIPH_ID_I2C1:
>>> + case PERIPH_ID_I2C2:
>>> + case PERIPH_ID_I2C3:
>>> + case PERIPH_ID_I2C4:
>>> + case PERIPH_ID_I2C5:
>>> + case PERIPH_ID_I2C6:
>>> + case PERIPH_ID_I2C7:
>>> + case PERIPH_ID_I2C8:
>>> + case PERIPH_ID_I2C9:
>>> + case PERIPH_ID_I2C10:
>>> + exynos5420_i2c_config(peripheral);
>>> + break;
>>> + default:
>>> + debug("%s: invalid peripheral %d", __func__, peripheral);
>>> + return -1;
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +
>>> static void exynos4_i2c_config(int peripheral, int flags)
>>> {
>>> struct exynos4_gpio_part1 *gpio1 =
>>> @@ -474,7 +711,9 @@ static int exynos4_pinmux_config(int peripheral, int
>>> flags)
>>>
>>> int exynos_pinmux_config(int peripheral, int flags)
>>> {
>>> - if (cpu_is_exynos5()) {
>>> + if (proid_is_exynos5420()) {
>>> + return exynos5420_pinmux_config(peripheral, flags);
>>> + } else if (proid_is_exynos5250()) {
>>>
>>
>> please don't mix cpu_is.. and proid_is..
> Will correct this.
Since we have both 5250 and 5420 in exynos5 used proid_is, to reduce
a extra if loop.
>>
>>
>>> return exynos5_pinmux_config(peripheral, flags);
>>> } else if (cpu_is_exynos4()) {
>>> return exynos4_pinmux_config(peripheral, flags);
>>> diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
>>> b/arch/arm/include/asm/arch-exynos/gpio.h
>>> index a1a7439..2a19852 100644
>>> --- a/arch/arm/include/asm/arch-exynos/gpio.h
>>> +++ b/arch/arm/include/asm/arch-exynos/gpio.h
>>> @@ -127,6 +127,58 @@ struct exynos4x12_gpio_part4 {
>>> struct s5p_gpio_bank v4;
>>> };
>>>
>>> +struct exynos5420_gpio_part1 {
>>> + struct s5p_gpio_bank a0;
>>> + struct s5p_gpio_bank a1;
>>> + struct s5p_gpio_bank a2;
>>> + struct s5p_gpio_bank b0;
>>> + struct s5p_gpio_bank b1;
>>> + struct s5p_gpio_bank b2;
>>> + struct s5p_gpio_bank b3;
>>> + struct s5p_gpio_bank b4;
>>> + struct s5p_gpio_bank h0;
>>> +};
>>> +
>>> +struct exynos5420_gpio_part2 {
>>> + struct s5p_gpio_bank y7; /* 0x1340_0000 */
>>> + struct s5p_gpio_bank res[0x5f]; /* */
>>> + struct s5p_gpio_bank x0; /* 0x1340_0C00 */
>>> + struct s5p_gpio_bank x1; /* 0x1340_0C20 */
>>> + struct s5p_gpio_bank x2; /* 0x1340_0C40 */
>>> + struct s5p_gpio_bank x3; /* 0x1340_0C60 */
>>> +};
>>> +
>>> +struct exynos5420_gpio_part3 {
>>> + struct s5p_gpio_bank c0;
>>> + struct s5p_gpio_bank c1;
>>> + struct s5p_gpio_bank c2;
>>> + struct s5p_gpio_bank c3;
>>> + struct s5p_gpio_bank c4;
>>> + struct s5p_gpio_bank d1;
>>> + struct s5p_gpio_bank y0;
>>> + struct s5p_gpio_bank y1;
>>> + struct s5p_gpio_bank y2;
>>> + struct s5p_gpio_bank y3;
>>> + struct s5p_gpio_bank y4;
>>> + struct s5p_gpio_bank y5;
>>> + struct s5p_gpio_bank y6;
>>> +};
>>> +
>>> +struct exynos5420_gpio_part4 {
>>> + struct s5p_gpio_bank e0; /* 0x1400_0000 */
>>> + struct s5p_gpio_bank e1; /* 0x1400_0020 */
>>> + struct s5p_gpio_bank f0; /* 0x1400_0040 */
>>> + struct s5p_gpio_bank f1; /* 0x1400_0060 */
>>> + struct s5p_gpio_bank g0; /* 0x1400_0080 */
>>> + struct s5p_gpio_bank g1; /* 0x1400_00A0 */
>>> + struct s5p_gpio_bank g2; /* 0x1400_00C0 */
>>> + struct s5p_gpio_bank j4; /* 0x1400_00E0 */
>>> +};
>>> +
>>> +struct exynos5420_gpio_part5 {
>>> + struct s5p_gpio_bank z0; /* 0x0386_0000 */
>>> +};
>>> +
>>> struct exynos5_gpio_part1 {
>>> struct s5p_gpio_bank a0;
>>> struct s5p_gpio_bank a1;
>>> @@ -259,16 +311,67 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank,
>>> int gpio, int mode);
>>> - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
>>> * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX)
>>>
>>> +
>>> +/* EXYNOS5420 */
>>> +#define exynos5420_gpio_part1_get_nr(bank, pin) \
>>> + ((((((unsigned int) &(((struct exynos5420_gpio_part1 *)\
>>> + EXYNOS5420_GPIO_PART1_BASE)->bank)) \
>>> + - EXYNOS5420_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
>>> + * GPIO_PER_BANK) + pin)
>>> +
>>> +#define EXYNOS5420_GPIO_PART1_MAX ((sizeof(struct exynos5420_gpio_part1) \
>>> + / sizeof(struct s5p_gpio_bank)) *
>>> GPIO_PER_BANK)
>>> +
>>> +#define exynos5420_gpio_part2_get_nr(bank, pin) \
>>> + (((((((unsigned int) &(((struct exynos5420_gpio_part2 *)\
>>> + EXYNOS5420_GPIO_PART2_BASE)->bank)) \
>>> + - EXYNOS5420_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
>>> + * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART1_MAX)
>>> +
>>> +#define EXYNOS5420_GPIO_PART2_MAX ((sizeof(struct exynos5420_gpio_part2) \
>>> + / sizeof(struct s5p_gpio_bank)) *
>>> GPIO_PER_BANK)
>>> +
>>> +#define exynos5420_gpio_part3_get_nr(bank, pin) \
>>> + (((((((unsigned int) &(((struct exynos5420_gpio_part3 *)\
>>> + EXYNOS5420_GPIO_PART3_BASE)->bank)) \
>>> + - EXYNOS5420_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
>>> + * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART2_MAX)
>>> +
>>> +#define EXYNOS5420_GPIO_PART3_MAX ((sizeof(struct exynos5420_gpio_part3) \
>>> + / sizeof(struct s5p_gpio_bank)) *
>>> GPIO_PER_BANK)
>>> +
>>> +#define exynos5420_gpio_part4_get_nr(bank, pin) \
>>> + (((((((unsigned int) &(((struct exynos5420_gpio_part4 *)\
>>> + EXYNOS5420_GPIO_PART4_BASE)->bank)) \
>>> + - EXYNOS5420_GPIO_PART4_BASE) / sizeof(struct s5p_gpio_bank)) \
>>> + * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART3_MAX)
>>> +
>>> +#define EXYNOS5420_GPIO_PART4_MAX ((sizeof(struct exynos5420_gpio_part4) \
>>> + / sizeof(struct s5p_gpio_bank)) *
>>> GPIO_PER_BANK)
>>> +
>>> +#define EXYNOS5420_GPIO_PART5_MAX ((sizeof(struct exynos5420_gpio_part5) \
>>> + / sizeof(struct s5p_gpio_bank)) *
>>> GPIO_PER_BANK)
>>> +
>>> static inline unsigned int s5p_gpio_base(int nr)
>>> {
>>> if (cpu_is_exynos5()) {
>>> - if (nr < EXYNOS5_GPIO_PART1_MAX)
>>> - return EXYNOS5_GPIO_PART1_BASE;
>>> - else if (nr < EXYNOS5_GPIO_PART2_MAX)
>>> - return EXYNOS5_GPIO_PART2_BASE;
>>> - else
>>> - return EXYNOS5_GPIO_PART3_BASE;
>>> -
>>> + if (proid_is_exynos5420()) {
>>> + if (nr < EXYNOS5420_GPIO_PART1_MAX)
>>> + return EXYNOS5420_GPIO_PART1_BASE;
>>> + else if (nr < EXYNOS5420_GPIO_PART2_MAX)
>>> + return EXYNOS5420_GPIO_PART2_BASE;
>>> + else if (nr < EXYNOS5420_GPIO_PART3_MAX)
>>> + return EXYNOS5420_GPIO_PART3_BASE;
>>> + else
>>> + return EXYNOS5420_GPIO_PART4_BASE;
>>> + } else {
>>> + if (nr < EXYNOS5_GPIO_PART1_MAX)
>>> + return EXYNOS5_GPIO_PART1_BASE;
>>> + else if (nr < EXYNOS5_GPIO_PART2_MAX)
>>> + return EXYNOS5_GPIO_PART2_BASE;
>>> + else
>>> + return EXYNOS5_GPIO_PART3_BASE;
>>> + }
>>> } else if (cpu_is_exynos4()) {
>>> if (nr < EXYNOS4_GPIO_PART1_MAX)
>>> return EXYNOS4_GPIO_PART1_BASE;
>>> @@ -282,13 +385,25 @@ static inline unsigned int s5p_gpio_base(int nr)
>>> static inline unsigned int s5p_gpio_part_max(int nr)
>>> {
>>> if (cpu_is_exynos5()) {
>>> - if (nr < EXYNOS5_GPIO_PART1_MAX)
>>> - return 0;
>>> - else if (nr < EXYNOS5_GPIO_PART2_MAX)
>>> - return EXYNOS5_GPIO_PART1_MAX;
>>> - else
>>> - return EXYNOS5_GPIO_PART2_MAX;
>>> -
>>> + if (proid_is_exynos5420()) {
>>> + if (nr < EXYNOS5420_GPIO_PART1_MAX)
>>> + return 0;
>>> + else if (nr < EXYNOS5420_GPIO_PART2_MAX)
>>> + return EXYNOS5420_GPIO_PART1_MAX;
>>> + else if (nr < EXYNOS5420_GPIO_PART3_MAX)
>>> + return EXYNOS5420_GPIO_PART2_MAX;
>>> + else if (nr < EXYNOS5420_GPIO_PART4_MAX)
>>> + return EXYNOS5420_GPIO_PART3_MAX;
>>> + else
>>> + return EXYNOS5420_GPIO_PART4_MAX;
>>> + } else {
>>> + if (nr < EXYNOS5_GPIO_PART1_MAX)
>>> + return 0;
>>> + else if (nr < EXYNOS5_GPIO_PART2_MAX)
>>> + return EXYNOS5_GPIO_PART1_MAX;
>>> + else
>>> + return EXYNOS5_GPIO_PART2_MAX;
>>> + }
>>> } else if (cpu_is_exynos4()) {
>>> if (proid_is_exynos4412()) {
>>> if (nr < EXYNOS4X12_GPIO_PART1_MAX)
>>> diff --git a/arch/arm/include/asm/arch-exynos/periph.h
>>> b/arch/arm/include/asm/arch-exynos/periph.h
>>> index 64bd8b7..30c7f18 100644
>>> --- a/arch/arm/include/asm/arch-exynos/periph.h
>>> +++ b/arch/arm/include/asm/arch-exynos/periph.h
>>> @@ -34,6 +34,9 @@ enum periph_id {
>>> PERIPH_ID_SDMMC1,
>>> PERIPH_ID_SDMMC2,
>>> PERIPH_ID_SDMMC3,
>>> + PERIPH_ID_I2C8 = 87,
>>> + PERIPH_ID_I2C9,
>>> + PERIPH_ID_I2C10 = 203,
>>> PERIPH_ID_I2S0 = 98,
>>> PERIPH_ID_I2S1 = 99,
>>>
>>> --
>>> 1.7.12.4
>>>
>>> _______________________________________________
>>> U-Boot mailing list
>>> U-Boot at lists.denx.de
>>> http://lists.denx.de/mailman/listinfo/u-boot
>>>
>>
>> Thanks,
>> Minkyu Kang.
>> --
>> from. prom.
>> www.promsoft.net
>>
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
>>
>
>
>
> --
> Regards,
> Rajeshwari Shinde
--
Regards,
Rajeshwari Shinde
^ permalink raw reply [flat|nested] 37+ messages in thread* [U-Boot] [PATCH 05/10 V6] Exynos5420: Add support for 5420 in pinmux and gpio
2013-11-13 6:04 ` Rajeshwari Birje
2013-11-13 6:08 ` Rajeshwari Birje
@ 2013-11-14 2:46 ` Minkyu Kang
1 sibling, 0 replies; 37+ messages in thread
From: Minkyu Kang @ 2013-11-14 2:46 UTC (permalink / raw)
To: u-boot
On 13 November 2013 15:04, Rajeshwari Birje <rajeshwari.birje@gmail.com>wrote:
> Hi Minkyu Kang,
>
> Thank you for comments.
>
> On Wed, Nov 13, 2013 at 8:31 AM, Minkyu Kang <promsoft@gmail.com> wrote:
> > Dear Rajeshwari S Shinde,
> >
> >
> > On 29 October 2013 16:23, Rajeshwari S Shinde <rajeshwari.s@samsung.com
> >wrote:
> >
> >> Adds code in pinmux and gpio framework to support Exynos5420.
> >>
> >> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> >> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
> >> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
> >> Acked-by: Simon Glass <sjg@chromium.org>
> >> ---
> >> Changes in V2:
> >> - None
> >> Changes in V3:
> >> - None
> >> Changes in V4:
> >> - Added correct calculation of gpio based addresses.
> >> Changes in V5:
> >> - None
> >> Changes in V6:
> >> - None
> >> arch/arm/cpu/armv7/exynos/pinmux.c | 241
> >> +++++++++++++++++++++++++++++-
> >> arch/arm/include/asm/arch-exynos/gpio.h | 143 ++++++++++++++++--
> >> arch/arm/include/asm/arch-exynos/periph.h | 3 +
> >> 3 files changed, 372 insertions(+), 15 deletions(-)
> >>
> >> diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
> >> b/arch/arm/cpu/armv7/exynos/pinmux.c
> >> index 8002bce..417ecae 100644
> >> --- a/arch/arm/cpu/armv7/exynos/pinmux.c
> >> +++ b/arch/arm/cpu/armv7/exynos/pinmux.c
> >> @@ -46,6 +46,41 @@ static void exynos5_uart_config(int peripheral)
> >> }
> >> }
> >>
> >> +static void exynos5420_uart_config(int peripheral)
> >> +{
> >> + struct exynos5420_gpio_part1 *gpio1 =
> >> + (struct exynos5420_gpio_part1
> >> *)samsung_get_base_gpio_part1();
> >> + struct s5p_gpio_bank *bank;
> >> + int i, start, count;
> >> +
> >> + switch (peripheral) {
> >> + case PERIPH_ID_UART0:
> >> + bank = &gpio1->a0;
> >> + start = 0;
> >> + count = 4;
> >> + break;
> >> + case PERIPH_ID_UART1:
> >> + bank = &gpio1->a0;
> >> + start = 4;
> >> + count = 4;
> >> + break;
> >> + case PERIPH_ID_UART2:
> >> + bank = &gpio1->a1;
> >> + start = 0;
> >> + count = 4;
> >> + break;
> >> + case PERIPH_ID_UART3:
> >> + bank = &gpio1->a1;
> >> + start = 4;
> >> + count = 2;
> >> + break;
> >
> > + }
> >>
> >
> > please add blank line.
> will correct this
> >
> >
> >> + for (i = start; i < start + count; i++) {
> >> + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
> >> + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
> >> + }
> >> +}
> >> +
> >> static int exynos5_mmc_config(int peripheral, int flags)
> >> {
> >> struct exynos5_gpio_part1 *gpio1 =
> >> @@ -101,6 +136,70 @@ static int exynos5_mmc_config(int peripheral, int
> >> flags)
> >> return 0;
> >> }
> >>
> >> +static int exynos5420_mmc_config(int peripheral, int flags)
> >> +{
> >> + struct exynos5420_gpio_part3 *gpio3 =
> >> + (struct exynos5420_gpio_part3
> >> *)samsung_get_base_gpio_part3();
> >> + struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL;
> >> + int i, start = 0, gpio_func = 0;
> >>
> >
> > I think we don' have to set to 0 to start and gpio_func.
> Will remove gpio_func, but if I dont set start to 0 I get following error:
>
> pinmux.c: In function ?exynos_pinmux_config?:
> pinmux.c:173:20: warning: ?start? may be used uninitialized in this
> function [-Wmaybe-uninitialized]
> pinmux.c:145:9: note: ?start? was declared here
>
because you missing start = 0 at MMC2.
Actually I like to set values explicitly at every conditions instead of
initial value.
It looks more clearly.
Thanks,
Minkyu Kang.
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 37+ messages in thread
* [U-Boot] [PATCH 06/10 V6] Exynos5420: Add base patch for SMDK5420
2013-10-29 7:23 [U-Boot] [PATCH 00/10 V6] EXYNOS5420: Add SMDK5420 board support Rajeshwari S Shinde
` (4 preceding siblings ...)
2013-10-29 7:23 ` [U-Boot] [PATCH 05/10 V6] Exynos5420: Add support for 5420 in pinmux and gpio Rajeshwari S Shinde
@ 2013-10-29 7:23 ` Rajeshwari S Shinde
2013-11-13 3:09 ` Minkyu Kang
2013-10-29 7:23 ` [U-Boot] [PATCH 07/10 V6] DTS: Add dts support " Rajeshwari S Shinde
` (4 subsequent siblings)
10 siblings, 1 reply; 37+ messages in thread
From: Rajeshwari S Shinde @ 2013-10-29 7:23 UTC (permalink / raw)
To: u-boot
Adding the base patch for Exynos based SMDK5420.
This shall enable compilation and basic boot support for
SMDK5420.
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Rebased on latest u-boot-samsung tree.
Changes in V5:
- Removed functions board_eth_init and board_mmc_init
as they were moved to common/board.c
Changes in V6:
- None
board/samsung/common/board.c | 2 +
board/samsung/smdk5420/Makefile | 34 ++++++++
board/samsung/smdk5420/smdk5420.c | 159 ++++++++++++++++++++++++++++++++++
board/samsung/smdk5420/smdk5420_spl.c | 52 +++++++++++
boards.cfg | 1 +
tools/Makefile | 2 +
6 files changed, 250 insertions(+)
create mode 100644 board/samsung/smdk5420/Makefile
create mode 100644 board/samsung/smdk5420/smdk5420.c
create mode 100644 board/samsung/smdk5420/smdk5420_spl.c
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 9ebfc42..2512a59 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -143,6 +143,7 @@ struct cros_ec_dev *board_get_cros_ec_dev(void)
return local.cros_ec_dev;
}
+#ifdef CONFIG_CROS_EC
static int board_init_cros_ec_devices(const void *blob)
{
local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
@@ -151,6 +152,7 @@ static int board_init_cros_ec_devices(const void *blob)
return 0;
}
+#endif
#if defined(CONFIG_POWER)
#ifdef CONFIG_POWER_MAX77686
diff --git a/board/samsung/smdk5420/Makefile b/board/samsung/smdk5420/Makefile
new file mode 100644
index 0000000..be538ec
--- /dev/null
+++ b/board/samsung/smdk5420/Makefile
@@ -0,0 +1,34 @@
+#
+# Copyright (C) 2013 Samsung Electronics
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS += smdk5420_spl.o
+
+ifndef CONFIG_SPL_BUILD
+COBJS += smdk5420.o
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+ALL := $(obj).depend $(LIB)
+
+all: $(ALL)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c
new file mode 100644
index 0000000..d85b953
--- /dev/null
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include <lcd.h>
+#include <spi.h>
+#include <asm/arch/board.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/dp_info.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_USB_EHCI_EXYNOS
+static int board_usb_vbus_init(void)
+{
+ struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
+ samsung_get_base_gpio_part1();
+
+ /* Enable VBUS power switch */
+ s5p_gpio_direction_output(&gpio1->x2, 6, 1);
+
+ /* VBUS turn ON time */
+ mdelay(3);
+
+ return 0;
+}
+#endif
+
+int exynos_init(void)
+{
+#ifdef CONFIG_USB_EHCI_EXYNOS
+ board_usb_vbus_init();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_LCD
+void cfg_lcd_gpio(void)
+{
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
+
+ /* For Backlight */
+ s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
+ s5p_gpio_set_value(&gpio1->b2, 0, 1);
+
+ /* LCD power on */
+ s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
+ s5p_gpio_set_value(&gpio1->x1, 5, 1);
+
+ /* Set Hotplug detect for DP */
+ s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+}
+
+vidinfo_t panel_info = {
+ .vl_freq = 60,
+ .vl_col = 2560,
+ .vl_row = 1600,
+ .vl_width = 2560,
+ .vl_height = 1600,
+ .vl_clkp = CONFIG_SYS_LOW,
+ .vl_hsp = CONFIG_SYS_LOW,
+ .vl_vsp = CONFIG_SYS_LOW,
+ .vl_dp = CONFIG_SYS_LOW,
+ .vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */
+
+ /* wDP panel timing infomation */
+ .vl_hspw = 32,
+ .vl_hbpd = 80,
+ .vl_hfpd = 48,
+
+ .vl_vspw = 6,
+ .vl_vbpd = 37,
+ .vl_vfpd = 3,
+ .vl_cmd_allow_len = 0xf,
+
+ .win_id = 3,
+ .cfg_gpio = cfg_lcd_gpio,
+ .backlight_on = NULL,
+ .lcd_power_on = NULL,
+ .reset_lcd = NULL,
+ .dual_lcd_enabled = 0,
+
+ .init_delay = 0,
+ .power_on_delay = 0,
+ .reset_delay = 0,
+ .interface_mode = FIMD_RGB_INTERFACE,
+ .dp_enabled = 1,
+};
+
+static struct edp_device_info edp_info = {
+ .disp_info = {
+ .h_res = 2560,
+ .h_sync_width = 32,
+ .h_back_porch = 80,
+ .h_front_porch = 48,
+ .v_res = 1600,
+ .v_sync_width = 6,
+ .v_back_porch = 37,
+ .v_front_porch = 3,
+ .v_sync_rate = 60,
+ },
+ .lt_info = {
+ .lt_status = DP_LT_NONE,
+ },
+ .video_info = {
+ .master_mode = 0,
+ .bist_mode = DP_DISABLE,
+ .bist_pattern = NO_PATTERN,
+ .h_sync_polarity = 0,
+ .v_sync_polarity = 0,
+ .interlaced = 0,
+ .color_space = COLOR_RGB,
+ .dynamic_range = VESA,
+ .ycbcr_coeff = COLOR_YCBCR601,
+ .color_depth = COLOR_8,
+ },
+};
+
+static struct exynos_dp_platform_data dp_platform_data = {
+ .phy_enable = set_dp_phy_ctrl,
+ .edp_dev_info = &edp_info,
+};
+
+void init_panel_info(vidinfo_t *vid)
+{
+ vid->rgb_mode = MODE_RGB_P,
+
+ exynos_set_dp_platform_data(&dp_platform_data);
+}
+#endif
+
+int board_get_revision(void)
+{
+ return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ const char *board_name;
+
+ board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
+ if (board_name == NULL)
+ printf("\nUnknown Board\n");
+ else
+ printf("\nBoard: %s\n", board_name);
+
+ return 0;
+}
+#endif
diff --git a/board/samsung/smdk5420/smdk5420_spl.c b/board/samsung/smdk5420/smdk5420_spl.c
new file mode 100644
index 0000000..73359f7
--- /dev/null
+++ b/board/samsung/smdk5420/smdk5420_spl.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2013 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/spl.h>
+#include <asm/arch/clk.h>
+
+#define SIGNATURE 0xdeadbeef
+
+/* Parameters of early board initialization in SPL */
+static struct spl_machine_param machine_param
+ __attribute__((section(".machine_param"))) = {
+ .signature = SIGNATURE,
+ .version = 1,
+ .params = "vmubfasirM",
+ .size = sizeof(machine_param),
+
+ .mem_iv_size = 0x1f,
+ .mem_type = DDR_MODE_DDR3,
+
+ /*
+ * Set uboot_size to 0x100000 bytes.
+ *
+ * This is an overly conservative value chosen to accommodate all
+ * possible U-Boot image. You are advised to set this value to a
+ * smaller realistic size via scripts that modifies the .machine_param
+ * section of output U-Boot image.
+ */
+ .uboot_size = 0x100000,
+
+ .boot_source = BOOT_MODE_OM,
+ .frequency_mhz = 800,
+ .arm_freq_mhz = 900,
+ .serial_base = 0x12c30000,
+ .i2c_base = 0x12c60000,
+ .mem_manuf = MEM_MANUF_SAMSUNG,
+};
+
+struct spl_machine_param *spl_get_machine_params(void)
+{
+ if (machine_param.signature != SIGNATURE) {
+ /* Will hang if SIGNATURE dont match */
+ while (1)
+ ;
+ }
+
+ return &machine_param;
+}
diff --git a/boards.cfg b/boards.cfg
index aa2ee64..e476ebc 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -272,6 +272,7 @@ Active arm armv7 exynos samsung arndale
Active arm armv7 exynos samsung origen origen - Chander Kashyap <k.chander@samsung.com>
Active arm armv7 exynos samsung smdk5250 smdk5250 - Chander Kashyap <k.chander@samsung.com>
Active arm armv7 exynos samsung smdk5250 snow - Rajeshwari Shinde <rajeshwari.s@samsung.com>
+Active arm armv7 exynos samsung smdk5420 smdk5420 - Rajeshwari Shinde <rajeshwari.s@samsung.com>
Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap <k.chander@samsung.com>
Active arm armv7 exynos samsung trats trats - Lukasz Majewski <l.majewski@samsung.com>
Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek <p.wilczek@samsung.com>
diff --git a/tools/Makefile b/tools/Makefile
index ca76f94..fcff6be 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -53,6 +53,7 @@ BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX)
BIN_FILES-y += mkenvimage$(SFX)
BIN_FILES-y += mkimage$(SFX)
BIN_FILES-$(CONFIG_EXYNOS5250) += mk$(BOARD)spl$(SFX)
+BIN_FILES-$(CONFIG_EXYNOS5420) += mk$(BOARD)spl$(SFX)
BIN_FILES-$(CONFIG_MX23) += mxsboot$(SFX)
BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
@@ -88,6 +89,7 @@ OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o
OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o
OBJ_FILES-$(CONFIG_EXYNOS5250) += mkexynosspl.o
+OBJ_FILES-$(CONFIG_EXYNOS5420) += mkexynosspl.o
OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o
OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o
OBJ_FILES-$(CONFIG_MX23) += mxsboot.o
--
1.7.12.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [U-Boot] [PATCH 06/10 V6] Exynos5420: Add base patch for SMDK5420
2013-10-29 7:23 ` [U-Boot] [PATCH 06/10 V6] Exynos5420: Add base patch for SMDK5420 Rajeshwari S Shinde
@ 2013-11-13 3:09 ` Minkyu Kang
0 siblings, 0 replies; 37+ messages in thread
From: Minkyu Kang @ 2013-11-13 3:09 UTC (permalink / raw)
To: u-boot
Dear Rajeshwari S Shinde,
On 29 October 2013 16:23, Rajeshwari S Shinde <rajeshwari.s@samsung.com>wrote:
> Adding the base patch for Exynos based SMDK5420.
> This shall enable compilation and basic boot support for
> SMDK5420.
>
> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
> Changes in V2:
> - None
> Changes in V3:
> - None
> Changes in V4:
> - Rebased on latest u-boot-samsung tree.
> Changes in V5:
> - Removed functions board_eth_init and board_mmc_init
> as they were moved to common/board.c
> Changes in V6:
> - None
> board/samsung/common/board.c | 2 +
> board/samsung/smdk5420/Makefile | 34 ++++++++
> board/samsung/smdk5420/smdk5420.c | 159
> ++++++++++++++++++++++++++++++++++
> board/samsung/smdk5420/smdk5420_spl.c | 52 +++++++++++
> boards.cfg | 1 +
> tools/Makefile | 2 +
> 6 files changed, 250 insertions(+)
> create mode 100644 board/samsung/smdk5420/Makefile
> create mode 100644 board/samsung/smdk5420/smdk5420.c
> create mode 100644 board/samsung/smdk5420/smdk5420_spl.c
>
> diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
> index 9ebfc42..2512a59 100644
> --- a/board/samsung/common/board.c
> +++ b/board/samsung/common/board.c
> @@ -143,6 +143,7 @@ struct cros_ec_dev *board_get_cros_ec_dev(void)
> return local.cros_ec_dev;
> }
>
> +#ifdef CONFIG_CROS_EC
> static int board_init_cros_ec_devices(const void *blob)
> {
> local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
> @@ -151,6 +152,7 @@ static int board_init_cros_ec_devices(const void *blob)
>
> return 0;
> }
> +#endif
>
> #if defined(CONFIG_POWER)
> #ifdef CONFIG_POWER_MAX77686
> diff --git a/board/samsung/smdk5420/Makefile
> b/board/samsung/smdk5420/Makefile
> new file mode 100644
> index 0000000..be538ec
> --- /dev/null
> +++ b/board/samsung/smdk5420/Makefile
> @@ -0,0 +1,34 @@
> +#
> +# Copyright (C) 2013 Samsung Electronics
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(BOARD).o
> +
> +COBJS += smdk5420_spl.o
> +
> +ifndef CONFIG_SPL_BUILD
> +COBJS += smdk5420.o
> +endif
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
> +
> +ALL := $(obj).depend $(LIB)
> +
> +all: $(ALL)
> +
> +$(LIB): $(OBJS)
> + $(call cmd_link_o_target, $(OBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/samsung/smdk5420/smdk5420.c
> b/board/samsung/smdk5420/smdk5420.c
> new file mode 100644
> index 0000000..d85b953
> --- /dev/null
> +++ b/board/samsung/smdk5420/smdk5420.c
> @@ -0,0 +1,159 @@
> +/*
> + * Copyright (C) 2013 Samsung Electronics
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <fdtdec.h>
> +#include <asm/io.h>
> +#include <i2c.h>
> +#include <lcd.h>
> +#include <spi.h>
> +#include <asm/arch/board.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/arch/pinmux.h>
> +#include <asm/arch/dp_info.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#ifdef CONFIG_USB_EHCI_EXYNOS
> +static int board_usb_vbus_init(void)
> +{
> + struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
> +
> samsung_get_base_gpio_part1();
> +
> + /* Enable VBUS power switch */
> + s5p_gpio_direction_output(&gpio1->x2, 6, 1);
> +
> + /* VBUS turn ON time */
> + mdelay(3);
> +
> + return 0;
> +}
> +#endif
> +
> +int exynos_init(void)
> +{
> +#ifdef CONFIG_USB_EHCI_EXYNOS
> + board_usb_vbus_init();
> +#endif
> + return 0;
> +}
> +
> +#ifdef CONFIG_LCD
> +void cfg_lcd_gpio(void)
> +{
> + struct exynos5_gpio_part1 *gpio1 =
> + (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
> +
> + /* For Backlight */
> + s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
> + s5p_gpio_set_value(&gpio1->b2, 0, 1);
> +
> + /* LCD power on */
> + s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
> + s5p_gpio_set_value(&gpio1->x1, 5, 1);
> +
> + /* Set Hotplug detect for DP */
> + s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
> +}
> +
> +vidinfo_t panel_info = {
> + .vl_freq = 60,
> + .vl_col = 2560,
> + .vl_row = 1600,
> + .vl_width = 2560,
> + .vl_height = 1600,
> + .vl_clkp = CONFIG_SYS_LOW,
> + .vl_hsp = CONFIG_SYS_LOW,
> + .vl_vsp = CONFIG_SYS_LOW,
> + .vl_dp = CONFIG_SYS_LOW,
> + .vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on
> LCD */
> +
> + /* wDP panel timing infomation */
> + .vl_hspw = 32,
> + .vl_hbpd = 80,
> + .vl_hfpd = 48,
> +
> + .vl_vspw = 6,
> + .vl_vbpd = 37,
> + .vl_vfpd = 3,
> + .vl_cmd_allow_len = 0xf,
> +
> + .win_id = 3,
> + .cfg_gpio = cfg_lcd_gpio,
> + .backlight_on = NULL,
> + .lcd_power_on = NULL,
> + .reset_lcd = NULL,
> + .dual_lcd_enabled = 0,
> +
> + .init_delay = 0,
> + .power_on_delay = 0,
> + .reset_delay = 0,
> + .interface_mode = FIMD_RGB_INTERFACE,
> + .dp_enabled = 1,
> +};
> +
> +static struct edp_device_info edp_info = {
> + .disp_info = {
> + .h_res = 2560,
> + .h_sync_width = 32,
> + .h_back_porch = 80,
> + .h_front_porch = 48,
> + .v_res = 1600,
> + .v_sync_width = 6,
> + .v_back_porch = 37,
> + .v_front_porch = 3,
> + .v_sync_rate = 60,
> + },
> + .lt_info = {
> + .lt_status = DP_LT_NONE,
> + },
> + .video_info = {
> + .master_mode = 0,
> + .bist_mode = DP_DISABLE,
> + .bist_pattern = NO_PATTERN,
> + .h_sync_polarity = 0,
> + .v_sync_polarity = 0,
> + .interlaced = 0,
> + .color_space = COLOR_RGB,
> + .dynamic_range = VESA,
> + .ycbcr_coeff = COLOR_YCBCR601,
> + .color_depth = COLOR_8,
> + },
> +};
> +
> +static struct exynos_dp_platform_data dp_platform_data = {
> + .phy_enable = set_dp_phy_ctrl,
> + .edp_dev_info = &edp_info,
> +};
> +
> +void init_panel_info(vidinfo_t *vid)
> +{
> + vid->rgb_mode = MODE_RGB_P,
> +
> + exynos_set_dp_platform_data(&dp_platform_data);
> +}
> +#endif
> +
> +int board_get_revision(void)
> +{
> + return 0;
> +}
> +
> +#ifdef CONFIG_DISPLAY_BOARDINFO
> +int checkboard(void)
> +{
> + const char *board_name;
> +
> + board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
> + if (board_name == NULL)
> + printf("\nUnknown Board\n");
> + else
> + printf("\nBoard: %s\n", board_name);
> +
> + return 0;
> +}
> +#endif
> diff --git a/board/samsung/smdk5420/smdk5420_spl.c
> b/board/samsung/smdk5420/smdk5420_spl.c
> new file mode 100644
> index 0000000..73359f7
> --- /dev/null
> +++ b/board/samsung/smdk5420/smdk5420_spl.c
> @@ -0,0 +1,52 @@
> +/*
> + * Copyright (C) 2013 The Chromium OS Authors.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/spl.h>
> +#include <asm/arch/clk.h>
> +
> +#define SIGNATURE 0xdeadbeef
> +
> +/* Parameters of early board initialization in SPL */
> +static struct spl_machine_param machine_param
> + __attribute__((section(".machine_param"))) = {
> + .signature = SIGNATURE,
> + .version = 1,
> + .params = "vmubfasirM",
> + .size = sizeof(machine_param),
> +
> + .mem_iv_size = 0x1f,
> + .mem_type = DDR_MODE_DDR3,
> +
> + /*
> + * Set uboot_size to 0x100000 bytes.
> + *
> + * This is an overly conservative value chosen to accommodate all
> + * possible U-Boot image. You are advised to set this value to a
> + * smaller realistic size via scripts that modifies the
> .machine_param
> + * section of output U-Boot image.
> + */
> + .uboot_size = 0x100000,
> +
> + .boot_source = BOOT_MODE_OM,
> + .frequency_mhz = 800,
> + .arm_freq_mhz = 900,
> + .serial_base = 0x12c30000,
> + .i2c_base = 0x12c60000,
> + .mem_manuf = MEM_MANUF_SAMSUNG,
> +};
> +
> +struct spl_machine_param *spl_get_machine_params(void)
> +{
> + if (machine_param.signature != SIGNATURE) {
> + /* Will hang if SIGNATURE dont match */
> + while (1)
> + ;
> + }
> +
> + return &machine_param;
> +}
> diff --git a/boards.cfg b/boards.cfg
> index aa2ee64..e476ebc 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -272,6 +272,7 @@ Active arm armv7 exynos samsung
> arndale
> Active arm armv7 exynos samsung origen
> origen -
>
> Chander Kashyap <k.chander@samsung.com>
> Active arm armv7 exynos samsung smdk5250
> smdk5250 -
>
> Chander Kashyap <k.chander@samsung.com>
> Active arm armv7 exynos samsung smdk5250
> snow -
>
> Rajeshwari Shinde <rajeshwari.s@samsung.com>
> +Active arm armv7 exynos samsung smdk5420
> smdk5420 -
>
> Rajeshwari Shinde <rajeshwari.s@samsung.com>
> Active arm armv7 exynos samsung smdkv310
> smdkv310 -
>
> Chander Kashyap <k.chander@samsung.com>
> Active arm armv7 exynos samsung trats
> trats -
>
> Lukasz Majewski <l.majewski@samsung.com>
> Active arm armv7 exynos samsung trats2
> trats2 -
>
> Piotr Wilczek <p.wilczek@samsung.com>
> diff --git a/tools/Makefile b/tools/Makefile
> index ca76f94..fcff6be 100644
> --- a/tools/Makefile
> +++ b/tools/Makefile
> @@ -53,6 +53,7 @@ BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) +=
> xway-swap-bytes$(SFX)
> BIN_FILES-y += mkenvimage$(SFX)
> BIN_FILES-y += mkimage$(SFX)
> BIN_FILES-$(CONFIG_EXYNOS5250) += mk$(BOARD)spl$(SFX)
> +BIN_FILES-$(CONFIG_EXYNOS5420) += mk$(BOARD)spl$(SFX)
> BIN_FILES-$(CONFIG_MX23) += mxsboot$(SFX)
> BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
> BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
> @@ -88,6 +89,7 @@ OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o
> OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
> OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o
> OBJ_FILES-$(CONFIG_EXYNOS5250) += mkexynosspl.o
> +OBJ_FILES-$(CONFIG_EXYNOS5420) += mkexynosspl.o
>
How about use same configuration for making mkexynosspl?
e.g) CONFIG_EXYNOS_SPL?
> OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o
> OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o
> OBJ_FILES-$(CONFIG_MX23) += mxsboot.o
> --
> 1.7.12.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
Thanks,
Minkyu Kang.
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 37+ messages in thread
* [U-Boot] [PATCH 07/10 V6] DTS: Add dts support for SMDK5420
2013-10-29 7:23 [U-Boot] [PATCH 00/10 V6] EXYNOS5420: Add SMDK5420 board support Rajeshwari S Shinde
` (5 preceding siblings ...)
2013-10-29 7:23 ` [U-Boot] [PATCH 06/10 V6] Exynos5420: Add base patch for SMDK5420 Rajeshwari S Shinde
@ 2013-10-29 7:23 ` Rajeshwari S Shinde
2013-11-13 3:17 ` Minkyu Kang
2013-10-29 7:23 ` [U-Boot] [PATCH 08/10 V6] Config: Add initial config " Rajeshwari S Shinde
` (3 subsequent siblings)
10 siblings, 1 reply; 37+ messages in thread
From: Rajeshwari S Shinde @ 2013-10-29 7:23 UTC (permalink / raw)
To: u-boot
This patch adds support for SMDK5420.
exynos5.dtsi created is a common file which has the nodes common
to both 5420 and 5250.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Added /include/ "exynos5420.dtsi
Changes in V5:
- None
Changes in V6:
- None
arch/arm/dts/exynos5.dtsi | 211 ++++++++++++++++++++++++++++++
arch/arm/dts/exynos5250.dtsi | 178 +------------------------
arch/arm/dts/exynos5420.dtsi | 74 +++++++++++
board/samsung/dts/exynos5420-smdk5420.dts | 172 ++++++++++++++++++++++++
4 files changed, 458 insertions(+), 177 deletions(-)
create mode 100644 arch/arm/dts/exynos5.dtsi
create mode 100644 arch/arm/dts/exynos5420.dtsi
create mode 100644 board/samsung/dts/exynos5420-smdk5420.dts
diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi
new file mode 100644
index 0000000..de86a06
--- /dev/null
+++ b/arch/arm/dts/exynos5.dtsi
@@ -0,0 +1,211 @@
+/*
+ * SAMSUNG EXYNOS5 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5 SoC device nodes are listed in this file.
+ * EXYNOS5 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * EXYNOS5 SoC. As device tree coverage for EXYNOS5 increases,
+ * additional nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "samsung,exynos5";
+
+ sromc at 12250000 {
+ compatible = "samsung,exynos-sromc";
+ reg = <0x12250000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c at 12c60000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x12C60000 0x100>;
+ interrupts = <0 56 0>;
+ };
+
+ i2c at 12c70000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x12C70000 0x100>;
+ interrupts = <0 57 0>;
+ };
+
+ i2c at 12c80000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x12C80000 0x100>;
+ interrupts = <0 58 0>;
+ };
+
+ i2c at 12c90000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x12C90000 0x100>;
+ interrupts = <0 59 0>;
+ };
+
+ spi at 12d20000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-spi";
+ reg = <0x12d20000 0x30>;
+ interrupts = <0 68 0>;
+ };
+
+ spi at 12d30000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-spi";
+ reg = <0x12d30000 0x30>;
+ interrupts = <0 69 0>;
+ };
+
+ spi at 12d40000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-spi";
+ reg = <0x12d40000 0x30>;
+ clock-frequency = <50000000>;
+ interrupts = <0 70 0>;
+ };
+
+ spi at 131a0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-spi";
+ reg = <0x131a0000 0x30>;
+ interrupts = <0 129 0>;
+ };
+
+ spi at 131b0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-spi";
+ reg = <0x131b0000 0x30>;
+ interrupts = <0 130 0>;
+ };
+
+ ehci at 12110000 {
+ compatible = "samsung,exynos-ehci";
+ reg = <0x12110000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ phy {
+ compatible = "samsung,exynos-usb-phy";
+ reg = <0x12130000 0x100>;
+ };
+ };
+
+ tmu at 10060000 {
+ compatible = "samsung,exynos-tmu";
+ reg = <0x10060000 0x10000>;
+ };
+
+ fimd at 14400000 {
+ compatible = "samsung,exynos-fimd";
+ reg = <0x14400000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ dp at 145b0000 {
+ compatible = "samsung,exynos5-dp";
+ reg = <0x145b0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ xhci0: xhci at 12000000 {
+ compatible = "samsung,exynos5250-xhci";
+ reg = <0x12000000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ phy {
+ compatible = "samsung,exynos5250-usb3-phy";
+ reg = <0x12100000 0x100>;
+ };
+ };
+
+
+ mmc at 12200000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos5250-dwmmc";
+ reg = <0x12200000 0x1000>;
+ interrupts = <0 75 0>;
+ };
+
+ mmc at 12210000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos5250-dwmmc";
+ reg = <0x12210000 0x1000>;
+ interrupts = <0 76 0>;
+ };
+
+ mmc at 12220000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos5250-dwmmc";
+ reg = <0x12220000 0x1000>;
+ interrupts = <0 77 0>;
+ };
+
+ mmc at 12230000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos5250-dwmmc";
+ reg = <0x12230000 0x1000>;
+ interrupts = <0 78 0>;
+ };
+
+ serial at 12C00000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C00000 0x100>;
+ interrupts = <0 51 0>;
+ id = <0>;
+ };
+
+ serial at 12C10000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C10000 0x100>;
+ interrupts = <0 52 0>;
+ id = <1>;
+ };
+
+ serial at 12C20000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C20000 0x100>;
+ interrupts = <0 53 0>;
+ id = <2>;
+ };
+
+ serial at 12C30000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C30000 0x100>;
+ interrupts = <0 54 0>;
+ id = <3>;
+ };
+
+ gpio: gpio {
+ };
+};
diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi
index 44cbb5a..4533481 100644
--- a/arch/arm/dts/exynos5250.dtsi
+++ b/arch/arm/dts/exynos5250.dtsi
@@ -17,50 +17,9 @@
* published by the Free Software Foundation.
*/
-/include/ "skeleton.dtsi"
+/include/ "exynos5.dtsi"
/ {
- compatible = "samsung,exynos5250";
-
- sromc at 12250000 {
- compatible = "samsung,exynos-sromc";
- reg = <0x12250000 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c at 12c60000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x12C60000 0x100>;
- interrupts = <0 56 0>;
- };
-
- i2c at 12c70000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x12C70000 0x100>;
- interrupts = <0 57 0>;
- };
-
- i2c at 12c80000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x12C80000 0x100>;
- interrupts = <0 58 0>;
- };
-
- i2c at 12c90000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x12C90000 0x100>;
- interrupts = <0 59 0>;
- };
-
i2c at 12ca0000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -116,139 +75,4 @@
samsung,i2s-bit-clk-framesize = <32>;
samsung,i2s-id = <1>;
};
-
- spi at 12d20000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,exynos-spi";
- reg = <0x12d20000 0x30>;
- interrupts = <0 68 0>;
- };
-
- spi at 12d30000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,exynos-spi";
- reg = <0x12d30000 0x30>;
- interrupts = <0 69 0>;
- };
-
- spi at 12d40000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,exynos-spi";
- reg = <0x12d40000 0x30>;
- clock-frequency = <50000000>;
- interrupts = <0 70 0>;
- };
-
- spi at 131a0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,exynos-spi";
- reg = <0x131a0000 0x30>;
- interrupts = <0 129 0>;
- };
-
- spi at 131b0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,exynos-spi";
- reg = <0x131b0000 0x30>;
- interrupts = <0 130 0>;
- };
-
- ehci at 12110000 {
- compatible = "samsung,exynos-ehci";
- reg = <0x12110000 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- phy {
- compatible = "samsung,exynos-usb-phy";
- reg = <0x12130000 0x100>;
- };
- };
-
- tmu at 10060000 {
- compatible = "samsung,exynos-tmu";
- reg = <0x10060000 0x10000>;
- };
-
- fimd at 14400000 {
- compatible = "samsung,exynos-fimd";
- reg = <0x14400000 0x10000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- dp at 145b0000 {
- compatible = "samsung,exynos5-dp";
- reg = <0x145b0000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- mmc at 12200000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,exynos5250-dwmmc";
- reg = <0x12200000 0x1000>;
- interrupts = <0 75 0>;
- };
-
- mmc at 12210000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,exynos5250-dwmmc";
- reg = <0x12210000 0x1000>;
- interrupts = <0 76 0>;
- };
-
- mmc at 12220000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,exynos5250-dwmmc";
- reg = <0x12220000 0x1000>;
- interrupts = <0 77 0>;
- };
-
- mmc at 12230000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,exynos5250-dwmmc";
- reg = <0x12230000 0x1000>;
- interrupts = <0 78 0>;
- };
-
- serial at 12C00000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C00000 0x100>;
- interrupts = <0 51 0>;
- id = <0>;
- };
-
- serial at 12C10000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C10000 0x100>;
- interrupts = <0 52 0>;
- id = <1>;
- };
-
- serial at 12C20000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C20000 0x100>;
- interrupts = <0 53 0>;
- id = <2>;
- };
-
- serial at 12C30000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C30000 0x100>;
- interrupts = <0 54 0>;
- id = <3>;
- };
-
- gpio: gpio {
- };
};
diff --git a/arch/arm/dts/exynos5420.dtsi b/arch/arm/dts/exynos5420.dtsi
new file mode 100644
index 0000000..ca6c605
--- /dev/null
+++ b/arch/arm/dts/exynos5420.dtsi
@@ -0,0 +1,74 @@
+/*
+ * SAMSUNG Peach board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/include/ "exynos5.dtsi"
+
+/ {
+ config {
+ machine-arch-id = <4151>;
+ };
+
+ i2c at 12ca0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos5-hsi2c";
+ reg = <0x12CA0000 0x100>;
+ interrupts = <0 60 0>;
+ };
+
+ i2c at 12cb0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos5-hsi2c";
+ reg = <0x12CB0000 0x100>;
+ interrupts = <0 61 0>;
+ };
+
+ i2c at 12cc0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos5-hsi2c";
+ reg = <0x12CC0000 0x100>;
+ interrupts = <0 62 0>;
+ };
+
+ i2c at 12cd0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos5-hsi2c";
+ reg = <0x12CD0000 0x100>;
+ interrupts = <0 63 0>;
+ };
+
+ i2c at 12e00000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos5-hsi2c";
+ reg = <0x12E00000 0x100>;
+ interrupts = <0 87 0>;
+ };
+
+ i2c at 12e10000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos5-hsi2c";
+ reg = <0x12E10000 0x100>;
+ interrupts = <0 88 0>;
+ };
+
+ i2c at 12e20000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos5-hsi2c";
+ reg = <0x12E20000 0x100>;
+ interrupts = <0 203 0>;
+ };
+};
diff --git a/board/samsung/dts/exynos5420-smdk5420.dts b/board/samsung/dts/exynos5420-smdk5420.dts
new file mode 100644
index 0000000..5ef0c92
--- /dev/null
+++ b/board/samsung/dts/exynos5420-smdk5420.dts
@@ -0,0 +1,172 @@
+/*
+ * SAMSUNG SMDK5420 board device tree source
+ *
+ * Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+/include/ "exynos5420.dtsi"
+
+/ {
+ model = "SAMSUNG SMDK5420 board based on EXYNOS5420";
+ compatible = "samsung,smdk5420", "samsung,exynos5";
+
+ config {
+ hwid = "smdk5420 TEST A-A 9382";
+ };
+
+ aliases {
+ i2c0 = "/i2c at 12c60000";
+ i2c1 = "/i2c at 12c70000";
+ i2c2 = "/i2c at 12c80000";
+ i2c3 = "/i2c at 12c90000";
+ i2c4 = "/i2c at 12ca0000";
+ i2c5 = "/i2c at 12cb0000";
+ i2c6 = "/i2c at 12cc0000";
+ i2c7 = "/i2c at 12cd0000";
+ i2c8 = "/i2c at 12e00000";
+ i2c9 = "/i2c at 12e10000";
+ i2c10 = "/i2c at 12e20000";
+ spi0 = "/spi at 12d20000";
+ spi1 = "/spi at 12d30000";
+ spi2 = "/spi at 12d40000";
+ spi3 = "/spi at 131a0000";
+ spi4 = "/spi at 131b0000";
+ mmc0 = "/mmc at 12200000";
+ mmc1 = "/mmc at 12210000";
+ mmc2 = "/mmc at 12220000";
+ xhci0 = "/xhci at 12000000";
+ xhci1 = "/xhci at 12400000";
+ serial0 = "/serial at 12C30000";
+ console = "/serial at 12C30000";
+ };
+
+ tmu at 10060000 {
+ samsung,min-temp = <25>;
+ samsung,max-temp = <125>;
+ samsung,start-warning = <95>;
+ samsung,start-tripping = <105>;
+ samsung,hw-tripping = <110>;
+ samsung,efuse-min-value = <40>;
+ samsung,efuse-value = <55>;
+ samsung,efuse-max-value = <100>;
+ samsung,slope = <274761730>;
+ samsung,dc-value = <25>;
+ };
+
+ /* s2mps11 is on i2c bus 4 */
+ i2c at 12ca0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pmic at 66 {
+ reg = <0x66>;
+ compatible = "samsung,s2mps11-pmic";
+ };
+ };
+
+ spi at 12d20000 { /* spi0 */
+ spi-max-frequency = <50000000>;
+ firmware_storage_spi: flash at 0 {
+ reg = <0>;
+ };
+ };
+
+ fimd at 14400000 {
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <2560>;
+ samsung,vl-row = <1600>;
+ samsung,vl-width = <2560>;
+ samsung,vl-height = <1600>;
+
+ samsung,vl-clkp;
+ samsung,vl-dp;
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <32>;
+ samsung,vl-hbpd = <80>;
+ samsung,vl-hfpd = <48>;
+ samsung,vl-vspw = <6>;
+ samsung,vl-vbpd = <37>;
+ samsung,vl-vfpd = <3>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,winid = <3>;
+ samsung,interface-mode = <1>;
+ samsung,dp-enabled = <1>;
+ samsung,dual-lcd-enabled = <0>;
+ };
+
+ dmc {
+ mem-type = "lpddr3";
+ };
+
+ sound at 3830000 {
+ samsung,codec-type = "wm8994";
+ };
+
+ i2c at 12c70000 {
+ soundcodec at 1a {
+ reg = <0x1a>;
+ compatible = "wolfson,wm8994-codec";
+ };
+ };
+
+ mmc at 12200000 {
+ samsung,bus-width = <8>;
+ samsung,timing = <1 3 3>;
+ samsung,removable = <0>;
+ samsung,pre-init;
+ };
+
+ mmc at 12210000 {
+ status = "disabled";
+ };
+
+ mmc at 12220000 {
+ samsung,bus-width = <4>;
+ samsung,timing = <1 2 3>;
+ samsung,removable = <1>;
+ };
+
+ mmc at 12230000 {
+ status = "disabled";
+ };
+
+ fimd at 14400000 {
+ /* sysmmu is not used in U-Boot */
+ samsung,disable-sysmmu;
+ };
+
+ dp at 145b0000 {
+ samsung,lt-status = <0>;
+
+ samsung,master-mode = <0>;
+ samsung,bist-mode = <0>;
+ samsung,bist-pattern = <0>;
+ samsung,h-sync-polarity = <0>;
+ samsung,v-sync-polarity = <0>;
+ samsung,interlaced = <0>;
+ samsung,color-space = <0>;
+ samsung,dynamic-range = <0>;
+ samsung,ycbcr-coeff = <0>;
+ samsung,color-depth = <1>;
+ };
+
+ dmc {
+ mem-type = "ddr3";
+ };
+
+ xhci1: xhci at 12400000 {
+ compatible = "samsung,exynos5250-xhci";
+ reg = <0x12400000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ phy {
+ compatible = "samsung,exynos5250-usb3-phy";
+ reg = <0x12500000 0x100>;
+ };
+ };
+};
--
1.7.12.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [U-Boot] [PATCH 07/10 V6] DTS: Add dts support for SMDK5420
2013-10-29 7:23 ` [U-Boot] [PATCH 07/10 V6] DTS: Add dts support " Rajeshwari S Shinde
@ 2013-11-13 3:17 ` Minkyu Kang
2013-11-13 4:26 ` Rajeshwari Birje
0 siblings, 1 reply; 37+ messages in thread
From: Minkyu Kang @ 2013-11-13 3:17 UTC (permalink / raw)
To: u-boot
Dear Rajeshwari S Shinde,
On 29 October 2013 16:23, Rajeshwari S Shinde <rajeshwari.s@samsung.com>wrote:
> This patch adds support for SMDK5420.
> exynos5.dtsi created is a common file which has the nodes common
> to both 5420 and 5250.
>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
> Changes in V2:
> - None
> Changes in V3:
> - None
> Changes in V4:
> - Added /include/ "exynos5420.dtsi
> Changes in V5:
> - None
> Changes in V6:
> - None
> arch/arm/dts/exynos5.dtsi | 211
> ++++++++++++++++++++++++++++++
> arch/arm/dts/exynos5250.dtsi | 178 +------------------------
> arch/arm/dts/exynos5420.dtsi | 74 +++++++++++
> board/samsung/dts/exynos5420-smdk5420.dts | 172 ++++++++++++++++++++++++
> 4 files changed, 458 insertions(+), 177 deletions(-)
> create mode 100644 arch/arm/dts/exynos5.dtsi
> create mode 100644 arch/arm/dts/exynos5420.dtsi
> create mode 100644 board/samsung/dts/exynos5420-smdk5420.dts
>
> diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi
> new file mode 100644
> index 0000000..de86a06
> --- /dev/null
> +++ b/arch/arm/dts/exynos5.dtsi
> @@ -0,0 +1,211 @@
> +/*
> + * SAMSUNG EXYNOS5 SoC device tree source
> + *
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * SAMSUNG EXYNOS5 SoC device nodes are listed in this file.
> + * EXYNOS5 based board files can include this file and provide
> + * values for board specfic bindings.
> + *
> + * Note: This file does not include device nodes for all the controllers
> in
> + * EXYNOS5 SoC. As device tree coverage for EXYNOS5 increases,
> + * additional nodes can be added to this file.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
>
please fix the license.
> +*/
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> + compatible = "samsung,exynos5";
> +
> + sromc at 12250000 {
> + compatible = "samsung,exynos-sromc";
> + reg = <0x12250000 0x20>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c at 12c60000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,s3c2440-i2c";
> + reg = <0x12C60000 0x100>;
> + interrupts = <0 56 0>;
> + };
> +
> + i2c at 12c70000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,s3c2440-i2c";
> + reg = <0x12C70000 0x100>;
> + interrupts = <0 57 0>;
> + };
> +
> + i2c at 12c80000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,s3c2440-i2c";
> + reg = <0x12C80000 0x100>;
> + interrupts = <0 58 0>;
> + };
> +
> + i2c at 12c90000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,s3c2440-i2c";
> + reg = <0x12C90000 0x100>;
> + interrupts = <0 59 0>;
> + };
> +
> + spi at 12d20000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,exynos-spi";
> + reg = <0x12d20000 0x30>;
> + interrupts = <0 68 0>;
> + };
> +
> + spi at 12d30000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,exynos-spi";
> + reg = <0x12d30000 0x30>;
> + interrupts = <0 69 0>;
> + };
> +
> + spi at 12d40000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,exynos-spi";
> + reg = <0x12d40000 0x30>;
> + clock-frequency = <50000000>;
> + interrupts = <0 70 0>;
> + };
> +
> + spi at 131a0000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,exynos-spi";
> + reg = <0x131a0000 0x30>;
> + interrupts = <0 129 0>;
> + };
> +
> + spi at 131b0000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,exynos-spi";
> + reg = <0x131b0000 0x30>;
> + interrupts = <0 130 0>;
> + };
> +
> + ehci at 12110000 {
> + compatible = "samsung,exynos-ehci";
> + reg = <0x12110000 0x100>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + phy {
> + compatible = "samsung,exynos-usb-phy";
> + reg = <0x12130000 0x100>;
> + };
> + };
> +
> + tmu at 10060000 {
> + compatible = "samsung,exynos-tmu";
> + reg = <0x10060000 0x10000>;
> + };
> +
> + fimd at 14400000 {
> + compatible = "samsung,exynos-fimd";
> + reg = <0x14400000 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> +
> + dp at 145b0000 {
> + compatible = "samsung,exynos5-dp";
> + reg = <0x145b0000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> +
> + xhci0: xhci at 12000000 {
> + compatible = "samsung,exynos5250-xhci";
> + reg = <0x12000000 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + phy {
> + compatible = "samsung,exynos5250-usb3-phy";
> + reg = <0x12100000 0x100>;
> + };
> + };
> +
>
please remove blank line.
> +
> + mmc at 12200000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,exynos5250-dwmmc";
> + reg = <0x12200000 0x1000>;
> + interrupts = <0 75 0>;
> + };
> +
> + mmc at 12210000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,exynos5250-dwmmc";
> + reg = <0x12210000 0x1000>;
> + interrupts = <0 76 0>;
> + };
> +
> + mmc at 12220000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,exynos5250-dwmmc";
> + reg = <0x12220000 0x1000>;
> + interrupts = <0 77 0>;
> + };
> +
> + mmc at 12230000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,exynos5250-dwmmc";
> + reg = <0x12230000 0x1000>;
> + interrupts = <0 78 0>;
> + };
> +
> + serial at 12C00000 {
> + compatible = "samsung,exynos4210-uart";
> + reg = <0x12C00000 0x100>;
> + interrupts = <0 51 0>;
> + id = <0>;
> + };
> +
> + serial at 12C10000 {
> + compatible = "samsung,exynos4210-uart";
> + reg = <0x12C10000 0x100>;
> + interrupts = <0 52 0>;
> + id = <1>;
> + };
> +
> + serial at 12C20000 {
> + compatible = "samsung,exynos4210-uart";
> + reg = <0x12C20000 0x100>;
> + interrupts = <0 53 0>;
> + id = <2>;
> + };
> +
> + serial at 12C30000 {
> + compatible = "samsung,exynos4210-uart";
> + reg = <0x12C30000 0x100>;
> + interrupts = <0 54 0>;
> + id = <3>;
> + };
> +
> + gpio: gpio {
> + };
> +};
> diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi
> index 44cbb5a..4533481 100644
> --- a/arch/arm/dts/exynos5250.dtsi
> +++ b/arch/arm/dts/exynos5250.dtsi
> @@ -17,50 +17,9 @@
> * published by the Free Software Foundation.
> */
>
> -/include/ "skeleton.dtsi"
> +/include/ "exynos5.dtsi"
>
> / {
> - compatible = "samsung,exynos5250";
> -
> - sromc at 12250000 {
> - compatible = "samsung,exynos-sromc";
> - reg = <0x12250000 0x20>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - i2c at 12c60000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "samsung,s3c2440-i2c";
> - reg = <0x12C60000 0x100>;
> - interrupts = <0 56 0>;
> - };
> -
> - i2c at 12c70000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "samsung,s3c2440-i2c";
> - reg = <0x12C70000 0x100>;
> - interrupts = <0 57 0>;
> - };
> -
> - i2c at 12c80000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "samsung,s3c2440-i2c";
> - reg = <0x12C80000 0x100>;
> - interrupts = <0 58 0>;
> - };
> -
> - i2c at 12c90000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "samsung,s3c2440-i2c";
> - reg = <0x12C90000 0x100>;
> - interrupts = <0 59 0>;
> - };
> -
> i2c at 12ca0000 {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -116,139 +75,4 @@
> samsung,i2s-bit-clk-framesize = <32>;
> samsung,i2s-id = <1>;
> };
> -
> - spi at 12d20000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "samsung,exynos-spi";
> - reg = <0x12d20000 0x30>;
> - interrupts = <0 68 0>;
> - };
> -
> - spi at 12d30000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "samsung,exynos-spi";
> - reg = <0x12d30000 0x30>;
> - interrupts = <0 69 0>;
> - };
> -
> - spi at 12d40000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "samsung,exynos-spi";
> - reg = <0x12d40000 0x30>;
> - clock-frequency = <50000000>;
> - interrupts = <0 70 0>;
> - };
> -
> - spi at 131a0000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "samsung,exynos-spi";
> - reg = <0x131a0000 0x30>;
> - interrupts = <0 129 0>;
> - };
> -
> - spi at 131b0000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "samsung,exynos-spi";
> - reg = <0x131b0000 0x30>;
> - interrupts = <0 130 0>;
> - };
> -
> - ehci at 12110000 {
> - compatible = "samsung,exynos-ehci";
> - reg = <0x12110000 0x100>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> -
> - phy {
> - compatible = "samsung,exynos-usb-phy";
> - reg = <0x12130000 0x100>;
> - };
> - };
> -
> - tmu at 10060000 {
> - compatible = "samsung,exynos-tmu";
> - reg = <0x10060000 0x10000>;
> - };
> -
> - fimd at 14400000 {
> - compatible = "samsung,exynos-fimd";
> - reg = <0x14400000 0x10000>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> - };
> -
> - dp at 145b0000 {
> - compatible = "samsung,exynos5-dp";
> - reg = <0x145b0000 0x1000>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> - };
> -
> - mmc at 12200000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "samsung,exynos5250-dwmmc";
> - reg = <0x12200000 0x1000>;
> - interrupts = <0 75 0>;
> - };
> -
> - mmc at 12210000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "samsung,exynos5250-dwmmc";
> - reg = <0x12210000 0x1000>;
> - interrupts = <0 76 0>;
> - };
> -
> - mmc at 12220000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "samsung,exynos5250-dwmmc";
> - reg = <0x12220000 0x1000>;
> - interrupts = <0 77 0>;
> - };
> -
> - mmc at 12230000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "samsung,exynos5250-dwmmc";
> - reg = <0x12230000 0x1000>;
> - interrupts = <0 78 0>;
> - };
> -
> - serial at 12C00000 {
> - compatible = "samsung,exynos4210-uart";
> - reg = <0x12C00000 0x100>;
> - interrupts = <0 51 0>;
> - id = <0>;
> - };
> -
> - serial at 12C10000 {
> - compatible = "samsung,exynos4210-uart";
> - reg = <0x12C10000 0x100>;
> - interrupts = <0 52 0>;
> - id = <1>;
> - };
> -
> - serial at 12C20000 {
> - compatible = "samsung,exynos4210-uart";
> - reg = <0x12C20000 0x100>;
> - interrupts = <0 53 0>;
> - id = <2>;
> - };
> -
> - serial at 12C30000 {
> - compatible = "samsung,exynos4210-uart";
> - reg = <0x12C30000 0x100>;
> - interrupts = <0 54 0>;
> - id = <3>;
> - };
> -
> - gpio: gpio {
> - };
> };
> diff --git a/arch/arm/dts/exynos5420.dtsi b/arch/arm/dts/exynos5420.dtsi
> new file mode 100644
> index 0000000..ca6c605
> --- /dev/null
> +++ b/arch/arm/dts/exynos5420.dtsi
> @@ -0,0 +1,74 @@
> +/*
> + * SAMSUNG Peach board device tree source
> + *
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
>
please fix the license.
> +*/
> +
> +/include/ "exynos5.dtsi"
> +
> +/ {
> + config {
> + machine-arch-id = <4151>;
> + };
> +
> + i2c at 12ca0000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,exynos5-hsi2c";
> + reg = <0x12CA0000 0x100>;
> + interrupts = <0 60 0>;
> + };
> +
> + i2c at 12cb0000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,exynos5-hsi2c";
> + reg = <0x12CB0000 0x100>;
> + interrupts = <0 61 0>;
> + };
> +
> + i2c at 12cc0000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,exynos5-hsi2c";
> + reg = <0x12CC0000 0x100>;
> + interrupts = <0 62 0>;
> + };
> +
> + i2c at 12cd0000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,exynos5-hsi2c";
> + reg = <0x12CD0000 0x100>;
> + interrupts = <0 63 0>;
> + };
> +
> + i2c at 12e00000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,exynos5-hsi2c";
> + reg = <0x12E00000 0x100>;
> + interrupts = <0 87 0>;
> + };
> +
> + i2c at 12e10000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,exynos5-hsi2c";
> + reg = <0x12E10000 0x100>;
> + interrupts = <0 88 0>;
> + };
> +
> + i2c at 12e20000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "samsung,exynos5-hsi2c";
> + reg = <0x12E20000 0x100>;
> + interrupts = <0 203 0>;
> + };
> +};
> diff --git a/board/samsung/dts/exynos5420-smdk5420.dts
> b/board/samsung/dts/exynos5420-smdk5420.dts
> new file mode 100644
> index 0000000..5ef0c92
> --- /dev/null
> +++ b/board/samsung/dts/exynos5420-smdk5420.dts
> @@ -0,0 +1,172 @@
> +/*
> + * SAMSUNG SMDK5420 board device tree source
> + *
> + * Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
> + * Use of this source code is governed by a BSD-style license that can be
> + * found in the LICENSE file.
>
is it right?
> + */
> +
> +/dts-v1/;
> +/include/ "exynos5420.dtsi"
> +
> +/ {
> + model = "SAMSUNG SMDK5420 board based on EXYNOS5420";
> + compatible = "samsung,smdk5420", "samsung,exynos5";
> +
> + config {
> + hwid = "smdk5420 TEST A-A 9382";
> + };
> +
> + aliases {
> + i2c0 = "/i2c at 12c60000";
> + i2c1 = "/i2c at 12c70000";
> + i2c2 = "/i2c at 12c80000";
> + i2c3 = "/i2c at 12c90000";
> + i2c4 = "/i2c at 12ca0000";
> + i2c5 = "/i2c at 12cb0000";
> + i2c6 = "/i2c at 12cc0000";
> + i2c7 = "/i2c at 12cd0000";
> + i2c8 = "/i2c at 12e00000";
> + i2c9 = "/i2c at 12e10000";
> + i2c10 = "/i2c at 12e20000";
> + spi0 = "/spi at 12d20000";
> + spi1 = "/spi at 12d30000";
> + spi2 = "/spi at 12d40000";
> + spi3 = "/spi at 131a0000";
> + spi4 = "/spi at 131b0000";
> + mmc0 = "/mmc at 12200000";
> + mmc1 = "/mmc at 12210000";
> + mmc2 = "/mmc at 12220000";
> + xhci0 = "/xhci at 12000000";
> + xhci1 = "/xhci at 12400000";
> + serial0 = "/serial at 12C30000";
> + console = "/serial at 12C30000";
> + };
> +
> + tmu at 10060000 {
> + samsung,min-temp = <25>;
> + samsung,max-temp = <125>;
> + samsung,start-warning = <95>;
> + samsung,start-tripping = <105>;
> + samsung,hw-tripping = <110>;
> + samsung,efuse-min-value = <40>;
> + samsung,efuse-value = <55>;
> + samsung,efuse-max-value = <100>;
> + samsung,slope = <274761730>;
> + samsung,dc-value = <25>;
> + };
> +
> + /* s2mps11 is on i2c bus 4 */
> + i2c at 12ca0000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pmic at 66 {
> + reg = <0x66>;
> + compatible = "samsung,s2mps11-pmic";
> + };
> + };
> +
> + spi at 12d20000 { /* spi0 */
> + spi-max-frequency = <50000000>;
> + firmware_storage_spi: flash at 0 {
> + reg = <0>;
> + };
> + };
> +
> + fimd at 14400000 {
> + samsung,vl-freq = <60>;
> + samsung,vl-col = <2560>;
> + samsung,vl-row = <1600>;
> + samsung,vl-width = <2560>;
> + samsung,vl-height = <1600>;
> +
> + samsung,vl-clkp;
> + samsung,vl-dp;
> + samsung,vl-bpix = <4>;
> +
> + samsung,vl-hspw = <32>;
> + samsung,vl-hbpd = <80>;
> + samsung,vl-hfpd = <48>;
> + samsung,vl-vspw = <6>;
> + samsung,vl-vbpd = <37>;
> + samsung,vl-vfpd = <3>;
> + samsung,vl-cmd-allow-len = <0xf>;
> +
> + samsung,winid = <3>;
> + samsung,interface-mode = <1>;
> + samsung,dp-enabled = <1>;
> + samsung,dual-lcd-enabled = <0>;
> + };
> +
> + dmc {
> + mem-type = "lpddr3";
> + };
> +
> + sound at 3830000 {
> + samsung,codec-type = "wm8994";
> + };
> +
> + i2c at 12c70000 {
> + soundcodec at 1a {
> + reg = <0x1a>;
> + compatible = "wolfson,wm8994-codec";
> + };
> + };
> +
> + mmc at 12200000 {
> + samsung,bus-width = <8>;
> + samsung,timing = <1 3 3>;
> + samsung,removable = <0>;
> + samsung,pre-init;
> + };
> +
> + mmc at 12210000 {
> + status = "disabled";
> + };
> +
> + mmc at 12220000 {
> + samsung,bus-width = <4>;
> + samsung,timing = <1 2 3>;
> + samsung,removable = <1>;
> + };
> +
> + mmc at 12230000 {
> + status = "disabled";
> + };
> +
> + fimd at 14400000 {
> + /* sysmmu is not used in U-Boot */
> + samsung,disable-sysmmu;
> + };
> +
> + dp at 145b0000 {
> + samsung,lt-status = <0>;
> +
> + samsung,master-mode = <0>;
> + samsung,bist-mode = <0>;
> + samsung,bist-pattern = <0>;
> + samsung,h-sync-polarity = <0>;
> + samsung,v-sync-polarity = <0>;
> + samsung,interlaced = <0>;
> + samsung,color-space = <0>;
> + samsung,dynamic-range = <0>;
> + samsung,ycbcr-coeff = <0>;
> + samsung,color-depth = <1>;
> + };
> +
> + dmc {
> + mem-type = "ddr3";
> + };
> +
> + xhci1: xhci at 12400000 {
> + compatible = "samsung,exynos5250-xhci";
> + reg = <0x12400000 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + phy {
> + compatible = "samsung,exynos5250-usb3-phy";
> + reg = <0x12500000 0x100>;
> + };
> + };
> +};
> --
> 1.7.12.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
Thanks,
Minkyu Kang.
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 37+ messages in thread* [U-Boot] [PATCH 07/10 V6] DTS: Add dts support for SMDK5420
2013-11-13 3:17 ` Minkyu Kang
@ 2013-11-13 4:26 ` Rajeshwari Birje
2013-11-14 2:01 ` Minkyu Kang
0 siblings, 1 reply; 37+ messages in thread
From: Rajeshwari Birje @ 2013-11-13 4:26 UTC (permalink / raw)
To: u-boot
Hi Minkyu Kang,
Thank you for comments.
On Wed, Nov 13, 2013 at 8:47 AM, Minkyu Kang <promsoft@gmail.com> wrote:
> Dear Rajeshwari S Shinde,
>
>
> On 29 October 2013 16:23, Rajeshwari S Shinde <rajeshwari.s@samsung.com>wrote:
>
>> This patch adds support for SMDK5420.
>> exynos5.dtsi created is a common file which has the nodes common
>> to both 5420 and 5250.
>>
>> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
>> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
>> Acked-by: Simon Glass <sjg@chromium.org>
>> ---
>> Changes in V2:
>> - None
>> Changes in V3:
>> - None
>> Changes in V4:
>> - Added /include/ "exynos5420.dtsi
>> Changes in V5:
>> - None
>> Changes in V6:
>> - None
>> arch/arm/dts/exynos5.dtsi | 211
>> ++++++++++++++++++++++++++++++
>> arch/arm/dts/exynos5250.dtsi | 178 +------------------------
>> arch/arm/dts/exynos5420.dtsi | 74 +++++++++++
>> board/samsung/dts/exynos5420-smdk5420.dts | 172 ++++++++++++++++++++++++
>> 4 files changed, 458 insertions(+), 177 deletions(-)
>> create mode 100644 arch/arm/dts/exynos5.dtsi
>> create mode 100644 arch/arm/dts/exynos5420.dtsi
>> create mode 100644 board/samsung/dts/exynos5420-smdk5420.dts
>>
>> diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi
>> new file mode 100644
>> index 0000000..de86a06
>> --- /dev/null
>> +++ b/arch/arm/dts/exynos5.dtsi
>> @@ -0,0 +1,211 @@
>> +/*
>> + * SAMSUNG EXYNOS5 SoC device tree source
>> + *
>> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
>> + * http://www.samsung.com
>> + *
>> + * SAMSUNG EXYNOS5 SoC device nodes are listed in this file.
>> + * EXYNOS5 based board files can include this file and provide
>> + * values for board specfic bindings.
>> + *
>> + * Note: This file does not include device nodes for all the controllers
>> in
>> + * EXYNOS5 SoC. As device tree coverage for EXYNOS5 increases,
>> + * additional nodes can be added to this file.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>>
>
> please fix the license.
>
>
>> +*/
>> +
>> +/include/ "skeleton.dtsi"
>> +
>> +/ {
>> + compatible = "samsung,exynos5";
>> +
>> + sromc at 12250000 {
>> + compatible = "samsung,exynos-sromc";
>> + reg = <0x12250000 0x20>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c at 12c60000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "samsung,s3c2440-i2c";
>> + reg = <0x12C60000 0x100>;
>> + interrupts = <0 56 0>;
>> + };
>> +
>> + i2c at 12c70000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "samsung,s3c2440-i2c";
>> + reg = <0x12C70000 0x100>;
>> + interrupts = <0 57 0>;
>> + };
>> +
>> + i2c at 12c80000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "samsung,s3c2440-i2c";
>> + reg = <0x12C80000 0x100>;
>> + interrupts = <0 58 0>;
>> + };
>> +
>> + i2c at 12c90000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "samsung,s3c2440-i2c";
>> + reg = <0x12C90000 0x100>;
>> + interrupts = <0 59 0>;
>> + };
>> +
>> + spi at 12d20000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "samsung,exynos-spi";
>> + reg = <0x12d20000 0x30>;
>> + interrupts = <0 68 0>;
>> + };
>> +
>> + spi at 12d30000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "samsung,exynos-spi";
>> + reg = <0x12d30000 0x30>;
>> + interrupts = <0 69 0>;
>> + };
>> +
>> + spi at 12d40000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "samsung,exynos-spi";
>> + reg = <0x12d40000 0x30>;
>> + clock-frequency = <50000000>;
>> + interrupts = <0 70 0>;
>> + };
>> +
>> + spi at 131a0000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "samsung,exynos-spi";
>> + reg = <0x131a0000 0x30>;
>> + interrupts = <0 129 0>;
>> + };
>> +
>> + spi at 131b0000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "samsung,exynos-spi";
>> + reg = <0x131b0000 0x30>;
>> + interrupts = <0 130 0>;
>> + };
>> +
>> + ehci at 12110000 {
>> + compatible = "samsung,exynos-ehci";
>> + reg = <0x12110000 0x100>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + phy {
>> + compatible = "samsung,exynos-usb-phy";
>> + reg = <0x12130000 0x100>;
>> + };
>> + };
>> +
>> + tmu at 10060000 {
>> + compatible = "samsung,exynos-tmu";
>> + reg = <0x10060000 0x10000>;
>> + };
>> +
>> + fimd at 14400000 {
>> + compatible = "samsung,exynos-fimd";
>> + reg = <0x14400000 0x10000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + };
>> +
>> + dp at 145b0000 {
>> + compatible = "samsung,exynos5-dp";
>> + reg = <0x145b0000 0x1000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + };
>> +
>> + xhci0: xhci at 12000000 {
>> + compatible = "samsung,exynos5250-xhci";
>> + reg = <0x12000000 0x10000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + phy {
>> + compatible = "samsung,exynos5250-usb3-phy";
>> + reg = <0x12100000 0x100>;
>> + };
>> + };
>> +
>>
>
> please remove blank line.
>
>
>> +
>> + mmc at 12200000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "samsung,exynos5250-dwmmc";
>> + reg = <0x12200000 0x1000>;
>> + interrupts = <0 75 0>;
>> + };
>> +
>> + mmc at 12210000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "samsung,exynos5250-dwmmc";
>> + reg = <0x12210000 0x1000>;
>> + interrupts = <0 76 0>;
>> + };
>> +
>> + mmc at 12220000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "samsung,exynos5250-dwmmc";
>> + reg = <0x12220000 0x1000>;
>> + interrupts = <0 77 0>;
>> + };
>> +
>> + mmc at 12230000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "samsung,exynos5250-dwmmc";
>> + reg = <0x12230000 0x1000>;
>> + interrupts = <0 78 0>;
>> + };
>> +
>> + serial at 12C00000 {
>> + compatible = "samsung,exynos4210-uart";
>> + reg = <0x12C00000 0x100>;
>> + interrupts = <0 51 0>;
>> + id = <0>;
>> + };
>> +
>> + serial at 12C10000 {
>> + compatible = "samsung,exynos4210-uart";
>> + reg = <0x12C10000 0x100>;
>> + interrupts = <0 52 0>;
>> + id = <1>;
>> + };
>> +
>> + serial at 12C20000 {
>> + compatible = "samsung,exynos4210-uart";
>> + reg = <0x12C20000 0x100>;
>> + interrupts = <0 53 0>;
>> + id = <2>;
>> + };
>> +
>> + serial at 12C30000 {
>> + compatible = "samsung,exynos4210-uart";
>> + reg = <0x12C30000 0x100>;
>> + interrupts = <0 54 0>;
>> + id = <3>;
>> + };
>> +
>> + gpio: gpio {
>> + };
>> +};
>> diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi
>> index 44cbb5a..4533481 100644
>> --- a/arch/arm/dts/exynos5250.dtsi
>> +++ b/arch/arm/dts/exynos5250.dtsi
>> @@ -17,50 +17,9 @@
>> * published by the Free Software Foundation.
>> */
>>
>> -/include/ "skeleton.dtsi"
>> +/include/ "exynos5.dtsi"
>>
>> / {
>> - compatible = "samsung,exynos5250";
>> -
>> - sromc at 12250000 {
>> - compatible = "samsung,exynos-sromc";
>> - reg = <0x12250000 0x20>;
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - };
>> -
>> - i2c at 12c60000 {
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - compatible = "samsung,s3c2440-i2c";
>> - reg = <0x12C60000 0x100>;
>> - interrupts = <0 56 0>;
>> - };
>> -
>> - i2c at 12c70000 {
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - compatible = "samsung,s3c2440-i2c";
>> - reg = <0x12C70000 0x100>;
>> - interrupts = <0 57 0>;
>> - };
>> -
>> - i2c at 12c80000 {
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - compatible = "samsung,s3c2440-i2c";
>> - reg = <0x12C80000 0x100>;
>> - interrupts = <0 58 0>;
>> - };
>> -
>> - i2c at 12c90000 {
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - compatible = "samsung,s3c2440-i2c";
>> - reg = <0x12C90000 0x100>;
>> - interrupts = <0 59 0>;
>> - };
>> -
>> i2c at 12ca0000 {
>> #address-cells = <1>;
>> #size-cells = <0>;
>> @@ -116,139 +75,4 @@
>> samsung,i2s-bit-clk-framesize = <32>;
>> samsung,i2s-id = <1>;
>> };
>> -
>> - spi at 12d20000 {
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - compatible = "samsung,exynos-spi";
>> - reg = <0x12d20000 0x30>;
>> - interrupts = <0 68 0>;
>> - };
>> -
>> - spi at 12d30000 {
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - compatible = "samsung,exynos-spi";
>> - reg = <0x12d30000 0x30>;
>> - interrupts = <0 69 0>;
>> - };
>> -
>> - spi at 12d40000 {
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - compatible = "samsung,exynos-spi";
>> - reg = <0x12d40000 0x30>;
>> - clock-frequency = <50000000>;
>> - interrupts = <0 70 0>;
>> - };
>> -
>> - spi at 131a0000 {
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - compatible = "samsung,exynos-spi";
>> - reg = <0x131a0000 0x30>;
>> - interrupts = <0 129 0>;
>> - };
>> -
>> - spi at 131b0000 {
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - compatible = "samsung,exynos-spi";
>> - reg = <0x131b0000 0x30>;
>> - interrupts = <0 130 0>;
>> - };
>> -
>> - ehci at 12110000 {
>> - compatible = "samsung,exynos-ehci";
>> - reg = <0x12110000 0x100>;
>> - #address-cells = <1>;
>> - #size-cells = <1>;
>> -
>> - phy {
>> - compatible = "samsung,exynos-usb-phy";
>> - reg = <0x12130000 0x100>;
>> - };
>> - };
>> -
>> - tmu at 10060000 {
>> - compatible = "samsung,exynos-tmu";
>> - reg = <0x10060000 0x10000>;
>> - };
>> -
>> - fimd at 14400000 {
>> - compatible = "samsung,exynos-fimd";
>> - reg = <0x14400000 0x10000>;
>> - #address-cells = <1>;
>> - #size-cells = <1>;
>> - };
>> -
>> - dp at 145b0000 {
>> - compatible = "samsung,exynos5-dp";
>> - reg = <0x145b0000 0x1000>;
>> - #address-cells = <1>;
>> - #size-cells = <1>;
>> - };
>> -
>> - mmc at 12200000 {
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - compatible = "samsung,exynos5250-dwmmc";
>> - reg = <0x12200000 0x1000>;
>> - interrupts = <0 75 0>;
>> - };
>> -
>> - mmc at 12210000 {
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - compatible = "samsung,exynos5250-dwmmc";
>> - reg = <0x12210000 0x1000>;
>> - interrupts = <0 76 0>;
>> - };
>> -
>> - mmc at 12220000 {
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - compatible = "samsung,exynos5250-dwmmc";
>> - reg = <0x12220000 0x1000>;
>> - interrupts = <0 77 0>;
>> - };
>> -
>> - mmc at 12230000 {
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - compatible = "samsung,exynos5250-dwmmc";
>> - reg = <0x12230000 0x1000>;
>> - interrupts = <0 78 0>;
>> - };
>> -
>> - serial at 12C00000 {
>> - compatible = "samsung,exynos4210-uart";
>> - reg = <0x12C00000 0x100>;
>> - interrupts = <0 51 0>;
>> - id = <0>;
>> - };
>> -
>> - serial at 12C10000 {
>> - compatible = "samsung,exynos4210-uart";
>> - reg = <0x12C10000 0x100>;
>> - interrupts = <0 52 0>;
>> - id = <1>;
>> - };
>> -
>> - serial at 12C20000 {
>> - compatible = "samsung,exynos4210-uart";
>> - reg = <0x12C20000 0x100>;
>> - interrupts = <0 53 0>;
>> - id = <2>;
>> - };
>> -
>> - serial at 12C30000 {
>> - compatible = "samsung,exynos4210-uart";
>> - reg = <0x12C30000 0x100>;
>> - interrupts = <0 54 0>;
>> - id = <3>;
>> - };
>> -
>> - gpio: gpio {
>> - };
>> };
>> diff --git a/arch/arm/dts/exynos5420.dtsi b/arch/arm/dts/exynos5420.dtsi
>> new file mode 100644
>> index 0000000..ca6c605
>> --- /dev/null
>> +++ b/arch/arm/dts/exynos5420.dtsi
>> @@ -0,0 +1,74 @@
>> +/*
>> + * SAMSUNG Peach board device tree source
>> + *
>> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
>> + * http://www.samsung.com
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>>
>
> please fix the license.
>
>
>> +*/
>> +
>> +/include/ "exynos5.dtsi"
>> +
>> +/ {
>> + config {
>> + machine-arch-id = <4151>;
>> + };
>> +
>> + i2c at 12ca0000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "samsung,exynos5-hsi2c";
>> + reg = <0x12CA0000 0x100>;
>> + interrupts = <0 60 0>;
>> + };
>> +
>> + i2c at 12cb0000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "samsung,exynos5-hsi2c";
>> + reg = <0x12CB0000 0x100>;
>> + interrupts = <0 61 0>;
>> + };
>> +
>> + i2c at 12cc0000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "samsung,exynos5-hsi2c";
>> + reg = <0x12CC0000 0x100>;
>> + interrupts = <0 62 0>;
>> + };
>> +
>> + i2c at 12cd0000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "samsung,exynos5-hsi2c";
>> + reg = <0x12CD0000 0x100>;
>> + interrupts = <0 63 0>;
>> + };
>> +
>> + i2c at 12e00000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "samsung,exynos5-hsi2c";
>> + reg = <0x12E00000 0x100>;
>> + interrupts = <0 87 0>;
>> + };
>> +
>> + i2c at 12e10000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "samsung,exynos5-hsi2c";
>> + reg = <0x12E10000 0x100>;
>> + interrupts = <0 88 0>;
>> + };
>> +
>> + i2c at 12e20000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "samsung,exynos5-hsi2c";
>> + reg = <0x12E20000 0x100>;
>> + interrupts = <0 203 0>;
>> + };
>> +};
>> diff --git a/board/samsung/dts/exynos5420-smdk5420.dts
>> b/board/samsung/dts/exynos5420-smdk5420.dts
>> new file mode 100644
>> index 0000000..5ef0c92
>> --- /dev/null
>> +++ b/board/samsung/dts/exynos5420-smdk5420.dts
>> @@ -0,0 +1,172 @@
>> +/*
>> + * SAMSUNG SMDK5420 board device tree source
>> + *
>> + * Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
>> + * Use of this source code is governed by a BSD-style license that can be
>> + * found in the LICENSE file.
>>
>
> is it right?
Iam sorry did not get your question, about what are you pointing to?.
>
>
>> + */
>> +
>> +/dts-v1/;
>> +/include/ "exynos5420.dtsi"
>> +
>> +/ {
>> + model = "SAMSUNG SMDK5420 board based on EXYNOS5420";
>> + compatible = "samsung,smdk5420", "samsung,exynos5";
>> +
>> + config {
>> + hwid = "smdk5420 TEST A-A 9382";
>> + };
>> +
>> + aliases {
>> + i2c0 = "/i2c at 12c60000";
>> + i2c1 = "/i2c at 12c70000";
>> + i2c2 = "/i2c at 12c80000";
>> + i2c3 = "/i2c at 12c90000";
>> + i2c4 = "/i2c at 12ca0000";
>> + i2c5 = "/i2c at 12cb0000";
>> + i2c6 = "/i2c at 12cc0000";
>> + i2c7 = "/i2c at 12cd0000";
>> + i2c8 = "/i2c at 12e00000";
>> + i2c9 = "/i2c at 12e10000";
>> + i2c10 = "/i2c at 12e20000";
>> + spi0 = "/spi at 12d20000";
>> + spi1 = "/spi at 12d30000";
>> + spi2 = "/spi at 12d40000";
>> + spi3 = "/spi at 131a0000";
>> + spi4 = "/spi at 131b0000";
>> + mmc0 = "/mmc at 12200000";
>> + mmc1 = "/mmc at 12210000";
>> + mmc2 = "/mmc at 12220000";
>> + xhci0 = "/xhci at 12000000";
>> + xhci1 = "/xhci at 12400000";
>> + serial0 = "/serial at 12C30000";
>> + console = "/serial at 12C30000";
>> + };
>> +
>> + tmu at 10060000 {
>> + samsung,min-temp = <25>;
>> + samsung,max-temp = <125>;
>> + samsung,start-warning = <95>;
>> + samsung,start-tripping = <105>;
>> + samsung,hw-tripping = <110>;
>> + samsung,efuse-min-value = <40>;
>> + samsung,efuse-value = <55>;
>> + samsung,efuse-max-value = <100>;
>> + samsung,slope = <274761730>;
>> + samsung,dc-value = <25>;
>> + };
>> +
>> + /* s2mps11 is on i2c bus 4 */
>> + i2c at 12ca0000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + pmic at 66 {
>> + reg = <0x66>;
>> + compatible = "samsung,s2mps11-pmic";
>> + };
>> + };
>> +
>> + spi at 12d20000 { /* spi0 */
>> + spi-max-frequency = <50000000>;
>> + firmware_storage_spi: flash at 0 {
>> + reg = <0>;
>> + };
>> + };
>> +
>> + fimd at 14400000 {
>> + samsung,vl-freq = <60>;
>> + samsung,vl-col = <2560>;
>> + samsung,vl-row = <1600>;
>> + samsung,vl-width = <2560>;
>> + samsung,vl-height = <1600>;
>> +
>> + samsung,vl-clkp;
>> + samsung,vl-dp;
>> + samsung,vl-bpix = <4>;
>> +
>> + samsung,vl-hspw = <32>;
>> + samsung,vl-hbpd = <80>;
>> + samsung,vl-hfpd = <48>;
>> + samsung,vl-vspw = <6>;
>> + samsung,vl-vbpd = <37>;
>> + samsung,vl-vfpd = <3>;
>> + samsung,vl-cmd-allow-len = <0xf>;
>> +
>> + samsung,winid = <3>;
>> + samsung,interface-mode = <1>;
>> + samsung,dp-enabled = <1>;
>> + samsung,dual-lcd-enabled = <0>;
>> + };
>> +
>> + dmc {
>> + mem-type = "lpddr3";
>> + };
>> +
>> + sound at 3830000 {
>> + samsung,codec-type = "wm8994";
>> + };
>> +
>> + i2c at 12c70000 {
>> + soundcodec at 1a {
>> + reg = <0x1a>;
>> + compatible = "wolfson,wm8994-codec";
>> + };
>> + };
>> +
>> + mmc at 12200000 {
>> + samsung,bus-width = <8>;
>> + samsung,timing = <1 3 3>;
>> + samsung,removable = <0>;
>> + samsung,pre-init;
>> + };
>> +
>> + mmc at 12210000 {
>> + status = "disabled";
>> + };
>> +
>> + mmc at 12220000 {
>> + samsung,bus-width = <4>;
>> + samsung,timing = <1 2 3>;
>> + samsung,removable = <1>;
>> + };
>> +
>> + mmc at 12230000 {
>> + status = "disabled";
>> + };
>> +
>> + fimd at 14400000 {
>> + /* sysmmu is not used in U-Boot */
>> + samsung,disable-sysmmu;
>> + };
>> +
>> + dp at 145b0000 {
>> + samsung,lt-status = <0>;
>> +
>> + samsung,master-mode = <0>;
>> + samsung,bist-mode = <0>;
>> + samsung,bist-pattern = <0>;
>> + samsung,h-sync-polarity = <0>;
>> + samsung,v-sync-polarity = <0>;
>> + samsung,interlaced = <0>;
>> + samsung,color-space = <0>;
>> + samsung,dynamic-range = <0>;
>> + samsung,ycbcr-coeff = <0>;
>> + samsung,color-depth = <1>;
>> + };
>> +
>> + dmc {
>> + mem-type = "ddr3";
>> + };
>> +
>> + xhci1: xhci at 12400000 {
>> + compatible = "samsung,exynos5250-xhci";
>> + reg = <0x12400000 0x10000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + phy {
>> + compatible = "samsung,exynos5250-usb3-phy";
>> + reg = <0x12500000 0x100>;
>> + };
>> + };
>> +};
>> --
>> 1.7.12.4
>>
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
>>
>
>
> Thanks,
> Minkyu Kang.
> --
> from. prom.
> www.promsoft.net
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
--
Regards,
Rajeshwari Shinde
^ permalink raw reply [flat|nested] 37+ messages in thread* [U-Boot] [PATCH 07/10 V6] DTS: Add dts support for SMDK5420
2013-11-13 4:26 ` Rajeshwari Birje
@ 2013-11-14 2:01 ` Minkyu Kang
2013-11-15 2:32 ` Rajeshwari Birje
0 siblings, 1 reply; 37+ messages in thread
From: Minkyu Kang @ 2013-11-14 2:01 UTC (permalink / raw)
To: u-boot
Dear Rajeshwari,
On 13 November 2013 13:26, Rajeshwari Birje <rajeshwari.birje@gmail.com>wrote:
> Hi Minkyu Kang,
>
> Thank you for comments.
>
> On Wed, Nov 13, 2013 at 8:47 AM, Minkyu Kang <promsoft@gmail.com> wrote:
> > Dear Rajeshwari S Shinde,
> >
> >
> > On 29 October 2013 16:23, Rajeshwari S Shinde <rajeshwari.s@samsung.com
> >wrote:
> >
> >> This patch adds support for SMDK5420.
> >> exynos5.dtsi created is a common file which has the nodes common
> >> to both 5420 and 5250.
> >>
> >> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
> >> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
> >> Acked-by: Simon Glass <sjg@chromium.org>
> >> ---
> >> Changes in V2:
> >> - None
> >> Changes in V3:
> >> - None
> >> Changes in V4:
> >> - Added /include/ "exynos5420.dtsi
> >> Changes in V5:
> >> - None
> >> Changes in V6:
> >> - None
> >> arch/arm/dts/exynos5.dtsi | 211
> >> ++++++++++++++++++++++++++++++
> >> arch/arm/dts/exynos5250.dtsi | 178
> +------------------------
> >> arch/arm/dts/exynos5420.dtsi | 74 +++++++++++
> >> board/samsung/dts/exynos5420-smdk5420.dts | 172
> ++++++++++++++++++++++++
> >> 4 files changed, 458 insertions(+), 177 deletions(-)
> >> create mode 100644 arch/arm/dts/exynos5.dtsi
> >> create mode 100644 arch/arm/dts/exynos5420.dtsi
> >> create mode 100644 board/samsung/dts/exynos5420-smdk5420.dts
> >>
> >> diff --git a/board/samsung/dts/exynos5420-smdk5420.dts
> >> b/board/samsung/dts/exynos5420-smdk5420.dts
> >> new file mode 100644
> >> index 0000000..5ef0c92
> >> --- /dev/null
> >> +++ b/board/samsung/dts/exynos5420-smdk5420.dts
> >> @@ -0,0 +1,172 @@
> >> +/*
> >> + * SAMSUNG SMDK5420 board device tree source
> >> + *
> >> + * Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
> >> + * Use of this source code is governed by a BSD-style license that can
> be
> >> + * found in the LICENSE file.
> >>
> >
> > is it right?
> Iam sorry did not get your question, about what are you pointing to?.
>
The Copyright and License.
>
> >
> >
> >> + */
> >> +
> >> +/dts-v1/;
> >> +/include/ "exynos5420.dtsi"
> >> +
> >> +/ {
> >> + model = "SAMSUNG SMDK5420 board based on EXYNOS5420";
> >> + compatible = "samsung,smdk5420", "samsung,exynos5";
> >> +
> >> + config {
> >> + hwid = "smdk5420 TEST A-A 9382";
> >> + };
> >> +
> >> + aliases {
> >> + i2c0 = "/i2c at 12c60000";
> >> + i2c1 = "/i2c at 12c70000";
> >> + i2c2 = "/i2c at 12c80000";
> >> + i2c3 = "/i2c at 12c90000";
> >> + i2c4 = "/i2c at 12ca0000";
> >> + i2c5 = "/i2c at 12cb0000";
> >> + i2c6 = "/i2c at 12cc0000";
> >> + i2c7 = "/i2c at 12cd0000";
> >> + i2c8 = "/i2c at 12e00000";
> >> + i2c9 = "/i2c at 12e10000";
> >> + i2c10 = "/i2c at 12e20000";
> >> + spi0 = "/spi at 12d20000";
> >> + spi1 = "/spi at 12d30000";
> >> + spi2 = "/spi at 12d40000";
> >> + spi3 = "/spi at 131a0000";
> >> + spi4 = "/spi at 131b0000";
> >> + mmc0 = "/mmc at 12200000";
> >> + mmc1 = "/mmc at 12210000";
> >> + mmc2 = "/mmc at 12220000";
> >> + xhci0 = "/xhci at 12000000";
> >> + xhci1 = "/xhci at 12400000";
> >> + serial0 = "/serial at 12C30000";
> >> + console = "/serial at 12C30000";
> >> + };
> >> +
> >> + tmu at 10060000 {
> >> + samsung,min-temp = <25>;
> >> + samsung,max-temp = <125>;
> >> + samsung,start-warning = <95>;
> >> + samsung,start-tripping = <105>;
> >> + samsung,hw-tripping = <110>;
> >> + samsung,efuse-min-value = <40>;
> >> + samsung,efuse-value = <55>;
> >> + samsung,efuse-max-value = <100>;
> >> + samsung,slope = <274761730>;
> >> + samsung,dc-value = <25>;
> >> + };
> >> +
> >> + /* s2mps11 is on i2c bus 4 */
> >> + i2c at 12ca0000 {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> + pmic at 66 {
> >> + reg = <0x66>;
> >> + compatible = "samsung,s2mps11-pmic";
> >> + };
> >> + };
> >> +
> >> + spi at 12d20000 { /* spi0 */
> >> + spi-max-frequency = <50000000>;
> >> + firmware_storage_spi: flash at 0 {
> >> + reg = <0>;
> >> + };
> >> + };
> >> +
> >> + fimd at 14400000 {
> >> + samsung,vl-freq = <60>;
> >> + samsung,vl-col = <2560>;
> >> + samsung,vl-row = <1600>;
> >> + samsung,vl-width = <2560>;
> >> + samsung,vl-height = <1600>;
> >> +
> >> + samsung,vl-clkp;
> >> + samsung,vl-dp;
> >> + samsung,vl-bpix = <4>;
> >> +
> >> + samsung,vl-hspw = <32>;
> >> + samsung,vl-hbpd = <80>;
> >> + samsung,vl-hfpd = <48>;
> >> + samsung,vl-vspw = <6>;
> >> + samsung,vl-vbpd = <37>;
> >> + samsung,vl-vfpd = <3>;
> >> + samsung,vl-cmd-allow-len = <0xf>;
> >> +
> >> + samsung,winid = <3>;
> >> + samsung,interface-mode = <1>;
> >> + samsung,dp-enabled = <1>;
> >> + samsung,dual-lcd-enabled = <0>;
> >> + };
> >> +
> >> + dmc {
> >> + mem-type = "lpddr3";
> >> + };
> >> +
> >> + sound at 3830000 {
> >> + samsung,codec-type = "wm8994";
> >> + };
> >> +
> >> + i2c at 12c70000 {
> >> + soundcodec at 1a {
> >> + reg = <0x1a>;
> >> + compatible = "wolfson,wm8994-codec";
> >> + };
> >> + };
> >> +
> >> + mmc at 12200000 {
> >> + samsung,bus-width = <8>;
> >> + samsung,timing = <1 3 3>;
> >> + samsung,removable = <0>;
> >> + samsung,pre-init;
> >> + };
> >> +
> >> + mmc at 12210000 {
> >> + status = "disabled";
> >> + };
> >> +
> >> + mmc at 12220000 {
> >> + samsung,bus-width = <4>;
> >> + samsung,timing = <1 2 3>;
> >> + samsung,removable = <1>;
> >> + };
> >> +
> >> + mmc at 12230000 {
> >> + status = "disabled";
> >> + };
> >> +
> >> + fimd at 14400000 {
> >> + /* sysmmu is not used in U-Boot */
> >> + samsung,disable-sysmmu;
> >> + };
> >> +
> >> + dp at 145b0000 {
> >> + samsung,lt-status = <0>;
> >> +
> >> + samsung,master-mode = <0>;
> >> + samsung,bist-mode = <0>;
> >> + samsung,bist-pattern = <0>;
> >> + samsung,h-sync-polarity = <0>;
> >> + samsung,v-sync-polarity = <0>;
> >> + samsung,interlaced = <0>;
> >> + samsung,color-space = <0>;
> >> + samsung,dynamic-range = <0>;
> >> + samsung,ycbcr-coeff = <0>;
> >> + samsung,color-depth = <1>;
> >> + };
> >> +
> >> + dmc {
> >> + mem-type = "ddr3";
> >> + };
> >> +
> >> + xhci1: xhci at 12400000 {
> >> + compatible = "samsung,exynos5250-xhci";
> >> + reg = <0x12400000 0x10000>;
> >> + #address-cells = <1>;
> >> + #size-cells = <1>;
> >> +
> >> + phy {
> >> + compatible = "samsung,exynos5250-usb3-phy";
> >> + reg = <0x12500000 0x100>;
> >> + };
> >> + };
> >> +};
> >> --
> >> 1.7.12.4
> >>
> >> _______________________________________________
> >> U-Boot mailing list
> >> U-Boot at lists.denx.de
> >> http://lists.denx.de/mailman/listinfo/u-boot
> >>
> >
> >
> > Thanks,
> > Minkyu Kang.
> > --
> > from. prom.
> > www.promsoft.net
> >
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > http://lists.denx.de/mailman/listinfo/u-boot
> >
>
>
>
> --
> Regards,
> Rajeshwari Shinde
>
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 37+ messages in thread* [U-Boot] [PATCH 07/10 V6] DTS: Add dts support for SMDK5420
2013-11-14 2:01 ` Minkyu Kang
@ 2013-11-15 2:32 ` Rajeshwari Birje
0 siblings, 0 replies; 37+ messages in thread
From: Rajeshwari Birje @ 2013-11-15 2:32 UTC (permalink / raw)
To: u-boot
Hi Minkyu Kang,
On Thu, Nov 14, 2013 at 7:31 AM, Minkyu Kang <promsoft@gmail.com> wrote:
> Dear Rajeshwari,
>
>
> On 13 November 2013 13:26, Rajeshwari Birje <rajeshwari.birje@gmail.com>
> wrote:
>>
>> Hi Minkyu Kang,
>>
>> Thank you for comments.
>>
>> On Wed, Nov 13, 2013 at 8:47 AM, Minkyu Kang <promsoft@gmail.com> wrote:
>> > Dear Rajeshwari S Shinde,
>> >
>> >
>> > On 29 October 2013 16:23, Rajeshwari S Shinde
>> > <rajeshwari.s@samsung.com>wrote:
>> >
>> >> This patch adds support for SMDK5420.
>> >> exynos5.dtsi created is a common file which has the nodes common
>> >> to both 5420 and 5250.
>> >>
>> >> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
>> >> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
>> >> Acked-by: Simon Glass <sjg@chromium.org>
>> >> ---
>> >> Changes in V2:
>> >> - None
>> >> Changes in V3:
>> >> - None
>> >> Changes in V4:
>> >> - Added /include/ "exynos5420.dtsi
>> >> Changes in V5:
>> >> - None
>> >> Changes in V6:
>> >> - None
>> >> arch/arm/dts/exynos5.dtsi | 211
>> >> ++++++++++++++++++++++++++++++
>> >> arch/arm/dts/exynos5250.dtsi | 178
>> >> +------------------------
>> >> arch/arm/dts/exynos5420.dtsi | 74 +++++++++++
>> >> board/samsung/dts/exynos5420-smdk5420.dts | 172
>> >> ++++++++++++++++++++++++
>> >> 4 files changed, 458 insertions(+), 177 deletions(-)
>> >> create mode 100644 arch/arm/dts/exynos5.dtsi
>> >> create mode 100644 arch/arm/dts/exynos5420.dtsi
>> >> create mode 100644 board/samsung/dts/exynos5420-smdk5420.dts
>> >>
>> >> diff --git a/board/samsung/dts/exynos5420-smdk5420.dts
>> >> b/board/samsung/dts/exynos5420-smdk5420.dts
>> >> new file mode 100644
>> >> index 0000000..5ef0c92
>> >> --- /dev/null
>> >> +++ b/board/samsung/dts/exynos5420-smdk5420.dts
>> >> @@ -0,0 +1,172 @@
>> >> +/*
>> >> + * SAMSUNG SMDK5420 board device tree source
>> >> + *
>> >> + * Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
>> >> + * Use of this source code is governed by a BSD-style license that can
>> >> be
>> >> + * found in the LICENSE file.
>> >>
>> >
>> > is it right?
>> Iam sorry did not get your question, about what are you pointing to?.
>
>
> The Copyright and License.
Have corrected this in V7.
>
>>
>>
>> >
>> >
>> >> + */
>> >> +
>> >> +/dts-v1/;
>> >> +/include/ "exynos5420.dtsi"
>> >> +
>> >> +/ {
>> >> + model = "SAMSUNG SMDK5420 board based on EXYNOS5420";
>> >> + compatible = "samsung,smdk5420", "samsung,exynos5";
>> >> +
>> >> + config {
>> >> + hwid = "smdk5420 TEST A-A 9382";
>> >> + };
>> >> +
>> >> + aliases {
>> >> + i2c0 = "/i2c at 12c60000";
>> >> + i2c1 = "/i2c at 12c70000";
>> >> + i2c2 = "/i2c at 12c80000";
>> >> + i2c3 = "/i2c at 12c90000";
>> >> + i2c4 = "/i2c at 12ca0000";
>> >> + i2c5 = "/i2c at 12cb0000";
>> >> + i2c6 = "/i2c at 12cc0000";
>> >> + i2c7 = "/i2c at 12cd0000";
>> >> + i2c8 = "/i2c at 12e00000";
>> >> + i2c9 = "/i2c at 12e10000";
>> >> + i2c10 = "/i2c at 12e20000";
>> >> + spi0 = "/spi at 12d20000";
>> >> + spi1 = "/spi at 12d30000";
>> >> + spi2 = "/spi at 12d40000";
>> >> + spi3 = "/spi at 131a0000";
>> >> + spi4 = "/spi at 131b0000";
>> >> + mmc0 = "/mmc at 12200000";
>> >> + mmc1 = "/mmc at 12210000";
>> >> + mmc2 = "/mmc at 12220000";
>> >> + xhci0 = "/xhci at 12000000";
>> >> + xhci1 = "/xhci at 12400000";
>> >> + serial0 = "/serial at 12C30000";
>> >> + console = "/serial at 12C30000";
>> >> + };
>> >> +
>> >> + tmu at 10060000 {
>> >> + samsung,min-temp = <25>;
>> >> + samsung,max-temp = <125>;
>> >> + samsung,start-warning = <95>;
>> >> + samsung,start-tripping = <105>;
>> >> + samsung,hw-tripping = <110>;
>> >> + samsung,efuse-min-value = <40>;
>> >> + samsung,efuse-value = <55>;
>> >> + samsung,efuse-max-value = <100>;
>> >> + samsung,slope = <274761730>;
>> >> + samsung,dc-value = <25>;
>> >> + };
>> >> +
>> >> + /* s2mps11 is on i2c bus 4 */
>> >> + i2c at 12ca0000 {
>> >> + #address-cells = <1>;
>> >> + #size-cells = <0>;
>> >> + pmic at 66 {
>> >> + reg = <0x66>;
>> >> + compatible = "samsung,s2mps11-pmic";
>> >> + };
>> >> + };
>> >> +
>> >> + spi at 12d20000 { /* spi0 */
>> >> + spi-max-frequency = <50000000>;
>> >> + firmware_storage_spi: flash at 0 {
>> >> + reg = <0>;
>> >> + };
>> >> + };
>> >> +
>> >> + fimd at 14400000 {
>> >> + samsung,vl-freq = <60>;
>> >> + samsung,vl-col = <2560>;
>> >> + samsung,vl-row = <1600>;
>> >> + samsung,vl-width = <2560>;
>> >> + samsung,vl-height = <1600>;
>> >> +
>> >> + samsung,vl-clkp;
>> >> + samsung,vl-dp;
>> >> + samsung,vl-bpix = <4>;
>> >> +
>> >> + samsung,vl-hspw = <32>;
>> >> + samsung,vl-hbpd = <80>;
>> >> + samsung,vl-hfpd = <48>;
>> >> + samsung,vl-vspw = <6>;
>> >> + samsung,vl-vbpd = <37>;
>> >> + samsung,vl-vfpd = <3>;
>> >> + samsung,vl-cmd-allow-len = <0xf>;
>> >> +
>> >> + samsung,winid = <3>;
>> >> + samsung,interface-mode = <1>;
>> >> + samsung,dp-enabled = <1>;
>> >> + samsung,dual-lcd-enabled = <0>;
>> >> + };
>> >> +
>> >> + dmc {
>> >> + mem-type = "lpddr3";
>> >> + };
>> >> +
>> >> + sound at 3830000 {
>> >> + samsung,codec-type = "wm8994";
>> >> + };
>> >> +
>> >> + i2c at 12c70000 {
>> >> + soundcodec at 1a {
>> >> + reg = <0x1a>;
>> >> + compatible = "wolfson,wm8994-codec";
>> >> + };
>> >> + };
>> >> +
>> >> + mmc at 12200000 {
>> >> + samsung,bus-width = <8>;
>> >> + samsung,timing = <1 3 3>;
>> >> + samsung,removable = <0>;
>> >> + samsung,pre-init;
>> >> + };
>> >> +
>> >> + mmc at 12210000 {
>> >> + status = "disabled";
>> >> + };
>> >> +
>> >> + mmc at 12220000 {
>> >> + samsung,bus-width = <4>;
>> >> + samsung,timing = <1 2 3>;
>> >> + samsung,removable = <1>;
>> >> + };
>> >> +
>> >> + mmc at 12230000 {
>> >> + status = "disabled";
>> >> + };
>> >> +
>> >> + fimd at 14400000 {
>> >> + /* sysmmu is not used in U-Boot */
>> >> + samsung,disable-sysmmu;
>> >> + };
>> >> +
>> >> + dp at 145b0000 {
>> >> + samsung,lt-status = <0>;
>> >> +
>> >> + samsung,master-mode = <0>;
>> >> + samsung,bist-mode = <0>;
>> >> + samsung,bist-pattern = <0>;
>> >> + samsung,h-sync-polarity = <0>;
>> >> + samsung,v-sync-polarity = <0>;
>> >> + samsung,interlaced = <0>;
>> >> + samsung,color-space = <0>;
>> >> + samsung,dynamic-range = <0>;
>> >> + samsung,ycbcr-coeff = <0>;
>> >> + samsung,color-depth = <1>;
>> >> + };
>> >> +
>> >> + dmc {
>> >> + mem-type = "ddr3";
>> >> + };
>> >> +
>> >> + xhci1: xhci at 12400000 {
>> >> + compatible = "samsung,exynos5250-xhci";
>> >> + reg = <0x12400000 0x10000>;
>> >> + #address-cells = <1>;
>> >> + #size-cells = <1>;
>> >> +
>> >> + phy {
>> >> + compatible = "samsung,exynos5250-usb3-phy";
>> >> + reg = <0x12500000 0x100>;
>> >> + };
>> >> + };
>> >> +};
>> >> --
>> >> 1.7.12.4
>> >>
>> >> _______________________________________________
>> >> U-Boot mailing list
>> >> U-Boot at lists.denx.de
>> >> http://lists.denx.de/mailman/listinfo/u-boot
>> >>
>> >
>> >
>> > Thanks,
>> > Minkyu Kang.
>> > --
>> > from. prom.
>> > www.promsoft.net
>> >
>> > _______________________________________________
>> > U-Boot mailing list
>> > U-Boot at lists.denx.de
>> > http://lists.denx.de/mailman/listinfo/u-boot
>> >
>>
>>
>>
>> --
>> Regards,
>> Rajeshwari Shinde
>
>
>
>
> --
> from. prom.
> www.promsoft.net
--
Regards,
Rajeshwari Shinde
^ permalink raw reply [flat|nested] 37+ messages in thread
* [U-Boot] [PATCH 08/10 V6] Config: Add initial config for SMDK5420
2013-10-29 7:23 [U-Boot] [PATCH 00/10 V6] EXYNOS5420: Add SMDK5420 board support Rajeshwari S Shinde
` (6 preceding siblings ...)
2013-10-29 7:23 ` [U-Boot] [PATCH 07/10 V6] DTS: Add dts support " Rajeshwari S Shinde
@ 2013-10-29 7:23 ` Rajeshwari S Shinde
2013-11-13 3:31 ` Minkyu Kang
2013-10-29 7:23 ` [U-Boot] [PATCH 09/10 V6] SPL: EXYNOS: Prepare for variable size SPL support Rajeshwari S Shinde
` (2 subsequent siblings)
10 siblings, 1 reply; 37+ messages in thread
From: Rajeshwari S Shinde @ 2013-10-29 7:23 UTC (permalink / raw)
To: u-boot
Adding initial config for SMDK5420 to build and boot U-Boot
over Exynos based SMDK5420.
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Created a common exynos5-dt.h
Changes in V5:
- None
Changes in V6:
- None
include/configs/exynos5-dt.h | 302 +++++++++++++++++++++++++++++++++++++
include/configs/exynos5250-dt.h | 319 +---------------------------------------
include/configs/smdk5420.h | 49 ++++++
3 files changed, 359 insertions(+), 311 deletions(-)
create mode 100644 include/configs/exynos5-dt.h
create mode 100644 include/configs/smdk5420.h
diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h
new file mode 100644
index 0000000..fa6bb89
--- /dev/null
+++ b/include/configs/exynos5-dt.h
@@ -0,0 +1,302 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5 board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG /* in a SAMSUNG core */
+#define CONFIG_S5P /* S5P Family */
+#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_COMMON
+#define CONFIG_ARCH_EARLY_INIT_R
+
+/* Enable fdt support for Exynos5250 */
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* Allow tracing to be enabled */
+#define CONFIG_TRACE
+#define CONFIG_CMD_TRACE
+#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
+#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
+#define CONFIG_TRACE_EARLY
+#define CONFIG_TRACE_EARLY_ADDR 0x50000000
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_SYS_DCACHE_OFF
+
+/* Enable ACE acceleration for SHA1 and SHA256 */
+#define CONFIG_EXYNOS_ACE_SHA
+#define CONFIG_SHA_HW_ACCEL
+
+
+/* input clock of PLL: SMDK5250 has 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ 24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP 0x00000BAD
+#define S5P_CHECK_DIDLE 0xBAD00000
+#define S5P_CHECK_LPA 0xABAD0000
+
+/* Offset for inform registers */
+#define INFORM0_OFFSET 0x800
+#define INFORM1_OFFSET 0x804
+#define INFORM2_OFFSET 0x808
+#define INFORM3_OFFSET 0x80c
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE 115200
+#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
+#define CONFIG_SILENT_CONSOLE
+
+/* Enable keyboard */
+#define CONFIG_CROS_EC /* CROS_EC protocol */
+#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
+#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */
+#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */
+#define CONFIG_CMD_CROS_EC
+#define CONFIG_KEYBOARD
+
+/* Console configuration */
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define EXYNOS_DEVICE_SETTINGS \
+ "stdin=serial,cros-ec-keyb\0" \
+ "stdout=serial,lcd\0" \
+ "stderr=serial,lcd\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ EXYNOS_DEVICE_SETTINGS
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_S5P_SDHCI
+#define CONFIG_DWMMC
+#define CONFIG_EXYNOS_DWMMC
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* PWM */
+#define CONFIG_PWM
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_HASH
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/* Thermal Management Unit */
+#define CONFIG_EXYNOS_TMU
+#define CONFIG_CMD_DTT
+#define CONFIG_TMU_CMD_DTT
+
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_EXYNOS
+#define CONFIG_USB_STORAGE
+
+/* USB boot mode */
+#define CONFIG_USB_BOOTING
+#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
+#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
+#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
+
+/* TPM */
+#define CONFIG_TPM
+#define CONFIG_CMD_TPM
+#define CONFIG_TPM_TIS_I2C
+#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3
+#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20
+
+/* MMC SPL */
+#define CONFIG_SPL
+#define COPY_BL2_FNPTR_ADDR 0x02020030
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+
+/* specific .lds file */
+#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
+#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
+
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_RD_LVL
+
+#define CONFIG_NR_DRAM_BANKS 8
+#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_SECURE_BL1_ONLY
+
+/* Secure FW size configuration */
+#ifdef CONFIG_SECURE_BL1_ONLY
+#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
+#else
+#define CONFIG_SEC_FW_SIZE 0
+#endif
+
+/* Configuration of BL1, BL2, ENV Blocks on mmc */
+#define CONFIG_RES_BLOCK_SIZE (512)
+#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
+#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
+
+#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
+#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
+#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
+
+/* U-boot copy size from boot Media to DRAM.*/
+#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
+#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
+
+#define CONFIG_SPI_BOOTING
+#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
+#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_PART
+#define CONFIG_PARTITION_UUIDS
+
+/* I2C */
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_HARD_I2C
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
+#define CONFIG_DRIVER_S3C24X0_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_I2C_EDID
+
+/* SPI */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SPI_FLASH
+
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_EXYNOS_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SPI_FLASH_GIGADEVICE
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED 50000000
+#define EXYNOS5_SPI_NUM_CONTROLLERS 5
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MODE SPI_MODE_0
+#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
+#define CONFIG_ENV_SPI_BUS 1
+#define CONFIG_ENV_SPI_MAX_HZ 50000000
+#endif
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+
+/* Ethernet Controllor Driver */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE 0x5000000
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_ENV_SROM_BANK 1
+#endif /*CONFIG_CMD_NET*/
+
+/* Enable PXE Support */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_PXE
+#define CONFIG_MENU
+#endif
+
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
+
+/* SHA hashing */
+#define CONFIG_CMD_HASH
+#define CONFIG_HASH_VERIFY
+#define CONFIG_SHA1
+#define CONFIG_SHA256
+
+/* Enable Time Command */
+#define CONFIG_CMD_TIME
+
+#define CONFIG_CMD_BOOTZ
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 3736ea8..689919d 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -1,3 +1,4 @@
+
/*
* Copyright (C) 2012 Samsung Electronics
*
@@ -6,325 +7,34 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_SAMSUNG /* in a SAMSUNG core */
-#define CONFIG_S5P /* S5P Family */
-#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
-#define CONFIG_EXYNOS5250
-
-#include <asm/arch/cpu.h> /* get chip and board defs */
-
-#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOARD_COMMON
-#define CONFIG_ARCH_EARLY_INIT_R
+#ifndef __CONFIG_5250_H
+#define __CONFIG_5250_H
-/* Enable fdt support for Exynos5250 */
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
+#include <configs/exynos5-dt.h>
-/* Allow tracing to be enabled */
-#define CONFIG_TRACE
-#define CONFIG_CMD_TRACE
-#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
-#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
-#define CONFIG_TRACE_EARLY
-#define CONFIG_TRACE_EARLY_ADDR 0x50000000
-
-/* Keep L2 Cache Disabled */
-#define CONFIG_SYS_DCACHE_OFF
-
-/* Enable ACE acceleration for SHA1 and SHA256 */
-#define CONFIG_EXYNOS_ACE_SHA
-#define CONFIG_SHA_HW_ACCEL
+#define CONFIG_EXYNOS5250
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_TEXT_BASE 0x43E00000
-/* input clock of PLL: SMDK5250 has 24MHz input clock */
-#define CONFIG_SYS_CLK_FREQ 24000000
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_EDITING
-
/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
#define MACH_TYPE_SMDK5250 3774
#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
-/* Power Down Modes */
-#define S5P_CHECK_SLEEP 0x00000BAD
-#define S5P_CHECK_DIDLE 0xBAD00000
-#define S5P_CHECK_LPA 0xABAD0000
-
-/* Offset for inform registers */
-#define INFORM0_OFFSET 0x800
-#define INFORM1_OFFSET 0x804
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
-
-/* select serial console configuration */
-#define CONFIG_BAUDRATE 115200
-#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
-#define CONFIG_SILENT_CONSOLE
-
-/* Enable keyboard */
-#define CONFIG_CROS_EC /* CROS_EC protocol */
-#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
-#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */
-#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */
-#define CONFIG_CMD_CROS_EC
-#define CONFIG_KEYBOARD
-
-/* Console configuration */
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define EXYNOS_DEVICE_SETTINGS \
- "stdin=serial,cros-ec-keyb\0" \
- "stdout=serial,lcd\0" \
- "stderr=serial,lcd\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- EXYNOS_DEVICE_SETTINGS
-
-/* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_S5P_SDHCI
-#define CONFIG_DWMMC
-#define CONFIG_EXYNOS_DWMMC
-#define CONFIG_SUPPORT_EMMC_BOOT
-
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-/* PWM */
-#define CONFIG_PWM
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Command definition*/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_HASH
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-/* Thermal Management Unit */
-#define CONFIG_EXYNOS_TMU
-#define CONFIG_CMD_DTT
-#define CONFIG_TMU_CMD_DTT
-
-/* USB */
-#define CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_EXYNOS
-#define CONFIG_USB_STORAGE
-
-/* USB boot mode */
-#define CONFIG_USB_BOOTING
-#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
-#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
-#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
-
-/* TPM */
-#define CONFIG_TPM
-#define CONFIG_CMD_TPM
-#define CONFIG_TPM_TIS_I2C
-#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3
-#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20
-
-/* MMC SPL */
-#define CONFIG_SPL
-#define COPY_BL2_FNPTR_ADDR 0x02020030
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-
-/* specific .lds file */
-#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
#define CONFIG_SPL_TEXT_BASE 0x02023400
-#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
-
#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT "SMDK5250 # "
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-
-#define CONFIG_SYS_HZ 1000
-
-#define CONFIG_RD_LVL
-
-#define CONFIG_NR_DRAM_BANKS 8
-#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
-#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
-#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
-
-#define CONFIG_SYS_MONITOR_BASE 0x00000000
-
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-#undef CONFIG_CMD_IMLS
#define CONFIG_IDENT_STRING " for SMDK5250"
-#define CONFIG_SYS_MMC_ENV_DEV 0
-
-#define CONFIG_SECURE_BL1_ONLY
-
-/* Secure FW size configuration */
-#ifdef CONFIG_SECURE_BL1_ONLY
-#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
-#else
-#define CONFIG_SEC_FW_SIZE 0
-#endif
-
-/* Configuration of BL1, BL2, ENV Blocks on mmc */
-#define CONFIG_RES_BLOCK_SIZE (512)
-#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
-#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
-#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
-
-#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
-#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
-#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
-
-/* U-boot copy size from boot Media to DRAM.*/
-#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
-#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
-
-#define CONFIG_SPI_BOOTING
-#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
-#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
-
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_PART
-#define CONFIG_PARTITION_UUIDS
-
-
#define CONFIG_IRAM_STACK 0x02050000
-
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
-/* I2C */
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_HARD_I2C
-#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
-#define CONFIG_DRIVER_S3C24X0_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_MAX_I2C_NUM 8
-#define CONFIG_SYS_I2C_SLAVE 0x0
-#define CONFIG_I2C_EDID
-
/* PMIC */
-#define CONFIG_PMIC
-#define CONFIG_PMIC_I2C
-#define CONFIG_PMIC_MAX77686
-
-/* SPI */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_SPI_FLASH
-
-#ifdef CONFIG_SPI_FLASH
-#define CONFIG_EXYNOS_SPI
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
-#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_SPI_FLASH_GIGADEVICE
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-#define CONFIG_SF_DEFAULT_SPEED 50000000
-#define EXYNOS5_SPI_NUM_CONTROLLERS 5
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_MODE SPI_MODE_0
-#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-#define CONFIG_ENV_SPI_BUS 1
-#define CONFIG_ENV_SPI_MAX_HZ 50000000
-#endif
-
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
#define CONFIG_POWER_MAX77686
-/* SPI */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_SPI_FLASH
-
-#ifdef CONFIG_SPI_FLASH
-#define CONFIG_EXYNOS_SPI
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
-#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-#define CONFIG_SF_DEFAULT_SPEED 50000000
-#define EXYNOS5_SPI_NUM_CONTROLLERS 5
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_MODE SPI_MODE_0
-#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-#define CONFIG_ENV_SPI_BUS 1
-#define CONFIG_ENV_SPI_MAX_HZ 50000000
-#endif
-
-/* Ethernet Controllor Driver */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_SMC911X
-#define CONFIG_SMC911X_BASE 0x5000000
-#define CONFIG_SMC911X_16_BIT
-#define CONFIG_ENV_SROM_BANK 1
-#endif /*CONFIG_CMD_NET*/
-
-/* Enable PXE Support */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_PXE
-#define CONFIG_MENU
-#endif
+/* I2C */
+#define CONFIG_MAX_I2C_NUM 8
/* Sound */
#define CONFIG_CMD_SOUND
@@ -335,15 +45,6 @@
#define CONFIG_SOUND_WM8994
#endif
-/* Enable devicetree support */
-#define CONFIG_OF_LIBFDT
-
-/* SHA hashing */
-#define CONFIG_CMD_HASH
-#define CONFIG_HASH_VERIFY
-#define CONFIG_SHA1
-#define CONFIG_SHA256
-
/* Display */
#define CONFIG_LCD
#ifdef CONFIG_LCD
@@ -353,8 +54,4 @@
#define LCD_YRES 1600
#define LCD_BPP LCD_COLOR16
#endif
-
-/* Enable Time Command */
-#define CONFIG_CMD_TIME
-
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_5250_H */
diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
new file mode 100644
index 0000000..e580049
--- /dev/null
+++ b/include/configs/smdk5420.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5420 board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_5420_H
+#define __CONFIG_5420_H
+
+#include <configs/exynos5-dt.h>
+
+#define CONFIG_EXYNOS5420 /* which is in a Exynos5 Family */
+#define CONFIG_SMDK5420 /* which is in a SMDK5420 */
+
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE exynos5420-smdk5420
+
+#define CONFIG_ARCH_DEVICE_TREE exynos5420
+
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_TEXT_BASE 0x23E00000
+
+#define CONFIG_BOARD_REV_GPIO_COUNT 2
+
+/* MACH_TYPE_SMDK5420 macro will be removed once added to mach-types */
+#define MACH_TYPE_SMDK5420 8002 /* Temporary number */
+#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420
+
+/* select serial console configuration */
+#define CONFIG_SERIAL3 /* use SERIAL 3 */
+
+#define CONFIG_SPL_TEXT_BASE 0x02024400
+#define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000"
+
+#define CONFIG_SYS_PROMPT "SMDK5420 # "
+#define CONFIG_IDENT_STRING " for SMDK5420"
+
+#define CONFIG_IRAM_TOP 0x02074000
+/*
+ * Put the initial stack pointer 1KB below this to allow room for the
+ * SPL marker. This value is arbitrary, but gd_t is placed starting here.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800)
+
+#define CONFIG_MAX_I2C_NUM 11
+
+#endif /* __CONFIG_5420_H */
--
1.7.12.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [U-Boot] [PATCH 08/10 V6] Config: Add initial config for SMDK5420
2013-10-29 7:23 ` [U-Boot] [PATCH 08/10 V6] Config: Add initial config " Rajeshwari S Shinde
@ 2013-11-13 3:31 ` Minkyu Kang
0 siblings, 0 replies; 37+ messages in thread
From: Minkyu Kang @ 2013-11-13 3:31 UTC (permalink / raw)
To: u-boot
Dear Rajeshwari S Shinde,
On 29 October 2013 16:23, Rajeshwari S Shinde <rajeshwari.s@samsung.com>wrote:
> Adding initial config for SMDK5420 to build and boot U-Boot
> over Exynos based SMDK5420.
>
> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
> Changes in V2:
> - None
> Changes in V3:
> - None
> Changes in V4:
> - Created a common exynos5-dt.h
> Changes in V5:
> - None
> Changes in V6:
> - None
> include/configs/exynos5-dt.h | 302
> +++++++++++++++++++++++++++++++++++++
> include/configs/exynos5250-dt.h | 319
> +---------------------------------------
> include/configs/smdk5420.h | 49 ++++++
> 3 files changed, 359 insertions(+), 311 deletions(-)
> create mode 100644 include/configs/exynos5-dt.h
> create mode 100644 include/configs/smdk5420.h
>
> diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h
> new file mode 100644
> index 0000000..fa6bb89
> --- /dev/null
> +++ b/include/configs/exynos5-dt.h
> @@ -0,0 +1,302 @@
> +/*
> + * Copyright (C) 2013 Samsung Electronics
> + *
> + * Configuration settings for the SAMSUNG EXYNOS5 board.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/* High Level Configuration Options */
> +#define CONFIG_SAMSUNG /* in a SAMSUNG core */
> +#define CONFIG_S5P /* S5P Family */
> +#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
> +
> +#include <asm/arch/cpu.h> /* get chip and board defs */
> +
> +#define CONFIG_SYS_GENERIC_BOARD
> +#define CONFIG_ARCH_CPU_INIT
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +#define CONFIG_BOARD_COMMON
> +#define CONFIG_ARCH_EARLY_INIT_R
> +
> +/* Enable fdt support for Exynos5250 */
> +#define CONFIG_OF_CONTROL
> +#define CONFIG_OF_SEPARATE
> +
> +/* Allow tracing to be enabled */
> +#define CONFIG_TRACE
> +#define CONFIG_CMD_TRACE
> +#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
> +#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
> +#define CONFIG_TRACE_EARLY
> +#define CONFIG_TRACE_EARLY_ADDR 0x50000000
> +
> +/* Keep L2 Cache Disabled */
> +#define CONFIG_SYS_DCACHE_OFF
> +
> +/* Enable ACE acceleration for SHA1 and SHA256 */
> +#define CONFIG_EXYNOS_ACE_SHA
> +#define CONFIG_SHA_HW_ACCEL
> +
> +
>
please remove blank line.
> +/* input clock of PLL: SMDK5250 has 24MHz input clock */
> +#define CONFIG_SYS_CLK_FREQ 24000000
> +
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_CMDLINE_EDITING
> +
> +
>
please remove blank line.
> +/* Power Down Modes */
> +#define S5P_CHECK_SLEEP 0x00000BAD
> +#define S5P_CHECK_DIDLE 0xBAD00000
> +#define S5P_CHECK_LPA 0xABAD0000
> +
> +/* Offset for inform registers */
> +#define INFORM0_OFFSET 0x800
> +#define INFORM1_OFFSET 0x804
> +#define INFORM2_OFFSET 0x808
> +#define INFORM3_OFFSET 0x80c
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
> +
> +/* select serial console configuration */
> +#define CONFIG_BAUDRATE 115200
> +#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
> +#define CONFIG_SILENT_CONSOLE
> +
> +/* Enable keyboard */
> +#define CONFIG_CROS_EC /* CROS_EC protocol */
> +#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
> +#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */
> +#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */
> +#define CONFIG_CMD_CROS_EC
> +#define CONFIG_KEYBOARD
> +
> +/* Console configuration */
> +#define CONFIG_CONSOLE_MUX
> +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
> +#define EXYNOS_DEVICE_SETTINGS \
> + "stdin=serial,cros-ec-keyb\0" \
> + "stdout=serial,lcd\0" \
> + "stderr=serial,lcd\0"
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + EXYNOS_DEVICE_SETTINGS
> +
> +/* SD/MMC configuration */
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_MMC
> +#define CONFIG_SDHCI
> +#define CONFIG_S5P_SDHCI
> +#define CONFIG_DWMMC
> +#define CONFIG_EXYNOS_DWMMC
> +#define CONFIG_SUPPORT_EMMC_BOOT
> +
> +
>
please remove blank line.
> +#define CONFIG_BOARD_EARLY_INIT_F
> +#define CONFIG_SKIP_LOWLEVEL_INIT
> +
> +/* PWM */
> +#define CONFIG_PWM
> +
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +
> +/* Command definition*/
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_ELF
> +#define CONFIG_CMD_MMC
> +#define CONFIG_CMD_EXT2
> +#define CONFIG_CMD_FAT
> +#define CONFIG_CMD_NET
> +#define CONFIG_CMD_HASH
> +
> +#define CONFIG_BOOTDELAY 3
> +#define CONFIG_ZERO_BOOTDELAY_CHECK
> +
> +/* Thermal Management Unit */
> +#define CONFIG_EXYNOS_TMU
> +#define CONFIG_CMD_DTT
> +#define CONFIG_TMU_CMD_DTT
> +
> +/* USB */
> +#define CONFIG_CMD_USB
> +#define CONFIG_USB_EHCI
> +#define CONFIG_USB_EHCI_EXYNOS
> +#define CONFIG_USB_STORAGE
> +
> +/* USB boot mode */
> +#define CONFIG_USB_BOOTING
> +#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
> +#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
> +#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
> +
> +/* TPM */
> +#define CONFIG_TPM
> +#define CONFIG_CMD_TPM
> +#define CONFIG_TPM_TIS_I2C
> +#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3
> +#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20
> +
> +/* MMC SPL */
> +#define CONFIG_SPL
> +#define COPY_BL2_FNPTR_ADDR 0x02020030
> +
> +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> +
> +/* specific .lds file */
> +#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
> +#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
> +
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
> +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size
> */
> +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
> +#define CONFIG_SYS_MAXARGS 16 /* max number of command
> args */
> +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
> +/* Boot Argument Buffer Size */
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +/* memtest works on */
> +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
> +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
> +
> +#define CONFIG_SYS_HZ 1000
> +
> +#define CONFIG_RD_LVL
> +
> +#define CONFIG_NR_DRAM_BANKS 8
> +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
> +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
> +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
> +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
> +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
> +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 *
> SDRAM_BANK_SIZE))
> +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
> +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 *
> SDRAM_BANK_SIZE))
> +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
> +#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 *
> SDRAM_BANK_SIZE))
> +#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
> +#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 *
> SDRAM_BANK_SIZE))
> +#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
> +#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 *
> SDRAM_BANK_SIZE))
> +#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
> +#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 *
> SDRAM_BANK_SIZE))
> +#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
> +
> +#define CONFIG_SYS_MONITOR_BASE 0x00000000
> +
> +/* FLASH and environment organization */
> +#define CONFIG_SYS_NO_FLASH
> +#undef CONFIG_CMD_IMLS
> +
> +#define CONFIG_SYS_MMC_ENV_DEV 0
> +
> +#define CONFIG_SECURE_BL1_ONLY
> +
> +/* Secure FW size configuration */
> +#ifdef CONFIG_SECURE_BL1_ONLY
> +#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
>
please remove spaces.
+#else
> +#define CONFIG_SEC_FW_SIZE 0
>
ditto.
> +#endif
> +
> +/* Configuration of BL1, BL2, ENV Blocks on mmc */
> +#define CONFIG_RES_BLOCK_SIZE (512)
> +#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for
> BL1*/
> +#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
>
ditto.
> +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
> +
> +#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE +
> CONFIG_SEC_FW_SIZE)
> +#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
> +#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
> +
> +/* U-boot copy size from boot Media to DRAM.*/
> +#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
> +#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
> +
> +#define CONFIG_SPI_BOOTING
> +#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
> +#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE +
> CONFIG_BL1_SIZE)
> +
> +#define CONFIG_DOS_PARTITION
> +#define CONFIG_EFI_PARTITION
> +#define CONFIG_CMD_PART
> +#define CONFIG_PARTITION_UUIDS
> +
> +/* I2C */
> +#define CONFIG_SYS_I2C_INIT_BOARD
> +#define CONFIG_HARD_I2C
> +#define CONFIG_CMD_I2C
> +#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
> +#define CONFIG_DRIVER_S3C24X0_I2C
> +#define CONFIG_I2C_MULTI_BUS
> +#define CONFIG_SYS_I2C_SLAVE 0x0
> +#define CONFIG_I2C_EDID
> +
> +/* SPI */
> +#define CONFIG_ENV_IS_IN_SPI_FLASH
> +#define CONFIG_SPI_FLASH
> +
> +#ifdef CONFIG_SPI_FLASH
> +#define CONFIG_EXYNOS_SPI
> +#define CONFIG_CMD_SF
> +#define CONFIG_CMD_SPI
> +#define CONFIG_SPI_FLASH_WINBOND
> +#define CONFIG_SPI_FLASH_GIGADEVICE
> +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
> +#define CONFIG_SF_DEFAULT_SPEED 50000000
> +#define EXYNOS5_SPI_NUM_CONTROLLERS 5
> +#endif
> +
> +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
> +#define CONFIG_ENV_SPI_MODE SPI_MODE_0
> +#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
> +#define CONFIG_ENV_SPI_BUS 1
> +#define CONFIG_ENV_SPI_MAX_HZ 50000000
> +#endif
> +
> +/* PMIC */
> +#define CONFIG_POWER
> +#define CONFIG_POWER_I2C
> +
> +/* Ethernet Controllor Driver */
> +#ifdef CONFIG_CMD_NET
> +#define CONFIG_SMC911X
> +#define CONFIG_SMC911X_BASE 0x5000000
> +#define CONFIG_SMC911X_16_BIT
> +#define CONFIG_ENV_SROM_BANK 1
> +#endif /*CONFIG_CMD_NET*/
> +
> +/* Enable PXE Support */
> +#ifdef CONFIG_CMD_NET
> +#define CONFIG_CMD_PXE
> +#define CONFIG_MENU
> +#endif
> +
> +/* Enable devicetree support */
> +#define CONFIG_OF_LIBFDT
> +
> +/* SHA hashing */
> +#define CONFIG_CMD_HASH
> +#define CONFIG_HASH_VERIFY
> +#define CONFIG_SHA1
> +#define CONFIG_SHA256
> +
> +/* Enable Time Command */
> +#define CONFIG_CMD_TIME
> +
> +#define CONFIG_CMD_BOOTZ
> +
> +#endif /* __CONFIG_H */
> diff --git a/include/configs/exynos5250-dt.h
> b/include/configs/exynos5250-dt.h
> index 3736ea8..689919d 100644
> --- a/include/configs/exynos5250-dt.h
> +++ b/include/configs/exynos5250-dt.h
> @@ -1,3 +1,4 @@
> +
> /*
> * Copyright (C) 2012 Samsung Electronics
> *
> @@ -6,325 +7,34 @@
> * SPDX-License-Identifier: GPL-2.0+
> */
>
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -/* High Level Configuration Options */
> -#define CONFIG_SAMSUNG /* in a SAMSUNG core */
> -#define CONFIG_S5P /* S5P Family */
> -#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
> -#define CONFIG_EXYNOS5250
> -
> -#include <asm/arch/cpu.h> /* get chip and board defs */
> -
> -#define CONFIG_SYS_GENERIC_BOARD
> -#define CONFIG_ARCH_CPU_INIT
> -#define CONFIG_DISPLAY_CPUINFO
> -#define CONFIG_DISPLAY_BOARDINFO
> -#define CONFIG_BOARD_COMMON
> -#define CONFIG_ARCH_EARLY_INIT_R
> +#ifndef __CONFIG_5250_H
> +#define __CONFIG_5250_H
>
> -/* Enable fdt support for Exynos5250 */
> -#define CONFIG_OF_CONTROL
> -#define CONFIG_OF_SEPARATE
> +#include <configs/exynos5-dt.h>
>
> -/* Allow tracing to be enabled */
> -#define CONFIG_TRACE
> -#define CONFIG_CMD_TRACE
> -#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
> -#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
> -#define CONFIG_TRACE_EARLY
> -#define CONFIG_TRACE_EARLY_ADDR 0x50000000
> -
> -/* Keep L2 Cache Disabled */
> -#define CONFIG_SYS_DCACHE_OFF
> -
> -/* Enable ACE acceleration for SHA1 and SHA256 */
> -#define CONFIG_EXYNOS_ACE_SHA
> -#define CONFIG_SHA_HW_ACCEL
> +#define CONFIG_EXYNOS5250
>
> #define CONFIG_SYS_SDRAM_BASE 0x40000000
> #define CONFIG_SYS_TEXT_BASE 0x43E00000
>
> -/* input clock of PLL: SMDK5250 has 24MHz input clock */
> -#define CONFIG_SYS_CLK_FREQ 24000000
> -
> -#define CONFIG_SETUP_MEMORY_TAGS
> -#define CONFIG_CMDLINE_TAG
> -#define CONFIG_INITRD_TAG
> -#define CONFIG_CMDLINE_EDITING
> -
> /* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
> #define MACH_TYPE_SMDK5250 3774
> #define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
>
> -/* Power Down Modes */
> -#define S5P_CHECK_SLEEP 0x00000BAD
> -#define S5P_CHECK_DIDLE 0xBAD00000
> -#define S5P_CHECK_LPA 0xABAD0000
> -
> -/* Offset for inform registers */
> -#define INFORM0_OFFSET 0x800
> -#define INFORM1_OFFSET 0x804
> -
> -/* Size of malloc() pool */
> -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
> -
> -/* select serial console configuration */
> -#define CONFIG_BAUDRATE 115200
> -#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
> -#define CONFIG_SILENT_CONSOLE
> -
> -/* Enable keyboard */
> -#define CONFIG_CROS_EC /* CROS_EC protocol */
> -#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
> -#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */
> -#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */
> -#define CONFIG_CMD_CROS_EC
> -#define CONFIG_KEYBOARD
> -
> -/* Console configuration */
> -#define CONFIG_CONSOLE_MUX
> -#define CONFIG_SYS_CONSOLE_IS_IN_ENV
> -#define EXYNOS_DEVICE_SETTINGS \
> - "stdin=serial,cros-ec-keyb\0" \
> - "stdout=serial,lcd\0" \
> - "stderr=serial,lcd\0"
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - EXYNOS_DEVICE_SETTINGS
> -
> -/* SD/MMC configuration */
> -#define CONFIG_GENERIC_MMC
> -#define CONFIG_MMC
> -#define CONFIG_SDHCI
> -#define CONFIG_S5P_SDHCI
> -#define CONFIG_DWMMC
> -#define CONFIG_EXYNOS_DWMMC
> -#define CONFIG_SUPPORT_EMMC_BOOT
> -
> -
> -#define CONFIG_BOARD_EARLY_INIT_F
> -#define CONFIG_SKIP_LOWLEVEL_INIT
> -
> -/* PWM */
> -#define CONFIG_PWM
> -
> -/* allow to overwrite serial and ethaddr */
> -#define CONFIG_ENV_OVERWRITE
> -
> -/* Command definition*/
> -#include <config_cmd_default.h>
> -
> -#define CONFIG_CMD_PING
> -#define CONFIG_CMD_ELF
> -#define CONFIG_CMD_MMC
> -#define CONFIG_CMD_EXT2
> -#define CONFIG_CMD_FAT
> -#define CONFIG_CMD_NET
> -#define CONFIG_CMD_HASH
> -
> -#define CONFIG_BOOTDELAY 3
> -#define CONFIG_ZERO_BOOTDELAY_CHECK
> -
> -/* Thermal Management Unit */
> -#define CONFIG_EXYNOS_TMU
> -#define CONFIG_CMD_DTT
> -#define CONFIG_TMU_CMD_DTT
> -
> -/* USB */
> -#define CONFIG_CMD_USB
> -#define CONFIG_USB_EHCI
> -#define CONFIG_USB_EHCI_EXYNOS
> -#define CONFIG_USB_STORAGE
> -
> -/* USB boot mode */
> -#define CONFIG_USB_BOOTING
> -#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
> -#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
> -#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
> -
> -/* TPM */
> -#define CONFIG_TPM
> -#define CONFIG_CMD_TPM
> -#define CONFIG_TPM_TIS_I2C
> -#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3
> -#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20
> -
> -/* MMC SPL */
> -#define CONFIG_SPL
> -#define COPY_BL2_FNPTR_ADDR 0x02020030
> -
> -#define CONFIG_SPL_LIBCOMMON_SUPPORT
> -
> -/* specific .lds file */
> -#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
> #define CONFIG_SPL_TEXT_BASE 0x02023400
> -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
> -
> #define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm
> 40007000"
>
> -/* Miscellaneous configurable options */
> -#define CONFIG_SYS_LONGHELP /* undef to save memory */
> -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
> #define CONFIG_SYS_PROMPT "SMDK5250 # "
> -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size
> */
> -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
> -#define CONFIG_SYS_MAXARGS 16 /* max number of command
> args */
> -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
> -/* Boot Argument Buffer Size */
> -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> -/* memtest works on */
> -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
> -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
> -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
> -
> -#define CONFIG_SYS_HZ 1000
> -
> -#define CONFIG_RD_LVL
> -
> -#define CONFIG_NR_DRAM_BANKS 8
> -#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
> -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
> -#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
> -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
> -#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
> -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 *
> SDRAM_BANK_SIZE))
> -#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
> -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 *
> SDRAM_BANK_SIZE))
> -#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
> -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 *
> SDRAM_BANK_SIZE))
> -#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
> -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 *
> SDRAM_BANK_SIZE))
> -#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
> -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 *
> SDRAM_BANK_SIZE))
> -#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
> -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 *
> SDRAM_BANK_SIZE))
> -#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
> -
> -#define CONFIG_SYS_MONITOR_BASE 0x00000000
> -
> -/* FLASH and environment organization */
> -#define CONFIG_SYS_NO_FLASH
> -#undef CONFIG_CMD_IMLS
> #define CONFIG_IDENT_STRING " for SMDK5250"
>
> -#define CONFIG_SYS_MMC_ENV_DEV 0
> -
> -#define CONFIG_SECURE_BL1_ONLY
> -
> -/* Secure FW size configuration */
> -#ifdef CONFIG_SECURE_BL1_ONLY
> -#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
> -#else
> -#define CONFIG_SEC_FW_SIZE 0
> -#endif
> -
> -/* Configuration of BL1, BL2, ENV Blocks on mmc */
> -#define CONFIG_RES_BLOCK_SIZE (512)
> -#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for
> BL1*/
> -#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
> -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
> -
> -#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE +
> CONFIG_SEC_FW_SIZE)
> -#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
> -#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
> -
> -/* U-boot copy size from boot Media to DRAM.*/
> -#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
> -#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
> -
> -#define CONFIG_SPI_BOOTING
> -#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
> -#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE +
> CONFIG_BL1_SIZE)
> -
> -#define CONFIG_DOS_PARTITION
> -#define CONFIG_EFI_PARTITION
> -#define CONFIG_CMD_PART
> -#define CONFIG_PARTITION_UUIDS
> -
> -
> #define CONFIG_IRAM_STACK 0x02050000
> -
> #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
>
> -/* I2C */
> -#define CONFIG_SYS_I2C_INIT_BOARD
> -#define CONFIG_HARD_I2C
> -#define CONFIG_CMD_I2C
> -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
> -#define CONFIG_DRIVER_S3C24X0_I2C
> -#define CONFIG_I2C_MULTI_BUS
> -#define CONFIG_MAX_I2C_NUM 8
> -#define CONFIG_SYS_I2C_SLAVE 0x0
> -#define CONFIG_I2C_EDID
> -
> /* PMIC */
> -#define CONFIG_PMIC
> -#define CONFIG_PMIC_I2C
> -#define CONFIG_PMIC_MAX77686
> -
> -/* SPI */
> -#define CONFIG_ENV_IS_IN_SPI_FLASH
> -#define CONFIG_SPI_FLASH
> -
> -#ifdef CONFIG_SPI_FLASH
> -#define CONFIG_EXYNOS_SPI
> -#define CONFIG_CMD_SF
> -#define CONFIG_CMD_SPI
> -#define CONFIG_SPI_FLASH_WINBOND
> -#define CONFIG_SPI_FLASH_GIGADEVICE
> -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
> -#define CONFIG_SF_DEFAULT_SPEED 50000000
> -#define EXYNOS5_SPI_NUM_CONTROLLERS 5
> -#endif
> -
> -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
> -#define CONFIG_ENV_SPI_MODE SPI_MODE_0
> -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
> -#define CONFIG_ENV_SPI_BUS 1
> -#define CONFIG_ENV_SPI_MAX_HZ 50000000
> -#endif
> -
> -/* PMIC */
> -#define CONFIG_POWER
> -#define CONFIG_POWER_I2C
> #define CONFIG_POWER_MAX77686
>
> -/* SPI */
> -#define CONFIG_ENV_IS_IN_SPI_FLASH
> -#define CONFIG_SPI_FLASH
> -
> -#ifdef CONFIG_SPI_FLASH
> -#define CONFIG_EXYNOS_SPI
> -#define CONFIG_CMD_SF
> -#define CONFIG_CMD_SPI
> -#define CONFIG_SPI_FLASH_WINBOND
> -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
> -#define CONFIG_SF_DEFAULT_SPEED 50000000
> -#define EXYNOS5_SPI_NUM_CONTROLLERS 5
> -#endif
> -
> -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
> -#define CONFIG_ENV_SPI_MODE SPI_MODE_0
> -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
> -#define CONFIG_ENV_SPI_BUS 1
> -#define CONFIG_ENV_SPI_MAX_HZ 50000000
> -#endif
> -
> -/* Ethernet Controllor Driver */
> -#ifdef CONFIG_CMD_NET
> -#define CONFIG_SMC911X
> -#define CONFIG_SMC911X_BASE 0x5000000
> -#define CONFIG_SMC911X_16_BIT
> -#define CONFIG_ENV_SROM_BANK 1
> -#endif /*CONFIG_CMD_NET*/
> -
> -/* Enable PXE Support */
> -#ifdef CONFIG_CMD_NET
> -#define CONFIG_CMD_PXE
> -#define CONFIG_MENU
> -#endif
> +/* I2C */
> +#define CONFIG_MAX_I2C_NUM 8
>
> /* Sound */
> #define CONFIG_CMD_SOUND
> @@ -335,15 +45,6 @@
> #define CONFIG_SOUND_WM8994
> #endif
>
> -/* Enable devicetree support */
> -#define CONFIG_OF_LIBFDT
> -
> -/* SHA hashing */
> -#define CONFIG_CMD_HASH
> -#define CONFIG_HASH_VERIFY
> -#define CONFIG_SHA1
> -#define CONFIG_SHA256
> -
> /* Display */
> #define CONFIG_LCD
> #ifdef CONFIG_LCD
> @@ -353,8 +54,4 @@
> #define LCD_YRES 1600
> #define LCD_BPP LCD_COLOR16
> #endif
> -
> -/* Enable Time Command */
> -#define CONFIG_CMD_TIME
> -
> -#endif /* __CONFIG_H */
> +#endif /* __CONFIG_5250_H */
> diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
> new file mode 100644
> index 0000000..e580049
> --- /dev/null
> +++ b/include/configs/smdk5420.h
> @@ -0,0 +1,49 @@
> +/*
> + * Copyright (C) 2013 Samsung Electronics
> + *
> + * Configuration settings for the SAMSUNG EXYNOS5420 board.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __CONFIG_5420_H
> +#define __CONFIG_5420_H
> +
> +#include <configs/exynos5-dt.h>
> +
> +#define CONFIG_EXYNOS5420 /* which is in a Exynos5 Family */
> +#define CONFIG_SMDK5420 /* which is in a SMDK5420
> */
> +
> +#undef CONFIG_DEFAULT_DEVICE_TREE
> +#define CONFIG_DEFAULT_DEVICE_TREE exynos5420-smdk5420
> +
> +#define CONFIG_ARCH_DEVICE_TREE exynos5420
> +
> +#define CONFIG_SYS_SDRAM_BASE 0x20000000
> +#define CONFIG_SYS_TEXT_BASE 0x23E00000
> +
> +#define CONFIG_BOARD_REV_GPIO_COUNT 2
> +
> +/* MACH_TYPE_SMDK5420 macro will be removed once added to mach-types */
> +#define MACH_TYPE_SMDK5420 8002 /* Temporary number */
> +#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420
> +
> +/* select serial console configuration */
> +#define CONFIG_SERIAL3 /* use SERIAL 3 */
> +
> +#define CONFIG_SPL_TEXT_BASE 0x02024400
> +#define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm
> 20007000"
> +
> +#define CONFIG_SYS_PROMPT "SMDK5420 # "
> +#define CONFIG_IDENT_STRING " for SMDK5420"
> +
> +#define CONFIG_IRAM_TOP 0x02074000
> +/*
> + * Put the initial stack pointer 1KB below this to allow room for the
> + * SPL marker. This value is arbitrary, but gd_t is placed starting here.
> + */
> +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800)
> +
> +#define CONFIG_MAX_I2C_NUM 11
> +
> +#endif /* __CONFIG_5420_H */
> --
> 1.7.12.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
Thanks,
Minkyu Kang.
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 37+ messages in thread
* [U-Boot] [PATCH 09/10 V6] SPL: EXYNOS: Prepare for variable size SPL support
2013-10-29 7:23 [U-Boot] [PATCH 00/10 V6] EXYNOS5420: Add SMDK5420 board support Rajeshwari S Shinde
` (7 preceding siblings ...)
2013-10-29 7:23 ` [U-Boot] [PATCH 08/10 V6] Config: Add initial config " Rajeshwari S Shinde
@ 2013-10-29 7:23 ` Rajeshwari S Shinde
2013-10-29 7:23 ` [U-Boot] [PATCH 10/10 V6] DWMMC: SMDK5420: Disable SMU for eMMC Rajeshwari S Shinde
2013-10-31 8:42 ` [U-Boot] [PATCH 00/10 V6] EXYNOS5420: Add SMDK5420 board support Rajeshwari Birje
10 siblings, 0 replies; 37+ messages in thread
From: Rajeshwari S Shinde @ 2013-10-29 7:23 UTC (permalink / raw)
To: u-boot
When variable size SPL is used, the BL1 expects the SPL to be
encapsulated differently: instead of putting the checksum at a fixed
offset in the SPL blob, prepend the blob with a header including the
size and the checksum.
The enhancements include
- adding a command line option, '--vs' to indicate the need for the
variable size encapsulation
- padding the fixed size encapsulated blob with 0xff instead of random
memory contents
- do not silently truncate the input file, report error instead
- no need to explicitly closing files/freeing memory, this all happens
on exit; removing cleanups it makes code clearer
- profuse commenting
- modify Makefile to allow enabling the new feature per board
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Created a common exynos5-dt.h
Changes in V5:
- None
Changes in V6:
- None.
include/configs/smdk5420.h | 7 ++
spl/Makefile | 7 +-
tools/mkexynosspl.c | 167 +++++++++++++++++++++++++++++++++------------
3 files changed, 137 insertions(+), 44 deletions(-)
diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
index e580049..447f8e5 100644
--- a/include/configs/smdk5420.h
+++ b/include/configs/smdk5420.h
@@ -19,6 +19,8 @@
#define CONFIG_ARCH_DEVICE_TREE exynos5420
+#define CONFIG_VAR_SIZE_SPL
+
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_TEXT_BASE 0x23E00000
@@ -31,7 +33,12 @@
/* select serial console configuration */
#define CONFIG_SERIAL3 /* use SERIAL 3 */
+#ifdef CONFIG_VAR_SIZE_SPL
+#define CONFIG_SPL_TEXT_BASE 0x02024410
+#else
#define CONFIG_SPL_TEXT_BASE 0x02024400
+#endif
+
#define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000"
#define CONFIG_SYS_PROMPT "SMDK5420 # "
diff --git a/spl/Makefile b/spl/Makefile
index b366ac2..d5f6ae8 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -184,8 +184,13 @@ endif
all: $(ALL-y)
ifdef CONFIG_SAMSUNG
+ifdef CONFIG_VAR_SIZE_SPL
+VAR_SIZE_PARAM = --vs
+else
+VAR_SIZE_PARAM =
+endif
$(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin
- $(OBJTREE)/tools/mk$(BOARD)spl \
+ $(OBJTREE)/tools/mk$(BOARD)spl $(VAR_SIZE_PARAM) \
$(obj)u-boot-spl.bin $(obj)$(BOARD)-spl.bin
endif
diff --git a/tools/mkexynosspl.c b/tools/mkexynosspl.c
index ef685b7..32b786c 100644
--- a/tools/mkexynosspl.c
+++ b/tools/mkexynosspl.c
@@ -14,93 +14,174 @@
#include <compiler.h>
#define CHECKSUM_OFFSET (14*1024-4)
-#define BUFSIZE (14*1024)
#define FILE_PERM (S_IRUSR | S_IWUSR | S_IRGRP \
| S_IWGRP | S_IROTH | S_IWOTH)
/*
-* Requirement:
-* IROM code reads first 14K bytes from boot device.
-* It then calculates the checksum of 14K-4 bytes and compare with data at
-* 14K-4 offset.
-*
-* This function takes two filenames:
-* IN "u-boot-spl.bin" and
-* OUT "$(BOARD)-spl.bin as filenames.
-* It reads the "u-boot-spl.bin" in 16K buffer.
-* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer.
-* It writes the buffer to "$(BOARD)-spl.bin" file.
-*/
+ * Requirement for the fixed size SPL header:
+ * IROM code reads first (CHECKSUM_OFFSET + 4) bytes from boot device. It then
+ * calculates the checksum of CHECKSUM_OFFSET bytes and compares with data at
+ * CHECKSUM_OFFSET location.
+ *
+ * Requirement for the variable size SPL header:
+
+ * IROM code reads the below header to find out the size of the blob (total
+ * size, header size included) and its checksum. Then it reads the rest of the
+ * blob [i.e size - sizeof(struct var_size_header) bytes], calculates the
+ * checksum and compares it with value read from the header.
+ */
+struct var_size_header {
+ uint32_t spl_size;
+ uint32_t spl_checksum;
+ uint32_t reserved[2];
+};
+
+static const char *prog_name;
+
+static void write_to_file(int ofd, void *buffer, int size)
+{
+ if (write(ofd, buffer, size) == size)
+ return;
+
+ fprintf(stderr, "%s: Failed to write to output file: %s\n",
+ prog_name, strerror(errno));
+ exit(EXIT_FAILURE);
+}
+/*
+ * The argv is expected to include one optional parameter and two filenames:
+ * [--vs] IN OUT
+ *
+ * --vs - turns on the variable size SPL mode
+ * IN - the u-boot SPL binary, usually u-boot-spl.bin
+ * OUT - the prepared SPL blob, usually ${BOARD}-spl.bin
+ *
+ * This utility first reads the "u-boot-spl.bin" into a buffer. In case of
+ * fixed size SPL the buffer size is exactly CHECKSUM_OFFSET (such that
+ * smaller u-boot-spl.bin gets padded with 0xff bytes, the larger than limit
+ * u-boot-spl.bin causes an error). For variable size SPL the buffer size is
+ * eqaul to size of the IN file.
+ *
+ * Then it calculates checksum of the buffer by just summing up all bytes.
+ * Then
+ *
+ * - for fixed size SPL the buffer is written into the output file and the
+ * checksum is appended to the file in little endian format, which results
+ * in checksum added exactly at CHECKSUM_OFFSET.
+ *
+ * - for variable size SPL the checksum and file size are stored in the
+ * var_size_header structure (again, in little endian format) and the
+ * structure is written into the output file. Then the buffer is written
+ * into the output file.
+ */
int main(int argc, char **argv)
{
- unsigned char buffer[BUFSIZE];
+ unsigned char *buffer;
int i, ifd, ofd;
uint32_t checksum = 0;
off_t len;
- ssize_t count;
+ int var_size_flag, read_size, count;
struct stat stat;
-
- if (argc != 3) {
- fprintf(stderr, "Usage: %s <infile> <outfile>\n", argv[0]);
+ const int if_index = argc - 2; /* Input file name index in argv. */
+ const int of_index = argc - 1; /* Output file name index in argv. */
+
+ /* Strip path off the program name. */
+ prog_name = strrchr(argv[0], '/');
+ if (prog_name)
+ prog_name++;
+ else
+ prog_name = argv[0];
+
+ if ((argc < 3) ||
+ (argc > 4) ||
+ ((argc == 4) && strcmp(argv[1], "--vs"))) {
+ fprintf(stderr, "Usage: %s [--vs] <infile> <outfile>\n",
+ prog_name);
exit(EXIT_FAILURE);
}
- ifd = open(argv[1], O_RDONLY);
+ /* four args mean variable size SPL wrapper is required */
+ var_size_flag = (argc == 4);
+
+ ifd = open(argv[if_index], O_RDONLY);
if (ifd < 0) {
fprintf(stderr, "%s: Can't open %s: %s\n",
- argv[0], argv[1], strerror(errno));
+ prog_name, argv[if_index], strerror(errno));
exit(EXIT_FAILURE);
}
- ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM);
+ ofd = open(argv[of_index], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM);
if (ifd < 0) {
fprintf(stderr, "%s: Can't open %s: %s\n",
- argv[0], argv[2], strerror(errno));
- close(ifd);
+ prog_name, argv[of_index], strerror(errno));
exit(EXIT_FAILURE);
}
if (fstat(ifd, &stat)) {
fprintf(stderr, "%s: Unable to get size of %s: %s\n",
- argv[0], argv[1], strerror(errno));
- close(ifd);
- close(ofd);
+ prog_name, argv[if_index], strerror(errno));
exit(EXIT_FAILURE);
}
len = stat.st_size;
- count = (len < CHECKSUM_OFFSET) ? len : CHECKSUM_OFFSET;
-
- if (read(ifd, buffer, count) != count) {
- fprintf(stderr, "%s: Can't read %s: %s\n",
- argv[0], argv[1], strerror(errno));
+ if (var_size_flag) {
+ read_size = len;
+ count = len;
+ } else {
+ if (len > CHECKSUM_OFFSET) {
+ fprintf(stderr,
+ "%s: %s is too big (exceeds %d bytes)\n",
+ prog_name, argv[if_index], CHECKSUM_OFFSET);
+ exit(EXIT_FAILURE);
+ }
+ count = CHECKSUM_OFFSET;
+ read_size = len;
+ }
- close(ifd);
- close(ofd);
+ buffer = malloc(count);
+ if (!buffer) {
+ fprintf(stderr,
+ "%s: Failed to allocate %d bytes to store %s\n",
+ prog_name, count, argv[if_index]);
+ exit(EXIT_FAILURE);
+ }
+ if (read(ifd, buffer, read_size) != read_size) {
+ fprintf(stderr, "%s: Can't read %s: %s\n",
+ prog_name, argv[if_index], strerror(errno));
exit(EXIT_FAILURE);
}
- for (i = 0, checksum = 0; i < CHECKSUM_OFFSET; i++)
- checksum += buffer[i];
+ /* Pad if needed with 0xff to make flashing faster. */
+ if (read_size < count)
+ memset((char *)buffer + read_size, 0xff, count - read_size);
+ for (i = 0, checksum = 0; i < count; i++)
+ checksum += buffer[i];
checksum = cpu_to_le32(checksum);
- memcpy(&buffer[CHECKSUM_OFFSET], &checksum, sizeof(checksum));
-
- if (write(ofd, buffer, BUFSIZE) != BUFSIZE) {
- fprintf(stderr, "%s: Can't write %s: %s\n",
- argv[0], argv[2], strerror(errno));
+ if (var_size_flag) {
+ /* Prepare and write out the variable size SPL header. */
+ struct var_size_header vsh;
+ uint32_t spl_size;
- close(ifd);
- close(ofd);
+ memset(&vsh, 0, sizeof(vsh));
+ memcpy(&vsh.spl_checksum, &checksum, sizeof(checksum));
- exit(EXIT_FAILURE);
+ spl_size = cpu_to_le32(count + sizeof(struct var_size_header));
+ memcpy(&vsh.spl_size, &spl_size, sizeof(spl_size));
+ write_to_file(ofd, &vsh, sizeof(vsh));
}
+ write_to_file(ofd, buffer, count);
+
+ /* For fixed size SPL checksum is appended in the end. */
+ if (!var_size_flag)
+ write_to_file(ofd, &checksum, sizeof(checksum));
+
close(ifd);
close(ofd);
+ free(buffer);
return EXIT_SUCCESS;
}
--
1.7.12.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [U-Boot] [PATCH 10/10 V6] DWMMC: SMDK5420: Disable SMU for eMMC
2013-10-29 7:23 [U-Boot] [PATCH 00/10 V6] EXYNOS5420: Add SMDK5420 board support Rajeshwari S Shinde
` (8 preceding siblings ...)
2013-10-29 7:23 ` [U-Boot] [PATCH 09/10 V6] SPL: EXYNOS: Prepare for variable size SPL support Rajeshwari S Shinde
@ 2013-10-29 7:23 ` Rajeshwari S Shinde
2013-10-29 10:24 ` Jaehoon Chung
2013-10-31 7:50 ` Pantelis Antoniou
2013-10-31 8:42 ` [U-Boot] [PATCH 00/10 V6] EXYNOS5420: Add SMDK5420 board support Rajeshwari Birje
10 siblings, 2 replies; 37+ messages in thread
From: Rajeshwari S Shinde @ 2013-10-29 7:23 UTC (permalink / raw)
To: u-boot
SMDK5420 has a new Security Management Unit added
for dwmmc driver, hence, configuring the control
registers to support booting via eMMC.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in V3:
- New patch.
Changes in V4:
Added flag to dissble SMU
Changes in V5:
- None
Changes in V6:
- Moved the SMU definitions to arch/arm dwmmc.h
arch/arm/include/asm/arch-exynos/dwmmc.h | 13 +++++++++++++
drivers/mmc/dw_mmc.c | 11 +++++++++++
drivers/mmc/exynos_dw_mmc.c | 3 +++
include/dwmmc.h | 3 +++
4 files changed, 30 insertions(+)
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h
index b9eca76..d1c5d4f 100644
--- a/arch/arm/include/asm/arch-exynos/dwmmc.h
+++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
@@ -14,6 +14,19 @@
#define DWMCI_SET_DRV_CLK(x) ((x) << 16)
#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
+#define EMMCP_MPSBEGIN0 0x1200
+#define EMMCP_SEND0 0x1204
+#define EMMCP_CTRL0 0x120C
+
+#define MPSCTRL_SECURE_READ_BIT (0x1<<7)
+#define MPSCTRL_SECURE_WRITE_BIT (0x1<<6)
+#define MPSCTRL_NON_SECURE_READ_BIT (0x1<<5)
+#define MPSCTRL_NON_SECURE_WRITE_BIT (0x1<<4)
+#define MPSCTRL_USE_FUSE_KEY (0x1<<3)
+#define MPSCTRL_ECB_MODE (0x1<<2)
+#define MPSCTRL_ENCRYPTION (0x1<<1)
+#define MPSCTRL_VALID (0x1<<0)
+
#ifdef CONFIG_OF_CONTROL
int exynos_dwmmc_init(const void *blob);
#endif
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 9a803a0..a3506d4 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -11,6 +11,7 @@
#include <mmc.h>
#include <dwmmc.h>
#include <asm-generic/errno.h>
+#include <asm/arch/dwmmc.h>
#define PAGE_SIZE 4096
@@ -301,6 +302,16 @@ static int dwmci_init(struct mmc *mmc)
struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
u32 fifo_size;
+ if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
+ dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
+ dwmci_writel(host, EMMCP_SEND0, 0);
+ dwmci_writel(host, EMMCP_CTRL0,
+ MPSCTRL_SECURE_READ_BIT |
+ MPSCTRL_SECURE_WRITE_BIT |
+ MPSCTRL_NON_SECURE_READ_BIT |
+ MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
+ }
+
dwmci_writel(host, DWMCI_PWREN, 1);
if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 4ef9fec..f7439a0 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -62,6 +62,9 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
host->name = "EXYNOS DWMMC";
host->ioaddr = (void *)regbase;
host->buswidth = bus_width;
+#ifdef CONFIG_EXYNOS5420
+ host->quirks = DWMCI_QUIRK_DISABLE_SMU;
+#endif
if (clksel) {
host->clksel_val = clksel;
diff --git a/include/dwmmc.h b/include/dwmmc.h
index 08ced0b..6263140 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -123,6 +123,9 @@
#define DWMCI_BMOD_IDMAC_FB (1 << 1)
#define DWMCI_BMOD_IDMAC_EN (1 << 7)
+/* quirks */
+#define DWMCI_QUIRK_DISABLE_SMU (1 << 0)
+
struct dwmci_host {
char *name;
void *ioaddr;
--
1.7.12.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [U-Boot] [PATCH 10/10 V6] DWMMC: SMDK5420: Disable SMU for eMMC
2013-10-29 7:23 ` [U-Boot] [PATCH 10/10 V6] DWMMC: SMDK5420: Disable SMU for eMMC Rajeshwari S Shinde
@ 2013-10-29 10:24 ` Jaehoon Chung
2013-10-31 7:50 ` Pantelis Antoniou
1 sibling, 0 replies; 37+ messages in thread
From: Jaehoon Chung @ 2013-10-29 10:24 UTC (permalink / raw)
To: u-boot
Looks good to me.
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
On 10/29/2013 04:23 PM, Rajeshwari S Shinde wrote:
> SMDK5420 has a new Security Management Unit added
> for dwmmc driver, hence, configuring the control
> registers to support booting via eMMC.
>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
> Changes in V3:
> - New patch.
> Changes in V4:
> Added flag to dissble SMU
> Changes in V5:
> - None
> Changes in V6:
> - Moved the SMU definitions to arch/arm dwmmc.h
> arch/arm/include/asm/arch-exynos/dwmmc.h | 13 +++++++++++++
> drivers/mmc/dw_mmc.c | 11 +++++++++++
> drivers/mmc/exynos_dw_mmc.c | 3 +++
> include/dwmmc.h | 3 +++
> 4 files changed, 30 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h
> index b9eca76..d1c5d4f 100644
> --- a/arch/arm/include/asm/arch-exynos/dwmmc.h
> +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
> @@ -14,6 +14,19 @@
> #define DWMCI_SET_DRV_CLK(x) ((x) << 16)
> #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
>
> +#define EMMCP_MPSBEGIN0 0x1200
> +#define EMMCP_SEND0 0x1204
> +#define EMMCP_CTRL0 0x120C
> +
> +#define MPSCTRL_SECURE_READ_BIT (0x1<<7)
> +#define MPSCTRL_SECURE_WRITE_BIT (0x1<<6)
> +#define MPSCTRL_NON_SECURE_READ_BIT (0x1<<5)
> +#define MPSCTRL_NON_SECURE_WRITE_BIT (0x1<<4)
> +#define MPSCTRL_USE_FUSE_KEY (0x1<<3)
> +#define MPSCTRL_ECB_MODE (0x1<<2)
> +#define MPSCTRL_ENCRYPTION (0x1<<1)
> +#define MPSCTRL_VALID (0x1<<0)
> +
> #ifdef CONFIG_OF_CONTROL
> int exynos_dwmmc_init(const void *blob);
> #endif
> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
> index 9a803a0..a3506d4 100644
> --- a/drivers/mmc/dw_mmc.c
> +++ b/drivers/mmc/dw_mmc.c
> @@ -11,6 +11,7 @@
> #include <mmc.h>
> #include <dwmmc.h>
> #include <asm-generic/errno.h>
> +#include <asm/arch/dwmmc.h>
>
> #define PAGE_SIZE 4096
>
> @@ -301,6 +302,16 @@ static int dwmci_init(struct mmc *mmc)
> struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
> u32 fifo_size;
>
> + if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
> + dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
> + dwmci_writel(host, EMMCP_SEND0, 0);
> + dwmci_writel(host, EMMCP_CTRL0,
> + MPSCTRL_SECURE_READ_BIT |
> + MPSCTRL_SECURE_WRITE_BIT |
> + MPSCTRL_NON_SECURE_READ_BIT |
> + MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
> + }
> +
> dwmci_writel(host, DWMCI_PWREN, 1);
>
> if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
> index 4ef9fec..f7439a0 100644
> --- a/drivers/mmc/exynos_dw_mmc.c
> +++ b/drivers/mmc/exynos_dw_mmc.c
> @@ -62,6 +62,9 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
> host->name = "EXYNOS DWMMC";
> host->ioaddr = (void *)regbase;
> host->buswidth = bus_width;
> +#ifdef CONFIG_EXYNOS5420
> + host->quirks = DWMCI_QUIRK_DISABLE_SMU;
> +#endif
>
> if (clksel) {
> host->clksel_val = clksel;
> diff --git a/include/dwmmc.h b/include/dwmmc.h
> index 08ced0b..6263140 100644
> --- a/include/dwmmc.h
> +++ b/include/dwmmc.h
> @@ -123,6 +123,9 @@
> #define DWMCI_BMOD_IDMAC_FB (1 << 1)
> #define DWMCI_BMOD_IDMAC_EN (1 << 7)
>
> +/* quirks */
> +#define DWMCI_QUIRK_DISABLE_SMU (1 << 0)
> +
> struct dwmci_host {
> char *name;
> void *ioaddr;
>
^ permalink raw reply [flat|nested] 37+ messages in thread* [U-Boot] [PATCH 10/10 V6] DWMMC: SMDK5420: Disable SMU for eMMC
2013-10-29 7:23 ` [U-Boot] [PATCH 10/10 V6] DWMMC: SMDK5420: Disable SMU for eMMC Rajeshwari S Shinde
2013-10-29 10:24 ` Jaehoon Chung
@ 2013-10-31 7:50 ` Pantelis Antoniou
1 sibling, 0 replies; 37+ messages in thread
From: Pantelis Antoniou @ 2013-10-31 7:50 UTC (permalink / raw)
To: u-boot
Hi Rajeshwari,
On Oct 29, 2013, at 9:23 AM, Rajeshwari S Shinde wrote:
> SMDK5420 has a new Security Management Unit added
> for dwmmc driver, hence, configuring the control
> registers to support booting via eMMC.
>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
> Changes in V3:
> - New patch.
> Changes in V4:
> Added flag to dissble SMU
> Changes in V5:
> - None
> Changes in V6:
> - Moved the SMU definitions to arch/arm dwmmc.h
> arch/arm/include/asm/arch-exynos/dwmmc.h | 13 +++++++++++++
> drivers/mmc/dw_mmc.c | 11 +++++++++++
> drivers/mmc/exynos_dw_mmc.c | 3 +++
> include/dwmmc.h | 3 +++
> 4 files changed, 30 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h
> index b9eca76..d1c5d4f 100644
> --- a/arch/arm/include/asm/arch-exynos/dwmmc.h
> +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
> @@ -14,6 +14,19 @@
> #define DWMCI_SET_DRV_CLK(x) ((x) << 16)
> #define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
>
> +#define EMMCP_MPSBEGIN0 0x1200
> +#define EMMCP_SEND0 0x1204
> +#define EMMCP_CTRL0 0x120C
> +
> +#define MPSCTRL_SECURE_READ_BIT (0x1<<7)
> +#define MPSCTRL_SECURE_WRITE_BIT (0x1<<6)
> +#define MPSCTRL_NON_SECURE_READ_BIT (0x1<<5)
> +#define MPSCTRL_NON_SECURE_WRITE_BIT (0x1<<4)
> +#define MPSCTRL_USE_FUSE_KEY (0x1<<3)
> +#define MPSCTRL_ECB_MODE (0x1<<2)
> +#define MPSCTRL_ENCRYPTION (0x1<<1)
> +#define MPSCTRL_VALID (0x1<<0)
> +
> #ifdef CONFIG_OF_CONTROL
> int exynos_dwmmc_init(const void *blob);
> #endif
> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
> index 9a803a0..a3506d4 100644
> --- a/drivers/mmc/dw_mmc.c
> +++ b/drivers/mmc/dw_mmc.c
> @@ -11,6 +11,7 @@
> #include <mmc.h>
> #include <dwmmc.h>
> #include <asm-generic/errno.h>
> +#include <asm/arch/dwmmc.h>
>
> #define PAGE_SIZE 4096
>
> @@ -301,6 +302,16 @@ static int dwmci_init(struct mmc *mmc)
> struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
> u32 fifo_size;
>
> + if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
> + dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
> + dwmci_writel(host, EMMCP_SEND0, 0);
> + dwmci_writel(host, EMMCP_CTRL0,
> + MPSCTRL_SECURE_READ_BIT |
> + MPSCTRL_SECURE_WRITE_BIT |
> + MPSCTRL_NON_SECURE_READ_BIT |
> + MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
> + }
> +
> dwmci_writel(host, DWMCI_PWREN, 1);
>
> if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
> index 4ef9fec..f7439a0 100644
> --- a/drivers/mmc/exynos_dw_mmc.c
> +++ b/drivers/mmc/exynos_dw_mmc.c
> @@ -62,6 +62,9 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
> host->name = "EXYNOS DWMMC";
> host->ioaddr = (void *)regbase;
> host->buswidth = bus_width;
> +#ifdef CONFIG_EXYNOS5420
> + host->quirks = DWMCI_QUIRK_DISABLE_SMU;
> +#endif
>
> if (clksel) {
> host->clksel_val = clksel;
> diff --git a/include/dwmmc.h b/include/dwmmc.h
> index 08ced0b..6263140 100644
> --- a/include/dwmmc.h
> +++ b/include/dwmmc.h
> @@ -123,6 +123,9 @@
> #define DWMCI_BMOD_IDMAC_FB (1 << 1)
> #define DWMCI_BMOD_IDMAC_EN (1 << 7)
>
> +/* quirks */
> +#define DWMCI_QUIRK_DISABLE_SMU (1 << 0)
> +
> struct dwmci_host {
> char *name;
> void *ioaddr;
> --
> 1.7.12.4
>
Applied, thanks
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [U-Boot] [PATCH 00/10 V6] EXYNOS5420: Add SMDK5420 board support
2013-10-29 7:23 [U-Boot] [PATCH 00/10 V6] EXYNOS5420: Add SMDK5420 board support Rajeshwari S Shinde
` (9 preceding siblings ...)
2013-10-29 7:23 ` [U-Boot] [PATCH 10/10 V6] DWMMC: SMDK5420: Disable SMU for eMMC Rajeshwari S Shinde
@ 2013-10-31 8:42 ` Rajeshwari Birje
2013-11-06 11:42 ` Rajeshwari Birje
10 siblings, 1 reply; 37+ messages in thread
From: Rajeshwari Birje @ 2013-10-31 8:42 UTC (permalink / raw)
To: u-boot
Hi Minkyu Kang,
Kindly do review the patch set and do let me know if any review comments.
Pantelis Antoniou has merged the patch 10 (DWMMC: SMDK5420: Disable
SMU for eMMC) into mmc tree.
Regards,
Rajeshwari Shinde.
On Tue, Oct 29, 2013 at 12:53 PM, Rajeshwari S Shinde
<rajeshwari.s@samsung.com> wrote:
> This patch adds basic board support for SMDK5420 board.
> These patches are tested for booting fine on EVT1 SMDK5420.
>
> Changes in V2:
> - Corrected a compilation issue for SMDK5420.
>
> Changes in V3:
> - Add patch to support variable size SPL support
> - Add patch to disable SMU for eMMC.
>
> Changes in V4:
> - Added check for MAX77686 pmic compilation.
> - Added correct calculation of gpio based addresses.
> - Rebased on the latest u-boot code.
> - Removed patches for UART and TZPC changes as
> they were not needed.
> - Added flag to disable SMU for eMMC.
>
> Changes in V5:
> - Moved functions board_mmc_init and board_eth_init
> to common/board.c in case of device tree support.
>
> Changes in V6:
> - Rebased on the latest mainline branch.
> - Moved the definitions for SMU to arch/arm dwmmc.h
>
> Rajeshwari S Shinde (10):
> EXYNOS5: Create a common board file
> Exynos5420: Add base addresses for 5420
> Exynos5420: Add clock initialization for 5420
> Exynos5420: Add DDR3 initialization for 5420
> Exynos5420: Add support for 5420 in pinmux and gpio
> Exynos5420: Add base patch for SMDK5420
> DTS: Add dts support for SMDK5420
> Config: Add initial config for SMDK5420
> SPL: EXYNOS: Prepare for variable size SPL support
> DWMMC: SMDK5420: Disable SMU for eMMC
>
> arch/arm/cpu/armv7/exynos/clock.c | 270 ++++++++-
> arch/arm/cpu/armv7/exynos/clock_init.h | 17 +
> arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 352 +++++++++++-
> arch/arm/cpu/armv7/exynos/dmc_common.c | 10 +-
> arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 421 +++++++++++++-
> arch/arm/cpu/armv7/exynos/exynos5_setup.h | 740 +++++++++++++++++++------
> arch/arm/cpu/armv7/exynos/pinmux.c | 241 +++++++-
> arch/arm/dts/exynos5.dtsi | 211 +++++++
> arch/arm/dts/exynos5250.dtsi | 178 +-----
> arch/arm/dts/exynos5420.dtsi | 74 +++
> arch/arm/include/asm/arch-exynos/board.h | 17 +
> arch/arm/include/asm/arch-exynos/clk.h | 1 +
> arch/arm/include/asm/arch-exynos/clock.h | 494 +++++++++++++++++
> arch/arm/include/asm/arch-exynos/cpu.h | 53 +-
> arch/arm/include/asm/arch-exynos/dmc.h | 121 ++--
> arch/arm/include/asm/arch-exynos/dwmmc.h | 13 +
> arch/arm/include/asm/arch-exynos/gpio.h | 143 ++++-
> arch/arm/include/asm/arch-exynos/periph.h | 3 +
> board/samsung/common/Makefile | 4 +
> board/samsung/common/board.c | 407 ++++++++++++++
> board/samsung/dts/exynos5420-smdk5420.dts | 172 ++++++
> board/samsung/smdk5250/exynos5-dt.c | 361 +-----------
> board/samsung/smdk5250/smdk5250.c | 182 +-----
> board/samsung/smdk5420/Makefile | 34 ++
> board/samsung/smdk5420/smdk5420.c | 159 ++++++
> board/samsung/smdk5420/smdk5420_spl.c | 52 ++
> boards.cfg | 1 +
> drivers/mmc/dw_mmc.c | 11 +
> drivers/mmc/exynos_dw_mmc.c | 3 +
> include/configs/exynos5-dt.h | 302 ++++++++++
> include/configs/exynos5250-dt.h | 317 +----------
> include/configs/smdk5420.h | 56 ++
> include/dwmmc.h | 3 +
> spl/Makefile | 7 +-
> tools/Makefile | 2 +
> tools/mkexynosspl.c | 167 ++++--
> 36 files changed, 4271 insertions(+), 1328 deletions(-)
> create mode 100644 arch/arm/dts/exynos5.dtsi
> create mode 100644 arch/arm/dts/exynos5420.dtsi
> create mode 100644 arch/arm/include/asm/arch-exynos/board.h
> create mode 100644 board/samsung/common/board.c
> create mode 100644 board/samsung/dts/exynos5420-smdk5420.dts
> create mode 100644 board/samsung/smdk5420/Makefile
> create mode 100644 board/samsung/smdk5420/smdk5420.c
> create mode 100644 board/samsung/smdk5420/smdk5420_spl.c
> create mode 100644 include/configs/exynos5-dt.h
> create mode 100644 include/configs/smdk5420.h
>
> --
> 1.7.12.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
--
Regards,
Rajeshwari Shinde
^ permalink raw reply [flat|nested] 37+ messages in thread* [U-Boot] [PATCH 00/10 V6] EXYNOS5420: Add SMDK5420 board support
2013-10-31 8:42 ` [U-Boot] [PATCH 00/10 V6] EXYNOS5420: Add SMDK5420 board support Rajeshwari Birje
@ 2013-11-06 11:42 ` Rajeshwari Birje
2013-11-07 1:32 ` Minkyu Kang
0 siblings, 1 reply; 37+ messages in thread
From: Rajeshwari Birje @ 2013-11-06 11:42 UTC (permalink / raw)
To: u-boot
Hi Minkyu Kang,
On Thu, Oct 31, 2013 at 2:12 PM, Rajeshwari Birje
<rajeshwari.birje@gmail.com> wrote:
> Hi Minkyu Kang,
>
> Kindly do review the patch set and do let me know if any review comments.
> Pantelis Antoniou has merged the patch 10 (DWMMC: SMDK5420: Disable
> SMU for eMMC) into mmc tree.
>
We have merge window in next three days, this patches are acked by Simon.
Can you please have a look and get it merged if no review comments
from your end, or
please do let me know if some rework needed.
--
Regards,
Rajeshwari Shinde
> Regards,
> Rajeshwari Shinde.
>
> On Tue, Oct 29, 2013 at 12:53 PM, Rajeshwari S Shinde
> <rajeshwari.s@samsung.com> wrote:
>> This patch adds basic board support for SMDK5420 board.
>> These patches are tested for booting fine on EVT1 SMDK5420.
>>
>> Changes in V2:
>> - Corrected a compilation issue for SMDK5420.
>>
>> Changes in V3:
>> - Add patch to support variable size SPL support
>> - Add patch to disable SMU for eMMC.
>>
>> Changes in V4:
>> - Added check for MAX77686 pmic compilation.
>> - Added correct calculation of gpio based addresses.
>> - Rebased on the latest u-boot code.
>> - Removed patches for UART and TZPC changes as
>> they were not needed.
>> - Added flag to disable SMU for eMMC.
>>
>> Changes in V5:
>> - Moved functions board_mmc_init and board_eth_init
>> to common/board.c in case of device tree support.
>>
>> Changes in V6:
>> - Rebased on the latest mainline branch.
>> - Moved the definitions for SMU to arch/arm dwmmc.h
>>
>> Rajeshwari S Shinde (10):
>> EXYNOS5: Create a common board file
>> Exynos5420: Add base addresses for 5420
>> Exynos5420: Add clock initialization for 5420
>> Exynos5420: Add DDR3 initialization for 5420
>> Exynos5420: Add support for 5420 in pinmux and gpio
>> Exynos5420: Add base patch for SMDK5420
>> DTS: Add dts support for SMDK5420
>> Config: Add initial config for SMDK5420
>> SPL: EXYNOS: Prepare for variable size SPL support
>> DWMMC: SMDK5420: Disable SMU for eMMC
>>
>> arch/arm/cpu/armv7/exynos/clock.c | 270 ++++++++-
>> arch/arm/cpu/armv7/exynos/clock_init.h | 17 +
>> arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 352 +++++++++++-
>> arch/arm/cpu/armv7/exynos/dmc_common.c | 10 +-
>> arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 421 +++++++++++++-
>> arch/arm/cpu/armv7/exynos/exynos5_setup.h | 740 +++++++++++++++++++------
>> arch/arm/cpu/armv7/exynos/pinmux.c | 241 +++++++-
>> arch/arm/dts/exynos5.dtsi | 211 +++++++
>> arch/arm/dts/exynos5250.dtsi | 178 +-----
>> arch/arm/dts/exynos5420.dtsi | 74 +++
>> arch/arm/include/asm/arch-exynos/board.h | 17 +
>> arch/arm/include/asm/arch-exynos/clk.h | 1 +
>> arch/arm/include/asm/arch-exynos/clock.h | 494 +++++++++++++++++
>> arch/arm/include/asm/arch-exynos/cpu.h | 53 +-
>> arch/arm/include/asm/arch-exynos/dmc.h | 121 ++--
>> arch/arm/include/asm/arch-exynos/dwmmc.h | 13 +
>> arch/arm/include/asm/arch-exynos/gpio.h | 143 ++++-
>> arch/arm/include/asm/arch-exynos/periph.h | 3 +
>> board/samsung/common/Makefile | 4 +
>> board/samsung/common/board.c | 407 ++++++++++++++
>> board/samsung/dts/exynos5420-smdk5420.dts | 172 ++++++
>> board/samsung/smdk5250/exynos5-dt.c | 361 +-----------
>> board/samsung/smdk5250/smdk5250.c | 182 +-----
>> board/samsung/smdk5420/Makefile | 34 ++
>> board/samsung/smdk5420/smdk5420.c | 159 ++++++
>> board/samsung/smdk5420/smdk5420_spl.c | 52 ++
>> boards.cfg | 1 +
>> drivers/mmc/dw_mmc.c | 11 +
>> drivers/mmc/exynos_dw_mmc.c | 3 +
>> include/configs/exynos5-dt.h | 302 ++++++++++
>> include/configs/exynos5250-dt.h | 317 +----------
>> include/configs/smdk5420.h | 56 ++
>> include/dwmmc.h | 3 +
>> spl/Makefile | 7 +-
>> tools/Makefile | 2 +
>> tools/mkexynosspl.c | 167 ++++--
>> 36 files changed, 4271 insertions(+), 1328 deletions(-)
>> create mode 100644 arch/arm/dts/exynos5.dtsi
>> create mode 100644 arch/arm/dts/exynos5420.dtsi
>> create mode 100644 arch/arm/include/asm/arch-exynos/board.h
>> create mode 100644 board/samsung/common/board.c
>> create mode 100644 board/samsung/dts/exynos5420-smdk5420.dts
>> create mode 100644 board/samsung/smdk5420/Makefile
>> create mode 100644 board/samsung/smdk5420/smdk5420.c
>> create mode 100644 board/samsung/smdk5420/smdk5420_spl.c
>> create mode 100644 include/configs/exynos5-dt.h
>> create mode 100644 include/configs/smdk5420.h
>>
>> --
>> 1.7.12.4
>>
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
>
>
>
> --
> Regards,
> Rajeshwari Shinde
^ permalink raw reply [flat|nested] 37+ messages in thread
* [U-Boot] [PATCH 00/10 V6] EXYNOS5420: Add SMDK5420 board support
2013-11-06 11:42 ` Rajeshwari Birje
@ 2013-11-07 1:32 ` Minkyu Kang
0 siblings, 0 replies; 37+ messages in thread
From: Minkyu Kang @ 2013-11-07 1:32 UTC (permalink / raw)
To: u-boot
Hi,
On 06/11/13 20:42, Rajeshwari Birje wrote:
> Hi Minkyu Kang,
>
> On Thu, Oct 31, 2013 at 2:12 PM, Rajeshwari Birje
> <rajeshwari.birje@gmail.com> wrote:
>> Hi Minkyu Kang,
>>
>> Kindly do review the patch set and do let me know if any review comments.
>> Pantelis Antoniou has merged the patch 10 (DWMMC: SMDK5420: Disable
>> SMU for eMMC) into mmc tree.
>>
> We have merge window in next three days, this patches are acked by Simon.
> Can you please have a look and get it merged if no review comments
> from your end, or
> please do let me know if some rework needed.
>
Since my working schedule, I were away from mailing list.
I have plan to review pending patches at next week.
So, please wait few days.
Thanks,
Minkyu Kang.
^ permalink raw reply [flat|nested] 37+ messages in thread