* [U-Boot] [PATCH 01/10] fdtdec: Add compatible string for Intel IvyBridge FSP
2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
@ 2015-12-11 10:55 ` Bin Meng
2015-12-19 2:51 ` Simon Glass
2015-12-11 10:55 ` [U-Boot] [PATCH 02/10] x86: ivybridge: Add FSP support Bin Meng
` (8 subsequent siblings)
9 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
To: u-boot
Use "intel,ivybridge-fsp" for Intel IvyBridge FSP compatible string.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
include/fdtdec.h | 1 +
lib/fdtdec.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 7fe657d..c515a3c 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -169,6 +169,7 @@ enum fdt_compat_id {
COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */
COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */
COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
+ COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */
COMPAT_COUNT,
};
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 82d0090..002594d 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -73,6 +73,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
+ COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
--
1.8.2.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 01/10] fdtdec: Add compatible string for Intel IvyBridge FSP
2015-12-11 10:55 ` [U-Boot] [PATCH 01/10] fdtdec: Add compatible string for Intel IvyBridge FSP Bin Meng
@ 2015-12-19 2:51 ` Simon Glass
2015-12-21 2:33 ` Bin Meng
2015-12-21 7:50 ` Bin Meng
0 siblings, 2 replies; 39+ messages in thread
From: Simon Glass @ 2015-12-19 2:51 UTC (permalink / raw)
To: u-boot
Hi Bin,
On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> Use "intel,ivybridge-fsp" for Intel IvyBridge FSP compatible string.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> include/fdtdec.h | 1 +
> lib/fdtdec.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/include/fdtdec.h b/include/fdtdec.h
> index 7fe657d..c515a3c 100644
> --- a/include/fdtdec.h
> +++ b/include/fdtdec.h
> @@ -169,6 +169,7 @@ enum fdt_compat_id {
> COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */
> COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */
> COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
> + COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */
>
> COMPAT_COUNT,
> };
> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
> index 82d0090..002594d 100644
> --- a/lib/fdtdec.c
> +++ b/lib/fdtdec.c
> @@ -73,6 +73,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
> COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
> COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
> COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
> + COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
> };
>
> const char *fdtdec_get_compatible(enum fdt_compat_id id)
> --
> 1.8.2.1
>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>
We should create an FSP uclass I think.
^ permalink raw reply [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 01/10] fdtdec: Add compatible string for Intel IvyBridge FSP
2015-12-19 2:51 ` Simon Glass
@ 2015-12-21 2:33 ` Bin Meng
2016-02-06 4:29 ` Bin Meng
2015-12-21 7:50 ` Bin Meng
1 sibling, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-21 2:33 UTC (permalink / raw)
To: u-boot
Hi Simon,
On Sat, Dec 19, 2015 at 10:51 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Use "intel,ivybridge-fsp" for Intel IvyBridge FSP compatible string.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>> include/fdtdec.h | 1 +
>> lib/fdtdec.c | 1 +
>> 2 files changed, 2 insertions(+)
>>
>> diff --git a/include/fdtdec.h b/include/fdtdec.h
>> index 7fe657d..c515a3c 100644
>> --- a/include/fdtdec.h
>> +++ b/include/fdtdec.h
>> @@ -169,6 +169,7 @@ enum fdt_compat_id {
>> COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */
>> COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */
>> COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
>> + COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */
>>
>> COMPAT_COUNT,
>> };
>> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
>> index 82d0090..002594d 100644
>> --- a/lib/fdtdec.c
>> +++ b/lib/fdtdec.c
>> @@ -73,6 +73,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
>> COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
>> COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
>> COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
>> + COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
>> };
>>
>> const char *fdtdec_get_compatible(enum fdt_compat_id id)
>> --
>> 1.8.2.1
>>
>
> Acked-by: Simon Glass <sjg@chromium.org>
> Tested on link (ivybridge non-FSP)
> Tested-by: Simon Glass <sjg@chromium.org>
>
> We should create an FSP uclass I think.
Maybe, I will add this in my todo list for next release.
Regards,
Bin
^ permalink raw reply [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 01/10] fdtdec: Add compatible string for Intel IvyBridge FSP
2015-12-21 2:33 ` Bin Meng
@ 2016-02-06 4:29 ` Bin Meng
2016-02-19 20:56 ` Simon Glass
0 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2016-02-06 4:29 UTC (permalink / raw)
To: u-boot
Hi Simon,
On Mon, Dec 21, 2015 at 10:33 AM, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Sat, Dec 19, 2015 at 10:51 AM, Simon Glass <sjg@chromium.org> wrote:
>> Hi Bin,
>>
>> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> Use "intel,ivybridge-fsp" for Intel IvyBridge FSP compatible string.
>>>
>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>> ---
>>>
>>> include/fdtdec.h | 1 +
>>> lib/fdtdec.c | 1 +
>>> 2 files changed, 2 insertions(+)
>>>
>>> diff --git a/include/fdtdec.h b/include/fdtdec.h
>>> index 7fe657d..c515a3c 100644
>>> --- a/include/fdtdec.h
>>> +++ b/include/fdtdec.h
>>> @@ -169,6 +169,7 @@ enum fdt_compat_id {
>>> COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */
>>> COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */
>>> COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
>>> + COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */
>>>
>>> COMPAT_COUNT,
>>> };
>>> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
>>> index 82d0090..002594d 100644
>>> --- a/lib/fdtdec.c
>>> +++ b/lib/fdtdec.c
>>> @@ -73,6 +73,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
>>> COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
>>> COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
>>> COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
>>> + COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
>>> };
>>>
>>> const char *fdtdec_get_compatible(enum fdt_compat_id id)
>>> --
>>> 1.8.2.1
>>>
>>
>> Acked-by: Simon Glass <sjg@chromium.org>
>> Tested on link (ivybridge non-FSP)
>> Tested-by: Simon Glass <sjg@chromium.org>
>>
>> We should create an FSP uclass I think.
>
> Maybe, I will add this in my todo list for next release.
>
I looked into the FSP uclass today. Looks if want to do this, we have
to move x86_fsp_init() call to a much later phase, ie: after
initf_dm() is called. I am afraid this does not bring us a bigger
benefits. What do you think?
Regards,
Bin
^ permalink raw reply [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 01/10] fdtdec: Add compatible string for Intel IvyBridge FSP
2016-02-06 4:29 ` Bin Meng
@ 2016-02-19 20:56 ` Simon Glass
0 siblings, 0 replies; 39+ messages in thread
From: Simon Glass @ 2016-02-19 20:56 UTC (permalink / raw)
To: u-boot
Hi Bin,
On 5 February 2016 at 21:29, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Mon, Dec 21, 2015 at 10:33 AM, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Hi Simon,
>>
>> On Sat, Dec 19, 2015 at 10:51 AM, Simon Glass <sjg@chromium.org> wrote:
>>> Hi Bin,
>>>
>>> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>> Use "intel,ivybridge-fsp" for Intel IvyBridge FSP compatible string.
>>>>
>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>>> ---
>>>>
>>>> include/fdtdec.h | 1 +
>>>> lib/fdtdec.c | 1 +
>>>> 2 files changed, 2 insertions(+)
>>>>
>>>> diff --git a/include/fdtdec.h b/include/fdtdec.h
>>>> index 7fe657d..c515a3c 100644
>>>> --- a/include/fdtdec.h
>>>> +++ b/include/fdtdec.h
>>>> @@ -169,6 +169,7 @@ enum fdt_compat_id {
>>>> COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */
>>>> COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */
>>>> COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
>>>> + COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */
>>>>
>>>> COMPAT_COUNT,
>>>> };
>>>> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
>>>> index 82d0090..002594d 100644
>>>> --- a/lib/fdtdec.c
>>>> +++ b/lib/fdtdec.c
>>>> @@ -73,6 +73,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
>>>> COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
>>>> COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
>>>> COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
>>>> + COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
>>>> };
>>>>
>>>> const char *fdtdec_get_compatible(enum fdt_compat_id id)
>>>> --
>>>> 1.8.2.1
>>>>
>>>
>>> Acked-by: Simon Glass <sjg@chromium.org>
>>> Tested on link (ivybridge non-FSP)
>>> Tested-by: Simon Glass <sjg@chromium.org>
>>>
>>> We should create an FSP uclass I think.
>>
>> Maybe, I will add this in my todo list for next release.
>>
>
> I looked into the FSP uclass today. Looks if want to do this, we have
> to move x86_fsp_init() call to a much later phase, ie: after
> initf_dm() is called. I am afraid this does not bring us a bigger
> benefits. What do you think?
Yes I suspect you are right. But we do want eventually move all this
compat stuff into drivers. I'm not sure sure of the best approach yet.
Let's keep an eye on it.
Regards,
Simon
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 01/10] fdtdec: Add compatible string for Intel IvyBridge FSP
2015-12-19 2:51 ` Simon Glass
2015-12-21 2:33 ` Bin Meng
@ 2015-12-21 7:50 ` Bin Meng
1 sibling, 0 replies; 39+ messages in thread
From: Bin Meng @ 2015-12-21 7:50 UTC (permalink / raw)
To: u-boot
On Sat, Dec 19, 2015 at 10:51 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Use "intel,ivybridge-fsp" for Intel IvyBridge FSP compatible string.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>> include/fdtdec.h | 1 +
>> lib/fdtdec.c | 1 +
>> 2 files changed, 2 insertions(+)
>>
>> diff --git a/include/fdtdec.h b/include/fdtdec.h
>> index 7fe657d..c515a3c 100644
>> --- a/include/fdtdec.h
>> +++ b/include/fdtdec.h
>> @@ -169,6 +169,7 @@ enum fdt_compat_id {
>> COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */
>> COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */
>> COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
>> + COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */
>>
>> COMPAT_COUNT,
>> };
>> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
>> index 82d0090..002594d 100644
>> --- a/lib/fdtdec.c
>> +++ b/lib/fdtdec.c
>> @@ -73,6 +73,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
>> COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
>> COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
>> COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
>> + COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
>> };
>>
>> const char *fdtdec_get_compatible(enum fdt_compat_id id)
>> --
>> 1.8.2.1
>>
>
> Acked-by: Simon Glass <sjg@chromium.org>
> Tested on link (ivybridge non-FSP)
> Tested-by: Simon Glass <sjg@chromium.org>
>
applied to u-boot-x86/next, thanks!
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 02/10] x86: ivybridge: Add FSP support
2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
2015-12-11 10:55 ` [U-Boot] [PATCH 01/10] fdtdec: Add compatible string for Intel IvyBridge FSP Bin Meng
@ 2015-12-11 10:55 ` Bin Meng
2015-12-19 2:52 ` Simon Glass
2015-12-11 10:55 ` [U-Boot] [PATCH 03/10] tools: microcode-tool: Support parsing header file with a license block Bin Meng
` (7 subsequent siblings)
9 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
To: u-boot
IvyBridge FSP package is built with a base address at 0xfff80000,
and does not use UPD data region. This adds basic FSP support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/x86/cpu/ivybridge/Kconfig | 8 ++++
arch/x86/cpu/ivybridge/Makefile | 4 ++
arch/x86/cpu/ivybridge/fsp_configs.c | 45 ++++++++++++++++++++++
arch/x86/cpu/ivybridge/ivybridge.c | 22 +++++++++++
.../include/asm/arch-ivybridge/fsp/fsp_configs.h | 40 +++++++++++++++++++
arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h | 12 ++++++
6 files changed, 131 insertions(+)
create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c
create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c
create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
index 56abd8f..36b74c2 100644
--- a/arch/x86/cpu/ivybridge/Kconfig
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -72,4 +72,12 @@ config ENABLE_VMX
will be unable to support virtualisation, or it will run very
slowly.
+config FSP_ADDR
+ hex
+ default 0xfff80000
+
+config FSP_USE_UPD
+ bool
+ default n
+
endif
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index 0c7efae..d74635e 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -4,6 +4,9 @@
# SPDX-License-Identifier: GPL-2.0+
#
+ifdef CONFIG_HAVE_FSP
+obj-y += fsp_configs.o ivybridge.o
+else
obj-y += bd82x6x.o
obj-y += car.o
obj-y += cpu.o
@@ -22,3 +25,4 @@ obj-y += sata.o
obj-y += sdram.o
obj-y += usb_ehci.o
obj-y += usb_xhci.o
+endif
diff --git a/arch/x86/cpu/ivybridge/fsp_configs.c b/arch/x86/cpu/ivybridge/fsp_configs.c
new file mode 100644
index 0000000..5d8b814
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/fsp_configs.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/fsp/fsp_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void update_fsp_configs(struct fsp_config_data *config,
+ struct fspinit_rtbuf *rt_buf)
+{
+ struct platform_config *plat_config = &config->plat_config;
+ struct memory_config *mem_config = &config->mem_config;
+ const void *blob = gd->fdt_blob;
+ int node;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_IVYBRIDGE_FSP);
+ if (node < 0) {
+ debug("%s: Cannot find FSP node\n", __func__);
+ return;
+ }
+
+ plat_config->enable_ht =
+ fdtdec_get_bool(blob, node, "fsp,enable-ht");
+ plat_config->enable_turbo =
+ fdtdec_get_bool(blob, node, "fsp,enable-turbo");
+ plat_config->enable_memory_down =
+ fdtdec_get_bool(blob, node, "fsp,enable-memory-down");
+ plat_config->enable_fast_boot =
+ fdtdec_get_bool(blob, node, "fsp,enable-fast-boot");
+
+ /* Initialize runtime buffer for fsp_init() */
+ rt_buf->stack_top = config->common.stack_top - 32;
+ rt_buf->boot_mode = config->common.boot_mode;
+ rt_buf->plat_config = plat_config;
+
+ if (plat_config->enable_memory_down)
+ rt_buf->mem_config = mem_config;
+ else
+ rt_buf->mem_config = NULL;
+}
diff --git a/arch/x86/cpu/ivybridge/ivybridge.c b/arch/x86/cpu/ivybridge/ivybridge.c
new file mode 100644
index 0000000..afe7e57
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/ivybridge.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/post.h>
+#include <asm/processor.h>
+
+int arch_cpu_init(void)
+{
+ int ret;
+
+ post_code(POST_CPU_INIT);
+
+ ret = x86_cpu_init_f();
+ if (ret)
+ return ret;
+
+ return 0;
+}
diff --git a/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
new file mode 100644
index 0000000..24e2f2f
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef __FSP_CONFIGS_H__
+#define __FSP_CONFIGS_H__
+
+struct platform_config {
+ u8 enable_ht;
+ u8 enable_turbo;
+ u8 enable_memory_down;
+ u8 enable_fast_boot;
+};
+
+/*
+ * Dummy structure for now as currently only SPD is verified in U-Boot.
+ *
+ * We can add the missing parameters when adding support on a board with
+ * memory down configuration.
+ */
+struct memory_config {
+ u8 dummy;
+};
+
+struct fsp_config_data {
+ struct fsp_cfg_common common;
+ struct platform_config plat_config;
+ struct memory_config mem_config;
+};
+
+struct fspinit_rtbuf {
+ u32 stack_top;
+ u32 boot_mode;
+ struct platform_config *plat_config;
+ struct memory_config *mem_config;
+};
+
+#endif /* __FSP_CONFIGS_H__ */
diff --git a/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
new file mode 100644
index 0000000..be9f055
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef __FSP_VPD_H__
+#define __FSP_VPD_H__
+
+/* IvyBridge FSP does not support VPD/UPD */
+
+#endif
--
1.8.2.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 02/10] x86: ivybridge: Add FSP support
2015-12-11 10:55 ` [U-Boot] [PATCH 02/10] x86: ivybridge: Add FSP support Bin Meng
@ 2015-12-19 2:52 ` Simon Glass
2015-12-21 2:27 ` Bin Meng
0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2015-12-19 2:52 UTC (permalink / raw)
To: u-boot
On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> IvyBridge FSP package is built with a base address at 0xfff80000,
> and does not use UPD data region. This adds basic FSP support.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> arch/x86/cpu/ivybridge/Kconfig | 8 ++++
> arch/x86/cpu/ivybridge/Makefile | 4 ++
> arch/x86/cpu/ivybridge/fsp_configs.c | 45 ++++++++++++++++++++++
> arch/x86/cpu/ivybridge/ivybridge.c | 22 +++++++++++
> .../include/asm/arch-ivybridge/fsp/fsp_configs.h | 40 +++++++++++++++++++
> arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h | 12 ++++++
> 6 files changed, 131 insertions(+)
> create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c
> create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c
> create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
> create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>
One question: why do we need an Intel license on this code?
- Simon
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 02/10] x86: ivybridge: Add FSP support
2015-12-19 2:52 ` Simon Glass
@ 2015-12-21 2:27 ` Bin Meng
2015-12-23 16:44 ` Simon Glass
0 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-21 2:27 UTC (permalink / raw)
To: u-boot
Hi Simon,
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> IvyBridge FSP package is built with a base address at 0xfff80000,
>> and does not use UPD data region. This adds basic FSP support.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>> arch/x86/cpu/ivybridge/Kconfig | 8 ++++
>> arch/x86/cpu/ivybridge/Makefile | 4 ++
>> arch/x86/cpu/ivybridge/fsp_configs.c | 45 ++++++++++++++++++++++
>> arch/x86/cpu/ivybridge/ivybridge.c | 22 +++++++++++
>> .../include/asm/arch-ivybridge/fsp/fsp_configs.h | 40 +++++++++++++++++++
>> arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h | 12 ++++++
>> 6 files changed, 131 insertions(+)
>> create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c
>> create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c
>> create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
>> create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
>
> Acked-by: Simon Glass <sjg@chromium.org>
> Tested on link (ivybridge non-FSP)
> Tested-by: Simon Glass <sjg@chromium.org>
>
> One question: why do we need an Intel license on this code?
>
It was a copy and paste from other platform (queensbay and baytrail)
files. Do you think we should change it to GPLv2+?
Regards,
Bin
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 02/10] x86: ivybridge: Add FSP support
2015-12-21 2:27 ` Bin Meng
@ 2015-12-23 16:44 ` Simon Glass
2015-12-23 22:48 ` Bin Meng
0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2015-12-23 16:44 UTC (permalink / raw)
To: u-boot
Hi Bin,
On 20 December 2015 at 19:27, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
>> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> IvyBridge FSP package is built with a base address at 0xfff80000,
>>> and does not use UPD data region. This adds basic FSP support.
>>>
>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>> ---
>>>
>>> arch/x86/cpu/ivybridge/Kconfig | 8 ++++
>>> arch/x86/cpu/ivybridge/Makefile | 4 ++
>>> arch/x86/cpu/ivybridge/fsp_configs.c | 45 ++++++++++++++++++++++
>>> arch/x86/cpu/ivybridge/ivybridge.c | 22 +++++++++++
>>> .../include/asm/arch-ivybridge/fsp/fsp_configs.h | 40 +++++++++++++++++++
>>> arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h | 12 ++++++
>>> 6 files changed, 131 insertions(+)
>>> create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c
>>> create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c
>>> create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
>>> create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
>>
>> Acked-by: Simon Glass <sjg@chromium.org>
>> Tested on link (ivybridge non-FSP)
>> Tested-by: Simon Glass <sjg@chromium.org>
>>
>> One question: why do we need an Intel license on this code?
>>
>
> It was a copy and paste from other platform (queensbay and baytrail)
> files. Do you think we should change it to GPLv2+?
Hmm - is it using this license because it was written by Intel, or
because you modified it from the FSP code that was written by Intel?
If so, then I suppose it is reasonable to use the Intel license.
Regards,
Simon
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 02/10] x86: ivybridge: Add FSP support
2015-12-23 16:44 ` Simon Glass
@ 2015-12-23 22:48 ` Bin Meng
0 siblings, 0 replies; 39+ messages in thread
From: Bin Meng @ 2015-12-23 22:48 UTC (permalink / raw)
To: u-boot
Hi Simon,
On Thu, Dec 24, 2015 at 12:44 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 20 December 2015 at 19:27, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Hi Simon,
>>
>> On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
>>> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>> IvyBridge FSP package is built with a base address at 0xfff80000,
>>>> and does not use UPD data region. This adds basic FSP support.
>>>>
>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>>> ---
>>>>
>>>> arch/x86/cpu/ivybridge/Kconfig | 8 ++++
>>>> arch/x86/cpu/ivybridge/Makefile | 4 ++
>>>> arch/x86/cpu/ivybridge/fsp_configs.c | 45 ++++++++++++++++++++++
>>>> arch/x86/cpu/ivybridge/ivybridge.c | 22 +++++++++++
>>>> .../include/asm/arch-ivybridge/fsp/fsp_configs.h | 40 +++++++++++++++++++
>>>> arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h | 12 ++++++
>>>> 6 files changed, 131 insertions(+)
>>>> create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c
>>>> create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c
>>>> create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
>>>> create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
>>>
>>> Acked-by: Simon Glass <sjg@chromium.org>
>>> Tested on link (ivybridge non-FSP)
>>> Tested-by: Simon Glass <sjg@chromium.org>
>>>
>>> One question: why do we need an Intel license on this code?
>>>
>>
>> It was a copy and paste from other platform (queensbay and baytrail)
>> files. Do you think we should change it to GPLv2+?
>
> Hmm - is it using this license because it was written by Intel, or
> because you modified it from the FSP code that was written by Intel?
> If so, then I suppose it is reasonable to use the Intel license.
>
The file was not written by Intel. Current U-Boot implementation is
our own. I will change the license in v2.
Regards,
Bin
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 03/10] tools: microcode-tool: Support parsing header file with a license block
2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
2015-12-11 10:55 ` [U-Boot] [PATCH 01/10] fdtdec: Add compatible string for Intel IvyBridge FSP Bin Meng
2015-12-11 10:55 ` [U-Boot] [PATCH 02/10] x86: ivybridge: Add FSP support Bin Meng
@ 2015-12-11 10:55 ` Bin Meng
2015-12-19 2:52 ` Simon Glass
2015-12-11 10:55 ` [U-Boot] [PATCH 04/10] x86: ivybridge: Add microcode blobs for all the steppings Bin Meng
` (6 subsequent siblings)
9 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
To: u-boot
The microcode header files in the Intel Chief River FSP package have
a license comment block. Update the microcode-tool to support parsing
it and extract the license text to the .dtsi file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
tools/microcode-tool.py | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/tools/microcode-tool.py b/tools/microcode-tool.py
index 71c2e91..790c27e 100755
--- a/tools/microcode-tool.py
+++ b/tools/microcode-tool.py
@@ -95,9 +95,23 @@ def ParseHeaderFiles(fname_list):
name = os.path.splitext(name)[0]
data = []
with open(fname) as fd:
+ license_start = False
+ license_end = False
for line in fd:
line = line.rstrip()
+ if len(line) >= 2:
+ if line[0] == '/' and line[1] == '*':
+ license_start = True
+ continue
+ if line[0] == '*' and line[1] == '/':
+ license_end = True
+ continue
+ if license_start and not license_end:
+ # Ignore blank line
+ if len(line) > 0:
+ license_text.append(line)
+ continue
# Omit anything after the last comma
words = line.split(',')[:-1]
data += [word + ',' for word in words]
--
1.8.2.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 03/10] tools: microcode-tool: Support parsing header file with a license block
2015-12-11 10:55 ` [U-Boot] [PATCH 03/10] tools: microcode-tool: Support parsing header file with a license block Bin Meng
@ 2015-12-19 2:52 ` Simon Glass
2015-12-21 7:50 ` Bin Meng
0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2015-12-19 2:52 UTC (permalink / raw)
To: u-boot
On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> The microcode header files in the Intel Chief River FSP package have
> a license comment block. Update the microcode-tool to support parsing
> it and extract the license text to the .dtsi file.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> tools/microcode-tool.py | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
Acked-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 03/10] tools: microcode-tool: Support parsing header file with a license block
2015-12-19 2:52 ` Simon Glass
@ 2015-12-21 7:50 ` Bin Meng
0 siblings, 0 replies; 39+ messages in thread
From: Bin Meng @ 2015-12-21 7:50 UTC (permalink / raw)
To: u-boot
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> The microcode header files in the Intel Chief River FSP package have
>> a license comment block. Update the microcode-tool to support parsing
>> it and extract the license text to the .dtsi file.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>> tools/microcode-tool.py | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>
> Acked-by: Simon Glass <sjg@chromium.org>
applied to u-boot-x86/next, thanks!
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 04/10] x86: ivybridge: Add microcode blobs for all the steppings
2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
` (2 preceding siblings ...)
2015-12-11 10:55 ` [U-Boot] [PATCH 03/10] tools: microcode-tool: Support parsing header file with a license block Bin Meng
@ 2015-12-11 10:55 ` Bin Meng
2015-12-19 2:52 ` Simon Glass
2015-12-11 10:55 ` [U-Boot] [PATCH 05/10] superio: Add SMSC SIO1007 driver Bin Meng
` (5 subsequent siblings)
9 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
To: u-boot
This adds microcode blobs created from Intel FSP package for the
Chief River platform. They are for all the Ivy Bridge steppings:
306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the
306a9 which is already in the U-Boot tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/x86/dts/microcode/m12306a2_00000008.dtsi | 554 +++++++++++++++++++++
arch/x86/dts/microcode/m12306a4_00000007.dtsi | 618 +++++++++++++++++++++++
arch/x86/dts/microcode/m12306a5_00000007.dtsi | 618 +++++++++++++++++++++++
arch/x86/dts/microcode/m12306a8_00000010.dtsi | 682 ++++++++++++++++++++++++++
4 files changed, 2472 insertions(+)
create mode 100644 arch/x86/dts/microcode/m12306a2_00000008.dtsi
create mode 100644 arch/x86/dts/microcode/m12306a4_00000007.dtsi
create mode 100644 arch/x86/dts/microcode/m12306a5_00000007.dtsi
create mode 100644 arch/x86/dts/microcode/m12306a8_00000010.dtsi
diff --git a/arch/x86/dts/microcode/m12306a2_00000008.dtsi b/arch/x86/dts/microcode/m12306a2_00000008.dtsi
new file mode 100644
index 0000000..6b35c39
--- /dev/null
+++ b/arch/x86/dts/microcode/m12306a2_00000008.dtsi
@@ -0,0 +1,554 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x8>;
+intel,date-code = <0x5182011>;
+intel,processor-signature = <0x306a2>;
+intel,checksum = <0xa0e51feb>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x08000000 0x11201805 0xa2060300
+ 0xeb1fe5a0 0x01000000 0x12000000 0xd01f0000
+ 0x00200000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x08000000
+ 0x00000000 0x00000000 0x17051120 0xd1070000
+ 0x01000000 0xa2060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x5665ff94 0x179da7cf 0x1e819fb2 0xb0c24e8e
+ 0x5cb7beb5 0x43af9a6c 0xcb0b4ccc 0x195d8712
+ 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6
+ 0x5fb36178 0xbc17d76b 0x31b7b923 0xc81aec82
+ 0x647b3320 0xf1db9653 0xff3b9759 0xe9c74b72
+ 0x3b193752 0xc147860b 0x160e0d6a 0x5bdb9dbf
+ 0x1ccce2ac 0x387670ad 0x2f106f05 0xf8607ea3
+ 0x42562576 0x30e086fb 0x409a06b8 0xf1957736
+ 0x5eb03f65 0xad147fab 0xe1a8e8b6 0x208d59d2
+ 0x683fba2e 0xf172b378 0xf8138dba 0x61e81d1f
+ 0xd551f997 0x28c79780 0x04f9db27 0xa80679b9
+ 0xaca4e7ff 0x6876944b 0x26d7dbc1 0x77f7dc2a
+ 0xf0bcb163 0x1b2a8e81 0x7b90aa49 0x8d5eaf2f
+ 0x522384ae 0xae7f7082 0x412ba10a 0x1ce1baa0
+ 0x478c29b4 0x9c09b4d2 0xf225f64f 0xd43026cd
+ 0x81098579 0x7df5db05 0xa5815bb0 0xc73ee756
+ 0x9738cb95 0xa5bd62e2 0x88e2c6b2 0x778e7fcb
+ 0xd3bdb872 0x9404403f 0x5be6ad63 0x71dc4abc
+ 0x11000000 0x72873db0 0x0f41a6d6 0x609f17c3
+ 0x1b1349d0 0xe1950c52 0xdbc8e4fc 0xebc212b5
+ 0x77697371 0x7b156982 0xe71e5ccf 0x78bd638c
+ 0x1b196322 0x8b7ebfbf 0xc2e2588f 0xf139b826
+ 0x98ac3169 0xaa9131b0 0x2d7563f8 0xa1300b39
+ 0x5bd4675f 0x25a4b079 0xe006afb1 0x2bd60828
+ 0x453a0abb 0x3b944679 0x33fd63fd 0xd26ff3c9
+ 0x23c0a581 0xf3beb03a 0xc07109cb 0x2e4c27d9
+ 0xc857a22e 0x470c5b1d 0x5b990a43 0x9f6999e6
+ 0xb5d88f30 0x48c6a95c 0x3756bdc5 0xdc7011d2
+ 0x705d8ef2 0xa657f56c 0xa0b168a4 0x219a3d73
+ 0xb761630a 0x3fa1fb9a 0xe82b74c6 0x037911be
+ 0x5104f10d 0xb4b9e04c 0x4db05893 0x86feb635
+ 0x7391fed4 0x5a690081 0x05797a02 0xce30465e
+ 0x989cdec2 0xa478a8c8 0xa406b02b 0x4ac6e170
+ 0x54ceef3f 0xbbe5e10f 0x7e60e8e1 0x32a015cf
+ 0xaf6491a8 0xef6c1c39 0x38d54b81 0xbca9aa3f
+ 0x7be47871 0x1af28407 0x07fde04d 0x56d82648
+ 0x9f91a24f 0xa71eb768 0x263f176d 0x324196dd
+ 0xa31a37a9 0x3f14178c 0xb3fbb89e 0x18d29b03
+ 0x95c2e349 0xbf559bbe 0xa011c68a 0x0be59ecf
+ 0x644217f4 0x330a8356 0x89f5956e 0xb7103120
+ 0x7d0d2203 0x9d40fc96 0xa9279679 0x81d22306
+ 0x1bc7b5fa 0x679e3a28 0x511a7129 0x81a006a4
+ 0x9791dd09 0xed9dd69a 0xe28904ab 0x90621a2e
+ 0x22efe24d 0x215fd043 0x833f7214 0xf4603491
+ 0x38147d32 0xb4a8fadf 0x306947c3 0xf0998693
+ 0x42fc3ed8 0xe04820c4 0x377e0027 0xd9ed3c92
+ 0xcd166b69 0x1d43b6b7 0x16efc18a 0x5890992a
+ 0xae281f65 0x94b09325 0x6129dee5 0x60ccec89
+ 0xae1b35bb 0xdbe389b3 0xd140a7cf 0xccfe2e86
+ 0x72eff1e3 0x625e92d5 0x7e85420e 0x857f43db
+ 0x22c8784b 0x614e4fff 0x02e87cf8 0x2cb6de43
+ 0xd0bc235d 0xcd19968c 0xcce91f04 0xf36b1f2b
+ 0x8552a638 0x8c3b66fa 0x6fce17b0 0xa1a44384
+ 0x141c8798 0xa8981b4d 0x5d62efa2 0x2b9c0cdd
+ 0x985db4b2 0xbdcb9557 0xd46a70e4 0x90353762
+ 0xdb088ed9 0xcb410eb4 0x7d6bb4b1 0x9b451d22
+ 0xd96dca73 0xec56e8fc 0xa450a765 0x327ca511
+ 0x8d498359 0x1c9ec3a8 0x1986a9a5 0x42c679d5
+ 0xbfbe6164 0xde72b0ba 0xec2c6e93 0x97079604
+ 0x11657c6b 0xf82e6bbe 0x98cddc0b 0xb3168682
+ 0xc22896e3 0x33885964 0xc4791283 0x50553998
+ 0x21976704 0x167c459a 0xb083168c 0x77f08c0f
+ 0x31bbef07 0xff142fda 0xca69c3aa 0x56b2c97c
+ 0x4ba16716 0x7c0688a8 0x8a975497 0x5b7d39f6
+ 0x92815873 0x83bba85a 0x561a8fe1 0xd8b1a419
+ 0x092b76af 0xa708fdcc 0x49986eb3 0xd6ff3b26
+ 0x7bc162a2 0xe1d164fb 0x008705e0 0x825bf6b2
+ 0x5f14e5be 0x69a27ff8 0xd8803cea 0x813c89d2
+ 0xd0558aee 0x88dfdd34 0xb959a0e2 0x948e4309
+ 0xd11e40fa 0x12e739ee 0x453a6b84 0xb85174b9
+ 0x433b0d8c 0x44a8a145 0xe904b21b 0x6a824691
+ 0xf9a191ff 0xe930a249 0x54cc511b 0x76860260
+ 0x268756d3 0x6c535556 0xa89514ea 0x553d3792
+ 0xcb004a7b 0xa2f0234b 0x044d0f13 0x92fa800e
+ 0x5c3ff9d0 0x58dbc14d 0xe305c4da 0xa8af0443
+ 0x88efda5c 0xdeba05ec 0xb128acf7 0x8246648d
+ 0x1ff6d432 0xe919faec 0xd7593779 0xbf4f4ffa
+ 0x26ff3f67 0xe385e75c 0xece43afa 0xd18361ac
+ 0x6f1ff0fd 0x34930c03 0x21c3bb52 0x18508c5a
+ 0x5fac5947 0x93bf46c5 0x0093135f 0x976eee2b
+ 0x0d151deb 0x4b80987a 0x172ce7ac 0x3858dca0
+ 0xf97070db 0x2ac62f48 0xb4a51e8a 0x419c1d35
+ 0xdd9e5157 0xdb21aaea 0xb81f9985 0x19ad9859
+ 0x2074a3fb 0x6f15f27d 0xef3f652b 0x9896582e
+ 0x6787efe9 0xcd8c63a6 0xb94fa052 0xe20b59c5
+ 0x1ae5c0b4 0x46c3b1cc 0xe47ae0a2 0x979ceb01
+ 0x8281c594 0x87d430bc 0x8e6942f1 0x73f40077
+ 0x201415c5 0x46f3e2ea 0x2804b307 0xfa897dc7
+ 0xb79c8456 0x9a7f1b68 0x21f77388 0x0a40a857
+ 0xfa9f096e 0x097fec4b 0xb59a8326 0x25825192
+ 0x68c6b0a0 0xd2757f43 0xd09b408f 0x725ee748
+ 0x4391e4eb 0x8147e982 0x2f153b18 0x6251b500
+ 0x69963d11 0xdd3d67f7 0x67efacc9 0xface6418
+ 0xf4d9b154 0x3e6a6c27 0x95ab29e6 0x75d11283
+ 0xe5377709 0x08831cbb 0x9151f9ee 0x23e3dd5e
+ 0x8b7c87d1 0x71e2550f 0x85943522 0x4486916b
+ 0x8c253c1f 0x197c271c 0xda897e03 0x0ba0b957
+ 0xfefb65f3 0x53e500f3 0xcc52630b 0x008ec579
+ 0x225da363 0xfb129d9f 0x7069493e 0x4657e2d2
+ 0xc1d73c79 0xd292191b 0x26314c0f 0x8a20f248
+ 0x76a162b3 0x5b55dd77 0xa03e9e9b 0xca6b073d
+ 0x813cbaa7 0x7078a94e 0x7d14ed49 0xd86e4ddc
+ 0xe2038ab7 0x75e3ca49 0xd65dfae1 0x340125b8
+ 0x815bb509 0xe7270f14 0xd9f5770c 0x9aca22c5
+ 0x0c48deca 0x3c2ff24f 0x2afdbc05 0x1dafce0a
+ 0x3cbe90b4 0xb37b8faf 0xb83cc372 0xe0468ba6
+ 0x32dca511 0x3c026766 0xceb30b38 0x4cfe6196
+ 0x98bbba31 0xe6322e2c 0x7bcd465a 0x9825fc05
+ 0xe9a469ad 0x94e517ec 0x49318a22 0xbee03c9e
+ 0x85e37df3 0x44358a91 0x00c0490a 0xad1e4041
+ 0xef509388 0xf3194050 0xda5a0de5 0x849d1b1a
+ 0xad5c5ce7 0x624cadd7 0xef00b2c8 0x5c423950
+ 0x8ecbf150 0x98314268 0xe7188ca4 0x4c7ab52e
+ 0xe8bd4c4f 0xdd2360e4 0xf72623e8 0xed45c186
+ 0xf1271f39 0xf128076c 0x499fe644 0xc243460d
+ 0xb399912a 0x1894c1fc 0xcc5a12f5 0xb554e06c
+ 0xf7cf59fd 0xd09ce7ed 0x8f93995d 0xad38e480
+ 0x92cfa3cb 0xef29ce8c 0x1ca8efb2 0x4c390618
+ 0x33e36271 0x752074a0 0xda478d2d 0x10a52d8c
+ 0xd99a36a7 0x50d0db0d 0x728e2f68 0x2eaec798
+ 0x6f5ee097 0x965b0f08 0x0e15ab52 0xadcd83da
+ 0xc2a386bb 0x9ba0071f 0xac242740 0x362668f6
+ 0x01e0adea 0x6d1b2254 0xdbd0fa8d 0x2ef68fe9
+ 0x19742cda 0xa2522cd1 0xad6009c1 0x56374b42
+ 0xf77e7b87 0xf47d5152 0x34ef274c 0x6c8f69db
+ 0xe7c1cd2a 0x60ad1a6c 0x5f11b920 0xe4e903e2
+ 0x6d6d9227 0xcd1f2eb2 0x5c81902d 0x637840a0
+ 0x47f88b3c 0xfcc51034 0xad97af5c 0x14403d02
+ 0x9aae22d0 0x42c50b60 0xdf483d6e 0x5b123f8f
+ 0xb8567830 0x4552282d 0x67ecb54f 0xc5279a68
+ 0x47ca430f 0xf3b581cf 0x70084982 0x04e7a816
+ 0x339e2452 0x0ef1fb04 0x15e018cc 0xd2f83552
+ 0x25be4294 0x643a42a0 0x6ea8207e 0xfd01053a
+ 0xfb25050b 0x8f9d5a9b 0x97e55134 0xb338c705
+ 0xcd1fed07 0x21e5fea1 0xbefd892a 0xe870d3b7
+ 0x696555e9 0x02e80efb 0x91be36e5 0xe98e722a
+ 0x0984101b 0x5b7e344c 0x2c37b88d 0xd153be06
+ 0x58a02ee9 0xb74cde84 0xf2c74516 0x86e3e608
+ 0xf476e86e 0x08053489 0xd8eaa295 0x1042e1aa
+ 0xdc1f613a 0x87af7b7b 0x4bc87db1 0xa005aa8f
+ 0xf85e8566 0xeefb7891 0x6a71cdde 0xc897237c
+ 0xd08778ac 0xdb46f47e 0x87900844 0x19bf15ab
+ 0x0fac1b10 0xbca22485 0xf09a3374 0x222594b1
+ 0xbeac6e17 0x9751d50a 0xe57b78de 0x00c901d4
+ 0x6f8569b0 0x7d778d8e 0x146b7a5e 0x017752fe
+ 0xd2efab56 0x92b6414b 0x796c0dac 0xf2c9ba15
+ 0xffaaf707 0x9e1e0c82 0x22410900 0x703caaf1
+ 0x3ba1fbb8 0x6e330a79 0xe8e3416d 0x19f96d99
+ 0xaad45f95 0x8c23afce 0x79ee1c03 0xf9926e38
+ 0x4552598e 0x2a1ab185 0x9614a74f 0x3ee75de8
+ 0xcfd5e9bf 0xfa7c8c10 0xec727ddd 0x596c2a3a
+ 0x2602a577 0xc8701cc0 0x90670ca5 0x6fd2074a
+ 0x237729e5 0xf94389fe 0x56294aca 0xf0e25fcb
+ 0x92d8755e 0xc9ebab69 0x0056c4bf 0x0802b4bd
+ 0xdca506fb 0x8af71ac1 0x5664ee70 0xc0cc9b12
+ 0x1f2b957c 0x86d75b65 0x0356f061 0xb2a7df2d
+ 0xeebcaed9 0x82240f86 0xd442e66e 0x1c90f7a0
+ 0x340ffd46 0x6665830d 0x92d79070 0x5b84b23b
+ 0x73652140 0x9cc4ba89 0x7a5e361b 0x889de8a4
+ 0xf767445b 0x9c6e7316 0x35e07fc4 0x762678c9
+ 0x8a3e23a1 0x8cf392c6 0xbb9bba49 0xb212b538
+ 0x786d11be 0xc04b989b 0xd286c664 0x9e666e96
+ 0x28987d62 0x5620e31f 0x09284b40 0x2c655487
+ 0xce2d6072 0x1f253329 0xffdc93fe 0x7945e700
+ 0x3e063409 0x6b24a76c 0xdc165d13 0x3f1924ad
+ 0x9a20aec4 0xabbd3741 0xa9242541 0x9c2e780b
+ 0xc8369a55 0x285bee8f 0x34564d35 0x36e55913
+ 0x3e64991f 0x17d9e58c 0x8dd1fb64 0x4d8358d3
+ 0x87a80361 0xa4d61dc4 0xf6dfa482 0x81d24c35
+ 0xaf27cba3 0x5e332395 0xfad6e5a3 0x9cabf33a
+ 0xdcf0921d 0xd893c3a9 0xee8cd5a4 0x4803a801
+ 0x4083023b 0x23272921 0xbe63102a 0x6b62f4fc
+ 0xd1358925 0x4c87470c 0xed7e0c37 0x789f86b5
+ 0x48312d14 0xb50547c3 0x310318b3 0xad0e876b
+ 0x3a2b377d 0xed05829b 0x652ded97 0x316081ba
+ 0xd2d2e21c 0xfc3ca2b5 0x1d480f5b 0x854ae0b9
+ 0x1cb9edae 0x1e8f5f6c 0x0b1cac90 0xd02474f8
+ 0xb6cb0359 0x991a241f 0x961dfdd4 0xf4f8a95b
+ 0xa67e5206 0xbe5efa25 0xdc619c64 0xf350e2b2
+ 0x8244d7a0 0x95ff2840 0x1c8b0751 0x001daf7b
+ 0xb4690af6 0x8ada4365 0xebae8afb 0xa9899cc7
+ 0x651b4e76 0xd42501d5 0xbb5a2d30 0x6b0b4fe7
+ 0xb66d5241 0xe4793b34 0x18e98006 0x2f6217e4
+ 0x9dd33721 0xfdd14fb3 0x03e82ad0 0xd5e2dfaa
+ 0xa248461b 0xa309bef3 0x47472de0 0x0ce6c4c7
+ 0xd9c0bf01 0x5c54a2ca 0x9e55fa97 0x992a4b89
+ 0xc75b9782 0xb02d7a3d 0xd948fab4 0x1b6501d6
+ 0x2674a8ad 0xb1ca0d48 0xcfb534c8 0x729864bb
+ 0x047b2178 0xd88ea657 0x863cf450 0xf0fb6923
+ 0x8399574f 0x2bc03d5c 0xb0f7d334 0xfddf7c72
+ 0x462f1132 0x0640ff38 0x03b426be 0x6af7f1f8
+ 0x474d955c 0xd8174573 0x9975e719 0x4956644c
+ 0x38702613 0xa5ca4cdd 0xc55e5234 0xcd7f3532
+ 0x5696e34e 0xbe5a5c3a 0x1faa53bc 0xba0b5b0a
+ 0xc02b0e33 0xa13f7ec5 0x424cbc5c 0x5aa097cf
+ 0x8e8d1c22 0xab66e427 0x9c1053f7 0x7e62751d
+ 0xd4b094a1 0x57d4766f 0xd023b33a 0xbe020296
+ 0x8102755f 0x6bda667c 0x98f6ea76 0x6deaffb3
+ 0x151caa3c 0x0a1040da 0xf125ebd5 0x929de719
+ 0x6618f307 0x30725caa 0x43a034bf 0x3c576c26
+ 0x77fcf426 0xc360ce49 0x11bc4948 0x2e6dcbf3
+ 0x8b97bf44 0x6eb13c10 0x00cd36ab 0x96b6882c
+ 0x0b312e25 0x534ce45f 0xa6989601 0x6c6c7cdf
+ 0x55fcf9b5 0xea942bc0 0x8252c5ce 0xfd09785c
+ 0x229c3b7d 0xe7129a97 0x9f8db8fb 0xcf692362
+ 0xec8bd49b 0x5b8af7c5 0x020d4843 0xb93cf2c8
+ 0xedcd4fa7 0xf2a9574a 0xa90f2c74 0x5e07cf79
+ 0x0eec3c4c 0x7072b5f5 0x510792d6 0x903a8ca6
+ 0x0952d985 0xa48b5979 0xc6f1cfc7 0xbac813be
+ 0x736163ef 0x6c8e44e9 0x06d2bd0a 0x3fc587d5
+ 0x286e1d65 0x5b6555f6 0x275f8dcc 0x5edb3403
+ 0x412474ed 0x4e41ec00 0xb715c278 0x2777a192
+ 0x40ded494 0x319ec8a6 0xb39c0eef 0xfe4dafca
+ 0xa708b162 0x11d2111f 0xc2806d8e 0x2b631990
+ 0xfc59bb27 0x440667ec 0xc1c43799 0x4aa51bc7
+ 0x08ce990d 0x2425580c 0x9645de2a 0xe7196d6c
+ 0x08d4d524 0xcf4e772a 0x21c18347 0x5bd72d56
+ 0x883bf90b 0xbc262ff0 0x10cfdc55 0x18022197
+ 0x5f0ab36f 0xd689e2b8 0x1c69f462 0x48bba7d6
+ 0x0ab172cd 0xdf060504 0xf8973c1b 0x3206adfe
+ 0xb2cb1735 0xcd9a2237 0xa5fb46de 0x9ffccb44
+ 0xf10d190e 0x587966c0 0xc51151f6 0xadf04413
+ 0x3d06c31b 0x04ee4955 0xc8e0c658 0xc18cf4b3
+ 0xb8819010 0xca4f5220 0xe344f060 0x570b4cda
+ 0x012d0bbc 0xddd75842 0xa6785823 0x03817bbe
+ 0x0a36b9c3 0xa63ce601 0xb400ed89 0x54269ffd
+ 0x932e8525 0xe2e69e40 0xe58b54cc 0x719413e6
+ 0x7d4f6793 0x646d4539 0x697134ac 0x5e748699
+ 0x9c139a59 0x70481219 0x5dde0274 0x6360523a
+ 0xdbb51cc7 0xba4b4e11 0x963acf63 0x023187de
+ 0x7cafba20 0x720a2328 0xdfde4451 0x3f316592
+ 0x90a1cd0b 0x1efcf177 0x2670f653 0x5dc15d80
+ 0xf3f6b6ae 0x0a99dbc7 0x42fa199c 0xd007fb9a
+ 0x20fddba0 0x6a405776 0x729727cc 0xd241beb5
+ 0x68157d9b 0xe4757002 0x17213665 0x75a6352a
+ 0xf501fc00 0x1b3c2485 0x26b32b05 0x134c5648
+ 0x02a9493d 0xd09b71a2 0x37c03496 0x93cc61cc
+ 0xb540cb5e 0x97621e22 0x100e80eb 0xa1c6a6dd
+ 0x697d0e7c 0x50983ef1 0x94ade415 0x594c996d
+ 0x83adaaf7 0xcddebdbb 0x15d5084d 0x7f553445
+ 0xaa9b4988 0x7d2d6485 0x747505ce 0xcfce8f7a
+ 0x2460e3b1 0x8a9bae7b 0xef9577b1 0x9bd8aa4d
+ 0x0b39d25b 0x7ee75813 0x354d25f0 0xb3230a99
+ 0x4099e76f 0xef5294dc 0x749229d7 0x4a3628ba
+ 0xf3bc338c 0x27fdd85d 0x88710bdc 0x8019ae20
+ 0x03d2ba10 0x357d2071 0xa632494d 0x2b72e5dd
+ 0x66dc090d 0x7b4e6d16 0x5b8d04c4 0xa7188afe
+ 0x436cbfc4 0x6b06bb33 0x4ed3b64a 0x1f19f9a6
+ 0xb74c124d 0x035aa538 0x204e90a2 0x07f4a34e
+ 0x244c6e48 0x6df56192 0x98f6efda 0xf5ebfe38
+ 0xa2508e2b 0x41a8ba61 0x19076be1 0x265caeca
+ 0x5ae8330a 0x72cb54b9 0x01423f2e 0xbd26ddc0
+ 0x5cfffbcd 0x23a8a126 0x070d1b98 0x7849ee2f
+ 0x39809bf9 0xc2da255d 0xc13469cd 0xf6286206
+ 0x04077eba 0x201b7a33 0xe33b328c 0x15c3f97f
+ 0xb39eacf4 0x5d17c15f 0x206f29dc 0xa298d441
+ 0x0bc3d7d3 0x056b38e7 0x6dba2ddd 0x9215e8e2
+ 0xddb6a59e 0x82e17b35 0x58c5d983 0x7d71a528
+ 0xd9b3d554 0x4437e4c0 0x24752e5f 0x342dab09
+ 0x07976a7e 0x28aa6c17 0xfcad822e 0xda81303b
+ 0x47707d1c 0x94cb1a79 0xca4a5585 0x82db40d3
+ 0x418fab17 0x9f07d457 0x5fbf0969 0x3f6a9267
+ 0x10d09946 0x79fdb96a 0x02e3cf5b 0xcc1d33c8
+ 0x8d8b4306 0x4ea1f4e4 0xa1d6bd16 0x052652bd
+ 0xfdf0c3fd 0xd3c81915 0x31a728c0 0x713109fa
+ 0x75ade7d9 0x17f501f1 0x6a9ffc21 0xcbae22a7
+ 0x17b58e47 0x2df71e53 0x8fd029c7 0x8a14431b
+ 0xd017e657 0xe5227432 0xd60aa2b7 0x5ccf5cc2
+ 0x3637b99b 0x2fabd50a 0x253f3516 0x4c73647e
+ 0xf1c1a7c1 0xff49d9f8 0x9472bc31 0xd7ecbdfc
+ 0x13584a3b 0x935aa0ff 0xe8f1568b 0x6f2e93f1
+ 0xd0848d18 0xeaac770b 0x068d836b 0xd7cb7f30
+ 0x82557503 0xb2cc8fdd 0xb16524be 0xbee1c84c
+ 0x913f67a7 0x2cef225d 0x905c4bf3 0xeffa55a0
+ 0x17205823 0x7b33ad42 0x5eda3922 0x28764451
+ 0x6be1d259 0xdec153d8 0xdb9bd4ff 0x174833bc
+ 0x9b8bd1b2 0x752369c8 0x451085fa 0x0bcfe982
+ 0x5f9477e3 0x287b2a94 0xda780fc0 0xc0da6ca2
+ 0x41fc527b 0xa2ac493b 0xcab2f3ea 0x9a84c661
+ 0x4dc2d3a8 0x550fd8c0 0xd9d1774c 0x13777ae0
+ 0x5ba5ce24 0x729283f7 0x882e7a83 0x1c0ea2b6
+ 0xd6a25b38 0x0f14165d 0x1e0255f7 0x7086589d
+ 0x30e2c981 0x0e94cef8 0x92b2f0e8 0xb2e75616
+ 0x8c5b34a3 0xf6481b65 0x2ad413ba 0xe769ff51
+ 0xdfa4ebce 0x2b1b5d7c 0x8ce41a20 0x226d6e1f
+ 0x2892a50f 0xad3f3a07 0x65796c47 0x622bb66c
+ 0x990d85ca 0x3d229d65 0x7fd00f34 0xceda262c
+ 0x1d440bfd 0x3ca0dc2d 0x0f873c0c 0x7e58f266
+ 0x54ccb060 0x4fff4fe6 0x7b430464 0xbb021813
+ 0xc8f5afbd 0xd8c51583 0x17bfa087 0x3ab67c6f
+ 0x8a565d95 0xaf406a6b 0x512e9093 0xda8e4a62
+ 0x99e157a4 0x2f9b4633 0x9cd0dd79 0x18d48107
+ 0x4d288586 0x027c2541 0xc8e11802 0x9853a6b8
+ 0x174e39e2 0xb7661927 0x6edcde3c 0xe7d5b097
+ 0xbc01e85a 0x37f13dd2 0x8acca432 0x785467fa
+ 0xcb0a7227 0x13aa06fd 0xce63951a 0x63aeddb9
+ 0x60f5e939 0xeac8b8dc 0xad7c32ec 0x29bc00ad
+ 0x4a208a62 0xa5cd0c01 0xb7e6e14a 0x74b93978
+ 0x0cb98aed 0x1acf90d1 0x30a12963 0xe2faa3bf
+ 0x8a38e084 0xb506d79c 0xe9f5a398 0x49a1dc43
+ 0x649fe466 0x71fb0bd7 0xd37054ea 0x99eb2046
+ 0xf98bb913 0xa66dd966 0x3bf533d8 0xb90c0d94
+ 0xf10a44bb 0x4e24b124 0xab972198 0xb1c067e6
+ 0x51b5b660 0x25599615 0x7fb78acd 0x1186fb6f
+ 0x2e298a6c 0x64759710 0xea6346f4 0xd95be20f
+ 0x9dfacc80 0x54840473 0x20e25fd8 0xf477b617
+ 0x95108065 0x6853d6d5 0x934059ef 0x98ed024f
+ 0x2b9ab13c 0xebabf08c 0x455f3ccb 0xe16795ec
+ 0xee4f37ac 0x58c23de8 0x605bf91a 0x820606af
+ 0x49780126 0x3de6f2b2 0xd7163a54 0xe37fbd12
+ 0x42dc4ac8 0xa9dba6a8 0x2a52e044 0x6a3cd755
+ 0x0a50bd7e 0x7381e5ec 0x6113300b 0xca9ef1c4
+ 0xfcbf9fb1 0x02f2fe14 0x14ef8d92 0xaf3479f5
+ 0x5476e6ad 0x60f8a51c 0x9a48294e 0x6374a21a
+ 0x3aa905cd 0x0b7dfd0f 0x8c732396 0x32feb8e9
+ 0xa6f6b561 0x53b12131 0x3c33d3ab 0x9d21a63c
+ 0x47f0bf5e 0x2724a54a 0xaf9e8b13 0xdefa0851
+ 0x4642ee69 0xd1c53770 0x96ae6df2 0xcdec381d
+ 0x66cda20a 0x3118ab96 0xb976b2b7 0x26edfc39
+ 0x55935013 0x9fad6ed7 0x45828ac9 0x226cff75
+ 0x0fed2634 0xa1d814ba 0x072b1f47 0x8fffb2ce
+ 0xa09a6843 0x530673e4 0x4859b9bf 0x8187a24a
+ 0xe27981e0 0xe8f391d9 0x32589e20 0x37da379e
+ 0xad59afdb 0x183cd4d3 0xf7469108 0xbc628572
+ 0x7551944c 0xfee39d3a 0xde1cd9ea 0x7ef53855
+ 0x5d2b7e29 0xa62cdacf 0x1adb5a78 0xa40b54f7
+ 0x9668c5e1 0x191e0c4c 0x93a121eb 0x09531f1f
+ 0x96ba49f4 0x2d1e896c 0xba78f90a 0xece1583e
+ 0x6c15bc44 0xcf8f520a 0x9a9e83ad 0x9b6b6c7c
+ 0xbff862a2 0xf17c48ed 0xcc40b386 0x75379aa0
+ 0x6fcc78f9 0x5ee6d91d 0x60e2881b 0xc5a50f2b
+ 0xb0e21c76 0x77293b3f 0x4dc3c125 0x71e5e326
+ 0x752180b6 0xf6966af7 0x96b13f47 0x842f1470
+ 0xd3cebc0a 0x23931ca2 0x9fa82e41 0x1569625a
+ 0xab11f0fd 0x0dabfc2f 0x4f499d06 0xdf2f551f
+ 0x1d59c866 0x228b7c5a 0xcb5c338c 0xf779d337
+ 0x5661e179 0x57ee6674 0x92c67b12 0x2ab20094
+ 0x86443609 0x96c11603 0x52150c42 0xbe7a1a0c
+ 0x417323c5 0x8f535a20 0x0ee45abc 0xd831b3ab
+ 0x4b56c35e 0xadfca903 0xdb953e87 0x06c100be
+ 0xccd4e5a1 0x84b1eb7a 0x740cce47 0x61e9a67f
+ 0x873b3e77 0x7dbb260e 0x2837cadc 0x2f253b42
+ 0x7afe427a 0xe8ec3710 0x5900dbbc 0x2174e514
+ 0x84ea376a 0xdd3e79a3 0xa567abf1 0xdff5891f
+ 0x4b88082f 0x70d28e4e 0xb265f970 0x8fa57c8c
+ 0x6fb84267 0x1ffed689 0xc8dfaf03 0x593d6750
+ 0x5c96ee39 0x0199636c 0x415fb6c2 0x77ab0c5a
+ 0x7f3d0014 0xb51ef843 0xdcc02ceb 0x75cf2a1a
+ 0x675e057e 0x6fd4b8e0 0xc35c810a 0x0263e828
+ 0xb3b38e6a 0xeb6f1904 0x38e0e3d5 0xe56c97cb
+ 0xb9ab05fe 0x7d00aae0 0xc3e2f290 0xd17b0539
+ 0xab6b0d3c 0x01949b89 0xbde6d45a 0x3ea48534
+ 0x2585b3ae 0x20eaec0a 0x12165161 0x81eb9e23
+ 0xbf087042 0x769a37d3 0xbee94e4b 0xd82d0346
+ 0x95284516 0x9cdd530b 0x610188a3 0xe1cb1a84
+ 0x201023e8 0xa2b51aa1 0x5f793de7 0x7822f6b7
+ 0x3415fd61 0x80d0dbd2 0xeaa0b1d0 0x0647a151
+ 0x37a04153 0x64dd9b5b 0xbea43949 0x7ffc6b1d
+ 0x3ec171d9 0x16399842 0x0d539e5b 0x168772af
+ 0x50528a24 0x1ba46948 0x4d1c7622 0x7eabb87b
+ 0xe1f28f53 0xedfe9f50 0x0882e6f4 0x0b0e858c
+ 0x53202809 0xdd40481c 0x98f9548c 0xd305e7f4
+ 0xaa3a3b82 0xf5dfbd5a 0x7f3f0103 0x68d7e48a
+ 0xf9cbe6ec 0x0aaa6ce6 0x983430db 0xa93473f0
+ 0xab4a9fe8 0x5967af5f 0x2e4a1aad 0x0eb753b9
+ 0x5252c78f 0x20cc9e56 0x6d7d06b4 0x01ed2c54
+ 0x7458f014 0xc472083b 0x5ebc4b2d 0x11938115
+ 0x5609a0d3 0xcfccc47c 0x44c7215c 0xf87411c1
+ 0x22a92265 0xd2b00607 0x033ba680 0xb4ed58ed
+ 0xc58e4a87 0x60836e06 0x9eaff4fc 0xa0528e78
+ 0xfd20b0d3 0x02356e10 0xa047e404 0xa9283593
+ 0x54cdff7d 0x3eb1403e 0x9f4a7f56 0x670a19e4
+ 0x497d4c90 0x7d4b5b52 0x240ad44f 0xa8d2f730
+ 0xae53e947 0x566c963f 0x109b6ca8 0x27dd1a3f
+ 0x2c1c5ef0 0x796228e6 0x24220a88 0x008e2bcb
+ 0x74d45ba5 0xce0484fb 0x8160be45 0xdc3b4bb5
+ 0xc1cc6e3d 0x1f692d98 0xd4387a6d 0x6efc2aab
+ 0xdcad07eb 0x95be0966 0x58b6c364 0xc23613b5
+ 0xe911e2c4 0xd323a52d 0xba9a0937 0x026db7a6
+ 0xdcb5253e 0xc4d75876 0xfe7c5882 0x70cb8faa
+ 0x8fd4396f 0x71f19b8a 0x5c6d8137 0xaf3c55e2
+ 0xe4fa5eaf 0xb489bc28 0xe4059d20 0x7f776f27
+ 0x418d7e67 0x0560dd23 0xddc8a9f2 0x5d24cfc9
+ 0x9e0e807d 0x1baeba2b 0xd4085729 0x95604427
+ 0xa1b82a01 0x9ebf78b3 0x7da9a0bb 0xebad0bcc
+ 0x876ac5f0 0x50f5e56d 0x35bd1ac5 0x33ce5e78
+ 0xd0796806 0x28523eb0 0xe0e25542 0xd89e9c2f
+ 0xf6aa4a94 0xd9843f54 0xde1c58f0 0xa43b7439
+ 0x438c402a 0xb29e8468 0x2d8b8b39 0x3ac583c5
+ 0xad2624a0 0x2e57fd2d 0xbf4fd6b8 0x8f86a6ad
+ 0xee7b10ce 0xd6a0ff5c 0x796cc316 0xe9592c97
+ 0x78fb0448 0xeb7142a7 0xc23de330 0x510681d9
+ 0x34034a90 0x535cc5d7 0xbaafd38c 0x5d11e611
+ 0x58c99b2c 0x2eb95f00 0x8db62076 0xf49d8396
+ 0xae6f906e 0x7ac672ff 0xc82f6f2f 0xe04071c7
+ 0xc60fb70b 0x2d0065b4 0xc7dc4d8e 0xe5386450
+ 0x45de7648 0x4d9d9ed5 0x1ea63c26 0x7e65c525
+ 0x5a3aa43d 0x68d8ad03 0x125edc7f 0xe444712f
+ 0x04f20274 0x8e892ae5 0x790c0141 0x3589a296
+ 0x6615472c 0x923399e6 0xb796db99 0x36b70376
+ 0xfa59ef8e 0x580ed43f 0x770c41c8 0x0760ac46
+ 0x76755f0a 0x55272e71 0x64778d44 0xcc8e527a
+ 0x0863f548 0x2b42f2c5 0x20756bcb 0xf1753f6a
+ 0xaab7bc8d 0x8d58c65a 0xc2292ed5 0x92f5f173
+ 0x0ff9fbe6 0x805f2512 0x617a5b90 0x92532577
+ 0x152d0a3b 0x51c6273a 0xb467eb12 0x973aa5fc
+ 0xffd5fe17 0x9def8fb4 0xe5f9ee6f 0x3050215b
+ 0xa6c512c4 0x95fc2825 0x56b9c86a 0x296ff9f7
+ 0xd5bbd16f 0xfdd6408f 0xcab0ce03 0xa3a37242
+ 0x6fbc45d8 0x528f4f44 0x195c3aa5 0x3df1ddfe
+ 0xd705871a 0x6d525fdb 0xf2f0177b 0xe856b5f9
+ 0x5a62fb0e 0xa10c6b11 0x76c4de6a 0x620929d3
+ 0xc74465cd 0x70d6eb66 0xc789cff7 0x9b40ec8c
+ 0xf8d44b90 0x89467100 0xbf5de474 0xd93ffb76
+ 0xa77e0fd6 0x9a6dedf2 0x7a4b5bff 0x4353cc95
+ 0x19ad6141 0xe93efcc1 0x63716258 0x5dcb90e0
+ 0x216ed316 0x38e053f7 0xb2d11a29 0x401fb696
+ 0x0f60ff0a 0x59c96ce3 0x41ae78bf 0x11293802
+ 0xe2140131 0x06b3aaed 0x945a8a4d 0xbdc051cc
+ 0x12a396f8 0x86c84c40 0x2398465d 0x90831319
+ 0x4d8b474e 0x31edf74a 0x68605ffb 0xdbd5aab4
+ 0x03a20ef4 0xcb578309 0x55cf8de4 0xeb63cc3e
+ 0x77b6e657 0x9064c204 0x7e508ca7 0x51f9cc07
+ 0x2034a87f 0x9e8d6363 0x2347348b 0xb33811f8
+ 0x61059c50 0x6644040c 0xbb47186a 0x0b39b8a5
+ 0x719a5cb0 0xf6039950 0x890dc3a5 0xb2c3e909
+ 0x843ba28a 0xeeb824c6 0x0b0fd3c8 0xa0ae5b58
+ 0x5fc0fbad 0x869e0f43 0x8157a6ce 0x012ff9e2
+ 0x7aa0588e 0xcea70c7e 0xdbeb31a2 0x1cdc813c
+ 0x58772a19 0xd6ef8b39 0x211d0c2b 0x521336f3
+ 0x0748e0d6 0x31180d54 0x17f2e391 0x7b200851
+ 0x12a76efa 0x93584a83 0x59a26d00 0xf443aff8
+ 0x3a6c1c64 0xab949fb1 0x54bb06a5 0x818d1d12
+ 0xc69783c8 0x6effa0a8 0xd61c0c05 0xd76d617a
+ 0xf89c3b36 0xbbf2c9e4 0xefd5e16a 0xf239e70b
+ 0xe124dcf9 0x0ce35a7e 0x4e5de898 0xe898bb85
+ 0x0eda9543 0x189bb85e 0x3237d51e 0xa81afba4
+ 0x50e5417c 0xadfe8513 0xd00a97c3 0x7942e79c
+ 0x45a3f95d 0x38c92d7f 0x66b0fa65 0x88f34b2e
+ 0x945e83de 0x6fd718fa 0x09988ebc 0x185afb1a
+ 0xa4bc09ab 0x763ee195 0xd565b562 0x513d30cc
+ 0x4eca27db 0xab95cb61 0x797f0ba2 0xd1d17c13
+ 0x7fbdcbc0 0xf2680538 0x8b7d8039 0x545a92be
+ 0xf7e5dc0b 0x17ff40cb 0x91b1aaf5 0xa65cfaec
+ 0xe4b88f59 0x5d4a3d52 0xf649b8a7 0xe2d5240a
+ 0x5e4090d8 0xe8ceb64c 0x5e7604a0 0x87e50b84
+ 0x78baa4b7 0x8a134528 0xc130aa24 0xbadf6b92
+ 0x3996d321 0x13d44664 0x6c30618f 0x9546bc58
+ 0x440b2d80 0x4ab82baf 0xe605672c 0xda1e84c7
+ 0x0436c4e8 0xf1726cd4 0x380df7f4 0x76cff6ea
+ 0xec52b439 0xbd0acfa6 0x4a66c6c1 0xee77b3c8
+ 0x305e5ad1 0xe3df7a5f 0x6d3ca452 0xe2f0bb6a
+ 0x20aca9dc 0xff5f2785 0xaf1d85e8 0xd4c55653
+ 0x52bb24e1 0x54d928ac 0x07cd70ee 0x39274492
+ 0xf7baebc4 0x65071bbc 0xb73a6304 0x2a18402c
+ 0x04e85d51 0x0eb01c76 0x6f73e255 0xd392e3ab
+ 0x31ab0616 0x9ab8ba65 0xab2a2eb9 0x34934a78
+ 0xf8561348 0x2f6642b1 0x30261a32 0xb2a6c09a
+ 0x4a420e88 0x33557453 0x19bda003 0xaf4e76ba
+ 0xed9dc685 0x604c61a9 0x9725b972 0x329201c2
+ 0xa9b4b087 0x5e06c74d 0x9628fdb1 0xe6dc0d04
+ 0xb18577fa 0xa989c3cc 0x5b299fb7 0x36aaa3cb
+ 0x6b39a761 0x25bdf05f 0x7b7c71ba 0x8265ae16
+ 0x403fe456 0x96ec45f1 0x087b5470 0x217e734d
+ 0xe65c9541 0x688d43f3 0x5bcec90f 0x80e971c0
+ 0x62f76d35 0x5f9030d0 0xacefa05f 0x64ac9810
+ 0xd6667793 0x35f8565f 0xf7247bcb 0xc34e0feb
+ 0xcae60e22 0x728fffe8 0xcf6a16ce 0x8d4fac73
+ 0x8ad230fc 0x987257c0 0x8c7a1da5 0xa7dbda8d
+ 0x3c09c385 0x647f2867 0xf0b3b5dc 0x781eb0e9
+ 0x6244d05d 0x337bd6a2 0x77dd9e28 0xc48c5512
+ 0x883e4cfe 0x66ad74fd 0x1f659c37 0xd65bfb11
+ 0xb2389cda 0xdfdd6141 0x28888c3d 0x2e76ac3f
+ 0x7b21a7f9 0x5ceb1f5b 0x97f62545 0xaefe190f
+ 0x16fd077d 0xd558d127 0x1fe8a8a7 0xaab0dc71
+ 0x8ea4576c 0x17a8b8ef 0x7476364f 0x229b0ca9
+ 0x236b1e56 0x5c1bd152 0x20002652 0x8c0805cd
+ 0x4c122c4d 0x6cbd72db 0xa9d9d258 0x4817fa88
+ 0xc805adb3 0x227416db 0xd58adbb5 0x11cdd037
+ 0xc06e6c92 0x1c548525 0x8cbfab9f 0xa4b1c180
+ 0xffab2b24 0x186068bb 0x8983f63b 0x982997b0
+ 0x5abc10e6 0xdfd139c5 0x11c9b6e9 0x86cdfc81
+ 0x4f8010c7 0x1e1646b6 0x9d66a0d2 0x37c4239d
+ 0x8066847b 0xaadad61e 0x3eaf7caf 0x957e015c
+ 0x4d78bfc3 0x15c3fe27 0x6c2d2fc5 0x84af2a8b
+ 0x59a66a0b 0x3e13f346 0xe9874a62 0xa7446843
+ 0xdecfe92c 0x120cf098 0x1d188cb6 0xa4938e5f
+ 0x9023d7e1 0x8bbdb7db 0xaf452ce8 0x6854d9e8
+ 0x0604f218 0xd39c3237 0x3754ebaf 0x4ae59d90
+ 0x3913e367 0x99b1902a 0x78c06ff6 0xc177a4a5
+ 0x218159ad 0x01ec7cd6 0x5a6bda31 0x9a753f92
+ 0xecad36d9 0xa2216cdb 0x4fc8328e 0x879ac7be
+ 0x23f3f907 0x5b59fad8 0x122a1644 0x16e63209
+ 0xcfc827a1 0xfe332476 0x2b72bb15 0xd478caf1
+ 0x21deb5e0 0x3c1a561e 0xb59be4e8 0x4598f63e
+ 0x20194b01 0xb4d76ed5 0xb58e06d8 0xb1219a36
+ 0xdefe3946 0x0731248f 0xcfa09f93 0xe420d6e6
+ 0x8a0518ba 0x013d8f80 0xd32a05ed 0x7d9d8209
+ 0x548cb1d4 0x69457a2c 0x668a0a70 0x8cc2b661
+ 0xb72d4ad3 0x19b388c7 0xb844dd6f 0x4dc39493
+ 0x7e96565c 0x53959236 0x1dd4a349 0xe50914a5
+ 0x319844c0 0xddbb2abd 0x2f126ba4 0xa46c6d63
+ 0xd6829c4d 0x8f178677 0x8ae6291d 0xb5660702
+ >;
diff --git a/arch/x86/dts/microcode/m12306a4_00000007.dtsi b/arch/x86/dts/microcode/m12306a4_00000007.dtsi
new file mode 100644
index 0000000..c39fbd3
--- /dev/null
+++ b/arch/x86/dts/microcode/m12306a4_00000007.dtsi
@@ -0,0 +1,618 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x7>;
+intel,date-code = <0x9082011>;
+intel,processor-signature = <0x306a4>;
+intel,checksum = <0x7e23e5af>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x07000000 0x11200809 0xa4060300
+ 0xafe5237e 0x01000000 0x12000000 0xd0230000
+ 0x00240000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x07000000
+ 0x00000000 0x00000000 0x07091120 0xd1080000
+ 0x01000000 0xa4060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x9539a0b3 0xc7bb991d 0x308f0f1a 0xb1ba077d
+ 0x8bd7260b 0xd710ad0c 0xf82ee64b 0xe6f11ce1
+ 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6
+ 0x5fb36178 0xbc17d76b 0x31b7b923 0xc81aec82
+ 0x647b3320 0xf1db9653 0xff3b9759 0xe9c74b72
+ 0x3b193752 0xc147860b 0x160e0d6a 0x5bdb9dbf
+ 0x1ccce2ac 0x387670ad 0x2f106f05 0xf8607ea3
+ 0x42562576 0x30e086fb 0x409a06b8 0xf1957736
+ 0x5eb03f65 0xad147fab 0xe1a8e8b6 0x208d59d2
+ 0x683fba2e 0xf172b378 0xf8138dba 0x61e81d1f
+ 0xd551f997 0x28c79780 0x04f9db27 0xa80679b9
+ 0xaca4e7ff 0x6876944b 0x26d7dbc1 0x77f7dc2a
+ 0xf0bcb163 0x1b2a8e81 0x7b90aa49 0x8d5eaf2f
+ 0x522384ae 0xae7f7082 0x412ba10a 0x1ce1baa0
+ 0x478c29b4 0x9c09b4d2 0xf225f64f 0xd43026cd
+ 0x81098579 0x7df5db05 0xa5815bb0 0xc73ee756
+ 0x9738cb95 0xa5bd62e2 0x88e2c6b2 0x778e7fcb
+ 0xd3bdb872 0x9404403f 0x5be6ad63 0x71dc4abc
+ 0x11000000 0x71f0ab19 0x85635e57 0xfecdeb36
+ 0x7c93f457 0x13e3fb92 0xa512551d 0x6ac10509
+ 0x423fe38d 0x778481b6 0xff413c23 0x534d1d6c
+ 0xade61b9c 0x8cc43e62 0x0a8e5091 0x47382579
+ 0x8ee1d885 0x370915dc 0x8d8274f9 0xff11ba81
+ 0xb0919d7d 0xac434821 0x46d13494 0xe7fcc12e
+ 0x37876ec1 0x67a67b02 0x8d80b952 0xa2bdb26e
+ 0xf19c0c77 0x7b1f5296 0x544fbc2f 0xa8a3b1de
+ 0x8285fcfb 0xcab6dcc3 0x2a63f8de 0xab28edcf
+ 0x86e0e1cf 0xc21e5137 0x04616818 0x3172cc2e
+ 0x4a472e10 0xea8d7f3d 0x7e225494 0x7df2be43
+ 0x8a86b11c 0xf6894a26 0x81b6df9a 0x967c4076
+ 0x8c3e7b47 0xf81709e7 0x8bc622d9 0x4ed8aeae
+ 0x7cc696b5 0x45fb131d 0x77f322fb 0x4801173e
+ 0x056db13d 0x9a64fc3a 0x1508afa7 0xbb357cd3
+ 0xb863aa72 0xe57b932d 0x30892535 0x56a5e167
+ 0x842d402f 0x3113bd4c 0x04016ae3 0x7d81c983
+ 0xdeb79060 0x950e14e6 0xab7833c9 0x297e8abe
+ 0x49252831 0x489acc6f 0x9ed63fab 0x3166416d
+ 0x97319343 0x28ad40d7 0x3fbb9b52 0x203c7460
+ 0xe03bf6a8 0xbe288f65 0x8183b5d7 0x3752814b
+ 0x57405958 0xb4b3ab8d 0x235ba207 0x20bf3240
+ 0x9ea6da77 0xb8f77bf6 0x83d7ce90 0x5575d3de
+ 0x21f46a2d 0xaba56e91 0xb5657416 0x6ed3bce3
+ 0x1cf28b50 0x7e3f8573 0x76ed8028 0x8c785c22
+ 0x5a0fec15 0xbec7ac15 0x3763a0c6 0xd0fcfcdb
+ 0x39581ba2 0x386e0e74 0x4336b4a8 0x4bcc5176
+ 0x314b2da1 0x2ec76c38 0x2a517be5 0x17ce6f78
+ 0x7f124d6b 0xc68ce86a 0xac7d29f3 0x7ea7cbd0
+ 0x053169e4 0x4c0d5e6c 0xe39aa81a 0x083a39bd
+ 0x6d71ce68 0x7c50cc9b 0x10aa72b9 0xdd11c952
+ 0x43bea88d 0x9c1ddab6 0x41b013af 0x1e98de66
+ 0x554b92a3 0x86bac233 0x50fae8f6 0x358742c8
+ 0xa80c50d9 0xdfe9302d 0xc9b4c715 0xdb4b1c66
+ 0x78b7d75b 0xadde8aa8 0x59c09d74 0xa46b87d0
+ 0x548cc5b2 0xf9b8b729 0xa738e8c3 0x1c5a00e1
+ 0xd9c2d59a 0x8d1cc5de 0x05bae2e5 0x0ecdfd2e
+ 0xab3a984e 0xcf53db57 0x3ebc3c88 0x6b60e477
+ 0xa112a3b0 0x827400c9 0x9e7d8495 0xea378c48
+ 0xb19eaf60 0xdfe2da05 0x796b70f0 0x6c595e5c
+ 0xc0600c02 0x9e038536 0xea914072 0xa53e20b8
+ 0x30ab9653 0xb0bb4beb 0xce3d842c 0xb2a5cc91
+ 0xaa6f847f 0xe2aa1414 0xeede8231 0x067d99da
+ 0xa5638b21 0x27ac1f32 0x2231ada1 0x5ca081e4
+ 0x8e30a578 0x21f9f43d 0xc3b5ea88 0x1f1a9d74
+ 0xf7faba90 0x8163a801 0x09b1dcd6 0x3419385a
+ 0xd4ecb2e1 0x33e9df04 0xd5659af7 0x9eea6e2e
+ 0xf6ae859e 0x7c268181 0xaa07ea78 0x892c1c42
+ 0xe66a5fe0 0x9e7f5446 0xf18c42cb 0x49c7296a
+ 0x671484a0 0x3bdf31e2 0xed31d1d1 0xc2e8900b
+ 0x1175996c 0x70a0c04f 0x0394f2c4 0x070d9ca3
+ 0xc67229d1 0xcf29d228 0x4fd61fc4 0x92aa5df4
+ 0xa88afb58 0xb683a2c7 0x16239fe4 0x84bb685b
+ 0xb09cdc69 0x58be548c 0x99f0c940 0xa54bae2d
+ 0x108d7ccf 0x08773f13 0x4ba953c8 0xd290c27c
+ 0x9913f3be 0x8338ab76 0x4a51ca62 0xeb00862c
+ 0x03320962 0xd9bfb225 0x7e90e28e 0x7a86a4ae
+ 0x3a919994 0x91afec57 0xaef1a380 0x30ee8b2c
+ 0xb3dca7a3 0x26bb0fb1 0x36a18ed7 0xe0f1e5bc
+ 0xcd3c7b7b 0x6a3e7546 0x11fbb8ef 0x45800497
+ 0xd18d2714 0x5b2205e1 0x88903c77 0xb04c3c71
+ 0x8f52ca2c 0x3410f445 0x47847239 0x519adc73
+ 0x5e0b948c 0x0d8399f7 0x095d1fd0 0x001a43d5
+ 0xe806d835 0x199ff3d8 0x615fb809 0xa6d8aa7f
+ 0x64f3fdf1 0x6d048b33 0x69967629 0x2036eaf5
+ 0xd2514a6d 0x1719f81a 0x8030c9aa 0x3b1623af
+ 0xc8990859 0xea7d5f87 0x925fddd1 0x3470f55e
+ 0xcc4c6a72 0x4e94dba8 0x51861bfd 0xfc3aa50e
+ 0x65570977 0x615bbb67 0xd1cd8c1c 0xe8c52c28
+ 0xa4b1b599 0xef092f99 0x38c67c4b 0xa48b1fb0
+ 0x34bbdfee 0x162a0308 0x0118df20 0x839c54dd
+ 0x30c28bc9 0xd195aab6 0x14eecbfa 0x5292e262
+ 0xc4d26048 0xc8a7f725 0xb5be922b 0x540c734a
+ 0x12c53607 0x84a598b9 0x7c8418f2 0xe70c82dc
+ 0xa5f9f219 0x7023a821 0x7223e7ef 0xd63c008e
+ 0x29ddf8f4 0x586ac4ea 0x8f734809 0xbf22ff2d
+ 0x1c9b1aef 0x4249d5db 0xc4140c09 0xc927aae3
+ 0xf6c17d0d 0x822bd729 0x1ea56fbc 0x941240f4
+ 0x93a2e220 0x8596eba8 0xb9dc285a 0x58343237
+ 0x649f47b3 0xc214fb8a 0x1aceb84c 0x8a311f8a
+ 0x408e4b98 0xd0401a07 0x99fe7a30 0xdba70218
+ 0x6eabcecb 0x963f4937 0x4c980ab1 0xb1700cb8
+ 0x8762c553 0xed8d7267 0x96ef21bd 0x851452e1
+ 0x0cacc88c 0xb6320bf9 0x2c99e72e 0x98acaadf
+ 0x19c2f27d 0xe6a43a58 0x3b516fcf 0x643305c1
+ 0x28a991c1 0xcf0b9c6f 0x061e8030 0xcf1faf5c
+ 0xf5b441ce 0x0d00231e 0xab56cb21 0x28b7f4a0
+ 0x4fc8e58c 0x4860d87c 0x4b96bbdc 0x73f35c76
+ 0x81cb09f8 0xd80735f0 0x3dd494f2 0xce4517e4
+ 0x4c314ae2 0x4233cb18 0xf737b84b 0x1c745c08
+ 0xe0645e41 0xe716ddb8 0xec3c7c0f 0xa3667da4
+ 0x63533172 0x46598306 0xd34def1a 0xdf443342
+ 0x517cb001 0x917ed9ae 0x0d3070ab 0xf3d0431b
+ 0xc76ab146 0x7967163d 0x3f645862 0xa98a3610
+ 0xb17ec8b9 0x8809d7a3 0xbf98ab84 0x6addf0b7
+ 0x4a6ba3a0 0x4d377e62 0x5c13c16d 0x0657b882
+ 0x24bec841 0x639f476d 0x497db8cb 0x973ac543
+ 0x34ca0aa7 0x2033f4a1 0xf055d2ac 0x4f1e0605
+ 0xa06d020d 0x7e9d7b25 0x24dcf595 0x088c88f3
+ 0xcda1d4e5 0x2b9f9f21 0x4cebb038 0x4bfbaea5
+ 0xd51e9298 0x26dfd44d 0x419d2259 0x6b90a88b
+ 0x698ab356 0x78e59c8d 0xc9587560 0xe89547c6
+ 0xc92b0c0e 0x77a364ca 0xa7fb6e72 0x9e5f2f9c
+ 0xa825edb8 0x75d8d49d 0x227c61d7 0xbe75e877
+ 0x992628bf 0xcb5d570f 0xd55cb2a0 0x6b8ed5d0
+ 0x196f54bb 0x17d433ff 0xb089401a 0x89206c8c
+ 0xd2c5daef 0xafff07d3 0x07d1adf5 0x49b27ca9
+ 0x2e39157a 0x9bd214a3 0xe2409115 0xcefa1c6b
+ 0xdcb07810 0x41261e2e 0x665dfff2 0xbb315742
+ 0x65ef7d13 0x70b21c29 0x74507dd9 0x129c0ed9
+ 0x0ae1742a 0xd73c61ce 0x1e190eda 0xf74e3d06
+ 0x038fe01d 0x556d513a 0x3fcdaef6 0x6586fa4d
+ 0xd2d7e6ca 0x7e2e933b 0x120fa46a 0x894987a4
+ 0x4d5799f5 0x317bed63 0xeb8b2be3 0xcc927633
+ 0xff655d06 0x7535f440 0xb3281970 0x0f792db6
+ 0x53cde6cf 0x0db39a6f 0xef9eb25a 0x5e39ff58
+ 0x116b6c76 0x6faa29b8 0x9636bac1 0x42b9db6a
+ 0x5e1087f0 0x50cb3c88 0xbeae0ba8 0x5e2c536a
+ 0xf7817f0e 0x68a23d7d 0x4e5f95b0 0xb0c8d3be
+ 0xe765577a 0xe7f14c38 0x5cb0e2ea 0x6c760e04
+ 0xd4f00923 0x761dadca 0x26b3b752 0xfddd725a
+ 0x7a2d788f 0xd8895f45 0x26e4bf89 0x65f14803
+ 0x0d2e9b48 0xc3f70c99 0xf2c361bb 0x0623ca36
+ 0x1da1dc4c 0x5cf46bbe 0x5936d951 0xf3c7f826
+ 0x9fecfbaf 0x7461ab85 0x0d544474 0xe4120a8f
+ 0x569d033b 0x948b12e3 0xdb41b453 0xe9762a09
+ 0x7f2ded9f 0x6c25dc18 0xd2acdbbf 0x23ed04a8
+ 0x3b56bc43 0xbfc5d268 0x2fd5c405 0xc7b2ea06
+ 0x5a546023 0x30e9040a 0xe3c7722d 0xcf4ca6f4
+ 0x5f32c333 0x32f07d3d 0x45b9d4d6 0x9c41af5f
+ 0x5ee9a9c8 0xc3e280fa 0xee575013 0x04e0607a
+ 0xdd94800f 0x8292d93a 0xff10e469 0xcb706918
+ 0xdaa9276a 0x4d91add9 0x8e1ebb82 0x67452108
+ 0x49b22b5d 0x70b810a6 0x4497d9b4 0x86cd0335
+ 0xa691d65e 0x824db77d 0xeb09d413 0x9b723ebc
+ 0x896dc436 0x64780810 0xc5e34ef7 0x4f108f18
+ 0x8b55065e 0x4ef522ae 0x2c781bd0 0x32088deb
+ 0x2e052408 0x9b78cbec 0x4aed1bc3 0x31db2739
+ 0x89eb6695 0xf3df3627 0x576645df 0x123cff77
+ 0x1acb1522 0x246e719e 0x8baa34cb 0x6ba43aea
+ 0xfb057ac3 0xc87040a4 0x3d3ab58c 0xe9442e38
+ 0x89ce6ecf 0x3fa669c7 0x58919e44 0xa08a2e58
+ 0x8fd1fa50 0xc087b003 0xbfe787e3 0x5678b75a
+ 0x911fb37b 0x9942a375 0xcffeac92 0x24388c2b
+ 0xfe481ed2 0xf6e322dc 0x48cc215f 0xafdcd948
+ 0xbcd97425 0x655694bb 0x970a5b10 0xef8c398e
+ 0xb8171bbe 0x99e739c6 0xe169b100 0xe56c5c42
+ 0x8190cd45 0xf8d2b2dd 0xe1e981a6 0xc0c2aaf0
+ 0xc5c0baa1 0x6ce19d37 0x839d230a 0xfb84b2af
+ 0xf52b9069 0x903c39b2 0x97c52d92 0x71d78be4
+ 0x9bbb12c5 0xaff3990d 0x575fdc6d 0x7e4317d7
+ 0xdd1f9b49 0x24903168 0x2007fa4f 0x4abe4f6d
+ 0x263e39fa 0xb7e24055 0x93265f6c 0xe183e382
+ 0x2b19046c 0x185632e5 0xa024df44 0xdc7b6a40
+ 0x31c97b5a 0xd1db7afb 0x7ff27636 0xbdf79391
+ 0x5148a6c2 0x9fcf91f6 0x814f4f72 0x5a60d42e
+ 0xed3f9a1c 0xbcc0fafb 0x262ffcc6 0x041f2aa2
+ 0xa9bcdfac 0xc5897711 0xf39b154b 0xe8bb2687
+ 0x68c411aa 0x67e3cbc1 0x544ddb04 0xd248c866
+ 0x9b107e9b 0xff6b8cd8 0x94dd2262 0x1a7dd15c
+ 0xea03e879 0xf534244f 0x84485354 0x35225d96
+ 0xb58c8b19 0xc64cf0e5 0x7305411b 0x80770715
+ 0xbfc71f00 0xb962ccc0 0x21bdf0e2 0x048bda12
+ 0x2102ac9e 0x64e889d5 0xbc30eb49 0x03eab004
+ 0xabe124a3 0x58a41ae7 0xd945ba34 0x7d485b3b
+ 0x013ccf7f 0x487df444 0xae74b9de 0x4828972a
+ 0x97bd1ca2 0x28c64e58 0xbee11d3f 0x347652c7
+ 0x37814af4 0x99b7adc4 0xf6ebab70 0x07aa21ff
+ 0x64174862 0x467de331 0xb6a88187 0xde63b3c2
+ 0xcaec36c8 0xbf4f3de8 0x9bd70e15 0xdf4b907c
+ 0x640f2594 0xfaee60f6 0x9480c381 0xcb4e0996
+ 0x03b30491 0x055c512e 0x512e5b67 0x3c0c5209
+ 0x84c9c0be 0x069907cf 0x49d4a871 0xe5fd978a
+ 0xbd7ffb3a 0xfaf9643b 0x119bd155 0x4eebc032
+ 0xf12cfed1 0xae23dc3d 0xbf9472dc 0x0c9f240e
+ 0xa376c5b3 0xbc168e61 0x715ee9c8 0xf0d3bf95
+ 0x951f938c 0x17a1b2f2 0x998b2c63 0x5f6bef20
+ 0xc364fb8b 0x90d9863f 0xbb65674f 0x9cf94066
+ 0xf4a43b1f 0x9e5f0a13 0xae62623c 0xf445c858
+ 0x4021ed28 0xf1562704 0x0e1c1596 0xe9cd23ee
+ 0x28131eac 0x5406abd2 0x7f599eb8 0xaf471f70
+ 0xd275f6dc 0x5ff75a54 0xa82c13b9 0xa2b0a583
+ 0xbfaffd3c 0xac5342f4 0xf0e1963c 0x993dbaae
+ 0x3d0cd111 0xe9ee6ce3 0xd85f5004 0xec8f711a
+ 0xafcfb6f2 0x6926e1c1 0x0f1a5e40 0xc002ec74
+ 0x83344203 0xffdacd7f 0x1f2efcc1 0x8b511582
+ 0x013cb6f8 0x7781d777 0x4aaaab9f 0xa2223fd6
+ 0x07c2557e 0x27ca061b 0xbe94f543 0xfa94ff76
+ 0x03ab13b7 0x69bf8a84 0xbcb641eb 0x5e89208b
+ 0xc4e51876 0xd58dd9be 0x4ebdf2ac 0x14b79754
+ 0x8cc79438 0xb6d37437 0x6b843097 0x0d11bde4
+ 0x2ef0fd04 0x788b3007 0x6feca051 0xe147b98e
+ 0xa6b9139c 0x9446b26d 0x4920adab 0x7cb94980
+ 0x5ff17b2b 0xa22b81ea 0xce5e999f 0x7d4173ac
+ 0xd99aa4fc 0xebec0bf5 0xf10d6c52 0x5d97f82c
+ 0x0738353b 0x208e43a6 0xcec8ddb3 0x999847e8
+ 0x10d94541 0x68d5c5a2 0xee34f623 0x86536280
+ 0x4f4e5bc0 0x4e569e0e 0x4c7d1738 0x427d42c3
+ 0xaa94a27f 0x8bfff36b 0x036d1073 0x2ebe67f1
+ 0x85f8e9d5 0x6b7c5425 0x4ef72dc2 0x8b89450d
+ 0x20011c1f 0xebd91d71 0x16c0ba50 0xd7c10f19
+ 0x46c9ca67 0x23787788 0xe8175e53 0xebe05e52
+ 0x3303af3f 0x6b058a55 0x3f960abd 0x8d362407
+ 0x33415c6f 0xdbad54d0 0xfd473812 0x9394e4c2
+ 0xac3c803a 0x489113cd 0xeb749070 0x4f813729
+ 0x1f83102e 0xda39d44d 0x2f995892 0x178549e4
+ 0xaa04838d 0xc08bc6f2 0x8e965361 0xe5633efb
+ 0x39927e9f 0x5c7d5014 0x783f5048 0x1c872f55
+ 0xe41ba625 0xeacfc296 0x1e1202d9 0xde9fa0a6
+ 0x1dac6dd6 0x6eaa865d 0x09f40fd9 0x9c8d9647
+ 0xfc8e6645 0x77626236 0xc61d1276 0x59948fa3
+ 0x0296fd66 0xcf07611f 0xc27022bd 0x34aaa9c9
+ 0x0ad7b71d 0xb13ec602 0xabd244cc 0x3d3387f0
+ 0x5a9f9fbe 0x11e4971d 0x38f0a9b2 0x44bc7933
+ 0xaee55dfd 0x9a5c2137 0x8d3a85e0 0xf748d910
+ 0xe25eb57f 0xb3dbafe4 0x386b0f20 0x767872b5
+ 0xfd675769 0x34ba841f 0xf7604e1a 0x99572947
+ 0x72fcc0ed 0x8f914e81 0xebd404de 0x29c263bd
+ 0x10978d02 0xea57338e 0xe7aa0d47 0xbd4a124d
+ 0x4fd7185a 0xcbf7f9c2 0x567f4318 0x96b1858b
+ 0x0f24fc24 0x7ac200f4 0x688ad1fc 0x8bc3b74d
+ 0x275ae45a 0xd4dcd957 0x4898351d 0xedd41253
+ 0xce413d09 0x11df9297 0x4ee35a8a 0xb3e506c5
+ 0x6f43f262 0xf7cf6cb4 0x7c87a2c3 0xcf4b7cb4
+ 0xb7f72f04 0xc21d35bb 0x570fa807 0x4a500ff0
+ 0xd157fa61 0xace9ab6c 0x66b98d3f 0xdd59c459
+ 0x5a8022fe 0x72122376 0x507806be 0x73e4b7be
+ 0x4a88e7eb 0xef72d6fb 0x57ead7d1 0xb7a2eb21
+ 0x327830ab 0x874e0b86 0x17c27b5e 0xdf7fe64d
+ 0xc07f158e 0x506a5a1c 0x8e2ef0ad 0xeaeddcfb
+ 0x76d5d48d 0xf20a01de 0x62454d95 0xc5ee387b
+ 0xc3b17190 0x00136ccc 0x988abbd8 0x57c6ad77
+ 0xde70f835 0x01fbc472 0x99b4822f 0x00fbf0bf
+ 0x6e919c0b 0xc5fe1ed5 0x5ff3ae66 0x5d42c098
+ 0x59bd5712 0xb06fc973 0xb6093014 0x5461dac8
+ 0x3139ddce 0x55f239e6 0x55541931 0xf184d3f8
+ 0x1127627c 0x7e1b4676 0x3ab1d112 0xad8c4549
+ 0x01170df7 0x62e25822 0x551824ab 0xb2f82a7e
+ 0x15544a0f 0x24fbab9f 0xe3675302 0x89dde28e
+ 0x6dce0a37 0x3dd7b171 0x8d04e91b 0xdd8d2640
+ 0xab0db01b 0x166f8408 0x3a4dd9b1 0x0f6e0e71
+ 0x4f322f5c 0x39343841 0xe07bca48 0xaa135ce5
+ 0xb12211f2 0xabfccdf5 0xebf7f510 0x6773c043
+ 0x763601cc 0x0a49fa28 0x9a7f8f6c 0x8e1b8ef6
+ 0x41f434c9 0xc673a8d3 0xdb67ca50 0x784cc5bc
+ 0xb4339d90 0x1b331afb 0x0419b04a 0x76983ccd
+ 0x2f4d56cc 0xbd1b0920 0x605f7579 0x95b26082
+ 0x5d1af353 0x9aa19300 0xacbbfd43 0x71d1e615
+ 0xf9037ea7 0xa14464f4 0xac987389 0x113ad6f6
+ 0x9ca375fc 0x98fd00a9 0x7707ddd0 0x5678ab5c
+ 0x1c6ad080 0xd8c1e89e 0x2c71d71c 0x074f1a5b
+ 0x759a03b7 0x96534362 0xbb944132 0xb55e5eae
+ 0x4bfccb91 0xa24def46 0x591d5740 0x94c6b99d
+ 0xfb2074f0 0x494e6f1e 0x52ae5274 0xe1d49c1a
+ 0x92f03134 0x1759bf52 0xc392bce2 0xe6c2c774
+ 0x521055c3 0x18329921 0x83308d98 0xba7b3f54
+ 0x704d6822 0x24e562f1 0x494a8992 0x3183e726
+ 0xef86b2d8 0x79b3fc8c 0x56eab200 0x8602ae41
+ 0x900a3613 0x5100f884 0xe216a6eb 0xe227a887
+ 0xfe9fd01b 0xf3ba709b 0x5ea4d2f3 0xfec8ee3c
+ 0xeddf6d69 0x0d6bc870 0x94c1b0d2 0x21686063
+ 0x375dba2f 0x0865ab2f 0x01628907 0x170ab107
+ 0xe909ef36 0xe9c260dd 0x2522609c 0x9a5956c5
+ 0x1e494cec 0xbf0e6c6b 0xf8868417 0xd664e19a
+ 0x524733db 0xfb9c9b70 0xb98bbbb6 0x08083c38
+ 0xe5d80347 0xee79b62d 0x01387fac 0xd26d87c4
+ 0x5fe568b5 0x96a82fda 0xca66e58f 0x2579768c
+ 0x63116536 0xe959d2e7 0x0f854cf9 0x4eabe9b6
+ 0x5ece1cd3 0xd14b79d5 0x16d43031 0xc3eee230
+ 0xe5f8dce9 0xc435d411 0x66c30e0d 0x78815b84
+ 0xae738a85 0xfcb680dd 0x1158c848 0xf83499e3
+ 0x2427441b 0xb5de1525 0x908ffd2e 0xd0c325ab
+ 0x6972ce23 0xe14dde3f 0x9d6a5c5a 0xc81ae057
+ 0xe775239e 0x80d9d083 0xb758aed7 0x4b0a960f
+ 0x95d421b1 0x8457d800 0x7fdf0f33 0x6a8da972
+ 0x5a1e43a6 0x7075b383 0x1a56e8df 0x6881ef0d
+ 0x927e4a53 0x2b229988 0xbf955c6b 0xddb168e9
+ 0xf4c3a41b 0x7f5aaeb2 0x3703df12 0x82fefc6d
+ 0x9072a83a 0x15912eb3 0xc3b709b7 0xf2688911
+ 0xff761108 0xa9bc129e 0xa8b7185c 0x3e18a6bb
+ 0x9ad22d22 0xd89c2d61 0x8a77f5f5 0xdc62e278
+ 0xf9225008 0x3af51072 0xcfe039cd 0x443d7dea
+ 0xf11280f2 0xd537ef15 0x8a563c9b 0x977ea6a9
+ 0x5ae7791b 0x8767d5ec 0xbc1c4c2f 0xb0fad47b
+ 0x056607ee 0xe3064364 0x67d8a4b0 0x14c60ef1
+ 0xcd5881f0 0x115caf21 0x2f85528f 0xe002c620
+ 0xb6c7063f 0x97ecc4fe 0xf1767731 0x04e5ff88
+ 0x8a4ae2de 0x61908c05 0xc5eafb5f 0x160554d5
+ 0x10f4891a 0x346f5021 0xbbcfa5f6 0x0def8165
+ 0xb2dec581 0x79e35980 0x6f2837f5 0x3db025c2
+ 0xde12696a 0x33f0d559 0xb7666011 0x1ddf70d8
+ 0x95116e31 0xc283742f 0xf7c090a9 0xd6c35acd
+ 0x1b59fa95 0x40d6a440 0xf5124a8e 0x851b2eb5
+ 0xe23f909e 0x51e7d43e 0xe8448ad2 0xecebb43a
+ 0xba214d3f 0x8668acf0 0x3af07c0f 0x5d522cb7
+ 0x18e1e776 0x13d1c118 0x8eae9d53 0x9abb258d
+ 0x4b5d4b48 0x4395da72 0xb8b3e620 0xaf1be0db
+ 0x5dc55eba 0x1bd22e25 0x557a72d0 0x163e00f7
+ 0x61188e81 0x258a2c1e 0x0c4276ee 0xd7c0f6cf
+ 0xcae90383 0x6b9a226d 0x130005a9 0xde508db5
+ 0xaa834c3c 0xe07538bf 0x5d5c9640 0x09e5e3a6
+ 0x925b2f59 0xfc0c262c 0xb3fe8482 0xd55f9dd2
+ 0x18824ddd 0xcca0e20a 0x58f5e91e 0xbe9bfc6b
+ 0xed8fb482 0x06272330 0x58049c9c 0x746c2ec4
+ 0xb3f7560c 0x28cafafc 0x537795d3 0x74198ba2
+ 0xe74e67f4 0x77294fca 0x3af10e99 0x8e19bc12
+ 0x6518d98d 0xf770119c 0x30dfee06 0x171175c1
+ 0x2834cada 0x38dc4780 0xb1a8873e 0x47a626f2
+ 0x790e757c 0x71d5196b 0xded342ff 0x4fce9787
+ 0xae6c198a 0xb26100e3 0x758992a3 0xc9021e08
+ 0x54de129a 0x793b2e40 0x78d5e95c 0x6f433a46
+ 0x49264de9 0xe155bf0e 0x3bd4788b 0x7b9291ec
+ 0xf80b3c50 0x5ada3b87 0xd1a7b055 0x4cb0eb44
+ 0x4f712378 0x36bc14b4 0x7bd0b6b9 0x62920554
+ 0x780ea525 0x1c74f629 0xe1431d38 0x4ea1ff33
+ 0xba9ad4ab 0x6b8113fe 0x0022a139 0x835303e0
+ 0xfa39cff6 0xe45918a5 0x844484a2 0x55b42e18
+ 0xf14cd964 0xb65c5efa 0xd04e9cbb 0xcba8edf6
+ 0x2dd6a76e 0x1d5da1ec 0x9329bd8b 0x527d6e4c
+ 0x956956fa 0xeaba1ade 0x9125ddfd 0xd6f09a18
+ 0x4d2db260 0x8c8b9e8d 0xca95ab0a 0x5bbe0573
+ 0x7310a64b 0x4d5c4c73 0x0a2f0b12 0xaf9bf6c7
+ 0xc9687aa8 0xe5a2a604 0x54ec3dbe 0xf4256cc1
+ 0x405fc417 0xa19ca399 0x93531bda 0x595298c7
+ 0xa28dfa52 0x7385a266 0x027dc36c 0xcdb82903
+ 0x5ce4b82c 0x98977244 0x0d4cf474 0x99236465
+ 0xb67a8672 0x1e1fee2b 0x38a75771 0xfb017ac3
+ 0xc04889d4 0x93753894 0xa9603439 0xb37a2ca7
+ 0x8491a2b3 0xdf1cad03 0x6717cc79 0x9f8bacae
+ 0xa053641e 0x8383fb3b 0x0229b112 0xf9d2a0f0
+ 0xb578ff0e 0x79a48f10 0x33a2f133 0x8d9a77ae
+ 0xd931bc20 0x6629f839 0xeb0e4ada 0x2b8c1290
+ 0x2c3aee9b 0x324eef42 0x13b50a02 0x059aa872
+ 0x8ac20f06 0xd2d8eb70 0xf575298c 0xca65765b
+ 0xf7a92001 0x9bb5dec8 0x49b44f85 0xa3f93611
+ 0xf2d51bfd 0xf8e42618 0x03d9a8dd 0x34526d3b
+ 0xa3b9112a 0x385ff261 0xae991c2f 0xdd990afb
+ 0xf10471f1 0x842b7feb 0xc959bba6 0x51db24ca
+ 0x7af01558 0x1abc2242 0x8adea69a 0x77140ced
+ 0xd7fa451f 0x46c48f08 0xf19545c7 0xc571c2a0
+ 0xd24188c2 0x2da3f8c2 0x035b1847 0xcfbccf6c
+ 0xe4e6123e 0x56967bb0 0xb0187725 0x1e98dd1f
+ 0x2c5f8b17 0x42ad6c44 0x7dc0cdaf 0xbdbc7762
+ 0xf926a4fb 0xac0b9ea6 0x7108af88 0x335f4e85
+ 0x174ff319 0x08263330 0x9ab6c830 0x2dca63a5
+ 0x479bf730 0xc8187fd6 0x97daf5aa 0x66f9147c
+ 0x448b62b1 0x9db3dfaa 0x4c0abeec 0x3eb5e03b
+ 0x726606d9 0xe2c3faf8 0x8bf2f174 0x6395c1fb
+ 0x1e84bf32 0xfb452586 0xee550d69 0x40858cdd
+ 0xf454cd26 0xefb81d50 0x3c879cfc 0x41a58812
+ 0x30338aea 0x42288f92 0x4a4980a6 0x40556e1f
+ 0x3d14bcdb 0xd6509d13 0x494d8e13 0x05ae949d
+ 0x1d8528cb 0x40c73cb9 0x24e60bba 0xbdd52ae9
+ 0x4aa0fc29 0x5f01792b 0xd0d13875 0x7c3553dd
+ 0x41a52955 0x0325f0f0 0x49ba411c 0x05d30bd1
+ 0x2af8ea4b 0xf91e6a39 0x17054898 0x33516ff4
+ 0xc62cf75c 0x301a0459 0xc18857e3 0x78f05585
+ 0x07eee4db 0x014c9d2d 0x5e67a82e 0x9babf458
+ 0xb7ada3a8 0xb4c978ea 0x0ac14e64 0x6c47ff91
+ 0x9900eea4 0x1ba7c285 0x51c7f0e4 0x64d8f725
+ 0x0f0cdc9c 0x69cd6c3a 0x37589cc1 0xe9bcd133
+ 0x23b39134 0x205ba564 0xc00dbffb 0xf01c3680
+ 0xada1dfc4 0x3494c547 0x34f95b08 0xfaff44b5
+ 0x8a2b6e4a 0x579f3f04 0x7cedfc17 0x41ef4344
+ 0xe786cd57 0x5ddfbc7b 0xecd5c628 0xfe55a66e
+ 0xa68bcf08 0xd69384d9 0x9cfe6968 0xa98b01b1
+ 0xf569ba00 0xdbb51d1c 0x3df4a346 0xf913cbfc
+ 0x8b156a28 0xf95684bc 0x5bc070cd 0xf6b27548
+ 0xe7f9c2ae 0x9233351d 0xa9ba9381 0x632c9197
+ 0x6dbd7022 0x67b448df 0xbb62f843 0x6a712209
+ 0x03867759 0xd7baeeb4 0x5104c12a 0x11f9e0c8
+ 0x9fae9186 0x46c17ca4 0x33b16593 0x20308078
+ 0xdfebe428 0xac27d933 0x59cff948 0x60eae57f
+ 0xec308135 0x2a2b3da3 0x47c74c7e 0x24dd1bac
+ 0x11f67090 0xd2b37df5 0x2367170b 0x08b3ce06
+ 0xfeef940d 0x46cd6519 0x6685cee3 0x23244876
+ 0x5929c779 0xf8fd52b5 0x7520251b 0xbe64ea34
+ 0x594ba72e 0x8a522818 0x3a563759 0x448dfe58
+ 0x28b8193a 0x8b898a6d 0x26b1864f 0x94b9a512
+ 0x58c57299 0x326b3c96 0x3073f0c2 0x5c9623f5
+ 0x69e2d14d 0x06c69b27 0xbae70a29 0x77120eff
+ 0xbd57a135 0x3182e024 0xc48ce0fc 0x889476f2
+ 0x9c5c428e 0x18243a48 0xf226e200 0xa434bc0a
+ 0xc31975ba 0x7a7ff48c 0x6e459a3b 0x171057cc
+ 0x7e4cacae 0x6e2d9566 0x4a253a89 0xb26b3cab
+ 0x342ba69c 0x03c13ba4 0xce667e63 0x32250c84
+ 0xb15f105a 0x436c5c66 0xdbfd79b1 0x090ca274
+ 0xa3f5ece3 0x4b3b4650 0xa41a96b2 0xe527bc5d
+ 0xada0de6d 0x87e5a944 0x5d99e654 0x3cc3d95c
+ 0x67c2e1fe 0xa05b8205 0x5fe902ef 0xcef05b37
+ 0x1081e4f5 0xe381012c 0xd4953b82 0xacb344b4
+ 0x278b5104 0x9e8f6f53 0x539cc1cd 0x55a16099
+ 0x235f5ac5 0xcaed439c 0xad386728 0x5d2656fd
+ 0x50e1622b 0x76422754 0x88c2a109 0x6c5faaa8
+ 0x413faaa4 0x8e64eca2 0x1c900d41 0xab89b33c
+ 0xec9e418a 0xcd7d4db8 0x65a17ab1 0xbf52c694
+ 0xeecff735 0xa540d8c3 0xaa45a930 0xc0070502
+ 0x18f8e76c 0x0d0958bc 0xf5c2aa4d 0x1deb8b87
+ 0xb06edbcb 0x50228379 0x600947b3 0x99f01bc6
+ 0x9290adf1 0x3353fa5f 0x5256cbef 0x19c196fb
+ 0x822b7e48 0x5400d0c3 0x12fe150f 0x5ada541a
+ 0x410eea57 0xc34b0ac3 0x3a7ea361 0x3dfdbc15
+ 0x3d2ae574 0xd3f41956 0x79bcebc8 0x85681660
+ 0x27855dc6 0xe61bd8a2 0x47eee402 0x7e6e74c9
+ 0x0e1fd6bf 0x6ff32cb5 0x40da8747 0x85e02a6b
+ 0x9f7d9a5c 0xaa512efd 0xc6673d19 0x8218c318
+ 0x0fde8712 0x612ec9c8 0xbd40745c 0x2daf88a0
+ 0xad6e44c6 0x2e087d9e 0x1652702a 0x4fd9afe1
+ 0xabe830ef 0x08dd3913 0xce99af5e 0x2ad29258
+ 0x2d2bb1fc 0x4cd05f07 0x86c1d313 0xc121df89
+ 0xdc34b9d7 0xcf66a60b 0xf4be35c7 0xaea67507
+ 0x0905d5b2 0x6e6aec02 0xa4ed411f 0xeaada4ec
+ 0xf548fe2b 0x4a2e9a7f 0x8884168d 0x7b3cd8f9
+ 0xe380c72e 0x6332531d 0x96228e28 0x0d019478
+ 0x38b0bba7 0x3b35de12 0xbd8cf061 0xc40be0db
+ 0x308f624f 0x014dce9c 0xdc9d4c1c 0xe7cf4845
+ 0xd3c3cb56 0xd273eca6 0xd4574a88 0x47df611f
+ 0xeea7b70e 0xdc4b81b8 0x1f3adf2e 0x695634c6
+ 0x249ef15f 0x7b2b6dfa 0xa39a7367 0xf3cc99dc
+ 0xe0743236 0x6e00ecef 0x4bc24c6b 0x557ca804
+ 0xbe759d03 0x0eb2c5c4 0x366a6da4 0xa40acf07
+ 0xcaaa7952 0x63dd5b89 0x6f09f54d 0xc598a3b8
+ 0x818270a9 0xe85e2b53 0x6d437ced 0x3301c4ff
+ 0x8950ff23 0x88e3303d 0xf3b7c745 0xd823996d
+ 0x2a4caebc 0xa1eb7e2c 0x960fa785 0xa5d9192d
+ 0xb771a75f 0x6c17bda4 0xa4c62290 0x01f559c4
+ 0x5b6bcb90 0xbdf4e260 0x37d24146 0xe9f7c113
+ 0x224c8d1e 0x944f0d14 0xb7a446db 0x470e1bd8
+ 0x5b4553b1 0x9713ed1f 0x3bb0621f 0x5d13ccd2
+ 0xd1512876 0x92172e03 0x80d4f34e 0xfd03a89e
+ 0x82de677a 0xe72e0a3b 0x593b0502 0x7825be45
+ 0xa765c6c7 0xddef9369 0xd449c6a6 0xe4440203
+ 0x8be34a5c 0x22617938 0x6eaacd0b 0xd0b47183
+ 0xd39589f4 0x3159c597 0x76a0a4ec 0xf434b1c5
+ 0xf3a26de7 0xe9b69e3c 0xceb232f8 0x7bc91c43
+ 0x225cfa3a 0xdbabb166 0x04d4782f 0xd573884a
+ 0x351f5f88 0x4acda1e6 0x2cb93b68 0xed4b0663
+ 0x1dd147b0 0x4b64aa81 0x9baaddd3 0xdb305d03
+ 0xe44403aa 0xd52140b8 0x442e2197 0xfb8f8aa2
+ 0xa1d2b054 0x30ac7b0e 0x535ff138 0xa34c29fb
+ 0x4dcff8e5 0x4d4b5af7 0x75846d8b 0x29060275
+ 0x154f0dbc 0xf506c696 0x18706d08 0xbe1cddfe
+ 0xc972edf3 0x070f4aae 0xe5055290 0x12ff9063
+ 0xe4b81a09 0x11ad8348 0x184faea6 0xfe9b3674
+ 0xd8a68c8c 0x28366da2 0xd0729297 0x8c07e77b
+ 0xe85cb507 0x54d582d1 0x0e10aa56 0x5f79aff3
+ 0xb5c2f58c 0x0976ca59 0xd43bed61 0x9e76951d
+ 0x4bc2542e 0x7a1870fc 0x2cd01266 0xcc717daa
+ 0x045e2757 0xa5b943c8 0xbbb21e51 0xa19b070c
+ 0x985e3e58 0xb0f22523 0x1dfac693 0xe2491946
+ 0x649791b6 0x54d4f8fc 0x2920c0c0 0x45af983c
+ 0xd400878f 0xbf94ce47 0x00dacb15 0x8f79afc0
+ 0x96d4d1f6 0xdacc4fee 0x3eac2a87 0x89f808a3
+ 0xa8963eb3 0x3bfbf9fc 0x16970a5b 0xdc925ecb
+ 0xfa5e4920 0x219ffbea 0xfb442d8f 0x32a5d657
+ 0x7db7483a 0xfb330167 0xe75f7f87 0xea1de0e1
+ 0x764b080a 0xed1eab80 0x6b75f59a 0x8dceba7f
+ 0x735a7fce 0x68128837 0x7243057b 0x4da7a027
+ 0xc1c502ca 0xa5f2bcc4 0xf2c6209c 0xb675c45d
+ 0xa5aef423 0x362b5df4 0x7840609c 0x714209ea
+ 0x3919be09 0xc67c360b 0x6ffe8d84 0x3dcc0e10
+ 0x558ec8dd 0xa2285d7b 0x9eb86078 0xb4685e77
+ 0x3840ab30 0x2ac2fdb1 0xc6b795c0 0x834c15c0
+ 0xaa0ff942 0x74fdc7e3 0x87ab3565 0xa9d3f71c
+ 0x53ad4955 0xad5191de 0x3e30a79e 0xee227702
+ 0x5910cbaa 0xce926dbc 0x629937d9 0x271e98ea
+ 0x29ac6f12 0x09248669 0x74d8fbb5 0x435a83c3
+ 0x93dd39a3 0x7bcab8ab 0xf86858ac 0x403823a8
+ 0xd9fb5669 0xddfdc2b6 0x9b7e771a 0xf7a6a574
+ 0x1bdc0062 0x54c621be 0x45a49ac5 0xf4b5c38c
+ 0xe7916b1f 0x4ea7f121 0xd5457986 0x6bb57a6f
+ 0x1bc4d42b 0x2ab0ee84 0x5b8e508e 0x6adf0b60
+ 0x1c39dc48 0x25d58fce 0x54327b32 0x93718903
+ 0x991e452b 0x627cc0d3 0x15233871 0xf921f79a
+ 0xea6475d1 0x9b155143 0x5914ee94 0xbbeb43cf
+ 0xbd590426 0x8aaaa0c4 0x50b174a1 0x51aa1955
+ 0xea349dfc 0x005a2de4 0x4603a63a 0x971af0b8
+ 0xbcd89a17 0x1d49e631 0x63d3a40c 0x63b0f1eb
+ 0x975757fe 0x706e086e 0x161d0cad 0x5b5f4fe0
+ 0x4a82f4de 0x34800a89 0xdcfeeb96 0xae9c0bb8
+ 0xa6422c15 0x8ee1b10d 0xa454ec0b 0x1a51e7eb
+ 0xd2767564 0x8541c726 0x7e0a8cb8 0xbd6f58ef
+ 0x7325c5fd 0x5f8b8144 0xb18853e2 0xd6ac3e90
+ 0xeccfdfaa 0x8bed8778 0x7d65f220 0x86502ddb
+ 0x272d7bbd 0x9546beb4 0x2fdbc971 0x8f86c26d
+ 0x317131ee 0x06a2d84b 0xcfaeb274 0xbdc64496
+ 0x842eee16 0xc5596e5e 0x3fc8d83e 0x60ce3e3d
+ 0x233ff26f 0x8e7eea69 0x3dfb8b62 0x0bd1271f
+ 0x3276add3 0xdce0f322 0x272f2fed 0x310b01b9
+ 0xec13dbff 0x44ecef5f 0x716a95b1 0x8e2ed760
+ 0xfc1cdbf3 0x363ab021 0x529c749c 0xb8361787
+ 0xb576b8dd 0x05ba72be 0xbd94ddca 0x995823cd
+ 0x4bf10e99 0x6350d475 0x6fab0d5d 0xa3fb7ef0
+ 0xa755d719 0xefeb5c22 0x8369b60e 0xa190b7b2
+ 0xf1ca5eba 0x406fbd8f 0x0b858d59 0x9f4f3a99
+ 0x600706c0 0x8efb77fd 0x8ebd23fe 0xa82b4e93
+ 0x44d50e4f 0x92a2b5a1 0xde8229a0 0xa9128ba4
+ 0x6dc829bb 0x5d63bac1 0x8948d416 0xbb85eebc
+ 0x4b280f18 0x6156e24b 0x5271526e 0x3a550970
+ 0x7212c942 0x09040eba 0x0c199ae0 0x3f41b3f9
+ 0x8d439401 0x83319b2d 0xf3deffb4 0xfd813e2a
+ 0xa8ac6a50 0x72858022 0x5650a6ea 0x8b9e18a3
+ 0x7dc2d48e 0xabf0c35c 0xe9d93f5c 0x228412d4
+ 0xa7b07016 0x0babb01b 0x36faa524 0x3157fe90
+ 0x4cf0fd08 0x1272a76a 0x8e701e54 0xd1ed3067
+ 0xe92bc6ac 0xea2fcc5d 0xdae1a6c7 0x4ec3465f
+ 0x97556141 0xda282893 0x2bdf77f3 0x458abb7b
+ 0x8c98d27e 0x9f2ddc8e 0x4bf66134 0x7ef33d1d
+ 0xe7bfef39 0xa9b37d3e 0x2272b785 0x41bc32d3
+ 0x16790e7a 0xfcd172a9 0x4dcbdb4f 0xadc6cea4
+ 0xe72aab79 0xd3a530cd 0x153171ea 0x60d6122e
+ 0x1b00ebde 0x366861f2 0x6781fc14 0xe6d6189c
+ 0x3b9beebb 0x5c239e07 0x51999573 0x5b900c94
+ 0x52a14fae 0xc7c0bdfb 0x5bebb646 0xaaebca2f
+ 0x360c6d2f 0xc8b43453 0x16ae683d 0x11248d2a
+ 0x08fa3017 0x2bfc636f 0x7360ae91 0x793ad23c
+ 0x7d2bc4bc 0x2d505664 0xee449c94 0xbd0beb6a
+ 0xa9b818e7 0x251354ca 0x119825e5 0xae8b8d2c
+ 0xeea15a2f 0x8b3c47ad 0x2af74ac7 0xaedb8156
+ 0x9b96ee47 0x05034a2f 0x752f8722 0x0f1ee372
+ 0xff55b4b5 0xd12d4ead 0x554c31c4 0xc167849a
+ 0x118d9c61 0x9825a5b5 0xd1941592 0xa21440d6
+ 0x0c8fa874 0xd23ff93c 0xf592f75b 0x6d171131
+ 0xe1cc848b 0xe73fe5cf 0x38677f4a 0xddbbd004
+ 0x6af79754 0xa666b38e 0xf5afba55 0x036b1f0b
+ 0xd55860f2 0x1efdbe6f 0xafc557a4 0x3b24c27d
+ 0x68f319ef 0xf863285e 0x80e88563 0xbe2af6a4
+ 0x81360909 0xcfbaac9a 0xa0a07505 0x8c653634
+ 0xf630bc25 0xdea1640f 0x51445022 0x8bd02194
+ 0x593185c9 0xc23f98f1 0x06b6d384 0x432278ed
+ 0x9c422519 0x0664dc91 0x733e7075 0x9e05a4c2
+ 0x1b014110 0xc4787233 0x4aad488b 0x756f0d47
+ 0x9e29a6df 0xabde4b5d 0x23727bdb 0xf1e3a05d
+ 0xa1f22c40 0x2d290090 0x62d3b212 0xcc247195
+ 0xcd5c84a1 0xf277c61f 0x4f9f213a 0xa69e7391
+ 0xf09f4162 0x44771471 0x6be202f9 0xf27e05bd
+ 0xef27ffc6 0xb94d8b95 0xcc124e11 0x6d22e955
+ 0x8c572ef0 0xc59727f0 0xa68aa858 0x034de5f4
+ 0x242700ae 0xcad4225a 0xb5e792ea 0xf791ab32
+ 0x8f75a863 0xd078bb02 0xec889a62 0xbae59fa8
+ 0xd0e96b37 0x7127e3a9 0x69283a7c 0x7fe26fca
+ 0x3b33f97f 0xef3bfad2 0x0a33c011 0x060e0e58
+ 0x27de1402 0x55f0b8c9 0xf48de31c 0xacbc1c7e
+ 0x228459e6 0x9119a04c 0xeae173ef 0x50347a6c
+ 0x6da1ae72 0xcea1256b 0xc328fe6a 0x85a48b53
+ 0xd8bdb49b 0x857cd611 0x2218a975 0x4893fbe3
+ 0xbd0b7590 0xdc35b430 0x0b37d8a4 0xc1938a77
+ 0x78423be3 0xbb14bb91 0x0c900fe5 0x82037d1e
+ 0x1fc0a8c5 0x5b83cd7a 0xf1a7ff8d 0x36cb83e6
+ >;
diff --git a/arch/x86/dts/microcode/m12306a5_00000007.dtsi b/arch/x86/dts/microcode/m12306a5_00000007.dtsi
new file mode 100644
index 0000000..de50372
--- /dev/null
+++ b/arch/x86/dts/microcode/m12306a5_00000007.dtsi
@@ -0,0 +1,618 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x7>;
+intel,date-code = <0x9092011>;
+intel,processor-signature = <0x306a5>;
+intel,checksum = <0x8e38731>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x07000000 0x11200909 0xa5060300
+ 0x3187e308 0x01000000 0x12000000 0xd0230000
+ 0x00240000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x07000000
+ 0x00000000 0x00000000 0x08091120 0x71080000
+ 0x01000000 0xa5060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x27649db1 0x904b6445 0x6acff7e8 0xc4ac0631
+ 0x6830ec45 0x3aece98d 0x97bf40c8 0x83b8fef0
+ 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6
+ 0x5fb36178 0xbc17d76b 0x31b7b923 0xc81aec82
+ 0x647b3320 0xf1db9653 0xff3b9759 0xe9c74b72
+ 0x3b193752 0xc147860b 0x160e0d6a 0x5bdb9dbf
+ 0x1ccce2ac 0x387670ad 0x2f106f05 0xf8607ea3
+ 0x42562576 0x30e086fb 0x409a06b8 0xf1957736
+ 0x5eb03f65 0xad147fab 0xe1a8e8b6 0x208d59d2
+ 0x683fba2e 0xf172b378 0xf8138dba 0x61e81d1f
+ 0xd551f997 0x28c79780 0x04f9db27 0xa80679b9
+ 0xaca4e7ff 0x6876944b 0x26d7dbc1 0x77f7dc2a
+ 0xf0bcb163 0x1b2a8e81 0x7b90aa49 0x8d5eaf2f
+ 0x522384ae 0xae7f7082 0x412ba10a 0x1ce1baa0
+ 0x478c29b4 0x9c09b4d2 0xf225f64f 0xd43026cd
+ 0x81098579 0x7df5db05 0xa5815bb0 0xc73ee756
+ 0x9738cb95 0xa5bd62e2 0x88e2c6b2 0x778e7fcb
+ 0xd3bdb872 0x9404403f 0x5be6ad63 0x71dc4abc
+ 0x11000000 0xb290ba8e 0x6671b099 0x7834fb60
+ 0xe02e439f 0x55712161 0x5dca20ba 0xb62c06df
+ 0x83d86103 0x35cbe438 0xeb7841c9 0xded7ad9a
+ 0xda76b9f2 0xa39233f5 0x11377a10 0x6928a0e1
+ 0xf6164be1 0xab9cb400 0x0ac5e864 0x978e6cdc
+ 0x51d9070c 0x3786d896 0xa6b103d0 0x288c8c83
+ 0x9c644099 0xf9a8a7ad 0xd2a96566 0x2e985d7e
+ 0x3531b0b8 0x3906909b 0xce3878c3 0x30b950a6
+ 0x536b312c 0xb9f07473 0x29366b16 0x7a515f52
+ 0xce7d21ff 0xfe5aef73 0x69b91f78 0xd50b9686
+ 0xa384ac5c 0x6e90981b 0xc37028fa 0xc448c695
+ 0x3c5275e0 0x2ea780c0 0x5fe9aeb5 0xa733e8e1
+ 0x2a04c422 0x68243f2e 0x5311d43b 0x93c27dfc
+ 0xc78b431f 0x9a7bd54e 0x7731f225 0x0f71db56
+ 0xf89a8f8c 0xc5eb2d2a 0x45f973ec 0xbb0635b3
+ 0x5b825acf 0x8744ccef 0xceb1dfca 0x5e5b882f
+ 0x356cfd00 0x68e42c02 0xf0ea6e97 0xa0c1327c
+ 0x5fb06338 0x3e7df893 0x5c3eb0ec 0xac7cc79f
+ 0x3dee3b4b 0x313a2915 0x4002db54 0xe8a96a04
+ 0xb79c367e 0x6d53a3a8 0x9b2720c7 0xf5e7dee4
+ 0x357fc3d7 0xcfc9b54e 0x72f9732e 0x3ccbe991
+ 0xe0486033 0xabeab549 0x032089b2 0xeb1467b3
+ 0x3898e23d 0x4f25f3d4 0xe2f64597 0x3e7facd4
+ 0x455514e6 0x99dea4e4 0xc1201200 0x72d68181
+ 0x25046d7e 0xd3b6ada4 0xd3f358b2 0xb6a0dcf5
+ 0xfbf43626 0xd9cafa7a 0x27ec8d4a 0x84d60c14
+ 0x35e79275 0x413169be 0xbc9847c4 0x0ddcad0f
+ 0x5e098c03 0x03187763 0xed64abff 0x8eaada0c
+ 0xdf378018 0xf394b0fa 0xd4abca64 0x3ad203b6
+ 0x1347cdf9 0xffaf1040 0x078c6baf 0xf2e7d31f
+ 0xdfc334c5 0x061d2348 0x85877503 0x561b6cef
+ 0xfc9aa2ed 0x6057d0b6 0x288df59a 0xda7c47f2
+ 0x727a8584 0x58f74d64 0x8afa48dc 0xf50d3582
+ 0x9f42eec8 0x776d1b6a 0x35f42768 0xbdb7f7bb
+ 0xa239bc05 0x1d26bcce 0x025568ca 0xa2ef8189
+ 0x0054417e 0xf9aff2b5 0x56cc33be 0xed695186
+ 0x58b21d0d 0xea2215c7 0xa565b724 0x2931c422
+ 0xe20b2043 0xa85a082d 0xd7760789 0x58c317cd
+ 0x8c500d70 0xecd22975 0x79542e54 0x790b048f
+ 0xcbbc98fb 0x125b81f9 0xe3e74009 0xc6f4ebc8
+ 0x1e22f4b7 0x0485cac9 0xeb4dc6c9 0xab9076a3
+ 0x9feccd38 0x733e57dc 0xe250d25c 0xf0eb5a8f
+ 0x3db33c3c 0x36c52b3b 0xfe5f92fa 0x0ddc38bf
+ 0x003c6542 0x154abb1d 0x4feb8d85 0x6aae78dd
+ 0x59282b12 0x04fec81c 0xf6f117c7 0x7123b56e
+ 0xd8c53d48 0xff2eeac6 0x09716dee 0x5d24cb13
+ 0xae7c77ef 0xf0213c38 0xd7290320 0xfe3ce627
+ 0x9402607f 0x42ebf5c3 0x4b25a536 0x7167f997
+ 0xe456ed20 0x5a8ed54c 0x8f774e9c 0xa9f1bf83
+ 0x2322ca10 0x3bd6021f 0x2ad0affb 0x0a727ca8
+ 0x228cf77f 0x19f54f70 0x2b7cc811 0xa7193b61
+ 0xcc097688 0x395a8700 0x073e2b6b 0x8e90c718
+ 0x0855f8c6 0x7de3d62b 0x2f582aee 0xeb8667b7
+ 0x6a09f600 0x119a656a 0x7502100c 0x36d51cb0
+ 0xb398a2fe 0xce1a11fe 0xa75b725b 0xf8d69c5a
+ 0x69b6a07f 0x3b5e712b 0x07d647d0 0x80bbe6af
+ 0x80cdefb0 0x03ae17e9 0xda7da860 0x39610997
+ 0x67afea64 0x2d141230 0xd845efe5 0x346b9c22
+ 0xf03d45ce 0xa7f96ffd 0x21bbd7fd 0x035297c4
+ 0x27b88b33 0x8ff80f90 0xa41161cc 0xe38a33d1
+ 0x3d12c73c 0xc81ca705 0x55bb79a9 0xc80037b2
+ 0x2b1b7c7d 0x47ccc91e 0x440370f4 0xb754bfe2
+ 0xf9774b91 0xa8d2fa85 0xb7db3a31 0x102a7131
+ 0x61a200b0 0xea8bf0f9 0x826ca613 0xd3842856
+ 0x27fa5f1b 0xdc6f7aa8 0xc4351ff1 0x13e8d56c
+ 0x3b81f6fb 0x444bb6a0 0xb5fadf26 0xf1e0fd81
+ 0x5c75fa49 0x1e66f533 0x74f83da7 0x749327f5
+ 0x1f41d35d 0xabb10c2c 0x15ff553f 0xbb5ad732
+ 0x904b2bde 0x6eb6c5d7 0xc38cef3e 0x5b62a4c7
+ 0x4c1d0297 0xeb0d88e3 0xe147c6c8 0x726bde4d
+ 0x2cce53ca 0x2e0ad784 0xb5ce9c2e 0x04fa3a1c
+ 0x85fdc1ba 0x87a73107 0x3b1a12db 0x84f7c886
+ 0xbb9c65d3 0xf319fa80 0x8684ad1a 0x8b675754
+ 0xcefe8be8 0x19fb7f42 0x9fbc80de 0xea169c83
+ 0x7aeb705a 0xee25f4ee 0x2f51d222 0xe553b558
+ 0x3bbc3526 0x9b99ac52 0x97b7fa61 0x997ff0fd
+ 0x1d90099d 0x611d8fdf 0x180e1256 0x02436dd8
+ 0xf5c0088b 0x977ce145 0x3e22559a 0xa7434bbc
+ 0xbc0af767 0x61f2adbd 0x6b414aa5 0x23256487
+ 0xcd90a1de 0xa212e85f 0x5a8cbfda 0x901ce98d
+ 0x58784538 0x3a02ddb2 0xd388d8fe 0x18e21114
+ 0xc0ce52ac 0x10eb99b3 0x434dbf0d 0x9fc25de8
+ 0xf4166b7d 0xf520d339 0x80889748 0x36c5122f
+ 0xb0f53d62 0x78f18c2b 0x10b7e0ec 0xb515926e
+ 0x70065726 0xd83b26cb 0x284b191e 0x33c4a3f7
+ 0x97998f96 0xd7458672 0x5e23c14e 0x78a584f9
+ 0xa334e7d1 0x8fcf2992 0x0d7748be 0x3d5e9309
+ 0xa4a46124 0x536108b4 0x57af0c09 0x7ec11806
+ 0xd6b8c03b 0x8618900f 0x6c1c60bb 0x9650af3b
+ 0x83b8c109 0xfbe91320 0x681cc792 0x76fb441f
+ 0x69eace4a 0x66563862 0x86a7a909 0x59815c86
+ 0x604c949f 0xba39a0a4 0x51a1322d 0xaff2a150
+ 0xcba82656 0xc82a79cb 0x9eaa5989 0x5602a25b
+ 0x91917c30 0x46e610b4 0xcb698616 0x571cacc8
+ 0x642c25fd 0xc61a5c96 0x5c0d7b2b 0xb22e2868
+ 0xc5697ac3 0xf69795be 0x9aa5f24f 0xbd4c0815
+ 0x61e63957 0x9a2c3a0c 0x452bd662 0x06ce51e9
+ 0x849769c2 0xe7d1ece0 0x53fbe99a 0x1f8c3976
+ 0x04bbf199 0xa11ebe8b 0xcf862106 0x75f9410f
+ 0x4e573a0f 0xd37b1822 0x45e821b5 0xa72f103e
+ 0x87d41b9a 0x751c1360 0xa3d9bf04 0x38817c3b
+ 0xa1243092 0xeaffa979 0x315d68ea 0xdf4544d4
+ 0xd7bc8ed8 0x4200e14f 0x46cb8d5d 0xe53e695a
+ 0x20fdcc05 0x7bc91fc1 0x21a08c38 0x70377159
+ 0xf000b852 0x010b2051 0x64f27dae 0xa5d40c9f
+ 0x0d2d05db 0x035026b4 0x4dfd9dc6 0xe1ba51b6
+ 0x182921b3 0x3a14fd50 0xfd822b9f 0x1c475677
+ 0xa23ca2d4 0xa4471500 0xb0a3425d 0xc384422e
+ 0x1791bb5e 0x300db057 0x015cdb9b 0xa9254782
+ 0x850a6ed2 0x939270a4 0x6173f301 0x59c678bd
+ 0x8dc33d87 0x8ea24bbe 0x8ffaf807 0xd132392a
+ 0xeb824b6c 0x6dc0e254 0xba2588ea 0x83c5b65b
+ 0xed46fa12 0xc9932295 0x6feb2198 0x74cef43c
+ 0xda34147d 0x338e8acd 0xb6bc8ae3 0x62eeeb57
+ 0xcfd703ec 0x0fa51fb7 0xe6dedfc6 0x06e05089
+ 0x0cd711f6 0x43f73969 0xf43b945e 0x1a63c878
+ 0x366aa911 0x946e06d0 0x8ff0d6f5 0x99e7a128
+ 0x96bf8c82 0x93ffc377 0x9e7d65a8 0x6ef2f639
+ 0x57ac2e72 0xd0d643e2 0x228bc4cd 0x76f8d2a3
+ 0x2c845f50 0x830d3729 0x58d7485d 0x0024caa6
+ 0xac3a5590 0xf18e17a6 0x684dc526 0x6c727c92
+ 0x9abaaa66 0xbd78b8b8 0xac5a3426 0x15c1111b
+ 0x0ee1a7c1 0x665f4531 0x617e891f 0x3285e4d5
+ 0x4cf347dd 0x7b66024a 0x081de006 0x1005600a
+ 0xf124826a 0x2fcb5728 0xc1ddc0de 0xbd7c76d8
+ 0xed4d9ef0 0xaeb0472a 0x2b07a2b0 0x3737ffed
+ 0xd40ef124 0xd1c577fc 0x58076c85 0xb88a0dc0
+ 0x87a5020d 0x062dc1d0 0xb7c62806 0x9aa2c8cf
+ 0xca896ae8 0x40ff25d1 0xe97e160f 0x9f55451b
+ 0x9ba07423 0x6c93a22f 0x55f124cf 0x39ef755e
+ 0x04dac73b 0xa8e8c97c 0xf97d7be2 0xd6200b18
+ 0xf9299b79 0x86abae89 0x661f5e34 0x7317dfda
+ 0x38dff8e7 0x9cea93ba 0x503971a0 0x2837691c
+ 0xbf4eb209 0xa20ce894 0x255c4fff 0x74180a05
+ 0x3c5715da 0x017ec40b 0x6f580634 0xaab316b4
+ 0xcaf9fe94 0x3ca6b65e 0x74015cee 0x4a3ca213
+ 0xa7db4345 0x5a2bb90c 0x2bc01b3e 0x8949fab9
+ 0x548cbb0d 0xf8fda387 0x6e833630 0x786ab073
+ 0xe6fa5787 0x0a659d86 0xe75b17ce 0xf2d07498
+ 0x2ab3ef78 0x74b31ba9 0x623e7ee5 0x1dd7ac63
+ 0xf30617ca 0x34385e0c 0x5cffcadd 0x97bb21b4
+ 0x0aa7cae5 0x679e83e2 0xd15be3a7 0x35a68299
+ 0x7bb0a530 0x33f4793d 0x098b4d9e 0x10123f64
+ 0x39dfe4c1 0xc826ca0c 0xc0f0959a 0x8ab66a8d
+ 0x537e4273 0x93a9c3ac 0xd8d04d5a 0xec511096
+ 0xe14318ca 0x2933223b 0xf89e7a44 0x8fe3680d
+ 0x0ac46c4f 0x87bfbc2e 0xaf4161d7 0x80a1d020
+ 0x91b7b729 0x212b7294 0x6cf14779 0x89faf74a
+ 0x7c5ebbfa 0x6dc0b4a0 0xd3617c72 0x08525097
+ 0x102bb960 0xcfc6c0ca 0x65a604bd 0xd39affdb
+ 0xcab7df61 0x2fb9080d 0x48175e89 0x25133092
+ 0x4a0229e5 0xf88ec53d 0xac24abe7 0xb84598f8
+ 0x1bab71db 0x3c6fa6cd 0x2c4dfd2e 0x22dbc3ef
+ 0x5ac3e6cb 0x66234a29 0x2c26aacb 0xfcb4bb99
+ 0x204c226c 0xc20561ac 0x1e5bffaf 0xaacafe8c
+ 0xf03bfa31 0x0dbe0396 0xd7561d7f 0xb53794dc
+ 0xfe641d5e 0x54e48453 0x611700e5 0x0639b5cf
+ 0x7028a7ef 0x6f3be4b7 0xda5b1755 0xc988199a
+ 0x48497e7a 0x4e3cf3fe 0x99d212e3 0xbd2b89e6
+ 0x98b4ef8a 0xeef8e602 0xef153f89 0x143151c2
+ 0x90557d9b 0xe6a8ef65 0x2e380066 0xe54ac324
+ 0x8e8fc6dc 0xc23f7add 0xaf1fb336 0x3e60c29a
+ 0xe1d56ba3 0x8f654c53 0xf30e755d 0x3b4fa485
+ 0xf8ab5ed0 0x77336bd7 0x56489149 0xc284403e
+ 0x86801f98 0x5a4230ca 0x3af70662 0xfd8ce85b
+ 0xf6adfca8 0xe8cd1021 0x203bbbd2 0xdbb3c8c1
+ 0xe08a736a 0x29a9b3fa 0x3ac18aa0 0xa109b619
+ 0xc7fdbc67 0x161ef5b0 0x6efe8dc1 0x3b9214dc
+ 0xda2ef14b 0x4beec8ac 0x587806a1 0xe796b93a
+ 0xcd1efc91 0x3402e472 0x77150586 0xf8b4381e
+ 0x9d8bfae1 0xfb07a3e9 0xe84d8f52 0x97b0ea6e
+ 0x3e082a35 0xf4b05402 0xd29d4891 0x7da3c1d2
+ 0x3ea5fb56 0x78785f7f 0x6b09f74e 0xd4055e3e
+ 0xeede0d53 0x5b8b354b 0xb5132dfa 0xc5682461
+ 0x78971da4 0x290869a1 0x972e7460 0x91e2ff0a
+ 0x6c0b11c3 0xe91a471c 0x6e0eac24 0x320f7064
+ 0x017e0db4 0x7787cb8f 0xaeee8791 0x1845374f
+ 0x96affa9d 0x26b1a81e 0x9d303406 0x87ea47b9
+ 0xfb91e077 0x9b6f5e58 0xc03cfae2 0x494c55f8
+ 0x3080c429 0xe001b48a 0x3819f103 0x13cd3b86
+ 0xc8bdc304 0x1694671d 0x37217270 0xfa15992e
+ 0xf3448fa1 0x70567b60 0x75e6b3db 0x9e411eba
+ 0xeeac50ca 0x5d5a067a 0x1f555a8e 0xa5dae7ef
+ 0x6205551b 0x1f886ad7 0xb980337a 0xb20cf87c
+ 0xf2ed482c 0x787c6e0e 0x180a809f 0x723eefb1
+ 0xb4ba42a9 0x617a054b 0xed5cd307 0x3aee8414
+ 0x03db3a2e 0x7b17b0d3 0x15b6cf15 0x07fdc220
+ 0x172f174a 0x3420f66f 0x731294c1 0x2f4f40bd
+ 0xc5077559 0xe224c0d0 0x481e0614 0x52fa9a86
+ 0x2de9ebfc 0x568cda73 0x30e3e521 0x4d74db41
+ 0xe6bba3bd 0x15dcf205 0x684c95bb 0xc700dc76
+ 0x09b2ba8a 0x44fab1c4 0x0cc69cb5 0x30647b12
+ 0x1d6027e5 0x3e41cea5 0xebac90c8 0x0faaceb5
+ 0x0da396a0 0x7ba7dbb7 0x6383f0b2 0x2ab79b0e
+ 0x2609b0c8 0x9483a4dc 0x15b518bd 0x8ef64ab3
+ 0x04525707 0x2e7508a5 0x6345f48c 0x4c91d9b5
+ 0x0cac5beb 0x2608fc0e 0xf2e856f2 0x98cd968d
+ 0x1d3d91f5 0x176604ea 0x0a2d2dfc 0xb3434c9e
+ 0x39310c4c 0x03023246 0xf35ce087 0x1687dcd9
+ 0x42a7c9b1 0x7cb216e1 0x42eae528 0x9f412af7
+ 0x774f7224 0x67810c12 0x65a5f218 0x61e4a7b5
+ 0xe7545f4a 0x99173997 0xbec075a4 0x652039b4
+ 0x780fe7b2 0x0984ddf1 0xbadc6857 0xdee86ac8
+ 0x3d327811 0x1b425172 0x55d337d1 0xb44177b8
+ 0xf79e7837 0xf8da74f5 0xb5c10868 0xb9cecb56
+ 0xd61b6202 0x5982d5e1 0xeb940541 0x0b761afe
+ 0xe65acc8f 0x5494b48e 0xc5fd1459 0x1829484d
+ 0x94bcce9b 0xa2b0dff8 0xaf7f8a70 0x238bc2ea
+ 0xad4dbb94 0x783054fb 0x0d8cc536 0x3703a186
+ 0x40c6562f 0xeaee25e1 0xe2909809 0xa9846735
+ 0xd8ad895a 0x37615e99 0x9c95d6e0 0x047c5b36
+ 0x6496bb81 0x19d885c0 0xe291b192 0xc8b17833
+ 0xd55a539c 0xc68172ac 0xc63ec8eb 0xd12415cc
+ 0x862b22b9 0x2943b1ea 0x8ed7a4b1 0xfe052a43
+ 0x258ea403 0x0ca78dd7 0x8f586047 0xbbfe7fb6
+ 0xa3380f8a 0x10569198 0x597f88a6 0xa0ae9fda
+ 0x66dd24cb 0x1c832157 0x399e1973 0xcf9dd548
+ 0x88ee7f20 0x100ff596 0xd9be3e56 0xdef236c1
+ 0x2f0e99af 0x32a752d9 0xc9668712 0x7f6c5480
+ 0xc15a44f2 0x98f9d8d4 0xafadbcbc 0x3743a44d
+ 0xf03d4b88 0x55ca6a18 0xb0dbc9e6 0x71212e48
+ 0xd3be7163 0x4fd4549f 0x61669de9 0x8d9ad4bc
+ 0xf686b563 0xfa360d43 0x53add021 0xbe326f90
+ 0x89818483 0xa7a511d7 0x2d46a2e1 0x8101f8f1
+ 0xb2d2f30a 0x2c5e3a4a 0x742439a2 0x6a005d30
+ 0x78567846 0x05b04ef5 0x9a182c4a 0x221e446e
+ 0xd018da8d 0x119e2e6c 0xad5ca7f9 0x50d38b69
+ 0x99dbbb87 0x12e356d6 0xc3791592 0x300da550
+ 0xad8a6c81 0xa0db19f0 0x8cb34461 0x83707ea9
+ 0xbcdcd577 0x673e75db 0xbc35ac61 0x16e9ee67
+ 0xd9dccf93 0x57caf1e2 0xeccf5499 0xfdc12d0f
+ 0x97da0037 0x961585b9 0xccc672e8 0xd62192f5
+ 0x439ca19a 0xd918c5d3 0xd2c0f5bf 0xf8dba053
+ 0x434b8aaa 0x5e9e7f7f 0xdba2d664 0x090f789d
+ 0xda704e2a 0x3bf49b6b 0x9a56e688 0x464a6c03
+ 0x072450b3 0x9bf0955a 0xa56bad97 0xba999dcb
+ 0x04807d22 0x486db7a7 0xe6311414 0x068ebf6c
+ 0xbb69fabe 0x1abfc72a 0x4b839860 0x67feb6db
+ 0xe996518f 0xf6b67f21 0x8b5b917f 0x133090f6
+ 0x2e3524ed 0xa6fdbb3d 0x6e7f1c2d 0x4994765a
+ 0x3544fbf5 0x7e66e6d4 0x6d6d5fb6 0x1ce9e2ca
+ 0xff985901 0x8e0dbef4 0x7b388a2d 0xe9149dc5
+ 0xa3c84368 0x8d8dc7b3 0xdaa7659f 0x868a91c2
+ 0x2c6b23d0 0xcedec4dc 0xe03122cb 0xba43941f
+ 0x7b883e9c 0x6c4178e8 0xda6b3f3e 0x4055ac09
+ 0xe7c51544 0xe5764724 0x97a7f9c2 0x78954b06
+ 0xc6e49901 0xb7d3abcd 0x150df345 0x491fd23a
+ 0x0e676438 0xe6d5dce1 0x02b6275c 0x53758880
+ 0x4486b54d 0xfcbb2570 0x4b7df2e5 0x532df181
+ 0x8df5b498 0xf84cf259 0xce3069ad 0x3c3cd864
+ 0x6c845f46 0xc1efba88 0x9d6a9a81 0x065e312f
+ 0xc8c6b470 0x25c4a3bb 0x273e75c5 0xa1c5ea74
+ 0x61ecb8e9 0x526053d3 0xda33ce24 0xe4ad247a
+ 0x6efa242e 0x1b55024f 0x03c1e447 0x4bc3331d
+ 0x9b3b4820 0x9b7f31c8 0xedfaa865 0x487ac0d5
+ 0x733064a1 0x3a5ddb5d 0xfd5a13c2 0xd00a809d
+ 0x6801afaf 0x837306d6 0x5230ebdd 0x07fc0210
+ 0x49b251da 0x4aca0425 0x9948ff5d 0xceebe8a5
+ 0x9c90b8ba 0x1b97a25c 0x0e04afb0 0x7fff9d2f
+ 0xa0538fe5 0x4fbaa822 0x7c6ab622 0xa3d9519a
+ 0x09cdde4e 0x02646d7e 0x676df07c 0x15aa2fca
+ 0x50e42757 0xfdfb8dbb 0x60b113ef 0xa5311754
+ 0x99b676a1 0xb5d67a33 0xe718e7af 0x7347ea31
+ 0x94cd5918 0xc4704c50 0x5adaf5d0 0x77b2bae0
+ 0x952aa975 0x372223cb 0x4a9a140b 0x61a13149
+ 0xffd77681 0x6f3de7a8 0xb03f76e6 0x929b509a
+ 0xbf3e5471 0xb6fb2aaf 0x982e8ffa 0xe199b2d6
+ 0xd3eda942 0xdb70c9e9 0x68762bb5 0xcc69f70d
+ 0x17cefdf5 0x9f911741 0xdbe7ab10 0xb7270fff
+ 0x7014244d 0x6287ee89 0x1846bcac 0x446813d8
+ 0x3161e3f0 0x18dec6aa 0xfcb8ebe0 0x9eab2a12
+ 0x499a5a82 0x3e2efa16 0xa07c3ae7 0x078f0c81
+ 0x18ad16e1 0x4c033a21 0x0b9f9a7c 0xc25a5eea
+ 0xe52e2175 0x94f75591 0x2e644f41 0x0818c4cc
+ 0x97d45921 0xe126045d 0xd077bc13 0x6d666b78
+ 0xbc44ea8d 0xc68554cf 0x60aa6bc6 0xa7c15918
+ 0x62c7abc4 0x27e20ba8 0x9ee6b287 0x8cf00a2f
+ 0xdee0d40a 0x587a1962 0x6232c094 0x713bd4da
+ 0x9fd6632d 0x079eaf81 0x053b65f0 0x4ebe2754
+ 0xcbd4c6a3 0x77387931 0x2503876b 0xc152ed21
+ 0x17d8e3dd 0x165a3cd4 0x8feaf21d 0xcd9df543
+ 0x8d3c36a3 0x7fdbae42 0xcc14a09a 0x9936d605
+ 0x7e5735fc 0xf3b53490 0xc1f0beb5 0x96dddf0b
+ 0xbfba3a6a 0xf599f44f 0x00849851 0x6c95dcfc
+ 0x494fad8c 0x8e4de300 0x1346d588 0x416ffd74
+ 0x6aa7502d 0x3d59f56f 0x8e005a45 0xd599d254
+ 0x2e1856e1 0xad7f0c79 0x6db65cab 0x2c19bbf5
+ 0xaeb2ef91 0xffde8ba5 0x96253f98 0xd22fc961
+ 0xc6a904cb 0xac69581c 0x0c694b05 0x3a855fd7
+ 0xbf1b2938 0xff4b9701 0x74861e73 0xdb03cf5e
+ 0x4b068efd 0x7ce2de33 0x764351f4 0x16e09496
+ 0x16c9f496 0xa69eedab 0x381d3423 0x2b2248b2
+ 0x1bd08597 0xb438a9fe 0x447ed05d 0xaf0a2f10
+ 0xd432e993 0xe1bfef94 0x971fe56b 0x1ad94ce9
+ 0x96ea6461 0x20c56baa 0x13260948 0x665e47cc
+ 0x5b34ae5b 0xa7f8ecc5 0xb132a486 0xbf496717
+ 0x8affae18 0x6602dcbe 0xc76411ff 0x422fa77d
+ 0x53f83f03 0xc292e30e 0x96614278 0xd75b6cff
+ 0xe0c71f76 0xec1808cc 0xaca18846 0x4905d1e5
+ 0x20648c39 0x4b1b17d6 0x76c7b664 0xfbdfd23c
+ 0x506e0094 0x6994606d 0x2f319375 0x2fbf93ae
+ 0xff1b4086 0x88f60348 0x7a103381 0x1473c242
+ 0x388b1273 0x9da1be0b 0x13bc7b81 0x2b595ba3
+ 0x5e43f7f3 0x06452d3d 0x23a1a2a2 0x29fc9962
+ 0xf4b6d0c8 0x1043073e 0x01fe3f5a 0x598ff4a3
+ 0xddafe1c6 0x3ffa2b5e 0x689ed44d 0xd9586601
+ 0x0945cd48 0xa902e572 0x96d608c7 0x51db96ff
+ 0x10473fa0 0x6dc06b2b 0xb1d22ea1 0xcefef2f5
+ 0xe3443d0d 0x535537d8 0x225b6bd5 0x06aaf266
+ 0xeb766f57 0x04863c5a 0x3bc424c6 0x6560f13d
+ 0xf7ab627e 0x5b014dbf 0x63e064f5 0xcc19e54e
+ 0xac8a9334 0xfc35c060 0x8062720a 0x16151fe8
+ 0x56cfead6 0xf8dfdb84 0x4126eb0c 0x3d7cb05a
+ 0xe8ffc7e9 0xe0e02a01 0xfb0ba2b9 0x82aaf26e
+ 0x2f4bc387 0x045940b0 0x4590e30b 0xb950d57e
+ 0xfc9e095a 0xac94107e 0xbde59a0c 0x3a84808b
+ 0x5d3240e0 0x951c867b 0x9e695e32 0x998fe6ce
+ 0x513ea21d 0xa52e2c8b 0x19e811b9 0xf7b8404f
+ 0x9e70972b 0x913a6bba 0x48e10b9a 0x7e011ed3
+ 0x734c76f4 0xe1599757 0xaaae937b 0x51100d47
+ 0x7d17124e 0x35ecfd95 0x2e953315 0xf5ff688b
+ 0xed16901e 0x90428937 0x9e2070af 0xe4ef8897
+ 0xc443333f 0xeec2c3ff 0xd194031d 0xff460594
+ 0xd1e9cd6a 0xb1d70ef3 0x341500c0 0x9e90b9cb
+ 0x469a4773 0x8de2477c 0x117fc666 0x4f9054ff
+ 0xc927dbed 0x67c74937 0x3baf30ea 0x40936d14
+ 0x0c9ac739 0x041137e0 0x3d059009 0xb7f5421a
+ 0xbb0126af 0xce177510 0xf6de21c9 0xb5f3c076
+ 0x0f2fff63 0x86eafd85 0x802188eb 0x0f7bbf4d
+ 0xcbd9c89e 0xfd9a22f3 0xedd2c250 0x6c58a749
+ 0xa14f1a77 0x4d530eee 0xacf5122f 0x5ec73aa7
+ 0x6fafb960 0xa183fff7 0x3c70bbe2 0x02633064
+ 0xe58b5614 0x1134d39d 0xf8f881d2 0x69d59940
+ 0x868185e9 0x9d0890fa 0x7d9bf165 0x5bb8db70
+ 0xa8945b39 0xa7d9feef 0x1407353f 0x43d1617e
+ 0x120d0afe 0xaac34195 0xa57168df 0xcb961fd5
+ 0xc3224007 0xf59e9967 0x8f15d16a 0xa1316dc9
+ 0xcb26f47f 0xc527ea60 0x926d3346 0x2c6b68de
+ 0x1b3006fb 0xb2756318 0xaca473af 0x272b57cb
+ 0xd60d2c46 0x4e95e451 0xa2f394f1 0x683214d2
+ 0xb9605bdc 0xa115d6e4 0xa6083a9c 0x68dc3d47
+ 0x5a8f50ce 0x169b2488 0x27208e8e 0xe58ad90b
+ 0x45d701e8 0x4112922f 0xb9aa2b3f 0xede2202a
+ 0xa392f747 0xb4bfa7ad 0xce1fd86f 0x70ef8742
+ 0x20953b5b 0x13ebd4ee 0xf595936b 0xc9e8dedd
+ 0x9500e2fd 0xb310d9f5 0x85a0bdde 0x61c15820
+ 0x1115f8d3 0x8785f7be 0x41c14891 0x7933dfc2
+ 0x71d1b4ba 0xa23b8102 0x5faeb285 0x8e57ea62
+ 0xcc850793 0xc87939d2 0x59e20f98 0xca1a3b98
+ 0x33b06934 0xee5a3331 0xbdd162f3 0xaeef3bbb
+ 0x78a32364 0x605fe058 0x46b26fdc 0x12837872
+ 0x16099e34 0x085f188c 0xfe5e4cc8 0xd93cd8a1
+ 0x6dc59005 0x28316a2e 0x9195e418 0x0e214d25
+ 0xfe0e5b53 0x6e9c76fe 0x1dcb3a92 0x9913d086
+ 0x645123e4 0xc908a92b 0x4b88bf41 0x2097f641
+ 0x80e244b8 0x5e003730 0x5a0f58d3 0x16088761
+ 0xd28591cf 0xce0fe936 0x045553a1 0x26c00405
+ 0x6e4bf3f0 0x64290de6 0xe9a19aff 0xd87bf684
+ 0xed4daf00 0x2810c0db 0x128cfee0 0x1e508c6d
+ 0x49467929 0xbbfb2b1d 0xd9c32057 0x6ece8a60
+ 0x22e2d5bc 0xd1abc452 0x1d6ad999 0x8a55d752
+ 0xbb1d05d3 0xfddd231d 0xd4015973 0x5622ec3b
+ 0x09dd64f1 0xa9d70f43 0x68e7297e 0x339d7030
+ 0x4e895dff 0xf4670d21 0x0936a426 0xd122a9df
+ 0xd216184f 0x387ba4a0 0xc8243d33 0x856697d0
+ 0xf6abcaef 0x84d7a4a4 0x4dbee515 0x93c9e8e5
+ 0xb29193a6 0x4f1f7d60 0x76155a55 0xdcac3a70
+ 0x8bfabc0d 0xf9a3e9f4 0x0394ae0e 0xf6f119cb
+ 0xabad1677 0x10acd369 0x978d5da0 0xcf002655
+ 0xe82fb631 0x0aa94bc1 0x722d2cd4 0xd719a922
+ 0xa757ba81 0x81fbd096 0xf9a551e2 0x76149e2d
+ 0x1ddc020a 0xd372ecdb 0xd9638c1a 0xa1e88b8a
+ 0x50078c91 0x214850fe 0x25d6b007 0x727de93e
+ 0xf03cc409 0x053795dc 0x1ef31bd4 0x2f5c10c9
+ 0xfccebcd1 0x44ac9ee9 0x80428302 0x4acef759
+ 0xd91b7495 0x31f152e1 0x72ed8eff 0x0085114e
+ 0x81bbaf96 0x84ecedff 0xbef7bb0c 0xb5c848db
+ 0x23b345ea 0xab388f25 0xd30f937c 0x71f79868
+ 0x0f525e32 0xdbfa767b 0xcf0de0b8 0x7af15903
+ 0xa11eee62 0x70cf63d5 0x4458af62 0x56d50908
+ 0x9da8403f 0x221da3cc 0xbd0aade5 0x183d267e
+ 0x3e156120 0x9b509a32 0x3b5ddce8 0xc11669fd
+ 0xa917981a 0x7da3cdc8 0x783babe8 0x51bf0088
+ 0x9c00c498 0x1e874f17 0x46deb849 0x0fbf988e
+ 0xa5446f28 0x7e6f0822 0x6cf41525 0x6c72bffc
+ 0x720c723d 0x2b55fe0c 0xf18768ef 0x5aab31f9
+ 0x789ced3a 0x96310d66 0xeffc13c8 0xf876eb4b
+ 0x3d873163 0x13fc946d 0xe8d8ddf0 0x210b9b69
+ 0xfc303435 0xc0445e72 0x0837fd7f 0xbae8ddf1
+ 0xc0e9c2bc 0x995280dc 0x46685fda 0xf3af75d4
+ 0xe7ded1be 0xdcafd05a 0x206ee6d7 0x8f6033be
+ 0x215b79ce 0xed907e16 0x5601af38 0x0973ac88
+ 0xd53350d2 0x9d16abdc 0x4d370a82 0x844bd339
+ 0xf794dd28 0x92d34b83 0x059613da 0xaad853c0
+ 0x0b58b92c 0xe930d280 0x3ae36754 0x49b1d72f
+ 0xa886613a 0x88d74d88 0x8f56701d 0xf1e818ee
+ 0xb2795931 0x48b661e2 0xa221d210 0x3bb81578
+ 0x418b80ff 0x3e86c6b9 0xaed36f80 0x4141343e
+ 0xad1ceaa3 0x3329cbdf 0x857da730 0x31d4a9a6
+ 0x277c5e78 0xb32c94da 0x674203b0 0x0c449415
+ 0x4677ae79 0x25abf896 0xa1091aab 0x2825835b
+ 0xe679b6e2 0x205d8da7 0xe4e1aac8 0x95830755
+ 0x40e6e4bb 0x610cfbdf 0xca1b1c44 0x3fe7308d
+ 0xb3e930fa 0x076bf0d8 0x354e1b7f 0xadf06e4d
+ 0x6db0643a 0x36d4bc97 0xeb22d83e 0x3099966f
+ 0xac073c10 0xd5e437e5 0xbbb909a3 0x4feb8b83
+ 0xedd7f264 0xbdcadef1 0xf3086990 0xece45074
+ 0xf952de8d 0x6292598b 0xbc80abbf 0x7393cb7b
+ 0xb5a2f4cd 0x1ca8c4c2 0xaf05b117 0x0672793f
+ 0xd0d075c0 0x48418531 0x8d011a01 0x15c51e9b
+ 0xc51e7e51 0xa974bab5 0x95109a8c 0x06eb3ca1
+ 0x87a097f0 0xad14a4d0 0x314191b1 0x5627955e
+ 0x458c6134 0xb10f0a92 0x96acaef3 0xd90457f1
+ 0x4de019ae 0xeba25c70 0xebe5c14b 0x158d3898
+ 0xf0691820 0x161df4bb 0x136e0c58 0x3af86045
+ 0x1bc6e724 0x23101c77 0x153431d4 0xd609b2c0
+ 0xaa1ae519 0x2be7a14b 0xe7bcc16c 0xc2dc8079
+ 0xb49905fb 0xd95e3f33 0xb92e63f4 0xd3cd2c98
+ 0x190354d7 0xa62dce06 0xfa600031 0xefc6efd3
+ 0x1d3b654c 0xb639ccd0 0x2b7b0983 0x63eae4b9
+ 0xd54b0d33 0x08aa5eea 0x99be4902 0xcc1078a1
+ 0x1c0c0341 0xc82720e1 0xdcd9417b 0x9fa87ac3
+ 0xa77356a3 0x9f35e75e 0xdc6b4248 0x1a146d1b
+ 0xa7fbb7d9 0x1e21490a 0x27b91430 0x594975c1
+ 0x54d33a1c 0x12096461 0x2427f1f5 0x110d0724
+ 0xa72c6e3d 0x6e09f629 0xbcacad98 0x9732276a
+ 0x749107e5 0xebf47d70 0x6b6c4c63 0xfb22cb3e
+ 0x3684453d 0x3dfc9181 0xc5bbe7eb 0x7d3464f3
+ 0x7db3db12 0x69f8d54a 0xc3cb57e9 0xa3a6c364
+ 0x5408adfb 0x260f2384 0x5baf6f43 0xd3791026
+ 0x2719238f 0x68d4f3cd 0xc67bcdbb 0xb23e47aa
+ 0x33c0e8ec 0x8eb2ed26 0xb45d0553 0xa0a51edf
+ 0x63d94bbe 0x3b7997e2 0xa8247af2 0x66af60ff
+ 0xa5cf96d5 0x357bfd57 0xea573081 0xd953943a
+ 0x4b70801a 0x5b18a19c 0x83547b44 0xd1225a31
+ 0xaaecdc1d 0xd9bc2dc5 0xdbab4697 0xe837c74b
+ 0xf3afdeb4 0xa4ae7b27 0x67f514d5 0x135d8d7f
+ 0x718cc961 0x3fa14697 0xd76b4e28 0x7377f49f
+ 0x0e1723b2 0xb2b34ca2 0xe5a713af 0xd0f2eef9
+ 0xd425d842 0x1bf685de 0xfc688084 0xe01d0db4
+ 0x2b33af87 0x523f542e 0x583949fb 0x716d5dcf
+ 0xf2b516b2 0xbbb40cb1 0x28a395af 0x416d8047
+ 0x3add469e 0x2bdda5d5 0x4a0bab2f 0xbb26bb5a
+ 0xa5c4458f 0x87aea38d 0x0d84fbbc 0xc91c5dee
+ 0x226d403f 0xa89803b1 0x362f6461 0xd327ccc3
+ 0x0d3172fe 0x5ee8f57a 0xed862a4e 0xc9e72fca
+ 0xaf37a7bb 0x0e823c62 0xc1f1d185 0x32e22081
+ 0x72427d25 0x9492c7ad 0xaed29771 0xdff35edf
+ 0xbdef0a5e 0x5d9d2f18 0xa0bc1ee9 0x0c397a65
+ 0xc911d530 0x481d294c 0x1a84ce5d 0xf5a5504b
+ 0x22cfca7e 0xaff7e8e9 0x0394d9b1 0x7832305b
+ 0xf853d344 0x89571b4e 0xd2e2bfdd 0x0c72e467
+ 0xb236aea0 0xde6cabce 0xfce515d5 0x0f8c4779
+ 0x3c74d971 0x81b0b3e3 0x2d4c4ecc 0xf4da0ae0
+ 0xa0947a82 0x47609cd3 0x6f81ad8f 0x2bf75b0c
+ 0x46cf40b8 0x344f9edf 0xbad2a5af 0x9e13f884
+ 0x205ea013 0xd54fcb5d 0x20a86658 0x739cfb67
+ 0x7971ea26 0x7841375b 0x649b81e7 0x31ab0179
+ 0xb0730487 0xdba21463 0xa5f6cb07 0xd4f92687
+ 0xca5fbcda 0xc8de464e 0xc7263f7b 0xb93678db
+ 0x1b3ca8dd 0x4636a901 0xd4a16614 0xf96c26e1
+ 0xc58c8da6 0x2965c74a 0x59ff32cd 0x4d77e88e
+ 0x23843ad3 0xa85b9246 0xfd2d5bef 0x1257bf58
+ 0x9c0aa762 0x9ec8ac35 0x77d9bc0a 0xa2bbdee5
+ 0x56d690cf 0x5cdc4461 0x3ef6afed 0xaeb51f80
+ 0x492d6fc9 0xfe4df4b1 0xce23606f 0x40eff82d
+ 0x715eaa41 0xa4e8b2ad 0x19c3e72f 0x9333d4f2
+ 0x9b902cf0 0x70c9bbd4 0x9901f889 0xc342ab6d
+ 0xd36492ae 0x38dc739c 0x0928ffce 0x8d724b2b
+ 0xd5b29bbc 0xa0ce992d 0x8856178b 0x026948bf
+ 0x08809e04 0x541c960d 0x210b71e0 0xf1b9e474
+ 0x85bca8cc 0x90ce42b7 0x6682b7d8 0xe0c50c48
+ 0x25a8075e 0x33dc1ab1 0xf0ff1627 0x89d6d8e9
+ 0x4790ebbb 0x7ba5cfb5 0xe97327bb 0xb06fa0d6
+ 0x7db34b48 0xdf96d115 0xce3fb871 0x03b1557c
+ 0x7eb6d43c 0xceaf3826 0x247e0851 0x840637d2
+ 0x9f979955 0x08f67a6a 0x525d8295 0xdee447c9
+ 0x91ed75bc 0xe4960419 0xb9700051 0x0344b46e
+ 0xbd6b6827 0xa38ab219 0x817e8ba0 0xe86dd20f
+ 0xb9240181 0x4765dd8c 0xc59d8325 0x9b8cfb61
+ 0x6632d86e 0xaf8c2a11 0xbc47dcfb 0x26544374
+ 0xe2beca9d 0xf6355863 0x4291bd11 0x94489a1c
+ 0xc52476f9 0x05fb6fda 0x4d315edb 0xa8e285d0
+ 0x0cd624e3 0x599b9d80 0xd21d8746 0x4d9f3528
+ 0x3a634276 0x9a1f1481 0xa5a015ee 0x6639f7bd
+ 0xd5d20e14 0xe90d52f1 0x3318a40d 0xf3f4f5db
+ 0xb92a7eb5 0x2d730844 0x8282ae9d 0x2f369ced
+ 0x5355d63d 0x984d651b 0x47041c38 0xd65d225b
+ 0xfc2c77a5 0x8822efe6 0x49087974 0xff3c04f0
+ 0xcba80501 0x7e6e1c68 0xa7b7421d 0x6b906771
+ 0x4b2b3b5e 0x233421e5 0x78d0d0d8 0x222dad37
+ 0x875b564f 0x336662fa 0x2bfae345 0x47ff9f91
+ 0xb3e7beee 0x3a7ae071 0x3bd0f29e 0xaee9af97
+ 0x6f0d58fd 0xb5147803 0x32a6ea49 0x70a0a245
+ 0x25b0ace0 0x281e4418 0xfcb5553f 0x1151518f
+ 0x50e67760 0x068c8b22 0xbed7234a 0x4120c5d6
+ 0xec22b6d5 0xc600bef1 0xfd9bd4a2 0xa29451b6
+ 0xcd51bac2 0xc1bd0e26 0xe8432d25 0x2deb06a0
+ 0x9ae54a7a 0x536799e4 0xef4fab62 0x4c9f3e5d
+ 0xeda219fb 0x5947eebd 0x2dec73ae 0x11da15cf
+ 0x94ddc24c 0x2c28b710 0xa5c3620c 0x0722dd36
+ 0xedd98464 0xafa8e23c 0xfd750c04 0x829dc6d6
+ 0x6ee56697 0x2cf2380f 0x3cfa8cd6 0xfa42971f
+ 0x415ad936 0x0b1fea9a 0x65c8b5d2 0x1a5828a6
+ 0x4295092a 0x54596d12 0xa419acef 0xefeddbf9
+ 0xcabda915 0x053abb3c 0xe4b38d10 0x141d9ebc
+ 0xcceb3e75 0xa4fdd9cf 0x9450f718 0xe2a7e7e0
+ 0xbf98f6a0 0x4885a7d5 0x53f871b3 0x0a57e4cf
+ 0x22b36b98 0xd705d611 0x12db0f11 0x546186e1
+ 0x2629257f 0x74587452 0x2659526c 0x2913ca70
+ 0xb3d5b27e 0x1040c827 0x18a192d1 0x2731ba8a
+ 0x5865a15d 0x12b9dce7 0xd0b05fea 0xe35d2de2
+ 0x0f1fc309 0x28df230d 0xcac0338a 0x724f0b25
+ 0x0a36bfeb 0x4c196443 0x392068ee 0x8cc1a2d9
+ 0xbc4f0871 0xea33986e 0x22e90aa1 0x2a43d9e3
+ 0x81214348 0x3745f469 0xaed24012 0x092a728f
+ 0x6b5bb659 0xb46d810d 0xc146cfa5 0xdd3e6954
+ 0x20d6283c 0x0a47baee 0x45aa3873 0xe2c0795b
+ 0xf1cb3519 0x566f951f 0x5e34314d 0xab31c4f1
+ 0x10e0b305 0xfa7d0a3c 0x9adc26fc 0x55fc8af5
+ 0x90314c7d 0xa54954f9 0x27cc0f21 0xbe30da42
+ 0xa04432b0 0x670e176c 0x904a4df4 0x4342618d
+ 0x8b43d3f8 0x086fbc28 0x54954d7a 0x73502d23
+ 0x2ebbaa2e 0x2549f553 0x06946ef5 0x61b621d4
+ 0xafde5d4c 0xbc0faabe 0x0e110c04 0x44ddda52
+ 0xad3883ba 0x1464c595 0x3c5d9f28 0x95573165
+ 0x3e92db93 0x41f19b03 0xb60a4c71 0xf519a623
+ 0x5dc2b562 0xa822e25d 0x09ba6793 0x5e3f5958
+ 0xb80ae32a 0x3f2a8120 0x50cab916 0x8a2664c7
+ 0xe9a0730e 0x74ef9c02 0xbe1b891b 0x8cdeb1cb
+ 0x8f05f87e 0xf4ebaee8 0x12fab9dd 0xfbc8ab3c
+ 0xe6d443b8 0xbaaf9253 0xa4b28356 0x3a105c02
+ 0xb3ceb634 0x26c2d231 0x1e509d45 0xb010dc16
+ 0xbaed93e6 0xffd995a5 0x2274c579 0x081c20f5
+ 0x0e890545 0x9bf20a67 0x534d1668 0xbe0d8a9e
+ 0xe6a3b6a6 0xa19826e8 0x8c369600 0x9b00d171
+ 0xdec22ff7 0x0de50b44 0x4ca2d735 0xe9142307
+ 0xb2d75e8f 0x74018651 0x8a93b3dc 0x679f8926
+ 0xf216f6dc 0xaebc58e5 0x820b6760 0x6e49feb6
+ 0x3ad58a8f 0x62ab576e 0x31829e46 0xb1a2bd35
+ 0xd3db9735 0x248c8e9a 0x8db52fa6 0x8b65b2de
+ 0xebfee08e 0x0d2bdaa1 0xb3d9a282 0xde361f30
+ 0xc121c45c 0x12cdcb27 0x8d7ab875 0xcefac8dc
+ 0x573f8424 0x783fb263 0xbc2d8f2f 0x04f05791
+ 0xa880912a 0x22042163 0xb7891d1d 0x27a3b82a
+ 0x70e35ee9 0xb0b74dc8 0x72b51ef4 0xc074941c
+ 0xeb765569 0x8fba1f5b 0x044aaefa 0xc0db48d0
+ 0x31bed72a 0x7f5ad220 0x132e1da0 0x4cc7e7b5
+ 0x145a80c6 0x39367173 0x0689d163 0x96822f9a
+ >;
diff --git a/arch/x86/dts/microcode/m12306a8_00000010.dtsi b/arch/x86/dts/microcode/m12306a8_00000010.dtsi
new file mode 100644
index 0000000..0672ff1
--- /dev/null
+++ b/arch/x86/dts/microcode/m12306a8_00000010.dtsi
@@ -0,0 +1,682 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x10>;
+intel,date-code = <0x2202012>;
+intel,processor-signature = <0x306a8>;
+intel,checksum = <0xe44a4ef2>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x10000000 0x12202002 0xa8060300
+ 0xf24e4ae4 0x01000000 0x12000000 0xd0270000
+ 0x00280000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x10000000
+ 0x00000000 0x00000000 0x17021220 0xe1090000
+ 0x01000000 0xa8060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x493d401b 0x64106cf1 0x0ffc7f0f 0x9b4b97f6
+ 0xb8fab9c2 0x46353316 0x0247d91b 0x3c36c361
+ 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6
+ 0x5fb36178 0xbc17d76b 0x31b7b923 0xc81aec82
+ 0x647b3320 0xf1db9653 0xff3b9759 0xe9c74b72
+ 0x3b193752 0xc147860b 0x160e0d6a 0x5bdb9dbf
+ 0x1ccce2ac 0x387670ad 0x2f106f05 0xf8607ea3
+ 0x42562576 0x30e086fb 0x409a06b8 0xf1957736
+ 0x5eb03f65 0xad147fab 0xe1a8e8b6 0x208d59d2
+ 0x683fba2e 0xf172b378 0xf8138dba 0x61e81d1f
+ 0xd551f997 0x28c79780 0x04f9db27 0xa80679b9
+ 0xaca4e7ff 0x6876944b 0x26d7dbc1 0x77f7dc2a
+ 0xf0bcb163 0x1b2a8e81 0x7b90aa49 0x8d5eaf2f
+ 0x522384ae 0xae7f7082 0x412ba10a 0x1ce1baa0
+ 0x478c29b4 0x9c09b4d2 0xf225f64f 0xd43026cd
+ 0x81098579 0x7df5db05 0xa5815bb0 0xc73ee756
+ 0x9738cb95 0xa5bd62e2 0x88e2c6b2 0x778e7fcb
+ 0xd3bdb872 0x9404403f 0x5be6ad63 0x71dc4abc
+ 0x11000000 0xe5ffd18e 0x9c10c032 0xef097758
+ 0x5b44fb3b 0xabbc6973 0xb040312f 0x6267ab0a
+ 0x35ef3655 0x694c0da7 0x6eaf94db 0x293feb5f
+ 0x225a62bf 0x550edd27 0x8e4da670 0x9afcd29b
+ 0x62ad52f1 0xddcdc6fb 0x059e156b 0x9472a491
+ 0x20d8e6fb 0x7041822d 0x5af9c518 0x7e6c342f
+ 0xb113a311 0xdec46650 0x91c8a91c 0x157cde4d
+ 0xec563d5d 0x92470d0e 0x373c488c 0xf18a8f84
+ 0x757fa8ad 0xf8959ce7 0x95e1e3c9 0x47347f30
+ 0xfbd6e4a3 0x18c2f2e2 0xb6c6eb68 0xd2a81838
+ 0xa44964bb 0x36893d55 0x0b411d47 0x5addcf15
+ 0x47584269 0x972c08b3 0x0935b300 0xec7d36a7
+ 0x1c373823 0x487626be 0xacfecd64 0x6688c83c
+ 0xb96f01f9 0x2b6c9719 0x97e955da 0xc4f3b25a
+ 0xfcf12050 0x961bc5be 0x53ebb1e4 0xdc7deaa3
+ 0x3b86819a 0x7c498a21 0x129bc1b6 0x2aa5c324
+ 0x6fb58020 0x0c8e24a8 0xb7c1f0cf 0x37287581
+ 0xf417e311 0x5fd7b8cb 0xe615c56a 0x6a6c6aa7
+ 0x46c97d63 0xcc71adee 0x239b7483 0xea6750f7
+ 0x17bae7c2 0xbf4de5e1 0x6c37a1e0 0x314fc762
+ 0x68bffc94 0x4069875c 0x60d3a593 0x3a923495
+ 0x70f7a899 0xc959db6f 0xfd440374 0x0be4f668
+ 0xc15b74e9 0x9eb15fc7 0x04dc5939 0x1c2d0faf
+ 0x8ca378c9 0x15aaae90 0x2c53e471 0x2ada3977
+ 0x750d6d3b 0xd3e27cdd 0xf63ece4c 0xcbbf9463
+ 0xf0b26aad 0xacc9dc7e 0xcb2131eb 0xc2da14bc
+ 0x01b57719 0x901319e9 0x86b16d25 0x89fe5e27
+ 0xfa3135cd 0x51ebcf8e 0x91b36807 0x6efb87a1
+ 0xbe05489f 0x0461f6c7 0x4f1ddb59 0x007a7e35
+ 0xdde5c360 0xf137a520 0x153d9512 0xebe49940
+ 0xb81727b3 0xdff04ada 0x504811d5 0x6192a2a1
+ 0x418ad287 0x44278f0f 0xc8d70fcc 0x5d5953ca
+ 0xeca4ae03 0xb507f886 0x90a6726b 0xec2c60b6
+ 0xfe003923 0x8cd52bb2 0x87397bbb 0xec98c514
+ 0x28501352 0xd5518d70 0xf3258a19 0x15e4e0f4
+ 0xae272618 0x164ece6f 0x19b5449c 0x2717cf2a
+ 0xffee98cf 0xf18d6c04 0xffb6f744 0x5ed2cb50
+ 0x9421a65a 0x76150be7 0x9689d9eb 0xe6ce395b
+ 0xa5857737 0xe51b5a0f 0x5cc95766 0x365a6f04
+ 0xee8a6d1b 0x219da3e7 0x81004946 0xce4f00f9
+ 0x852eebd0 0x3a39b164 0x96863ddd 0x43b46d69
+ 0x064e138b 0x2ac312a3 0xe7eac082 0xb958803f
+ 0x3138940e 0x4c1d5d99 0x49e9ed02 0xeb3a904e
+ 0x14c2ce82 0x8449493e 0x3cdd6dbf 0xdddb592e
+ 0xaae39fca 0x163c6e65 0xee5a0e52 0xae8c2f8c
+ 0x07fd1416 0x406bd0dc 0x52811c06 0x18316363
+ 0xf954d2eb 0xa8ec83dc 0xe24996e9 0xc92af45f
+ 0x5a73f1d0 0xf5b9948f 0xa6960f5f 0xef3d1266
+ 0x97ac2b43 0x20ce72fe 0x0d774f96 0x29653967
+ 0xca765fe6 0x470ded7f 0x42a9b87e 0x3c9cfb36
+ 0xcd9354db 0x0f2fa889 0xb35e5c71 0xc3da1e0d
+ 0x85f9bfd0 0x1afc94a1 0xf05524d4 0x2b2138ef
+ 0x3c77b905 0x55d26a06 0xcc3a045d 0xad05a556
+ 0xef80f5b7 0x3ca6e8de 0xc40df9e4 0xdc5bdd8a
+ 0xdee9349d 0x258ecbc9 0xa29faf0e 0xf41daab4
+ 0x47af938b 0x6a6a1cf1 0x7a3d2f4a 0x11ede796
+ 0x61f25722 0x6864a35e 0xb4d96fae 0xcdc6a722
+ 0xce64615d 0xef56b252 0x0b89020b 0x2a1ac24c
+ 0x582c3283 0x124f274e 0xf6a58fdc 0x847c262d
+ 0x31517f9b 0x8cd34984 0xc60f7204 0xa94875c1
+ 0x12abf4e6 0xfbdd2b29 0xdb51a1c1 0xb10f9ec9
+ 0xc52b5d3c 0xfa5f75c4 0xb63c6fef 0x8ccd4fe0
+ 0x74b6cc11 0x013babd9 0x0bc30209 0xb1597dcf
+ 0xbda5ac76 0x0371d13a 0x67252505 0xf3081369
+ 0x0d7a4e53 0x25f89a9f 0xd0d9e53f 0xa25d897d
+ 0x822f83e0 0x3008eae6 0x428d3320 0x9890d235
+ 0xfec38910 0x56c87e21 0x7f7f594b 0xdf46866a
+ 0x34a34b40 0x0987267e 0xb47033d1 0x331f5d40
+ 0x935a4ec5 0xab480f95 0x1803d8e7 0x00e2e693
+ 0xab18b053 0x1cf706dd 0x7dda5849 0xb422e2e3
+ 0xba5fd0f3 0x3aee2ce1 0x33b21147 0x5fdec0d7
+ 0xd509d289 0x61187bf4 0xf7687684 0x48edbc90
+ 0x519dcd0b 0x77f026eb 0xc52eb470 0x1d4dd497
+ 0x2fa69c9c 0x8fcfef0d 0x1ed8a0b3 0x9312d199
+ 0x596b55be 0xc8c68e56 0x6aa8dc28 0x3100ec70
+ 0x737bfff7 0x40e51f14 0x695baf1f 0xad786740
+ 0x6278b108 0xcd066fb0 0x74f9d22c 0x9dd7d6f6
+ 0xc9d8d081 0xb82f32ae 0x797beeed 0xa34ce8dd
+ 0xd57ad56e 0xa4bec19f 0xe2cc7268 0xd2b85f64
+ 0x4faf835d 0xda6f3933 0x28397cd3 0x010b5a17
+ 0x6d904bfb 0x26fc2b26 0xdc7b440c 0x4e985f16
+ 0x92fb8abe 0xab8d7b77 0xb906004f 0xb0bdac98
+ 0xee64230b 0xe768ebf6 0x3c96a534 0x4e2aa084
+ 0x5f4c5c4a 0x7bff964e 0x4b4fdde3 0xfc36550b
+ 0xe90220be 0x0056c3d4 0x65599751 0x00c71265
+ 0x83011ea4 0x5bd8113f 0x616bc4ab 0xcdbbfdab
+ 0x187abde6 0xcb0b2059 0x24244c94 0xa05cac8b
+ 0x15e0e4eb 0xe93d7e1e 0xd4016e08 0x8144e1e9
+ 0x1c256625 0x841f4379 0x782edb54 0x6a70674d
+ 0x5de874f9 0x075b423b 0x71a8adc4 0x3f7c5ed1
+ 0xc045ffb0 0xd94e8bbf 0xf7ff3edc 0xb1d3aab5
+ 0x7e78f4b5 0x2e9f0c64 0x17efe45a 0x2a2dd14b
+ 0x9eda4e59 0x2c3689c7 0xe15e5efc 0xf4f11a2f
+ 0x0edb0000 0xf7afa169 0x05558b03 0x1ed6aa69
+ 0x8174d362 0x922814cc 0xcfb1c31c 0xe7cbaba6
+ 0x6aa77d7a 0xea48a37b 0x23b7a2af 0xc2b602da
+ 0x03076aeb 0xef659eb5 0x3c2833e6 0x7dd8521b
+ 0xe80a8ff3 0xe3af24d2 0x6d15f067 0x1c05b90b
+ 0x306e10ea 0xd45b1a99 0xc65a85ac 0xb4ddda13
+ 0x1f2b0bbe 0x716421c1 0x33c2f599 0x0deba688
+ 0xa44de1c2 0x1d33833e 0x3d454600 0x07cdb855
+ 0x57b42914 0x2b3015d8 0xf7893119 0xa754aa11
+ 0xfc8bab1c 0x6aabb3ff 0xeb9a35ba 0x9433e224
+ 0x88225f56 0xb3376d46 0x9203225d 0xfdd591f8
+ 0xb4452f63 0xeccbcf9c 0x60d07a28 0x021f7b69
+ 0xc355e1f5 0xdabc3f4b 0x3a3925e8 0xffc15e96
+ 0xd37cf717 0xbd580830 0x9527f96c 0x91b1119b
+ 0x527baf62 0xdcd8cb14 0xceff6ef8 0x7a64b27d
+ 0xc2bced42 0x62693867 0x171d7869 0x82a502af
+ 0x98c84c3e 0x8a0dd77e 0xcb01c7bb 0x91373992
+ 0xd28e7281 0x487d2036 0x1e98d48c 0x60f56b74
+ 0x3199129d 0xab6205ca 0x95c811b6 0xce78fbbb
+ 0x92f0b76a 0x2a448276 0x975d891a 0x5c945417
+ 0xc2ff2603 0x045c8a04 0xc8b41e0c 0x461623d6
+ 0x640bb5bd 0x386feb24 0x5ecc0bdc 0x1c56fd05
+ 0x3c6b32a1 0xde2d2b8a 0x1f76b23e 0xc78c9108
+ 0x5febf899 0x3c55d772 0x226aa903 0x4916231d
+ 0x44928c52 0x7dfe932a 0xb4420968 0x1997faaa
+ 0xb9a3dab1 0x5bec5d70 0xcb5dba0d 0xcc4052bb
+ 0xfc26b557 0xf04a044a 0x83ad1b1b 0x781935b0
+ 0xd3fe7102 0x210b7f15 0x0002e47f 0x95709de3
+ 0x7ccbab76 0x701f28b1 0xc2151880 0xb88778eb
+ 0x33bfeeb0 0x1498b52f 0x2694b5bb 0x85332e53
+ 0x103b6ddf 0xb410d999 0x3687d2fe 0x92fdecd7
+ 0x6c7d4179 0x89a2fc40 0xc8a2a4b0 0xc140a6a6
+ 0x36b20598 0x3c6e05b6 0x2d67b87b 0xc09b651c
+ 0x2cd528f0 0x2e2f38b7 0xee7fa2fb 0x84075fca
+ 0x98bacf32 0x2b965415 0xd019df29 0x83a5e980
+ 0xde8322b6 0xf592ef9d 0x22be4a4b 0x5568e883
+ 0xaf95393b 0x43b2f828 0xe44f0894 0x0c17a91a
+ 0x46271d4c 0x3ea308ba 0x757ab95f 0xeb841efb
+ 0x86def448 0x806b7e0a 0x704125ce 0xb103138d
+ 0xc70bdc0f 0x9b020964 0x8d5326c3 0x22265cf1
+ 0x07e9158e 0x1b77f0e7 0xc4249a77 0x0ec99717
+ 0x91f9860f 0xa22527bf 0x1c351901 0x8dd07723
+ 0x1b10062a 0x75db2a1b 0x300f48c7 0xe2b47dc5
+ 0xf9be873e 0xeb78cba6 0x48a02062 0xe57a4d34
+ 0x8d6d6093 0x0f3748af 0xea0fd86a 0xbb57cac5
+ 0x1aae31a2 0xc68f6732 0xfe6d09a2 0xa8ec7655
+ 0x15fb82e4 0x0fd62a02 0xde712cc6 0xa6983f8d
+ 0x0a511623 0x1802140c 0x8882d161 0x0639f7be
+ 0xca8fc8b1 0x87cc7eb0 0xaad2814b 0x53736976
+ 0xd6c2aad2 0x2ad078d6 0x8d098537 0x0d9e1f65
+ 0x060ed492 0x47fe55bd 0x56e2f9d9 0x7dafc9d5
+ 0x1f3b21fb 0xb781e9ee 0x3861d899 0x5e532398
+ 0x59813473 0xf0bae8c3 0x7b621c48 0xc6e42f38
+ 0xa779e75a 0x44fb061f 0x8e4d99dc 0x96139885
+ 0x520df1c4 0x166a3b5a 0x555f53c5 0x41f8e765
+ 0x7622012b 0x6d26b80c 0xec4292ee 0x8192e701
+ 0x6833ad36 0xa0ac765a 0x479ac6b6 0x3297deb0
+ 0x93190386 0xf349a9d8 0xff138d81 0xba18b630
+ 0xe8f5410b 0xbfe20c22 0xc233505c 0x40beb25e
+ 0xcae9866d 0x6eb2cad9 0xc2836a6e 0x66df20fe
+ 0x8faa6eb5 0xb8dfb4de 0x29e2391e 0x4e25fa37
+ 0x9b894dea 0x6210200d 0x7ebcfc1f 0x45e25079
+ 0x3a5caa11 0x45a740b0 0x3bafebb8 0x9e50294c
+ 0xa2503207 0x22f6a91d 0x04da4b6a 0xe89358d3
+ 0x5ac8cfcc 0x8b6f0821 0x85743e1c 0xf84b5389
+ 0x456ae17b 0xa51507ca 0x50cf0243 0x2701b851
+ 0x21060ad6 0x35b0d234 0x4ef230c0 0x8e8a8f08
+ 0x161949c0 0xff340399 0xdaafa36c 0xe333ae22
+ 0xeebe25ab 0xd8db6722 0x40a89344 0x9684d1ec
+ 0x357a81c5 0x6821d9d4 0xfac791fb 0x4f2dcb85
+ 0xb67017a6 0xd3234e88 0x279d5ca4 0x3f63ba99
+ 0x21622bbf 0x07caf2eb 0x8b7076ab 0x8e4ebcbd
+ 0xd10a0bfb 0xf55952f9 0xf488837a 0x8ffae6fb
+ 0x71d76515 0x44fb3730 0x7a7c61b7 0x1bd1e2de
+ 0x8a92eaaf 0xb21e7751 0xb28522e5 0xedd3b173
+ 0x03882afd 0xfab1fd71 0xf5b8d389 0x0073ba5b
+ 0x83c4bdde 0x0ae4303c 0x445ca8b9 0x6b757b77
+ 0xfeb103e9 0xccd485bc 0x0ad310c2 0xe2192e5c
+ 0x4dec1c82 0xee1986b7 0x352a80c8 0xa8151575
+ 0x6fe0d28f 0x771c3d8f 0x871e87e1 0xdacebc59
+ 0xe8ca49f6 0xb926a028 0xa6b3e515 0xefa223a5
+ 0x8a54e354 0x897e5a4d 0x21b8224d 0xd416f2ec
+ 0xcbe7f0bd 0xb2447fea 0x9e793f69 0x0fef54ad
+ 0xe8b59733 0xcf1f604a 0xb6fcca90 0x828ab637
+ 0x544d1f6a 0xd3f9bb08 0xd33e5002 0xf2bb0902
+ 0xbacb7493 0x8f49ee50 0xc8b026fd 0x548c5f6a
+ 0xa69ac56c 0x3048c9fe 0x2f4099be 0x5e2db858
+ 0x86af0440 0x63ad790c 0x2f21596a 0xa678770e
+ 0x6d35026b 0x60e5ffd7 0xd8c5ee84 0x0e8f4a5f
+ 0xb32368ab 0x06ce6d77 0xaff9a8a7 0x9b7bfe08
+ 0xf1c41bd9 0x5d97e65a 0xae3185d0 0x04a81ce0
+ 0x515afaf2 0xcc0bed19 0x7fa0ed19 0x29d747da
+ 0xb3be6d42 0xaea891fc 0x596327f6 0x169685d7
+ 0xaec527c3 0x58d7f4a5 0x1ec8f0fb 0x5121ab73
+ 0x77482d34 0xb9374023 0x593f2fb7 0x806bd03c
+ 0x0c3d2df9 0x48db6a6a 0x8d4e3bf0 0xf7c0b614
+ 0x4277692e 0x8bd2a7e8 0x2ced9478 0xd6d0958f
+ 0x1f11c590 0x64eea64e 0xfd0d9181 0xfe337731
+ 0xf2e4d68b 0x5f5c5e22 0xba1be116 0x01947bd2
+ 0x6e6f5cf0 0x99ed610b 0x1c9c6591 0xb5b9e932
+ 0x1881f045 0x4a07d22c 0x2534671a 0xf98db0e6
+ 0x3eecedcc 0x03d88a38 0x473f8803 0x0e964e29
+ 0xe7865109 0x067ce3a2 0xb67ea547 0xc9478d11
+ 0x77824680 0xe44e870b 0x26409f76 0xf56325e4
+ 0x83850a25 0x5778bde0 0xeccc9cbe 0x2b2a510c
+ 0x00fb4fe5 0xb1e44d88 0x25017b6f 0x6a07d28a
+ 0xc63259df 0x6138534e 0xb365098e 0x9063c5e5
+ 0x45457621 0x80a16d60 0xd8ace6a1 0xaf8e5612
+ 0x5a59035a 0x4a7ece35 0x2b54eda7 0x5bc3beb6
+ 0x87b79dfb 0x49145956 0xecab73c6 0x9d1929c5
+ 0x8d9a403e 0x62670b62 0x301612e1 0x55661d64
+ 0xfa4642cf 0xe995b648 0x678dfc40 0xd4ee70c9
+ 0x9b148b4a 0x26feeb0f 0x34e8c1a4 0x0eeeabf7
+ 0x3185cd83 0x17fd5de8 0x0eb47a60 0x8b390214
+ 0x813d2606 0xa98680cf 0xe1320b2c 0xb1cff298
+ 0x55954a20 0x2832306f 0x022e5c5a 0x248ace30
+ 0x12fdb8ef 0xa1ccd483 0x46722ba6 0x383957a3
+ 0x89d7daab 0x5bea5c37 0xeffde670 0x1bb5755c
+ 0xddb34251 0x97edd945 0x7538c562 0xd219d3a4
+ 0x7dd10fff 0xcd755fca 0xb6b74e08 0x953a094b
+ 0x6d5c8acc 0x17d6a577 0x5cf9cffa 0x6bef258f
+ 0x257f161c 0xefa3596d 0x2e55d01d 0x8accce49
+ 0x78637612 0xb709a740 0x9d40a46d 0xf1b76593
+ 0x941bb52f 0x72e8e334 0x731d55a9 0x28eb1126
+ 0x64488b68 0x1bc8609c 0x7ae731d3 0x6cd9e9d8
+ 0xe3f193b1 0x704102dc 0xc9c217ef 0x7334e9c6
+ 0x077bf32c 0x111e8651 0x0add1b81 0x50aa4ce6
+ 0x58931d65 0x70c12f8d 0xf958146c 0x313ec286
+ 0xb66ae984 0xeedfc1ed 0xdff5b926 0x7cd6767a
+ 0x909e1f2a 0x2e67ce4a 0x210d17a9 0x2407a7d6
+ 0xa9454c46 0x4ab7af23 0x674e4a24 0x5df3499f
+ 0x87fe9d85 0xd538b623 0xd715790a 0x5a3b6924
+ 0x98286489 0xd0e054fa 0xe0d52748 0x2cbd3b28
+ 0xed241d2b 0xf1522f35 0x2d3f6b3f 0x18adc4ba
+ 0xaed87ae4 0x8fe52079 0xde6f1284 0xbce2c970
+ 0xc3562e43 0x33707205 0x74af0b7c 0xa90d5bb6
+ 0xae850b5c 0xbba8bb6e 0x3805510b 0x78ccd517
+ 0x28139afa 0x9aa3a321 0x02577c39 0xd1339b37
+ 0xc73ab16a 0x6d219868 0xc47f0ed1 0x3d679319
+ 0xa6a0518d 0xbd8ef844 0x6c70a676 0x9f5e745c
+ 0xbbec38c8 0x085b1e7e 0x38c80048 0x73eb179f
+ 0x158edda6 0x086b980f 0xaef51250 0x4513fb22
+ 0xabb57e49 0x41d5ccde 0x47d8186e 0xc405fbba
+ 0x985881c8 0x4c20555c 0xd4719f4e 0xeb24d863
+ 0x163fce3d 0xc4083220 0x5cd27427 0xd21b3dbc
+ 0x97fd8af7 0xe936b66a 0x024e597f 0x83d45caa
+ 0xa16c668a 0xd869cff5 0x63b6d757 0xb780941a
+ 0xaa96f2d9 0xbc0661a8 0xe924336b 0x587a0117
+ 0x0dd9eba3 0x5908b928 0x336d386f 0x119dc036
+ 0x5e1ed561 0x4ad4f319 0xcf901dc1 0x154b5878
+ 0x16aec960 0xf13a5643 0xa755e201 0x9159b4ff
+ 0x983ef850 0x65d3e929 0xe310a2ed 0xd58bf035
+ 0xa2553613 0xc51f589b 0x68f3371c 0xca99ec10
+ 0xdbfc78c9 0x80c4c5dd 0x0fac0fd7 0x38a34baf
+ 0xb5a662b7 0x0be19a25 0xfae5d7ed 0xf1bfceb7
+ 0xc261e162 0xbe4990c3 0xb8911d6b 0x87738701
+ 0x9e8b4304 0x6cec1d55 0x273e2ee1 0x345a2f0e
+ 0xd5fc410f 0x25dc0844 0xff54749a 0x2a0a5364
+ 0xc8791715 0xe086fc97 0x5f757613 0x45e92b76
+ 0x87892ea6 0xe3b0e43a 0x7c648ab0 0xa3a8c54e
+ 0x5fe5a0ee 0xca7a4261 0x555ddb79 0x9d4f2a63
+ 0x74f06878 0xde200798 0xd37ae5f2 0x55d7a6c0
+ 0x5fb2dc4e 0x5b3ad326 0xb65765f5 0x63427670
+ 0x46f5c7d4 0x12307e35 0xe8a28a17 0x9db32fa6
+ 0x9adccbdd 0xc6184cae 0xfd78192b 0x926d5791
+ 0xe703b4e8 0xa5e69e45 0x88223b08 0x9e3b8a28
+ 0x0457a863 0x2a37db05 0x9153400a 0x3b8b14ac
+ 0x69bfe269 0x06f5e4bf 0xd464afa5 0x2d9a82f3
+ 0x602a92db 0x87338f91 0x67f209dd 0x5ce4b3e6
+ 0xe2809522 0xb7f94017 0xc9ece863 0xb6aeed89
+ 0x378f891f 0xcad6a973 0xb96c6cf1 0x46c60a01
+ 0xb88459d8 0xfe3e3779 0x0513a1ce 0xf400f2dd
+ 0x8f23cbec 0x2fb511e5 0xec80e04f 0xdb208487
+ 0xd314d381 0xed5d8b84 0x6da657b7 0xcb1bd0bd
+ 0xc4e9fc1e 0x2dae2765 0xa6d3b0a0 0xa1faa26b
+ 0x7cf2f561 0x4d52e032 0x1beef152 0x95950541
+ 0xf18c3dbe 0x495d0818 0x42c5a22c 0x59888e35
+ 0xeddd5cee 0xafd86b9e 0xaee47e02 0x23beeaed
+ 0xb9d6ceec 0xbeedec29 0xac32e51c 0x04c197e3
+ 0x20a135d1 0xb11448a5 0x3484ae14 0x0434b359
+ 0xef3ec2c8 0xcce90290 0xc695b789 0xd3a8b71f
+ 0x5872d621 0x722b6196 0xb616d479 0xab8a66d8
+ 0xd2e7e112 0x12349531 0xfc3e4ad3 0xb2ccdd87
+ 0x28a3bd51 0x3b16e2ed 0xf8ce78e8 0x20731a86
+ 0x5e719bfc 0x2d7ca49a 0xa3992d3f 0xe551f317
+ 0x6832634c 0x7deb4d22 0x7c0bc8f4 0x275a5782
+ 0x3fdd330f 0x138d4c4d 0xa4157e8d 0x34f2b9be
+ 0x1bf52bac 0xb9813b28 0x519dfa35 0x01e58ca5
+ 0xbc3677d8 0x939cc9d5 0x5915cfdd 0xb97cdefa
+ 0x1d15657f 0x1e72f016 0xfd2c4677 0xbc97145f
+ 0xab079f7d 0xed5e5972 0x1e190e78 0x9a1231ae
+ 0x1ed9090b 0x895ccde4 0xa937b0e6 0x60ff5871
+ 0x5847392b 0x785e17b2 0xd89b12fd 0xa0b5c7ea
+ 0x72d71263 0x9f11a27e 0x4e5409ae 0xb5f2edfa
+ 0x8798948a 0x452e74e3 0x68c95f07 0xc4f6430d
+ 0x6c46c2c4 0x2fafa74b 0x6a44c53c 0xdf7ce8c2
+ 0x51c96835 0x62970522 0x919cfe27 0x5849c94e
+ 0xbfb44809 0xb7dde12e 0x999f66cd 0x0c074754
+ 0x8f4ac0bc 0x652f9fd5 0x52b7613c 0xe04835c5
+ 0xf17a34a5 0xe2218efd 0x858ca16e 0x47eac06b
+ 0x54f66a40 0x7ea88066 0x83eb9445 0x13d13637
+ 0xfaeb75ff 0xc9a083c2 0x2cc0fd30 0xf513d44a
+ 0xf6b96811 0x4941a7a6 0xc1819a10 0x9639200a
+ 0x2cb196ad 0x8317352c 0xf10c2931 0xe713a326
+ 0x22aa792d 0xa1efb4cc 0x7c6b53d3 0xb6c87d92
+ 0x86216481 0x7f5a7163 0x2e46a131 0x70f18df8
+ 0x18964efd 0xb56cf7e8 0xe7341960 0xeec703e7
+ 0x921c12b3 0x3947abd7 0x81875a3a 0x74cce2a1
+ 0xa164461b 0x4c6dbfa3 0x8d918aa3 0xfef73a33
+ 0x66e39687 0xb464d9b4 0x42228636 0x88e403fb
+ 0xac22ae57 0xe017291b 0xf3a45b09 0xe35c2277
+ 0xe315a695 0x3f5d403a 0xed440354 0xf7b40fcf
+ 0xf539d67d 0x800f9254 0x254d971f 0x5a922b5a
+ 0x0b04d196 0x8861c8c4 0xf1066432 0x9365cca9
+ 0xcacd3a7c 0x58c10ddc 0xd411a203 0x3acda8b6
+ 0x7c3896d3 0x58c14180 0x4f17bb0a 0xcb535d3d
+ 0x00aee06a 0xa014e8e4 0x2370aebe 0x8db2890d
+ 0x32101f94 0x93e5364e 0x20947d1b 0xd14146ba
+ 0xc491e61c 0x53035a42 0x8d35e879 0x9a8b306b
+ 0xeee182bc 0x9123dcfd 0x0e077297 0x28e25da5
+ 0x165ff375 0xc95a7f9a 0xc32843c7 0xd224f615
+ 0x64ad8b3b 0x9da90396 0xa231630e 0x71806a0d
+ 0x4e2f45d6 0x21444bbe 0x986bf26a 0xd9090d2f
+ 0x0ee65758 0x54895661 0x072e3f23 0x07e350af
+ 0xe3953270 0xa7c0cfb9 0x02cecb83 0xc3f14f38
+ 0x90d6cb0b 0x16376fd3 0x359c1d26 0x86d946e7
+ 0x91dbf84d 0x81a9b349 0x9036f826 0x7932d603
+ 0x927edf94 0x18bc8d03 0x4d678541 0x17ade635
+ 0x19bb81f9 0x71f045f3 0xf4bd25ad 0xa5760638
+ 0xe756688e 0x38b29d3c 0xfb30460c 0xc68ac4d6
+ 0x06377294 0x5a327276 0x778b4a68 0x4ffa7472
+ 0x069c56e6 0xe933498a 0xef04089b 0x780a3303
+ 0x66b1e1b3 0x1c393723 0xa86b3411 0xec767268
+ 0xb97f8d53 0xccb0d910 0xb011bd4d 0xee12bfaa
+ 0x48eef80b 0x0a142e36 0x7f8f9f10 0xc78629de
+ 0x3efbf202 0x530716e3 0xd10ba525 0x54967e80
+ 0x4c6b7c05 0x9fb26e7a 0xa4a9d9c5 0xbba6cb3e
+ 0x858eb19c 0x0d944403 0x907b8c70 0xcb5f37d8
+ 0xe91b1536 0x6843e3f1 0xc8afabb4 0x8504d9e9
+ 0x1713f6c2 0x530febc2 0xb620862a 0x75e2ed50
+ 0x94163707 0x66ea0482 0xf1708bb7 0xf0677075
+ 0xeeaffe1f 0x686330a2 0xb8dfeae5 0xc6e58ec2
+ 0xcb0f62b5 0x7107d06f 0x1bce36af 0x9d99bf9f
+ 0xe79909a2 0x19a15e0a 0x82a563f5 0x5c98fb06
+ 0x594d5329 0x5e57fbe7 0xff9bbb06 0xabd6be40
+ 0x4eef225c 0x5f6062b6 0x2b61c656 0xb2f00977
+ 0x03f2993d 0x0b4f95c9 0x9ad27701 0x2e237d78
+ 0x3d0a0c21 0x81e74efd 0x7905da00 0x8853df61
+ 0x32691529 0x1e14d54a 0xcc04a569 0x4958dedb
+ 0x36482baa 0xc1ab8a83 0xca3a8c67 0xfc375fd0
+ 0xc4389c07 0x5331676a 0xdd7b2d25 0x3e524eaf
+ 0x0ed82c44 0x68dae84e 0xd141036b 0xa21d5e06
+ 0xf525fe25 0xb74132bf 0x4040013f 0x8e92884f
+ 0x97fdb7fe 0x4c0553c9 0x328a75f5 0xce5bd4a3
+ 0x4902450f 0x33469577 0x4e073acd 0xd6d93c91
+ 0xfdb7244d 0x8669429c 0x9b4c1690 0xaaccec1a
+ 0xcd1ce8e2 0x30b1b01d 0xde97ff08 0x5554be5c
+ 0xb76ae32c 0xe984e71e 0x6fb89f89 0x1d51899b
+ 0x73163e05 0x540721ff 0x39263d03 0xf51d365c
+ 0xd9957a33 0x80bb35d1 0xf3f8a2e5 0xd43952d3
+ 0x7c98bbcf 0xdb29fbdd 0x26ffef42 0x52fbe30c
+ 0x01c6cbaf 0x7bb65fa8 0x53015450 0xae920a47
+ 0x24bb2057 0x7c673ea9 0x602dbd7d 0xeb92994b
+ 0x821bc8c0 0x4fec8b18 0xf1361cf0 0xb5e99442
+ 0x7ea3b92c 0x843eb0c8 0x1631c6a5 0x38be4f7c
+ 0xaecb2505 0x96725799 0x0466b1d6 0xdbc36c3d
+ 0x15f6981d 0x2e52c8c5 0x3481eb3a 0x3384627d
+ 0xea53cf95 0xf77dec97 0x66897bc7 0x0154a1d1
+ 0x1ec26446 0x9a47eded 0x2cda2248 0x96bb98c1
+ 0xe3d4d28a 0x11533c0c 0x9bea583d 0xfe5180f5
+ 0x86180cdb 0xf067b1b2 0x581197de 0x36c2bf1d
+ 0x2d140238 0x646d3f89 0x4b4a1acb 0x35530ccd
+ 0xe87387d4 0xb2f29390 0xf9cdf459 0xae2d1802
+ 0x10d6781d 0x9a680a03 0x61f55f5c 0x6112cdde
+ 0x39aea13a 0x0986c57d 0x1274ee81 0xfc2902b0
+ 0x12035d41 0x4d3cbddf 0x2f1f6136 0x1114e937
+ 0x2b578520 0xdf9f5811 0x5545e0f9 0x3204025b
+ 0xd916ef5a 0xfb5e8c36 0x76a7b93e 0x40a881cc
+ 0xed314574 0x81fee9ca 0x5e664127 0x2567fedc
+ 0xccc24545 0x9bd63c33 0xdc875d2a 0xa991afcb
+ 0xcffb484c 0x8861201b 0x6a67fe7c 0xfcda7cba
+ 0x1f4a828e 0x7124de5b 0x93b7e81f 0x1fb316b6
+ 0xb3b7420b 0xe8dedede 0x5f2a3a0a 0xf89340ba
+ 0x4c155d52 0x7278d04d 0xa245f4a3 0x5dfcf0fb
+ 0x1adc4713 0xb85377fe 0x35138a96 0x5fac5600
+ 0xdecf8d38 0xdb4c1ffb 0xdb07469e 0x26af2008
+ 0x71531c05 0x4f269510 0x332a0060 0xcb08dff2
+ 0x48eab1db 0x88a86507 0xdf6d0501 0x36202cca
+ 0xef4cf30f 0x9abb662d 0x3ed7f0ed 0x43bcf26b
+ 0xfd9f88af 0x52b7abff 0x24d20402 0x8dbc246d
+ 0x530452a4 0x4b3714e2 0x91d99e62 0x4be86c83
+ 0xcfa73676 0x814cc9f1 0x49a05ec7 0xea75e853
+ 0xb2fae459 0xe049bf6d 0x95f9d78f 0xb512a76f
+ 0x763fb577 0x124d55c3 0x77080e28 0x89672472
+ 0xce578237 0xcf59d373 0x17a45e2d 0xaad3c482
+ 0x50161024 0xbdc8ade7 0xe9e474e0 0x30db1f08
+ 0x3e595fba 0x0bdae343 0x35fdbe82 0x03192612
+ 0x61ba73cc 0x40f41633 0xa9e1d9ca 0x4ab72299
+ 0x4e9bcaa8 0x87c09d3b 0xd5a2e624 0xfe31b004
+ 0xe080acaf 0xf52cb59f 0x0ed69789 0xbc7aae50
+ 0x097d0dc9 0xb250835a 0xac4d2b62 0x72d775ab
+ 0x29ed99ad 0xda94151f 0xd12aaa71 0xd5c01185
+ 0xb51d0b88 0x0c9d6f2d 0xa48394c5 0xdbb2d57e
+ 0x3ae4d70a 0xd6add3d7 0x4b3dc251 0xafd1be1f
+ 0x90687d0a 0x84a07d85 0xe78eca6b 0x68f66aa8
+ 0x6b64a3ee 0x44a0e334 0x8085791b 0xcc8b9893
+ 0x600ef53c 0xa4cb69a7 0x9d30e312 0x1128eb16
+ 0x4d51ce44 0xdc2d0736 0xdf605b7f 0x854b83b3
+ 0x2ee28ee7 0x16c889b3 0x2550ce0f 0x4cff4ea3
+ 0x42b5a123 0x36773c1c 0xde358d32 0x063a64a5
+ 0xca073150 0x8e55ad6d 0x358ee044 0x1afb0721
+ 0x9a3e1062 0x2bbaa6af 0x29679c34 0x7e073a7d
+ 0x3d8e6461 0x8146fcbe 0xbfc9ae45 0x893e8e8c
+ 0x06f5508c 0xad4dc27a 0x8eb524c1 0x089d6e8a
+ 0x06814420 0xf195e6a0 0x5b9651b1 0x7f55737a
+ 0xf23fb3b1 0x270a10c0 0xc6d1adf6 0x16ef7ed1
+ 0x463492b7 0xa71a7736 0xc8685ff2 0x46eebcad
+ 0x4489c299 0xc46ea5cd 0x0ba37c88 0x8e744be1
+ 0xeb2b315f 0xb3c180ee 0xab833e40 0x2223d8a2
+ 0x4e18ba02 0x830b5559 0xc100c3e5 0x89bca4cd
+ 0x43646b89 0xa94d0f31 0x517daa8f 0xf0633802
+ 0x5f2d9886 0x476f3e91 0x80a20ec9 0x65039697
+ 0x58c021c0 0x06adc086 0x9a7a6ddc 0xedd48be9
+ 0x85383dec 0xb5dea0f4 0xd3b438a3 0x20ef6788
+ 0x0334f429 0xc98fbe55 0x11a38f24 0x020f0f38
+ 0x1d6b4e0f 0x4a99af26 0x1af1d8ca 0x0f61b492
+ 0x2df039b8 0xc8db9dd9 0x978c1442 0xd43af75a
+ 0xaba9101a 0x47778b7d 0x58a36cad 0x2b062567
+ 0x1b68832e 0xe730afd3 0xd083acdf 0x4beec818
+ 0xe15e1338 0x134b9a6c 0xe5a65f74 0x82d64ded
+ 0x552ec9e0 0x36ff5ade 0x0eec84ce 0xdff77b21
+ 0xc2337bb4 0xb038c393 0x8661a487 0x1c47bd8e
+ 0x1664330e 0x4793df4e 0xba9c357b 0xbcecf2a9
+ 0xf8484a42 0x89e26341 0xdea84220 0x7173ff02
+ 0xf091e01b 0xd1789105 0x8876a7a3 0x249398c1
+ 0x35a96528 0x2c9cd555 0x8f9026bb 0x4683dfe7
+ 0x0d322c0e 0xcfdeadc2 0x2e6d657a 0x214f7fad
+ 0x1a6feb96 0x70f24984 0x1e2e919b 0x709a412c
+ 0x7c0820e0 0x4372a2e0 0x3a5fca7b 0x7e098692
+ 0xdcdadb6a 0x83bbaece 0xcf7b4ee7 0xa15deb5c
+ 0x0a5cd850 0x76432692 0xd633e87a 0x3b106b75
+ 0xfb1f675d 0xe2d75d53 0xe525819e 0x639ec794
+ 0xaf3fce1e 0x31f7c2fa 0xf62eed9a 0xa581cbe4
+ 0xdcfd3909 0x683b240a 0x5e609152 0xc011e52c
+ 0xe2b40996 0xd4a9c582 0x34f1b16e 0x67fcc219
+ 0x58554b65 0xee82ffee 0x574d2326 0xb3f72df1
+ 0xe75f740b 0x2081271b 0x21039cca 0x274f5ed9
+ 0xad0e16f1 0x92958ca8 0xbc9af36f 0xde0d81c0
+ 0x8e549069 0x7b675ff9 0xc469cd4a 0x7e9286fe
+ 0xad955974 0x5ddaf59f 0xb444e3c3 0x48c0da41
+ 0x08496091 0x13083e2e 0xd769c0e7 0x12c9c1ac
+ 0xad0eaf72 0x9fb4dc0e 0xba8dec9f 0x92ebb8b1
+ 0x17cfb953 0xbd1aa608 0xa7488be0 0x07020299
+ 0x680e40ed 0x8a1eb384 0x337e047e 0xa68e6188
+ 0x8063eb28 0xc3415333 0x4f744899 0x5c55f1d1
+ 0x8f71d1e3 0x06a02111 0x258ecec0 0x1fd1abc5
+ 0x11c9dd66 0xa4dad7d5 0xedaeecfc 0x1b172d78
+ 0x0f433cf3 0x43c8a18e 0x64af2f5a 0x08374214
+ 0x1bd2211e 0x42d44134 0xd45b7bb7 0x7f981a8e
+ 0x8ca78cbb 0xe2f1e4d6 0xb75e239a 0x43be0647
+ 0x374a4e0e 0xd9bb5925 0xcf158582 0xf229203f
+ 0x70b8fb27 0xa245b677 0xd2d8d526 0x192a9510
+ 0x83a24fed 0xdb806e4b 0xd667de62 0x79119c25
+ 0x28a26484 0x259f5647 0x38653837 0x27084263
+ 0x291da1ad 0x08629d2d 0xc645256f 0x5f5bfebc
+ 0x1c2c0a54 0xd29134d5 0xeb5f441c 0x4dcab922
+ 0x96bd0275 0x9ce7c4f4 0xe74c3ecf 0x4d7ebf4a
+ 0xccb98c87 0x4087533d 0x4bc9d551 0x1dd9b49f
+ 0x470182f8 0xe5764366 0x5cbcbbf4 0xa6e3cd20
+ 0x0beefab1 0x71e29729 0x023e9dad 0xc2816f30
+ 0x8c17209c 0xdb579ef7 0xc2f38a82 0x81219d22
+ 0xa7eaac3a 0x51b5e632 0x8cd23cfa 0x1c14a751
+ 0x4e942e65 0xa8c73ba0 0xf949b6d7 0xe78fc2f1
+ 0x89974a85 0xed5eb057 0xdee39bb6 0xed8c0cab
+ 0x2a526c09 0xcfe60940 0x0d610c5e 0x484899ee
+ 0x92d4c509 0x3d822950 0x9cc21bfc 0x8635bf03
+ 0xaca9721d 0x654adb87 0x9642ee22 0x292d68fd
+ 0x55542325 0x511bb3dd 0x0db3d7c3 0x219cfd34
+ 0x70b944ee 0x9a96b3bf 0x7c7dbd32 0x47237e37
+ 0x93236405 0xc16867a0 0x71709059 0x6a602b3c
+ 0xe0c44204 0x21c010ac 0x1114b7b2 0x994094dc
+ 0x66e3fa66 0x6abb8afa 0x3dd1c246 0x1f35d1c9
+ 0xd6386abd 0x5a1e92ef 0x8214e792 0x1742727b
+ 0xea5724b8 0xd117876c 0x8aeae636 0xc339960b
+ 0xb491151d 0x1cdc17a3 0xe583b556 0x3927556b
+ 0x56b62c9e 0xda90add3 0x2c40a08f 0xb062928a
+ 0x31b7fb6e 0xa031f67e 0x9ac90564 0x09a4791e
+ 0x8675a98c 0x14d0da71 0x9c0e13a7 0xfad7410d
+ 0xdfeab9b3 0x8f798c75 0x2359e65a 0x666c074e
+ 0x79a559b9 0x297a6cfc 0x9b80d725 0x231980df
+ 0x5aba4182 0x6b8930ed 0xfad6b3bf 0x03b99393
+ 0x2ce7b19b 0xd12071f4 0x4c2d0204 0x54833fe9
+ 0x1c8d0433 0xb32e9724 0x02a273bf 0xc52a9d5a
+ 0x62aa1fa6 0x68ca34ad 0x1ac94c91 0x1794e58d
+ 0xa74691ef 0x0e22c1d3 0x66be923f 0x6f6f2c45
+ 0x15ce79a4 0x3b8c9c40 0xa11ff2f9 0xb18f0e8a
+ 0x1e0763e8 0xab472e97 0xd011b9c7 0x7f4cd77e
+ 0x60291b08 0xfc4746db 0x1101cb2f 0x7127e03e
+ 0x39dd8454 0x9e18e09b 0x449c71ba 0xc1106522
+ 0xee38c53b 0x8e30f2a1 0x30a5c398 0xbde9c623
+ 0x49ff1078 0x36360091 0x2b797c99 0x553ff25a
+ 0x063174e2 0xcd5fb064 0xbaf1c003 0xbbbba060
+ 0x9e7bd54a 0xe3bb944c 0xa7586ca4 0x4586a706
+ 0x5bd43e12 0x9139b258 0x5962b23e 0xb20799b8
+ 0x23ef9a21 0xb505a156 0xed51d1ae 0x82dced20
+ 0xfed14015 0xe50de153 0xcb1de201 0x20407156
+ 0x6e6c8c9f 0x4e33f0f7 0xb61006ea 0x81bcca2d
+ 0x8fd94695 0x576fe5c7 0x074ff2db 0xd707ccf4
+ 0x581503ca 0xfcc1c71b 0xcfc21805 0xcb8251a8
+ 0x69361b9a 0x14ec2bbe 0x2df3d3f6 0xa5e66081
+ 0xc5c70b23 0x5dfa028b 0x22338ffa 0x1932168a
+ 0x11a0ed71 0xf676d717 0x823b48d7 0xe02bc37e
+ 0xfc624cac 0x03795ade 0x845ff149 0x5b657ed4
+ 0xbe434a2e 0x8a77afde 0x3615b39d 0xba7200d9
+ 0x674e4541 0x12f91c65 0x694cb6ab 0x22e78146
+ 0x8f574161 0x58f35068 0xce5b6f43 0xd1f0f21e
+ 0x1be73d35 0x7b2dd03f 0x39bf4987 0xd9a00a8b
+ 0xa1285004 0x64b6871e 0xee7377af 0x51d239c8
+ 0x54521a4e 0xcb661f19 0xf26dc3a8 0x8772cda3
+ 0x2c827fa9 0x16f8f76f 0x1de27a89 0xf8b4a070
+ 0xab4243b4 0x2c910203 0x1fc663ad 0xe310c2a3
+ 0x9476000d 0x11e66913 0x346d42a8 0xa513fd81
+ 0xfc260d0f 0x54c7995a 0x228585bc 0xefc0dbb0
+ 0xb9999ca4 0x7dfc9ec2 0x1556bde4 0x2749b83f
+ 0x753da831 0x5d415b40 0x763debe4 0x94a2d4df
+ 0xcc560707 0x08a3de8d 0x7d9f0997 0xe3ff555e
+ 0xa8d05131 0xc75a1e9c 0xd696df91 0x633551a7
+ 0x7ead2980 0x6c8b10b9 0x2b97f758 0xa785048f
+ 0x744ba0dc 0xd350342d 0x6dbdccaa 0x10a5e224
+ 0x0963176d 0x71a4325c 0xa9bfeca5 0x73c90b16
+ 0x5f486277 0xc897525a 0x57a8234d 0x78a73eeb
+ 0x2640604e 0x1598efd9 0x135cb408 0x486bd6d3
+ 0xef98ab1b 0x0ce2744c 0x6a690e5d 0xa65e3af1
+ 0x5263f69d 0x10feb14e 0xd857d93a 0x94d52946
+ 0x52162f56 0xe72a0b7d 0x3e7d7b23 0xdff4b663
+ 0xcbad0105 0x4886da29 0x7d5521d0 0xa37ad7b6
+ 0xe4e79a68 0x4c6cc715 0xbb746a87 0x0a222aa2
+ 0xcff26451 0xe5b51d1a 0xd786658d 0x0edc8ddc
+ 0x95a91b59 0x2b7b0dd7 0xc4003ca8 0xa90e574b
+ 0xf6d1b6c5 0x0880fcaa 0xda31fd31 0x5e2c3099
+ 0x9e9cf801 0x069347b4 0x66215bcc 0x8698d9cc
+ 0x5d53b7ce 0x3b0a3025 0x1765a598 0xba1f4f29
+ 0xa6017b4a 0x1db6bb22 0xd9b63caf 0x531e2601
+ 0x24fa819b 0x8ab091a2 0xbbc3b96a 0x6d4e061d
+ 0x5f7b1d3a 0x13fc2925 0x564b9a06 0x2b0d7a90
+ 0x933a10c7 0x8aa5e38a 0x9b79b254 0x9444c3c2
+ 0xd737212d 0xb13f74df 0x7193f8c1 0xa95f42de
+ 0x6c5a39de 0xf1263eb0 0x57c322ea 0x829cf7e7
+ 0xf8c58a2e 0x2408ad3a 0xe05fa2b7 0xf61c2132
+ 0x47bcb102 0x167f4eb3 0x6a9ca49a 0x03c76439
+ 0x69fa64cc 0xd715eab1 0x26b9ff58 0x65a0d362
+ 0x168ed37e 0x1c4f3752 0xd4e7d4de 0x26e7865d
+ 0xfbd25786 0x347be5c6 0xb610ff32 0xdae6720f
+ 0xa01ff608 0x4a093466 0x7dce182b 0x5eb3cc1e
+ 0xadd542b4 0xfff308b2 0x9deaf2fb 0xd6fa9bac
+ 0x7f1729b9 0x54ae192c 0x85e8e337 0x840f4bfc
+ 0x566993d1 0x2cf2af63 0xf86cbf7b 0xa78e4aa1
+ 0x11806adc 0x06070f3d 0xa833c724 0x3ffef088
+ 0x78febf93 0x2cf6ae38 0x8c4d8867 0x485a2845
+ 0x003a5def 0xe8d1b155 0xcb675ca8 0xcf4fec75
+ 0xb7fe3198 0xf5da0890 0x9f1599b4 0xb952a34e
+ 0x7f1bc151 0x362e7bbb 0x063507a0 0x99c65de4
+ 0xd5130eb3 0x8613ee0b 0xfd6a8987 0x01c85a32
+ 0xed25a8ce 0x3e81114d 0x3f96d0be 0xfa892912
+ 0xb8ab3d94 0x7f10a909 0xe20ebd7e 0x30e900b7
+ 0x05b0d117 0x423ee599 0xd09dacd3 0xd385eb38
+ 0xa0839eee 0x4f29f80c 0x7f253d6e 0xbc757a72
+ 0x326c615c 0x43e0c8e2 0x21771593 0xa71e6072
+ 0xf355b109 0xf2852219 0x9a6ab7b6 0x9b1c39ad
+ 0x2edb942f 0x51234e78 0xbbe44b02 0x9078446a
+ 0x1ff97b31 0xb2967297 0x5f1267ac 0xf8ccd029
+ 0x846ccba2 0x3a2a8297 0xf60c1eae 0xd8b7a467
+ 0x517e2f1f 0xe0087865 0x2a952fa4 0x75963d8d
+ 0x1bb14788 0x1375edb3 0x941303f7 0x6738a9c9
+ 0xe3c99502 0x5f42b5ec 0xb53339d3 0x65896cac
+ 0x8d992623 0x8b09fdc1 0x47e71464 0xc09733fb
+ 0xfa8cfbfe 0x898ba57d 0xe74ca247 0x4fc21f9f
+ 0xc880e39a 0x973ab5b7 0x78628ad6 0x8a6fe2a0
+ 0x92a5a189 0x7a6ff475 0x7db81d10 0x81deea09
+ 0xa4ff44fd 0x056e383e 0x7cd47b4c 0x2182a401
+ 0xd0c4ce01 0xeb313665 0x8bbb4e07 0xbb4d4a64
+ 0x15fe41cb 0x53a267ce 0x8ee4ae7c 0x01678630
+ 0xda477daf 0x7ee74db4 0xf6e9228b 0x06c57aef
+ 0x5b9c8e80 0x1e05611b 0x26682707 0x7111591a
+ 0x7646cb3b 0x20f2d117 0x4dae44a9 0x395871da
+ 0x54e6172c 0x4ab90f71 0x65209536 0xb3b57c85
+ 0x11d10b0b 0xc9e50256 0x47521f5a 0x4416012f
+ 0x6d8042b6 0x454542fa 0x77f0fea3 0xce983a27
+ 0x40f74a4e 0xabc2d476 0xcd6a647d 0xca633336
+ 0xeb7fa467 0x4b14425f 0xd7abae15 0xb9652306
+ 0x990b3a98 0x03e6f53a 0xa5f3ec3c 0xb40c953f
+ 0x5cd8470a 0xbf93da01 0x89a52e28 0x5984bd42
+ 0xe9d93e95 0xa3b67bbf 0x099ff7cf 0x07b80086
+ 0x20cdf1cb 0xcfbbdb2e 0xeb0da53d 0x33b82f36
+ 0x28fb9aca 0x013bb5b7 0xcfbfefea 0x7f4400d1
+ 0xd3ad108f 0xe32556f3 0xa9e77e41 0x92955338
+ 0x3d102663 0x63bde93f 0xbbb464c4 0xcc1ff27f
+ 0x7968d83b 0xca32b52d 0x1d4102ff 0x84cfd695
+ 0x8303a6d3 0xc6f8ba69 0xdd78d4ef 0x98b195af
+ 0x50f92a15 0x2066c503 0x61281597 0x5d0197b7
+ 0x59e6f0be 0x02423dd6 0x9b4d27af 0xb2a0755d
+ 0x72f2eb4e 0xdb5aa819 0xddb42e82 0x9688712a
+ 0xb430e384 0x6484e439 0x44f68d17 0x195c6382
+ 0xddee2db1 0xd9af2e18 0x7fbd30d6 0x2ac223db
+ 0x0d3bd809 0xec982530 0x1a41d13f 0xef2849a8
+ 0x9c233021 0xc074a29c 0xe7b8f28f 0xd0adf47f
+ 0x23cdf70d 0x6795e85d 0x1168d6ea 0x3c8bb4c7
+ 0xad1d00c9 0xf3eeb5d0 0x2f950982 0x9fbbde57
+ 0xdc733a93 0xb23e2beb 0x7dbb34af 0xf1323cff
+ 0xf6c9a9bc 0xf69900a6 0x9447ab0b 0xf03e55fa
+ 0x2816479b 0x487e507e 0x494087fb 0x0601d1ef
+ 0x27c86510 0x6a14691a 0xb78886de 0xe89e8c84
+ 0xf2cd073c 0x09144b70 0xa82227a5 0x82f88828
+ 0x71f7e10a 0x6c2b46b6 0xf813fe7d 0xf76d2602
+ 0x044d5543 0x9e1b6a76 0x967ad7b5 0xe803b0a7
+ 0x01e03dd9 0x6d5c94d8 0x112357c8 0x8e0bfe12
+ 0xcc8c7461 0xfbc1c562 0x9838886c 0xa16c46a7
+ 0x020631ad 0x70fb29ff 0x5f5f1795 0x07a762e8
+ 0x3467aa2b 0xd396d1d7 0xa12aaf4c 0xd3c13b6b
+ 0xf158d7dd 0x17b1317a 0xd847a91d 0x7612ab8e
+ >;
--
1.8.2.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 04/10] x86: ivybridge: Add microcode blobs for all the steppings
2015-12-11 10:55 ` [U-Boot] [PATCH 04/10] x86: ivybridge: Add microcode blobs for all the steppings Bin Meng
@ 2015-12-19 2:52 ` Simon Glass
2015-12-21 7:50 ` Bin Meng
0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2015-12-19 2:52 UTC (permalink / raw)
To: u-boot
On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> This adds microcode blobs created from Intel FSP package for the
> Chief River platform. They are for all the Ivy Bridge steppings:
> 306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the
> 306a9 which is already in the U-Boot tree.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> arch/x86/dts/microcode/m12306a2_00000008.dtsi | 554 +++++++++++++++++++++
> arch/x86/dts/microcode/m12306a4_00000007.dtsi | 618 +++++++++++++++++++++++
> arch/x86/dts/microcode/m12306a5_00000007.dtsi | 618 +++++++++++++++++++++++
> arch/x86/dts/microcode/m12306a8_00000010.dtsi | 682 ++++++++++++++++++++++++++
> 4 files changed, 2472 insertions(+)
> create mode 100644 arch/x86/dts/microcode/m12306a2_00000008.dtsi
> create mode 100644 arch/x86/dts/microcode/m12306a4_00000007.dtsi
> create mode 100644 arch/x86/dts/microcode/m12306a5_00000007.dtsi
> create mode 100644 arch/x86/dts/microcode/m12306a8_00000010.dtsi
Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 04/10] x86: ivybridge: Add microcode blobs for all the steppings
2015-12-19 2:52 ` Simon Glass
@ 2015-12-21 7:50 ` Bin Meng
0 siblings, 0 replies; 39+ messages in thread
From: Bin Meng @ 2015-12-21 7:50 UTC (permalink / raw)
To: u-boot
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> This adds microcode blobs created from Intel FSP package for the
>> Chief River platform. They are for all the Ivy Bridge steppings:
>> 306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the
>> 306a9 which is already in the U-Boot tree.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>> arch/x86/dts/microcode/m12306a2_00000008.dtsi | 554 +++++++++++++++++++++
>> arch/x86/dts/microcode/m12306a4_00000007.dtsi | 618 +++++++++++++++++++++++
>> arch/x86/dts/microcode/m12306a5_00000007.dtsi | 618 +++++++++++++++++++++++
>> arch/x86/dts/microcode/m12306a8_00000010.dtsi | 682 ++++++++++++++++++++++++++
>> 4 files changed, 2472 insertions(+)
>> create mode 100644 arch/x86/dts/microcode/m12306a2_00000008.dtsi
>> create mode 100644 arch/x86/dts/microcode/m12306a4_00000007.dtsi
>> create mode 100644 arch/x86/dts/microcode/m12306a5_00000007.dtsi
>> create mode 100644 arch/x86/dts/microcode/m12306a8_00000010.dtsi
>
> Acked-by: Simon Glass <sjg@chromium.org>
> Tested on link (ivybridge non-FSP)
> Tested-by: Simon Glass <sjg@chromium.org>
applied to u-boot-x86/next, thanks!
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 05/10] superio: Add SMSC SIO1007 driver
2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
` (3 preceding siblings ...)
2015-12-11 10:55 ` [U-Boot] [PATCH 04/10] x86: ivybridge: Add microcode blobs for all the steppings Bin Meng
@ 2015-12-11 10:55 ` Bin Meng
2015-12-19 2:52 ` Simon Glass
2015-12-11 10:55 ` [U-Boot] [PATCH 06/10] x86: ivybridge: Do not require HAVE_INTEL_ME Bin Meng
` (4 subsequent siblings)
9 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
To: u-boot
The SMSC SIO1007 superio chipset integrates two ns16550 compatible
serial ports for legacy applications, 16 GPIO pins and some other
functionalities like power management.
This adds a simple driver to enable serial port and handle GPIO.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
drivers/misc/Makefile | 1 +
drivers/misc/smsc_sio1007.c | 126 ++++++++++++++++++++++++++++++++++++++++++++
include/smsc_sio1007.h | 115 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 242 insertions(+)
create mode 100644 drivers/misc/smsc_sio1007.c
create mode 100644 include/smsc_sio1007.h
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index aa137f5..6952f8ce 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -29,6 +29,7 @@ ifdef CONFIG_DM_I2C
obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
endif
obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
+obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
obj-$(CONFIG_STATUS_LED) += status_led.o
obj-$(CONFIG_SANDBOX) += swap_case.o
obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c
new file mode 100644
index 0000000..79e9e15
--- /dev/null
+++ b/drivers/misc/smsc_sio1007.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <smsc_sio1007.h>
+
+static inline u8 sio1007_read(int port, int reg)
+{
+ outb(reg, port);
+
+ return inb(port + 1);
+}
+
+static inline void sio1007_write(int port, int reg, int val)
+{
+ outb(reg, port);
+ outb(val, port + 1);
+}
+
+static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set)
+{
+ sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set);
+}
+
+void sio1007_enable_serial(int port, int num, int iobase, int irq)
+{
+ if (num < 0 || num > SIO1007_UART_NUM)
+ return;
+
+ /* enter configuration state */
+ outb(0x55, port);
+
+ /* power on serial port and set up its i/o base & irq */
+ if (!num) {
+ sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON);
+ sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2);
+ sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4);
+ } else {
+ sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON);
+ sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2);
+ sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq);
+ }
+
+ /* exit configuration state */
+ outb(0xaa, port);
+}
+
+void sio1007_enable_runtime(int port, int iobase)
+{
+ /* enter configuration state */
+ outb(0x55, port);
+
+ /* set i/o base for the runtime register block */
+ sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4);
+ sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12);
+ /* turn on address decoding for this block */
+ sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN);
+
+ /* exit configuration state */
+ outb(0xaa, port);
+}
+
+void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type)
+{
+ int reg = GPIO0_DIR;
+
+ if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
+ return;
+ if (gpio >= GPIO_NUM_PER_GROUP) {
+ reg = GPIO1_DIR;
+ gpio -= GPIO_NUM_PER_GROUP;
+ }
+
+ /* enter configuration state */
+ outb(0x55, port);
+
+ /* set gpio pin direction, polority and type */
+ sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio);
+ sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio);
+ sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio);
+
+ /* exit configuration state */
+ outb(0xaa, port);
+}
+
+int sio1007_gpio_get_value(int port, int gpio)
+{
+ int reg = GPIO0_DATA;
+ int val;
+
+ if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
+ return -EINVAL;
+ if (gpio >= GPIO_NUM_PER_GROUP) {
+ reg = GPIO1_DATA;
+ gpio -= GPIO_NUM_PER_GROUP;
+ }
+
+ val = inb(port + reg);
+ if (val & (1 << gpio))
+ return 1;
+ else
+ return 0;
+}
+
+void sio1007_gpio_set_value(int port, int gpio, int val)
+{
+ int reg = GPIO0_DATA;
+ u8 data;
+
+ if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
+ return;
+ if (gpio >= GPIO_NUM_PER_GROUP) {
+ reg = GPIO1_DATA;
+ gpio -= GPIO_NUM_PER_GROUP;
+ }
+
+ data = inb(port + reg);
+ data &= ~(1 << gpio);
+ data |= (val << gpio);
+ outb(data, port + reg);
+}
diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h
new file mode 100644
index 0000000..eff57a7
--- /dev/null
+++ b/include/smsc_sio1007.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SMSC_SIO1007_H_
+#define _SMSC_SIO1007_H_
+
+/*
+ * The I/O base address of SIO1007 at power-up is determined by the SYSOPT0
+ * and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of
+ * SYSOPT0 and SYSOPT1 determines one of the following addresses.
+ */
+#define SIO1007_IOPORT0 0x002e
+#define SIO1007_IOPORT1 0x004e
+#define SIO1007_IOPORT2 0x162e
+#define SIO1007_IOPORT3 0x164e
+
+/* SIO1007 registers */
+
+#define DEV_POWER_CTRL 0x02
+#define UART1_POWER_ON (1 << 3)
+#define UART2_POWER_ON (1 << 7)
+
+#define UART1_IOBASE 0x24
+#define UART2_IOBASE 0x25
+#define UART_IRQ 0x28
+
+#define RTR_IOBASE_HIGH 0x21
+#define RTR_IOBASE_LOW 0x30
+
+#define GPIO0_DIR 0x31
+#define GPIO1_DIR 0x35
+#define GPIO_DIR_INPUT 0
+#define GPIO_DIR_OUTPUT 1
+
+#define GPIO0_POL 0x32
+#define GPIO1_POL 0x36
+#define GPIO_POL_NO_INVERT 0
+#define GPIO_POL_INVERT 1
+
+#define GPIO0_TYPE 0x33
+#define GPIO1_TYPE 0x37
+#define GPIO_TYPE_PUSH_PULL 0
+#define GPIO_TYPE_OPEN_DRAIN 1
+
+#define DEV_ACTIVATE 0x3a
+#define RTR_EN (1 << 1)
+
+/* Runtime register offset */
+
+#define GPIO0_DATA 0xc
+#define GPIO1_DATA 0xe
+
+/* Number of serial ports supported */
+#define SIO1007_UART_NUM 2
+
+/* Number of gpio pins supported */
+#define GPIO_NUM_PER_GROUP 8
+#define GPIO_GROUP_NUM 2
+#define SIO1007_GPIO_NUM (GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM)
+
+/**
+ * Configure the I/O port address of the specified serial device and
+ * enable the serial device.
+ *
+ * @port: SIO1007 I/O port address
+ * @num: serial device number (0 or 1)
+ * @iobase: processor I/O port address to assign to this serial device
+ * @irq: processor IRQ number to assign to this serial device
+ */
+void sio1007_enable_serial(int port, int num, int iobase, int irq);
+
+/**
+ * Configure the I/O port address of the runtime register block and
+ * enable the address decoding.
+ *
+ * @port: SIO1007 I/O port address
+ * @iobase: processor I/O port address to assign to the runtime registers
+ */
+void sio1007_enable_runtime(int port, int iobase);
+
+/**
+ * Configure the direction/polority/type of a specified GPIO pin
+ *
+ * @port: SIO1007 I/O port address
+ * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
+ * @dir: GPIO_DIR_INPUT or GPIO_DIR_OUTPUT
+ * @pol: GPIO_POL_NO_INVERT or GPIO_POL_INVERT
+ * @type: GPIO_TYPE_PUSH_PULL or GPIO_TYPE_OPEN_DRAIN
+ */
+void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type);
+
+/**
+ * Get a GPIO pin value.
+ * This will work whether the GPIO is an input or an output.
+ *
+ * @port: runtime register block I/O port address
+ * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
+ * @return: 0 if low, 1 if high, -EINVAL if gpio number is invalid
+ */
+int sio1007_gpio_get_value(int port, int gpio);
+
+/**
+ * Set a GPIO pin value.
+ * This will only work when the GPIO is configured as an output.
+ *
+ * @port: runtime register block I/O port address
+ * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
+ * @val: 0 if low, 1 if high
+ */
+void sio1007_gpio_set_value(int port, int gpio, int val);
+
+#endif /* _SMSC_SIO1007_H_ */
--
1.8.2.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 05/10] superio: Add SMSC SIO1007 driver
2015-12-11 10:55 ` [U-Boot] [PATCH 05/10] superio: Add SMSC SIO1007 driver Bin Meng
@ 2015-12-19 2:52 ` Simon Glass
2015-12-21 2:42 ` Bin Meng
0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2015-12-19 2:52 UTC (permalink / raw)
To: u-boot
Hi Bin,
On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> The SMSC SIO1007 superio chipset integrates two ns16550 compatible
> serial ports for legacy applications, 16 GPIO pins and some other
> functionalities like power management.
>
> This adds a simple driver to enable serial port and handle GPIO.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> drivers/misc/Makefile | 1 +
> drivers/misc/smsc_sio1007.c | 126 ++++++++++++++++++++++++++++++++++++++++++++
> include/smsc_sio1007.h | 115 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 242 insertions(+)
> create mode 100644 drivers/misc/smsc_sio1007.c
> create mode 100644 include/smsc_sio1007.h
>
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> index aa137f5..6952f8ce 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -29,6 +29,7 @@ ifdef CONFIG_DM_I2C
> obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
> endif
> obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
> +obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
> obj-$(CONFIG_STATUS_LED) += status_led.o
> obj-$(CONFIG_SANDBOX) += swap_case.o
> obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
> diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c
> new file mode 100644
> index 0000000..79e9e15
> --- /dev/null
> +++ b/drivers/misc/smsc_sio1007.c
> @@ -0,0 +1,126 @@
> +/*
> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <errno.h>
> +#include <smsc_sio1007.h>
> +
> +static inline u8 sio1007_read(int port, int reg)
> +{
> + outb(reg, port);
> +
> + return inb(port + 1);
> +}
> +
> +static inline void sio1007_write(int port, int reg, int val)
> +{
> + outb(reg, port);
> + outb(val, port + 1);
> +}
> +
> +static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set)
> +{
> + sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set);
> +}
> +
> +void sio1007_enable_serial(int port, int num, int iobase, int irq)
> +{
> + if (num < 0 || num > SIO1007_UART_NUM)
> + return;
> +
> + /* enter configuration state */
> + outb(0x55, port);
> +
> + /* power on serial port and set up its i/o base & irq */
> + if (!num) {
> + sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON);
> + sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2);
> + sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4);
> + } else {
> + sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON);
> + sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2);
> + sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq);
> + }
> +
> + /* exit configuration state */
> + outb(0xaa, port);
> +}
> +
> +void sio1007_enable_runtime(int port, int iobase)
> +{
> + /* enter configuration state */
> + outb(0x55, port);
> +
> + /* set i/o base for the runtime register block */
> + sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4);
> + sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12);
> + /* turn on address decoding for this block */
> + sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN);
> +
> + /* exit configuration state */
> + outb(0xaa, port);
> +}
> +
> +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type)
> +{
> + int reg = GPIO0_DIR;
> +
> + if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
> + return;
> + if (gpio >= GPIO_NUM_PER_GROUP) {
> + reg = GPIO1_DIR;
> + gpio -= GPIO_NUM_PER_GROUP;
> + }
> +
> + /* enter configuration state */
> + outb(0x55, port);
> +
> + /* set gpio pin direction, polority and type */
> + sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio);
> + sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio);
> + sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio);
> +
> + /* exit configuration state */
> + outb(0xaa, port);
> +}
> +
> +int sio1007_gpio_get_value(int port, int gpio)
> +{
> + int reg = GPIO0_DATA;
> + int val;
> +
> + if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
> + return -EINVAL;
> + if (gpio >= GPIO_NUM_PER_GROUP) {
> + reg = GPIO1_DATA;
> + gpio -= GPIO_NUM_PER_GROUP;
> + }
> +
> + val = inb(port + reg);
> + if (val & (1 << gpio))
> + return 1;
> + else
> + return 0;
> +}
> +
> +void sio1007_gpio_set_value(int port, int gpio, int val)
> +{
> + int reg = GPIO0_DATA;
> + u8 data;
> +
> + if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
> + return;
> + if (gpio >= GPIO_NUM_PER_GROUP) {
> + reg = GPIO1_DATA;
> + gpio -= GPIO_NUM_PER_GROUP;
> + }
> +
> + data = inb(port + reg);
> + data &= ~(1 << gpio);
> + data |= (val << gpio);
> + outb(data, port + reg);
> +}
This should be modeled as a GPIO driver in the GPIO uclass.
> diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h
> new file mode 100644
> index 0000000..eff57a7
> --- /dev/null
> +++ b/include/smsc_sio1007.h
> @@ -0,0 +1,115 @@
> +/*
> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef _SMSC_SIO1007_H_
> +#define _SMSC_SIO1007_H_
> +
> +/*
> + * The I/O base address of SIO1007 at power-up is determined by the SYSOPT0
> + * and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of
> + * SYSOPT0 and SYSOPT1 determines one of the following addresses.
> + */
> +#define SIO1007_IOPORT0 0x002e
> +#define SIO1007_IOPORT1 0x004e
> +#define SIO1007_IOPORT2 0x162e
> +#define SIO1007_IOPORT3 0x164e
> +
> +/* SIO1007 registers */
> +
> +#define DEV_POWER_CTRL 0x02
> +#define UART1_POWER_ON (1 << 3)
> +#define UART2_POWER_ON (1 << 7)
> +
> +#define UART1_IOBASE 0x24
> +#define UART2_IOBASE 0x25
> +#define UART_IRQ 0x28
> +
> +#define RTR_IOBASE_HIGH 0x21
> +#define RTR_IOBASE_LOW 0x30
> +
> +#define GPIO0_DIR 0x31
> +#define GPIO1_DIR 0x35
> +#define GPIO_DIR_INPUT 0
> +#define GPIO_DIR_OUTPUT 1
> +
> +#define GPIO0_POL 0x32
> +#define GPIO1_POL 0x36
> +#define GPIO_POL_NO_INVERT 0
> +#define GPIO_POL_INVERT 1
> +
> +#define GPIO0_TYPE 0x33
> +#define GPIO1_TYPE 0x37
> +#define GPIO_TYPE_PUSH_PULL 0
> +#define GPIO_TYPE_OPEN_DRAIN 1
> +
> +#define DEV_ACTIVATE 0x3a
> +#define RTR_EN (1 << 1)
> +
> +/* Runtime register offset */
> +
> +#define GPIO0_DATA 0xc
> +#define GPIO1_DATA 0xe
> +
> +/* Number of serial ports supported */
> +#define SIO1007_UART_NUM 2
> +
> +/* Number of gpio pins supported */
> +#define GPIO_NUM_PER_GROUP 8
> +#define GPIO_GROUP_NUM 2
> +#define SIO1007_GPIO_NUM (GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM)
> +
> +/**
> + * Configure the I/O port address of the specified serial device and
> + * enable the serial device.
> + *
> + * @port: SIO1007 I/O port address
> + * @num: serial device number (0 or 1)
> + * @iobase: processor I/O port address to assign to this serial device
> + * @irq: processor IRQ number to assign to this serial device
> + */
> +void sio1007_enable_serial(int port, int num, int iobase, int irq);
I wonder if we need a parent device which provides access to these
features, and then a GPIO child device?
> +
> +/**
> + * Configure the I/O port address of the runtime register block and
> + * enable the address decoding.
> + *
> + * @port: SIO1007 I/O port address
> + * @iobase: processor I/O port address to assign to the runtime registers
> + */
> +void sio1007_enable_runtime(int port, int iobase);
> +
> +/**
> + * Configure the direction/polority/type of a specified GPIO pin
> + *
> + * @port: SIO1007 I/O port address
> + * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
> + * @dir: GPIO_DIR_INPUT or GPIO_DIR_OUTPUT
> + * @pol: GPIO_POL_NO_INVERT or GPIO_POL_INVERT
> + * @type: GPIO_TYPE_PUSH_PULL or GPIO_TYPE_OPEN_DRAIN
> + */
> +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type);
> +
> +/**
> + * Get a GPIO pin value.
> + * This will work whether the GPIO is an input or an output.
> + *
> + * @port: runtime register block I/O port address
> + * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
> + * @return: 0 if low, 1 if high, -EINVAL if gpio number is invalid
> + */
> +int sio1007_gpio_get_value(int port, int gpio);
> +
> +/**
> + * Set a GPIO pin value.
> + * This will only work when the GPIO is configured as an output.
> + *
> + * @port: runtime register block I/O port address
> + * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
> + * @val: 0 if low, 1 if high
> + */
> +void sio1007_gpio_set_value(int port, int gpio, int val);
> +
> +#endif /* _SMSC_SIO1007_H_ */
> --
> 1.8.2.1
>
Regards,
Simon
^ permalink raw reply [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 05/10] superio: Add SMSC SIO1007 driver
2015-12-19 2:52 ` Simon Glass
@ 2015-12-21 2:42 ` Bin Meng
2016-01-06 0:24 ` Simon Glass
0 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-21 2:42 UTC (permalink / raw)
To: u-boot
Hi Simon,
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> The SMSC SIO1007 superio chipset integrates two ns16550 compatible
>> serial ports for legacy applications, 16 GPIO pins and some other
>> functionalities like power management.
>>
>> This adds a simple driver to enable serial port and handle GPIO.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>> drivers/misc/Makefile | 1 +
>> drivers/misc/smsc_sio1007.c | 126 ++++++++++++++++++++++++++++++++++++++++++++
>> include/smsc_sio1007.h | 115 ++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 242 insertions(+)
>> create mode 100644 drivers/misc/smsc_sio1007.c
>> create mode 100644 include/smsc_sio1007.h
>>
>> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
>> index aa137f5..6952f8ce 100644
>> --- a/drivers/misc/Makefile
>> +++ b/drivers/misc/Makefile
>> @@ -29,6 +29,7 @@ ifdef CONFIG_DM_I2C
>> obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
>> endif
>> obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
>> +obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
>> obj-$(CONFIG_STATUS_LED) += status_led.o
>> obj-$(CONFIG_SANDBOX) += swap_case.o
>> obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
>> diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c
>> new file mode 100644
>> index 0000000..79e9e15
>> --- /dev/null
>> +++ b/drivers/misc/smsc_sio1007.c
>> @@ -0,0 +1,126 @@
>> +/*
>> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <asm/io.h>
>> +#include <errno.h>
>> +#include <smsc_sio1007.h>
>> +
>> +static inline u8 sio1007_read(int port, int reg)
>> +{
>> + outb(reg, port);
>> +
>> + return inb(port + 1);
>> +}
>> +
>> +static inline void sio1007_write(int port, int reg, int val)
>> +{
>> + outb(reg, port);
>> + outb(val, port + 1);
>> +}
>> +
>> +static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set)
>> +{
>> + sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set);
>> +}
>> +
>> +void sio1007_enable_serial(int port, int num, int iobase, int irq)
>> +{
>> + if (num < 0 || num > SIO1007_UART_NUM)
>> + return;
>> +
>> + /* enter configuration state */
>> + outb(0x55, port);
>> +
>> + /* power on serial port and set up its i/o base & irq */
>> + if (!num) {
>> + sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON);
>> + sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2);
>> + sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4);
>> + } else {
>> + sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON);
>> + sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2);
>> + sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq);
>> + }
>> +
>> + /* exit configuration state */
>> + outb(0xaa, port);
>> +}
>> +
>> +void sio1007_enable_runtime(int port, int iobase)
>> +{
>> + /* enter configuration state */
>> + outb(0x55, port);
>> +
>> + /* set i/o base for the runtime register block */
>> + sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4);
>> + sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12);
>> + /* turn on address decoding for this block */
>> + sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN);
>> +
>> + /* exit configuration state */
>> + outb(0xaa, port);
>> +}
>> +
>> +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type)
>> +{
>> + int reg = GPIO0_DIR;
>> +
>> + if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
>> + return;
>> + if (gpio >= GPIO_NUM_PER_GROUP) {
>> + reg = GPIO1_DIR;
>> + gpio -= GPIO_NUM_PER_GROUP;
>> + }
>> +
>> + /* enter configuration state */
>> + outb(0x55, port);
>> +
>> + /* set gpio pin direction, polority and type */
>> + sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio);
>> + sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio);
>> + sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio);
>> +
>> + /* exit configuration state */
>> + outb(0xaa, port);
>> +}
>> +
>> +int sio1007_gpio_get_value(int port, int gpio)
>> +{
>> + int reg = GPIO0_DATA;
>> + int val;
>> +
>> + if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
>> + return -EINVAL;
>> + if (gpio >= GPIO_NUM_PER_GROUP) {
>> + reg = GPIO1_DATA;
>> + gpio -= GPIO_NUM_PER_GROUP;
>> + }
>> +
>> + val = inb(port + reg);
>> + if (val & (1 << gpio))
>> + return 1;
>> + else
>> + return 0;
>> +}
>> +
>> +void sio1007_gpio_set_value(int port, int gpio, int val)
>> +{
>> + int reg = GPIO0_DATA;
>> + u8 data;
>> +
>> + if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
>> + return;
>> + if (gpio >= GPIO_NUM_PER_GROUP) {
>> + reg = GPIO1_DATA;
>> + gpio -= GPIO_NUM_PER_GROUP;
>> + }
>> +
>> + data = inb(port + reg);
>> + data &= ~(1 << gpio);
>> + data |= (val << gpio);
>> + outb(data, port + reg);
>> +}
>
> This should be modeled as a GPIO driver in the GPIO uclass.
>
>> diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h
>> new file mode 100644
>> index 0000000..eff57a7
>> --- /dev/null
>> +++ b/include/smsc_sio1007.h
>> @@ -0,0 +1,115 @@
>> +/*
>> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#ifndef _SMSC_SIO1007_H_
>> +#define _SMSC_SIO1007_H_
>> +
>> +/*
>> + * The I/O base address of SIO1007 at power-up is determined by the SYSOPT0
>> + * and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of
>> + * SYSOPT0 and SYSOPT1 determines one of the following addresses.
>> + */
>> +#define SIO1007_IOPORT0 0x002e
>> +#define SIO1007_IOPORT1 0x004e
>> +#define SIO1007_IOPORT2 0x162e
>> +#define SIO1007_IOPORT3 0x164e
>> +
>> +/* SIO1007 registers */
>> +
>> +#define DEV_POWER_CTRL 0x02
>> +#define UART1_POWER_ON (1 << 3)
>> +#define UART2_POWER_ON (1 << 7)
>> +
>> +#define UART1_IOBASE 0x24
>> +#define UART2_IOBASE 0x25
>> +#define UART_IRQ 0x28
>> +
>> +#define RTR_IOBASE_HIGH 0x21
>> +#define RTR_IOBASE_LOW 0x30
>> +
>> +#define GPIO0_DIR 0x31
>> +#define GPIO1_DIR 0x35
>> +#define GPIO_DIR_INPUT 0
>> +#define GPIO_DIR_OUTPUT 1
>> +
>> +#define GPIO0_POL 0x32
>> +#define GPIO1_POL 0x36
>> +#define GPIO_POL_NO_INVERT 0
>> +#define GPIO_POL_INVERT 1
>> +
>> +#define GPIO0_TYPE 0x33
>> +#define GPIO1_TYPE 0x37
>> +#define GPIO_TYPE_PUSH_PULL 0
>> +#define GPIO_TYPE_OPEN_DRAIN 1
>> +
>> +#define DEV_ACTIVATE 0x3a
>> +#define RTR_EN (1 << 1)
>> +
>> +/* Runtime register offset */
>> +
>> +#define GPIO0_DATA 0xc
>> +#define GPIO1_DATA 0xe
>> +
>> +/* Number of serial ports supported */
>> +#define SIO1007_UART_NUM 2
>> +
>> +/* Number of gpio pins supported */
>> +#define GPIO_NUM_PER_GROUP 8
>> +#define GPIO_GROUP_NUM 2
>> +#define SIO1007_GPIO_NUM (GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM)
>> +
>> +/**
>> + * Configure the I/O port address of the specified serial device and
>> + * enable the serial device.
>> + *
>> + * @port: SIO1007 I/O port address
>> + * @num: serial device number (0 or 1)
>> + * @iobase: processor I/O port address to assign to this serial device
>> + * @irq: processor IRQ number to assign to this serial device
>> + */
>> +void sio1007_enable_serial(int port, int num, int iobase, int irq);
>
> I wonder if we need a parent device which provides access to these
> features, and then a GPIO child device?
I was thinking we create a superio uclass for this, but I found it's
not generic enough to abstract the ops for this uclass, if we take a
look at the existing SMSC LPC47M and this new one. Given these
routines will only need to be called just once during boot up, I
decided not to use driver model on this type of device.
>
>> +
>> +/**
>> + * Configure the I/O port address of the runtime register block and
>> + * enable the address decoding.
>> + *
>> + * @port: SIO1007 I/O port address
>> + * @iobase: processor I/O port address to assign to the runtime registers
>> + */
>> +void sio1007_enable_runtime(int port, int iobase);
>> +
>> +/**
>> + * Configure the direction/polority/type of a specified GPIO pin
>> + *
>> + * @port: SIO1007 I/O port address
>> + * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
>> + * @dir: GPIO_DIR_INPUT or GPIO_DIR_OUTPUT
>> + * @pol: GPIO_POL_NO_INVERT or GPIO_POL_INVERT
>> + * @type: GPIO_TYPE_PUSH_PULL or GPIO_TYPE_OPEN_DRAIN
>> + */
>> +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type);
>> +
>> +/**
>> + * Get a GPIO pin value.
>> + * This will work whether the GPIO is an input or an output.
>> + *
>> + * @port: runtime register block I/O port address
>> + * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
>> + * @return: 0 if low, 1 if high, -EINVAL if gpio number is invalid
>> + */
>> +int sio1007_gpio_get_value(int port, int gpio);
>> +
>> +/**
>> + * Set a GPIO pin value.
>> + * This will only work when the GPIO is configured as an output.
>> + *
>> + * @port: runtime register block I/O port address
>> + * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
>> + * @val: 0 if low, 1 if high
>> + */
>> +void sio1007_gpio_set_value(int port, int gpio, int val);
>> +
>> +#endif /* _SMSC_SIO1007_H_ */
>> --
>> 1.8.2.1
>>
Regards,
Bin
^ permalink raw reply [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 05/10] superio: Add SMSC SIO1007 driver
2015-12-21 2:42 ` Bin Meng
@ 2016-01-06 0:24 ` Simon Glass
2016-01-26 8:29 ` Bin Meng
0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2016-01-06 0:24 UTC (permalink / raw)
To: u-boot
Hi Bin,
On 20 December 2015 at 19:42, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
>> Hi Bin,
>>
>> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> The SMSC SIO1007 superio chipset integrates two ns16550 compatible
>>> serial ports for legacy applications, 16 GPIO pins and some other
>>> functionalities like power management.
>>>
>>> This adds a simple driver to enable serial port and handle GPIO.
>>>
>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>> ---
>>>
>>> drivers/misc/Makefile | 1 +
>>> drivers/misc/smsc_sio1007.c | 126 ++++++++++++++++++++++++++++++++++++++++++++
>>> include/smsc_sio1007.h | 115 ++++++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 242 insertions(+)
>>> create mode 100644 drivers/misc/smsc_sio1007.c
>>> create mode 100644 include/smsc_sio1007.h
>>>
>>> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
>>> index aa137f5..6952f8ce 100644
>>> --- a/drivers/misc/Makefile
>>> +++ b/drivers/misc/Makefile
>>> @@ -29,6 +29,7 @@ ifdef CONFIG_DM_I2C
>>> obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
>>> endif
>>> obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
>>> +obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
>>> obj-$(CONFIG_STATUS_LED) += status_led.o
>>> obj-$(CONFIG_SANDBOX) += swap_case.o
>>> obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
>>> diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c
>>> new file mode 100644
>>> index 0000000..79e9e15
>>> --- /dev/null
>>> +++ b/drivers/misc/smsc_sio1007.c
>>> @@ -0,0 +1,126 @@
>>> +/*
>>> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0+
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <asm/io.h>
>>> +#include <errno.h>
>>> +#include <smsc_sio1007.h>
>>> +
>>> +static inline u8 sio1007_read(int port, int reg)
>>> +{
>>> + outb(reg, port);
>>> +
>>> + return inb(port + 1);
>>> +}
>>> +
>>> +static inline void sio1007_write(int port, int reg, int val)
>>> +{
>>> + outb(reg, port);
>>> + outb(val, port + 1);
>>> +}
>>> +
>>> +static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set)
>>> +{
>>> + sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set);
>>> +}
>>> +
>>> +void sio1007_enable_serial(int port, int num, int iobase, int irq)
>>> +{
>>> + if (num < 0 || num > SIO1007_UART_NUM)
>>> + return;
>>> +
>>> + /* enter configuration state */
>>> + outb(0x55, port);
>>> +
>>> + /* power on serial port and set up its i/o base & irq */
>>> + if (!num) {
>>> + sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON);
>>> + sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2);
>>> + sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4);
>>> + } else {
>>> + sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON);
>>> + sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2);
>>> + sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq);
>>> + }
>>> +
>>> + /* exit configuration state */
>>> + outb(0xaa, port);
>>> +}
>>> +
>>> +void sio1007_enable_runtime(int port, int iobase)
>>> +{
>>> + /* enter configuration state */
>>> + outb(0x55, port);
>>> +
>>> + /* set i/o base for the runtime register block */
>>> + sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4);
>>> + sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12);
>>> + /* turn on address decoding for this block */
>>> + sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN);
>>> +
>>> + /* exit configuration state */
>>> + outb(0xaa, port);
>>> +}
>>> +
>>> +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type)
>>> +{
>>> + int reg = GPIO0_DIR;
>>> +
>>> + if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
>>> + return;
>>> + if (gpio >= GPIO_NUM_PER_GROUP) {
>>> + reg = GPIO1_DIR;
>>> + gpio -= GPIO_NUM_PER_GROUP;
>>> + }
>>> +
>>> + /* enter configuration state */
>>> + outb(0x55, port);
>>> +
>>> + /* set gpio pin direction, polority and type */
>>> + sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio);
>>> + sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio);
>>> + sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio);
>>> +
>>> + /* exit configuration state */
>>> + outb(0xaa, port);
>>> +}
>>> +
>>> +int sio1007_gpio_get_value(int port, int gpio)
>>> +{
>>> + int reg = GPIO0_DATA;
>>> + int val;
>>> +
>>> + if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
>>> + return -EINVAL;
>>> + if (gpio >= GPIO_NUM_PER_GROUP) {
>>> + reg = GPIO1_DATA;
>>> + gpio -= GPIO_NUM_PER_GROUP;
>>> + }
>>> +
>>> + val = inb(port + reg);
>>> + if (val & (1 << gpio))
>>> + return 1;
>>> + else
>>> + return 0;
>>> +}
>>> +
>>> +void sio1007_gpio_set_value(int port, int gpio, int val)
>>> +{
>>> + int reg = GPIO0_DATA;
>>> + u8 data;
>>> +
>>> + if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
>>> + return;
>>> + if (gpio >= GPIO_NUM_PER_GROUP) {
>>> + reg = GPIO1_DATA;
>>> + gpio -= GPIO_NUM_PER_GROUP;
>>> + }
>>> +
>>> + data = inb(port + reg);
>>> + data &= ~(1 << gpio);
>>> + data |= (val << gpio);
>>> + outb(data, port + reg);
>>> +}
>>
>> This should be modeled as a GPIO driver in the GPIO uclass.
>>
>>> diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h
>>> new file mode 100644
>>> index 0000000..eff57a7
>>> --- /dev/null
>>> +++ b/include/smsc_sio1007.h
>>> @@ -0,0 +1,115 @@
>>> +/*
>>> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0+
>>> + */
>>> +
>>> +#ifndef _SMSC_SIO1007_H_
>>> +#define _SMSC_SIO1007_H_
>>> +
>>> +/*
>>> + * The I/O base address of SIO1007 at power-up is determined by the SYSOPT0
>>> + * and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of
>>> + * SYSOPT0 and SYSOPT1 determines one of the following addresses.
>>> + */
>>> +#define SIO1007_IOPORT0 0x002e
>>> +#define SIO1007_IOPORT1 0x004e
>>> +#define SIO1007_IOPORT2 0x162e
>>> +#define SIO1007_IOPORT3 0x164e
>>> +
>>> +/* SIO1007 registers */
>>> +
>>> +#define DEV_POWER_CTRL 0x02
>>> +#define UART1_POWER_ON (1 << 3)
>>> +#define UART2_POWER_ON (1 << 7)
>>> +
>>> +#define UART1_IOBASE 0x24
>>> +#define UART2_IOBASE 0x25
>>> +#define UART_IRQ 0x28
>>> +
>>> +#define RTR_IOBASE_HIGH 0x21
>>> +#define RTR_IOBASE_LOW 0x30
>>> +
>>> +#define GPIO0_DIR 0x31
>>> +#define GPIO1_DIR 0x35
>>> +#define GPIO_DIR_INPUT 0
>>> +#define GPIO_DIR_OUTPUT 1
>>> +
>>> +#define GPIO0_POL 0x32
>>> +#define GPIO1_POL 0x36
>>> +#define GPIO_POL_NO_INVERT 0
>>> +#define GPIO_POL_INVERT 1
>>> +
>>> +#define GPIO0_TYPE 0x33
>>> +#define GPIO1_TYPE 0x37
>>> +#define GPIO_TYPE_PUSH_PULL 0
>>> +#define GPIO_TYPE_OPEN_DRAIN 1
>>> +
>>> +#define DEV_ACTIVATE 0x3a
>>> +#define RTR_EN (1 << 1)
>>> +
>>> +/* Runtime register offset */
>>> +
>>> +#define GPIO0_DATA 0xc
>>> +#define GPIO1_DATA 0xe
>>> +
>>> +/* Number of serial ports supported */
>>> +#define SIO1007_UART_NUM 2
>>> +
>>> +/* Number of gpio pins supported */
>>> +#define GPIO_NUM_PER_GROUP 8
>>> +#define GPIO_GROUP_NUM 2
>>> +#define SIO1007_GPIO_NUM (GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM)
>>> +
>>> +/**
>>> + * Configure the I/O port address of the specified serial device and
>>> + * enable the serial device.
>>> + *
>>> + * @port: SIO1007 I/O port address
>>> + * @num: serial device number (0 or 1)
>>> + * @iobase: processor I/O port address to assign to this serial device
>>> + * @irq: processor IRQ number to assign to this serial device
>>> + */
>>> +void sio1007_enable_serial(int port, int num, int iobase, int irq);
>>
>> I wonder if we need a parent device which provides access to these
>> features, and then a GPIO child device?
>
> I was thinking we create a superio uclass for this, but I found it's
> not generic enough to abstract the ops for this uclass, if we take a
> look at the existing SMSC LPC47M and this new one. Given these
> routines will only need to be called just once during boot up, I
> decided not to use driver model on this type of device.
>
But won't we want to use the 'gpio' command to access these GPIOs?
>>
>>> +
>>> +/**
>>> + * Configure the I/O port address of the runtime register block and
>>> + * enable the address decoding.
>>> + *
>>> + * @port: SIO1007 I/O port address
>>> + * @iobase: processor I/O port address to assign to the runtime registers
>>> + */
>>> +void sio1007_enable_runtime(int port, int iobase);
>>> +
>>> +/**
>>> + * Configure the direction/polority/type of a specified GPIO pin
>>> + *
>>> + * @port: SIO1007 I/O port address
>>> + * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
>>> + * @dir: GPIO_DIR_INPUT or GPIO_DIR_OUTPUT
>>> + * @pol: GPIO_POL_NO_INVERT or GPIO_POL_INVERT
>>> + * @type: GPIO_TYPE_PUSH_PULL or GPIO_TYPE_OPEN_DRAIN
>>> + */
>>> +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type);
>>> +
>>> +/**
>>> + * Get a GPIO pin value.
>>> + * This will work whether the GPIO is an input or an output.
>>> + *
>>> + * @port: runtime register block I/O port address
>>> + * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
>>> + * @return: 0 if low, 1 if high, -EINVAL if gpio number is invalid
>>> + */
>>> +int sio1007_gpio_get_value(int port, int gpio);
>>> +
>>> +/**
>>> + * Set a GPIO pin value.
>>> + * This will only work when the GPIO is configured as an output.
>>> + *
>>> + * @port: runtime register block I/O port address
>>> + * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
>>> + * @val: 0 if low, 1 if high
>>> + */
>>> +void sio1007_gpio_set_value(int port, int gpio, int val);
>>> +
>>> +#endif /* _SMSC_SIO1007_H_ */
>>> --
>>> 1.8.2.1
>>>
>
> Regards,
> Bin
Regards,
Simon
^ permalink raw reply [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 05/10] superio: Add SMSC SIO1007 driver
2016-01-06 0:24 ` Simon Glass
@ 2016-01-26 8:29 ` Bin Meng
2016-01-26 17:03 ` Simon Glass
0 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2016-01-26 8:29 UTC (permalink / raw)
To: u-boot
Hi Simon,
On Wed, Jan 6, 2016 at 8:24 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 20 December 2015 at 19:42, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Hi Simon,
>>
>> On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
>>> Hi Bin,
>>>
>>> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>> The SMSC SIO1007 superio chipset integrates two ns16550 compatible
>>>> serial ports for legacy applications, 16 GPIO pins and some other
>>>> functionalities like power management.
>>>>
>>>> This adds a simple driver to enable serial port and handle GPIO.
>>>>
>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>>> ---
>>>>
>>>> drivers/misc/Makefile | 1 +
>>>> drivers/misc/smsc_sio1007.c | 126 ++++++++++++++++++++++++++++++++++++++++++++
>>>> include/smsc_sio1007.h | 115 ++++++++++++++++++++++++++++++++++++++++
>>>> 3 files changed, 242 insertions(+)
>>>> create mode 100644 drivers/misc/smsc_sio1007.c
>>>> create mode 100644 include/smsc_sio1007.h
>>>>
>>>> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
>>>> index aa137f5..6952f8ce 100644
>>>> --- a/drivers/misc/Makefile
>>>> +++ b/drivers/misc/Makefile
>>>> @@ -29,6 +29,7 @@ ifdef CONFIG_DM_I2C
>>>> obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
>>>> endif
>>>> obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
>>>> +obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
>>>> obj-$(CONFIG_STATUS_LED) += status_led.o
>>>> obj-$(CONFIG_SANDBOX) += swap_case.o
>>>> obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
>>>> diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c
>>>> new file mode 100644
>>>> index 0000000..79e9e15
>>>> --- /dev/null
>>>> +++ b/drivers/misc/smsc_sio1007.c
>>>> @@ -0,0 +1,126 @@
>>>> +/*
>>>> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
>>>> + *
>>>> + * SPDX-License-Identifier: GPL-2.0+
>>>> + */
>>>> +
>>>> +#include <common.h>
>>>> +#include <asm/io.h>
>>>> +#include <errno.h>
>>>> +#include <smsc_sio1007.h>
>>>> +
>>>> +static inline u8 sio1007_read(int port, int reg)
>>>> +{
>>>> + outb(reg, port);
>>>> +
>>>> + return inb(port + 1);
>>>> +}
>>>> +
>>>> +static inline void sio1007_write(int port, int reg, int val)
>>>> +{
>>>> + outb(reg, port);
>>>> + outb(val, port + 1);
>>>> +}
>>>> +
>>>> +static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set)
>>>> +{
>>>> + sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set);
>>>> +}
>>>> +
>>>> +void sio1007_enable_serial(int port, int num, int iobase, int irq)
>>>> +{
>>>> + if (num < 0 || num > SIO1007_UART_NUM)
>>>> + return;
>>>> +
>>>> + /* enter configuration state */
>>>> + outb(0x55, port);
>>>> +
>>>> + /* power on serial port and set up its i/o base & irq */
>>>> + if (!num) {
>>>> + sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON);
>>>> + sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2);
>>>> + sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4);
>>>> + } else {
>>>> + sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON);
>>>> + sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2);
>>>> + sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq);
>>>> + }
>>>> +
>>>> + /* exit configuration state */
>>>> + outb(0xaa, port);
>>>> +}
>>>> +
>>>> +void sio1007_enable_runtime(int port, int iobase)
>>>> +{
>>>> + /* enter configuration state */
>>>> + outb(0x55, port);
>>>> +
>>>> + /* set i/o base for the runtime register block */
>>>> + sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4);
>>>> + sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12);
>>>> + /* turn on address decoding for this block */
>>>> + sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN);
>>>> +
>>>> + /* exit configuration state */
>>>> + outb(0xaa, port);
>>>> +}
>>>> +
>>>> +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type)
>>>> +{
>>>> + int reg = GPIO0_DIR;
>>>> +
>>>> + if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
>>>> + return;
>>>> + if (gpio >= GPIO_NUM_PER_GROUP) {
>>>> + reg = GPIO1_DIR;
>>>> + gpio -= GPIO_NUM_PER_GROUP;
>>>> + }
>>>> +
>>>> + /* enter configuration state */
>>>> + outb(0x55, port);
>>>> +
>>>> + /* set gpio pin direction, polority and type */
>>>> + sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio);
>>>> + sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio);
>>>> + sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio);
>>>> +
>>>> + /* exit configuration state */
>>>> + outb(0xaa, port);
>>>> +}
>>>> +
>>>> +int sio1007_gpio_get_value(int port, int gpio)
>>>> +{
>>>> + int reg = GPIO0_DATA;
>>>> + int val;
>>>> +
>>>> + if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
>>>> + return -EINVAL;
>>>> + if (gpio >= GPIO_NUM_PER_GROUP) {
>>>> + reg = GPIO1_DATA;
>>>> + gpio -= GPIO_NUM_PER_GROUP;
>>>> + }
>>>> +
>>>> + val = inb(port + reg);
>>>> + if (val & (1 << gpio))
>>>> + return 1;
>>>> + else
>>>> + return 0;
>>>> +}
>>>> +
>>>> +void sio1007_gpio_set_value(int port, int gpio, int val)
>>>> +{
>>>> + int reg = GPIO0_DATA;
>>>> + u8 data;
>>>> +
>>>> + if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
>>>> + return;
>>>> + if (gpio >= GPIO_NUM_PER_GROUP) {
>>>> + reg = GPIO1_DATA;
>>>> + gpio -= GPIO_NUM_PER_GROUP;
>>>> + }
>>>> +
>>>> + data = inb(port + reg);
>>>> + data &= ~(1 << gpio);
>>>> + data |= (val << gpio);
>>>> + outb(data, port + reg);
>>>> +}
>>>
>>> This should be modeled as a GPIO driver in the GPIO uclass.
>>>
>>>> diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h
>>>> new file mode 100644
>>>> index 0000000..eff57a7
>>>> --- /dev/null
>>>> +++ b/include/smsc_sio1007.h
>>>> @@ -0,0 +1,115 @@
>>>> +/*
>>>> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
>>>> + *
>>>> + * SPDX-License-Identifier: GPL-2.0+
>>>> + */
>>>> +
>>>> +#ifndef _SMSC_SIO1007_H_
>>>> +#define _SMSC_SIO1007_H_
>>>> +
>>>> +/*
>>>> + * The I/O base address of SIO1007 at power-up is determined by the SYSOPT0
>>>> + * and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of
>>>> + * SYSOPT0 and SYSOPT1 determines one of the following addresses.
>>>> + */
>>>> +#define SIO1007_IOPORT0 0x002e
>>>> +#define SIO1007_IOPORT1 0x004e
>>>> +#define SIO1007_IOPORT2 0x162e
>>>> +#define SIO1007_IOPORT3 0x164e
>>>> +
>>>> +/* SIO1007 registers */
>>>> +
>>>> +#define DEV_POWER_CTRL 0x02
>>>> +#define UART1_POWER_ON (1 << 3)
>>>> +#define UART2_POWER_ON (1 << 7)
>>>> +
>>>> +#define UART1_IOBASE 0x24
>>>> +#define UART2_IOBASE 0x25
>>>> +#define UART_IRQ 0x28
>>>> +
>>>> +#define RTR_IOBASE_HIGH 0x21
>>>> +#define RTR_IOBASE_LOW 0x30
>>>> +
>>>> +#define GPIO0_DIR 0x31
>>>> +#define GPIO1_DIR 0x35
>>>> +#define GPIO_DIR_INPUT 0
>>>> +#define GPIO_DIR_OUTPUT 1
>>>> +
>>>> +#define GPIO0_POL 0x32
>>>> +#define GPIO1_POL 0x36
>>>> +#define GPIO_POL_NO_INVERT 0
>>>> +#define GPIO_POL_INVERT 1
>>>> +
>>>> +#define GPIO0_TYPE 0x33
>>>> +#define GPIO1_TYPE 0x37
>>>> +#define GPIO_TYPE_PUSH_PULL 0
>>>> +#define GPIO_TYPE_OPEN_DRAIN 1
>>>> +
>>>> +#define DEV_ACTIVATE 0x3a
>>>> +#define RTR_EN (1 << 1)
>>>> +
>>>> +/* Runtime register offset */
>>>> +
>>>> +#define GPIO0_DATA 0xc
>>>> +#define GPIO1_DATA 0xe
>>>> +
>>>> +/* Number of serial ports supported */
>>>> +#define SIO1007_UART_NUM 2
>>>> +
>>>> +/* Number of gpio pins supported */
>>>> +#define GPIO_NUM_PER_GROUP 8
>>>> +#define GPIO_GROUP_NUM 2
>>>> +#define SIO1007_GPIO_NUM (GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM)
>>>> +
>>>> +/**
>>>> + * Configure the I/O port address of the specified serial device and
>>>> + * enable the serial device.
>>>> + *
>>>> + * @port: SIO1007 I/O port address
>>>> + * @num: serial device number (0 or 1)
>>>> + * @iobase: processor I/O port address to assign to this serial device
>>>> + * @irq: processor IRQ number to assign to this serial device
>>>> + */
>>>> +void sio1007_enable_serial(int port, int num, int iobase, int irq);
>>>
>>> I wonder if we need a parent device which provides access to these
>>> features, and then a GPIO child device?
>>
>> I was thinking we create a superio uclass for this, but I found it's
>> not generic enough to abstract the ops for this uclass, if we take a
>> look at the existing SMSC LPC47M and this new one. Given these
>> routines will only need to be called just once during boot up, I
>> decided not to use driver model on this type of device.
>>
>
> But won't we want to use the 'gpio' command to access these GPIOs?
>
I don't see value of accessing them after boot. Also as you can see,
these superio chipsets are really not good candidates to model. To
operate on a specific GPIO pin, we need access two IO ports which
looks quite weird, but unfortunately that is how the chipset was
designed :(
[snip]
Regards,
Bin
^ permalink raw reply [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 05/10] superio: Add SMSC SIO1007 driver
2016-01-26 8:29 ` Bin Meng
@ 2016-01-26 17:03 ` Simon Glass
0 siblings, 0 replies; 39+ messages in thread
From: Simon Glass @ 2016-01-26 17:03 UTC (permalink / raw)
To: u-boot
Hi Bin,
On 26 January 2016 at 01:29, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Wed, Jan 6, 2016 at 8:24 AM, Simon Glass <sjg@chromium.org> wrote:
> > Hi Bin,
> >
> > On 20 December 2015 at 19:42, Bin Meng <bmeng.cn@gmail.com> wrote:
> >> Hi Simon,
> >>
> >> On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> >>> Hi Bin,
> >>>
> >>> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> >>>> The SMSC SIO1007 superio chipset integrates two ns16550 compatible
> >>>> serial ports for legacy applications, 16 GPIO pins and some other
> >>>> functionalities like power management.
> >>>>
> >>>> This adds a simple driver to enable serial port and handle GPIO.
> >>>>
> >>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> >>>> ---
> >>>>
> >>>> drivers/misc/Makefile | 1 +
> >>>> drivers/misc/smsc_sio1007.c | 126 ++++++++++++++++++++++++++++++++++++++++++++
> >>>> include/smsc_sio1007.h | 115 ++++++++++++++++++++++++++++++++++++++++
> >>>> 3 files changed, 242 insertions(+)
> >>>> create mode 100644 drivers/misc/smsc_sio1007.c
> >>>> create mode 100644 include/smsc_sio1007.h
> >>>>
> >>>> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> >>>> index aa137f5..6952f8ce 100644
> >>>> --- a/drivers/misc/Makefile
> >>>> +++ b/drivers/misc/Makefile
> >>>> @@ -29,6 +29,7 @@ ifdef CONFIG_DM_I2C
> >>>> obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
> >>>> endif
> >>>> obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
> >>>> +obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
> >>>> obj-$(CONFIG_STATUS_LED) += status_led.o
> >>>> obj-$(CONFIG_SANDBOX) += swap_case.o
> >>>> obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
> >>>> diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c
> >>>> new file mode 100644
> >>>> index 0000000..79e9e15
> >>>> --- /dev/null
> >>>> +++ b/drivers/misc/smsc_sio1007.c
> >>>> @@ -0,0 +1,126 @@
> >>>> +/*
> >>>> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
> >>>> + *
> >>>> + * SPDX-License-Identifier: GPL-2.0+
> >>>> + */
> >>>> +
> >>>> +#include <common.h>
> >>>> +#include <asm/io.h>
> >>>> +#include <errno.h>
> >>>> +#include <smsc_sio1007.h>
> >>>> +
> >>>> +static inline u8 sio1007_read(int port, int reg)
> >>>> +{
> >>>> + outb(reg, port);
> >>>> +
> >>>> + return inb(port + 1);
> >>>> +}
> >>>> +
> >>>> +static inline void sio1007_write(int port, int reg, int val)
> >>>> +{
> >>>> + outb(reg, port);
> >>>> + outb(val, port + 1);
> >>>> +}
> >>>> +
> >>>> +static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set)
> >>>> +{
> >>>> + sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set);
> >>>> +}
> >>>> +
> >>>> +void sio1007_enable_serial(int port, int num, int iobase, int irq)
> >>>> +{
> >>>> + if (num < 0 || num > SIO1007_UART_NUM)
> >>>> + return;
> >>>> +
> >>>> + /* enter configuration state */
> >>>> + outb(0x55, port);
> >>>> +
> >>>> + /* power on serial port and set up its i/o base & irq */
> >>>> + if (!num) {
> >>>> + sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON);
> >>>> + sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2);
> >>>> + sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4);
> >>>> + } else {
> >>>> + sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON);
> >>>> + sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2);
> >>>> + sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq);
> >>>> + }
> >>>> +
> >>>> + /* exit configuration state */
> >>>> + outb(0xaa, port);
> >>>> +}
> >>>> +
> >>>> +void sio1007_enable_runtime(int port, int iobase)
> >>>> +{
> >>>> + /* enter configuration state */
> >>>> + outb(0x55, port);
> >>>> +
> >>>> + /* set i/o base for the runtime register block */
> >>>> + sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4);
> >>>> + sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12);
> >>>> + /* turn on address decoding for this block */
> >>>> + sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN);
> >>>> +
> >>>> + /* exit configuration state */
> >>>> + outb(0xaa, port);
> >>>> +}
> >>>> +
> >>>> +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type)
> >>>> +{
> >>>> + int reg = GPIO0_DIR;
> >>>> +
> >>>> + if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
> >>>> + return;
> >>>> + if (gpio >= GPIO_NUM_PER_GROUP) {
> >>>> + reg = GPIO1_DIR;
> >>>> + gpio -= GPIO_NUM_PER_GROUP;
> >>>> + }
> >>>> +
> >>>> + /* enter configuration state */
> >>>> + outb(0x55, port);
> >>>> +
> >>>> + /* set gpio pin direction, polority and type */
> >>>> + sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio);
> >>>> + sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio);
> >>>> + sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio);
> >>>> +
> >>>> + /* exit configuration state */
> >>>> + outb(0xaa, port);
> >>>> +}
> >>>> +
> >>>> +int sio1007_gpio_get_value(int port, int gpio)
> >>>> +{
> >>>> + int reg = GPIO0_DATA;
> >>>> + int val;
> >>>> +
> >>>> + if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
> >>>> + return -EINVAL;
> >>>> + if (gpio >= GPIO_NUM_PER_GROUP) {
> >>>> + reg = GPIO1_DATA;
> >>>> + gpio -= GPIO_NUM_PER_GROUP;
> >>>> + }
> >>>> +
> >>>> + val = inb(port + reg);
> >>>> + if (val & (1 << gpio))
> >>>> + return 1;
> >>>> + else
> >>>> + return 0;
> >>>> +}
> >>>> +
> >>>> +void sio1007_gpio_set_value(int port, int gpio, int val)
> >>>> +{
> >>>> + int reg = GPIO0_DATA;
> >>>> + u8 data;
> >>>> +
> >>>> + if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
> >>>> + return;
> >>>> + if (gpio >= GPIO_NUM_PER_GROUP) {
> >>>> + reg = GPIO1_DATA;
> >>>> + gpio -= GPIO_NUM_PER_GROUP;
> >>>> + }
> >>>> +
> >>>> + data = inb(port + reg);
> >>>> + data &= ~(1 << gpio);
> >>>> + data |= (val << gpio);
> >>>> + outb(data, port + reg);
> >>>> +}
> >>>
> >>> This should be modeled as a GPIO driver in the GPIO uclass.
> >>>
> >>>> diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h
> >>>> new file mode 100644
> >>>> index 0000000..eff57a7
> >>>> --- /dev/null
> >>>> +++ b/include/smsc_sio1007.h
> >>>> @@ -0,0 +1,115 @@
> >>>> +/*
> >>>> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
> >>>> + *
> >>>> + * SPDX-License-Identifier: GPL-2.0+
> >>>> + */
> >>>> +
> >>>> +#ifndef _SMSC_SIO1007_H_
> >>>> +#define _SMSC_SIO1007_H_
> >>>> +
> >>>> +/*
> >>>> + * The I/O base address of SIO1007 at power-up is determined by the SYSOPT0
> >>>> + * and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of
> >>>> + * SYSOPT0 and SYSOPT1 determines one of the following addresses.
> >>>> + */
> >>>> +#define SIO1007_IOPORT0 0x002e
> >>>> +#define SIO1007_IOPORT1 0x004e
> >>>> +#define SIO1007_IOPORT2 0x162e
> >>>> +#define SIO1007_IOPORT3 0x164e
> >>>> +
> >>>> +/* SIO1007 registers */
> >>>> +
> >>>> +#define DEV_POWER_CTRL 0x02
> >>>> +#define UART1_POWER_ON (1 << 3)
> >>>> +#define UART2_POWER_ON (1 << 7)
> >>>> +
> >>>> +#define UART1_IOBASE 0x24
> >>>> +#define UART2_IOBASE 0x25
> >>>> +#define UART_IRQ 0x28
> >>>> +
> >>>> +#define RTR_IOBASE_HIGH 0x21
> >>>> +#define RTR_IOBASE_LOW 0x30
> >>>> +
> >>>> +#define GPIO0_DIR 0x31
> >>>> +#define GPIO1_DIR 0x35
> >>>> +#define GPIO_DIR_INPUT 0
> >>>> +#define GPIO_DIR_OUTPUT 1
> >>>> +
> >>>> +#define GPIO0_POL 0x32
> >>>> +#define GPIO1_POL 0x36
> >>>> +#define GPIO_POL_NO_INVERT 0
> >>>> +#define GPIO_POL_INVERT 1
> >>>> +
> >>>> +#define GPIO0_TYPE 0x33
> >>>> +#define GPIO1_TYPE 0x37
> >>>> +#define GPIO_TYPE_PUSH_PULL 0
> >>>> +#define GPIO_TYPE_OPEN_DRAIN 1
> >>>> +
> >>>> +#define DEV_ACTIVATE 0x3a
> >>>> +#define RTR_EN (1 << 1)
> >>>> +
> >>>> +/* Runtime register offset */
> >>>> +
> >>>> +#define GPIO0_DATA 0xc
> >>>> +#define GPIO1_DATA 0xe
> >>>> +
> >>>> +/* Number of serial ports supported */
> >>>> +#define SIO1007_UART_NUM 2
> >>>> +
> >>>> +/* Number of gpio pins supported */
> >>>> +#define GPIO_NUM_PER_GROUP 8
> >>>> +#define GPIO_GROUP_NUM 2
> >>>> +#define SIO1007_GPIO_NUM (GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM)
> >>>> +
> >>>> +/**
> >>>> + * Configure the I/O port address of the specified serial device and
> >>>> + * enable the serial device.
> >>>> + *
> >>>> + * @port: SIO1007 I/O port address
> >>>> + * @num: serial device number (0 or 1)
> >>>> + * @iobase: processor I/O port address to assign to this serial device
> >>>> + * @irq: processor IRQ number to assign to this serial device
> >>>> + */
> >>>> +void sio1007_enable_serial(int port, int num, int iobase, int irq);
> >>>
> >>> I wonder if we need a parent device which provides access to these
> >>> features, and then a GPIO child device?
> >>
> >> I was thinking we create a superio uclass for this, but I found it's
> >> not generic enough to abstract the ops for this uclass, if we take a
> >> look at the existing SMSC LPC47M and this new one. Given these
> >> routines will only need to be called just once during boot up, I
> >> decided not to use driver model on this type of device.
> >>
> >
> > But won't we want to use the 'gpio' command to access these GPIOs?
> >
>
> I don't see value of accessing them after boot. Also as you can see,
> these superio chipsets are really not good candidates to model. To
> operate on a specific GPIO pin, we need access two IO ports which
> looks quite weird, but unfortunately that is how the chipset was
> designed :(
I'm not sure why the access method matters, and I don't understand why
a GPIO would only be used on boot. But clearly you do, so I'm OK with
it.
>
> [snip]
>
> Regards,
> Bin
Regards,
Simon
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 06/10] x86: ivybridge: Do not require HAVE_INTEL_ME
2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
` (4 preceding siblings ...)
2015-12-11 10:55 ` [U-Boot] [PATCH 05/10] superio: Add SMSC SIO1007 driver Bin Meng
@ 2015-12-11 10:55 ` Bin Meng
2015-12-19 2:52 ` Simon Glass
2015-12-11 10:55 ` [U-Boot] [PATCH 07/10] x86: fsp: Make sure HOB list is not overwritten by U-Boot Bin Meng
` (3 subsequent siblings)
9 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
To: u-boot
Do not set HAVE_INTEL_ME by default as for some cases Intel ME
firmware even does not reside on the same SPI flash as U-Boot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/x86/cpu/ivybridge/Kconfig | 1 -
board/google/chromebook_link/Kconfig | 1 +
board/google/chromebox_panther/Kconfig | 1 +
3 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
index 36b74c2..b9f290a 100644
--- a/arch/x86/cpu/ivybridge/Kconfig
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -48,7 +48,6 @@ config DCACHE_RAM_MRC_VAR_SIZE
config CPU_SPECIFIC_OPTIONS
def_bool y
select SMM_TSEG
- select HAVE_INTEL_ME
select X86_RAMTEST
config SMM_TSEG_SIZE
diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
index 6b13939..fa12f33 100644
--- a/board/google/chromebook_link/Kconfig
+++ b/board/google/chromebook_link/Kconfig
@@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select X86_RESET_VECTOR
select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select HAVE_INTEL_ME
select BOARD_ROMSIZE_KB_8192
config PCIE_ECAM_BASE
diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig
index ae96d23..2af3aa9 100644
--- a/board/google/chromebox_panther/Kconfig
+++ b/board/google/chromebox_panther/Kconfig
@@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select X86_RESET_VECTOR
select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select HAVE_INTEL_ME
select BOARD_ROMSIZE_KB_8192
config SYS_CAR_ADDR
--
1.8.2.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 06/10] x86: ivybridge: Do not require HAVE_INTEL_ME
2015-12-11 10:55 ` [U-Boot] [PATCH 06/10] x86: ivybridge: Do not require HAVE_INTEL_ME Bin Meng
@ 2015-12-19 2:52 ` Simon Glass
2015-12-21 7:50 ` Bin Meng
0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2015-12-19 2:52 UTC (permalink / raw)
To: u-boot
On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> Do not set HAVE_INTEL_ME by default as for some cases Intel ME
> firmware even does not reside on the same SPI flash as U-Boot.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> arch/x86/cpu/ivybridge/Kconfig | 1 -
> board/google/chromebook_link/Kconfig | 1 +
> board/google/chromebox_panther/Kconfig | 1 +
> 3 files changed, 2 insertions(+), 1 deletion(-)
Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 06/10] x86: ivybridge: Do not require HAVE_INTEL_ME
2015-12-19 2:52 ` Simon Glass
@ 2015-12-21 7:50 ` Bin Meng
0 siblings, 0 replies; 39+ messages in thread
From: Bin Meng @ 2015-12-21 7:50 UTC (permalink / raw)
To: u-boot
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Do not set HAVE_INTEL_ME by default as for some cases Intel ME
>> firmware even does not reside on the same SPI flash as U-Boot.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>> arch/x86/cpu/ivybridge/Kconfig | 1 -
>> board/google/chromebook_link/Kconfig | 1 +
>> board/google/chromebox_panther/Kconfig | 1 +
>> 3 files changed, 2 insertions(+), 1 deletion(-)
>
> Acked-by: Simon Glass <sjg@chromium.org>
> Tested on link (ivybridge non-FSP)
> Tested-by: Simon Glass <sjg@chromium.org>
applied to u-boot-x86/next, thanks!
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 07/10] x86: fsp: Make sure HOB list is not overwritten by U-Boot
2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
` (5 preceding siblings ...)
2015-12-11 10:55 ` [U-Boot] [PATCH 06/10] x86: ivybridge: Do not require HAVE_INTEL_ME Bin Meng
@ 2015-12-11 10:55 ` Bin Meng
2015-12-19 2:52 ` Simon Glass
2015-12-11 10:55 ` [U-Boot] [PATCH 08/10] x86: fsp: Always use hex numbers in the hob command output Bin Meng
` (2 subsequent siblings)
9 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
To: u-boot
Intel IvyBridge FSP seems to be buggy that it does not report memory
used by FSP itself as reserved in the resource descriptor HOB. The
FSP specification does not describe how resource descriptor HOBs are
generated by the FSP to describe what memory regions. It looks newer
FSPs like Queensbay and BayTrail do not have such issue. This causes
U-Boot relocation overwrites the important boot service data which is
used by FSP, and the subsequent call to fsp_notify() will fail.
To resolve this, we find out the lowest memory base address allocated
by FSP for the boot service data when walking through the HOB list in
fsp_get_usable_lowmem_top(). Check whether the memory top address is
below the FSP HOB list, and if not, use the lowest memory base address
allocated by FSP as the memory top address.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/x86/lib/fsp/fsp_support.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
index 875c96a..d6bbe1a 100644
--- a/arch/x86/lib/fsp/fsp_support.c
+++ b/arch/x86/lib/fsp/fsp_support.c
@@ -223,7 +223,9 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list)
{
const struct hob_header *hdr;
struct hob_res_desc *res_desc;
+ struct hob_mem_alloc *res_mem;
phys_addr_t phys_start;
+ phys_addr_t mem_base = 0;
u32 top;
/* Get the HOB list for processing */
@@ -242,9 +244,34 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list)
top += (u32)(res_desc->len);
}
}
+
+ /*
+ * Find out the lowest memory base address allocated by FSP
+ * for the boot service data
+ */
+ if (hdr->type == HOB_TYPE_MEM_ALLOC) {
+ res_mem = (struct hob_mem_alloc *)hdr;
+ if (!mem_base)
+ mem_base = res_mem->mem_base;
+ if (res_mem->mem_base < mem_base)
+ mem_base = res_mem->mem_base;
+ }
+
hdr = get_next_hob(hdr);
}
+ /*
+ * Check whether the memory top address is below the FSP HOB list.
+ * If not, use the lowest memory base address allocated by FSP as
+ * the memory top address. This is to prevent U-Boot relocation
+ * overwrites the important boot service data which is used by FSP,
+ * otherwise the subsequent call to fsp_notify() will fail.
+ */
+ if (top > (u32)hob_list) {
+ debug("Adjust memory top address due to a buggy FSP\n");
+ top = (u32)mem_base;
+ }
+
return top;
}
--
1.8.2.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 07/10] x86: fsp: Make sure HOB list is not overwritten by U-Boot
2015-12-11 10:55 ` [U-Boot] [PATCH 07/10] x86: fsp: Make sure HOB list is not overwritten by U-Boot Bin Meng
@ 2015-12-19 2:52 ` Simon Glass
2015-12-21 2:36 ` Bin Meng
0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2015-12-19 2:52 UTC (permalink / raw)
To: u-boot
Hi Bin,
On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> Intel IvyBridge FSP seems to be buggy that it does not report memory
> used by FSP itself as reserved in the resource descriptor HOB. The
> FSP specification does not describe how resource descriptor HOBs are
> generated by the FSP to describe what memory regions. It looks newer
> FSPs like Queensbay and BayTrail do not have such issue. This causes
> U-Boot relocation overwrites the important boot service data which is
> used by FSP, and the subsequent call to fsp_notify() will fail.
>
> To resolve this, we find out the lowest memory base address allocated
> by FSP for the boot service data when walking through the HOB list in
> fsp_get_usable_lowmem_top(). Check whether the memory top address is
> below the FSP HOB list, and if not, use the lowest memory base address
> allocated by FSP as the memory top address.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> arch/x86/lib/fsp/fsp_support.c | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>
But if this is a bug I'd prefer to have it behind an #iffdef, or with
a large comment in the code. Otherwise we might think it is an
important feature for all platforms.
>
> diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
> index 875c96a..d6bbe1a 100644
> --- a/arch/x86/lib/fsp/fsp_support.c
> +++ b/arch/x86/lib/fsp/fsp_support.c
> @@ -223,7 +223,9 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list)
> {
> const struct hob_header *hdr;
> struct hob_res_desc *res_desc;
> + struct hob_mem_alloc *res_mem;
> phys_addr_t phys_start;
> + phys_addr_t mem_base = 0;
> u32 top;
>
> /* Get the HOB list for processing */
> @@ -242,9 +244,34 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list)
> top += (u32)(res_desc->len);
> }
> }
> +
> + /*
> + * Find out the lowest memory base address allocated by FSP
> + * for the boot service data
> + */
> + if (hdr->type == HOB_TYPE_MEM_ALLOC) {
> + res_mem = (struct hob_mem_alloc *)hdr;
> + if (!mem_base)
> + mem_base = res_mem->mem_base;
> + if (res_mem->mem_base < mem_base)
> + mem_base = res_mem->mem_base;
> + }
> +
> hdr = get_next_hob(hdr);
> }
>
> + /*
> + * Check whether the memory top address is below the FSP HOB list.
> + * If not, use the lowest memory base address allocated by FSP as
> + * the memory top address. This is to prevent U-Boot relocation
> + * overwrites the important boot service data which is used by FSP,
> + * otherwise the subsequent call to fsp_notify() will fail.
> + */
> + if (top > (u32)hob_list) {
> + debug("Adjust memory top address due to a buggy FSP\n");
> + top = (u32)mem_base;
> + }
> +
> return top;
> }
>
> --
> 1.8.2.1
>
Regards,
Simon
^ permalink raw reply [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 07/10] x86: fsp: Make sure HOB list is not overwritten by U-Boot
2015-12-19 2:52 ` Simon Glass
@ 2015-12-21 2:36 ` Bin Meng
0 siblings, 0 replies; 39+ messages in thread
From: Bin Meng @ 2015-12-21 2:36 UTC (permalink / raw)
To: u-boot
Hi Simon,
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Intel IvyBridge FSP seems to be buggy that it does not report memory
>> used by FSP itself as reserved in the resource descriptor HOB. The
>> FSP specification does not describe how resource descriptor HOBs are
>> generated by the FSP to describe what memory regions. It looks newer
>> FSPs like Queensbay and BayTrail do not have such issue. This causes
>> U-Boot relocation overwrites the important boot service data which is
>> used by FSP, and the subsequent call to fsp_notify() will fail.
>>
>> To resolve this, we find out the lowest memory base address allocated
>> by FSP for the boot service data when walking through the HOB list in
>> fsp_get_usable_lowmem_top(). Check whether the memory top address is
>> below the FSP HOB list, and if not, use the lowest memory base address
>> allocated by FSP as the memory top address.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>> arch/x86/lib/fsp/fsp_support.c | 27 +++++++++++++++++++++++++++
>> 1 file changed, 27 insertions(+)
>
> Acked-by: Simon Glass <sjg@chromium.org>
> Tested on link (ivybridge non-FSP)
> Tested-by: Simon Glass <sjg@chromium.org>
>
> But if this is a bug I'd prefer to have it behind an #iffdef, or with
> a large comment in the code. Otherwise we might think it is an
> important feature for all platforms.
>
Yep, will change to use #ifdef in v2.
Regards,
Bin
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 08/10] x86: fsp: Always use hex numbers in the hob command output
2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
` (6 preceding siblings ...)
2015-12-11 10:55 ` [U-Boot] [PATCH 07/10] x86: fsp: Make sure HOB list is not overwritten by U-Boot Bin Meng
@ 2015-12-11 10:55 ` Bin Meng
2015-12-19 2:52 ` Simon Glass
2015-12-11 10:55 ` [U-Boot] [PATCH 09/10] x86: ivybridge: Add macros for LPC decode ranges Bin Meng
2015-12-11 10:55 ` [U-Boot] [PATCH 10/10] x86: Add Intel Cougar Canyon 2 board Bin Meng
9 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
To: u-boot
In the 'fsp hob' command output, decimal numbers and hexadecimal
numbers are used mixedly. Now change to always use hex numbers
to keep consistency.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/x86/lib/fsp/cmd_fsp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/lib/fsp/cmd_fsp.c b/arch/x86/lib/fsp/cmd_fsp.c
index 4959edf..2554663 100644
--- a/arch/x86/lib/fsp/cmd_fsp.c
+++ b/arch/x86/lib/fsp/cmd_fsp.c
@@ -69,7 +69,7 @@ static int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
printf("---|----------|-----------|------|-");
printf("------------------------------------------\n");
while (!end_of_hob(hdr)) {
- printf("%-2d | %08x | ", i, (unsigned int)hdr);
+ printf("%02x | %08x | ", i, (unsigned int)hdr);
type = hdr->type;
if (type == HOB_TYPE_UNUSED)
desc = "*Unused*";
@@ -79,7 +79,7 @@ static int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
desc = hob_type[type];
else
desc = "*Invalid*";
- printf("%-9s | %-4d | ", desc, hdr->len);
+ printf("%-9s | %04x | ", desc, hdr->len);
if (type == HOB_TYPE_MEM_ALLOC || type == HOB_TYPE_RES_DESC ||
type == HOB_TYPE_GUID_EXT) {
--
1.8.2.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 08/10] x86: fsp: Always use hex numbers in the hob command output
2015-12-11 10:55 ` [U-Boot] [PATCH 08/10] x86: fsp: Always use hex numbers in the hob command output Bin Meng
@ 2015-12-19 2:52 ` Simon Glass
2015-12-21 7:50 ` Bin Meng
0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2015-12-19 2:52 UTC (permalink / raw)
To: u-boot
On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> In the 'fsp hob' command output, decimal numbers and hexadecimal
> numbers are used mixedly. Now change to always use hex numbers
> to keep consistency.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> arch/x86/lib/fsp/cmd_fsp.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Acked-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 08/10] x86: fsp: Always use hex numbers in the hob command output
2015-12-19 2:52 ` Simon Glass
@ 2015-12-21 7:50 ` Bin Meng
0 siblings, 0 replies; 39+ messages in thread
From: Bin Meng @ 2015-12-21 7:50 UTC (permalink / raw)
To: u-boot
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> In the 'fsp hob' command output, decimal numbers and hexadecimal
>> numbers are used mixedly. Now change to always use hex numbers
>> to keep consistency.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>> arch/x86/lib/fsp/cmd_fsp.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> Acked-by: Simon Glass <sjg@chromium.org>
applied to u-boot-x86/next, thanks!
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 09/10] x86: ivybridge: Add macros for LPC decode ranges
2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
` (7 preceding siblings ...)
2015-12-11 10:55 ` [U-Boot] [PATCH 08/10] x86: fsp: Always use hex numbers in the hob command output Bin Meng
@ 2015-12-11 10:55 ` Bin Meng
2015-12-19 2:52 ` Simon Glass
2015-12-11 10:55 ` [U-Boot] [PATCH 10/10] x86: Add Intel Cougar Canyon 2 board Bin Meng
9 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
To: u-boot
Add several macros for LPC decode registers on PCH.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/x86/include/asm/arch-ivybridge/pch.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
index 21df083..31437c8 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -105,6 +105,8 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
#define GPIO_ROUT 0xb8
#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
+#define COMB_DEC_RANGE (1 << 4) /* 0x2f8-0x2ff (COM2) */
+#define COMA_DEC_RANGE (0 << 0) /* 0x3f8-0x3ff (COM1) */
#define LPC_EN 0x82 /* LPC IF Enables Register */
#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
@@ -121,6 +123,14 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
#define LPC_GENX_DEC(x) (0x84 + 4 * (x))
+#define GEN_DEC_RANGE_256B 0xfc0000 /* 256 Bytes */
+#define GEN_DEC_RANGE_128B 0x7c0000 /* 128 Bytes */
+#define GEN_DEC_RANGE_64B 0x3c0000 /* 64 Bytes */
+#define GEN_DEC_RANGE_32B 0x1c0000 /* 32 Bytes */
+#define GEN_DEC_RANGE_16B 0x0c0000 /* 16 Bytes */
+#define GEN_DEC_RANGE_8B 0x040000 /* 8 Bytes */
+#define GEN_DEC_RANGE_4B 0x000000 /* 4 Bytes */
+#define GEN_DEC_RANGE_EN (1 << 0) /* Range Enable */
/* PCI Configuration Space (D31:F1): IDE */
#define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1)
--
1.8.2.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 09/10] x86: ivybridge: Add macros for LPC decode ranges
2015-12-11 10:55 ` [U-Boot] [PATCH 09/10] x86: ivybridge: Add macros for LPC decode ranges Bin Meng
@ 2015-12-19 2:52 ` Simon Glass
2015-12-21 7:50 ` Bin Meng
0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2015-12-19 2:52 UTC (permalink / raw)
To: u-boot
On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> Add several macros for LPC decode registers on PCH.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> arch/x86/include/asm/arch-ivybridge/pch.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 09/10] x86: ivybridge: Add macros for LPC decode ranges
2015-12-19 2:52 ` Simon Glass
@ 2015-12-21 7:50 ` Bin Meng
0 siblings, 0 replies; 39+ messages in thread
From: Bin Meng @ 2015-12-21 7:50 UTC (permalink / raw)
To: u-boot
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Add several macros for LPC decode registers on PCH.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>> arch/x86/include/asm/arch-ivybridge/pch.h | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>
> Acked-by: Simon Glass <sjg@chromium.org>
> Tested on link (ivybridge non-FSP)
> Tested-by: Simon Glass <sjg@chromium.org>
applied to u-boot-x86/next, thanks!
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 10/10] x86: Add Intel Cougar Canyon 2 board
2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
` (8 preceding siblings ...)
2015-12-11 10:55 ` [U-Boot] [PATCH 09/10] x86: ivybridge: Add macros for LPC decode ranges Bin Meng
@ 2015-12-11 10:55 ` Bin Meng
2015-12-19 2:52 ` Simon Glass
9 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
To: u-boot
This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/x86/dts/Makefile | 1 +
arch/x86/dts/cougarcanyon2.dts | 96 +++++++++++++++++++++++++++++++
board/intel/Kconfig | 9 +++
board/intel/cougarcanyon2/Kconfig | 25 ++++++++
board/intel/cougarcanyon2/MAINTAINERS | 6 ++
board/intel/cougarcanyon2/Makefile | 7 +++
board/intel/cougarcanyon2/cougarcanyon2.c | 48 ++++++++++++++++
board/intel/cougarcanyon2/start.S | 9 +++
configs/cougarcanyon2_defconfig | 21 +++++++
include/configs/cougarcanyon2.h | 34 +++++++++++
10 files changed, 256 insertions(+)
create mode 100644 arch/x86/dts/cougarcanyon2.dts
create mode 100644 board/intel/cougarcanyon2/Kconfig
create mode 100644 board/intel/cougarcanyon2/MAINTAINERS
create mode 100644 board/intel/cougarcanyon2/Makefile
create mode 100644 board/intel/cougarcanyon2/cougarcanyon2.c
create mode 100644 board/intel/cougarcanyon2/start.S
create mode 100644 configs/cougarcanyon2_defconfig
create mode 100644 include/configs/cougarcanyon2.h
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 64e5694..84feb19 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -5,6 +5,7 @@
dtb-y += bayleybay.dtb \
chromebook_link.dtb \
chromebox_panther.dtb \
+ cougarcanyon2.dtb \
crownbay.dtb \
efi.dtb \
galileo.dtb \
diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts
new file mode 100644
index 0000000..486999e
--- /dev/null
+++ b/arch/x86/dts/cougarcanyon2.dts
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+/include/ "keyboard.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+ model = "Intel Cougar Canyon 2";
+ compatible = "intel,cougarcanyon2", "intel,chiefriver";
+
+ aliases {
+ spi0 = "/spi";
+ };
+
+ config {
+ silent_console = <0>;
+ };
+
+ chosen {
+ stdout-path = "/serial";
+ };
+
+ microcode {
+ update at 0 {
+#include "microcode/m12306a2_00000008.dtsi"
+ };
+ update at 1 {
+#include "microcode/m12306a4_00000007.dtsi"
+ };
+ update at 2 {
+#include "microcode/m12306a5_00000007.dtsi"
+ };
+ update at 3 {
+#include "microcode/m12306a8_00000010.dtsi"
+ };
+ update at 4 {
+#include "microcode/m12306a9_0000001b.dtsi"
+ };
+ };
+
+ fsp {
+ compatible = "intel,ivybridge-fsp";
+ fsp,enable-ht;
+ };
+
+ pci {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ compatible = "pci-x86";
+ u-boot,dm-pre-reloc;
+ ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
+ 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
+ 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+ };
+
+ gpioa {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0 0x10>;
+ bank-name = "A";
+ };
+
+ gpiob {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x30 0x10>;
+ bank-name = "B";
+ };
+
+ gpioc {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x40 0x10>;
+ bank-name = "C";
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash at 0 {
+ reg = <0>;
+ compatible = "winbond,w25q64bv", "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ };
+ };
+
+};
diff --git a/board/intel/Kconfig b/board/intel/Kconfig
index f7d71c3..4d341aa 100644
--- a/board/intel/Kconfig
+++ b/board/intel/Kconfig
@@ -18,6 +18,14 @@ config TARGET_BAYLEYBAY
4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC,
PCIe and some other sensor interfaces.
+config TARGET_COUGARCANYON2
+ bool "Cougar Canyon 2"
+ help
+ This is the Intel Cougar Canyon 2 Customer Reference Board. It
+ is built on the Chief River platform with Intel Ivybridge Processor
+ and Panther Point chipset. The board has 4GB RAM, with some other
+ peripheral connectors for PCIe/SATA/USB2/USB3/LAN/UART/PS2/VGA/HDMI.
+
config TARGET_CROWNBAY
bool "Crown Bay"
help
@@ -54,6 +62,7 @@ config TARGET_MINNOWMAX
endchoice
source "board/intel/bayleybay/Kconfig"
+source "board/intel/cougarcanyon2/Kconfig"
source "board/intel/crownbay/Kconfig"
source "board/intel/galileo/Kconfig"
source "board/intel/minnowmax/Kconfig"
diff --git a/board/intel/cougarcanyon2/Kconfig b/board/intel/cougarcanyon2/Kconfig
new file mode 100644
index 0000000..95a617b
--- /dev/null
+++ b/board/intel/cougarcanyon2/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_COUGARCANYON2
+
+config SYS_BOARD
+ default "cougarcanyon2"
+
+config SYS_VENDOR
+ default "intel"
+
+config SYS_SOC
+ default "ivybridge"
+
+config SYS_CONFIG_NAME
+ default "cougarcanyon2"
+
+config SYS_TEXT_BASE
+ default 0xffe00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select X86_RESET_VECTOR
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select HAVE_FSP
+ select BOARD_ROMSIZE_KB_2048
+
+endif
diff --git a/board/intel/cougarcanyon2/MAINTAINERS b/board/intel/cougarcanyon2/MAINTAINERS
new file mode 100644
index 0000000..a486739
--- /dev/null
+++ b/board/intel/cougarcanyon2/MAINTAINERS
@@ -0,0 +1,6 @@
+INTEL COUGAR CANYON 2 BOARD
+M: Bin Meng <bmeng.cn@gmail.com>
+S: Maintained
+F: board/intel/cougarcanyon2/
+F: include/configs/cougarcanyon2.h
+F: configs/cougarcanyon2_defconfig
diff --git a/board/intel/cougarcanyon2/Makefile b/board/intel/cougarcanyon2/Makefile
new file mode 100644
index 0000000..807f284
--- /dev/null
+++ b/board/intel/cougarcanyon2/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cougarcanyon2.o start.o
diff --git a/board/intel/cougarcanyon2/cougarcanyon2.c b/board/intel/cougarcanyon2/cougarcanyon2.c
new file mode 100644
index 0000000..4cc47fb
--- /dev/null
+++ b/board/intel/cougarcanyon2/cougarcanyon2.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ibmpc.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+#include <pci.h>
+#include <smsc_sio1007.h>
+
+#define SIO1007_RUNTIME_IOPORT 0x180
+
+int board_early_init_f(void)
+{
+ /* Initialize LPC interface to turn on superio chipset decode range */
+ x86_pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC,
+ COMA_DEC_RANGE | COMB_DEC_RANGE);
+ x86_pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | COMA_LPC_EN);
+ x86_pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, GEN_DEC_RANGE_256B |
+ (SIO1007_IOPORT3 & 0xff00) | GEN_DEC_RANGE_EN);
+ x86_pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, GEN_DEC_RANGE_16B |
+ SIO1007_RUNTIME_IOPORT | GEN_DEC_RANGE_EN);
+
+ /* Enable legacy serial port at 0x3f8 */
+ sio1007_enable_serial(SIO1007_IOPORT3, 0, UART0_BASE, UART0_IRQ);
+
+ /* Enable SIO1007 runtime I/O port at 0x180 */
+ sio1007_enable_runtime(SIO1007_IOPORT3, SIO1007_RUNTIME_IOPORT);
+
+ /*
+ * On Cougar Canyon 2 board, the RS232 transiver connected to serial
+ * port 0 (0x3f8) is controlled by a GPIO pin (GPIO10) on the SIO1007.
+ * Set the pin value to 1 to enable the RS232 transiver.
+ */
+ sio1007_gpio_config(SIO1007_IOPORT3, 0, GPIO_DIR_OUTPUT,
+ GPIO_POL_NO_INVERT, GPIO_TYPE_PUSH_PULL);
+ sio1007_gpio_set_value(SIO1007_RUNTIME_IOPORT, 0, 1);
+
+ return 0;
+}
+
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
+{
+ return;
+}
diff --git a/board/intel/cougarcanyon2/start.S b/board/intel/cougarcanyon2/start.S
new file mode 100644
index 0000000..a71db69
--- /dev/null
+++ b/board/intel/cougarcanyon2/start.S
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+ jmp early_board_init_ret
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
new file mode 100644
index 0000000..2d23dc3
--- /dev/null
+++ b/configs/cougarcanyon2_defconfig
@@ -0,0 +1,21 @@
+CONFIG_X86=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2"
+CONFIG_TARGET_COUGARCANYON2=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
+CONFIG_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_VSNPRINTF=y
diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h
new file mode 100644
index 0000000..faac552
--- /dev/null
+++ b/include/configs/cougarcanyon2.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN (2 << 20)
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SMSC_SIO1007
+
+#define CONFIG_PCI_PNP
+
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
+ "stdout=serial,vga\0" \
+ "stderr=serial,vga\0"
+
+#define CONFIG_SCSI_DEV_LIST \
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
+
+/* Environment configuration */
+#define CONFIG_ENV_SECT_SIZE 0x1000
+#define CONFIG_ENV_OFFSET 0x5ff000
+
+/* Video is not supported for now */
+#undef CONFIG_VIDEO
+#undef CONFIG_CFB_CONSOLE
+
+#endif /* __CONFIG_H */
--
1.8.2.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [U-Boot] [PATCH 10/10] x86: Add Intel Cougar Canyon 2 board
2015-12-11 10:55 ` [U-Boot] [PATCH 10/10] x86: Add Intel Cougar Canyon 2 board Bin Meng
@ 2015-12-19 2:52 ` Simon Glass
2015-12-21 2:34 ` Bin Meng
0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2015-12-19 2:52 UTC (permalink / raw)
To: u-boot
Hi Bin,
On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> This adds basic support to Intel Cougar Canyon 2 board, a board
> based on Chief River platform with an Ivy Bridge processor and
> a Panther Point chipset.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
>
> arch/x86/dts/Makefile | 1 +
> arch/x86/dts/cougarcanyon2.dts | 96 +++++++++++++++++++++++++++++++
> board/intel/Kconfig | 9 +++
> board/intel/cougarcanyon2/Kconfig | 25 ++++++++
> board/intel/cougarcanyon2/MAINTAINERS | 6 ++
> board/intel/cougarcanyon2/Makefile | 7 +++
> board/intel/cougarcanyon2/cougarcanyon2.c | 48 ++++++++++++++++
> board/intel/cougarcanyon2/start.S | 9 +++
> configs/cougarcanyon2_defconfig | 21 +++++++
> include/configs/cougarcanyon2.h | 34 +++++++++++
> 10 files changed, 256 insertions(+)
> create mode 100644 arch/x86/dts/cougarcanyon2.dts
> create mode 100644 board/intel/cougarcanyon2/Kconfig
> create mode 100644 board/intel/cougarcanyon2/MAINTAINERS
> create mode 100644 board/intel/cougarcanyon2/Makefile
> create mode 100644 board/intel/cougarcanyon2/cougarcanyon2.c
> create mode 100644 board/intel/cougarcanyon2/start.S
> create mode 100644 configs/cougarcanyon2_defconfig
> create mode 100644 include/configs/cougarcanyon2.h
Acked-by: Simon Glass <sjg@chromium.org>
A few nits though:
- Include order - <asm/... should go after the normal includes
- can we drop the calls to x86_pci_...? Please check it on top of the
u-boot-dm/pcif-working series
- Simon
^ permalink raw reply [flat|nested] 39+ messages in thread
* [U-Boot] [PATCH 10/10] x86: Add Intel Cougar Canyon 2 board
2015-12-19 2:52 ` Simon Glass
@ 2015-12-21 2:34 ` Bin Meng
0 siblings, 0 replies; 39+ messages in thread
From: Bin Meng @ 2015-12-21 2:34 UTC (permalink / raw)
To: u-boot
Hi Simon,
On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> This adds basic support to Intel Cougar Canyon 2 board, a board
>> based on Chief River platform with an Ivy Bridge processor and
>> a Panther Point chipset.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>
>> ---
>>
>> arch/x86/dts/Makefile | 1 +
>> arch/x86/dts/cougarcanyon2.dts | 96 +++++++++++++++++++++++++++++++
>> board/intel/Kconfig | 9 +++
>> board/intel/cougarcanyon2/Kconfig | 25 ++++++++
>> board/intel/cougarcanyon2/MAINTAINERS | 6 ++
>> board/intel/cougarcanyon2/Makefile | 7 +++
>> board/intel/cougarcanyon2/cougarcanyon2.c | 48 ++++++++++++++++
>> board/intel/cougarcanyon2/start.S | 9 +++
>> configs/cougarcanyon2_defconfig | 21 +++++++
>> include/configs/cougarcanyon2.h | 34 +++++++++++
>> 10 files changed, 256 insertions(+)
>> create mode 100644 arch/x86/dts/cougarcanyon2.dts
>> create mode 100644 board/intel/cougarcanyon2/Kconfig
>> create mode 100644 board/intel/cougarcanyon2/MAINTAINERS
>> create mode 100644 board/intel/cougarcanyon2/Makefile
>> create mode 100644 board/intel/cougarcanyon2/cougarcanyon2.c
>> create mode 100644 board/intel/cougarcanyon2/start.S
>> create mode 100644 configs/cougarcanyon2_defconfig
>> create mode 100644 include/configs/cougarcanyon2.h
>
> Acked-by: Simon Glass <sjg@chromium.org>
>
> A few nits though:
> - Include order - <asm/... should go after the normal includes
> - can we drop the calls to x86_pci_...? Please check it on top of the
> u-boot-dm/pcif-working series
>
Yep, I plan to do v2 after all your previous DM patches are applied.
Regards,
Bin
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