[Qemu-devel] [PATCH] PPC64: Add support for ldbrx and stdbrx instructions

[Qemu-devel] [PATCH] PPC64: Add support for ldbrx and stdbrx instructions

[David Gibson]

From: Thomas Huth <thuth@linux.vnet.ibm.com>

These instructions for loading and storing byte-swapped 64-bit values have
been introduced in PowerISA 2.06.

Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>
---
 target-ppc/translate.c |   30 ++++++++++++++++++++++++++++++
 1 files changed, 30 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index b2780db..bb06b2b 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2897,6 +2897,18 @@ static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
 }
 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
 
+#if defined(TARGET_PPC64)
+/* ldbrx */
+static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
+{
+    tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
+    if (likely(!ctx->le_mode)) {
+        tcg_gen_bswap64_tl(arg1, arg1);
+    }
+}
+GEN_LDX(ldbr, ld64ur, 0x14, 0x10, PPC_64B);
+#endif  /* TARGET_PPC64 */
+
 /* sthbrx */
 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
 {
@@ -2927,6 +2939,22 @@ static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
 }
 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
 
+#if defined(TARGET_PPC64)
+/* stdbrx */
+static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
+{
+    if (likely(!ctx->le_mode)) {
+        TCGv t0 = tcg_temp_new();
+        tcg_gen_bswap64_tl(t0, arg1);
+        tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
+        tcg_temp_free(t0);
+    } else {
+        tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
+    }
+}
+GEN_STX(stdbr, st64r, 0x14, 0x14, PPC_64B);
+#endif  /* TARGET_PPC64 */
+
 /***                    Integer load and store multiple                    ***/
 
 /* lmw */
@@ -8849,6 +8877,7 @@ GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
+GEN_LDX(ldbr, ld64ur, 0x14, 0x10, PPC_64B)
 #endif
 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
@@ -8878,6 +8907,7 @@ GEN_STS(stw, st32, 0x04, PPC_INTEGER)
 #if defined(TARGET_PPC64)
 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
+GEN_STX(stdbr, st64r, 0x14, 0x14, PPC_64B)
 #endif
 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
-- 
1.7.8.3

Re: [Qemu-devel] [PATCH] PPC64: Add support for ldbrx and stdbrx instructions

[malc]

On Wed, 8 Feb 2012, David Gibson wrote:

> From: Thomas Huth <thuth@linux.vnet.ibm.com>
> 
> These instructions for loading and storing byte-swapped 64-bit values have
> been introduced in PowerISA 2.06.
> 
> Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>
> ---
>  target-ppc/translate.c |   30 ++++++++++++++++++++++++++++++
>  1 files changed, 30 insertions(+), 0 deletions(-)

I seem to recall that POWER5 machine i had access to didn't have 
ld/stdbrx while CBE did have it (or was it the other way around?)
so question is - is PPC_64B sufficient?

[..snip..]

>  GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
>  GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
> @@ -8878,6 +8907,7 @@ GEN_STS(stw, st32, 0x04, PPC_INTEGER)
>  #if defined(TARGET_PPC64)
>  GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
>  GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
> +GEN_STX(stdbr, st64r, 0x14, 0x14, PPC_64B)
>  #endif
>  GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
>  GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
> 

-- 
mailto:av1474@comtv.ru

Re: [Qemu-devel] [Qemu-ppc] [PATCH] PPC64: Add support for ldbrx and stdbrx instructions

[David Gibson]

On Wed, Feb 08, 2012 at 10:54:21AM +0400, malc wrote:
> On Wed, 8 Feb 2012, David Gibson wrote:
> 
> > From: Thomas Huth <thuth@linux.vnet.ibm.com>
> > 
> > These instructions for loading and storing byte-swapped 64-bit values have
> > been introduced in PowerISA 2.06.
> > 
> > Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>
> > ---
> >  target-ppc/translate.c |   30 ++++++++++++++++++++++++++++++
> >  1 files changed, 30 insertions(+), 0 deletions(-)
> 
> I seem to recall that POWER5 machine i had access to didn't have 
> ld/stdbrx while CBE did have it (or was it the other way around?)
> so question is - is PPC_64B sufficient?

Ah, I think it's not.  I think I spotted that before, but then forgot
about it.  Thanks for the reminder.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Re: [Qemu-devel] [Qemu-ppc] [PATCH] PPC64: Add support for ldbrx and stdbrx instructions

[Thomas Huth]

Am Wed, 8 Feb 2012 21:48:40 +1100
schrieb David Gibson <david@gibson.dropbear.id.au>:

> On Wed, Feb 08, 2012 at 10:54:21AM +0400, malc wrote:
> > On Wed, 8 Feb 2012, David Gibson wrote:
> > 
> > > From: Thomas Huth <thuth@linux.vnet.ibm.com>
> > > 
> > > These instructions for loading and storing byte-swapped 64-bit values have
> > > been introduced in PowerISA 2.06.
> > > 
> > > Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>
> > > ---
> > >  target-ppc/translate.c |   30 ++++++++++++++++++++++++++++++
> > >  1 files changed, 30 insertions(+), 0 deletions(-)
> > 
> > I seem to recall that POWER5 machine i had access to didn't have 
> > ld/stdbrx while CBE did have it (or was it the other way around?)
> > so question is - is PPC_64B sufficient?
> 
> Ah, I think it's not.  I think I spotted that before, but then forgot
> about it.  Thanks for the reminder.

Maybe it's a better idea to use PPC_64BX here? ... but that flag seems
to be missing in POWERPC_INSNS_POWER7... David, could PPC_64BX also be
included in that flag list?

 Thomas

Re: [Qemu-devel] [Qemu-ppc] [PATCH] PPC64: Add support for ldbrx and stdbrx instructions

[David Gibson]

On Wed, Feb 08, 2012 at 02:27:35PM +0100, Thomas Huth wrote:
> Am Wed, 8 Feb 2012 21:48:40 +1100
> schrieb David Gibson <david@gibson.dropbear.id.au>:
> 
> > On Wed, Feb 08, 2012 at 10:54:21AM +0400, malc wrote:
> > > On Wed, 8 Feb 2012, David Gibson wrote:
> > > 
> > > > From: Thomas Huth <thuth@linux.vnet.ibm.com>
> > > > 
> > > > These instructions for loading and storing byte-swapped 64-bit values have
> > > > been introduced in PowerISA 2.06.
> > > > 
> > > > Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>
> > > > ---
> > > >  target-ppc/translate.c |   30 ++++++++++++++++++++++++++++++
> > > >  1 files changed, 30 insertions(+), 0 deletions(-)
> > > 
> > > I seem to recall that POWER5 machine i had access to didn't have 
> > > ld/stdbrx while CBE did have it (or was it the other way around?)
> > > so question is - is PPC_64B sufficient?
> > 
> > Ah, I think it's not.  I think I spotted that before, but then forgot
> > about it.  Thanks for the reminder.
> 
> Maybe it's a better idea to use PPC_64BX here? ... but that flag seems
> to be missing in POWERPC_INSNS_POWER7... David, could PPC_64BX also be
> included in that flag list?

Um.. what exactly do you mean by 64BX?

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Re: [Qemu-devel] [Qemu-ppc] [PATCH] PPC64: Add support for ldbrx and stdbrx instructions

[Thomas Huth]

Am Thu, 9 Feb 2012 11:26:09 +1100
schrieb David Gibson <dwg@au1.ibm.com>:

> On Wed, Feb 08, 2012 at 02:27:35PM +0100, Thomas Huth wrote:
> > Am Wed, 8 Feb 2012 21:48:40 +1100
> > schrieb David Gibson <david@gibson.dropbear.id.au>:
> > 
> > > On Wed, Feb 08, 2012 at 10:54:21AM +0400, malc wrote:
> > > > On Wed, 8 Feb 2012, David Gibson wrote:
> > > > 
> > > > > From: Thomas Huth <thuth@linux.vnet.ibm.com>
> > > > > 
> > > > > These instructions for loading and storing byte-swapped 64-bit values have
> > > > > been introduced in PowerISA 2.06.
> > > > > 
> > > > > Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>
> > > > > ---
> > > > >  target-ppc/translate.c |   30 ++++++++++++++++++++++++++++++
> > > > >  1 files changed, 30 insertions(+), 0 deletions(-)
> > > > 
> > > > I seem to recall that POWER5 machine i had access to didn't have 
> > > > ld/stdbrx while CBE did have it (or was it the other way around?)
> > > > so question is - is PPC_64B sufficient?
> > > 
> > > Ah, I think it's not.  I think I spotted that before, but then forgot
> > > about it.  Thanks for the reminder.
> > 
> > Maybe it's a better idea to use PPC_64BX here? ... but that flag seems
> > to be missing in POWERPC_INSNS_POWER7... David, could PPC_64BX also be
> > included in that flag list?
> 
> Um.. what exactly do you mean by 64BX?
> 

There is a definition in target-ppc/cpu.h:

    /*   New 64 bits extensions (PowerPC 2.0x)     */
    PPC_64BX           = 0x0000000000000040ULL,

According to the comment, I thought the PPC_64BX might be designed
for new 64-bit instructions?

 Thomas

Re: [Qemu-devel] [Qemu-ppc] [PATCH] PPC64: Add support for ldbrx and stdbrx instructions

[Alexander Graf]

On 09.02.2012, at 08:43, Thomas Huth wrote:

> Am Thu, 9 Feb 2012 11:26:09 +1100
> schrieb David Gibson <dwg@au1.ibm.com>:
> 
>> On Wed, Feb 08, 2012 at 02:27:35PM +0100, Thomas Huth wrote:
>>> Am Wed, 8 Feb 2012 21:48:40 +1100
>>> schrieb David Gibson <david@gibson.dropbear.id.au>:
>>> 
>>>> On Wed, Feb 08, 2012 at 10:54:21AM +0400, malc wrote:
>>>>> On Wed, 8 Feb 2012, David Gibson wrote:
>>>>> 
>>>>>> From: Thomas Huth <thuth@linux.vnet.ibm.com>
>>>>>> 
>>>>>> These instructions for loading and storing byte-swapped 64-bit values have
>>>>>> been introduced in PowerISA 2.06.
>>>>>> 
>>>>>> Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>
>>>>>> ---
>>>>>> target-ppc/translate.c |   30 ++++++++++++++++++++++++++++++
>>>>>> 1 files changed, 30 insertions(+), 0 deletions(-)
>>>>> 
>>>>> I seem to recall that POWER5 machine i had access to didn't have 
>>>>> ld/stdbrx while CBE did have it (or was it the other way around?)
>>>>> so question is - is PPC_64B sufficient?
>>>> 
>>>> Ah, I think it's not.  I think I spotted that before, but then forgot
>>>> about it.  Thanks for the reminder.
>>> 
>>> Maybe it's a better idea to use PPC_64BX here? ... but that flag seems
>>> to be missing in POWERPC_INSNS_POWER7... David, could PPC_64BX also be
>>> included in that flag list?
>> 
>> Um.. what exactly do you mean by 64BX?
>> 
> 
> There is a definition in target-ppc/cpu.h:
> 
>    /*   New 64 bits extensions (PowerPC 2.0x)     */
>    PPC_64BX           = 0x0000000000000040ULL,
> 
> According to the comment, I thought the PPC_64BX might be designed
> for new 64-bit instructions?

Well, we need to be a bit more specific here to know what we're implementing. The flag above just indicates the lq opcode:

  target-ppc/translate.c:GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),

So how about we create a new PPC2 flag for BRX and add that in POWER7 INSNS? If you could find out if Cell also supports these instructions, that'd be great. I don't have a 2.05 spec handy and 2.04 doesn't implement it yet.


Alex

[Qemu-devel] [PATCH] PPC64: Add support for ldbrx and stdbrx instructions

[David Gibson]

From: Thomas Huth <thuth@linux.vnet.ibm.com>

These instructions for loading and storing byte-swapped 64-bit values have
been introduced in PowerISA 2.06.

Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 target-ppc/cpu.h            |    4 ++-
 target-ppc/translate.c      |   52 +++++++++++++++++++++++++++++++++++-------
 target-ppc/translate_init.c |    2 +-
 3 files changed, 47 insertions(+), 11 deletions(-)

Alex, resending with the type updated as requested.  Please review to
make sure I haven't messed anything up in extending the GEN_LDX and
GEN_STX macros to take the type2 field.

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index fbcf488..036b3b6 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1918,8 +1918,10 @@ enum {
     PPC2_DFP           = 0x0000000000000004ULL,
     /* Embedded.Processor Control                                            */
     PPC2_PRCNTL        = 0x0000000000000008ULL,
+    /* Byte-reversed, indexed, double-word load and store                    */
+    PPC2_DBRX          = 0x0000000000000010ULL,
 
-#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL)
+#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX)
 };
 
 /*****************************************************************************/
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index b2780db..2728941 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2656,7 +2656,7 @@ static void glue(gen_, name##ux)(DisasContext *ctx)
     tcg_temp_free(EA);                                                        \
 }
 
-#define GEN_LDX(name, ldop, opc2, opc3, type)                                 \
+#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2)                        \
 static void glue(gen_, name##x)(DisasContext *ctx)                            \
 {                                                                             \
     TCGv EA;                                                                  \
@@ -2666,6 +2666,8 @@ static void glue(gen_, name##x)(DisasContext *ctx)                            \
     gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
     tcg_temp_free(EA);                                                        \
 }
+#define GEN_LDX(name, ldop, opc2, opc3, type)                                 \
+    GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
 
 #define GEN_LDS(name, ldop, op, type)                                         \
 GEN_LD(name, ldop, op | 0x20, type);                                          \
@@ -2799,8 +2801,8 @@ static void glue(gen_, name##ux)(DisasContext *ctx)
     tcg_temp_free(EA);                                                        \
 }
 
-#define GEN_STX(name, stop, opc2, opc3, type)                                 \
-static void glue(gen_, name##x)(DisasContext *ctx)                                    \
+#define GEN_STX_E(name, stop, opc2, opc3, type, type2)                        \
+static void glue(gen_, name##x)(DisasContext *ctx)                            \
 {                                                                             \
     TCGv EA;                                                                  \
     gen_set_access_type(ctx, ACCESS_INT);                                     \
@@ -2809,6 +2811,8 @@ static void glue(gen_, name##x)(DisasContext *ctx)
     gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
     tcg_temp_free(EA);                                                        \
 }
+#define GEN_STX(name, stop, opc2, opc3, type)                                 \
+    GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
 
 #define GEN_STS(name, stop, op, type)                                         \
 GEN_ST(name, stop, op | 0x20, type);                                          \
@@ -2897,6 +2901,18 @@ static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
 }
 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
 
+#if defined(TARGET_PPC64)
+/* ldbrx */
+static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
+{
+    tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
+    if (likely(!ctx->le_mode)) {
+        tcg_gen_bswap64_tl(arg1, arg1);
+    }
+}
+GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
+#endif  /* TARGET_PPC64 */
+
 /* sthbrx */
 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
 {
@@ -2927,6 +2943,22 @@ static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
 }
 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
 
+#if defined(TARGET_PPC64)
+/* stdbrx */
+static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
+{
+    if (likely(!ctx->le_mode)) {
+        TCGv t0 = tcg_temp_new();
+        tcg_gen_bswap64_tl(t0, arg1);
+        tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
+        tcg_temp_free(t0);
+    } else {
+        tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
+    }
+}
+GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
+#endif  /* TARGET_PPC64 */
+
 /***                    Integer load and store multiple                    ***/
 
 /* lmw */
@@ -8824,7 +8856,7 @@ GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
 #undef GEN_LD
 #undef GEN_LDU
 #undef GEN_LDUX
-#undef GEN_LDX
+#undef GEN_LDX_E
 #undef GEN_LDS
 #define GEN_LD(name, ldop, opc, type)                                         \
 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
@@ -8832,8 +8864,8 @@ GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
 #define GEN_LDUX(name, ldop, opc2, opc3, type)                                \
 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
-#define GEN_LDX(name, ldop, opc2, opc3, type)                                 \
-GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
+#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2)                        \
+GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
 #define GEN_LDS(name, ldop, op, type)                                         \
 GEN_LD(name, ldop, op | 0x20, type)                                           \
 GEN_LDU(name, ldop, op | 0x21, type)                                          \
@@ -8849,6 +8881,7 @@ GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
+GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
 #endif
 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
@@ -8856,7 +8889,7 @@ GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
 #undef GEN_ST
 #undef GEN_STU
 #undef GEN_STUX
-#undef GEN_STX
+#undef GEN_STX_E
 #undef GEN_STS
 #define GEN_ST(name, stop, opc, type)                                         \
 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
@@ -8864,8 +8897,8 @@ GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
 #define GEN_STUX(name, stop, opc2, opc3, type)                                \
 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
-#define GEN_STX(name, stop, opc2, opc3, type)                                 \
-GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
+#define GEN_STX_E(name, stop, opc2, opc3, type, type2)                        \
+GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
 #define GEN_STS(name, stop, op, type)                                         \
 GEN_ST(name, stop, op | 0x20, type)                                           \
 GEN_STU(name, stop, op | 0x21, type)                                          \
@@ -8878,6 +8911,7 @@ GEN_STS(stw, st32, 0x04, PPC_INTEGER)
 #if defined(TARGET_PPC64)
 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
+GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
 #endif
 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 6253076..087f2f0 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -6571,7 +6571,7 @@ static void init_proc_970MP (CPUPPCState *env)
                               PPC_64B | PPC_ALTIVEC |                         \
                               PPC_SEGMENT_64B | PPC_SLBI |                    \
                               PPC_POPCNTB | PPC_POPCNTWD)
-#define POWERPC_INSNS2_POWER7 (PPC2_VSX | PPC2_DFP)
+#define POWERPC_INSNS2_POWER7 (PPC2_VSX | PPC2_DFP | PPC2_DBRX)
 #define POWERPC_MSRM_POWER7   (0x800000000204FF36ULL)
 #define POWERPC_MMU_POWER7    (POWERPC_MMU_2_06)
 #define POWERPC_EXCP_POWER7   (POWERPC_EXCP_POWER7)
-- 
1.7.8.3