[PATCH 0/2] serial: pl011: Add xilinx uart

[PATCH 0/2] serial: pl011: Add xilinx uart

[Shubhrajyoti Datta]

-Support uart peripheral in Xilinx Versal SOC.
Add the dt-binding for the same


Raviteja Narayanam (1):
  serial: pl011: Add support for Xilinx Uart

Shubhrajyoti Datta (1):
  dt-bindings: serial: pl011: Add 'arm,xlnx-uart'

 .../devicetree/bindings/serial/pl011.yaml     | 10 ++++--
 drivers/tty/serial/amba-pl011.c               | 33 +++++++++++++++++--
 2 files changed, 38 insertions(+), 5 deletions(-)

-- 
2.25.1

[PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'

[Shubhrajyoti Datta]

Add support for Uart used in Xilinx Versal SOCs as a platform
device.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
---
 Documentation/devicetree/bindings/serial/pl011.yaml | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml
index 5ea00f8a283d..6c73923dd15e 100644
--- a/Documentation/devicetree/bindings/serial/pl011.yaml
+++ b/Documentation/devicetree/bindings/serial/pl011.yaml
@@ -24,9 +24,13 @@ select:
 
 properties:
   compatible:
-    items:
-      - const: arm,pl011
-      - const: arm,primecell
+    oneOf:
+      - items:
+          - const: arm,pl011
+          - const: arm,primecell
+      - items:
+          - const: arm,pl011
+          - const: arm,xlnx-uart # xilinx uart as platform device
 
   reg:
     maxItems: 1
-- 
2.25.1

Re: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'

[Rob Herring]

On Tue, Nov 16, 2021 at 04:47:45PM +0530, Shubhrajyoti Datta wrote:
> Add support for Uart used in Xilinx Versal SOCs as a platform
> device.

No. Why would we want to do that?

> 
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
> ---
>  Documentation/devicetree/bindings/serial/pl011.yaml | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml
> index 5ea00f8a283d..6c73923dd15e 100644
> --- a/Documentation/devicetree/bindings/serial/pl011.yaml
> +++ b/Documentation/devicetree/bindings/serial/pl011.yaml
> @@ -24,9 +24,13 @@ select:
>  
>  properties:
>    compatible:
> -    items:
> -      - const: arm,pl011
> -      - const: arm,primecell
> +    oneOf:
> +      - items:
> +          - const: arm,pl011
> +          - const: arm,primecell
> +      - items:
> +          - const: arm,pl011
> +          - const: arm,xlnx-uart # xilinx uart as platform device

'arm,primecell' means the block has ID registers. Are you saying this 
implementation doesn't?

>  
>    reg:
>      maxItems: 1
> -- 
> 2.25.1
> 
> 

RE: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'

[Shubhrajyoti Datta]

> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Tuesday, November 30, 2021 3:39 AM
> To: Shubhrajyoti Datta <shubhraj@xilinx.com>
> Cc: linux-serial@vger.kernel.org; devicetree@vger.kernel.org;
> gregkh@linuxfoundation.org; Raviteja Narayanam <rna@xlnx.xilinx.com>
> Subject: Re: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'
> 
> On Tue, Nov 16, 2021 at 04:47:45PM +0530, Shubhrajyoti Datta wrote:
> > Add support for Uart used in Xilinx Versal SOCs as a platform device.
> 
> No. Why would we want to do that?
Apologies did not understand that. 

> 
> >
> > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> > Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
> > ---
> >  Documentation/devicetree/bindings/serial/pl011.yaml | 10 +++++++---
> >  1 file changed, 7 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml
> > b/Documentation/devicetree/bindings/serial/pl011.yaml
> > index 5ea00f8a283d..6c73923dd15e 100644
> > --- a/Documentation/devicetree/bindings/serial/pl011.yaml
> > +++ b/Documentation/devicetree/bindings/serial/pl011.yaml
> > @@ -24,9 +24,13 @@ select:
> >
> >  properties:
> >    compatible:
> > -    items:
> > -      - const: arm,pl011
> > -      - const: arm,primecell
> > +    oneOf:
> > +      - items:
> > +          - const: arm,pl011
> > +          - const: arm,primecell
> > +      - items:
> > +          - const: arm,pl011
> > +          - const: arm,xlnx-uart # xilinx uart as platform device
> 
> 'arm,primecell' means the block has ID registers. Are you saying this
> implementation doesn't?

The ID registers do not have any Xilinx specific identifiers.
However there are differences  like 32-bit access.
> 
> >
> >    reg:
> >      maxItems: 1
> > --
> > 2.25.1
> >
> >

RE: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'

[Shubhrajyoti Datta]

> -----Original Message-----
> From: Shubhrajyoti Datta
> Sent: Friday, December 10, 2021 7:12 PM
> To: Rob Herring <robh@kernel.org>
> Cc: linux-serial@vger.kernel.org; devicetree@vger.kernel.org;
> gregkh@linuxfoundation.org; Raviteja Narayanam <rna@xlnx.xilinx.com>
> Subject: RE: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'
> 
> 
> 
> > -----Original Message-----
> > From: Rob Herring <robh@kernel.org>
> > Sent: Tuesday, November 30, 2021 3:39 AM
> > To: Shubhrajyoti Datta <shubhraj@xilinx.com>
> > Cc: linux-serial@vger.kernel.org; devicetree@vger.kernel.org;
> > gregkh@linuxfoundation.org; Raviteja Narayanam <rna@xlnx.xilinx.com>
> > Subject: Re: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'
> >
> > On Tue, Nov 16, 2021 at 04:47:45PM +0530, Shubhrajyoti Datta wrote:
> > > Add support for Uart used in Xilinx Versal SOCs as a platform device.
> >
> > No. Why would we want to do that?
> Apologies did not understand that.
> 
> >
> > >
> > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> > > Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
> > > ---
> > >  Documentation/devicetree/bindings/serial/pl011.yaml | 10 +++++++---
> > >  1 file changed, 7 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml
> > > b/Documentation/devicetree/bindings/serial/pl011.yaml
> > > index 5ea00f8a283d..6c73923dd15e 100644
> > > --- a/Documentation/devicetree/bindings/serial/pl011.yaml
> > > +++ b/Documentation/devicetree/bindings/serial/pl011.yaml
> > > @@ -24,9 +24,13 @@ select:
> > >
> > >  properties:
> > >    compatible:
> > > -    items:
> > > -      - const: arm,pl011
> > > -      - const: arm,primecell
> > > +    oneOf:
> > > +      - items:
> > > +          - const: arm,pl011
> > > +          - const: arm,primecell
> > > +      - items:
> > > +          - const: arm,pl011
> > > +          - const: arm,xlnx-uart # xilinx uart as platform device
> >
> > 'arm,primecell' means the block has ID registers. Are you saying this
> > implementation doesn't?
> 
> The ID registers do not have any Xilinx specific identifiers.
> However there are differences  like 32-bit access.

Hope that the current approach is fine with you.

Thanks 
> >
> > >
> > >    reg:
> > >      maxItems: 1
> > > --
> > > 2.25.1
> > >
> > >

RE: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'

[Shubhrajyoti Datta]

<snip>
> > > > diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml
> > > > b/Documentation/devicetree/bindings/serial/pl011.yaml
> > > > index 5ea00f8a283d..6c73923dd15e 100644
> > > > --- a/Documentation/devicetree/bindings/serial/pl011.yaml
> > > > +++ b/Documentation/devicetree/bindings/serial/pl011.yaml
> > > > @@ -24,9 +24,13 @@ select:
> > > >
> > > >  properties:
> > > >    compatible:
> > > > -    items:
> > > > -      - const: arm,pl011
> > > > -      - const: arm,primecell
> > > > +    oneOf:
> > > > +      - items:
> > > > +          - const: arm,pl011
> > > > +          - const: arm,primecell
> > > > +      - items:
> > > > +          - const: arm,pl011
> > > > +          - const: arm,xlnx-uart # xilinx uart as platform device
> > >
> > > 'arm,primecell' means the block has ID registers. Are you saying
> > > this implementation doesn't?
> >
> > The ID registers do not have any Xilinx specific identifiers.
> > However there are differences  like 32-bit access.
> 
> Hope that the current approach is fine with you.

Could you please guide  how to go about it.
> 
> Thanks
> > >
> > > >
> > > >    reg:
> > > >      maxItems: 1
> > > > --
> > > > 2.25.1
> > > >
> > > >

Re: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'

[Rob Herring]

On Tue, Mar 22, 2022 at 5:59 AM Shubhrajyoti Datta <shubhraj@xilinx.com> wrote:
>
> <snip>
> > > > > diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml
> > > > > b/Documentation/devicetree/bindings/serial/pl011.yaml
> > > > > index 5ea00f8a283d..6c73923dd15e 100644
> > > > > --- a/Documentation/devicetree/bindings/serial/pl011.yaml
> > > > > +++ b/Documentation/devicetree/bindings/serial/pl011.yaml
> > > > > @@ -24,9 +24,13 @@ select:
> > > > >
> > > > >  properties:
> > > > >    compatible:
> > > > > -    items:
> > > > > -      - const: arm,pl011
> > > > > -      - const: arm,primecell
> > > > > +    oneOf:
> > > > > +      - items:
> > > > > +          - const: arm,pl011
> > > > > +          - const: arm,primecell
> > > > > +      - items:
> > > > > +          - const: arm,pl011
> > > > > +          - const: arm,xlnx-uart # xilinx uart as platform device
> > > >
> > > > 'arm,primecell' means the block has ID registers. Are you saying
> > > > this implementation doesn't?
> > >
> > > The ID registers do not have any Xilinx specific identifiers.
> > > However there are differences  like 32-bit access.
> >
> > Hope that the current approach is fine with you.
>
> Could you please guide  how to go about it.

No, I don't know what the differences are in your h/w. You have ID
registers, but changed the IP and didn't change the ID registers? How
has the IP changed?

Rob

Re: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'

[Shubhrajyoti Datta]

> >
 <snip>

>
> No, I don't know what the differences are in your h/w. You have ID
> registers, but changed the IP and didn't change the ID registers? How
> has the IP changed?
>

The IP is not changed and the ID registers are not updated.
The limitation is coming from the AXI  port that the IP is connected to.
The axi port is allowing only the 32 bit access.
The same information will be updated in the Versal TRM.




> Rob

Re: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'

[Michal Simek]

Hi Rob and Krzysztof,

On 6/14/22 14:21, Shubhrajyoti Datta wrote:
>>>
>   <snip>
> 
>>
>> No, I don't know what the differences are in your h/w. You have ID
>> registers, but changed the IP and didn't change the ID registers? How
>> has the IP changed?
>>
> 
> The IP is not changed and the ID registers are not updated.
> The limitation is coming from the AXI  port that the IP is connected to.
> The axi port is allowing only the 32 bit access.
> The same information will be updated in the Versal TRM.

Can you please give us your recommendation how to process with this?

Thanks,
Michal

Re: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'

[Krzysztof Kozlowski]

On 14/07/2022 12:55, Michal Simek wrote:
> Hi Rob and Krzysztof,
> 
> On 6/14/22 14:21, Shubhrajyoti Datta wrote:
>>>>
>>   <snip>
>>
>>>
>>> No, I don't know what the differences are in your h/w. You have ID
>>> registers, but changed the IP and didn't change the ID registers? How
>>> has the IP changed?
>>>
>>
>> The IP is not changed and the ID registers are not updated.
>> The limitation is coming from the AXI  port that the IP is connected to.
>> The axi port is allowing only the 32 bit access.
>> The same information will be updated in the Versal TRM.
> 
> Can you please give us your recommendation how to process with this?

Unfortunately I don't think that anyone remembers context from last
year, especially me who was not Cced. Rob responded at end of March and
it took two months to get back any answer. Such slow response time from
submitter does not help to stay in the context. :(


Best regards,
Krzysztof

RE: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'

[Datta, Shubhrajyoti]

[AMD Official Use Only - General]



> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Thursday, July 14, 2022 5:29 PM
> To: Michal Simek <michal.simek@xilinx.com>; Shubhrajyoti Datta
> <shubhrajyoti.datta@gmail.com>; Rob Herring <robh@kernel.org>; Krzysztof
> Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Shubhrajyoti Datta <shubhraj@xilinx.com>; linux-serial@vger.kernel.org;
> devicetree@vger.kernel.org; gregkh@linuxfoundation.org; Srinivas Goud
> <sgoud@xilinx.com>
> Subject: Re: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'
> 
> CAUTION: This message has originated from an External Source. Please use
> proper judgment and caution when opening attachments, clicking links, or
> responding to this email.
> 
> 
> On 14/07/2022 12:55, Michal Simek wrote:
> > Hi Rob and Krzysztof,
> >
> > On 6/14/22 14:21, Shubhrajyoti Datta wrote:
> >>>>
> >>   <snip>
> >>
> >>>
> >>> No, I don't know what the differences are in your h/w. You have ID
> >>> registers, but changed the IP and didn't change the ID registers?
> >>> How has the IP changed?
> >>>
> >>
> >> The IP is not changed and the ID registers are not updated.
> >> The limitation is coming from the AXI  port that the IP is connected to.
> >> The axi port is allowing only the 32 bit access.
> >> The same information will be updated in the Versal TRM.
> >
> > Can you please give us your recommendation how to process with this?
> 
> Unfortunately I don't think that anyone remembers context from last year,
> especially me who was not Cced. Rob responded at end of March and it took
> two months to get back any answer. Such slow response time from submitter
> does not help to stay in the context. :(

I had to contact the hardware team and get the details on the issue it took me sometime to get a response.

I will summarize 

We are using the ip from ARM but the AXI port that we hooked has a limitation that it allows only 32 bit accesses.

So to tide over the and differentiate  I am adding a new compatible arm,xlnx-uart.

> 
> 
> Best regards,
> Krzysztof

Re: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'

[Michal Simek]

On 7/14/22 14:14, Datta, Shubhrajyoti wrote:
> [AMD Official Use Only - General]
> 
> 
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Sent: Thursday, July 14, 2022 5:29 PM
>> To: Michal Simek <michal.simek@xilinx.com>; Shubhrajyoti Datta
>> <shubhrajyoti.datta@gmail.com>; Rob Herring <robh@kernel.org>; Krzysztof
>> Kozlowski <krzysztof.kozlowski+dt@linaro.org>
>> Cc: Shubhrajyoti Datta <shubhraj@xilinx.com>; linux-serial@vger.kernel.org;
>> devicetree@vger.kernel.org; gregkh@linuxfoundation.org; Srinivas Goud
>> <sgoud@xilinx.com>
>> Subject: Re: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'
>>
>> CAUTION: This message has originated from an External Source. Please use
>> proper judgment and caution when opening attachments, clicking links, or
>> responding to this email.
>>
>>
>> On 14/07/2022 12:55, Michal Simek wrote:
>>> Hi Rob and Krzysztof,
>>>
>>> On 6/14/22 14:21, Shubhrajyoti Datta wrote:
>>>>>>
>>>>    <snip>
>>>>
>>>>>
>>>>> No, I don't know what the differences are in your h/w. You have ID
>>>>> registers, but changed the IP and didn't change the ID registers?
>>>>> How has the IP changed?
>>>>>
>>>>
>>>> The IP is not changed and the ID registers are not updated.
>>>> The limitation is coming from the AXI  port that the IP is connected to.
>>>> The axi port is allowing only the 32 bit access.
>>>> The same information will be updated in the Versal TRM.
>>>
>>> Can you please give us your recommendation how to process with this?
>>
>> Unfortunately I don't think that anyone remembers context from last year,
>> especially me who was not Cced. Rob responded at end of March and it took
>> two months to get back any answer. Such slow response time from submitter
>> does not help to stay in the context. :(
> 
> I had to contact the hardware team and get the details on the issue it took me sometime to get a response.
> 
> I will summarize
> 
> We are using the ip from ARM but the AXI port that we hooked has a limitation that it allows only 32 bit accesses.
> 
> So to tide over the and differentiate  I am adding a new compatible arm,xlnx-uart.

ok.

Shubhrajyoti: Please send this series again with updated commit message in 1/2 
which contains information you provided here. That means it will be v2 version.

Thanks,
Michal

[PATCH 2/2] serial: pl011: Add support for Xilinx Uart

[Shubhrajyoti Datta]

From: Raviteja Narayanam <raviteja.narayanam@xilinx.com>

The xilinx uart used in Versal SOC follows arm pl011 implementation
with just a minor change in data bus width. The minimum data
transaction width in Versal SOC is 32-bit as specified in the
TRM (Chapter 39: Transaction attributes). Pl011 defaults to 16-bit
in the driver.
So, add the xilinx uart as platform device with properties specified
in 'vendor_data' structure.

Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
 drivers/tty/serial/amba-pl011.c | 33 +++++++++++++++++++++++++++++++--
 1 file changed, 31 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index d361cd84ff8c..278255a45ad9 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -124,6 +124,21 @@ static const struct vendor_data vendor_sbsa = {
 	.fixed_options		= true,
 };
 
+static const struct vendor_data vendor_xlnx = {
+	.reg_offset             = pl011_std_offsets,
+	.ifls                   = UART011_IFLS_RX4_8 | UART011_IFLS_TX4_8,
+	.fr_busy                = UART01x_FR_BUSY,
+	.fr_dsr                 = UART01x_FR_DSR,
+	.fr_cts                 = UART01x_FR_CTS,
+	.fr_ri                  = UART011_FR_RI,
+	.access_32b             = true,
+	.oversampling           = false,
+	.dma_threshold          = false,
+	.cts_event_workaround   = false,
+	.always_enabled         = true,
+	.fixed_options          = false,
+};
+
 #ifdef CONFIG_ACPI_SPCR_TABLE
 static const struct vendor_data vendor_qdt_qdf2400_e44 = {
 	.reg_offset		= pl011_std_offsets,
@@ -2628,6 +2643,7 @@ static int __init pl011_early_console_setup(struct earlycon_device *device,
 }
 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
+OF_EARLYCON_DECLARE(pl011, "arm,xlnx-uart", pl011_early_console_setup);
 
 /*
  * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by
@@ -2872,6 +2888,7 @@ static int sbsa_uart_probe(struct platform_device *pdev)
 {
 	struct uart_amba_port *uap;
 	struct resource *r;
+	int xlnx_uart = 0;
 	int portnr, ret;
 	int baudrate;
 
@@ -2882,6 +2899,7 @@ static int sbsa_uart_probe(struct platform_device *pdev)
 	if (pdev->dev.of_node) {
 		struct device_node *np = pdev->dev.of_node;
 
+		xlnx_uart = of_device_is_compatible(np, "arm,xlnx-uart");
 		ret = of_property_read_u32(np, "current-speed", &baudrate);
 		if (ret)
 			return ret;
@@ -2911,13 +2929,23 @@ static int sbsa_uart_probe(struct platform_device *pdev)
 #endif
 		uap->vendor = &vendor_sbsa;
 
+	uap->port.ops   = &sbsa_uart_pops;
+
+	if (xlnx_uart) {
+		uap->vendor = &vendor_xlnx;
+		uap->clk = devm_clk_get(&pdev->dev, NULL);
+		if (IS_ERR(uap->clk))
+			return PTR_ERR(uap->clk);
+
+		uap->port.ops = &amba_pl011_pops;
+	}
+
 	uap->reg_offset	= uap->vendor->reg_offset;
 	uap->fifosize	= 32;
 	uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
-	uap->port.ops	= &sbsa_uart_pops;
 	uap->fixed_baud = baudrate;
 
-	snprintf(uap->type, sizeof(uap->type), "SBSA");
+	snprintf(uap->type, sizeof(uap->type), "%s\n", (xlnx_uart ? "xlnx_uart" : "SBSA"));
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 
@@ -2941,6 +2969,7 @@ static int sbsa_uart_remove(struct platform_device *pdev)
 
 static const struct of_device_id sbsa_uart_of_match[] = {
 	{ .compatible = "arm,sbsa-uart", },
+	{ .compatible = "arm,xlnx-uart", },
 	{},
 };
 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
-- 
2.25.1