From: Alexandru Elisei <alexandru.elisei@arm.com> To: Auger Eric <eric.auger@redhat.com>, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, drjones@redhat.com Cc: andre.przywara@arm.com Subject: Re: [kvm-unit-tests PATCH 01/10] lib: arm/arm64: gicv3: Add missing barrier when sending IPIs Date: Tue, 1 Dec 2020 17:37:26 +0000 [thread overview] Message-ID: <d4ea93b8-e275-11db-4c97-a697caa39516@arm.com> (raw) In-Reply-To: <c92e0793-d204-0a84-2f6e-8cbd6c455da2@redhat.com> Hi Eric, Thank you so much for having a look at the patches! On 12/1/20 4:37 PM, Auger Eric wrote: > Hi Alexandru, > > On 11/25/20 4:51 PM, Alexandru Elisei wrote: >> One common usage for IPIs is for one CPU to write to a shared memory >> location, send the IPI to kick another CPU, and the receiver to read from >> the same location. Proper synchronization is needed to make sure that the >> IPI receiver reads the most recent value and not stale data (for example, >> the write from the sender CPU might still be in a store buffer). >> >> For GICv3, IPIs are generated with a write to the ICC_SGI1R_EL1 register. >> To make sure the memory stores are observable by other CPUs, we need a >> wmb() barrier (DSB ST), which waits for stores to complete. >> >> From the definition of DSB from ARM DDI 0487F.b, page B2-139: >> >> "In addition, no instruction that appears in program order after the DSB >> instruction can alter any state of the system or perform any part of its >> functionality until the DSB completes other than: >> >> - Being fetched from memory and decoded. >> - Reading the general-purpose, SIMD and floating-point, Special-purpose, or >> System registers that are directly or indirectly read without causing >> side-effects." >> >> Similar definition for armv7 (ARM DDI 0406C.d, page A3-150). >> >> The DSB instruction is enough to prevent reordering of the GIC register >> write which comes in program order after the memory access. >> >> This also matches what the Linux GICv3 irqchip driver does (commit >> 21ec30c0ef52 ("irqchip/gic-v3: Use wmb() instead of smb_wmb() in >> gic_raise_softirq()")). >> >> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> >> --- >> lib/arm/gic-v3.c | 3 +++ >> arm/gic.c | 2 ++ >> 2 files changed, 5 insertions(+) >> >> diff --git a/lib/arm/gic-v3.c b/lib/arm/gic-v3.c >> index a7e2cb819746..a6afa42d5fbe 100644 >> --- a/lib/arm/gic-v3.c >> +++ b/lib/arm/gic-v3.c >> @@ -77,6 +77,9 @@ void gicv3_ipi_send_mask(int irq, const cpumask_t *dest) >> >> assert(irq < 16); >> >> + /* Ensure stores are visible to other CPUs before sending the IPI */ > nit: stores to normal memory ... Yes, you are completely right. Specifying that it affects only stores to normal memory would match the comment in the Linux irqchip driver and also what the architecture specifies for device memory (page B2-158): "Data accesses to memory locations are coherent for all observers in the system, and correspondingly are treated as being Outer Shareable. A memory location with any Device memory attribute cannot be allocated into a cache". Same thing below, will change. Thanks, Alex >> + wmb(); >> + >> /* >> * For each cpu in the mask collect its peers, which are also in >> * the mask, in order to form target lists. >> diff --git a/arm/gic.c b/arm/gic.c >> index acb060585fae..512c83636a2e 100644 >> --- a/arm/gic.c >> +++ b/arm/gic.c >> @@ -275,6 +275,8 @@ static void gicv3_ipi_send_self(void) >> >> static void gicv3_ipi_send_broadcast(void) >> { >> + /* Ensure stores are visible to other CPUs before sending the IPI */ > same >> + wmb(); >> gicv3_write_sgi1r(1ULL << 40 | IPI_IRQ << 24); >> isb(); >> } >> > Reviewed-by: Eric Auger <eric.auger@redhat.com> > > Thanks > > Eric >
WARNING: multiple messages have this Message-ID (diff)
From: Alexandru Elisei <alexandru.elisei@arm.com> To: Auger Eric <eric.auger@redhat.com>, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, drjones@redhat.com Cc: andre.przywara@arm.com Subject: Re: [kvm-unit-tests PATCH 01/10] lib: arm/arm64: gicv3: Add missing barrier when sending IPIs Date: Tue, 1 Dec 2020 17:37:26 +0000 [thread overview] Message-ID: <d4ea93b8-e275-11db-4c97-a697caa39516@arm.com> (raw) In-Reply-To: <c92e0793-d204-0a84-2f6e-8cbd6c455da2@redhat.com> Hi Eric, Thank you so much for having a look at the patches! On 12/1/20 4:37 PM, Auger Eric wrote: > Hi Alexandru, > > On 11/25/20 4:51 PM, Alexandru Elisei wrote: >> One common usage for IPIs is for one CPU to write to a shared memory >> location, send the IPI to kick another CPU, and the receiver to read from >> the same location. Proper synchronization is needed to make sure that the >> IPI receiver reads the most recent value and not stale data (for example, >> the write from the sender CPU might still be in a store buffer). >> >> For GICv3, IPIs are generated with a write to the ICC_SGI1R_EL1 register. >> To make sure the memory stores are observable by other CPUs, we need a >> wmb() barrier (DSB ST), which waits for stores to complete. >> >> From the definition of DSB from ARM DDI 0487F.b, page B2-139: >> >> "In addition, no instruction that appears in program order after the DSB >> instruction can alter any state of the system or perform any part of its >> functionality until the DSB completes other than: >> >> - Being fetched from memory and decoded. >> - Reading the general-purpose, SIMD and floating-point, Special-purpose, or >> System registers that are directly or indirectly read without causing >> side-effects." >> >> Similar definition for armv7 (ARM DDI 0406C.d, page A3-150). >> >> The DSB instruction is enough to prevent reordering of the GIC register >> write which comes in program order after the memory access. >> >> This also matches what the Linux GICv3 irqchip driver does (commit >> 21ec30c0ef52 ("irqchip/gic-v3: Use wmb() instead of smb_wmb() in >> gic_raise_softirq()")). >> >> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> >> --- >> lib/arm/gic-v3.c | 3 +++ >> arm/gic.c | 2 ++ >> 2 files changed, 5 insertions(+) >> >> diff --git a/lib/arm/gic-v3.c b/lib/arm/gic-v3.c >> index a7e2cb819746..a6afa42d5fbe 100644 >> --- a/lib/arm/gic-v3.c >> +++ b/lib/arm/gic-v3.c >> @@ -77,6 +77,9 @@ void gicv3_ipi_send_mask(int irq, const cpumask_t *dest) >> >> assert(irq < 16); >> >> + /* Ensure stores are visible to other CPUs before sending the IPI */ > nit: stores to normal memory ... Yes, you are completely right. Specifying that it affects only stores to normal memory would match the comment in the Linux irqchip driver and also what the architecture specifies for device memory (page B2-158): "Data accesses to memory locations are coherent for all observers in the system, and correspondingly are treated as being Outer Shareable. A memory location with any Device memory attribute cannot be allocated into a cache". Same thing below, will change. Thanks, Alex >> + wmb(); >> + >> /* >> * For each cpu in the mask collect its peers, which are also in >> * the mask, in order to form target lists. >> diff --git a/arm/gic.c b/arm/gic.c >> index acb060585fae..512c83636a2e 100644 >> --- a/arm/gic.c >> +++ b/arm/gic.c >> @@ -275,6 +275,8 @@ static void gicv3_ipi_send_self(void) >> >> static void gicv3_ipi_send_broadcast(void) >> { >> + /* Ensure stores are visible to other CPUs before sending the IPI */ > same >> + wmb(); >> gicv3_write_sgi1r(1ULL << 40 | IPI_IRQ << 24); >> isb(); >> } >> > Reviewed-by: Eric Auger <eric.auger@redhat.com> > > Thanks > > Eric > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
next prev parent reply other threads:[~2020-12-01 17:37 UTC|newest] Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-25 15:51 [kvm-unit-tests PATCH 00/10] GIC fixes and improvements Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-11-25 15:51 ` [kvm-unit-tests PATCH 01/10] lib: arm/arm64: gicv3: Add missing barrier when sending IPIs Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-12-01 16:37 ` Auger Eric 2020-12-01 16:37 ` Auger Eric 2020-12-01 17:37 ` Alexandru Elisei [this message] 2020-12-01 17:37 ` Alexandru Elisei 2020-11-25 15:51 ` [kvm-unit-tests PATCH 02/10] lib: arm/arm64: gicv2: " Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-12-01 16:37 ` Auger Eric 2020-12-01 16:37 ` Auger Eric 2020-11-25 15:51 ` [kvm-unit-tests PATCH 03/10] arm/arm64: gic: Remove memory synchronization from ipi_clear_active_handler() Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-12-01 16:37 ` Auger Eric 2020-12-01 16:37 ` Auger Eric 2020-12-02 14:02 ` Alexandru Elisei 2020-12-02 14:02 ` Alexandru Elisei 2020-12-02 14:14 ` Alexandru Elisei 2020-12-02 14:14 ` Alexandru Elisei 2020-12-03 9:41 ` Auger Eric 2020-12-03 9:41 ` Auger Eric 2020-11-25 15:51 ` [kvm-unit-tests PATCH 04/10] arm/arm64: gic: Remove unnecessary synchronization with stats_reset() Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-12-01 16:48 ` Auger Eric 2020-12-01 16:48 ` Auger Eric 2020-12-02 14:06 ` Alexandru Elisei 2020-12-02 14:06 ` Alexandru Elisei 2020-12-03 13:10 ` Auger Eric 2020-12-03 13:10 ` Auger Eric 2020-11-25 15:51 ` [kvm-unit-tests PATCH 05/10] arm/arm64: gic: Use correct memory ordering for the IPI test Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-12-03 13:10 ` Auger Eric 2020-12-03 13:10 ` Auger Eric 2020-12-03 13:21 ` Alexandru Elisei 2020-12-03 13:21 ` Alexandru Elisei 2020-11-25 15:51 ` [kvm-unit-tests PATCH 06/10] arm/arm64: gic: Check spurious and bad_sender in the active test Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-12-03 13:10 ` Auger Eric 2020-12-03 13:10 ` Auger Eric 2020-11-25 15:51 ` [kvm-unit-tests PATCH 07/10] arm/arm64: gic: Wait for writes to acked or spurious to complete Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-12-03 13:21 ` Auger Eric 2020-12-03 13:21 ` Auger Eric 2020-11-25 15:51 ` [kvm-unit-tests PATCH 08/10] arm/arm64: gic: Split check_acked() into two functions Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-12-03 13:39 ` Auger Eric 2020-12-03 13:39 ` Auger Eric 2020-12-10 14:45 ` Alexandru Elisei 2020-12-10 14:45 ` Alexandru Elisei 2020-12-15 13:58 ` Auger Eric 2020-12-15 13:58 ` Auger Eric 2020-12-16 11:40 ` Alexandru Elisei 2020-12-16 11:40 ` Alexandru Elisei 2020-12-16 12:37 ` Auger Eric 2020-12-16 12:37 ` Auger Eric 2020-11-25 15:51 ` [kvm-unit-tests PATCH 09/10] arm/arm64: gic: Make check_acked() more generic Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-12-03 14:59 ` Auger Eric 2020-12-03 14:59 ` Auger Eric 2020-11-25 15:51 ` [kvm-unit-tests PATCH 10/10] arm64: gic: Use IPI test checking for the LPI tests Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-11-26 9:30 ` Zenghui Yu 2020-11-26 9:30 ` Zenghui Yu 2020-11-27 14:50 ` Alexandru Elisei 2020-11-27 14:50 ` Alexandru Elisei 2020-11-30 13:59 ` Zenghui Yu 2020-11-30 13:59 ` Zenghui Yu 2020-11-30 14:19 ` Alexandru Elisei 2020-11-30 14:19 ` Alexandru Elisei 2020-12-01 15:09 ` Alexandru Elisei 2020-12-01 15:09 ` Alexandru Elisei 2020-11-30 17:48 ` Auger Eric 2020-11-30 17:48 ` Auger Eric 2020-12-03 14:59 ` Auger Eric 2020-12-03 14:59 ` Auger Eric 2020-12-09 10:29 ` Alexandru Elisei 2020-12-09 10:29 ` Alexandru Elisei
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=d4ea93b8-e275-11db-4c97-a697caa39516@arm.com \ --to=alexandru.elisei@arm.com \ --cc=andre.przywara@arm.com \ --cc=drjones@redhat.com \ --cc=eric.auger@redhat.com \ --cc=kvm@vger.kernel.org \ --cc=kvmarm@lists.cs.columbia.edu \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.