From: Alexandru Elisei <alexandru.elisei@arm.com> To: Auger Eric <eric.auger@redhat.com>, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, drjones@redhat.com Cc: andre.przywara@arm.com Subject: Re: [kvm-unit-tests PATCH 03/10] arm/arm64: gic: Remove memory synchronization from ipi_clear_active_handler() Date: Wed, 2 Dec 2020 14:02:32 +0000 [thread overview] Message-ID: <df9e2243-008b-3f93-e499-98b887b6c848@arm.com> (raw) In-Reply-To: <038402be-a119-c162-04f2-d32db26e8a96@redhat.com> Hi Eric, On 12/1/20 4:37 PM, Auger Eric wrote: > Hi Alexandru, > > On 11/25/20 4:51 PM, Alexandru Elisei wrote: >> The gicv{2,3}-active test sends an IPI from the boot CPU to itself, then >> checks that the interrupt has been received as expected. There is no need >> to use inter-processor memory synchronization primitives on code that runs >> on the same CPU, so remove the unneeded memory barriers. >> >> The arrays are modified asynchronously (in the interrupt handler) and it is >> possible for the compiler to infer that they won't be changed during normal >> program flow and try to perform harmful optimizations (like stashing a >> previous read in a register and reusing it). To prevent this, for GICv2, >> the smp_wmb() in gicv2_ipi_send_self() is replaced with a compiler barrier. >> For GICv3, the wmb() barrier in gic_ipi_send_single() already implies a >> compiler barrier. >> >> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> >> --- >> arm/gic.c | 8 ++++---- >> 1 file changed, 4 insertions(+), 4 deletions(-) >> >> diff --git a/arm/gic.c b/arm/gic.c >> index 401ffafe4299..4e947e8516a2 100644 >> --- a/arm/gic.c >> +++ b/arm/gic.c >> @@ -12,6 +12,7 @@ >> * This work is licensed under the terms of the GNU LGPL, version 2. >> */ >> #include <libcflat.h> >> +#include <linux/compiler.h> >> #include <errata.h> >> #include <asm/setup.h> >> #include <asm/processor.h> >> @@ -260,7 +261,8 @@ static void check_lpi_hits(int *expected, const char *msg) >> >> static void gicv2_ipi_send_self(void) >> {> - smp_wmb(); > nit: previous patch added it and this patch removes it. maybe squash the > modifs into the previous patch saying only a barrier() is needed for self()? You're right, this does look out of place. I'll merge this change into the previous patch. >> + /* Prevent the compiler from optimizing memory accesses */ >> + barrier(); >> writel(2 << 24 | IPI_IRQ, gicv2_dist_base() + GICD_SGIR); >> } >> >> @@ -359,6 +361,7 @@ static struct gic gicv3 = { >> }, >> }; >> >> +/* Runs on the same CPU as the sender, no need for memory synchronization */ >> static void ipi_clear_active_handler(struct pt_regs *regs __unused) >> { >> u32 irqstat = gic_read_iar(); >> @@ -375,13 +378,10 @@ static void ipi_clear_active_handler(struct pt_regs *regs __unused) >> >> writel(val, base + GICD_ICACTIVER); >> >> - smp_rmb(); /* pairs with wmb in stats_reset */ > the comment says it is paired with wmd in stats_reset. So is it OK to > leave the associated wmb? This patch removes multi-processor synchronization from the functions that run on the same CPU. stats_reset() can be called from one CPU (the IPI_SENDER CPU) and the variables it modifies accessed by the interrupt handlers running on different CPUs, like it happens for the IPI tests. In that case we do need the proper barriers in place. Thanks, Alex >> ++acked[smp_processor_id()]; >> check_irqnr(irqnr); >> - smp_wmb(); /* pairs with rmb in check_acked */ > same here. >> } else { >> ++spurious[smp_processor_id()]; >> - smp_wmb(); >> } >> } >> >> > Thanks > > Eric >
WARNING: multiple messages have this Message-ID (diff)
From: Alexandru Elisei <alexandru.elisei@arm.com> To: Auger Eric <eric.auger@redhat.com>, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, drjones@redhat.com Cc: andre.przywara@arm.com Subject: Re: [kvm-unit-tests PATCH 03/10] arm/arm64: gic: Remove memory synchronization from ipi_clear_active_handler() Date: Wed, 2 Dec 2020 14:02:32 +0000 [thread overview] Message-ID: <df9e2243-008b-3f93-e499-98b887b6c848@arm.com> (raw) In-Reply-To: <038402be-a119-c162-04f2-d32db26e8a96@redhat.com> Hi Eric, On 12/1/20 4:37 PM, Auger Eric wrote: > Hi Alexandru, > > On 11/25/20 4:51 PM, Alexandru Elisei wrote: >> The gicv{2,3}-active test sends an IPI from the boot CPU to itself, then >> checks that the interrupt has been received as expected. There is no need >> to use inter-processor memory synchronization primitives on code that runs >> on the same CPU, so remove the unneeded memory barriers. >> >> The arrays are modified asynchronously (in the interrupt handler) and it is >> possible for the compiler to infer that they won't be changed during normal >> program flow and try to perform harmful optimizations (like stashing a >> previous read in a register and reusing it). To prevent this, for GICv2, >> the smp_wmb() in gicv2_ipi_send_self() is replaced with a compiler barrier. >> For GICv3, the wmb() barrier in gic_ipi_send_single() already implies a >> compiler barrier. >> >> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> >> --- >> arm/gic.c | 8 ++++---- >> 1 file changed, 4 insertions(+), 4 deletions(-) >> >> diff --git a/arm/gic.c b/arm/gic.c >> index 401ffafe4299..4e947e8516a2 100644 >> --- a/arm/gic.c >> +++ b/arm/gic.c >> @@ -12,6 +12,7 @@ >> * This work is licensed under the terms of the GNU LGPL, version 2. >> */ >> #include <libcflat.h> >> +#include <linux/compiler.h> >> #include <errata.h> >> #include <asm/setup.h> >> #include <asm/processor.h> >> @@ -260,7 +261,8 @@ static void check_lpi_hits(int *expected, const char *msg) >> >> static void gicv2_ipi_send_self(void) >> {> - smp_wmb(); > nit: previous patch added it and this patch removes it. maybe squash the > modifs into the previous patch saying only a barrier() is needed for self()? You're right, this does look out of place. I'll merge this change into the previous patch. >> + /* Prevent the compiler from optimizing memory accesses */ >> + barrier(); >> writel(2 << 24 | IPI_IRQ, gicv2_dist_base() + GICD_SGIR); >> } >> >> @@ -359,6 +361,7 @@ static struct gic gicv3 = { >> }, >> }; >> >> +/* Runs on the same CPU as the sender, no need for memory synchronization */ >> static void ipi_clear_active_handler(struct pt_regs *regs __unused) >> { >> u32 irqstat = gic_read_iar(); >> @@ -375,13 +378,10 @@ static void ipi_clear_active_handler(struct pt_regs *regs __unused) >> >> writel(val, base + GICD_ICACTIVER); >> >> - smp_rmb(); /* pairs with wmb in stats_reset */ > the comment says it is paired with wmd in stats_reset. So is it OK to > leave the associated wmb? This patch removes multi-processor synchronization from the functions that run on the same CPU. stats_reset() can be called from one CPU (the IPI_SENDER CPU) and the variables it modifies accessed by the interrupt handlers running on different CPUs, like it happens for the IPI tests. In that case we do need the proper barriers in place. Thanks, Alex >> ++acked[smp_processor_id()]; >> check_irqnr(irqnr); >> - smp_wmb(); /* pairs with rmb in check_acked */ > same here. >> } else { >> ++spurious[smp_processor_id()]; >> - smp_wmb(); >> } >> } >> >> > Thanks > > Eric > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
next prev parent reply other threads:[~2020-12-02 14:01 UTC|newest] Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-25 15:51 [kvm-unit-tests PATCH 00/10] GIC fixes and improvements Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-11-25 15:51 ` [kvm-unit-tests PATCH 01/10] lib: arm/arm64: gicv3: Add missing barrier when sending IPIs Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-12-01 16:37 ` Auger Eric 2020-12-01 16:37 ` Auger Eric 2020-12-01 17:37 ` Alexandru Elisei 2020-12-01 17:37 ` Alexandru Elisei 2020-11-25 15:51 ` [kvm-unit-tests PATCH 02/10] lib: arm/arm64: gicv2: " Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-12-01 16:37 ` Auger Eric 2020-12-01 16:37 ` Auger Eric 2020-11-25 15:51 ` [kvm-unit-tests PATCH 03/10] arm/arm64: gic: Remove memory synchronization from ipi_clear_active_handler() Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-12-01 16:37 ` Auger Eric 2020-12-01 16:37 ` Auger Eric 2020-12-02 14:02 ` Alexandru Elisei [this message] 2020-12-02 14:02 ` Alexandru Elisei 2020-12-02 14:14 ` Alexandru Elisei 2020-12-02 14:14 ` Alexandru Elisei 2020-12-03 9:41 ` Auger Eric 2020-12-03 9:41 ` Auger Eric 2020-11-25 15:51 ` [kvm-unit-tests PATCH 04/10] arm/arm64: gic: Remove unnecessary synchronization with stats_reset() Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-12-01 16:48 ` Auger Eric 2020-12-01 16:48 ` Auger Eric 2020-12-02 14:06 ` Alexandru Elisei 2020-12-02 14:06 ` Alexandru Elisei 2020-12-03 13:10 ` Auger Eric 2020-12-03 13:10 ` Auger Eric 2020-11-25 15:51 ` [kvm-unit-tests PATCH 05/10] arm/arm64: gic: Use correct memory ordering for the IPI test Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-12-03 13:10 ` Auger Eric 2020-12-03 13:10 ` Auger Eric 2020-12-03 13:21 ` Alexandru Elisei 2020-12-03 13:21 ` Alexandru Elisei 2020-11-25 15:51 ` [kvm-unit-tests PATCH 06/10] arm/arm64: gic: Check spurious and bad_sender in the active test Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-12-03 13:10 ` Auger Eric 2020-12-03 13:10 ` Auger Eric 2020-11-25 15:51 ` [kvm-unit-tests PATCH 07/10] arm/arm64: gic: Wait for writes to acked or spurious to complete Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-12-03 13:21 ` Auger Eric 2020-12-03 13:21 ` Auger Eric 2020-11-25 15:51 ` [kvm-unit-tests PATCH 08/10] arm/arm64: gic: Split check_acked() into two functions Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-12-03 13:39 ` Auger Eric 2020-12-03 13:39 ` Auger Eric 2020-12-10 14:45 ` Alexandru Elisei 2020-12-10 14:45 ` Alexandru Elisei 2020-12-15 13:58 ` Auger Eric 2020-12-15 13:58 ` Auger Eric 2020-12-16 11:40 ` Alexandru Elisei 2020-12-16 11:40 ` Alexandru Elisei 2020-12-16 12:37 ` Auger Eric 2020-12-16 12:37 ` Auger Eric 2020-11-25 15:51 ` [kvm-unit-tests PATCH 09/10] arm/arm64: gic: Make check_acked() more generic Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-12-03 14:59 ` Auger Eric 2020-12-03 14:59 ` Auger Eric 2020-11-25 15:51 ` [kvm-unit-tests PATCH 10/10] arm64: gic: Use IPI test checking for the LPI tests Alexandru Elisei 2020-11-25 15:51 ` Alexandru Elisei 2020-11-26 9:30 ` Zenghui Yu 2020-11-26 9:30 ` Zenghui Yu 2020-11-27 14:50 ` Alexandru Elisei 2020-11-27 14:50 ` Alexandru Elisei 2020-11-30 13:59 ` Zenghui Yu 2020-11-30 13:59 ` Zenghui Yu 2020-11-30 14:19 ` Alexandru Elisei 2020-11-30 14:19 ` Alexandru Elisei 2020-12-01 15:09 ` Alexandru Elisei 2020-12-01 15:09 ` Alexandru Elisei 2020-11-30 17:48 ` Auger Eric 2020-11-30 17:48 ` Auger Eric 2020-12-03 14:59 ` Auger Eric 2020-12-03 14:59 ` Auger Eric 2020-12-09 10:29 ` Alexandru Elisei 2020-12-09 10:29 ` Alexandru Elisei
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=df9e2243-008b-3f93-e499-98b887b6c848@arm.com \ --to=alexandru.elisei@arm.com \ --cc=andre.przywara@arm.com \ --cc=drjones@redhat.com \ --cc=eric.auger@redhat.com \ --cc=kvm@vger.kernel.org \ --cc=kvmarm@lists.cs.columbia.edu \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.