* [PATCH v2 01/22] PCI: endpoint: Add EP core layer to enable EP controller and EP functions
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-17 11:26 ` Joao Pinto
2017-02-17 9:50 ` [PATCH v2 02/22] Documentation: PCI: Guide to use PCI Endpoint Core Layer Kishon Vijay Abraham I
` (20 subsequent siblings)
21 siblings, 1 reply; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: linux-pci, linux-doc, linux-kernel, devicetree, linux-omap,
linux-arm-kernel, nsekhar, Kishon Vijay Abraham I
Introduce a new EP core layer in order to support endpoint functions
in linux kernel. This comprises of EPC library
(Endpoint Controller Library) and EPF library (Endpoint
Function Library). EPC library implements functions that is specific
to an endpoint controller and EPF library implements functions
that is specific to an endpoint function.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/Makefile | 2 +
drivers/pci/Kconfig | 1 +
drivers/pci/endpoint/Kconfig | 21 ++
drivers/pci/endpoint/Makefile | 6 +
drivers/pci/endpoint/pci-epc-core.c | 548 +++++++++++++++++++++++++++++++++++
drivers/pci/endpoint/pci-epc-mem.c | 143 +++++++++
drivers/pci/endpoint/pci-epf-core.c | 347 ++++++++++++++++++++++
include/linux/mod_devicetable.h | 10 +
include/linux/pci-epc.h | 141 +++++++++
include/linux/pci-epf.h | 160 ++++++++++
10 files changed, 1379 insertions(+)
create mode 100644 drivers/pci/endpoint/Kconfig
create mode 100644 drivers/pci/endpoint/Makefile
create mode 100644 drivers/pci/endpoint/pci-epc-core.c
create mode 100644 drivers/pci/endpoint/pci-epc-mem.c
create mode 100644 drivers/pci/endpoint/pci-epf-core.c
create mode 100644 include/linux/pci-epc.h
create mode 100644 include/linux/pci-epf.h
diff --git a/drivers/Makefile b/drivers/Makefile
index f521cb0..a300bb1 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -14,7 +14,9 @@ obj-$(CONFIG_GENERIC_PHY) += phy/
obj-$(CONFIG_PINCTRL) += pinctrl/
obj-$(CONFIG_GPIOLIB) += gpio/
obj-y += pwm/
+
obj-$(CONFIG_PCI) += pci/
+obj-$(CONFIG_PCI_ENDPOINT) += pci/endpoint/
# PCI dwc controller drivers
obj-y += pci/dwc/
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index df14142..9747c1e 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -134,3 +134,4 @@ config PCI_HYPERV
source "drivers/pci/hotplug/Kconfig"
source "drivers/pci/dwc/Kconfig"
source "drivers/pci/host/Kconfig"
+source "drivers/pci/endpoint/Kconfig"
diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig
new file mode 100644
index 0000000..7eb1c79
--- /dev/null
+++ b/drivers/pci/endpoint/Kconfig
@@ -0,0 +1,21 @@
+#
+# PCI Endpoint Support
+#
+
+menu "PCI Endpoint"
+
+config PCI_ENDPOINT
+ bool "PCI Endpoint Support"
+ select CONFIGFS_FS
+ help
+ Enable this configuration option to support configurable PCI
+ endpoint. This should be enabled if the platform has a PCI
+ controller that can operate in endpoint mode.
+
+ Enabling this option will build the endpoint library, which
+ includes endpoint controller library and endpoint function
+ library.
+
+ If in doubt, say "N" to disable Endpoint support.
+
+endmenu
diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile
new file mode 100644
index 0000000..dc1bc16
--- /dev/null
+++ b/drivers/pci/endpoint/Makefile
@@ -0,0 +1,6 @@
+#
+# Makefile for PCI Endpoint Support
+#
+
+obj-$(CONFIG_PCI_ENDPOINT) += pci-epc-core.o pci-epf-core.o\
+ pci-epc-mem.o
diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
new file mode 100644
index 0000000..2c33e8a
--- /dev/null
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -0,0 +1,548 @@
+/**
+ * PCI Endpoint *Controller* (EPC) library
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+
+#include <linux/pci-epc.h>
+#include <linux/pci-epf.h>
+
+static struct class *pci_epc_class;
+
+static void devm_pci_epc_release(struct device *dev, void *res)
+{
+ struct pci_epc *epc = *(struct pci_epc **)res;
+
+ pci_epc_destroy(epc);
+}
+
+static int devm_pci_epc_match(struct device *dev, void *res, void *match_data)
+{
+ struct pci_epc **epc = res;
+
+ return *epc == match_data;
+}
+
+/**
+ * pci_epc_get() - get the pci endpoint controller
+ * @epc_name: device name of the endpoint controller
+ *
+ * Invoke to get struct pci_epc * corresponding to the device name of the
+ * endpoint controller
+ */
+struct pci_epc *pci_epc_get(char *epc_name)
+{
+ int ret = -EINVAL;
+ struct pci_epc *epc;
+ struct device *dev;
+ struct class_dev_iter iter;
+
+ class_dev_iter_init(&iter, pci_epc_class, NULL, NULL);
+ while ((dev = class_dev_iter_next(&iter))) {
+ if (strcmp(epc_name, dev_name(dev)))
+ continue;
+
+ epc = to_pci_epc(dev);
+ if (!try_module_get(epc->ops->owner)) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ get_device(&epc->dev);
+ return epc;
+ }
+
+err:
+ class_dev_iter_exit(&iter);
+ return ERR_PTR(ret);
+}
+EXPORT_SYMBOL_GPL(pci_epc_get);
+
+/**
+ * pci_epc_put() - release the pci endpoint controller
+ * @epc: epc returned by pci_epc_get()
+ *
+ * release the refcount the caller obtained by invoking pci_epc_get()
+ */
+void pci_epc_put(struct pci_epc *epc)
+{
+ if (!epc || IS_ERR(epc))
+ return;
+
+ module_put(epc->ops->owner);
+ put_device(&epc->dev);
+}
+EXPORT_SYMBOL_GPL(pci_epc_put);
+
+/**
+ * pci_epc_stop() - stop the PCI link
+ * @epc: the link of the EPC device that has to be stopped
+ *
+ * Invoke to stop the PCI link
+ */
+void pci_epc_stop(struct pci_epc *epc)
+{
+ unsigned long flags;
+
+ if (IS_ERR(epc) || !epc->ops->stop)
+ return;
+
+ spin_lock_irqsave(&epc->lock, flags);
+ epc->ops->stop(epc);
+ spin_unlock_irqrestore(&epc->lock, flags);
+}
+EXPORT_SYMBOL_GPL(pci_epc_stop);
+
+/**
+ * pci_epc_start() - start the PCI link
+ * @epc: the link of *this* EPC device has to be started
+ *
+ * Invoke to start the PCI link
+ */
+int pci_epc_start(struct pci_epc *epc)
+{
+ int ret;
+ unsigned long flags;
+
+ if (IS_ERR(epc))
+ return -EINVAL;
+
+ if (!epc->ops->start)
+ return 0;
+
+ spin_lock_irqsave(&epc->lock, flags);
+ ret = epc->ops->start(epc);
+ spin_unlock_irqrestore(&epc->lock, flags);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pci_epc_start);
+
+/**
+ * pci_epc_raise_irq() - interrupt the host system
+ * @epc: the EPC device which has to interrupt the host
+ * @type: specify the type of interrupt; legacy or MSI
+ * @interrupt_num: the MSI interrupt number
+ *
+ * Invoke to raise an MSI or legacy interrupt
+ */
+int pci_epc_raise_irq(struct pci_epc *epc, enum pci_epc_irq_type type,
+ u8 interrupt_num)
+{
+ int ret;
+ unsigned long flags;
+
+ if (IS_ERR(epc))
+ return -EINVAL;
+
+ if (!epc->ops->raise_irq)
+ return 0;
+
+ spin_lock_irqsave(&epc->lock, flags);
+ ret = epc->ops->raise_irq(epc, type, interrupt_num);
+ spin_unlock_irqrestore(&epc->lock, flags);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pci_epc_raise_irq);
+
+/**
+ * pci_epc_get_msi() - get the number of MSI interrupt numbers allocated
+ * @epc: the EPC device to which MSI interrupts was requested
+ *
+ * Invoke to get the number of MSI interrupts allocated by the RC
+ */
+int pci_epc_get_msi(struct pci_epc *epc)
+{
+ int interrupt;
+ unsigned long flags;
+
+ if (IS_ERR(epc))
+ return 0;
+
+ if (!epc->ops->get_msi)
+ return 0;
+
+ spin_lock_irqsave(&epc->lock, flags);
+ interrupt = epc->ops->get_msi(epc);
+ spin_unlock_irqrestore(&epc->lock, flags);
+
+ if (interrupt < 0)
+ return 0;
+
+ interrupt = 1 << interrupt;
+
+ return interrupt;
+}
+EXPORT_SYMBOL_GPL(pci_epc_get_msi);
+
+/**
+ * pci_epc_set_msi() - set the number of MSI interrupt numbers required
+ * @epc: the EPC device on which MSI has to be configured
+ * @interrupts: number of MSI interrupts required by the EPF
+ *
+ * Invoke to set the required number of MSI interrupts.
+ */
+int pci_epc_set_msi(struct pci_epc *epc, u8 interrupts)
+{
+ int ret;
+ u8 encode_int;
+ unsigned long flags;
+
+ if (IS_ERR(epc))
+ return -EINVAL;
+
+ if (!epc->ops->set_msi)
+ return 0;
+
+ encode_int = order_base_2(interrupts);
+
+ spin_lock_irqsave(&epc->lock, flags);
+ ret = epc->ops->set_msi(epc, encode_int);
+ spin_unlock_irqrestore(&epc->lock, flags);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pci_epc_set_msi);
+
+/**
+ * pci_epc_unmap_addr() - unmap cpu address from pci address
+ * @epc: the EPC device on which address is allocated
+ * @phys_addr: physical address of the local system
+ *
+ * Invoke to unmap the cpu address from pci address.
+ */
+void pci_epc_unmap_addr(struct pci_epc *epc, phys_addr_t phys_addr)
+{
+ unsigned long flags;
+
+ if (IS_ERR(epc))
+ return;
+
+ if (!epc->ops->unmap_addr)
+ return;
+
+ spin_lock_irqsave(&epc->lock, flags);
+ epc->ops->unmap_addr(epc, phys_addr);
+ spin_unlock_irqrestore(&epc->lock, flags);
+}
+EXPORT_SYMBOL_GPL(pci_epc_unmap_addr);
+
+/**
+ * pci_epc_map_addr() - map cpu address to pci address
+ * @epc: the EPC device on which address is allocated
+ * @phys_addr: physical address of the local system
+ * @pci_addr: pci address to which the physical address should be mapped
+ * @size: the size of the allocation
+ *
+ * Invoke to map cpu address with pci address.
+ */
+int pci_epc_map_addr(struct pci_epc *epc, phys_addr_t phys_addr,
+ u64 pci_addr, size_t size)
+{
+ int ret;
+ unsigned long flags;
+
+ if (IS_ERR(epc))
+ return -EINVAL;
+
+ if (!epc->ops->map_addr)
+ return 0;
+
+ spin_lock_irqsave(&epc->lock, flags);
+ ret = epc->ops->map_addr(epc, phys_addr, pci_addr, size);
+ spin_unlock_irqrestore(&epc->lock, flags);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pci_epc_map_addr);
+
+/**
+ * pci_epc_clear_bar() - reset the BAR
+ * @epc: the EPC device for which the BAR has to be cleared
+ * @bar: the bar number that has to be reset
+ *
+ * Invoke to reset the BAR of the endpoint device.
+ */
+void pci_epc_clear_bar(struct pci_epc *epc, int bar)
+{
+ unsigned long flags;
+
+ if (IS_ERR(epc))
+ return;
+
+ if (!epc->ops->clear_bar)
+ return;
+
+ spin_lock_irqsave(&epc->lock, flags);
+ epc->ops->clear_bar(epc, bar);
+ spin_unlock_irqrestore(&epc->lock, flags);
+}
+EXPORT_SYMBOL_GPL(pci_epc_clear_bar);
+
+/**
+ * pci_epc_set_bar() - configure BAR in order for host to assign PCI addr space
+ * @epc: the EPC device on which BAR has to be configured
+ * @bar: the bar number that has to be configured
+ * @size: the size of the addr space
+ * @flags: specify memory allocation/io allocation/32bit address/64 bit address
+ *
+ * Invoke to configure the BAR of the endpoint device.
+ */
+int pci_epc_set_bar(struct pci_epc *epc, enum pci_barno bar,
+ dma_addr_t bar_phys, size_t size, int flags)
+{
+ int ret;
+ unsigned long irq_flags;
+
+ if (IS_ERR(epc))
+ return -EINVAL;
+
+ if (!epc->ops->set_bar)
+ return 0;
+
+ spin_lock_irqsave(&epc->lock, irq_flags);
+ ret = epc->ops->set_bar(epc, bar, bar_phys, size, flags);
+ spin_unlock_irqrestore(&epc->lock, irq_flags);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pci_epc_set_bar);
+
+/**
+ * pci_epc_write_header() - write standard configuration header
+ * @epc: the EPC device to which the configuration header should be written
+ * @header: standard configuration header fields
+ *
+ * Invoke to write the configuration header to the endpoint controller. Every
+ * endpoint controller will have a dedicated location to which the standard
+ * configuration header would be written. The callback function should write
+ * the header fields to this dedicated location.
+ */
+int pci_epc_write_header(struct pci_epc *epc, struct pci_epf_header *header)
+{
+ int ret;
+ unsigned long flags;
+
+ if (IS_ERR(epc))
+ return -EINVAL;
+
+ if (!epc->ops->write_header)
+ return 0;
+
+ spin_lock_irqsave(&epc->lock, flags);
+ ret = epc->ops->write_header(epc, header);
+ spin_unlock_irqrestore(&epc->lock, flags);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pci_epc_write_header);
+
+/**
+ * pci_epc_add_epf() - bind pci endpoint function to an endpoint controller
+ * @epc: the EPC device to which the endpoint function should be added
+ * @epf: the endpoint function to be added
+ *
+ * A PCI endpoint device can have one or more functions. In the case of PCIe,
+ * the specification allows upto 8 PCIe endpoint functions. Invoke
+ * pci_epc_add_epf() to add a pci endpoint function to an endpoint controller.
+ */
+int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf)
+{
+ unsigned long flags;
+
+ if (IS_ERR(epc))
+ return -EINVAL;
+
+ if (epf->func_no > epc->max_functions - 1)
+ return -EINVAL;
+
+ dma_set_coherent_mask(&epf->dev, epc->dev.coherent_dma_mask);
+ epf->dev.dma_mask = epc->dev.dma_mask;
+
+ spin_lock_irqsave(&epc->lock, flags);
+ list_add_tail(&epf->list, &epc->pci_epf);
+ spin_unlock_irqrestore(&epc->lock, flags);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pci_epc_add_epf);
+
+/**
+ * pci_epc_remove_epf() - remove pci endpoint function from endpoint controller
+ * @epc: the EPC device from which the endpoint function should be removed
+ * @epf: the endpoint function to be removed
+ *
+ * Invoke to remove pci endpoint function from the endpoint controller.
+ */
+void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf)
+{
+ unsigned long flags;
+
+ if (!epc || IS_ERR(epc))
+ return;
+
+ spin_lock_irqsave(&epc->lock, flags);
+ list_del(&epf->list);
+ spin_unlock_irqrestore(&epc->lock, flags);
+}
+EXPORT_SYMBOL_GPL(pci_epc_remove_epf);
+
+/**
+ * pci_epc_destroy() - destroy the EPC device
+ * @epc: the EPC device that has to be destroyed
+ *
+ * Invoke to destroy the PCI EPC device
+ */
+void pci_epc_destroy(struct pci_epc *epc)
+{
+ device_unregister(&epc->dev);
+ kfree(epc);
+}
+EXPORT_SYMBOL_GPL(pci_epc_destroy);
+
+/**
+ * devm_pci_epc_destroy() - destroy the EPC device
+ * @dev: device that wants to destroy the EPC
+ * @epc: the EPC device that has to be destroyed
+ *
+ * Invoke to destroy the devres associated with this
+ * pci_epc and destroy the EPC device.
+ */
+void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc)
+{
+ int r;
+
+ r = devres_destroy(dev, devm_pci_epc_release, devm_pci_epc_match,
+ epc);
+ dev_WARN_ONCE(dev, r, "couldn't find PCI EPC resource\n");
+}
+EXPORT_SYMBOL_GPL(devm_pci_epc_destroy);
+
+/**
+ * __pci_epc_create() - create a new endpoint controller (EPC) device
+ * @dev: device that is creating the new EPC
+ * @ops: function pointers for performing EPC operations
+ * @owner: the owner of the module that creates the EPC device
+ *
+ * Invoke to create a new EPC device and add it to pci_epc class.
+ */
+struct pci_epc *
+__pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
+ struct module *owner)
+{
+ int ret;
+ struct pci_epc *epc;
+
+ if (WARN_ON(!dev)) {
+ ret = -EINVAL;
+ goto err_ret;
+ }
+
+ epc = kzalloc(sizeof(*epc), GFP_KERNEL);
+ if (!epc) {
+ ret = -ENOMEM;
+ goto err_ret;
+ }
+
+ spin_lock_init(&epc->lock);
+ INIT_LIST_HEAD(&epc->pci_epf);
+
+ device_initialize(&epc->dev);
+ dma_set_coherent_mask(&epc->dev, dev->coherent_dma_mask);
+ epc->dev.class = pci_epc_class;
+ epc->dev.dma_mask = dev->dma_mask;
+ epc->ops = ops;
+
+ ret = dev_set_name(&epc->dev, "%s", dev_name(dev));
+ if (ret)
+ goto put_dev;
+
+ ret = device_add(&epc->dev);
+ if (ret)
+ goto put_dev;
+
+ return epc;
+
+put_dev:
+ put_device(&epc->dev);
+ kfree(epc);
+
+err_ret:
+ return ERR_PTR(ret);
+}
+EXPORT_SYMBOL_GPL(__pci_epc_create);
+
+/**
+ * __devm_pci_epc_create() - create a new endpoint controller (EPC) device
+ * @dev: device that is creating the new EPC
+ * @ops: function pointers for performing EPC operations
+ * @owner: the owner of the module that creates the EPC device
+ *
+ * Invoke to create a new EPC device and add it to pci_epc class.
+ * While at that, it also associates the device with the pci_epc using devres.
+ * On driver detach, release function is invoked on the devres data,
+ * then, devres data is freed.
+ */
+struct pci_epc *
+__devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
+ struct module *owner)
+{
+ struct pci_epc **ptr, *epc;
+
+ ptr = devres_alloc(devm_pci_epc_release, sizeof(*ptr), GFP_KERNEL);
+ if (!ptr)
+ return ERR_PTR(-ENOMEM);
+
+ epc = __pci_epc_create(dev, ops, owner);
+ if (!IS_ERR(epc)) {
+ *ptr = epc;
+ devres_add(dev, ptr);
+ } else {
+ devres_free(ptr);
+ }
+
+ return epc;
+}
+EXPORT_SYMBOL_GPL(__devm_pci_epc_create);
+
+static int __init pci_epc_init(void)
+{
+ pci_epc_class = class_create(THIS_MODULE, "pci_epc");
+ if (IS_ERR(pci_epc_class)) {
+ pr_err("failed to create pci epc class --> %ld\n",
+ PTR_ERR(pci_epc_class));
+ return PTR_ERR(pci_epc_class);
+ }
+
+ return 0;
+}
+module_init(pci_epc_init);
+
+static void __exit pci_epc_exit(void)
+{
+ class_destroy(pci_epc_class);
+}
+module_exit(pci_epc_exit);
+
+MODULE_DESCRIPTION("PCI EPC Library");
+MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pci/endpoint/pci-epc-mem.c b/drivers/pci/endpoint/pci-epc-mem.c
new file mode 100644
index 0000000..3a94cc1
--- /dev/null
+++ b/drivers/pci/endpoint/pci-epc-mem.c
@@ -0,0 +1,143 @@
+/**
+ * PCI Endpoint *Controller* Address Space Management
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+
+#include <linux/pci-epc.h>
+
+/**
+ * pci_epc_mem_init() - initialize the pci_epc_mem structure
+ * @epc: the EPC device that invoked pci_epc_mem_init
+ * @phys_base: the physical address of the base
+ * @size: the size of the address space
+ *
+ * Invoke to initialize the pci_epc_mem structure used by the
+ * endpoint functions to allocate mapped PCI address.
+ */
+int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_base, size_t size)
+{
+ int ret;
+ struct pci_epc_mem *mem;
+ unsigned long *bitmap;
+ int pages = size >> PAGE_SHIFT;
+ int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
+
+ mem = kzalloc(sizeof(*mem), GFP_KERNEL);
+ if (!mem) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ bitmap = kzalloc(bitmap_size, GFP_KERNEL);
+ if (!bitmap) {
+ ret = -ENOMEM;
+ goto err_mem;
+ }
+
+ mem->bitmap = bitmap;
+ mem->phys_base = phys_base;
+ mem->pages = pages;
+ mem->size = size;
+
+ epc->mem = mem;
+
+ return 0;
+
+err_mem:
+ kfree(mem);
+
+err:
+return ret;
+}
+EXPORT_SYMBOL_GPL(pci_epc_mem_init);
+
+/**
+ * pci_epc_mem_exit() - cleanup the pci_epc_mem structure
+ * @epc: the EPC device that invoked pci_epc_mem_exit
+ *
+ * Invoke to cleanup the pci_epc_mem structure allocated in
+ * pci_epc_mem_init().
+ */
+void pci_epc_mem_exit(struct pci_epc *epc)
+{
+ struct pci_epc_mem *mem = epc->mem;
+
+ epc->mem = NULL;
+ kfree(mem->bitmap);
+ kfree(mem);
+}
+EXPORT_SYMBOL_GPL(pci_epc_mem_exit);
+
+/**
+ * pci_epc_mem_alloc_addr() - allocate memory address from EPC addr space
+ * @epc: the EPC device on which memory has to be allocated
+ * @phys_addr: populate the allocated physical address here
+ * @size: the size of the address space that has to be allocated
+ *
+ * Invoke to allocate memory address from the EPC address space. This
+ * is usually done to map the remote RC address into the local system.
+ */
+void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
+ phys_addr_t *phys_addr, size_t size)
+{
+ int pageno;
+ void __iomem *virt_addr;
+ struct pci_epc_mem *mem = epc->mem;
+ int order = get_order(size);
+
+ pageno = bitmap_find_free_region(mem->bitmap, mem->pages, order);
+ if (pageno < 0)
+ return NULL;
+
+ *phys_addr = mem->phys_base + (pageno << PAGE_SHIFT);
+ virt_addr = ioremap(*phys_addr, size);
+ if (!virt_addr)
+ bitmap_release_region(mem->bitmap, pageno, order);
+
+ return virt_addr;
+}
+EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr);
+
+/**
+ * pci_epc_mem_free_addr() - free the allocated memory address
+ * @epc: the EPC device on which memory was allocated
+ * @phys_addr: the allocated physical address
+ * @virt_addr: virtual address of the allocated mem space
+ * @size: the size of the allocated address space
+ *
+ * Invoke to free the memory allocated using pci_epc_mem_alloc_addr.
+ */
+void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
+ void __iomem *virt_addr, size_t size)
+{
+ int pageno;
+ int order = get_order(size);
+ struct pci_epc_mem *mem = epc->mem;
+
+ iounmap(virt_addr);
+ pageno = (phys_addr - mem->phys_base) >> PAGE_SHIFT;
+ bitmap_release_region(mem->bitmap, pageno, order);
+}
+EXPORT_SYMBOL_GPL(pci_epc_mem_free_addr);
+
+MODULE_DESCRIPTION("PCI EPC Address Space Management");
+MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c
new file mode 100644
index 0000000..4c903fc
--- /dev/null
+++ b/drivers/pci/endpoint/pci-epf-core.c
@@ -0,0 +1,347 @@
+/**
+ * PCI Endpoint *Function* (EPF) library
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+
+#include <linux/pci-epc.h>
+#include <linux/pci-epf.h>
+
+static struct bus_type pci_epf_bus_type;
+static struct device_type pci_epf_type;
+
+/**
+ * pci_epf_linkup() - Notify the function driver that EPC device has
+ * established a connection with the Root Complex.
+ * @epf: the EPF device bound to the EPC device which has established
+ * the connection with the host
+ *
+ * Invoke to notify the function driver that EPC device has established
+ * a connection with the Root Complex.
+ */
+void pci_epf_linkup(struct pci_epf *epf)
+{
+ if (!epf->driver)
+ dev_WARN(&epf->dev, "epf device not bound to driver\n");
+
+ epf->driver->ops->linkup(epf);
+}
+EXPORT_SYMBOL_GPL(pci_epf_linkup);
+
+/**
+ * pci_epf_unbind() - Notify the function driver that the binding between the
+ * EPF device and EPC device has been lost
+ * @epf: the EPF device which has lost the binding with the EPC device
+ *
+ * Invoke to notify the function driver that the binding between the EPF device
+ * and EPC device has been lost.
+ */
+void pci_epf_unbind(struct pci_epf *epf)
+{
+ if (!epf->driver)
+ dev_WARN(&epf->dev, "epf device not bound to driver\n");
+
+ epf->driver->ops->unbind(epf);
+ module_put(epf->driver->owner);
+}
+EXPORT_SYMBOL_GPL(pci_epf_unbind);
+
+/**
+ * pci_epf_bind() - Notify the function driver that the EPF device has been
+ * bound to a EPC device
+ * @epf: the EPF device which has been bound to the EPC device
+ *
+ * Invoke to notify the function driver that it has been bound to a EPC device
+ */
+int pci_epf_bind(struct pci_epf *epf)
+{
+ if (!epf->driver)
+ dev_WARN(&epf->dev, "epf device not bound to driver\n");
+
+ if (!try_module_get(epf->driver->owner))
+ return -EAGAIN;
+
+ return epf->driver->ops->bind(epf);
+}
+EXPORT_SYMBOL_GPL(pci_epf_bind);
+
+/**
+ * pci_epf_free_space() - free the allocated PCI EPF register space
+ * @addr: the virtual address of the PCI EPF register space
+ * @bar: the bar number corresponding to the register space
+ *
+ * Invoke to free the allocated PCI EPF register space.
+ */
+void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar)
+{
+ struct device *dev = &epf->dev;
+
+ if (!addr)
+ return;
+
+ dma_free_coherent(dev, epf->bar[bar].size, addr,
+ epf->bar[bar].phys_addr);
+
+ epf->bar[bar].phys_addr = 0;
+ epf->bar[bar].size = 0;
+}
+EXPORT_SYMBOL_GPL(pci_epf_free_space);
+
+/**
+ * pci_epf_alloc_space() - allocate memory for the PCI EPF register space
+ * @size: the size of the memory that has to be allocated
+ * @bar: the bar number corresponding to the allocated register space
+ *
+ * Invoke to allocate memory for the PCI EPF register space.
+ */
+void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar)
+{
+ void *space;
+ struct device *dev = &epf->dev;
+ dma_addr_t phys_addr;
+
+ if (size < 128)
+ size = 128;
+ size = roundup_pow_of_two(size);
+
+ space = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL);
+ if (!space) {
+ dev_err(dev, "failed to allocate mem space\n");
+ return NULL;
+ }
+
+ epf->bar[bar].phys_addr = phys_addr;
+ epf->bar[bar].size = size;
+
+ return space;
+}
+EXPORT_SYMBOL_GPL(pci_epf_alloc_space);
+
+/**
+ * pci_epf_unregister_driver() - unregister the PCI EPF driver
+ * @driver: the PCI EPF driver that has to be unregistered
+ *
+ * Invoke to unregister the PCI EPF driver.
+ */
+void pci_epf_unregister_driver(struct pci_epf_driver *driver)
+{
+ driver_unregister(&driver->driver);
+}
+EXPORT_SYMBOL_GPL(pci_epf_unregister_driver);
+
+/**
+ * __pci_epf_register_driver() - register a new PCI EPF driver
+ * @driver: structure representing PCI EPF driver
+ * @owner: the owner of the module that registers the PCI EPF driver
+ *
+ * Invoke to register a new PCI EPF driver.
+ */
+int __pci_epf_register_driver(struct pci_epf_driver *driver,
+ struct module *owner)
+{
+ int ret;
+
+ if (!driver->ops)
+ return -EINVAL;
+
+ if (!driver->ops->bind || !driver->ops->unbind || !driver->ops->linkup)
+ return -EINVAL;
+
+ driver->driver.bus = &pci_epf_bus_type;
+ driver->driver.owner = owner;
+
+ ret = driver_register(&driver->driver);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(__pci_epf_register_driver);
+
+/**
+ * pci_epf_destroy() - destroy the created PCI EPF device
+ * @epf: the PCI EPF device that has to be destroyed.
+ *
+ * Invoke to destroy the PCI EPF device created by invoking pci_epf_create().
+ */
+void pci_epf_destroy(struct pci_epf *epf)
+{
+ device_unregister(&epf->dev);
+}
+EXPORT_SYMBOL_GPL(pci_epf_destroy);
+
+/**
+ * pci_epf_create() - create a new PCI EPF device
+ * @name: the name of the PCI EPF device. This name will be used to bind the
+ * the EPF device to a EPF driver
+ *
+ * Invoke to create a new PCI EPF device by providing the name of the function
+ * device.
+ */
+struct pci_epf *pci_epf_create(const char *name)
+{
+ int ret;
+ struct pci_epf *epf;
+ struct device *dev;
+ char *func_name;
+ char *buf;
+
+ epf = kzalloc(sizeof(*epf), GFP_KERNEL);
+ if (!epf) {
+ ret = -ENOMEM;
+ goto err_ret;
+ }
+
+ buf = kstrdup(name, GFP_KERNEL);
+ if (!buf) {
+ ret = -ENOMEM;
+ goto free_epf;
+ }
+
+ func_name = buf;
+ buf = strchrnul(buf, '.');
+ *buf = '\0';
+
+ epf->name = kstrdup(func_name, GFP_KERNEL);
+ if (!epf->name) {
+ ret = -ENOMEM;
+ goto free_epf;
+ }
+
+ dev = &epf->dev;
+ device_initialize(dev);
+ dev->bus = &pci_epf_bus_type;
+ dev->type = &pci_epf_type;
+
+ ret = dev_set_name(dev, "%s", name);
+ if (ret)
+ goto put_dev;
+
+ ret = device_add(dev);
+ if (ret)
+ goto put_dev;
+
+ kfree(func_name);
+ return epf;
+
+put_dev:
+ put_device(dev);
+ kfree(epf->name);
+ kfree(func_name);
+
+free_epf:
+ kfree(epf);
+
+err_ret:
+ return ERR_PTR(ret);
+}
+EXPORT_SYMBOL_GPL(pci_epf_create);
+
+static void pci_epf_dev_release(struct device *dev)
+{
+ struct pci_epf *epf = to_pci_epf(dev);
+
+ kfree(epf->name);
+ kfree(epf);
+}
+
+static struct device_type pci_epf_type = {
+ .release = pci_epf_dev_release,
+};
+
+static int
+pci_epf_match_id(const struct pci_epf_device_id *id, const struct pci_epf *epf)
+{
+ while (id->name[0]) {
+ if (strcmp(epf->name, id->name) == 0)
+ return true;
+ id++;
+ }
+
+ return false;
+}
+
+static int pci_epf_device_match(struct device *dev, struct device_driver *drv)
+{
+ struct pci_epf *epf = to_pci_epf(dev);
+ struct pci_epf_driver *driver = to_pci_epf_driver(drv);
+
+ if (driver->id_table)
+ return pci_epf_match_id(driver->id_table, epf);
+
+ return !strcmp(epf->name, drv->name);
+}
+
+static int pci_epf_device_probe(struct device *dev)
+{
+ struct pci_epf *epf = to_pci_epf(dev);
+ struct pci_epf_driver *driver = to_pci_epf_driver(dev->driver);
+
+ if (!driver->probe)
+ return -ENODEV;
+
+ epf->driver = driver;
+
+ return driver->probe(epf);
+}
+
+static int pci_epf_device_remove(struct device *dev)
+{
+ int ret;
+ struct pci_epf *epf = to_pci_epf(dev);
+ struct pci_epf_driver *driver = to_pci_epf_driver(dev->driver);
+
+ ret = driver->remove(epf);
+ epf->driver = NULL;
+
+ return ret;
+}
+
+static struct bus_type pci_epf_bus_type = {
+ .name = "pci-epf",
+ .match = pci_epf_device_match,
+ .probe = pci_epf_device_probe,
+ .remove = pci_epf_device_remove,
+};
+
+static int __init pci_epf_init(void)
+{
+ int ret;
+
+ ret = bus_register(&pci_epf_bus_type);
+ if (ret) {
+ pr_err("failed to register pci epf bus --> %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+module_init(pci_epf_init);
+
+static void __exit pci_epf_exit(void)
+{
+ bus_unregister(&pci_epf_bus_type);
+}
+module_exit(pci_epf_exit);
+
+MODULE_DESCRIPTION("PCI EPF Library");
+MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index 8a57f0b..bf706c1 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -428,6 +428,16 @@ struct i2c_device_id {
kernel_ulong_t driver_data; /* Data private to the driver */
};
+/* pci_epf */
+
+#define PCI_EPF_NAME_SIZE 20
+#define PCI_EPF_MODULE_PREFIX "pci_epf:"
+
+struct pci_epf_device_id {
+ char name[PCI_EPF_NAME_SIZE];
+ kernel_ulong_t driver_data;
+};
+
/* spi */
#define SPI_NAME_SIZE 32
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
new file mode 100644
index 0000000..b62f39d
--- /dev/null
+++ b/include/linux/pci-epc.h
@@ -0,0 +1,141 @@
+/**
+ * PCI Endpoint *Controller* (EPC) header file
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_PCI_EPC_H
+#define __LINUX_PCI_EPC_H
+
+#include <linux/pci-epf.h>
+
+struct pci_epc;
+
+enum pci_epc_irq_type {
+ PCI_EPC_IRQ_UNKNOWN,
+ PCI_EPC_IRQ_LEGACY,
+ PCI_EPC_IRQ_MSI,
+};
+
+/**
+ * struct pci_epc_ops - set of function pointers for performing EPC operations
+ * @write_header: ops to populate configuration space header
+ * @set_bar: ops to configure the BAR
+ * @clear_bar: ops to reset the BAR
+ * @map_addr: ops to map cpu address to pci address
+ * @unmap_addr: ops to unmap cpu address and pci address
+ * @set_msi: ops to set the requested number of MSI interrupts in the MSI
+ * capability register
+ * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
+ * the MSI capability register
+ * @raise_irq: ops to raise a legacy or MSI interrupt
+ * @start: ops to start the PCI link
+ * @stop: ops to stop the PCI link
+ * @owner: the module owner containing the ops
+ */
+struct pci_epc_ops {
+ int (*write_header)(struct pci_epc *pci_epc,
+ struct pci_epf_header *hdr);
+ int (*set_bar)(struct pci_epc *epc, enum pci_barno bar,
+ dma_addr_t bar_phys, size_t size, int flags);
+ void (*clear_bar)(struct pci_epc *epc, enum pci_barno bar);
+ int (*map_addr)(struct pci_epc *epc, phys_addr_t addr,
+ u64 pci_addr, size_t size);
+ void (*unmap_addr)(struct pci_epc *epc, phys_addr_t addr);
+ int (*set_msi)(struct pci_epc *epc, u8 interrupts);
+ int (*get_msi)(struct pci_epc *epc);
+ int (*raise_irq)(struct pci_epc *pci_epc,
+ enum pci_epc_irq_type type, u8 interrupt_num);
+ int (*start)(struct pci_epc *epc);
+ void (*stop)(struct pci_epc *epc);
+ struct module *owner;
+};
+
+/**
+ * struct pci_epc_mem - address space of the endpoint controller
+ * @phys_base: physical base address of the pci address space
+ * @size: the size of the pci address space
+ * @bitmap: bitmap to manage the pci address space
+ * @pages: number of bits representing the address region
+ */
+struct pci_epc_mem {
+ phys_addr_t phys_base;
+ size_t size;
+ unsigned long *bitmap;
+ int pages;
+};
+
+/**
+ * struct pci_epc - represents the PCI EPC device
+ * @dev: PCI EPC device
+ * @pci_epf: list of endpoint functions present in this EPC device
+ * @ops: function pointers for performing endpoint operations
+ * @mem: address space of the endpoint controller
+ * @max_functions: max number of functions that can be configured in this EPC
+ * @lock: spinlock to protect pci_epc ops
+ */
+struct pci_epc {
+ struct device dev;
+ struct list_head pci_epf;
+ const struct pci_epc_ops *ops;
+ struct pci_epc_mem *mem;
+ u8 max_functions;
+ /* spinlock to protect against concurrent access of EP controller */
+ spinlock_t lock;
+};
+
+#define to_pci_epc(device) container_of((device), struct pci_epc, dev)
+
+#define pci_epc_create(dev, ops) \
+ __pci_epc_create((dev), (ops), THIS_MODULE)
+#define devm_pci_epc_create(dev, ops) \
+ __devm_pci_epc_create((dev), (ops), THIS_MODULE)
+
+static inline void epc_set_drvdata(struct pci_epc *epc, void *data)
+{
+ dev_set_drvdata(&epc->dev, data);
+}
+
+static inline void *epc_get_drvdata(struct pci_epc *epc)
+{
+ return dev_get_drvdata(&epc->dev);
+}
+
+struct pci_epc *
+__devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
+ struct module *owner);
+struct pci_epc *
+__pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
+ struct module *owner);
+void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc);
+void pci_epc_destroy(struct pci_epc *epc);
+int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf);
+void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf);
+int pci_epc_write_header(struct pci_epc *epc, struct pci_epf_header *hdr);
+int pci_epc_set_bar(struct pci_epc *epc, enum pci_barno bar,
+ dma_addr_t bar_phys, size_t size, int flags);
+void pci_epc_clear_bar(struct pci_epc *epc, int bar);
+int pci_epc_map_addr(struct pci_epc *epc, phys_addr_t phys_addr,
+ u64 pci_addr, size_t size);
+void pci_epc_unmap_addr(struct pci_epc *epc, phys_addr_t phys_addr);
+int pci_epc_set_msi(struct pci_epc *epc, u8 interrupts);
+int pci_epc_get_msi(struct pci_epc *epc);
+int pci_epc_raise_irq(struct pci_epc *epc, enum pci_epc_irq_type type,
+ u8 interrupt_num);
+int pci_epc_start(struct pci_epc *epc);
+void pci_epc_stop(struct pci_epc *epc);
+struct pci_epc *pci_epc_get(char *epc_name);
+void pci_epc_put(struct pci_epc *epc);
+
+int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_addr, size_t size);
+void pci_epc_mem_exit(struct pci_epc *epc);
+void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
+ phys_addr_t *phys_addr, size_t size);
+void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
+ void __iomem *virt_addr, size_t size);
+#endif /* __LINUX_PCI_EPC_H */
diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h
new file mode 100644
index 0000000..54f1338
--- /dev/null
+++ b/include/linux/pci-epf.h
@@ -0,0 +1,160 @@
+/**
+ * PCI Endpoint *Function* (EPF) header file
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_PCI_EPF_H
+#define __LINUX_PCI_EPF_H
+
+#include <linux/device.h>
+#include <linux/mod_devicetable.h>
+
+struct pci_epf;
+
+enum pci_interrupt_pin {
+ PCI_INTERRUPT_UNKNOWN,
+ PCI_INTERRUPT_INTA,
+ PCI_INTERRUPT_INTB,
+ PCI_INTERRUPT_INTC,
+ PCI_INTERRUPT_INTD,
+};
+
+enum pci_barno {
+ BAR_0,
+ BAR_1,
+ BAR_2,
+ BAR_3,
+ BAR_4,
+ BAR_5,
+};
+
+/**
+ * struct pci_epf_header - represents standard configuration header
+ * @vendorid: identifies device manufacturer
+ * @deviceid: identifies a particular device
+ * @revid: specifies a device specific revision identifier
+ * @progif_code: identifies a specific register-level programming interface
+ * @subclass_code: identifies more specifically the function of the device
+ * @baseclass_code: broadly classifies the type of function the device performs
+ * @cache_line_size: specifies the system cacheline size in units of DWORDs
+ * @subsys_vendor_id: vendor of the add-in card or subsystem
+ * @subsys_id: id specific to vendor
+ * @interrupt_pin: interrupt pin the device (or device function) uses
+ */
+struct pci_epf_header {
+ u16 vendorid;
+ u16 deviceid;
+ u8 revid;
+ u8 progif_code;
+ u8 subclass_code;
+ u8 baseclass_code;
+ u8 cache_line_size;
+ u16 subsys_vendor_id;
+ u16 subsys_id;
+ enum pci_interrupt_pin interrupt_pin;
+};
+
+/**
+ * struct pci_epf_ops - set of function pointers for performing EPF operations
+ * @bind: ops to perform when a EPC device has been bound to EPF device
+ * @unbind: ops to perform when a binding has been lost between a EPC device
+ * and EPF device
+ * @linkup: ops to perform when the EPC device has established a connection with
+ * a host system
+ */
+struct pci_epf_ops {
+ int (*bind)(struct pci_epf *epf);
+ void (*unbind)(struct pci_epf *epf);
+ void (*linkup)(struct pci_epf *epf);
+};
+
+/**
+ * struct pci_epf_driver - represents the PCI EPF driver
+ * @probe: ops to perform when a new EPF device has been bound to the EPF driver
+ * @remove: ops to perform when the binding between the EPF device and EPF
+ * driver is broken
+ * @driver: PCI EPF driver
+ * @ops: set of function pointers for performing EPF operations
+ * @owner: the owner of the module that registers the PCI EPF driver
+ * @id_table: identifies EPF devices for probing
+ */
+struct pci_epf_driver {
+ int (*probe)(struct pci_epf *epf);
+ int (*remove)(struct pci_epf *epf);
+
+ struct device_driver driver;
+ struct pci_epf_ops *ops;
+ struct module *owner;
+ const struct pci_epf_device_id *id_table;
+};
+
+#define to_pci_epf_driver(drv) (container_of((drv), struct pci_epf_driver, \
+ driver))
+
+/**
+ * struct pci_epf_bar - represents the BAR of EPF device
+ * @phys_addr: physical address that should be mapped to the BAR
+ * @size: the size of the address space present in BAR
+ */
+struct pci_epf_bar {
+ dma_addr_t phys_addr;
+ size_t size;
+};
+
+/**
+ * struct pci_epf - represents the PCI EPF device
+ * @dev: the PCI EPF device
+ * @name: the name of the PCI EPF device
+ * @header: represents standard configuration header
+ * @bar: represents the BAR of EPF device
+ * @msi_interrupts: number of msi interrupts required by this function
+ * @func_no: unique function number within this endpoint device
+ * @epc: the EPC device to which this EPF device is bound
+ * @driver: the EPF driver to which this EPF device is bound
+ * @list: to add pci_epf as a list of pci endpoint functions to pci_epc
+ */
+struct pci_epf {
+ struct device dev;
+ const char *name;
+ struct pci_epf_header *header;
+ struct pci_epf_bar bar[6];
+ u8 msi_interrupts;
+ u8 func_no;
+
+ struct pci_epc *epc;
+ struct pci_epf_driver *driver;
+ struct list_head list;
+};
+
+#define to_pci_epf(epf_dev) container_of((epf_dev), struct pci_epf, dev)
+
+#define pci_epf_register_driver(driver) \
+ __pci_epf_register_driver((driver), THIS_MODULE)
+
+static inline void epf_set_drvdata(struct pci_epf *epf, void *data)
+{
+ dev_set_drvdata(&epf->dev, data);
+}
+
+static inline void *epf_get_drvdata(struct pci_epf *epf)
+{
+ return dev_get_drvdata(&epf->dev);
+}
+
+struct pci_epf *pci_epf_create(const char *name);
+void pci_epf_destroy(struct pci_epf *epf);
+int __pci_epf_register_driver(struct pci_epf_driver *driver,
+ struct module *owner);
+void pci_epf_unregister_driver(struct pci_epf_driver *driver);
+void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar);
+void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar);
+int pci_epf_bind(struct pci_epf *epf);
+void pci_epf_unbind(struct pci_epf *epf);
+void pci_epf_linkup(struct pci_epf *epf);
+#endif /* __LINUX_PCI_EPF_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 49+ messages in thread* Re: [PATCH v2 01/22] PCI: endpoint: Add EP core layer to enable EP controller and EP functions
2017-02-17 9:50 ` [PATCH v2 01/22] PCI: endpoint: Add EP core layer to enable EP controller and EP functions Kishon Vijay Abraham I
@ 2017-02-17 11:26 ` Joao Pinto
2017-02-17 11:37 ` Kishon Vijay Abraham I
0 siblings, 1 reply; 49+ messages in thread
From: Joao Pinto @ 2017-02-17 11:26 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
linux-omap, linux-arm-kernel
Hi Kishon,
=C0s 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
> Introduce a new EP core layer in order to support endpoint functions
> in linux kernel. This comprises of EPC library
> (Endpoint Controller Library) and EPF library (Endpoint
> Function Library). EPC library implements functions that is specific
> to an endpoint controller and EPF library implements functions
> that is specific to an endpoint function.
> =
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/Makefile | 2 +
> drivers/pci/Kconfig | 1 +
> drivers/pci/endpoint/Kconfig | 21 ++
> drivers/pci/endpoint/Makefile | 6 +
> drivers/pci/endpoint/pci-epc-core.c | 548 +++++++++++++++++++++++++++++=
++++++
> drivers/pci/endpoint/pci-epc-mem.c | 143 +++++++++
> drivers/pci/endpoint/pci-epf-core.c | 347 ++++++++++++++++++++++
> include/linux/mod_devicetable.h | 10 +
> include/linux/pci-epc.h | 141 +++++++++
> include/linux/pci-epf.h | 160 ++++++++++
> 10 files changed, 1379 insertions(+)
> create mode 100644 drivers/pci/endpoint/Kconfig
> create mode 100644 drivers/pci/endpoint/Makefile
> create mode 100644 drivers/pci/endpoint/pci-epc-core.c
> create mode 100644 drivers/pci/endpoint/pci-epc-mem.c
> create mode 100644 drivers/pci/endpoint/pci-epf-core.c
> create mode 100644 include/linux/pci-epc.h
> create mode 100644 include/linux/pci-epf.h
> =
> diff --git a/drivers/Makefile b/drivers/Makefile
> index f521cb0..a300bb1 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -14,7 +14,9 @@ obj-$(CONFIG_GENERIC_PHY) +=3D phy/
> obj-$(CONFIG_PINCTRL) +=3D pinctrl/
> obj-$(CONFIG_GPIOLIB) +=3D gpio/
> obj-y +=3D pwm/
> +
> obj-$(CONFIG_PCI) +=3D pci/
> +obj-$(CONFIG_PCI_ENDPOINT) +=3D pci/endpoint/
> # PCI dwc controller drivers
> obj-y +=3D pci/dwc/
Any special reason to include pci/endpoint and pci/dwc in drivers/Makefile
instead of being inside pci/Makefile? pci/host is still inside pci/Makefile.
> =
> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> index df14142..9747c1e 100644
> --- a/drivers/pci/Kconfig
> +++ b/drivers/pci/Kconfig
> @@ -134,3 +134,4 @@ config PCI_HYPERV
> source "drivers/pci/hotplug/Kconfig"
> source "drivers/pci/dwc/Kconfig"
> source "drivers/pci/host/Kconfig"
> +source "drivers/pci/endpoint/Kconfig"
> diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig
> new file mode 100644
> index 0000000..7eb1c79
> --- /dev/null
> +++ b/drivers/pci/endpoint/Kconfig
> @@ -0,0 +1,21 @@
> +#
> +# PCI Endpoint Support
> +#
> +
> +menu "PCI Endpoint"
> +
> +config PCI_ENDPOINT
> + bool "PCI Endpoint Support"
> + select CONFIGFS_FS
> + help
> + Enable this configuration option to support configurable PCI
> + endpoint. This should be enabled if the platform has a PCI
> + controller that can operate in endpoint mode.
> +
> + Enabling this option will build the endpoint library, which
> + includes endpoint controller library and endpoint function
> + library.
> +
> + If in doubt, say "N" to disable Endpoint support.
> +
> +endmenu
> diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile
> new file mode 100644
> index 0000000..dc1bc16
> --- /dev/null
> +++ b/drivers/pci/endpoint/Makefile
> @@ -0,0 +1,6 @@
> +#
> +# Makefile for PCI Endpoint Support
> +#
> +
> +obj-$(CONFIG_PCI_ENDPOINT) +=3D pci-epc-core.o pci-epf-core.o\
> + pci-epc-mem.o
> diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/p=
ci-epc-core.c
> new file mode 100644
> index 0000000..2c33e8a
> --- /dev/null
> +++ b/drivers/pci/endpoint/pci-epc-core.c
> @@ -0,0 +1,548 @@
> +/**
> + * PCI Endpoint *Controller* (EPC) library
> + *
> + * Copyright (C) 2017 Texas Instruments
> + * Author: Kishon Vijay Abraham I <kishon@ti.com>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 of
> + * the License as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <https://urldefense.proofpoint.=
com/v2/url?u=3Dhttp-3A__www.gnu.org_licenses_&d=3DDwIBAg&c=3DDPL6_X_6JkXFx7=
AXWqB0tg&r=3Ds2fO0hii0OGNOv9qQy_HRXy-xAJUD1NNoEcc3io_kx0&m=3DswFEoYaziG2Fdc=
vbq0MAtOjv2PLxgqEMssA9yjQVqXI&s=3DibUotwnXH20Q3a_vRJYtFUvGbSQN_43xAmUcsQ4FN=
vo&e=3D >.
> + */
> +
> +#include <linux/device.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/slab.h>
> +#include <linux/module.h>
> +
> +#include <linux/pci-epc.h>
> +#include <linux/pci-epf.h>
> +
> +static struct class *pci_epc_class;
> +
> +static void devm_pci_epc_release(struct device *dev, void *res)
> +{
> + struct pci_epc *epc =3D *(struct pci_epc **)res;
> +
> + pci_epc_destroy(epc);
> +}
> +
> +static int devm_pci_epc_match(struct device *dev, void *res, void *match=
_data)
> +{
> + struct pci_epc **epc =3D res;
> +
> + return *epc =3D=3D match_data;
> +}
> +
> +/**
> + * pci_epc_get() - get the pci endpoint controller
> + * @epc_name: device name of the endpoint controller
> + *
> + * Invoke to get struct pci_epc * corresponding to the device name of the
> + * endpoint controller
> + */
> +struct pci_epc *pci_epc_get(char *epc_name)
> +{
> + int ret =3D -EINVAL;
> + struct pci_epc *epc;
> + struct device *dev;
> + struct class_dev_iter iter;
> +
> + class_dev_iter_init(&iter, pci_epc_class, NULL, NULL);
> + while ((dev =3D class_dev_iter_next(&iter))) {
> + if (strcmp(epc_name, dev_name(dev)))
> + continue;
> +
> + epc =3D to_pci_epc(dev);
> + if (!try_module_get(epc->ops->owner)) {
> + ret =3D -EINVAL;
> + goto err;
> + }
> +
> + get_device(&epc->dev);
> + return epc;
> + }
> +
> +err:
> + class_dev_iter_exit(&iter);
> + return ERR_PTR(ret);
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_get);
> +
> +/**
> + * pci_epc_put() - release the pci endpoint controller
> + * @epc: epc returned by pci_epc_get()
> + *
> + * release the refcount the caller obtained by invoking pci_epc_get()
> + */
> +void pci_epc_put(struct pci_epc *epc)
> +{
> + if (!epc || IS_ERR(epc))
> + return;
> +
> + module_put(epc->ops->owner);
> + put_device(&epc->dev);
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_put);
> +
> +/**
> + * pci_epc_stop() - stop the PCI link
> + * @epc: the link of the EPC device that has to be stopped
> + *
> + * Invoke to stop the PCI link
> + */
> +void pci_epc_stop(struct pci_epc *epc)
> +{
> + unsigned long flags;
> +
> + if (IS_ERR(epc) || !epc->ops->stop)
> + return;
> +
> + spin_lock_irqsave(&epc->lock, flags);
> + epc->ops->stop(epc);
> + spin_unlock_irqrestore(&epc->lock, flags);
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_stop);
> +
> +/**
> + * pci_epc_start() - start the PCI link
> + * @epc: the link of *this* EPC device has to be started
> + *
> + * Invoke to start the PCI link
> + */
> +int pci_epc_start(struct pci_epc *epc)
> +{
> + int ret;
> + unsigned long flags;
> +
> + if (IS_ERR(epc))
> + return -EINVAL;
> +
> + if (!epc->ops->start)
> + return 0;
> +
> + spin_lock_irqsave(&epc->lock, flags);
> + ret =3D epc->ops->start(epc);
> + spin_unlock_irqrestore(&epc->lock, flags);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_start);
> +
> +/**
> + * pci_epc_raise_irq() - interrupt the host system
> + * @epc: the EPC device which has to interrupt the host
> + * @type: specify the type of interrupt; legacy or MSI
> + * @interrupt_num: the MSI interrupt number
> + *
> + * Invoke to raise an MSI or legacy interrupt
> + */
> +int pci_epc_raise_irq(struct pci_epc *epc, enum pci_epc_irq_type type,
> + u8 interrupt_num)
> +{
> + int ret;
> + unsigned long flags;
> +
> + if (IS_ERR(epc))
> + return -EINVAL;
> +
> + if (!epc->ops->raise_irq)
> + return 0;
> +
> + spin_lock_irqsave(&epc->lock, flags);
> + ret =3D epc->ops->raise_irq(epc, type, interrupt_num);
> + spin_unlock_irqrestore(&epc->lock, flags);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_raise_irq);
> +
> +/**
> + * pci_epc_get_msi() - get the number of MSI interrupt numbers allocated
> + * @epc: the EPC device to which MSI interrupts was requested
> + *
> + * Invoke to get the number of MSI interrupts allocated by the RC
> + */
> +int pci_epc_get_msi(struct pci_epc *epc)
> +{
> + int interrupt;
> + unsigned long flags;
> +
> + if (IS_ERR(epc))
> + return 0;
> +
> + if (!epc->ops->get_msi)
> + return 0;
> +
> + spin_lock_irqsave(&epc->lock, flags);
> + interrupt =3D epc->ops->get_msi(epc);
> + spin_unlock_irqrestore(&epc->lock, flags);
> +
> + if (interrupt < 0)
> + return 0;
> +
> + interrupt =3D 1 << interrupt;
> +
> + return interrupt;
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_get_msi);
> +
> +/**
> + * pci_epc_set_msi() - set the number of MSI interrupt numbers required
> + * @epc: the EPC device on which MSI has to be configured
> + * @interrupts: number of MSI interrupts required by the EPF
> + *
> + * Invoke to set the required number of MSI interrupts.
> + */
> +int pci_epc_set_msi(struct pci_epc *epc, u8 interrupts)
> +{
> + int ret;
> + u8 encode_int;
> + unsigned long flags;
> +
> + if (IS_ERR(epc))
> + return -EINVAL;
> +
> + if (!epc->ops->set_msi)
> + return 0;
> +
> + encode_int =3D order_base_2(interrupts);
> +
> + spin_lock_irqsave(&epc->lock, flags);
> + ret =3D epc->ops->set_msi(epc, encode_int);
> + spin_unlock_irqrestore(&epc->lock, flags);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_set_msi);
> +
> +/**
> + * pci_epc_unmap_addr() - unmap cpu address from pci address
> + * @epc: the EPC device on which address is allocated
> + * @phys_addr: physical address of the local system
> + *
> + * Invoke to unmap the cpu address from pci address.
> + */
> +void pci_epc_unmap_addr(struct pci_epc *epc, phys_addr_t phys_addr)
> +{
> + unsigned long flags;
> +
> + if (IS_ERR(epc))
> + return;
> +
> + if (!epc->ops->unmap_addr)
> + return;
> +
> + spin_lock_irqsave(&epc->lock, flags);
> + epc->ops->unmap_addr(epc, phys_addr);
> + spin_unlock_irqrestore(&epc->lock, flags);
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_unmap_addr);
> +
> +/**
> + * pci_epc_map_addr() - map cpu address to pci address
> + * @epc: the EPC device on which address is allocated
> + * @phys_addr: physical address of the local system
> + * @pci_addr: pci address to which the physical address should be mapped
> + * @size: the size of the allocation
> + *
> + * Invoke to map cpu address with pci address.
> + */
> +int pci_epc_map_addr(struct pci_epc *epc, phys_addr_t phys_addr,
> + u64 pci_addr, size_t size)
> +{
> + int ret;
> + unsigned long flags;
> +
> + if (IS_ERR(epc))
> + return -EINVAL;
> +
> + if (!epc->ops->map_addr)
> + return 0;
> +
> + spin_lock_irqsave(&epc->lock, flags);
> + ret =3D epc->ops->map_addr(epc, phys_addr, pci_addr, size);
> + spin_unlock_irqrestore(&epc->lock, flags);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_map_addr);
> +
> +/**
> + * pci_epc_clear_bar() - reset the BAR
> + * @epc: the EPC device for which the BAR has to be cleared
> + * @bar: the bar number that has to be reset
> + *
> + * Invoke to reset the BAR of the endpoint device.
> + */
> +void pci_epc_clear_bar(struct pci_epc *epc, int bar)
> +{
> + unsigned long flags;
> +
> + if (IS_ERR(epc))
> + return;
> +
> + if (!epc->ops->clear_bar)
> + return;
> +
> + spin_lock_irqsave(&epc->lock, flags);
> + epc->ops->clear_bar(epc, bar);
> + spin_unlock_irqrestore(&epc->lock, flags);
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_clear_bar);
> +
> +/**
> + * pci_epc_set_bar() - configure BAR in order for host to assign PCI add=
r space
> + * @epc: the EPC device on which BAR has to be configured
> + * @bar: the bar number that has to be configured
> + * @size: the size of the addr space
> + * @flags: specify memory allocation/io allocation/32bit address/64 bit =
address
> + *
> + * Invoke to configure the BAR of the endpoint device.
> + */
> +int pci_epc_set_bar(struct pci_epc *epc, enum pci_barno bar,
> + dma_addr_t bar_phys, size_t size, int flags)
> +{
> + int ret;
> + unsigned long irq_flags;
> +
> + if (IS_ERR(epc))
> + return -EINVAL;
> +
> + if (!epc->ops->set_bar)
> + return 0;
> +
> + spin_lock_irqsave(&epc->lock, irq_flags);
> + ret =3D epc->ops->set_bar(epc, bar, bar_phys, size, flags);
> + spin_unlock_irqrestore(&epc->lock, irq_flags);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_set_bar);
> +
> +/**
> + * pci_epc_write_header() - write standard configuration header
> + * @epc: the EPC device to which the configuration header should be writ=
ten
> + * @header: standard configuration header fields
> + *
> + * Invoke to write the configuration header to the endpoint controller. =
Every
> + * endpoint controller will have a dedicated location to which the stand=
ard
> + * configuration header would be written. The callback function should w=
rite
> + * the header fields to this dedicated location.
> + */
> +int pci_epc_write_header(struct pci_epc *epc, struct pci_epf_header *hea=
der)
> +{
> + int ret;
> + unsigned long flags;
> +
> + if (IS_ERR(epc))
> + return -EINVAL;
> +
> + if (!epc->ops->write_header)
> + return 0;
> +
> + spin_lock_irqsave(&epc->lock, flags);
> + ret =3D epc->ops->write_header(epc, header);
> + spin_unlock_irqrestore(&epc->lock, flags);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_write_header);
> +
> +/**
> + * pci_epc_add_epf() - bind pci endpoint function to an endpoint control=
ler
> + * @epc: the EPC device to which the endpoint function should be added
> + * @epf: the endpoint function to be added
> + *
> + * A PCI endpoint device can have one or more functions. In the case of =
PCIe,
> + * the specification allows upto 8 PCIe endpoint functions. Invoke
> + * pci_epc_add_epf() to add a pci endpoint function to an endpoint contr=
oller.
> + */
> +int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf)
> +{
> + unsigned long flags;
> +
> + if (IS_ERR(epc))
> + return -EINVAL;
> +
> + if (epf->func_no > epc->max_functions - 1)
> + return -EINVAL;
> +
> + dma_set_coherent_mask(&epf->dev, epc->dev.coherent_dma_mask);
> + epf->dev.dma_mask =3D epc->dev.dma_mask;
> +
> + spin_lock_irqsave(&epc->lock, flags);
> + list_add_tail(&epf->list, &epc->pci_epf);
> + spin_unlock_irqrestore(&epc->lock, flags);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_add_epf);
> +
> +/**
> + * pci_epc_remove_epf() - remove pci endpoint function from endpoint con=
troller
> + * @epc: the EPC device from which the endpoint function should be remov=
ed
> + * @epf: the endpoint function to be removed
> + *
> + * Invoke to remove pci endpoint function from the endpoint controller.
> + */
> +void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf)
> +{
> + unsigned long flags;
> +
> + if (!epc || IS_ERR(epc))
> + return;
> +
> + spin_lock_irqsave(&epc->lock, flags);
> + list_del(&epf->list);
> + spin_unlock_irqrestore(&epc->lock, flags);
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_remove_epf);
> +
> +/**
> + * pci_epc_destroy() - destroy the EPC device
> + * @epc: the EPC device that has to be destroyed
> + *
> + * Invoke to destroy the PCI EPC device
> + */
> +void pci_epc_destroy(struct pci_epc *epc)
> +{
> + device_unregister(&epc->dev);
> + kfree(epc);
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_destroy);
> +
> +/**
> + * devm_pci_epc_destroy() - destroy the EPC device
> + * @dev: device that wants to destroy the EPC
> + * @epc: the EPC device that has to be destroyed
> + *
> + * Invoke to destroy the devres associated with this
> + * pci_epc and destroy the EPC device.
> + */
> +void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc)
> +{
> + int r;
> +
> + r =3D devres_destroy(dev, devm_pci_epc_release, devm_pci_epc_match,
> + epc);
> + dev_WARN_ONCE(dev, r, "couldn't find PCI EPC resource\n");
> +}
> +EXPORT_SYMBOL_GPL(devm_pci_epc_destroy);
> +
> +/**
> + * __pci_epc_create() - create a new endpoint controller (EPC) device
> + * @dev: device that is creating the new EPC
> + * @ops: function pointers for performing EPC operations
> + * @owner: the owner of the module that creates the EPC device
> + *
> + * Invoke to create a new EPC device and add it to pci_epc class.
> + */
> +struct pci_epc *
> +__pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
> + struct module *owner)
> +{
> + int ret;
> + struct pci_epc *epc;
> +
> + if (WARN_ON(!dev)) {
> + ret =3D -EINVAL;
> + goto err_ret;
> + }
> +
> + epc =3D kzalloc(sizeof(*epc), GFP_KERNEL);
> + if (!epc) {
> + ret =3D -ENOMEM;
> + goto err_ret;
> + }
> +
> + spin_lock_init(&epc->lock);
> + INIT_LIST_HEAD(&epc->pci_epf);
> +
> + device_initialize(&epc->dev);
> + dma_set_coherent_mask(&epc->dev, dev->coherent_dma_mask);
> + epc->dev.class =3D pci_epc_class;
> + epc->dev.dma_mask =3D dev->dma_mask;
> + epc->ops =3D ops;
> +
> + ret =3D dev_set_name(&epc->dev, "%s", dev_name(dev));
> + if (ret)
> + goto put_dev;
> +
> + ret =3D device_add(&epc->dev);
> + if (ret)
> + goto put_dev;
> +
> + return epc;
> +
> +put_dev:
> + put_device(&epc->dev);
> + kfree(epc);
> +
> +err_ret:
> + return ERR_PTR(ret);
> +}
> +EXPORT_SYMBOL_GPL(__pci_epc_create);
> +
> +/**
> + * __devm_pci_epc_create() - create a new endpoint controller (EPC) devi=
ce
> + * @dev: device that is creating the new EPC
> + * @ops: function pointers for performing EPC operations
> + * @owner: the owner of the module that creates the EPC device
> + *
> + * Invoke to create a new EPC device and add it to pci_epc class.
> + * While at that, it also associates the device with the pci_epc using d=
evres.
> + * On driver detach, release function is invoked on the devres data,
> + * then, devres data is freed.
> + */
> +struct pci_epc *
> +__devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
> + struct module *owner)
> +{
> + struct pci_epc **ptr, *epc;
> +
> + ptr =3D devres_alloc(devm_pci_epc_release, sizeof(*ptr), GFP_KERNEL);
> + if (!ptr)
> + return ERR_PTR(-ENOMEM);
> +
> + epc =3D __pci_epc_create(dev, ops, owner);
> + if (!IS_ERR(epc)) {
> + *ptr =3D epc;
> + devres_add(dev, ptr);
> + } else {
> + devres_free(ptr);
> + }
> +
> + return epc;
> +}
> +EXPORT_SYMBOL_GPL(__devm_pci_epc_create);
> +
> +static int __init pci_epc_init(void)
> +{
> + pci_epc_class =3D class_create(THIS_MODULE, "pci_epc");
> + if (IS_ERR(pci_epc_class)) {
> + pr_err("failed to create pci epc class --> %ld\n",
> + PTR_ERR(pci_epc_class));
> + return PTR_ERR(pci_epc_class);
> + }
> +
> + return 0;
> +}
> +module_init(pci_epc_init);
> +
> +static void __exit pci_epc_exit(void)
> +{
> + class_destroy(pci_epc_class);
> +}
> +module_exit(pci_epc_exit);
> +
> +MODULE_DESCRIPTION("PCI EPC Library");
> +MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/pci/endpoint/pci-epc-mem.c b/drivers/pci/endpoint/pc=
i-epc-mem.c
> new file mode 100644
> index 0000000..3a94cc1
> --- /dev/null
> +++ b/drivers/pci/endpoint/pci-epc-mem.c
> @@ -0,0 +1,143 @@
> +/**
> + * PCI Endpoint *Controller* Address Space Management
> + *
> + * Copyright (C) 2017 Texas Instruments
> + * Author: Kishon Vijay Abraham I <kishon@ti.com>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 of
> + * the License as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <https://urldefense.proofpoint.=
com/v2/url?u=3Dhttp-3A__www.gnu.org_licenses_&d=3DDwIBAg&c=3DDPL6_X_6JkXFx7=
AXWqB0tg&r=3Ds2fO0hii0OGNOv9qQy_HRXy-xAJUD1NNoEcc3io_kx0&m=3DswFEoYaziG2Fdc=
vbq0MAtOjv2PLxgqEMssA9yjQVqXI&s=3DibUotwnXH20Q3a_vRJYtFUvGbSQN_43xAmUcsQ4FN=
vo&e=3D >.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +
> +#include <linux/pci-epc.h>
> +
> +/**
> + * pci_epc_mem_init() - initialize the pci_epc_mem structure
> + * @epc: the EPC device that invoked pci_epc_mem_init
> + * @phys_base: the physical address of the base
> + * @size: the size of the address space
> + *
> + * Invoke to initialize the pci_epc_mem structure used by the
> + * endpoint functions to allocate mapped PCI address.
> + */
> +int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_base, size_t =
size)
> +{
> + int ret;
> + struct pci_epc_mem *mem;
> + unsigned long *bitmap;
> + int pages =3D size >> PAGE_SHIFT;
> + int bitmap_size =3D BITS_TO_LONGS(pages) * sizeof(long);
> +
> + mem =3D kzalloc(sizeof(*mem), GFP_KERNEL);
> + if (!mem) {
> + ret =3D -ENOMEM;
> + goto err;
> + }
> +
> + bitmap =3D kzalloc(bitmap_size, GFP_KERNEL);
> + if (!bitmap) {
> + ret =3D -ENOMEM;
> + goto err_mem;
> + }
> +
> + mem->bitmap =3D bitmap;
> + mem->phys_base =3D phys_base;
> + mem->pages =3D pages;
> + mem->size =3D size;
> +
> + epc->mem =3D mem;
> +
> + return 0;
> +
> +err_mem:
> + kfree(mem);
> +
> +err:
> +return ret;
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_mem_init);
> +
> +/**
> + * pci_epc_mem_exit() - cleanup the pci_epc_mem structure
> + * @epc: the EPC device that invoked pci_epc_mem_exit
> + *
> + * Invoke to cleanup the pci_epc_mem structure allocated in
> + * pci_epc_mem_init().
> + */
> +void pci_epc_mem_exit(struct pci_epc *epc)
> +{
> + struct pci_epc_mem *mem =3D epc->mem;
> +
> + epc->mem =3D NULL;
> + kfree(mem->bitmap);
> + kfree(mem);
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_mem_exit);
> +
> +/**
> + * pci_epc_mem_alloc_addr() - allocate memory address from EPC addr space
> + * @epc: the EPC device on which memory has to be allocated
> + * @phys_addr: populate the allocated physical address here
> + * @size: the size of the address space that has to be allocated
> + *
> + * Invoke to allocate memory address from the EPC address space. This
> + * is usually done to map the remote RC address into the local system.
> + */
> +void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
> + phys_addr_t *phys_addr, size_t size)
> +{
> + int pageno;
> + void __iomem *virt_addr;
> + struct pci_epc_mem *mem =3D epc->mem;
> + int order =3D get_order(size);
> +
> + pageno =3D bitmap_find_free_region(mem->bitmap, mem->pages, order);
> + if (pageno < 0)
> + return NULL;
> +
> + *phys_addr =3D mem->phys_base + (pageno << PAGE_SHIFT);
> + virt_addr =3D ioremap(*phys_addr, size);
> + if (!virt_addr)
> + bitmap_release_region(mem->bitmap, pageno, order);
> +
> + return virt_addr;
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr);
> +
> +/**
> + * pci_epc_mem_free_addr() - free the allocated memory address
> + * @epc: the EPC device on which memory was allocated
> + * @phys_addr: the allocated physical address
> + * @virt_addr: virtual address of the allocated mem space
> + * @size: the size of the allocated address space
> + *
> + * Invoke to free the memory allocated using pci_epc_mem_alloc_addr.
> + */
> +void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
> + void __iomem *virt_addr, size_t size)
> +{
> + int pageno;
> + int order =3D get_order(size);
> + struct pci_epc_mem *mem =3D epc->mem;
> +
> + iounmap(virt_addr);
> + pageno =3D (phys_addr - mem->phys_base) >> PAGE_SHIFT;
> + bitmap_release_region(mem->bitmap, pageno, order);
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_mem_free_addr);
> +
> +MODULE_DESCRIPTION("PCI EPC Address Space Management");
> +MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/p=
ci-epf-core.c
> new file mode 100644
> index 0000000..4c903fc
> --- /dev/null
> +++ b/drivers/pci/endpoint/pci-epf-core.c
> @@ -0,0 +1,347 @@
> +/**
> + * PCI Endpoint *Function* (EPF) library
> + *
> + * Copyright (C) 2017 Texas Instruments
> + * Author: Kishon Vijay Abraham I <kishon@ti.com>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 of
> + * the License as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <https://urldefense.proofpoint.=
com/v2/url?u=3Dhttp-3A__www.gnu.org_licenses_&d=3DDwIBAg&c=3DDPL6_X_6JkXFx7=
AXWqB0tg&r=3Ds2fO0hii0OGNOv9qQy_HRXy-xAJUD1NNoEcc3io_kx0&m=3DswFEoYaziG2Fdc=
vbq0MAtOjv2PLxgqEMssA9yjQVqXI&s=3DibUotwnXH20Q3a_vRJYtFUvGbSQN_43xAmUcsQ4FN=
vo&e=3D >.
> + */
> +
> +#include <linux/device.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/slab.h>
> +#include <linux/module.h>
> +
> +#include <linux/pci-epc.h>
> +#include <linux/pci-epf.h>
> +
> +static struct bus_type pci_epf_bus_type;
> +static struct device_type pci_epf_type;
> +
> +/**
> + * pci_epf_linkup() - Notify the function driver that EPC device has
> + * established a connection with the Root Complex.
> + * @epf: the EPF device bound to the EPC device which has established
> + * the connection with the host
> + *
> + * Invoke to notify the function driver that EPC device has established
> + * a connection with the Root Complex.
> + */
> +void pci_epf_linkup(struct pci_epf *epf)
> +{
> + if (!epf->driver)
> + dev_WARN(&epf->dev, "epf device not bound to driver\n");
> +
> + epf->driver->ops->linkup(epf);
> +}
> +EXPORT_SYMBOL_GPL(pci_epf_linkup);
> +
> +/**
> + * pci_epf_unbind() - Notify the function driver that the binding betwee=
n the
> + * EPF device and EPC device has been lost
> + * @epf: the EPF device which has lost the binding with the EPC device
> + *
> + * Invoke to notify the function driver that the binding between the EPF=
device
> + * and EPC device has been lost.
> + */
> +void pci_epf_unbind(struct pci_epf *epf)
> +{
> + if (!epf->driver)
> + dev_WARN(&epf->dev, "epf device not bound to driver\n");
> +
> + epf->driver->ops->unbind(epf);
> + module_put(epf->driver->owner);
> +}
> +EXPORT_SYMBOL_GPL(pci_epf_unbind);
> +
> +/**
> + * pci_epf_bind() - Notify the function driver that the EPF device has b=
een
> + * bound to a EPC device
> + * @epf: the EPF device which has been bound to the EPC device
> + *
> + * Invoke to notify the function driver that it has been bound to a EPC =
device
> + */
> +int pci_epf_bind(struct pci_epf *epf)
> +{
> + if (!epf->driver)
> + dev_WARN(&epf->dev, "epf device not bound to driver\n");
> +
> + if (!try_module_get(epf->driver->owner))
> + return -EAGAIN;
> +
> + return epf->driver->ops->bind(epf);
> +}
> +EXPORT_SYMBOL_GPL(pci_epf_bind);
> +
> +/**
> + * pci_epf_free_space() - free the allocated PCI EPF register space
> + * @addr: the virtual address of the PCI EPF register space
> + * @bar: the bar number corresponding to the register space
> + *
> + * Invoke to free the allocated PCI EPF register space.
> + */
> +void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno =
bar)
> +{
> + struct device *dev =3D &epf->dev;
> +
> + if (!addr)
> + return;
> +
> + dma_free_coherent(dev, epf->bar[bar].size, addr,
> + epf->bar[bar].phys_addr);
> +
> + epf->bar[bar].phys_addr =3D 0;
> + epf->bar[bar].size =3D 0;
> +}
> +EXPORT_SYMBOL_GPL(pci_epf_free_space);
> +
> +/**
> + * pci_epf_alloc_space() - allocate memory for the PCI EPF register space
> + * @size: the size of the memory that has to be allocated
> + * @bar: the bar number corresponding to the allocated register space
> + *
> + * Invoke to allocate memory for the PCI EPF register space.
> + */
> +void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_bar=
no bar)
> +{
> + void *space;
> + struct device *dev =3D &epf->dev;
> + dma_addr_t phys_addr;
> +
> + if (size < 128)
> + size =3D 128;
> + size =3D roundup_pow_of_two(size);
> +
> + space =3D dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL);
> + if (!space) {
> + dev_err(dev, "failed to allocate mem space\n");
> + return NULL;
> + }
> +
> + epf->bar[bar].phys_addr =3D phys_addr;
> + epf->bar[bar].size =3D size;
> +
> + return space;
> +}
> +EXPORT_SYMBOL_GPL(pci_epf_alloc_space);
> +
> +/**
> + * pci_epf_unregister_driver() - unregister the PCI EPF driver
> + * @driver: the PCI EPF driver that has to be unregistered
> + *
> + * Invoke to unregister the PCI EPF driver.
> + */
> +void pci_epf_unregister_driver(struct pci_epf_driver *driver)
> +{
> + driver_unregister(&driver->driver);
> +}
> +EXPORT_SYMBOL_GPL(pci_epf_unregister_driver);
> +
> +/**
> + * __pci_epf_register_driver() - register a new PCI EPF driver
> + * @driver: structure representing PCI EPF driver
> + * @owner: the owner of the module that registers the PCI EPF driver
> + *
> + * Invoke to register a new PCI EPF driver.
> + */
> +int __pci_epf_register_driver(struct pci_epf_driver *driver,
> + struct module *owner)
> +{
> + int ret;
> +
> + if (!driver->ops)
> + return -EINVAL;
> +
> + if (!driver->ops->bind || !driver->ops->unbind || !driver->ops->linkup)
> + return -EINVAL;
> +
> + driver->driver.bus =3D &pci_epf_bus_type;
> + driver->driver.owner =3D owner;
> +
> + ret =3D driver_register(&driver->driver);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(__pci_epf_register_driver);
> +
> +/**
> + * pci_epf_destroy() - destroy the created PCI EPF device
> + * @epf: the PCI EPF device that has to be destroyed.
> + *
> + * Invoke to destroy the PCI EPF device created by invoking pci_epf_crea=
te().
> + */
> +void pci_epf_destroy(struct pci_epf *epf)
> +{
> + device_unregister(&epf->dev);
> +}
> +EXPORT_SYMBOL_GPL(pci_epf_destroy);
> +
> +/**
> + * pci_epf_create() - create a new PCI EPF device
> + * @name: the name of the PCI EPF device. This name will be used to bind=
the
> + * the EPF device to a EPF driver
> + *
> + * Invoke to create a new PCI EPF device by providing the name of the fu=
nction
> + * device.
> + */
> +struct pci_epf *pci_epf_create(const char *name)
> +{
> + int ret;
> + struct pci_epf *epf;
> + struct device *dev;
> + char *func_name;
> + char *buf;
> +
> + epf =3D kzalloc(sizeof(*epf), GFP_KERNEL);
> + if (!epf) {
> + ret =3D -ENOMEM;
> + goto err_ret;
> + }
> +
> + buf =3D kstrdup(name, GFP_KERNEL);
> + if (!buf) {
> + ret =3D -ENOMEM;
> + goto free_epf;
> + }
> +
> + func_name =3D buf;
> + buf =3D strchrnul(buf, '.');
> + *buf =3D '\0';
> +
> + epf->name =3D kstrdup(func_name, GFP_KERNEL);
> + if (!epf->name) {
> + ret =3D -ENOMEM;
> + goto free_epf;
> + }
> +
> + dev =3D &epf->dev;
> + device_initialize(dev);
> + dev->bus =3D &pci_epf_bus_type;
> + dev->type =3D &pci_epf_type;
> +
> + ret =3D dev_set_name(dev, "%s", name);
> + if (ret)
> + goto put_dev;
> +
> + ret =3D device_add(dev);
> + if (ret)
> + goto put_dev;
> +
> + kfree(func_name);
> + return epf;
> +
> +put_dev:
> + put_device(dev);
> + kfree(epf->name);
> + kfree(func_name);
> +
> +free_epf:
> + kfree(epf);
> +
> +err_ret:
> + return ERR_PTR(ret);
> +}
> +EXPORT_SYMBOL_GPL(pci_epf_create);
> +
> +static void pci_epf_dev_release(struct device *dev)
> +{
> + struct pci_epf *epf =3D to_pci_epf(dev);
> +
> + kfree(epf->name);
> + kfree(epf);
> +}
> +
> +static struct device_type pci_epf_type =3D {
> + .release =3D pci_epf_dev_release,
> +};
> +
> +static int
> +pci_epf_match_id(const struct pci_epf_device_id *id, const struct pci_ep=
f *epf)
> +{
> + while (id->name[0]) {
> + if (strcmp(epf->name, id->name) =3D=3D 0)
> + return true;
> + id++;
> + }
> +
> + return false;
> +}
> +
> +static int pci_epf_device_match(struct device *dev, struct device_driver=
*drv)
> +{
> + struct pci_epf *epf =3D to_pci_epf(dev);
> + struct pci_epf_driver *driver =3D to_pci_epf_driver(drv);
> +
> + if (driver->id_table)
> + return pci_epf_match_id(driver->id_table, epf);
> +
> + return !strcmp(epf->name, drv->name);
> +}
> +
> +static int pci_epf_device_probe(struct device *dev)
> +{
> + struct pci_epf *epf =3D to_pci_epf(dev);
> + struct pci_epf_driver *driver =3D to_pci_epf_driver(dev->driver);
> +
> + if (!driver->probe)
> + return -ENODEV;
> +
> + epf->driver =3D driver;
> +
> + return driver->probe(epf);
> +}
> +
> +static int pci_epf_device_remove(struct device *dev)
> +{
> + int ret;
> + struct pci_epf *epf =3D to_pci_epf(dev);
> + struct pci_epf_driver *driver =3D to_pci_epf_driver(dev->driver);
> +
> + ret =3D driver->remove(epf);
> + epf->driver =3D NULL;
> +
> + return ret;
> +}
> +
> +static struct bus_type pci_epf_bus_type =3D {
> + .name =3D "pci-epf",
> + .match =3D pci_epf_device_match,
> + .probe =3D pci_epf_device_probe,
> + .remove =3D pci_epf_device_remove,
> +};
> +
> +static int __init pci_epf_init(void)
> +{
> + int ret;
> +
> + ret =3D bus_register(&pci_epf_bus_type);
> + if (ret) {
> + pr_err("failed to register pci epf bus --> %d\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +module_init(pci_epf_init);
> +
> +static void __exit pci_epf_exit(void)
> +{
> + bus_unregister(&pci_epf_bus_type);
> +}
> +module_exit(pci_epf_exit);
> +
> +MODULE_DESCRIPTION("PCI EPF Library");
> +MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
> +MODULE_LICENSE("GPL v2");
> diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_deviceta=
ble.h
> index 8a57f0b..bf706c1 100644
> --- a/include/linux/mod_devicetable.h
> +++ b/include/linux/mod_devicetable.h
> @@ -428,6 +428,16 @@ struct i2c_device_id {
> kernel_ulong_t driver_data; /* Data private to the driver */
> };
> =
> +/* pci_epf */
> +
> +#define PCI_EPF_NAME_SIZE 20
> +#define PCI_EPF_MODULE_PREFIX "pci_epf:"
> +
> +struct pci_epf_device_id {
> + char name[PCI_EPF_NAME_SIZE];
> + kernel_ulong_t driver_data;
> +};
> +
> /* spi */
> =
> #define SPI_NAME_SIZE 32
> diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
> new file mode 100644
> index 0000000..b62f39d
> --- /dev/null
> +++ b/include/linux/pci-epc.h
> @@ -0,0 +1,141 @@
> +/**
> + * PCI Endpoint *Controller* (EPC) header file
> + *
> + * Copyright (C) 2017 Texas Instruments
> + * Author: Kishon Vijay Abraham I <kishon@ti.com>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 of
> + * the License as published by the Free Software Foundation.
> + */
> +
> +#ifndef __LINUX_PCI_EPC_H
> +#define __LINUX_PCI_EPC_H
> +
> +#include <linux/pci-epf.h>
> +
> +struct pci_epc;
> +
> +enum pci_epc_irq_type {
> + PCI_EPC_IRQ_UNKNOWN,
> + PCI_EPC_IRQ_LEGACY,
> + PCI_EPC_IRQ_MSI,
> +};
> +
> +/**
> + * struct pci_epc_ops - set of function pointers for performing EPC oper=
ations
> + * @write_header: ops to populate configuration space header
> + * @set_bar: ops to configure the BAR
> + * @clear_bar: ops to reset the BAR
> + * @map_addr: ops to map cpu address to pci address
> + * @unmap_addr: ops to unmap cpu address and pci address
> + * @set_msi: ops to set the requested number of MSI interrupts in the MSI
> + * capability register
> + * @get_msi: ops to get the number of MSI interrupts allocated by the RC=
from
> + * the MSI capability register
> + * @raise_irq: ops to raise a legacy or MSI interrupt
> + * @start: ops to start the PCI link
> + * @stop: ops to stop the PCI link
> + * @owner: the module owner containing the ops
> + */
> +struct pci_epc_ops {
> + int (*write_header)(struct pci_epc *pci_epc,
> + struct pci_epf_header *hdr);
> + int (*set_bar)(struct pci_epc *epc, enum pci_barno bar,
> + dma_addr_t bar_phys, size_t size, int flags);
> + void (*clear_bar)(struct pci_epc *epc, enum pci_barno bar);
> + int (*map_addr)(struct pci_epc *epc, phys_addr_t addr,
> + u64 pci_addr, size_t size);
> + void (*unmap_addr)(struct pci_epc *epc, phys_addr_t addr);
> + int (*set_msi)(struct pci_epc *epc, u8 interrupts);
> + int (*get_msi)(struct pci_epc *epc);
> + int (*raise_irq)(struct pci_epc *pci_epc,
> + enum pci_epc_irq_type type, u8 interrupt_num);
> + int (*start)(struct pci_epc *epc);
> + void (*stop)(struct pci_epc *epc);
> + struct module *owner;
> +};
> +
> +/**
> + * struct pci_epc_mem - address space of the endpoint controller
> + * @phys_base: physical base address of the pci address space
> + * @size: the size of the pci address space
> + * @bitmap: bitmap to manage the pci address space
> + * @pages: number of bits representing the address region
> + */
> +struct pci_epc_mem {
> + phys_addr_t phys_base;
> + size_t size;
> + unsigned long *bitmap;
> + int pages;
> +};
> +
> +/**
> + * struct pci_epc - represents the PCI EPC device
> + * @dev: PCI EPC device
> + * @pci_epf: list of endpoint functions present in this EPC device
> + * @ops: function pointers for performing endpoint operations
> + * @mem: address space of the endpoint controller
> + * @max_functions: max number of functions that can be configured in thi=
s EPC
> + * @lock: spinlock to protect pci_epc ops
> + */
> +struct pci_epc {
> + struct device dev;
> + struct list_head pci_epf;
> + const struct pci_epc_ops *ops;
> + struct pci_epc_mem *mem;
> + u8 max_functions;
> + /* spinlock to protect against concurrent access of EP controller */
> + spinlock_t lock;
> +};
> +
> +#define to_pci_epc(device) container_of((device), struct pci_epc, dev)
> +
> +#define pci_epc_create(dev, ops) \
> + __pci_epc_create((dev), (ops), THIS_MODULE)
> +#define devm_pci_epc_create(dev, ops) \
> + __devm_pci_epc_create((dev), (ops), THIS_MODULE)
> +
> +static inline void epc_set_drvdata(struct pci_epc *epc, void *data)
> +{
> + dev_set_drvdata(&epc->dev, data);
> +}
> +
> +static inline void *epc_get_drvdata(struct pci_epc *epc)
> +{
> + return dev_get_drvdata(&epc->dev);
> +}
> +
> +struct pci_epc *
> +__devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
> + struct module *owner);
> +struct pci_epc *
> +__pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
> + struct module *owner);
> +void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc);
> +void pci_epc_destroy(struct pci_epc *epc);
> +int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf);
> +void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf);
> +int pci_epc_write_header(struct pci_epc *epc, struct pci_epf_header *hdr=
);
> +int pci_epc_set_bar(struct pci_epc *epc, enum pci_barno bar,
> + dma_addr_t bar_phys, size_t size, int flags);
> +void pci_epc_clear_bar(struct pci_epc *epc, int bar);
> +int pci_epc_map_addr(struct pci_epc *epc, phys_addr_t phys_addr,
> + u64 pci_addr, size_t size);
> +void pci_epc_unmap_addr(struct pci_epc *epc, phys_addr_t phys_addr);
> +int pci_epc_set_msi(struct pci_epc *epc, u8 interrupts);
> +int pci_epc_get_msi(struct pci_epc *epc);
> +int pci_epc_raise_irq(struct pci_epc *epc, enum pci_epc_irq_type type,
> + u8 interrupt_num);
> +int pci_epc_start(struct pci_epc *epc);
> +void pci_epc_stop(struct pci_epc *epc);
> +struct pci_epc *pci_epc_get(char *epc_name);
> +void pci_epc_put(struct pci_epc *epc);
> +
> +int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_addr, size_t =
size);
> +void pci_epc_mem_exit(struct pci_epc *epc);
> +void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
> + phys_addr_t *phys_addr, size_t size);
> +void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
> + void __iomem *virt_addr, size_t size);
> +#endif /* __LINUX_PCI_EPC_H */
> diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h
> new file mode 100644
> index 0000000..54f1338
> --- /dev/null
> +++ b/include/linux/pci-epf.h
> @@ -0,0 +1,160 @@
> +/**
> + * PCI Endpoint *Function* (EPF) header file
> + *
> + * Copyright (C) 2017 Texas Instruments
> + * Author: Kishon Vijay Abraham I <kishon@ti.com>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 of
> + * the License as published by the Free Software Foundation.
> + */
> +
> +#ifndef __LINUX_PCI_EPF_H
> +#define __LINUX_PCI_EPF_H
> +
> +#include <linux/device.h>
> +#include <linux/mod_devicetable.h>
> +
> +struct pci_epf;
> +
> +enum pci_interrupt_pin {
> + PCI_INTERRUPT_UNKNOWN,
> + PCI_INTERRUPT_INTA,
> + PCI_INTERRUPT_INTB,
> + PCI_INTERRUPT_INTC,
> + PCI_INTERRUPT_INTD,
> +};
> +
> +enum pci_barno {
> + BAR_0,
> + BAR_1,
> + BAR_2,
> + BAR_3,
> + BAR_4,
> + BAR_5,
> +};
> +
> +/**
> + * struct pci_epf_header - represents standard configuration header
> + * @vendorid: identifies device manufacturer
> + * @deviceid: identifies a particular device
> + * @revid: specifies a device specific revision identifier
> + * @progif_code: identifies a specific register-level programming interf=
ace
> + * @subclass_code: identifies more specifically the function of the devi=
ce
> + * @baseclass_code: broadly classifies the type of function the device p=
erforms
> + * @cache_line_size: specifies the system cacheline size in units of DWO=
RDs
> + * @subsys_vendor_id: vendor of the add-in card or subsystem
> + * @subsys_id: id specific to vendor
> + * @interrupt_pin: interrupt pin the device (or device function) uses
> + */
> +struct pci_epf_header {
> + u16 vendorid;
> + u16 deviceid;
> + u8 revid;
> + u8 progif_code;
> + u8 subclass_code;
> + u8 baseclass_code;
> + u8 cache_line_size;
> + u16 subsys_vendor_id;
> + u16 subsys_id;
> + enum pci_interrupt_pin interrupt_pin;
> +};
> +
> +/**
> + * struct pci_epf_ops - set of function pointers for performing EPF oper=
ations
> + * @bind: ops to perform when a EPC device has been bound to EPF device
> + * @unbind: ops to perform when a binding has been lost between a EPC de=
vice
> + * and EPF device
> + * @linkup: ops to perform when the EPC device has established a connect=
ion with
> + * a host system
> + */
> +struct pci_epf_ops {
> + int (*bind)(struct pci_epf *epf);
> + void (*unbind)(struct pci_epf *epf);
> + void (*linkup)(struct pci_epf *epf);
> +};
> +
> +/**
> + * struct pci_epf_driver - represents the PCI EPF driver
> + * @probe: ops to perform when a new EPF device has been bound to the EP=
F driver
> + * @remove: ops to perform when the binding between the EPF device and E=
PF
> + * driver is broken
> + * @driver: PCI EPF driver
> + * @ops: set of function pointers for performing EPF operations
> + * @owner: the owner of the module that registers the PCI EPF driver
> + * @id_table: identifies EPF devices for probing
> + */
> +struct pci_epf_driver {
> + int (*probe)(struct pci_epf *epf);
> + int (*remove)(struct pci_epf *epf);
> +
> + struct device_driver driver;
> + struct pci_epf_ops *ops;
> + struct module *owner;
> + const struct pci_epf_device_id *id_table;
> +};
> +
> +#define to_pci_epf_driver(drv) (container_of((drv), struct pci_epf_drive=
r, \
> + driver))
> +
> +/**
> + * struct pci_epf_bar - represents the BAR of EPF device
> + * @phys_addr: physical address that should be mapped to the BAR
> + * @size: the size of the address space present in BAR
> + */
> +struct pci_epf_bar {
> + dma_addr_t phys_addr;
> + size_t size;
> +};
> +
> +/**
> + * struct pci_epf - represents the PCI EPF device
> + * @dev: the PCI EPF device
> + * @name: the name of the PCI EPF device
> + * @header: represents standard configuration header
> + * @bar: represents the BAR of EPF device
> + * @msi_interrupts: number of msi interrupts required by this function
> + * @func_no: unique function number within this endpoint device
> + * @epc: the EPC device to which this EPF device is bound
> + * @driver: the EPF driver to which this EPF device is bound
> + * @list: to add pci_epf as a list of pci endpoint functions to pci_epc
> + */
> +struct pci_epf {
> + struct device dev;
> + const char *name;
> + struct pci_epf_header *header;
> + struct pci_epf_bar bar[6];
> + u8 msi_interrupts;
> + u8 func_no;
> +
> + struct pci_epc *epc;
> + struct pci_epf_driver *driver;
> + struct list_head list;
> +};
> +
> +#define to_pci_epf(epf_dev) container_of((epf_dev), struct pci_epf, dev)
> +
> +#define pci_epf_register_driver(driver) \
> + __pci_epf_register_driver((driver), THIS_MODULE)
> +
> +static inline void epf_set_drvdata(struct pci_epf *epf, void *data)
> +{
> + dev_set_drvdata(&epf->dev, data);
> +}
> +
> +static inline void *epf_get_drvdata(struct pci_epf *epf)
> +{
> + return dev_get_drvdata(&epf->dev);
> +}
> +
> +struct pci_epf *pci_epf_create(const char *name);
> +void pci_epf_destroy(struct pci_epf *epf);
> +int __pci_epf_register_driver(struct pci_epf_driver *driver,
> + struct module *owner);
> +void pci_epf_unregister_driver(struct pci_epf_driver *driver);
> +void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_bar=
no bar);
> +void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno =
bar);
> +int pci_epf_bind(struct pci_epf *epf);
> +void pci_epf_unbind(struct pci_epf *epf);
> +void pci_epf_linkup(struct pci_epf *epf);
> +#endif /* __LINUX_PCI_EPF_H */
> =
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^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 01/22] PCI: endpoint: Add EP core layer to enable EP controller and EP functions
2017-02-17 11:26 ` Joao Pinto
@ 2017-02-17 11:37 ` Kishon Vijay Abraham I
2017-02-17 11:39 ` Joao Pinto
0 siblings, 1 reply; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 11:37 UTC (permalink / raw)
To: Joao Pinto, Bjorn Helgaas, Jingoo Han
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
linux-omap, linux-arm-kernel
Hi Joao,
On Friday 17 February 2017 04:56 PM, Joao Pinto wrote:
> =
> Hi Kishon,
> =
> =C0s 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
>> Introduce a new EP core layer in order to support endpoint functions
>> in linux kernel. This comprises of EPC library
>> (Endpoint Controller Library) and EPF library (Endpoint
>> Function Library). EPC library implements functions that is specific
>> to an endpoint controller and EPF library implements functions
>> that is specific to an endpoint function.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> drivers/Makefile | 2 +
>> drivers/pci/Kconfig | 1 +
>> drivers/pci/endpoint/Kconfig | 21 ++
>> drivers/pci/endpoint/Makefile | 6 +
>> drivers/pci/endpoint/pci-epc-core.c | 548 ++++++++++++++++++++++++++++=
+++++++
>> drivers/pci/endpoint/pci-epc-mem.c | 143 +++++++++
>> drivers/pci/endpoint/pci-epf-core.c | 347 ++++++++++++++++++++++
>> include/linux/mod_devicetable.h | 10 +
>> include/linux/pci-epc.h | 141 +++++++++
>> include/linux/pci-epf.h | 160 ++++++++++
>> 10 files changed, 1379 insertions(+)
>> create mode 100644 drivers/pci/endpoint/Kconfig
>> create mode 100644 drivers/pci/endpoint/Makefile
>> create mode 100644 drivers/pci/endpoint/pci-epc-core.c
>> create mode 100644 drivers/pci/endpoint/pci-epc-mem.c
>> create mode 100644 drivers/pci/endpoint/pci-epf-core.c
>> create mode 100644 include/linux/pci-epc.h
>> create mode 100644 include/linux/pci-epf.h
>>
>> diff --git a/drivers/Makefile b/drivers/Makefile
>> index f521cb0..a300bb1 100644
>> --- a/drivers/Makefile
>> +++ b/drivers/Makefile
>> @@ -14,7 +14,9 @@ obj-$(CONFIG_GENERIC_PHY) +=3D phy/
>> obj-$(CONFIG_PINCTRL) +=3D pinctrl/
>> obj-$(CONFIG_GPIOLIB) +=3D gpio/
>> obj-y +=3D pwm/
>> +
>> obj-$(CONFIG_PCI) +=3D pci/
>> +obj-$(CONFIG_PCI_ENDPOINT) +=3D pci/endpoint/
>> # PCI dwc controller drivers
>> obj-y +=3D pci/dwc/
> =
> Any special reason to include pci/endpoint and pci/dwc in drivers/Makefile
> instead of being inside pci/Makefile? pci/host is still inside pci/Makefi=
le.
CONFIG_PCI enables all the pcie host support. Endpoint support should be
enabled independent of the host support. Moving pci/endpoint inside
pci/Makefile will build endpoint support only if CONFIG_PCI is enabled. For=
the
same reason kept pci/dwc in drivers/Makefile since dwc drivers can be used
either in host mode or device mode (or both).
Thanks
Kishon
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^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 01/22] PCI: endpoint: Add EP core layer to enable EP controller and EP functions
2017-02-17 11:37 ` Kishon Vijay Abraham I
@ 2017-02-17 11:39 ` Joao Pinto
0 siblings, 0 replies; 49+ messages in thread
From: Joao Pinto @ 2017-02-17 11:39 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Joao Pinto, Bjorn Helgaas, Jingoo Han
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
linux-omap, linux-arm-kernel
=C0s 11:37 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
> Hi Joao,
> =
> On Friday 17 February 2017 04:56 PM, Joao Pinto wrote:
>>
>> Hi Kishon,
>>
>> =C0s 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
>>> Introduce a new EP core layer in order to support endpoint functions
>>> in linux kernel. This comprises of EPC library
>>> (Endpoint Controller Library) and EPF library (Endpoint
>>> Function Library). EPC library implements functions that is specific
>>> to an endpoint controller and EPF library implements functions
>>> that is specific to an endpoint function.
>>>
>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>>> ---
>>> drivers/Makefile | 2 +
>>> drivers/pci/Kconfig | 1 +
>>> drivers/pci/endpoint/Kconfig | 21 ++
>>> drivers/pci/endpoint/Makefile | 6 +
>>> drivers/pci/endpoint/pci-epc-core.c | 548 +++++++++++++++++++++++++++=
++++++++
>>> drivers/pci/endpoint/pci-epc-mem.c | 143 +++++++++
>>> drivers/pci/endpoint/pci-epf-core.c | 347 ++++++++++++++++++++++
>>> include/linux/mod_devicetable.h | 10 +
>>> include/linux/pci-epc.h | 141 +++++++++
>>> include/linux/pci-epf.h | 160 ++++++++++
>>> 10 files changed, 1379 insertions(+)
>>> create mode 100644 drivers/pci/endpoint/Kconfig
>>> create mode 100644 drivers/pci/endpoint/Makefile
>>> create mode 100644 drivers/pci/endpoint/pci-epc-core.c
>>> create mode 100644 drivers/pci/endpoint/pci-epc-mem.c
>>> create mode 100644 drivers/pci/endpoint/pci-epf-core.c
>>> create mode 100644 include/linux/pci-epc.h
>>> create mode 100644 include/linux/pci-epf.h
>>>
>>> diff --git a/drivers/Makefile b/drivers/Makefile
>>> index f521cb0..a300bb1 100644
>>> --- a/drivers/Makefile
>>> +++ b/drivers/Makefile
>>> @@ -14,7 +14,9 @@ obj-$(CONFIG_GENERIC_PHY) +=3D phy/
>>> obj-$(CONFIG_PINCTRL) +=3D pinctrl/
>>> obj-$(CONFIG_GPIOLIB) +=3D gpio/
>>> obj-y +=3D pwm/
>>> +
>>> obj-$(CONFIG_PCI) +=3D pci/
>>> +obj-$(CONFIG_PCI_ENDPOINT) +=3D pci/endpoint/
>>> # PCI dwc controller drivers
>>> obj-y +=3D pci/dwc/
>>
>> Any special reason to include pci/endpoint and pci/dwc in drivers/Makefi=
le
>> instead of being inside pci/Makefile? pci/host is still inside pci/Makef=
ile.
> =
> CONFIG_PCI enables all the pcie host support. Endpoint support should be
> enabled independent of the host support. Moving pci/endpoint inside
> pci/Makefile will build endpoint support only if CONFIG_PCI is enabled. F=
or the
> same reason kept pci/dwc in drivers/Makefile since dwc drivers can be used
> either in host mode or device mode (or both).
Good point! Very well.
Acked-By: Joao Pinto <jpinto@synopsys.com>
> =
> Thanks
> Kishon
> =
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 02/22] Documentation: PCI: Guide to use PCI Endpoint Core Layer
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
2017-02-17 9:50 ` [PATCH v2 01/22] PCI: endpoint: Add EP core layer to enable EP controller and EP functions Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-17 11:43 ` Joao Pinto
2017-02-17 9:50 ` [PATCH v2 03/22] PCI: endpoint: Introduce configfs entry for configuring EP functions Kishon Vijay Abraham I
` (19 subsequent siblings)
21 siblings, 1 reply; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
Kishon Vijay Abraham I, linux-omap, linux-arm-kernel
Add Documentation to help users use endpoint library to enable endpoint
mode in the PCI controller and add new PCI endpoint functions.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Documentation/PCI/00-INDEX | 2 +
Documentation/PCI/endpoint/pci-endpoint.txt | 190 +++++++++++++++++++++++++++
2 files changed, 192 insertions(+)
create mode 100644 Documentation/PCI/endpoint/pci-endpoint.txt
diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX
index 147231f..ba950b2 100644
--- a/Documentation/PCI/00-INDEX
+++ b/Documentation/PCI/00-INDEX
@@ -12,3 +12,5 @@ pci.txt
- info on the PCI subsystem for device driver authors
pcieaer-howto.txt
- the PCI Express Advanced Error Reporting Driver Guide HOWTO
+endpoint/pci-endpoint.txt
+ - guide to add endpoint controller driver and endpoint function driver.
diff --git a/Documentation/PCI/endpoint/pci-endpoint.txt b/Documentation/PCI/endpoint/pci-endpoint.txt
new file mode 100644
index 0000000..68a7839
--- /dev/null
+++ b/Documentation/PCI/endpoint/pci-endpoint.txt
@@ -0,0 +1,190 @@
+ PCI ENDPOINT FRAMEWORK
+ Kishon Vijay Abraham I <kishon@ti.com>
+
+This document is a guide to use the PCI Endpoint Framework in order to create
+endpoint controller driver, endpoint function driver and using configfs
+interface to bind the function driver to the controller driver.
+
+1. Introduction
+
+*Linux* has a comprehensive PCI subsystem to support PCI controllers that
+operates in Root Complex mode. The subsystem has capability to scan PCI bus,
+assign memory resources and irq resources, load PCI driver (based on
+vendorid, deviceid), support other services like hot-plug, power management,
+advanced error reporting and virtual channels.
+
+However PCI controller IPs integrated in certain SoC is capable of operating
+either in Root Complex mode or Endpoint mode. PCI Endpoint Framework will
+add endpoint mode support in *Linux*. This will help to run Linux in an
+EP system which can have a wide variety of use cases from testing or
+validation, co-processor accelerator etc..
+
+2. PCI Endpoint Core
+
+The PCI Endpoint Core layer comprises of 3 components: the Endpoint Controller
+library, the Endpoint Function library and the configfs layer to bind the
+endpoint function with the endpoint controller.
+
+2.1 PCI Endpoint Controller(EPC) Library
+
+The EPC library provides APIs to be used by the controller that can operate
+in endpoint mode. It also provides APIs to be used by function driver/library
+in order to implement a particular endpoint function.
+
+2.1.1 APIs for the PCI controller Driver
+
+This section lists the APIs that the PCI Endpoint core provides to be used
+by the PCI controller driver.
+
+*) devm_pci_epc_create()/pci_epc_create()
+
+ The PCI controller driver should implement the following ops:
+ * write_header: ops to populate configuration space header
+ * set_bar: ops to configure the BAR
+ * clear_bar: ops to reset the BAR
+ * alloc_addr_space: ops to allocate *in* PCI controller address space
+ * free_addr_space: ops to free the allocated address space
+ * raise_irq: ops to raise a legacy or MSI interrupt
+ * start: ops to start the PCI link
+ * stop: ops to stop the PCI link
+
+ The PCI controller driver can then create a new EPC device by invoking
+ devm_pci_epc_create/pci_epc_create.
+
+*) devm_pci_epc_destroy()/pci_epc_destroy()
+
+ The PCI controller driver can destroy the EPC device created by either
+ devm_pci_epc_create or pci_epc_create using devm_pci_epc_destroy() or
+ /pci_epc_destroy()
+
+2.1.2 APIs for the PCI Endpoint Function Driver
+
+This section lists the APIs that the PCI Endpoint core provides to be used
+by the PCI endpoint function driver.
+
+*) pci_epc_write_header()
+
+ The PCI endpoint function driver should use pci_epc_write_header() to
+ write the standard configuration header to the endpoint controller.
+
+*) pci_epc_set_bar()
+
+ The PCI endpoint function driver should use pci_epc_set_bar() to configure
+ the Base Address Register in order for the host to assign PCI addr space.
+ Register space of the function driver is usually configured
+ using this API.
+
+*) pci_epc_clear_bar()
+
+ The PCI endpoint function driver should use pci_epc_clear_bar() to reset
+ the BAR.
+
+*) pci_epc_raise_irq()
+
+ The PCI endpoint function driver should use pci_epc_raise_irq() to raise
+ Legacy Interrupt or MSI Interrupt.
+
+*) pci_epc_start()
+
+ The PCI endpoint function driver should invoke pci_epc_start() once it
+ has configured the endpoint function and wants to start the PCI link.
+
+*) pci_epc_stop()
+
+ The PCI endpoint function driver should invoke pci_epc_stop() to stop
+ the PCI LINK.
+
+2.1.3 Other APIs
+
+There are other APIs provided by the EPC library. These are used for binding
+the epf device with epc device. pci-ep-cfs.c can be used as reference for
+using these APIs.
+
+*) pci_epc_get()
+
+ Get a reference to the pci endpoint controller based on the device name of
+ the controller.
+
+*) pci_epc_put()
+
+ Release the reference to the pci endpoint controller obtained using
+ pci_epc_get()
+
+*) pci_epc_add_epf()
+
+ Add a pci endpoint function to a pci endpoint controller. A pcie device
+ can have upto 8 functions according to the specification.
+
+*) pci_epc_remove_epf()
+
+ Remove the pci endpoint function from pci endpoint controller.
+
+2.2 PCI Endpoint Function(EPF) Library
+
+The EPF library provides APIs to be used by the function driver and the EPC
+library in order to provide endpoint mode functionality.
+
+2.2.1 APIs for the PCI Endpoint Function Driver
+
+This section lists the APIs that the PCI Endpoint core provides to be used
+by the PCI endpoint function driver.
+
+*) pci_epf_register_driver()
+
+ The PCI Endpoint Function driver should implement the following ops:
+ * bind: ops to perform when a EPC device has been bound to EPF device
+ * unbind: ops to perform when a binding has been lost between a EPC
+ device and EPF device
+ * linkup: ops to perform when the EPC device has established a
+ connection with a host system
+
+ The PCI Function driver can then register the PCI EPF driver by using
+ pci_epf_register_driver().
+
+*) pci_epf_unregister_driver()
+
+ The PCI Function driver can unregister the PCI EPF driver by using
+ pci_epf_unregister_driver().
+
+*) pci_epf_alloc_space()
+
+ The PCI Function driver can allocate space for a particular BAR using
+ pci_epf_alloc_space().
+
+*) pci_epf_free_space()
+
+ The PCI Function driver can free the allocated space
+ (using pci_epf_alloc_space) by invoking pci_epf_free_space().
+
+2.2.2 APIs for the PCI Endpoint Controller Library
+This section lists the APIs that the PCI Endpoint core provides to be used
+by the PCI endpoint controller library.
+
+*) pci_epf_linkup()
+
+ The PCI endpoint controller library invokes pci_epf_linkup() when the
+ EPC device has established the connection to the host.
+
+2.2.2 Other APIs
+There are other APIs provided by the EPF library. These are used to notify
+the function driver when the EPF device is bound to the EPC device.
+pci-ep-cfs.c can be used as reference for using these APIs.
+
+*) pci_epf_create()
+
+ Create a new PCI EPF device by passing the name of the PCI EPF device.
+ This name will be used to bind the the EPF device to a EPF driver.
+
+*) pci_epf_destroy()
+
+ Destroy the created PCI EPF device.
+
+*) pci_epf_bind()
+
+ pci_epf_bind() should be invoked when the EPF device has been bound to
+ a EPC device.
+
+*) pci_epf_unbind()
+
+ pci_epf_unbind() should be invoked when the binding between EPC device
+ and EPF device is lost.
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 49+ messages in thread* Re: [PATCH v2 02/22] Documentation: PCI: Guide to use PCI Endpoint Core Layer
2017-02-17 9:50 ` [PATCH v2 02/22] Documentation: PCI: Guide to use PCI Endpoint Core Layer Kishon Vijay Abraham I
@ 2017-02-17 11:43 ` Joao Pinto
0 siblings, 0 replies; 49+ messages in thread
From: Joao Pinto @ 2017-02-17 11:43 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
linux-omap, linux-arm-kernel
=C0s 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
> Add Documentation to help users use endpoint library to enable endpoint
> mode in the PCI controller and add new PCI endpoint functions.
> =
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> Documentation/PCI/00-INDEX | 2 +
> Documentation/PCI/endpoint/pci-endpoint.txt | 190 +++++++++++++++++++++=
++++++
> 2 files changed, 192 insertions(+)
> create mode 100644 Documentation/PCI/endpoint/pci-endpoint.txt
> =
> diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX
> index 147231f..ba950b2 100644
> --- a/Documentation/PCI/00-INDEX
> +++ b/Documentation/PCI/00-INDEX
> @@ -12,3 +12,5 @@ pci.txt
> - info on the PCI subsystem for device driver authors
> pcieaer-howto.txt
> - the PCI Express Advanced Error Reporting Driver Guide HOWTO
> +endpoint/pci-endpoint.txt
> + - guide to add endpoint controller driver and endpoint function driver.
> diff --git a/Documentation/PCI/endpoint/pci-endpoint.txt b/Documentation/=
PCI/endpoint/pci-endpoint.txt
> new file mode 100644
> index 0000000..68a7839
> --- /dev/null
> +++ b/Documentation/PCI/endpoint/pci-endpoint.txt
> @@ -0,0 +1,190 @@
> + PCI ENDPOINT FRAMEWORK
> + Kishon Vijay Abraham I <kishon@ti.com>
> +
> +This document is a guide to use the PCI Endpoint Framework in order to c=
reate
> +endpoint controller driver, endpoint function driver and using configfs
> +interface to bind the function driver to the controller driver.
> +
> +1. Introduction
> +
> +*Linux* has a comprehensive PCI subsystem to support PCI controllers that
> +operates in Root Complex mode. The subsystem has capability to scan PCI =
bus,
> +assign memory resources and irq resources, load PCI driver (based on
> +vendorid, deviceid), support other services like hot-plug, power managem=
ent,
> +advanced error reporting and virtual channels.
> +
> +However PCI controller IPs integrated in certain SoC is capable of opera=
ting
> +either in Root Complex mode or Endpoint mode. PCI Endpoint Framework will
> +add endpoint mode support in *Linux*. This will help to run Linux in an
> +EP system which can have a wide variety of use cases from testing or
> +validation, co-processor accelerator etc..
> +
> +2. PCI Endpoint Core
> +
> +The PCI Endpoint Core layer comprises of 3 components: the Endpoint Cont=
roller
> +library, the Endpoint Function library and the configfs layer to bind the
> +endpoint function with the endpoint controller.
> +
> +2.1 PCI Endpoint Controller(EPC) Library
> +
> +The EPC library provides APIs to be used by the controller that can oper=
ate
> +in endpoint mode. It also provides APIs to be used by function driver/li=
brary
> +in order to implement a particular endpoint function.
> +
> +2.1.1 APIs for the PCI controller Driver
> +
> +This section lists the APIs that the PCI Endpoint core provides to be us=
ed
> +by the PCI controller driver.
> +
> +*) devm_pci_epc_create()/pci_epc_create()
> +
> + The PCI controller driver should implement the following ops:
> + * write_header: ops to populate configuration space header
> + * set_bar: ops to configure the BAR
> + * clear_bar: ops to reset the BAR
> + * alloc_addr_space: ops to allocate *in* PCI controller address space
> + * free_addr_space: ops to free the allocated address space
> + * raise_irq: ops to raise a legacy or MSI interrupt
> + * start: ops to start the PCI link
> + * stop: ops to stop the PCI link
> +
> + The PCI controller driver can then create a new EPC device by invoking
> + devm_pci_epc_create/pci_epc_create.
> +
> +*) devm_pci_epc_destroy()/pci_epc_destroy()
> +
> + The PCI controller driver can destroy the EPC device created by either
> + devm_pci_epc_create or pci_epc_create using devm_pci_epc_destroy() or
> + /pci_epc_destroy()
> +
> +2.1.2 APIs for the PCI Endpoint Function Driver
> +
> +This section lists the APIs that the PCI Endpoint core provides to be us=
ed
> +by the PCI endpoint function driver.
> +
> +*) pci_epc_write_header()
> +
> + The PCI endpoint function driver should use pci_epc_write_header() to
> + write the standard configuration header to the endpoint controller.
> +
> +*) pci_epc_set_bar()
> +
> + The PCI endpoint function driver should use pci_epc_set_bar() to conf=
igure
> + the Base Address Register in order for the host to assign PCI addr sp=
ace.
> + Register space of the function driver is usually configured
> + using this API.
> +
> +*) pci_epc_clear_bar()
> +
> + The PCI endpoint function driver should use pci_epc_clear_bar() to re=
set
> + the BAR.
> +
> +*) pci_epc_raise_irq()
> +
> + The PCI endpoint function driver should use pci_epc_raise_irq() to ra=
ise
> + Legacy Interrupt or MSI Interrupt.
> +
> +*) pci_epc_start()
> +
> + The PCI endpoint function driver should invoke pci_epc_start() once it
> + has configured the endpoint function and wants to start the PCI link.
> +
> +*) pci_epc_stop()
> +
> + The PCI endpoint function driver should invoke pci_epc_stop() to stop
> + the PCI LINK.
> +
> +2.1.3 Other APIs
> +
> +There are other APIs provided by the EPC library. These are used for bin=
ding
> +the epf device with epc device. pci-ep-cfs.c can be used as reference for
> +using these APIs.
> +
> +*) pci_epc_get()
> +
> + Get a reference to the pci endpoint controller based on the device na=
me of
> + the controller.
> +
> +*) pci_epc_put()
> +
> + Release the reference to the pci endpoint controller obtained using
> + pci_epc_get()
> +
> +*) pci_epc_add_epf()
> +
> + Add a pci endpoint function to a pci endpoint controller. A pcie devi=
ce
> + can have upto 8 functions according to the specification.
> +
> +*) pci_epc_remove_epf()
> +
> + Remove the pci endpoint function from pci endpoint controller.
> +
> +2.2 PCI Endpoint Function(EPF) Library
> +
> +The EPF library provides APIs to be used by the function driver and the =
EPC
> +library in order to provide endpoint mode functionality.
> +
> +2.2.1 APIs for the PCI Endpoint Function Driver
> +
> +This section lists the APIs that the PCI Endpoint core provides to be us=
ed
> +by the PCI endpoint function driver.
> +
> +*) pci_epf_register_driver()
> +
> + The PCI Endpoint Function driver should implement the following ops:
> + * bind: ops to perform when a EPC device has been bound to EPF device
> + * unbind: ops to perform when a binding has been lost between a EPC
> + device and EPF device
> + * linkup: ops to perform when the EPC device has established a
> + connection with a host system
> +
> + The PCI Function driver can then register the PCI EPF driver by using
> + pci_epf_register_driver().
> +
> +*) pci_epf_unregister_driver()
> +
> + The PCI Function driver can unregister the PCI EPF driver by using
> + pci_epf_unregister_driver().
> +
> +*) pci_epf_alloc_space()
> +
> + The PCI Function driver can allocate space for a particular BAR using
> + pci_epf_alloc_space().
> +
> +*) pci_epf_free_space()
> +
> + The PCI Function driver can free the allocated space
> + (using pci_epf_alloc_space) by invoking pci_epf_free_space().
> +
> +2.2.2 APIs for the PCI Endpoint Controller Library
> +This section lists the APIs that the PCI Endpoint core provides to be us=
ed
> +by the PCI endpoint controller library.
> +
> +*) pci_epf_linkup()
> +
> + The PCI endpoint controller library invokes pci_epf_linkup() when the
> + EPC device has established the connection to the host.
> +
> +2.2.2 Other APIs
> +There are other APIs provided by the EPF library. These are used to noti=
fy
> +the function driver when the EPF device is bound to the EPC device.
> +pci-ep-cfs.c can be used as reference for using these APIs.
> +
> +*) pci_epf_create()
> +
> + Create a new PCI EPF device by passing the name of the PCI EPF device.
> + This name will be used to bind the the EPF device to a EPF driver.
> +
> +*) pci_epf_destroy()
> +
> + Destroy the created PCI EPF device.
> +
> +*) pci_epf_bind()
> +
> + pci_epf_bind() should be invoked when the EPF device has been bound to
> + a EPC device.
> +
> +*) pci_epf_unbind()
> +
> + pci_epf_unbind() should be invoked when the binding between EPC device
> + and EPF device is lost.
> =
Good initial reference guide.
Acked-By: Joao Pinto <jpinto@synopsys.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 03/22] PCI: endpoint: Introduce configfs entry for configuring EP functions
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
2017-02-17 9:50 ` [PATCH v2 01/22] PCI: endpoint: Add EP core layer to enable EP controller and EP functions Kishon Vijay Abraham I
2017-02-17 9:50 ` [PATCH v2 02/22] Documentation: PCI: Guide to use PCI Endpoint Core Layer Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-17 12:01 ` Kishon Vijay Abraham I
2017-02-17 17:04 ` Christoph Hellwig
2017-02-17 9:50 ` [PATCH v2 04/22] Documentation: PCI: Guide to use pci endpoint configfs Kishon Vijay Abraham I
` (18 subsequent siblings)
21 siblings, 2 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
Kishon Vijay Abraham I, linux-omap, linux-arm-kernel
Introduce a new configfs entry to configure the EP function (like
configuring the standard configuration header entries) and to
bind the EP function with EP controller.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/endpoint/Kconfig | 14 +-
drivers/pci/endpoint/Makefile | 1 +
drivers/pci/endpoint/pci-ep-cfs.c | 427 +++++++++++++++++++++++++++++++++++++
3 files changed, 440 insertions(+), 2 deletions(-)
create mode 100644 drivers/pci/endpoint/pci-ep-cfs.c
diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig
index 7eb1c79..8470f0b 100644
--- a/drivers/pci/endpoint/Kconfig
+++ b/drivers/pci/endpoint/Kconfig
@@ -6,7 +6,6 @@ menu "PCI Endpoint"
config PCI_ENDPOINT
bool "PCI Endpoint Support"
- select CONFIGFS_FS
help
Enable this configuration option to support configurable PCI
endpoint. This should be enabled if the platform has a PCI
@@ -14,8 +13,19 @@ config PCI_ENDPOINT
Enabling this option will build the endpoint library, which
includes endpoint controller library and endpoint function
- library.
+ library. This will also enable the configfs entry required to
+ configure the endpoint function and used to bind the
+ function with a endpoint controller.
If in doubt, say "N" to disable Endpoint support.
+config PCI_ENDPOINT_CONFIGFS
+ bool "PCI Endpoint Configfs Support"
+ depends on PCI_ENDPOINT
+ select CONFIGFS_FS
+ help
+ This will enable the configfs entry that can be used to
+ configure the endpoint function and used to bind the
+ function with a endpoint controller.
+
endmenu
diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile
index dc1bc16..dd9163c 100644
--- a/drivers/pci/endpoint/Makefile
+++ b/drivers/pci/endpoint/Makefile
@@ -4,3 +4,4 @@
obj-$(CONFIG_PCI_ENDPOINT) += pci-epc-core.o pci-epf-core.o\
pci-epc-mem.o
+obj-$(CONFIG_PCI_ENDPOINT_CONFIGFS) += pci-ep-cfs.o
diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-ep-cfs.c
new file mode 100644
index 0000000..ed0f8c2
--- /dev/null
+++ b/drivers/pci/endpoint/pci-ep-cfs.c
@@ -0,0 +1,427 @@
+/**
+ * configfs to configure the PCI endpoint
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/configfs.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+
+#include <linux/pci-epc.h>
+#include <linux/pci-epf.h>
+
+struct pci_epf_info {
+ struct config_group group;
+ struct list_head list;
+ struct pci_epf *epf;
+};
+
+struct pci_ep_info {
+ struct config_group group;
+ struct config_group pci_epf_group;
+ /* mutex to protect pci_epf list */
+ struct mutex lock;
+ struct list_head pci_epf;
+ const char *epc_name;
+ struct pci_epc *epc;
+};
+
+static inline struct pci_epf_info *to_pci_epf_info(struct config_item *item)
+{
+ return container_of(to_config_group(item), struct pci_epf_info, group);
+}
+
+static inline struct pci_ep_info *to_pci_ep_info(struct config_item *item)
+{
+ return container_of(to_config_group(item), struct pci_ep_info, group);
+}
+
+#define PCI_EPF_HEADER_R(_name) \
+static ssize_t pci_epf_##_name##_show(struct config_item *item, char *page) \
+{ \
+ struct pci_epf *epf = to_pci_epf_info(item)->epf; \
+ if (!epf->header) { \
+ WARN_ON_ONCE("epf device not bound to function driver\n"); \
+ return 0; \
+ } \
+ return sprintf(page, "0x%04x\n", epf->header->_name); \
+}
+
+#define PCI_EPF_HEADER_W_u32(_name) \
+static ssize_t pci_epf_##_name##_store(struct config_item *item, \
+ const char *page, size_t len) \
+{ \
+ u32 val; \
+ int ret; \
+ struct pci_epf *epf = to_pci_epf_info(item)->epf; \
+ if (!epf->header) { \
+ WARN_ON_ONCE("epf device not bound to function driver\n"); \
+ return 0; \
+ } \
+ ret = kstrtou32(page, 0, &val); \
+ if (ret) \
+ return ret; \
+ epf->header->_name = val; \
+ return len; \
+}
+
+#define PCI_EPF_HEADER_W_u16(_name) \
+static ssize_t pci_epf_##_name##_store(struct config_item *item, \
+ const char *page, size_t len) \
+{ \
+ u16 val; \
+ int ret; \
+ struct pci_epf *epf = to_pci_epf_info(item)->epf; \
+ if (!epf->header) { \
+ WARN_ON_ONCE("epf device not bound to function driver\n"); \
+ return 0; \
+ } \
+ ret = kstrtou16(page, 0, &val); \
+ if (ret) \
+ return ret; \
+ epf->header->_name = val; \
+ return len; \
+}
+
+#define PCI_EPF_HEADER_W_u8(_name) \
+static ssize_t pci_epf_##_name##_store(struct config_item *item, \
+ const char *page, size_t len) \
+{ \
+ u8 val; \
+ int ret; \
+ struct pci_epf *epf = to_pci_epf_info(item)->epf; \
+ if (!epf->header) { \
+ WARN_ON_ONCE("epf device not bound to function driver\n"); \
+ return 0; \
+ } \
+ ret = kstrtou8(page, 0, &val); \
+ if (ret) \
+ return ret; \
+ epf->header->_name = val; \
+ return len; \
+}
+
+static ssize_t pci_epf_msi_interrupts_store(struct config_item *item,
+ const char *page, size_t len)
+{
+ u8 val;
+ int ret;
+
+ ret = kstrtou8(page, 0, &val);
+ if (ret)
+ return ret;
+
+ to_pci_epf_info(item)->epf->msi_interrupts = val;
+
+ return len;
+}
+
+static ssize_t pci_epf_msi_interrupts_show(struct config_item *item,
+ char *page)
+{
+ return sprintf(page, "%d\n",
+ to_pci_epf_info(item)->epf->msi_interrupts);
+}
+
+static ssize_t pci_epf_function_show(struct config_item *item,
+ char *page)
+{
+ return sprintf(page, "%s\n",
+ to_pci_epf_info(item)->epf->name);
+}
+
+PCI_EPF_HEADER_R(vendorid)
+PCI_EPF_HEADER_W_u16(vendorid)
+
+PCI_EPF_HEADER_R(deviceid)
+PCI_EPF_HEADER_W_u16(deviceid)
+
+PCI_EPF_HEADER_R(revid)
+PCI_EPF_HEADER_W_u8(revid)
+
+PCI_EPF_HEADER_R(progif_code)
+PCI_EPF_HEADER_W_u8(progif_code)
+
+PCI_EPF_HEADER_R(subclass_code)
+PCI_EPF_HEADER_W_u8(subclass_code)
+
+PCI_EPF_HEADER_R(baseclass_code)
+PCI_EPF_HEADER_W_u8(baseclass_code)
+
+PCI_EPF_HEADER_R(cache_line_size)
+PCI_EPF_HEADER_W_u8(cache_line_size)
+
+PCI_EPF_HEADER_R(subsys_vendor_id)
+PCI_EPF_HEADER_W_u16(subsys_vendor_id)
+
+PCI_EPF_HEADER_R(subsys_id)
+PCI_EPF_HEADER_W_u16(subsys_id)
+
+PCI_EPF_HEADER_R(interrupt_pin)
+PCI_EPF_HEADER_W_u8(interrupt_pin)
+
+CONFIGFS_ATTR(pci_epf_, vendorid);
+CONFIGFS_ATTR(pci_epf_, deviceid);
+CONFIGFS_ATTR(pci_epf_, revid);
+CONFIGFS_ATTR(pci_epf_, progif_code);
+CONFIGFS_ATTR(pci_epf_, subclass_code);
+CONFIGFS_ATTR(pci_epf_, baseclass_code);
+CONFIGFS_ATTR(pci_epf_, cache_line_size);
+CONFIGFS_ATTR(pci_epf_, subsys_vendor_id);
+CONFIGFS_ATTR(pci_epf_, subsys_id);
+CONFIGFS_ATTR(pci_epf_, interrupt_pin);
+CONFIGFS_ATTR(pci_epf_, msi_interrupts);
+CONFIGFS_ATTR_RO(pci_epf_, function);
+
+static struct configfs_attribute *pci_epf_attrs[] = {
+ &pci_epf_attr_vendorid,
+ &pci_epf_attr_deviceid,
+ &pci_epf_attr_revid,
+ &pci_epf_attr_progif_code,
+ &pci_epf_attr_subclass_code,
+ &pci_epf_attr_baseclass_code,
+ &pci_epf_attr_cache_line_size,
+ &pci_epf_attr_subsys_vendor_id,
+ &pci_epf_attr_subsys_id,
+ &pci_epf_attr_interrupt_pin,
+ &pci_epf_attr_msi_interrupts,
+ &pci_epf_attr_function,
+ NULL,
+};
+
+static void pci_epf_release(struct config_item *item)
+{
+ struct pci_epf_info *epf_info = to_pci_epf_info(item);
+
+ pci_epf_destroy(epf_info->epf);
+ kfree(epf_info);
+}
+
+static struct configfs_item_operations pci_epf_ops = {
+ .release = pci_epf_release,
+};
+
+static struct config_item_type pci_epf_type = {
+ .ct_item_ops = &pci_epf_ops,
+ .ct_attrs = pci_epf_attrs,
+ .ct_owner = THIS_MODULE,
+};
+
+static struct config_group *pci_epf_make(struct config_group *group,
+ const char *name)
+{
+ struct pci_epf_info *epf_info;
+ struct pci_ep_info *ep_info;
+ struct pci_epf *epf;
+
+ epf_info = kzalloc(sizeof(*epf_info), GFP_KERNEL);
+ if (!epf_info)
+ return ERR_PTR(-ENOMEM);
+
+ config_group_init_type_name(&epf_info->group, name, &pci_epf_type);
+
+ epf = pci_epf_create(name);
+ if (IS_ERR(epf)) {
+ pr_err("failed to create endpoint function device\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ epf_info->epf = epf;
+ ep_info = container_of(group, struct pci_ep_info, pci_epf_group);
+
+ mutex_lock(&ep_info->lock);
+ list_add_tail(&epf_info->list, &ep_info->pci_epf);
+ mutex_unlock(&ep_info->lock);
+
+ return &epf_info->group;
+}
+
+static void pci_epf_drop(struct config_group *group, struct config_item *item)
+{
+ struct pci_ep_info *ep_info;
+ struct pci_epf_info *epf_info = to_pci_epf_info(item);
+
+ ep_info = container_of(group, struct pci_ep_info, pci_epf_group);
+
+ pci_epf_unbind(epf_info->epf);
+ pci_epc_remove_epf(ep_info->epc, epf_info->epf);
+
+ mutex_lock(&ep_info->lock);
+ list_del(&epf_info->list);
+ mutex_unlock(&ep_info->lock);
+
+ config_item_put(item);
+}
+
+static struct configfs_group_operations pci_epfs_ops = {
+ .make_group = &pci_epf_make,
+ .drop_item = &pci_epf_drop,
+};
+
+static struct config_item_type pci_epfs_type = {
+ .ct_group_ops = &pci_epfs_ops,
+ .ct_owner = THIS_MODULE,
+};
+
+static ssize_t pci_ep_epc_store(struct config_item *item, const char *page,
+ size_t len)
+{
+ int ret;
+ u8 func_no = 0;
+ char *epc_name;
+ struct pci_epc *epc;
+ struct pci_epf *epf;
+ struct pci_epf_info *epf_info;
+ struct pci_ep_info *ep_info = to_pci_ep_info(item);
+
+ epc_name = kstrdup(page, GFP_KERNEL);
+ if (!epc_name)
+ return -ENOMEM;
+ if (epc_name[len - 1] == '\n')
+ epc_name[len - 1] = '\0';
+
+ if (ep_info->epc) {
+ ret = -EBUSY;
+ goto err;
+ }
+
+ epc = pci_epc_get(epc_name);
+ if (IS_ERR(epc)) {
+ ret = PTR_ERR(epc);
+ goto err;
+ }
+
+ ep_info->epc = epc;
+ ep_info->epc_name = epc_name;
+
+ list_for_each_entry(epf_info, &ep_info->pci_epf, list) {
+ epf = epf_info->epf;
+ epf->func_no = func_no;
+ epf->epc = epc;
+ pci_epc_add_epf(epc, epf);
+ pci_epf_bind(epf);
+ func_no++;
+ }
+
+ return len;
+
+err:
+ kfree(epc_name);
+ return ret;
+}
+
+static ssize_t pci_ep_epc_show(struct config_item *item, char *page)
+{
+ return sprintf(page, "%s\n",
+ to_pci_ep_info(item)->epc_name);
+}
+
+CONFIGFS_ATTR(pci_ep_, epc);
+
+static struct configfs_attribute *pci_ep_attrs[] = {
+ &pci_ep_attr_epc,
+ NULL,
+};
+
+static void pci_ep_attr_release(struct config_item *item)
+{
+ struct pci_ep_info *ep_info = to_pci_ep_info(item);
+
+ pci_epc_put(ep_info->epc);
+ kfree(ep_info->epc_name);
+ kfree(ep_info);
+}
+
+static struct configfs_item_operations pci_ep_device_ops = {
+ .release = pci_ep_attr_release,
+};
+
+static struct config_item_type pci_ep_device_type = {
+ .ct_item_ops = &pci_ep_device_ops,
+ .ct_attrs = pci_ep_attrs,
+ .ct_owner = THIS_MODULE,
+};
+
+static struct config_group *pci_ep_make(struct config_group *group,
+ const char *name)
+{
+ struct pci_ep_info *ep_info;
+
+ ep_info = kzalloc(sizeof(*ep_info), GFP_KERNEL);
+ if (!ep_info)
+ return ERR_PTR(-ENOMEM);
+
+ config_group_init_type_name(&ep_info->group, name, &pci_ep_device_type);
+ config_group_init_type_name(&ep_info->pci_epf_group,
+ "epf", &pci_epfs_type);
+ configfs_add_default_group(&ep_info->pci_epf_group, &ep_info->group);
+
+ mutex_init(&ep_info->lock);
+ INIT_LIST_HEAD(&ep_info->pci_epf);
+
+ return &ep_info->group;
+}
+
+static void pci_ep_drop(struct config_group *group, struct config_item *item)
+{
+ config_item_put(item);
+}
+
+static struct configfs_group_operations pci_ep_ops = {
+ .make_group = &pci_ep_make,
+ .drop_item = &pci_ep_drop,
+};
+
+static struct config_item_type pci_ep_type = {
+ .ct_group_ops = &pci_ep_ops,
+ .ct_owner = THIS_MODULE,
+};
+
+static struct configfs_subsystem pci_ep_cfs_subsys = {
+ .su_group = {
+ .cg_item = {
+ .ci_namebuf = "pci_ep",
+ .ci_type = &pci_ep_type,
+ },
+ },
+ .su_mutex = __MUTEX_INITIALIZER(pci_ep_cfs_subsys.su_mutex),
+};
+
+static int __init pci_ep_cfs_init(void)
+{
+ int ret;
+
+ config_group_init(&pci_ep_cfs_subsys.su_group);
+
+ ret = configfs_register_subsystem(&pci_ep_cfs_subsys);
+ if (ret)
+ pr_err("Error %d while registering subsystem %s\n",
+ ret, pci_ep_cfs_subsys.su_group.cg_item.ci_namebuf);
+
+ return ret;
+}
+module_init(pci_ep_cfs_init);
+
+static void __exit pci_ep_cfs_exit(void)
+{
+ configfs_unregister_subsystem(&pci_ep_cfs_subsys);
+}
+module_exit(pci_ep_cfs_exit);
+
+MODULE_DESCRIPTION("PCI EP CONFIGFS");
+MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
+MODULE_LICENSE("GPL v2");
--
1.7.9.5
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread* Re: [PATCH v2 03/22] PCI: endpoint: Introduce configfs entry for configuring EP functions
2017-02-17 9:50 ` [PATCH v2 03/22] PCI: endpoint: Introduce configfs entry for configuring EP functions Kishon Vijay Abraham I
@ 2017-02-17 12:01 ` Kishon Vijay Abraham I
2017-02-17 17:04 ` Christoph Hellwig
1 sibling, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 12:01 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: linux-pci, linux-doc, linux-kernel, devicetree, linux-omap,
linux-arm-kernel, nsekhar
Hi,
On Friday 17 February 2017 03:20 PM, Kishon Vijay Abraham I wrote:
> Introduce a new configfs entry to configure the EP function (like
> configuring the standard configuration header entries) and to
> bind the EP function with EP controller.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/pci/endpoint/Kconfig | 14 +-
> drivers/pci/endpoint/Makefile | 1 +
> drivers/pci/endpoint/pci-ep-cfs.c | 427 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 440 insertions(+), 2 deletions(-)
> create mode 100644 drivers/pci/endpoint/pci-ep-cfs.c
>
> diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig
> index 7eb1c79..8470f0b 100644
> --- a/drivers/pci/endpoint/Kconfig
> +++ b/drivers/pci/endpoint/Kconfig
> @@ -6,7 +6,6 @@ menu "PCI Endpoint"
>
> config PCI_ENDPOINT
> bool "PCI Endpoint Support"
> - select CONFIGFS_FS
> help
> Enable this configuration option to support configurable PCI
> endpoint. This should be enabled if the platform has a PCI
> @@ -14,8 +13,19 @@ config PCI_ENDPOINT
>
> Enabling this option will build the endpoint library, which
> includes endpoint controller library and endpoint function
> - library.
> + library. This will also enable the configfs entry required to
> + configure the endpoint function and used to bind the
> + function with a endpoint controller.
This chunk shouldn't be added. I've missed removing this (it's added below).
I'll wait to get other review comments before sending a new revision.
Thanks
Kishon
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 03/22] PCI: endpoint: Introduce configfs entry for configuring EP functions
2017-02-17 9:50 ` [PATCH v2 03/22] PCI: endpoint: Introduce configfs entry for configuring EP functions Kishon Vijay Abraham I
2017-02-17 12:01 ` Kishon Vijay Abraham I
@ 2017-02-17 17:04 ` Christoph Hellwig
2017-03-06 9:41 ` Kishon Vijay Abraham I
1 sibling, 1 reply; 49+ messages in thread
From: Christoph Hellwig @ 2017-02-17 17:04 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: devicetree, Joao Pinto, linux-doc, Jingoo Han, nsekhar,
linux-kernel, linux-pci, Bjorn Helgaas, linux-omap,
linux-arm-kernel
On Fri, Feb 17, 2017 at 03:20:23PM +0530, Kishon Vijay Abraham I wrote:
> Introduce a new configfs entry to configure the EP function (like
> configuring the standard configuration header entries) and to
> bind the EP function with EP controller.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/pci/endpoint/Kconfig | 14 +-
> drivers/pci/endpoint/Makefile | 1 +
> drivers/pci/endpoint/pci-ep-cfs.c | 427 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 440 insertions(+), 2 deletions(-)
> create mode 100644 drivers/pci/endpoint/pci-ep-cfs.c
>
> diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig
> index 7eb1c79..8470f0b 100644
> --- a/drivers/pci/endpoint/Kconfig
> +++ b/drivers/pci/endpoint/Kconfig
> @@ -6,7 +6,6 @@ menu "PCI Endpoint"
>
> config PCI_ENDPOINT
> bool "PCI Endpoint Support"
> - select CONFIGFS_FS
> help
> Enable this configuration option to support configurable PCI
> endpoint. This should be enabled if the platform has a PCI
> @@ -14,8 +13,19 @@ config PCI_ENDPOINT
>
> Enabling this option will build the endpoint library, which
> includes endpoint controller library and endpoint function
> - library.
> + library. This will also enable the configfs entry required to
> + configure the endpoint function and used to bind the
> + function with a endpoint controller.
>
> If in doubt, say "N" to disable Endpoint support.
>
> +config PCI_ENDPOINT_CONFIGFS
> + bool "PCI Endpoint Configfs Support"
> + depends on PCI_ENDPOINT
> + select CONFIGFS_FS
> + help
> + This will enable the configfs entry that can be used to
> + configure the endpoint function and used to bind the
> + function with a endpoint controller.
> +
> endmenu
> diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile
> index dc1bc16..dd9163c 100644
> --- a/drivers/pci/endpoint/Makefile
> +++ b/drivers/pci/endpoint/Makefile
> @@ -4,3 +4,4 @@
>
> obj-$(CONFIG_PCI_ENDPOINT) += pci-epc-core.o pci-epf-core.o\
> pci-epc-mem.o
> +obj-$(CONFIG_PCI_ENDPOINT_CONFIGFS) += pci-ep-cfs.o
> diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-ep-cfs.c
> new file mode 100644
> index 0000000..ed0f8c2
> --- /dev/null
> +++ b/drivers/pci/endpoint/pci-ep-cfs.c
> @@ -0,0 +1,427 @@
> +/**
> + * configfs to configure the PCI endpoint
> + *
> + * Copyright (C) 2017 Texas Instruments
> + * Author: Kishon Vijay Abraham I <kishon@ti.com>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 of
> + * the License as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/configfs.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +
> +#include <linux/pci-epc.h>
> +#include <linux/pci-epf.h>
> +
> +struct pci_epf_info {
> + struct config_group group;
> + struct list_head list;
> + struct pci_epf *epf;
> +};
> +
> +struct pci_ep_info {
> + struct config_group group;
> + struct config_group pci_epf_group;
> + /* mutex to protect pci_epf list */
> + struct mutex lock;
> + struct list_head pci_epf;
> + const char *epc_name;
> + struct pci_epc *epc;
> +};
> +
> +static inline struct pci_epf_info *to_pci_epf_info(struct config_item *item)
> +{
> + return container_of(to_config_group(item), struct pci_epf_info, group);
> +}
> +
> +static inline struct pci_ep_info *to_pci_ep_info(struct config_item *item)
> +{
> + return container_of(to_config_group(item), struct pci_ep_info, group);
> +}
> +
> +#define PCI_EPF_HEADER_R(_name) \
> +static ssize_t pci_epf_##_name##_show(struct config_item *item, char *page) \
> +{ \
> + struct pci_epf *epf = to_pci_epf_info(item)->epf; \
> + if (!epf->header) { \
> + WARN_ON_ONCE("epf device not bound to function driver\n"); \
WARN_ON_ONCE takes a string to evaluate as argument, not a message
> + return 0;
and if we return 0 here the callers will retry because that is
interpreted as a short read. The code should be something like:
if (WARN_ON_ONCE(!epf->header))
return -EINVAL;
> + if (!epf->header) { \
> + WARN_ON_ONCE("epf device not bound to function driver\n"); \
> + return 0; \
> + } \
Same here, and a couple more instances down below.
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^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 03/22] PCI: endpoint: Introduce configfs entry for configuring EP functions
2017-02-17 17:04 ` Christoph Hellwig
@ 2017-03-06 9:41 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-03-06 9:41 UTC (permalink / raw)
To: Christoph Hellwig
Cc: devicetree, Joao Pinto, linux-doc, Jingoo Han, nsekhar,
linux-kernel, linux-pci, Bjorn Helgaas, linux-omap,
linux-arm-kernel
Hi,
On Friday 17 February 2017 10:34 PM, Christoph Hellwig wrote:
> On Fri, Feb 17, 2017 at 03:20:23PM +0530, Kishon Vijay Abraham I wrote:
>> Introduce a new configfs entry to configure the EP function (like
>> configuring the standard configuration header entries) and to
>> bind the EP function with EP controller.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> drivers/pci/endpoint/Kconfig | 14 +-
>> drivers/pci/endpoint/Makefile | 1 +
>> drivers/pci/endpoint/pci-ep-cfs.c | 427 +++++++++++++++++++++++++++++++++++++
>> 3 files changed, 440 insertions(+), 2 deletions(-)
>> create mode 100644 drivers/pci/endpoint/pci-ep-cfs.c
>>
>> diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig
>> index 7eb1c79..8470f0b 100644
>> --- a/drivers/pci/endpoint/Kconfig
>> +++ b/drivers/pci/endpoint/Kconfig
>> @@ -6,7 +6,6 @@ menu "PCI Endpoint"
>>
>> config PCI_ENDPOINT
>> bool "PCI Endpoint Support"
>> - select CONFIGFS_FS
>> help
>> Enable this configuration option to support configurable PCI
>> endpoint. This should be enabled if the platform has a PCI
>> @@ -14,8 +13,19 @@ config PCI_ENDPOINT
>>
>> Enabling this option will build the endpoint library, which
>> includes endpoint controller library and endpoint function
>> - library.
>> + library. This will also enable the configfs entry required to
>> + configure the endpoint function and used to bind the
>> + function with a endpoint controller.
>>
>> If in doubt, say "N" to disable Endpoint support.
>>
>> +config PCI_ENDPOINT_CONFIGFS
>> + bool "PCI Endpoint Configfs Support"
>> + depends on PCI_ENDPOINT
>> + select CONFIGFS_FS
>> + help
>> + This will enable the configfs entry that can be used to
>> + configure the endpoint function and used to bind the
>> + function with a endpoint controller.
>> +
>> endmenu
>> diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile
>> index dc1bc16..dd9163c 100644
>> --- a/drivers/pci/endpoint/Makefile
>> +++ b/drivers/pci/endpoint/Makefile
>> @@ -4,3 +4,4 @@
>>
>> obj-$(CONFIG_PCI_ENDPOINT) += pci-epc-core.o pci-epf-core.o\
>> pci-epc-mem.o
>> +obj-$(CONFIG_PCI_ENDPOINT_CONFIGFS) += pci-ep-cfs.o
>> diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-ep-cfs.c
>> new file mode 100644
>> index 0000000..ed0f8c2
>> --- /dev/null
>> +++ b/drivers/pci/endpoint/pci-ep-cfs.c
>> @@ -0,0 +1,427 @@
>> +/**
>> + * configfs to configure the PCI endpoint
>> + *
>> + * Copyright (C) 2017 Texas Instruments
>> + * Author: Kishon Vijay Abraham I <kishon@ti.com>
>> + *
>> + * This program is free software: you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 of
>> + * the License as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include <linux/configfs.h>
>> +#include <linux/module.h>
>> +#include <linux/slab.h>
>> +
>> +#include <linux/pci-epc.h>
>> +#include <linux/pci-epf.h>
>> +
>> +struct pci_epf_info {
>> + struct config_group group;
>> + struct list_head list;
>> + struct pci_epf *epf;
>> +};
>> +
>> +struct pci_ep_info {
>> + struct config_group group;
>> + struct config_group pci_epf_group;
>> + /* mutex to protect pci_epf list */
>> + struct mutex lock;
>> + struct list_head pci_epf;
>> + const char *epc_name;
>> + struct pci_epc *epc;
>> +};
>> +
>> +static inline struct pci_epf_info *to_pci_epf_info(struct config_item *item)
>> +{
>> + return container_of(to_config_group(item), struct pci_epf_info, group);
>> +}
>> +
>> +static inline struct pci_ep_info *to_pci_ep_info(struct config_item *item)
>> +{
>> + return container_of(to_config_group(item), struct pci_ep_info, group);
>> +}
>> +
>> +#define PCI_EPF_HEADER_R(_name) \
>> +static ssize_t pci_epf_##_name##_show(struct config_item *item, char *page) \
>> +{ \
>> + struct pci_epf *epf = to_pci_epf_info(item)->epf; \
>> + if (!epf->header) { \
>> + WARN_ON_ONCE("epf device not bound to function driver\n"); \
>
> WARN_ON_ONCE takes a string to evaluate as argument, not a message
>
>> + return 0;
>
> and if we return 0 here the callers will retry because that is
> interpreted as a short read. The code should be something like:
>
> if (WARN_ON_ONCE(!epf->header))
> return -EINVAL;
>
>> + if (!epf->header) { \
>> + WARN_ON_ONCE("epf device not bound to function driver\n"); \
>> + return 0; \
>> + } \
>
> Same here, and a couple more instances down below.
sure, fixed it now.
Thanks
Kishon
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 04/22] Documentation: PCI: Guide to use pci endpoint configfs
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
` (2 preceding siblings ...)
2017-02-17 9:50 ` [PATCH v2 03/22] PCI: endpoint: Introduce configfs entry for configuring EP functions Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-17 13:05 ` Joao Pinto
2017-02-17 17:15 ` Christoph Hellwig
2017-02-17 9:50 ` [PATCH v2 05/22] Documentation: PCI: Add specification for the *pci test* function device Kishon Vijay Abraham I
` (17 subsequent siblings)
21 siblings, 2 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
Kishon Vijay Abraham I, linux-omap, linux-arm-kernel
Add Documentation to help users use pci endpoint to configure
pci endpoint function and to bind the endpoint function
with endpoint controller.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Documentation/PCI/00-INDEX | 2 +
Documentation/PCI/endpoint/pci-endpoint-cfs.txt | 84 +++++++++++++++++++++++
2 files changed, 86 insertions(+)
create mode 100644 Documentation/PCI/endpoint/pci-endpoint-cfs.txt
diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX
index ba950b2..f84a23c 100644
--- a/Documentation/PCI/00-INDEX
+++ b/Documentation/PCI/00-INDEX
@@ -14,3 +14,5 @@ pcieaer-howto.txt
- the PCI Express Advanced Error Reporting Driver Guide HOWTO
endpoint/pci-endpoint.txt
- guide to add endpoint controller driver and endpoint function driver.
+endpoint/pci-endpoint-cfs.txt
+ - guide to use configfs to configure the pci endpoint function.
diff --git a/Documentation/PCI/endpoint/pci-endpoint-cfs.txt b/Documentation/PCI/endpoint/pci-endpoint-cfs.txt
new file mode 100644
index 0000000..d9f8734
--- /dev/null
+++ b/Documentation/PCI/endpoint/pci-endpoint-cfs.txt
@@ -0,0 +1,84 @@
+ CONFIGURING PCI ENDPOINT USING CONFIGFS
+ Kishon Vijay Abraham I <kishon@ti.com>
+
+The PCI Endpoint Core exposes configfs entry (pci_ep) in order to configure the
+PCI endpoint function and in order to bind the endpoint function
+with the endpoint controller. (For introducing other mechanisms to
+configure the PCI Endpoint Function refer [1]).
+
+*) Mounting configfs
+
+The PCI Endpoint Core layer creates pci_ep directory in the mounted configfs
+directory. configfs can be mounted using the following command.
+
+ mount -t configfs none /sys/kernel/config
+
+*) Directory Structure
+
+The pci_ep configfs directory structure has been created to reflect the
+natural tree like structure of PCI devices. So every directory created
+inside pci_ep represents a EPC device and every directory created inside
+epf directory represents EPF device.
+
+/sys/kernel/config/pci_ep/
+ | <dir>/ --------------------------------------> [2]
+ | epc
+ | epf/
+ | <dir>/ --------------------------> [3]
+ | vendorid
+ | deviceid
+ | revid
+ | progif_code
+ | subclass_code
+ | baseclass_code
+ | cache_line_size
+ | subsys_vendor_id
+ | subsys_id
+ | interrupt_pin
+ | function
+
+*) Creating configfs entry for EPC
+
+Any directory created inside *pci_ep* represents an EPC device. In the above
+directory structure [2] represents an EPC device. It consists of
+
+ *) epc: Use it to associate the configfs entry to an actual EPC device.
+ The list of valid entries for this field can be obtained from
+ ls /sys/class/pci_epc/
+
+ *) epf: Directory that contains all the endpoint functions. The name
+ of the created directory determines the driver this particular
+ epf device will be bound to. The name can be obtained either
+ from the function binding documentation [4] or
+ ls /sys/bus/pci-epf/drivers
+
+ If more than one endpoint function device has to be bound to
+ the same driver, then the directory should be created using
+ the following notation
+ mkdir <name>.<num>
+
+*) Creating configfs entry for EPF
+
+Any directory created inside *epf* directory represents an EPF device. In the
+above directory structure, [3] represents an EPF device. It consists of the
+following entries that can be used to configure the standard configuration
+header of the endpoint function. (These entries are created by the
+framework when any new directory is created inside epf directory.)
+
+ | vendorid
+ | deviceid
+ | revid
+ | progif_code
+ | subclass_code
+ | baseclass_code
+ | cache_line_size
+ | subsys_vendor_id
+ | subsys_id
+ | interrupt_pin
+
+The following entry identifies the function driver that is bound to the
+function device
+ | function
+
+[1] -> Documentation/PCI/endpoint/pci-endpoint.txt
+[4] -> Documentation/PCI/endpoint/function/binding/
--
1.7.9.5
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread* Re: [PATCH v2 04/22] Documentation: PCI: Guide to use pci endpoint configfs
2017-02-17 9:50 ` [PATCH v2 04/22] Documentation: PCI: Guide to use pci endpoint configfs Kishon Vijay Abraham I
@ 2017-02-17 13:05 ` Joao Pinto
2017-02-17 17:15 ` Christoph Hellwig
1 sibling, 0 replies; 49+ messages in thread
From: Joao Pinto @ 2017-02-17 13:05 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
linux-omap, linux-arm-kernel
=C0s 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
> Add Documentation to help users use pci endpoint to configure
> pci endpoint function and to bind the endpoint function
> with endpoint controller.
> =
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> Documentation/PCI/00-INDEX | 2 +
> Documentation/PCI/endpoint/pci-endpoint-cfs.txt | 84 +++++++++++++++++=
++++++
> 2 files changed, 86 insertions(+)
> create mode 100644 Documentation/PCI/endpoint/pci-endpoint-cfs.txt
> =
> diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX
> index ba950b2..f84a23c 100644
> --- a/Documentation/PCI/00-INDEX
> +++ b/Documentation/PCI/00-INDEX
> @@ -14,3 +14,5 @@ pcieaer-howto.txt
> - the PCI Express Advanced Error Reporting Driver Guide HOWTO
> endpoint/pci-endpoint.txt
> - guide to add endpoint controller driver and endpoint function driver.
> +endpoint/pci-endpoint-cfs.txt
> + - guide to use configfs to configure the pci endpoint function.
> diff --git a/Documentation/PCI/endpoint/pci-endpoint-cfs.txt b/Documentat=
ion/PCI/endpoint/pci-endpoint-cfs.txt
> new file mode 100644
> index 0000000..d9f8734
> --- /dev/null
> +++ b/Documentation/PCI/endpoint/pci-endpoint-cfs.txt
> @@ -0,0 +1,84 @@
> + CONFIGURING PCI ENDPOINT USING CONFIGFS
> + Kishon Vijay Abraham I <kishon@ti.com>
> +
> +The PCI Endpoint Core exposes configfs entry (pci_ep) in order to config=
ure the
> +PCI endpoint function and in order to bind the endpoint function
> +with the endpoint controller. (For introducing other mechanisms to
> +configure the PCI Endpoint Function refer [1]).
> +
> +*) Mounting configfs
> +
> +The PCI Endpoint Core layer creates pci_ep directory in the mounted conf=
igfs
> +directory. configfs can be mounted using the following command.
> +
> + mount -t configfs none /sys/kernel/config
> +
> +*) Directory Structure
> +
> +The pci_ep configfs directory structure has been created to reflect the
> +natural tree like structure of PCI devices. So every directory created
> +inside pci_ep represents a EPC device and every directory created inside
> +epf directory represents EPF device.
> +
> +/sys/kernel/config/pci_ep/
> + | <dir>/ --------------------------------------> [2]
> + | epc
> + | epf/
> + | <dir>/ --------------------------> [3]
> + | vendorid
> + | deviceid
> + | revid
> + | progif_code
> + | subclass_code
> + | baseclass_code
> + | cache_line_size
> + | subsys_vendor_id
> + | subsys_id
> + | interrupt_pin
> + | function
> +
> +*) Creating configfs entry for EPC
> +
> +Any directory created inside *pci_ep* represents an EPC device. In the a=
bove
> +directory structure [2] represents an EPC device. It consists of
> +
> + *) epc: Use it to associate the configfs entry to an actual EPC device.
> + The list of valid entries for this field can be obtained from
> + ls /sys/class/pci_epc/
> +
> + *) epf: Directory that contains all the endpoint functions. The name
> + of the created directory determines the driver this particular
> + epf device will be bound to. The name can be obtained either
> + from the function binding documentation [4] or
> + ls /sys/bus/pci-epf/drivers
> +
> + If more than one endpoint function device has to be bound to
> + the same driver, then the directory should be created using
> + the following notation
> + mkdir <name>.<num>
> +
> +*) Creating configfs entry for EPF
> +
> +Any directory created inside *epf* directory represents an EPF device. I=
n the
> +above directory structure, [3] represents an EPF device. It consists of =
the
> +following entries that can be used to configure the standard configurati=
on
> +header of the endpoint function. (These entries are created by the
> +framework when any new directory is created inside epf directory.)
> +
> + | vendorid
> + | deviceid
> + | revid
> + | progif_code
> + | subclass_code
> + | baseclass_code
> + | cache_line_size
> + | subsys_vendor_id
> + | subsys_id
> + | interrupt_pin
> +
> +The following entry identifies the function driver that is bound to the
> +function device
> + | function
> +
> +[1] -> Documentation/PCI/endpoint/pci-endpoint.txt
> +[4] -> Documentation/PCI/endpoint/function/binding/
> =
Good content.
Acked-By: Joao Pinto <jpinto@synopsys.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 04/22] Documentation: PCI: Guide to use pci endpoint configfs
2017-02-17 9:50 ` [PATCH v2 04/22] Documentation: PCI: Guide to use pci endpoint configfs Kishon Vijay Abraham I
2017-02-17 13:05 ` Joao Pinto
@ 2017-02-17 17:15 ` Christoph Hellwig
2017-03-06 10:16 ` Kishon Vijay Abraham I
1 sibling, 1 reply; 49+ messages in thread
From: Christoph Hellwig @ 2017-02-17 17:15 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: devicetree, Joao Pinto, linux-doc, Jingoo Han, nsekhar,
linux-kernel, linux-pci, Bjorn Helgaas, linux-omap,
linux-arm-kernel
I'm commenting on the configfs layout here instead of the patch with the
code as the issues are easier to explain that way. I think the layout
is a bit confusing and could be cleaner by making use of pre-created
entries and symlinks. Here is my suggestion:
/sys/kernel/config/pci_ep/functions/
.. test/ # a directory for each function driver
... user-specified-name1/
... user-specified-name2
.. nvme/
... user-specified-name42/
Each directory under /sys/kernel/config/pci_ep/functions/ is owned
by a function drivers. Under that function driver's directory you
can create a directory for each instance of a function driver. The
configfs layout is controlled by the function driver. E.g. your current
EPF fields would move into the test function driver, while the nvme
function would expose totally different fields.
/sys/kernel/config/pci_ep/controllers/
... dwc-0/
... function
... dwc-1/
... function
... vhost-0/
... function
Here you have a directory for each controller that can be bound
to a function. The directories are pre-created for each
controller port that is EP capable.
Function is a symlink to the function instance above.
Additional parameters might also be present depending on the
EPC driver.
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 04/22] Documentation: PCI: Guide to use pci endpoint configfs
2017-02-17 17:15 ` Christoph Hellwig
@ 2017-03-06 10:16 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-03-06 10:16 UTC (permalink / raw)
To: Christoph Hellwig
Cc: devicetree, Joao Pinto, linux-doc, Jingoo Han, nsekhar,
linux-kernel, linux-pci, Bjorn Helgaas, linux-omap,
linux-arm-kernel
Hi,
On Friday 17 February 2017 10:45 PM, Christoph Hellwig wrote:
> I'm commenting on the configfs layout here instead of the patch with the
> code as the issues are easier to explain that way. I think the layout
> is a bit confusing and could be cleaner by making use of pre-created
> entries and symlinks. Here is my suggestion:
>
> /sys/kernel/config/pci_ep/functions/
> .. test/ # a directory for each function driver
> ... user-specified-name1/
> ... user-specified-name2
> .. nvme/
> ... user-specified-name42/
>
> Each directory under /sys/kernel/config/pci_ep/functions/ is owned
> by a function drivers. Under that function driver's directory you
> can create a directory for each instance of a function driver. The
> configfs layout is controlled by the function driver. E.g. your current
> EPF fields would move into the test function driver, while the nvme
> function would expose totally different fields.
>
>
> /sys/kernel/config/pci_ep/controllers/
> ... dwc-0/
> ... function
> ... dwc-1/
> ... function
> ... vhost-0/
> ... function
>
> Here you have a directory for each controller that can be bound
> to a function. The directories are pre-created for each
> controller port that is EP capable.
> Function is a symlink to the function instance above.
> Additional parameters might also be present depending on the
> EPC driver.
I've changed the configfs entry according to your suggestion. However I've
considered only the generic test function and a standard EP controller and
implemented the configfs in a single file pci-ep-cfs.c. But I think this will
get more complex as we add custom parameters for individual EPC, new functions
etc..
Thanks
Kishon
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 05/22] Documentation: PCI: Add specification for the *pci test* function device
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
` (3 preceding siblings ...)
2017-02-17 9:50 ` [PATCH v2 04/22] Documentation: PCI: Guide to use pci endpoint configfs Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-17 9:50 ` [PATCH v2 06/22] PCI: endpoint: functions: Add an EP function to test PCI Kishon Vijay Abraham I
` (16 subsequent siblings)
21 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: linux-pci, linux-doc, linux-kernel, devicetree, linux-omap,
linux-arm-kernel, nsekhar, Kishon Vijay Abraham I
Add specification for the *pci test* virtual function device. The endpoint
function driver and the host pci driver should be created based on this
specification.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Documentation/PCI/00-INDEX | 2 +
Documentation/PCI/endpoint/pci-test-function.txt | 66 ++++++++++++++++++++++
2 files changed, 68 insertions(+)
create mode 100644 Documentation/PCI/endpoint/pci-test-function.txt
diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX
index f84a23c..4e5a283 100644
--- a/Documentation/PCI/00-INDEX
+++ b/Documentation/PCI/00-INDEX
@@ -16,3 +16,5 @@ endpoint/pci-endpoint.txt
- guide to add endpoint controller driver and endpoint function driver.
endpoint/pci-endpoint-cfs.txt
- guide to use configfs to configure the pci endpoint function.
+endpoint/pci-test-function.txt
+ - specification of *pci test* function device.
diff --git a/Documentation/PCI/endpoint/pci-test-function.txt b/Documentation/PCI/endpoint/pci-test-function.txt
new file mode 100644
index 0000000..1324376
--- /dev/null
+++ b/Documentation/PCI/endpoint/pci-test-function.txt
@@ -0,0 +1,66 @@
+ PCI TEST
+ Kishon Vijay Abraham I <kishon@ti.com>
+
+Traditionally PCI RC has always been validated by using standard
+PCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards.
+However with the addition of EP-core in linux kernel, it is possible
+to configure a PCI controller that can operate in EP mode to work as
+a test device.
+
+The PCI endpoint test device is a virtual device (defined in software)
+used to test the endpoint functionality and serve as a sample driver
+for other PCI endpoint devices (to use the EP framework).
+
+The PCI endpoint test device has the following registers:
+
+ 1) PCI_ENDPOINT_TEST_MAGIC
+ 2) PCI_ENDPOINT_TEST_COMMAND
+ 3) PCI_ENDPOINT_TEST_STATUS
+ 4) PCI_ENDPOINT_TEST_SRC_ADDR
+ 5) PCI_ENDPOINT_TEST_DST_ADDR
+ 6) PCI_ENDPOINT_TEST_SIZE
+ 7) PCI_ENDPOINT_TEST_CHECKSUM
+
+*) PCI_ENDPOINT_TEST_MAGIC
+
+This register will be used to test BAR0. A known pattern will be written
+and read back from MAGIC register to verify BAR0.
+
+*) PCI_ENDPOINT_TEST_COMMAND:
+
+This register will be used by the host driver to indicate the function
+that the endpoint device must perform.
+
+Bitfield Description:
+ Bit 0 : raise legacy irq
+ Bit 1 : raise MSI irq
+ Bit 2 - 7 : MSI interrupt number
+ Bit 8 : read command (read data from RC buffer)
+ Bit 9 : write command (write data to RC buffer)
+ Bit 10 : copy command (copy data from one RC buffer to another
+ RC buffer)
+
+*) PCI_ENDPOINT_TEST_STATUS
+
+This register reflects the status of the PCI endpoint device.
+
+Bitfield Description:
+ Bit 0 : read success
+ Bit 1 : read fail
+ Bit 2 : write success
+ Bit 3 : write fail
+ Bit 4 : copy success
+ Bit 5 : copy fail
+ Bit 6 : irq raised
+ Bit 7 : source address is invalid
+ Bit 8 : destination address is invalid
+
+*) PCI_ENDPOINT_TEST_SRC_ADDR
+
+This register contains the source address (RC buffer address) for the
+COPY/READ command.
+
+*) PCI_ENDPOINT_TEST_DST_ADDR
+
+This register contains the destination address (RC buffer address) for
+the COPY/WRITE command.
--
1.7.9.5
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 06/22] PCI: endpoint: functions: Add an EP function to test PCI
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
` (4 preceding siblings ...)
2017-02-17 9:50 ` [PATCH v2 05/22] Documentation: PCI: Add specification for the *pci test* function device Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-17 9:50 ` [PATCH v2 07/22] Documentation: PCI: Add binding documentation for pci-test endpoint function Kishon Vijay Abraham I
` (15 subsequent siblings)
21 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: linux-pci, linux-doc, linux-kernel, devicetree, linux-omap,
linux-arm-kernel, nsekhar, Kishon Vijay Abraham I
Adds a new endpoint function driver (to program the virtual
test device) making use of the EP-core library.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/endpoint/Kconfig | 2 +
drivers/pci/endpoint/Makefile | 2 +-
drivers/pci/endpoint/functions/Kconfig | 12 +
drivers/pci/endpoint/functions/Makefile | 5 +
drivers/pci/endpoint/functions/pci-epf-test.c | 513 +++++++++++++++++++++++++
5 files changed, 533 insertions(+), 1 deletion(-)
create mode 100644 drivers/pci/endpoint/functions/Kconfig
create mode 100644 drivers/pci/endpoint/functions/Makefile
create mode 100644 drivers/pci/endpoint/functions/pci-epf-test.c
diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig
index 8470f0b..f8455d7 100644
--- a/drivers/pci/endpoint/Kconfig
+++ b/drivers/pci/endpoint/Kconfig
@@ -28,4 +28,6 @@ config PCI_ENDPOINT_CONFIGFS
configure the endpoint function and used to bind the
function with a endpoint controller.
+source "drivers/pci/endpoint/functions/Kconfig"
+
endmenu
diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile
index dd9163c..a3d4c57 100644
--- a/drivers/pci/endpoint/Makefile
+++ b/drivers/pci/endpoint/Makefile
@@ -3,5 +3,5 @@
#
obj-$(CONFIG_PCI_ENDPOINT) += pci-epc-core.o pci-epf-core.o\
- pci-epc-mem.o
+ pci-epc-mem.o functions/
obj-$(CONFIG_PCI_ENDPOINT_CONFIGFS) += pci-ep-cfs.o
diff --git a/drivers/pci/endpoint/functions/Kconfig b/drivers/pci/endpoint/functions/Kconfig
new file mode 100644
index 0000000..175edad
--- /dev/null
+++ b/drivers/pci/endpoint/functions/Kconfig
@@ -0,0 +1,12 @@
+#
+# PCI Endpoint Functions
+#
+
+config PCI_EPF_TEST
+ tristate "PCI Endpoint Test driver"
+ depends on PCI_ENDPOINT
+ help
+ Enable this configuration option to enable the test driver
+ for PCI Endpoint.
+
+ If in doubt, say "N" to disable Endpoint test driver.
diff --git a/drivers/pci/endpoint/functions/Makefile b/drivers/pci/endpoint/functions/Makefile
new file mode 100644
index 0000000..6d94a48
--- /dev/null
+++ b/drivers/pci/endpoint/functions/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for PCI Endpoint Functions
+#
+
+obj-$(CONFIG_PCI_EPF_TEST) += pci-epf-test.o
diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
new file mode 100644
index 0000000..bbac323
--- /dev/null
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -0,0 +1,513 @@
+/**
+ * Test driver to test endpoint functionality
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/crc32.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/pci_ids.h>
+#include <linux/random.h>
+
+#include <linux/pci-epc.h>
+#include <linux/pci-epf.h>
+#include <linux/pci_regs.h>
+
+#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
+#define COMMAND_RAISE_MSI_IRQ BIT(1)
+#define MSI_NUMBER_SHIFT 2
+#define MSI_NUMBER_MASK (0x3f << MSI_NUMBER_SHIFT)
+#define COMMAND_READ BIT(8)
+#define COMMAND_WRITE BIT(9)
+#define COMMAND_COPY BIT(10)
+
+#define STATUS_READ_SUCCESS BIT(0)
+#define STATUS_READ_FAIL BIT(1)
+#define STATUS_WRITE_SUCCESS BIT(2)
+#define STATUS_WRITE_FAIL BIT(3)
+#define STATUS_COPY_SUCCESS BIT(4)
+#define STATUS_COPY_FAIL BIT(5)
+#define STATUS_IRQ_RAISED BIT(6)
+#define STATUS_SRC_ADDR_INVALID BIT(7)
+#define STATUS_DST_ADDR_INVALID BIT(8)
+
+#define TIMER_RESOLUTION 1
+
+static struct workqueue_struct *kpcitest_workqueue;
+
+struct pci_epf_test {
+ void *reg[6];
+ struct pci_epf *epf;
+ struct delayed_work cmd_handler;
+};
+
+struct pci_epf_test_reg {
+ u32 magic;
+ u32 command;
+ u32 status;
+ u64 src_addr;
+ u64 dst_addr;
+ u32 size;
+ u32 checksum;
+} __packed;
+
+static struct pci_epf_header test_header = {
+ .vendorid = PCI_ANY_ID,
+ .deviceid = PCI_ANY_ID,
+ .baseclass_code = PCI_CLASS_OTHERS,
+ .interrupt_pin = PCI_INTERRUPT_INTA,
+};
+
+static int bar_size[] = { 512, 1024, 16384, 131072, 1048576 };
+
+static int pci_epf_test_copy(struct pci_epf_test *epf_test)
+{
+ int ret;
+ void __iomem *src_addr;
+ void __iomem *dst_addr;
+ phys_addr_t src_phys_addr;
+ phys_addr_t dst_phys_addr;
+ struct pci_epf *epf = epf_test->epf;
+ struct device *dev = &epf->dev;
+ struct pci_epc *epc = epf->epc;
+ struct pci_epf_test_reg *reg = epf_test->reg[0];
+
+ src_addr = pci_epc_mem_alloc_addr(epc, &src_phys_addr, reg->size);
+ if (!src_addr) {
+ dev_err(dev, "failed to allocate source address\n");
+ reg->status = STATUS_SRC_ADDR_INVALID;
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ ret = pci_epc_map_addr(epc, src_phys_addr, reg->src_addr, reg->size);
+ if (ret) {
+ dev_err(dev, "failed to map source address\n");
+ reg->status = STATUS_SRC_ADDR_INVALID;
+ goto err_src_addr;
+ }
+
+ dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, reg->size);
+ if (!dst_addr) {
+ dev_err(dev, "failed to allocate destination address\n");
+ reg->status = STATUS_DST_ADDR_INVALID;
+ ret = -ENOMEM;
+ goto err_src_map_addr;
+ }
+
+ ret = pci_epc_map_addr(epc, dst_phys_addr, reg->dst_addr, reg->size);
+ if (ret) {
+ dev_err(dev, "failed to map destination address\n");
+ reg->status = STATUS_DST_ADDR_INVALID;
+ goto err_dst_addr;
+ }
+
+ memcpy(dst_addr, src_addr, reg->size);
+
+ pci_epc_unmap_addr(epc, dst_phys_addr);
+
+err_dst_addr:
+ pci_epc_mem_free_addr(epc, dst_phys_addr, dst_addr, reg->size);
+
+err_src_map_addr:
+ pci_epc_unmap_addr(epc, src_phys_addr);
+
+err_src_addr:
+ pci_epc_mem_free_addr(epc, src_phys_addr, src_addr, reg->size);
+
+err:
+ return ret;
+}
+
+static int pci_epf_test_read(struct pci_epf_test *epf_test)
+{
+ int ret;
+ void __iomem *src_addr;
+ void *buf;
+ u32 crc32;
+ phys_addr_t phys_addr;
+ struct pci_epf *epf = epf_test->epf;
+ struct device *dev = &epf->dev;
+ struct pci_epc *epc = epf->epc;
+ struct pci_epf_test_reg *reg = epf_test->reg[0];
+
+ src_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size);
+ if (!src_addr) {
+ dev_err(dev, "failed to allocate address\n");
+ reg->status = STATUS_SRC_ADDR_INVALID;
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ ret = pci_epc_map_addr(epc, phys_addr, reg->src_addr, reg->size);
+ if (ret) {
+ dev_err(dev, "failed to map address\n");
+ reg->status = STATUS_SRC_ADDR_INVALID;
+ goto err_addr;
+ }
+
+ buf = kzalloc(reg->size, GFP_KERNEL);
+ if (!buf) {
+ ret = -ENOMEM;
+ goto err_map_addr;
+ }
+
+ memcpy(buf, src_addr, reg->size);
+
+ crc32 = crc32_le(~0, buf, reg->size);
+ if (crc32 != reg->checksum)
+ ret = -EIO;
+
+ kfree(buf);
+
+err_map_addr:
+ pci_epc_unmap_addr(epc, phys_addr);
+
+err_addr:
+ pci_epc_mem_free_addr(epc, phys_addr, src_addr, reg->size);
+
+err:
+ return ret;
+}
+
+static int pci_epf_test_write(struct pci_epf_test *epf_test)
+{
+ int ret;
+ void __iomem *dst_addr;
+ void *buf;
+ phys_addr_t phys_addr;
+ struct pci_epf *epf = epf_test->epf;
+ struct device *dev = &epf->dev;
+ struct pci_epc *epc = epf->epc;
+ struct pci_epf_test_reg *reg = epf_test->reg[0];
+
+ dst_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size);
+ if (!dst_addr) {
+ dev_err(dev, "failed to allocate address\n");
+ reg->status = STATUS_DST_ADDR_INVALID;
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ ret = pci_epc_map_addr(epc, phys_addr, reg->dst_addr, reg->size);
+ if (ret) {
+ dev_err(dev, "failed to map address\n");
+ reg->status = STATUS_DST_ADDR_INVALID;
+ goto err_addr;
+ }
+
+ buf = kzalloc(reg->size, GFP_KERNEL);
+ if (!buf) {
+ ret = -ENOMEM;
+ goto err_map_addr;
+ }
+
+ get_random_bytes(buf, reg->size);
+ reg->checksum = crc32_le(~0, buf, reg->size);
+
+ memcpy(dst_addr, buf, reg->size);
+
+ /*
+ * wait 1ms inorder for the write to complete. Without this delay L3
+ * error in observed in the host system.
+ */
+ mdelay(1);
+
+ kfree(buf);
+
+err_map_addr:
+ pci_epc_unmap_addr(epc, phys_addr);
+
+err_addr:
+ pci_epc_mem_free_addr(epc, phys_addr, dst_addr, reg->size);
+
+err:
+ return ret;
+}
+
+static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test)
+{
+ u8 irq;
+ u8 msi_count;
+ struct pci_epf *epf = epf_test->epf;
+ struct pci_epc *epc = epf->epc;
+ struct pci_epf_test_reg *reg = epf_test->reg[0];
+
+ reg->status |= STATUS_IRQ_RAISED;
+ msi_count = pci_epc_get_msi(epc);
+ irq = (reg->command & MSI_NUMBER_MASK) >> MSI_NUMBER_SHIFT;
+ if (irq > msi_count || msi_count <= 0)
+ pci_epc_raise_irq(epc, PCI_EPC_IRQ_LEGACY, 0);
+ else
+ pci_epc_raise_irq(epc, PCI_EPC_IRQ_MSI, irq);
+}
+
+static void pci_epf_test_cmd_handler(struct work_struct *work)
+{
+ int ret;
+ u8 irq;
+ u8 msi_count;
+ struct pci_epf_test *epf_test = container_of(work, struct pci_epf_test,
+ cmd_handler.work);
+ struct pci_epf *epf = epf_test->epf;
+ struct pci_epc *epc = epf->epc;
+ struct pci_epf_test_reg *reg = epf_test->reg[0];
+
+ if (!reg->command)
+ goto reset_handler;
+
+ if (reg->command & COMMAND_RAISE_LEGACY_IRQ) {
+ reg->status = STATUS_IRQ_RAISED;
+ pci_epc_raise_irq(epc, PCI_EPC_IRQ_LEGACY, 0);
+ goto reset_handler;
+ }
+
+ if (reg->command & COMMAND_WRITE) {
+ ret = pci_epf_test_write(epf_test);
+ if (ret)
+ reg->status |= STATUS_WRITE_FAIL;
+ else
+ reg->status |= STATUS_WRITE_SUCCESS;
+ pci_epf_test_raise_irq(epf_test);
+ goto reset_handler;
+ }
+
+ if (reg->command & COMMAND_READ) {
+ ret = pci_epf_test_read(epf_test);
+ if (!ret)
+ reg->status |= STATUS_READ_SUCCESS;
+ else
+ reg->status |= STATUS_READ_FAIL;
+ pci_epf_test_raise_irq(epf_test);
+ goto reset_handler;
+ }
+
+ if (reg->command & COMMAND_COPY) {
+ ret = pci_epf_test_copy(epf_test);
+ if (!ret)
+ reg->status |= STATUS_COPY_SUCCESS;
+ else
+ reg->status |= STATUS_COPY_FAIL;
+ pci_epf_test_raise_irq(epf_test);
+ goto reset_handler;
+ }
+
+ if (reg->command & COMMAND_RAISE_MSI_IRQ) {
+ msi_count = pci_epc_get_msi(epc);
+ irq = (reg->command & MSI_NUMBER_MASK) >> MSI_NUMBER_SHIFT;
+ if (irq > msi_count || msi_count <= 0)
+ goto reset_handler;
+ reg->status = STATUS_IRQ_RAISED;
+ pci_epc_raise_irq(epc, PCI_EPC_IRQ_MSI, irq);
+ goto reset_handler;
+ }
+
+reset_handler:
+ reg->command = 0;
+
+ queue_delayed_work(kpcitest_workqueue, &epf_test->cmd_handler,
+ msecs_to_jiffies(1));
+}
+
+static void pci_epf_test_linkup(struct pci_epf *epf)
+{
+ struct pci_epf_test *epf_test = epf_get_drvdata(epf);
+
+ queue_delayed_work(kpcitest_workqueue, &epf_test->cmd_handler,
+ msecs_to_jiffies(1));
+}
+
+static void pci_epf_test_unbind(struct pci_epf *epf)
+{
+ struct pci_epf_test *epf_test = epf_get_drvdata(epf);
+ struct pci_epc *epc = epf->epc;
+ int bar;
+
+ cancel_delayed_work(&epf_test->cmd_handler);
+ pci_epc_stop(epc);
+ for (bar = BAR_0; bar <= BAR_5; bar++) {
+ if (epf_test->reg[bar]) {
+ pci_epf_free_space(epf, epf_test->reg[bar], bar);
+ pci_epc_clear_bar(epc, bar);
+ }
+ }
+}
+
+static int pci_epf_test_set_bar(struct pci_epf *epf)
+{
+ int flags;
+ int bar;
+ int ret;
+ struct pci_epf_bar *epf_bar;
+ struct pci_epc *epc = epf->epc;
+ struct device *dev = &epf->dev;
+ struct pci_epf_test *epf_test = epf_get_drvdata(epf);
+
+ flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32;
+ if (sizeof(dma_addr_t) == 0x8)
+ flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
+
+ for (bar = BAR_0; bar <= BAR_5; bar++) {
+ epf_bar = &epf->bar[bar];
+ ret = pci_epc_set_bar(epc, bar, epf_bar->phys_addr,
+ epf_bar->size, flags);
+ if (ret) {
+ pci_epf_free_space(epf, epf_test->reg[bar], bar);
+ dev_err(dev, "failed to set BAR%d\n", bar);
+ if (bar == BAR_0)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int pci_epf_test_alloc_space(struct pci_epf *epf)
+{
+ struct pci_epf_test *epf_test = epf_get_drvdata(epf);
+ struct device *dev = &epf->dev;
+ void *base;
+ int bar;
+
+ base = pci_epf_alloc_space(epf, sizeof(struct pci_epf_test_reg),
+ BAR_0);
+ if (!base) {
+ dev_err(dev, "failed to allocated register space\n");
+ return -ENOMEM;
+ }
+ epf_test->reg[0] = base;
+
+ for (bar = BAR_1; bar <= BAR_5; bar++) {
+ base = pci_epf_alloc_space(epf, bar_size[bar - 1], bar);
+ if (!base)
+ dev_err(dev, "failed to allocate space for BAR%d\n",
+ bar);
+ epf_test->reg[bar] = base;
+ }
+
+ return 0;
+}
+
+static int pci_epf_test_bind(struct pci_epf *epf)
+{
+ int ret;
+ struct pci_epf_header *header = epf->header;
+ struct pci_epc *epc = epf->epc;
+ struct device *dev = &epf->dev;
+
+ ret = pci_epc_write_header(epc, header);
+ if (ret) {
+ dev_err(dev, "configuration header write failed\n");
+ return ret;
+ }
+
+ ret = pci_epf_test_alloc_space(epf);
+ if (ret)
+ return ret;
+
+ ret = pci_epf_test_set_bar(epf);
+ if (ret)
+ return ret;
+
+ ret = pci_epc_set_msi(epc, epf->msi_interrupts);
+ if (ret)
+ return ret;
+
+ ret = pci_epc_start(epc);
+ if (ret) {
+ dev_err(dev, "failed to start endpoint controller\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int pci_epf_test_probe(struct pci_epf *epf)
+{
+ struct pci_epf_test *epf_test;
+ struct device *dev = &epf->dev;
+
+ epf_test = devm_kzalloc(dev, sizeof(*epf_test), GFP_KERNEL);
+ if (!epf)
+ return -ENOMEM;
+
+ epf->header = &test_header;
+ epf_test->epf = epf;
+
+ INIT_DELAYED_WORK(&epf_test->cmd_handler, pci_epf_test_cmd_handler);
+
+ epf_set_drvdata(epf, epf_test);
+ return 0;
+}
+
+static int pci_epf_test_remove(struct pci_epf *epf)
+{
+ struct pci_epf_test *epf_test = epf_get_drvdata(epf);
+
+ kfree(epf_test);
+ return 0;
+}
+
+static struct pci_epf_ops ops = {
+ .unbind = pci_epf_test_unbind,
+ .bind = pci_epf_test_bind,
+ .linkup = pci_epf_test_linkup,
+};
+
+static const struct pci_epf_device_id pci_epf_test_ids[] = {
+ {
+ .name = "pci_epf_test",
+ },
+ {},
+};
+
+static struct pci_epf_driver test_driver = {
+ .driver.name = "pci_epf_test",
+ .probe = pci_epf_test_probe,
+ .remove = pci_epf_test_remove,
+ .id_table = pci_epf_test_ids,
+ .ops = &ops,
+ .owner = THIS_MODULE,
+};
+
+static int __init pci_epf_test_init(void)
+{
+ int ret;
+
+ kpcitest_workqueue = alloc_workqueue("kpcitest",
+ WQ_MEM_RECLAIM | WQ_HIGHPRI, 0);
+ ret = pci_epf_register_driver(&test_driver);
+ if (ret) {
+ pr_err("failed to register pci epf test driver --> %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+module_init(pci_epf_test_init);
+
+static void __exit pci_epf_test_exit(void)
+{
+ pci_epf_unregister_driver(&test_driver);
+}
+module_exit(pci_epf_test_exit);
+
+MODULE_DESCRIPTION("PCI EPF TEST DRIVER");
+MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
+MODULE_LICENSE("GPL v2");
--
1.7.9.5
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 07/22] Documentation: PCI: Add binding documentation for pci-test endpoint function
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
` (5 preceding siblings ...)
2017-02-17 9:50 ` [PATCH v2 06/22] PCI: endpoint: functions: Add an EP function to test PCI Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-17 9:50 ` [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support Kishon Vijay Abraham I
` (14 subsequent siblings)
21 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
Kishon Vijay Abraham I, linux-omap, linux-arm-kernel
Add binding documentation for pci-test endpoint function that helps in
adding and configuring pci-test endpoint function.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Documentation/PCI/00-INDEX | 2 ++
.../PCI/endpoint/function/binding/pci-test.txt | 17 +++++++++++++++++
2 files changed, 19 insertions(+)
create mode 100644 Documentation/PCI/endpoint/function/binding/pci-test.txt
diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX
index 4e5a283..53717b7 100644
--- a/Documentation/PCI/00-INDEX
+++ b/Documentation/PCI/00-INDEX
@@ -18,3 +18,5 @@ endpoint/pci-endpoint-cfs.txt
- guide to use configfs to configure the pci endpoint function.
endpoint/pci-test-function.txt
- specification of *pci test* function device.
+endpoint/function/binding/
+ - binding documentation for pci endpoint function
diff --git a/Documentation/PCI/endpoint/function/binding/pci-test.txt b/Documentation/PCI/endpoint/function/binding/pci-test.txt
new file mode 100644
index 0000000..7358240
--- /dev/null
+++ b/Documentation/PCI/endpoint/function/binding/pci-test.txt
@@ -0,0 +1,17 @@
+PCI TEST ENDPOINT FUNCTION
+
+name: Should be "pci_epf_test" to bind to the pci_epf_test driver.
+
+Configurable Fields:
+vendorid : should be 0x104c
+deviceid : should be 0xffff
+revid : dont't care
+progif_code : don't care
+subclass_code : don't care
+baseclass_code : should be 0xff
+cache_line_size : don't care
+subsys_vendor_id : don't care
+subsys_id : don't care
+interrupt_pin : Should be 1 - INTA, 2 - INTB, 3 - INTC, 4 -INTD
+msi_interrupts : Should be 1 to 32 depending on the number of msi interrupts
+ to test
--
1.7.9.5
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
` (6 preceding siblings ...)
2017-02-17 9:50 ` [PATCH v2 07/22] Documentation: PCI: Add binding documentation for pci-test endpoint function Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-17 13:15 ` Kishon Vijay Abraham I
2017-02-17 17:20 ` Joao Pinto
2017-02-17 9:50 ` [PATCH v2 09/22] dt-bindings: PCI: Add dt bindings for pci designware EP mode Kishon Vijay Abraham I
` (13 subsequent siblings)
21 siblings, 2 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
Kishon Vijay Abraham I, linux-omap, linux-arm-kernel
Add endpoint mode support to designware driver. This uses the
EP Core layer introduced recently to add endpoint mode support.
*Any* function driver can now use this designware device
in order to achieve the EP functionality.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/dwc/Kconfig | 5 +
drivers/pci/dwc/Makefile | 1 +
drivers/pci/dwc/pcie-designware-ep.c | 342 ++++++++++++++++++++++++++++++++++
drivers/pci/dwc/pcie-designware.c | 51 +++++
drivers/pci/dwc/pcie-designware.h | 72 +++++++
5 files changed, 471 insertions(+)
create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
index dfb8a69..00335c7 100644
--- a/drivers/pci/dwc/Kconfig
+++ b/drivers/pci/dwc/Kconfig
@@ -9,6 +9,11 @@ config PCIE_DW_HOST
depends on PCI_MSI_IRQ_DOMAIN
select PCIE_DW
+config PCIE_DW_EP
+ bool
+ depends on PCI_ENDPOINT
+ select PCIE_DW
+
config PCI_DRA7XX
bool "TI DRA7xx PCIe controller"
depends on PCI
diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
index a2df13c..b38425d 100644
--- a/drivers/pci/dwc/Makefile
+++ b/drivers/pci/dwc/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_PCIE_DW) += pcie-designware.o
obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
+obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
new file mode 100644
index 0000000..e465c5e
--- /dev/null
+++ b/drivers/pci/dwc/pcie-designware-ep.c
@@ -0,0 +1,342 @@
+/**
+ * Synopsys Designware PCIe Endpoint controller driver
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/of.h>
+
+#include "pcie-designware.h"
+#include <linux/pci-epc.h>
+#include <linux/pci-epf.h>
+
+void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
+{
+ struct pci_epc *epc = ep->epc;
+ struct pci_epf *epf;
+
+ list_for_each_entry(epf, &epc->pci_epf, list)
+ pci_epf_linkup(epf);
+}
+
+static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
+{
+ u32 reg;
+
+ reg = PCI_BASE_ADDRESS_0 + (4 * bar);
+ dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, 0x0);
+ dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, 0x0);
+}
+
+static int dw_pcie_ep_write_header(struct pci_epc *epc,
+ struct pci_epf_header *hdr)
+{
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ void __iomem *base = pci->dbi_base;
+
+ dw_pcie_write_dbi(pci, base, PCI_VENDOR_ID, 0x2, hdr->vendorid);
+ dw_pcie_write_dbi(pci, base, PCI_DEVICE_ID, 0x2, hdr->deviceid);
+ dw_pcie_write_dbi(pci, base, PCI_REVISION_ID, 0x1, hdr->revid);
+ dw_pcie_write_dbi(pci, base, PCI_CLASS_PROG, 0x1, hdr->progif_code);
+ dw_pcie_write_dbi(pci, base, PCI_CLASS_DEVICE, 0x2,
+ hdr->subclass_code | hdr->baseclass_code << 8);
+ dw_pcie_write_dbi(pci, base, PCI_CACHE_LINE_SIZE, 0x1,
+ hdr->cache_line_size);
+ dw_pcie_write_dbi(pci, base, PCI_SUBSYSTEM_VENDOR_ID, 0x2,
+ hdr->subsys_vendor_id);
+ dw_pcie_write_dbi(pci, base, PCI_SUBSYSTEM_ID, 0x2, hdr->subsys_id);
+ dw_pcie_write_dbi(pci, base, PCI_INTERRUPT_PIN, 0x1,
+ hdr->interrupt_pin);
+
+ return 0;
+}
+
+static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
+ dma_addr_t cpu_addr,
+ enum dw_pcie_as_type as_type)
+{
+ int ret;
+ u32 free_win;
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+
+ free_win = find_first_zero_bit(&ep->ib_window_map,
+ sizeof(ep->ib_window_map));
+ if (free_win >= ep->num_ib_windows) {
+ dev_err(pci->dev, "no free inbound window\n");
+ return -EINVAL;
+ }
+
+ ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr,
+ as_type);
+ if (ret < 0) {
+ dev_err(pci->dev, "Failed to program IB window\n");
+ return ret;
+ }
+
+ ep->bar_to_atu[bar] = free_win;
+ set_bit(free_win, &ep->ib_window_map);
+
+ return 0;
+}
+
+static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr,
+ u64 pci_addr, size_t size)
+{
+ u32 free_win;
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+
+ free_win = find_first_zero_bit(&ep->ob_window_map,
+ sizeof(ep->ob_window_map));
+ if (free_win >= ep->num_ob_windows) {
+ dev_err(pci->dev, "no free outbound window\n");
+ return -EINVAL;
+ }
+
+ dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
+ phys_addr, pci_addr, size);
+
+ set_bit(free_win, &ep->ob_window_map);
+ ep->outbound_addr[free_win] = phys_addr;
+
+ return 0;
+}
+
+static void dw_pcie_ep_clear_bar(struct pci_epc *epc, enum pci_barno bar)
+{
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ u32 atu_index = ep->bar_to_atu[bar];
+
+ dw_pcie_ep_reset_bar(pci, bar);
+
+ dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
+ clear_bit(atu_index, &ep->ib_window_map);
+}
+
+static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar,
+ dma_addr_t bar_phys, size_t size, int flags)
+{
+ int ret;
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ enum dw_pcie_as_type as_type;
+ u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
+
+ if (!(flags & PCI_BASE_ADDRESS_SPACE))
+ as_type = DW_PCIE_AS_MEM;
+ else
+ as_type = DW_PCIE_AS_IO;
+
+ ret = dw_pcie_ep_inbound_atu(ep, bar, bar_phys, as_type);
+ if (ret)
+ return ret;
+
+ dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, size - 1);
+ dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, flags);
+
+ return 0;
+}
+
+static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr,
+ u32 *atu_index)
+{
+ u32 index;
+
+ for (index = 0; index < ep->num_ob_windows; index++) {
+ if (ep->outbound_addr[index] != addr)
+ continue;
+ *atu_index = index;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, phys_addr_t addr)
+{
+ int ret;
+ u32 atu_index;
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+
+ ret = dw_pcie_find_index(ep, addr, &atu_index);
+ if (ret < 0)
+ return;
+
+ dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND);
+ clear_bit(atu_index, &ep->ob_window_map);
+}
+
+static int dw_pcie_ep_map_addr(struct pci_epc *epc, phys_addr_t addr,
+ u64 pci_addr, size_t size)
+{
+ int ret;
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+
+ ret = dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size);
+ if (ret) {
+ dev_err(pci->dev, "failed to enable address\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int dw_pcie_ep_get_msi(struct pci_epc *epc)
+{
+ int val;
+ u32 lower_addr;
+ u32 upper_addr;
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+
+ val = dw_pcie_read_dbi(pci, pci->dbi_base, MSI_MESSAGE_CONTROL, 0x2);
+ val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
+
+ lower_addr = dw_pcie_read_dbi(pci, pci->dbi_base, MSI_MESSAGE_ADDR_L32,
+ 0x4);
+ upper_addr = dw_pcie_read_dbi(pci, pci->dbi_base, MSI_MESSAGE_ADDR_U32,
+ 0x4);
+
+ if (!(lower_addr || upper_addr))
+ return -EINVAL;
+
+ return val;
+}
+
+static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int)
+{
+ int val;
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+
+ val = (encode_int << MSI_CAP_MMC_SHIFT);
+ dw_pcie_write_dbi(pci, pci->dbi_base, MSI_MESSAGE_CONTROL, 0x2, val);
+
+ return 0;
+}
+
+static int dw_pcie_ep_raise_irq(struct pci_epc *epc,
+ enum pci_epc_irq_type type, u8 interrupt_num)
+{
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+
+ if (!ep->ops->raise_irq)
+ return -EINVAL;
+
+ return ep->ops->raise_irq(ep, type, interrupt_num);
+}
+
+static void dw_pcie_ep_stop(struct pci_epc *epc)
+{
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+
+ if (!pci->ops->stop_link)
+ return;
+
+ pci->ops->stop_link(pci);
+}
+
+static int dw_pcie_ep_start(struct pci_epc *epc)
+{
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+
+ if (!pci->ops->start_link)
+ return -EINVAL;
+
+ return pci->ops->start_link(pci);
+}
+
+static const struct pci_epc_ops epc_ops = {
+ .write_header = dw_pcie_ep_write_header,
+ .set_bar = dw_pcie_ep_set_bar,
+ .clear_bar = dw_pcie_ep_clear_bar,
+ .map_addr = dw_pcie_ep_map_addr,
+ .unmap_addr = dw_pcie_ep_unmap_addr,
+ .set_msi = dw_pcie_ep_set_msi,
+ .get_msi = dw_pcie_ep_get_msi,
+ .raise_irq = dw_pcie_ep_raise_irq,
+ .start = dw_pcie_ep_start,
+ .stop = dw_pcie_ep_stop,
+};
+
+void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
+{
+ struct pci_epc *epc = ep->epc;
+
+ pci_epc_mem_exit(epc);
+}
+
+int dw_pcie_ep_init(struct dw_pcie_ep *ep)
+{
+ int ret;
+ void *addr;
+ enum pci_barno bar;
+ struct pci_epc *epc;
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ struct device *dev = pci->dev;
+ struct device_node *np = dev->of_node;
+
+ ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
+ if (ret < 0) {
+ dev_err(dev, "unable to read *num-ib-windows* property\n");
+ return ret;
+ }
+
+ ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
+ if (ret < 0) {
+ dev_err(dev, "unable to read *num-ob-windows* property\n");
+ return ret;
+ }
+
+ addr = devm_kzalloc(dev, sizeof(phys_addr_t) * ep->num_ob_windows,
+ GFP_KERNEL);
+ if (!addr)
+ return -ENOMEM;
+ ep->outbound_addr = addr;
+
+ for (bar = BAR_0; bar <= BAR_5; bar++)
+ dw_pcie_ep_reset_bar(pci, bar);
+
+ if (ep->ops->ep_init)
+ ep->ops->ep_init(ep);
+
+ epc = devm_pci_epc_create(dev, &epc_ops);
+ if (IS_ERR(epc)) {
+ dev_err(dev, "failed to create epc device\n");
+ return PTR_ERR(epc);
+ }
+
+ ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
+ if (ret < 0)
+ epc->max_functions = 1;
+
+ ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size);
+ if (ret < 0) {
+ dev_err(dev, "Failed to initialize address space\n");
+ return ret;
+ }
+
+ ep->epc = epc;
+ epc_set_drvdata(epc, ep);
+ dw_pcie_setup(pci);
+
+ return 0;
+}
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 686945d..49b28c8 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -173,6 +173,57 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
dev_err(pci->dev, "iATU is not being enabled\n");
}
+int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
+ u64 cpu_addr, enum dw_pcie_as_type as_type)
+{
+ int type;
+ void __iomem *base = pci->dbi_base;
+
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4,
+ PCIE_ATU_REGION_INBOUND | index);
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4,
+ lower_32_bits(cpu_addr));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4,
+ upper_32_bits(cpu_addr));
+
+ switch (as_type) {
+ case DW_PCIE_AS_MEM:
+ type = PCIE_ATU_TYPE_MEM;
+ break;
+ case DW_PCIE_AS_IO:
+ type = PCIE_ATU_TYPE_IO;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type);
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4, PCIE_ATU_ENABLE |
+ PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
+ return 0;
+}
+
+void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
+ enum dw_pcie_region_type type)
+{
+ int region;
+ void __iomem *base = pci->dbi_base;
+
+ switch (type) {
+ case DW_PCIE_REGION_INBOUND:
+ region = PCIE_ATU_REGION_INBOUND;
+ break;
+ case DW_PCIE_REGION_OUTBOUND:
+ region = PCIE_ATU_REGION_OUTBOUND;
+ break;
+ default:
+ return;
+ }
+
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4, region | index);
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4, ~PCIE_ATU_ENABLE);
+}
+
int dw_pcie_wait_for_link(struct dw_pcie *pci)
{
int retries;
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index 0ef6ae7..7476234 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -18,6 +18,9 @@
#include <linux/msi.h>
#include <linux/pci.h>
+#include <linux/pci-epc.h>
+#include <linux/pci-epf.h>
+
/* Parameters for the waiting for link up routine */
#define LINK_WAIT_MAX_RETRIES 10
#define LINK_WAIT_USLEEP_MIN 90000
@@ -89,6 +92,13 @@
#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \
((0x3 << 20) | ((region) << 9))
+#define MSI_MESSAGE_CONTROL 0x52
+#define MSI_CAP_MMC_SHIFT 1
+#define MSI_CAP_MME_SHIFT 4
+#define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT)
+#define MSI_MESSAGE_ADDR_L32 0x54
+#define MSI_MESSAGE_ADDR_U32 0x58
+
/*
* Maximum number of MSI IRQs can be 256 per controller. But keep
* it 32 as of now. Probably we will never need more than 32. If needed,
@@ -99,6 +109,13 @@
struct pcie_port;
struct dw_pcie;
+struct dw_pcie_ep;
+
+enum dw_pcie_region_type {
+ DW_PCIE_REGION_UNKNOWN,
+ DW_PCIE_REGION_INBOUND,
+ DW_PCIE_REGION_OUTBOUND,
+};
struct dw_pcie_host_ops {
int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
@@ -142,6 +159,31 @@ struct pcie_port {
DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
};
+enum dw_pcie_as_type {
+ DW_PCIE_AS_UNKNOWN,
+ DW_PCIE_AS_MEM,
+ DW_PCIE_AS_IO,
+};
+
+struct dw_pcie_ep_ops {
+ void (*ep_init)(struct dw_pcie_ep *ep);
+ int (*raise_irq)(struct dw_pcie_ep *ep, enum pci_epc_irq_type type,
+ u8 interrupt_num);
+};
+
+struct dw_pcie_ep {
+ struct pci_epc *epc;
+ struct dw_pcie_ep_ops *ops;
+ phys_addr_t phys_base;
+ size_t addr_size;
+ u8 bar_to_atu[6];
+ phys_addr_t *outbound_addr;
+ unsigned long ib_window_map;
+ unsigned long ob_window_map;
+ u32 num_ib_windows;
+ u32 num_ob_windows;
+};
+
struct dw_pcie_ops {
u64 (*cpu_addr_fixup)(u64 cpu_addr);
u32 (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
@@ -149,19 +191,26 @@ struct dw_pcie_ops {
void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
int size, u32 val);
int (*link_up)(struct dw_pcie *pcie);
+ int (*start_link)(struct dw_pcie *pcie);
+ void (*stop_link)(struct dw_pcie *pcie);
};
struct dw_pcie {
struct device *dev;
void __iomem *dbi_base;
+ void __iomem *dbi_base2;
u32 num_viewport;
u8 iatu_unroll_enabled;
struct pcie_port pp;
+ struct dw_pcie_ep ep;
const struct dw_pcie_ops *ops;
};
#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
+#define to_dw_pcie_from_ep(endpoint) \
+ container_of((endpoint), struct dw_pcie, ep)
+
int dw_pcie_read(void __iomem *addr, int size, u32 *val);
int dw_pcie_write(void __iomem *addr, int size, u32 val);
@@ -174,6 +223,10 @@ void dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
int type, u64 cpu_addr, u64 pci_addr,
u32 size);
+int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
+ u64 cpu_addr, enum dw_pcie_as_type as_type);
+void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
+ enum dw_pcie_region_type type);
void dw_pcie_setup(struct dw_pcie *pci);
#ifdef CONFIG_PCIE_DW_HOST
@@ -200,4 +253,23 @@ static inline int dw_pcie_host_init(struct pcie_port *pp)
return 0;
}
#endif
+
+#ifdef CONFIG_PCIE_DW_EP
+void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
+int dw_pcie_ep_init(struct dw_pcie_ep *ep);
+void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
+#else
+static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
+{
+}
+
+static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep)
+{
+ return 0;
+}
+
+static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
+{
+}
+#endif
#endif /* _PCIE_DESIGNWARE_H */
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 49+ messages in thread* Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support
2017-02-17 9:50 ` [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support Kishon Vijay Abraham I
@ 2017-02-17 13:15 ` Kishon Vijay Abraham I
2017-02-17 17:20 ` Joao Pinto
1 sibling, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 13:15 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
linux-omap, linux-arm-kernel
Hi,
On Friday 17 February 2017 03:20 PM, Kishon Vijay Abraham I wrote:
> Add endpoint mode support to designware driver. This uses the
> EP Core layer introduced recently to add endpoint mode support.
> *Any* function driver can now use this designware device
> in order to achieve the EP functionality.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/pci/dwc/Kconfig | 5 +
> drivers/pci/dwc/Makefile | 1 +
> drivers/pci/dwc/pcie-designware-ep.c | 342 ++++++++++++++++++++++++++++++++++
> drivers/pci/dwc/pcie-designware.c | 51 +++++
> drivers/pci/dwc/pcie-designware.h | 72 +++++++
> 5 files changed, 471 insertions(+)
> create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
>
> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
> index dfb8a69..00335c7 100644
> --- a/drivers/pci/dwc/Kconfig
> +++ b/drivers/pci/dwc/Kconfig
> @@ -9,6 +9,11 @@ config PCIE_DW_HOST
> depends on PCI_MSI_IRQ_DOMAIN
> select PCIE_DW
>
> +config PCIE_DW_EP
> + bool
> + depends on PCI_ENDPOINT
> + select PCIE_DW
> +
> config PCI_DRA7XX
> bool "TI DRA7xx PCIe controller"
> depends on PCI
> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
> index a2df13c..b38425d 100644
> --- a/drivers/pci/dwc/Makefile
> +++ b/drivers/pci/dwc/Makefile
> @@ -1,5 +1,6 @@
> obj-$(CONFIG_PCIE_DW) += pcie-designware.o
> obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
> +obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
> obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
> obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
> obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
> diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
> new file mode 100644
> index 0000000..e465c5e
> --- /dev/null
> +++ b/drivers/pci/dwc/pcie-designware-ep.c
> @@ -0,0 +1,342 @@
> +/**
> + * Synopsys Designware PCIe Endpoint controller driver
> + *
> + * Copyright (C) 2017 Texas Instruments
> + * Author: Kishon Vijay Abraham I <kishon@ti.com>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 of
> + * the License as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/of.h>
> +
> +#include "pcie-designware.h"
> +#include <linux/pci-epc.h>
> +#include <linux/pci-epf.h>
> +
> +void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
> +{
> + struct pci_epc *epc = ep->epc;
> + struct pci_epf *epf;
> +
> + list_for_each_entry(epf, &epc->pci_epf, list)
> + pci_epf_linkup(epf);
Just notices, the right place to use this list should be pci-epc-core. Will fix
this in the next revision.
Thanks
Kishon
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^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support
2017-02-17 9:50 ` [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support Kishon Vijay Abraham I
2017-02-17 13:15 ` Kishon Vijay Abraham I
@ 2017-02-17 17:20 ` Joao Pinto
2017-03-06 9:55 ` Kishon Vijay Abraham I
2017-03-07 5:18 ` Kishon Vijay Abraham I
1 sibling, 2 replies; 49+ messages in thread
From: Joao Pinto @ 2017-02-17 17:20 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
linux-omap, linux-arm-kernel
=C0s 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
> Add endpoint mode support to designware driver. This uses the
> EP Core layer introduced recently to add endpoint mode support.
> *Any* function driver can now use this designware device
> in order to achieve the EP functionality.
> =
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/pci/dwc/Kconfig | 5 +
> drivers/pci/dwc/Makefile | 1 +
> drivers/pci/dwc/pcie-designware-ep.c | 342 ++++++++++++++++++++++++++++=
++++++
> drivers/pci/dwc/pcie-designware.c | 51 +++++
> drivers/pci/dwc/pcie-designware.h | 72 +++++++
> 5 files changed, 471 insertions(+)
> create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
> =
> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
> index dfb8a69..00335c7 100644
> --- a/drivers/pci/dwc/Kconfig
> +++ b/drivers/pci/dwc/Kconfig
> @@ -9,6 +9,11 @@ config PCIE_DW_HOST
> depends on PCI_MSI_IRQ_DOMAIN
> select PCIE_DW
> =
> +config PCIE_DW_EP
> + bool
> + depends on PCI_ENDPOINT
> + select PCIE_DW
> +
> config PCI_DRA7XX
> bool "TI DRA7xx PCIe controller"
> depends on PCI
> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
> index a2df13c..b38425d 100644
> --- a/drivers/pci/dwc/Makefile
> +++ b/drivers/pci/dwc/Makefile
> @@ -1,5 +1,6 @@
> obj-$(CONFIG_PCIE_DW) +=3D pcie-designware.o
> obj-$(CONFIG_PCIE_DW_HOST) +=3D pcie-designware-host.o
> +obj-$(CONFIG_PCIE_DW_EP) +=3D pcie-designware-ep.o
> obj-$(CONFIG_PCIE_DW_PLAT) +=3D pcie-designware-plat.o
> obj-$(CONFIG_PCI_DRA7XX) +=3D pci-dra7xx.o
> obj-$(CONFIG_PCI_EXYNOS) +=3D pci-exynos.o
> diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-=
designware-ep.c
> new file mode 100644
> index 0000000..e465c5e
> --- /dev/null
> +++ b/drivers/pci/dwc/pcie-designware-ep.c
> @@ -0,0 +1,342 @@
> +/**
> + * Synopsys Designware PCIe Endpoint controller driver
> + *
> + * Copyright (C) 2017 Texas Instruments
> + * Author: Kishon Vijay Abraham I <kishon@ti.com>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 of
> + * the License as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <https://urldefense.proofpoint.=
com/v2/url?u=3Dhttp-3A__www.gnu.org_licenses_&d=3DDwIBAg&c=3DDPL6_X_6JkXFx7=
AXWqB0tg&r=3Ds2fO0hii0OGNOv9qQy_HRXy-xAJUD1NNoEcc3io_kx0&m=3DWif-q5OZ-YZwRC=
xX1bBAl5itP28aoQ8Fv7NmxvWSvyg&s=3DN2kaSPkx7uqpiP9O357WPoXruWEiOzF6AhCVChKmd=
xc&e=3D >.
> + */
> +
> +#include <linux/of.h>
> +
> +#include "pcie-designware.h"
> +#include <linux/pci-epc.h>
> +#include <linux/pci-epf.h>
> +
> +void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
> +{
> + struct pci_epc *epc =3D ep->epc;
> + struct pci_epf *epf;
> +
> + list_for_each_entry(epf, &epc->pci_epf, list)
> + pci_epf_linkup(epf);
> +}
> +
> +static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
> +{
> + u32 reg;
> +
> + reg =3D PCI_BASE_ADDRESS_0 + (4 * bar);
> + dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, 0x0);
> + dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, 0x0);
> +}
> +
> +static int dw_pcie_ep_write_header(struct pci_epc *epc,
> + struct pci_epf_header *hdr)
> +{
> + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc);
> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
> + void __iomem *base =3D pci->dbi_base;
> +
> + dw_pcie_write_dbi(pci, base, PCI_VENDOR_ID, 0x2, hdr->vendorid);
> + dw_pcie_write_dbi(pci, base, PCI_DEVICE_ID, 0x2, hdr->deviceid);
> + dw_pcie_write_dbi(pci, base, PCI_REVISION_ID, 0x1, hdr->revid);
> + dw_pcie_write_dbi(pci, base, PCI_CLASS_PROG, 0x1, hdr->progif_code);
> + dw_pcie_write_dbi(pci, base, PCI_CLASS_DEVICE, 0x2,
> + hdr->subclass_code | hdr->baseclass_code << 8);
> + dw_pcie_write_dbi(pci, base, PCI_CACHE_LINE_SIZE, 0x1,
> + hdr->cache_line_size);
> + dw_pcie_write_dbi(pci, base, PCI_SUBSYSTEM_VENDOR_ID, 0x2,
> + hdr->subsys_vendor_id);
> + dw_pcie_write_dbi(pci, base, PCI_SUBSYSTEM_ID, 0x2, hdr->subsys_id);
> + dw_pcie_write_dbi(pci, base, PCI_INTERRUPT_PIN, 0x1,
> + hdr->interrupt_pin);
> +
> + return 0;
> +}
> +
> +static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno =
bar,
> + dma_addr_t cpu_addr,
> + enum dw_pcie_as_type as_type)
> +{
> + int ret;
> + u32 free_win;
> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
> +
> + free_win =3D find_first_zero_bit(&ep->ib_window_map,
> + sizeof(ep->ib_window_map));
> + if (free_win >=3D ep->num_ib_windows) {
> + dev_err(pci->dev, "no free inbound window\n");
> + return -EINVAL;
> + }
> +
> + ret =3D dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr,
> + as_type);
> + if (ret < 0) {
> + dev_err(pci->dev, "Failed to program IB window\n");
> + return ret;
> + }
> +
> + ep->bar_to_atu[bar] =3D free_win;
> + set_bit(free_win, &ep->ib_window_map);
> +
> + return 0;
> +}
> +
> +static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t ph=
ys_addr,
> + u64 pci_addr, size_t size)
> +{
> + u32 free_win;
> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
> +
> + free_win =3D find_first_zero_bit(&ep->ob_window_map,
> + sizeof(ep->ob_window_map));
> + if (free_win >=3D ep->num_ob_windows) {
> + dev_err(pci->dev, "no free outbound window\n");
> + return -EINVAL;
> + }
> +
> + dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
> + phys_addr, pci_addr, size);
> +
> + set_bit(free_win, &ep->ob_window_map);
> + ep->outbound_addr[free_win] =3D phys_addr;
> +
> + return 0;
> +}
> +
> +static void dw_pcie_ep_clear_bar(struct pci_epc *epc, enum pci_barno bar)
> +{
> + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc);
> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
> + u32 atu_index =3D ep->bar_to_atu[bar];
> +
> + dw_pcie_ep_reset_bar(pci, bar);
> +
> + dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
> + clear_bit(atu_index, &ep->ib_window_map);
> +}
> +
> +static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar,
> + dma_addr_t bar_phys, size_t size, int flags)
> +{
> + int ret;
> + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc);
> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
> + enum dw_pcie_as_type as_type;
> + u32 reg =3D PCI_BASE_ADDRESS_0 + (4 * bar);
> +
> + if (!(flags & PCI_BASE_ADDRESS_SPACE))
> + as_type =3D DW_PCIE_AS_MEM;
> + else
> + as_type =3D DW_PCIE_AS_IO;
> +
> + ret =3D dw_pcie_ep_inbound_atu(ep, bar, bar_phys, as_type);
> + if (ret)
> + return ret;
> +
> + dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, size - 1);
> + dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, flags);
> +
> + return 0;
> +}
> +
> +static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr,
> + u32 *atu_index)
> +{
> + u32 index;
> +
> + for (index =3D 0; index < ep->num_ob_windows; index++) {
> + if (ep->outbound_addr[index] !=3D addr)
> + continue;
> + *atu_index =3D index;
> + return 0;
> + }
> +
> + return -EINVAL;
> +}
> +
> +static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, phys_addr_t addr)
> +{
> + int ret;
> + u32 atu_index;
> + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc);
> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
> +
> + ret =3D dw_pcie_find_index(ep, addr, &atu_index);
> + if (ret < 0)
> + return;
> +
> + dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND);
> + clear_bit(atu_index, &ep->ob_window_map);
> +}
> +
> +static int dw_pcie_ep_map_addr(struct pci_epc *epc, phys_addr_t addr,
> + u64 pci_addr, size_t size)
> +{
> + int ret;
> + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc);
> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
> +
> + ret =3D dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size);
> + if (ret) {
> + dev_err(pci->dev, "failed to enable address\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int dw_pcie_ep_get_msi(struct pci_epc *epc)
> +{
> + int val;
> + u32 lower_addr;
> + u32 upper_addr;
> + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc);
> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
> +
> + val =3D dw_pcie_read_dbi(pci, pci->dbi_base, MSI_MESSAGE_CONTROL, 0x2);
> + val =3D (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
> +
> + lower_addr =3D dw_pcie_read_dbi(pci, pci->dbi_base, MSI_MESSAGE_ADDR_L3=
2,
> + 0x4);
> + upper_addr =3D dw_pcie_read_dbi(pci, pci->dbi_base, MSI_MESSAGE_ADDR_U3=
2,
> + 0x4);
> +
> + if (!(lower_addr || upper_addr))
> + return -EINVAL;
> +
> + return val;
> +}
> +
> +static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int)
> +{
> + int val;
> + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc);
> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
> +
> + val =3D (encode_int << MSI_CAP_MMC_SHIFT);
> + dw_pcie_write_dbi(pci, pci->dbi_base, MSI_MESSAGE_CONTROL, 0x2, val);
> +
> + return 0;
> +}
> +
> +static int dw_pcie_ep_raise_irq(struct pci_epc *epc,
> + enum pci_epc_irq_type type, u8 interrupt_num)
> +{
> + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc);
> +
> + if (!ep->ops->raise_irq)
> + return -EINVAL;
> +
> + return ep->ops->raise_irq(ep, type, interrupt_num);
> +}
> +
> +static void dw_pcie_ep_stop(struct pci_epc *epc)
> +{
> + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc);
> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
> +
> + if (!pci->ops->stop_link)
> + return;
> +
> + pci->ops->stop_link(pci);
> +}
> +
> +static int dw_pcie_ep_start(struct pci_epc *epc)
> +{
> + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc);
> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
> +
> + if (!pci->ops->start_link)
> + return -EINVAL;
> +
> + return pci->ops->start_link(pci);
> +}
> +
> +static const struct pci_epc_ops epc_ops =3D {
> + .write_header =3D dw_pcie_ep_write_header,
> + .set_bar =3D dw_pcie_ep_set_bar,
> + .clear_bar =3D dw_pcie_ep_clear_bar,
> + .map_addr =3D dw_pcie_ep_map_addr,
> + .unmap_addr =3D dw_pcie_ep_unmap_addr,
> + .set_msi =3D dw_pcie_ep_set_msi,
> + .get_msi =3D dw_pcie_ep_get_msi,
> + .raise_irq =3D dw_pcie_ep_raise_irq,
> + .start =3D dw_pcie_ep_start,
> + .stop =3D dw_pcie_ep_stop,
> +};
> +
> +void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
> +{
> + struct pci_epc *epc =3D ep->epc;
> +
> + pci_epc_mem_exit(epc);
> +}
> +
> +int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> +{
> + int ret;
> + void *addr;
> + enum pci_barno bar;
> + struct pci_epc *epc;
> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
> + struct device *dev =3D pci->dev;
> + struct device_node *np =3D dev->of_node;
> +
> + ret =3D of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
> + if (ret < 0) {
> + dev_err(dev, "unable to read *num-ib-windows* property\n");
> + return ret;
> + }
> +
> + ret =3D of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
> + if (ret < 0) {
> + dev_err(dev, "unable to read *num-ob-windows* property\n");
> + return ret;
> + }
> +
> + addr =3D devm_kzalloc(dev, sizeof(phys_addr_t) * ep->num_ob_windows,
> + GFP_KERNEL);
> + if (!addr)
> + return -ENOMEM;
> + ep->outbound_addr =3D addr;
> +
> + for (bar =3D BAR_0; bar <=3D BAR_5; bar++)
> + dw_pcie_ep_reset_bar(pci, bar);
> +
> + if (ep->ops->ep_init)
> + ep->ops->ep_init(ep);
> +
> + epc =3D devm_pci_epc_create(dev, &epc_ops);
> + if (IS_ERR(epc)) {
> + dev_err(dev, "failed to create epc device\n");
> + return PTR_ERR(epc);
> + }
> +
> + ret =3D of_property_read_u8(np, "max-functions", &epc->max_functions);
> + if (ret < 0)
> + epc->max_functions =3D 1;
> +
> + ret =3D pci_epc_mem_init(epc, ep->phys_base, ep->addr_size);
> + if (ret < 0) {
> + dev_err(dev, "Failed to initialize address space\n");
> + return ret;
> + }
> +
> + ep->epc =3D epc;
> + epc_set_drvdata(epc, ep);
> + dw_pcie_setup(pci);
> +
> + return 0;
> +}
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-des=
ignware.c
> index 686945d..49b28c8 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -173,6 +173,57 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, =
int index, int type,
> dev_err(pci->dev, "iATU is not being enabled\n");
> }
> =
> +int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
> + u64 cpu_addr, enum dw_pcie_as_type as_type)
> +{
> + int type;
> + void __iomem *base =3D pci->dbi_base;
> +
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4,
> + PCIE_ATU_REGION_INBOUND | index);
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4,
> + lower_32_bits(cpu_addr));
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4,
> + upper_32_bits(cpu_addr));
> +
> + switch (as_type) {
> + case DW_PCIE_AS_MEM:
> + type =3D PCIE_ATU_TYPE_MEM;
> + break;
> + case DW_PCIE_AS_IO:
> + type =3D PCIE_ATU_TYPE_IO;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type);
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4, PCIE_ATU_ENABLE |
> + PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
> + return 0;
> +}
> +
This Atu programming is for PCI Cores <=3D 4.70. Please follow the same app=
roach as:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/tree/drivers/p=
ci/dwc/pcie-designware.c?h=3Dpci/host-designware#n95
> +void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
> + enum dw_pcie_region_type type)
> +{
> + int region;
> + void __iomem *base =3D pci->dbi_base;
> +
> + switch (type) {
> + case DW_PCIE_REGION_INBOUND:
> + region =3D PCIE_ATU_REGION_INBOUND;
> + break;
> + case DW_PCIE_REGION_OUTBOUND:
> + region =3D PCIE_ATU_REGION_OUTBOUND;
> + break;
> + default:
> + return;
> + }
> +
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4, region | index);
> + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4, ~PCIE_ATU_ENABLE);
> +}
> +
> int dw_pcie_wait_for_link(struct dw_pcie *pci)
> {
> int retries;
> diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-des=
ignware.h
> index 0ef6ae7..7476234 100644
> --- a/drivers/pci/dwc/pcie-designware.h
> +++ b/drivers/pci/dwc/pcie-designware.h
> @@ -18,6 +18,9 @@
> #include <linux/msi.h>
> #include <linux/pci.h>
> =
> +#include <linux/pci-epc.h>
> +#include <linux/pci-epf.h>
> +
> /* Parameters for the waiting for link up routine */
> #define LINK_WAIT_MAX_RETRIES 10
> #define LINK_WAIT_USLEEP_MIN 90000
> @@ -89,6 +92,13 @@
> #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \
> ((0x3 << 20) | ((region) << 9))
> =
> +#define MSI_MESSAGE_CONTROL 0x52
> +#define MSI_CAP_MMC_SHIFT 1
> +#define MSI_CAP_MME_SHIFT 4
> +#define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT)
> +#define MSI_MESSAGE_ADDR_L32 0x54
> +#define MSI_MESSAGE_ADDR_U32 0x58
> +
> /*
> * Maximum number of MSI IRQs can be 256 per controller. But keep
> * it 32 as of now. Probably we will never need more than 32. If needed,
> @@ -99,6 +109,13 @@
> =
> struct pcie_port;
> struct dw_pcie;
> +struct dw_pcie_ep;
> +
> +enum dw_pcie_region_type {
> + DW_PCIE_REGION_UNKNOWN,
> + DW_PCIE_REGION_INBOUND,
> + DW_PCIE_REGION_OUTBOUND,
> +};
> =
> struct dw_pcie_host_ops {
> int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
> @@ -142,6 +159,31 @@ struct pcie_port {
> DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
> };
> =
> +enum dw_pcie_as_type {
> + DW_PCIE_AS_UNKNOWN,
> + DW_PCIE_AS_MEM,
> + DW_PCIE_AS_IO,
> +};
> +
> +struct dw_pcie_ep_ops {
> + void (*ep_init)(struct dw_pcie_ep *ep);
> + int (*raise_irq)(struct dw_pcie_ep *ep, enum pci_epc_irq_type type,
> + u8 interrupt_num);
> +};
> +
> +struct dw_pcie_ep {
> + struct pci_epc *epc;
> + struct dw_pcie_ep_ops *ops;
> + phys_addr_t phys_base;
> + size_t addr_size;
> + u8 bar_to_atu[6];
> + phys_addr_t *outbound_addr;
> + unsigned long ib_window_map;
> + unsigned long ob_window_map;
> + u32 num_ib_windows;
> + u32 num_ob_windows;
> +};
> +
> struct dw_pcie_ops {
> u64 (*cpu_addr_fixup)(u64 cpu_addr);
> u32 (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
> @@ -149,19 +191,26 @@ struct dw_pcie_ops {
> void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
> int size, u32 val);
> int (*link_up)(struct dw_pcie *pcie);
> + int (*start_link)(struct dw_pcie *pcie);
> + void (*stop_link)(struct dw_pcie *pcie);
> };
> =
> struct dw_pcie {
> struct device *dev;
> void __iomem *dbi_base;
> + void __iomem *dbi_base2;
> u32 num_viewport;
> u8 iatu_unroll_enabled;
> struct pcie_port pp;
> + struct dw_pcie_ep ep;
> const struct dw_pcie_ops *ops;
> };
> =
> #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
> =
> +#define to_dw_pcie_from_ep(endpoint) \
> + container_of((endpoint), struct dw_pcie, ep)
> +
> int dw_pcie_read(void __iomem *addr, int size, u32 *val);
> int dw_pcie_write(void __iomem *addr, int size, u32 val);
> =
> @@ -174,6 +223,10 @@ void dw_pcie_write_dbi(struct dw_pcie *pci, void __i=
omem *base, u32 reg,
> void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
> int type, u64 cpu_addr, u64 pci_addr,
> u32 size);
> +int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
> + u64 cpu_addr, enum dw_pcie_as_type as_type);
> +void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
> + enum dw_pcie_region_type type);
> void dw_pcie_setup(struct dw_pcie *pci);
> =
> #ifdef CONFIG_PCIE_DW_HOST
> @@ -200,4 +253,23 @@ static inline int dw_pcie_host_init(struct pcie_port=
*pp)
> return 0;
> }
> #endif
> +
> +#ifdef CONFIG_PCIE_DW_EP
> +void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
> +int dw_pcie_ep_init(struct dw_pcie_ep *ep);
> +void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
> +#else
> +static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
> +{
> +}
> +
> +static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> +{
> + return 0;
> +}
> +
> +static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
> +{
> +}
> +#endif
> #endif /* _PCIE_DESIGNWARE_H */
> =
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^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support
2017-02-17 17:20 ` Joao Pinto
@ 2017-03-06 9:55 ` Kishon Vijay Abraham I
2017-03-07 5:18 ` Kishon Vijay Abraham I
1 sibling, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-03-06 9:55 UTC (permalink / raw)
To: Joao Pinto, Bjorn Helgaas, Jingoo Han
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
linux-omap, linux-arm-kernel
Hi,
On Friday 17 February 2017 10:50 PM, Joao Pinto wrote:
> =C0s 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
>> Add endpoint mode support to designware driver. This uses the
>> EP Core layer introduced recently to add endpoint mode support.
>> *Any* function driver can now use this designware device
>> in order to achieve the EP functionality.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> drivers/pci/dwc/Kconfig | 5 +
>> drivers/pci/dwc/Makefile | 1 +
>> drivers/pci/dwc/pcie-designware-ep.c | 342 +++++++++++++++++++++++++++=
+++++++
>> drivers/pci/dwc/pcie-designware.c | 51 +++++
>> drivers/pci/dwc/pcie-designware.h | 72 +++++++
>> 5 files changed, 471 insertions(+)
>> create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
>>
>> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
>> index dfb8a69..00335c7 100644
>> --- a/drivers/pci/dwc/Kconfig
>> +++ b/drivers/pci/dwc/Kconfig
>> @@ -9,6 +9,11 @@ config PCIE_DW_HOST
>> depends on PCI_MSI_IRQ_DOMAIN
>> select PCIE_DW
>> =
>> +config PCIE_DW_EP
>> + bool
>> + depends on PCI_ENDPOINT
>> + select PCIE_DW
>> +
>> config PCI_DRA7XX
>> bool "TI DRA7xx PCIe controller"
>> depends on PCI
>> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
>> index a2df13c..b38425d 100644
>> --- a/drivers/pci/dwc/Makefile
>> +++ b/drivers/pci/dwc/Makefile
>> @@ -1,5 +1,6 @@
>> obj-$(CONFIG_PCIE_DW) +=3D pcie-designware.o
>> obj-$(CONFIG_PCIE_DW_HOST) +=3D pcie-designware-host.o
>> +obj-$(CONFIG_PCIE_DW_EP) +=3D pcie-designware-ep.o
>> obj-$(CONFIG_PCIE_DW_PLAT) +=3D pcie-designware-plat.o
>> obj-$(CONFIG_PCI_DRA7XX) +=3D pci-dra7xx.o
>> obj-$(CONFIG_PCI_EXYNOS) +=3D pci-exynos.o
>> diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie=
-designware-ep.c
>> new file mode 100644
>> index 0000000..e465c5e
>> --- /dev/null
>> +++ b/drivers/pci/dwc/pcie-designware-ep.c
>> @@ -0,0 +1,342 @@
>> +/**
>> + * Synopsys Designware PCIe Endpoint controller driver
>> + *
>> + * Copyright (C) 2017 Texas Instruments
>> + * Author: Kishon Vijay Abraham I <kishon@ti.com>
>> + *
>> + * This program is free software: you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 of
>> + * the License as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program. If not, see <https://urldefense.proofpoint=
.com/v2/url?u=3Dhttp-3A__www.gnu.org_licenses_&d=3DDwIBAg&c=3DDPL6_X_6JkXFx=
7AXWqB0tg&r=3Ds2fO0hii0OGNOv9qQy_HRXy-xAJUD1NNoEcc3io_kx0&m=3DWif-q5OZ-YZwR=
CxX1bBAl5itP28aoQ8Fv7NmxvWSvyg&s=3DN2kaSPkx7uqpiP9O357WPoXruWEiOzF6AhCVChKm=
dxc&e=3D >.
>> + */
>> +
>> +#include <linux/of.h>
>> +
>> +#include "pcie-designware.h"
>> +#include <linux/pci-epc.h>
>> +#include <linux/pci-epf.h>
>> +
>> +void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
>> +{
>> + struct pci_epc *epc =3D ep->epc;
>> + struct pci_epf *epf;
>> +
>> + list_for_each_entry(epf, &epc->pci_epf, list)
>> + pci_epf_linkup(epf);
>> +}
>> +
>> +static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno ba=
r)
>> +{
>> + u32 reg;
>> +
>> + reg =3D PCI_BASE_ADDRESS_0 + (4 * bar);
>> + dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, 0x0);
>> + dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, 0x0);
>> +}
>> +
>> +static int dw_pcie_ep_write_header(struct pci_epc *epc,
>> + struct pci_epf_header *hdr)
>> +{
>> + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc);
>> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
>> + void __iomem *base =3D pci->dbi_base;
>> +
>> + dw_pcie_write_dbi(pci, base, PCI_VENDOR_ID, 0x2, hdr->vendorid);
>> + dw_pcie_write_dbi(pci, base, PCI_DEVICE_ID, 0x2, hdr->deviceid);
>> + dw_pcie_write_dbi(pci, base, PCI_REVISION_ID, 0x1, hdr->revid);
>> + dw_pcie_write_dbi(pci, base, PCI_CLASS_PROG, 0x1, hdr->progif_code);
>> + dw_pcie_write_dbi(pci, base, PCI_CLASS_DEVICE, 0x2,
>> + hdr->subclass_code | hdr->baseclass_code << 8);
>> + dw_pcie_write_dbi(pci, base, PCI_CACHE_LINE_SIZE, 0x1,
>> + hdr->cache_line_size);
>> + dw_pcie_write_dbi(pci, base, PCI_SUBSYSTEM_VENDOR_ID, 0x2,
>> + hdr->subsys_vendor_id);
>> + dw_pcie_write_dbi(pci, base, PCI_SUBSYSTEM_ID, 0x2, hdr->subsys_id);
>> + dw_pcie_write_dbi(pci, base, PCI_INTERRUPT_PIN, 0x1,
>> + hdr->interrupt_pin);
>> +
>> + return 0;
>> +}
>> +
>> +static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno=
bar,
>> + dma_addr_t cpu_addr,
>> + enum dw_pcie_as_type as_type)
>> +{
>> + int ret;
>> + u32 free_win;
>> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
>> +
>> + free_win =3D find_first_zero_bit(&ep->ib_window_map,
>> + sizeof(ep->ib_window_map));
>> + if (free_win >=3D ep->num_ib_windows) {
>> + dev_err(pci->dev, "no free inbound window\n");
>> + return -EINVAL;
>> + }
>> +
>> + ret =3D dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr,
>> + as_type);
>> + if (ret < 0) {
>> + dev_err(pci->dev, "Failed to program IB window\n");
>> + return ret;
>> + }
>> +
>> + ep->bar_to_atu[bar] =3D free_win;
>> + set_bit(free_win, &ep->ib_window_map);
>> +
>> + return 0;
>> +}
>> +
>> +static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t p=
hys_addr,
>> + u64 pci_addr, size_t size)
>> +{
>> + u32 free_win;
>> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
>> +
>> + free_win =3D find_first_zero_bit(&ep->ob_window_map,
>> + sizeof(ep->ob_window_map));
>> + if (free_win >=3D ep->num_ob_windows) {
>> + dev_err(pci->dev, "no free outbound window\n");
>> + return -EINVAL;
>> + }
>> +
>> + dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
>> + phys_addr, pci_addr, size);
>> +
>> + set_bit(free_win, &ep->ob_window_map);
>> + ep->outbound_addr[free_win] =3D phys_addr;
>> +
>> + return 0;
>> +}
>> +
>> +static void dw_pcie_ep_clear_bar(struct pci_epc *epc, enum pci_barno ba=
r)
>> +{
>> + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc);
>> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
>> + u32 atu_index =3D ep->bar_to_atu[bar];
>> +
>> + dw_pcie_ep_reset_bar(pci, bar);
>> +
>> + dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
>> + clear_bit(atu_index, &ep->ib_window_map);
>> +}
>> +
>> +static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar,
>> + dma_addr_t bar_phys, size_t size, int flags)
>> +{
>> + int ret;
>> + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc);
>> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
>> + enum dw_pcie_as_type as_type;
>> + u32 reg =3D PCI_BASE_ADDRESS_0 + (4 * bar);
>> +
>> + if (!(flags & PCI_BASE_ADDRESS_SPACE))
>> + as_type =3D DW_PCIE_AS_MEM;
>> + else
>> + as_type =3D DW_PCIE_AS_IO;
>> +
>> + ret =3D dw_pcie_ep_inbound_atu(ep, bar, bar_phys, as_type);
>> + if (ret)
>> + return ret;
>> +
>> + dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, size - 1);
>> + dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, flags);
>> +
>> + return 0;
>> +}
>> +
>> +static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr,
>> + u32 *atu_index)
>> +{
>> + u32 index;
>> +
>> + for (index =3D 0; index < ep->num_ob_windows; index++) {
>> + if (ep->outbound_addr[index] !=3D addr)
>> + continue;
>> + *atu_index =3D index;
>> + return 0;
>> + }
>> +
>> + return -EINVAL;
>> +}
>> +
>> +static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, phys_addr_t addr)
>> +{
>> + int ret;
>> + u32 atu_index;
>> + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc);
>> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
>> +
>> + ret =3D dw_pcie_find_index(ep, addr, &atu_index);
>> + if (ret < 0)
>> + return;
>> +
>> + dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND);
>> + clear_bit(atu_index, &ep->ob_window_map);
>> +}
>> +
>> +static int dw_pcie_ep_map_addr(struct pci_epc *epc, phys_addr_t addr,
>> + u64 pci_addr, size_t size)
>> +{
>> + int ret;
>> + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc);
>> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
>> +
>> + ret =3D dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size);
>> + if (ret) {
>> + dev_err(pci->dev, "failed to enable address\n");
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int dw_pcie_ep_get_msi(struct pci_epc *epc)
>> +{
>> + int val;
>> + u32 lower_addr;
>> + u32 upper_addr;
>> + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc);
>> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
>> +
>> + val =3D dw_pcie_read_dbi(pci, pci->dbi_base, MSI_MESSAGE_CONTROL, 0x2);
>> + val =3D (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
>> +
>> + lower_addr =3D dw_pcie_read_dbi(pci, pci->dbi_base, MSI_MESSAGE_ADDR_L=
32,
>> + 0x4);
>> + upper_addr =3D dw_pcie_read_dbi(pci, pci->dbi_base, MSI_MESSAGE_ADDR_U=
32,
>> + 0x4);
>> +
>> + if (!(lower_addr || upper_addr))
>> + return -EINVAL;
>> +
>> + return val;
>> +}
>> +
>> +static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int)
>> +{
>> + int val;
>> + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc);
>> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
>> +
>> + val =3D (encode_int << MSI_CAP_MMC_SHIFT);
>> + dw_pcie_write_dbi(pci, pci->dbi_base, MSI_MESSAGE_CONTROL, 0x2, val);
>> +
>> + return 0;
>> +}
>> +
>> +static int dw_pcie_ep_raise_irq(struct pci_epc *epc,
>> + enum pci_epc_irq_type type, u8 interrupt_num)
>> +{
>> + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc);
>> +
>> + if (!ep->ops->raise_irq)
>> + return -EINVAL;
>> +
>> + return ep->ops->raise_irq(ep, type, interrupt_num);
>> +}
>> +
>> +static void dw_pcie_ep_stop(struct pci_epc *epc)
>> +{
>> + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc);
>> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
>> +
>> + if (!pci->ops->stop_link)
>> + return;
>> +
>> + pci->ops->stop_link(pci);
>> +}
>> +
>> +static int dw_pcie_ep_start(struct pci_epc *epc)
>> +{
>> + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc);
>> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
>> +
>> + if (!pci->ops->start_link)
>> + return -EINVAL;
>> +
>> + return pci->ops->start_link(pci);
>> +}
>> +
>> +static const struct pci_epc_ops epc_ops =3D {
>> + .write_header =3D dw_pcie_ep_write_header,
>> + .set_bar =3D dw_pcie_ep_set_bar,
>> + .clear_bar =3D dw_pcie_ep_clear_bar,
>> + .map_addr =3D dw_pcie_ep_map_addr,
>> + .unmap_addr =3D dw_pcie_ep_unmap_addr,
>> + .set_msi =3D dw_pcie_ep_set_msi,
>> + .get_msi =3D dw_pcie_ep_get_msi,
>> + .raise_irq =3D dw_pcie_ep_raise_irq,
>> + .start =3D dw_pcie_ep_start,
>> + .stop =3D dw_pcie_ep_stop,
>> +};
>> +
>> +void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
>> +{
>> + struct pci_epc *epc =3D ep->epc;
>> +
>> + pci_epc_mem_exit(epc);
>> +}
>> +
>> +int dw_pcie_ep_init(struct dw_pcie_ep *ep)
>> +{
>> + int ret;
>> + void *addr;
>> + enum pci_barno bar;
>> + struct pci_epc *epc;
>> + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
>> + struct device *dev =3D pci->dev;
>> + struct device_node *np =3D dev->of_node;
>> +
>> + ret =3D of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows=
);
>> + if (ret < 0) {
>> + dev_err(dev, "unable to read *num-ib-windows* property\n");
>> + return ret;
>> + }
>> +
>> + ret =3D of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows=
);
>> + if (ret < 0) {
>> + dev_err(dev, "unable to read *num-ob-windows* property\n");
>> + return ret;
>> + }
>> +
>> + addr =3D devm_kzalloc(dev, sizeof(phys_addr_t) * ep->num_ob_windows,
>> + GFP_KERNEL);
>> + if (!addr)
>> + return -ENOMEM;
>> + ep->outbound_addr =3D addr;
>> +
>> + for (bar =3D BAR_0; bar <=3D BAR_5; bar++)
>> + dw_pcie_ep_reset_bar(pci, bar);
>> +
>> + if (ep->ops->ep_init)
>> + ep->ops->ep_init(ep);
>> +
>> + epc =3D devm_pci_epc_create(dev, &epc_ops);
>> + if (IS_ERR(epc)) {
>> + dev_err(dev, "failed to create epc device\n");
>> + return PTR_ERR(epc);
>> + }
>> +
>> + ret =3D of_property_read_u8(np, "max-functions", &epc->max_functions);
>> + if (ret < 0)
>> + epc->max_functions =3D 1;
>> +
>> + ret =3D pci_epc_mem_init(epc, ep->phys_base, ep->addr_size);
>> + if (ret < 0) {
>> + dev_err(dev, "Failed to initialize address space\n");
>> + return ret;
>> + }
>> +
>> + ep->epc =3D epc;
>> + epc_set_drvdata(epc, ep);
>> + dw_pcie_setup(pci);
>> +
>> + return 0;
>> +}
>> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-de=
signware.c
>> index 686945d..49b28c8 100644
>> --- a/drivers/pci/dwc/pcie-designware.c
>> +++ b/drivers/pci/dwc/pcie-designware.c
>> @@ -173,6 +173,57 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci,=
int index, int type,
>> dev_err(pci->dev, "iATU is not being enabled\n");
>> }
>> =
>> +int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
>> + u64 cpu_addr, enum dw_pcie_as_type as_type)
>> +{
>> + int type;
>> + void __iomem *base =3D pci->dbi_base;
>> +
>> + dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4,
>> + PCIE_ATU_REGION_INBOUND | index);
>> + dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4,
>> + lower_32_bits(cpu_addr));
>> + dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4,
>> + upper_32_bits(cpu_addr));
>> +
>> + switch (as_type) {
>> + case DW_PCIE_AS_MEM:
>> + type =3D PCIE_ATU_TYPE_MEM;
>> + break;
>> + case DW_PCIE_AS_IO:
>> + type =3D PCIE_ATU_TYPE_IO;
>> + break;
>> + default:
>> + return -EINVAL;
>> + }
>> +
>> + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type);
>> + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4, PCIE_ATU_ENABLE |
>> + PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
>> + return 0;
>> +}
>> +
> =
> This Atu programming is for PCI Cores <=3D 4.70. Please follow the same a=
pproach as:
> https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/tree/drivers=
/pci/dwc/pcie-designware.c?h=3Dpci/host-designware#n95
Okay. But *iatu_unroll_enabled* is being set in "if (!pp->ops->rd_other_con=
f)".
This ops is specific to RC. I think we should have some other mechanism to
detect if iatu is required or not.
Thanks
Kishon
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^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support
2017-02-17 17:20 ` Joao Pinto
2017-03-06 9:55 ` Kishon Vijay Abraham I
@ 2017-03-07 5:18 ` Kishon Vijay Abraham I
2017-03-07 11:10 ` Joao Pinto
1 sibling, 1 reply; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-03-07 5:18 UTC (permalink / raw)
To: Joao Pinto, Bjorn Helgaas, Jingoo Han
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
linux-omap, linux-arm-kernel
Hi Joao,
On Friday 17 February 2017 10:50 PM, Joao Pinto wrote:
> =C0s 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
>> Add endpoint mode support to designware driver. This uses the
>> EP Core layer introduced recently to add endpoint mode support.
>> *Any* function driver can now use this designware device
>> in order to achieve the EP functionality.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> drivers/pci/dwc/Kconfig | 5 +
>> drivers/pci/dwc/Makefile | 1 +
>> drivers/pci/dwc/pcie-designware-ep.c | 342 +++++++++++++++++++++++++++=
+++++++
>> drivers/pci/dwc/pcie-designware.c | 51 +++++
>> drivers/pci/dwc/pcie-designware.h | 72 +++++++
>> 5 files changed, 471 insertions(+)
>> create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
>>
<snip>
>> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-de=
signware.c
>> index 686945d..49b28c8 100644
>> --- a/drivers/pci/dwc/pcie-designware.c
>> +++ b/drivers/pci/dwc/pcie-designware.c
>> @@ -173,6 +173,57 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci,=
int index, int type,
>> dev_err(pci->dev, "iATU is not being enabled\n");
>> }
>> =
>> +int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
>> + u64 cpu_addr, enum dw_pcie_as_type as_type)
>> +{
>> + int type;
>> + void __iomem *base =3D pci->dbi_base;
>> +
>> + dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4,
>> + PCIE_ATU_REGION_INBOUND | index);
>> + dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4,
>> + lower_32_bits(cpu_addr));
>> + dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4,
>> + upper_32_bits(cpu_addr));
>> +
>> + switch (as_type) {
>> + case DW_PCIE_AS_MEM:
>> + type =3D PCIE_ATU_TYPE_MEM;
>> + break;
>> + case DW_PCIE_AS_IO:
>> + type =3D PCIE_ATU_TYPE_IO;
>> + break;
>> + default:
>> + return -EINVAL;
>> + }
>> +
>> + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type);
>> + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4, PCIE_ATU_ENABLE |
>> + PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
>> + return 0;
>> +}
>> +
> =
> This Atu programming is for PCI Cores <=3D 4.70. Please follow the same a=
pproach as:
> https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/tree/drivers=
/pci/dwc/pcie-designware.c?h=3Dpci/host-designware#n95
Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
Thanks
Kishon
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^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support
2017-03-07 5:18 ` Kishon Vijay Abraham I
@ 2017-03-07 11:10 ` Joao Pinto
2017-03-08 11:32 ` Joao Pinto
0 siblings, 1 reply; 49+ messages in thread
From: Joao Pinto @ 2017-03-07 11:10 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Joao Pinto, Bjorn Helgaas, Jingoo Han
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
linux-omap, linux-arm-kernel
Hi Kishon,
=C0s 5:18 AM de 3/7/2017, Kishon Vijay Abraham I escreveu:
> Hi Joao,
> =
> On Friday 17 February 2017 10:50 PM, Joao Pinto wrote:
>> =C0s 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
>>> Add endpoint mode support to designware driver. This uses the
>>> EP Core layer introduced recently to add endpoint mode support.
>>> *Any* function driver can now use this designware device
>>> in order to achieve the EP functionality.
>>>
>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>>> ---
>>> drivers/pci/dwc/Kconfig | 5 +
>>> drivers/pci/dwc/Makefile | 1 +
>>> drivers/pci/dwc/pcie-designware-ep.c | 342 ++++++++++++++++++++++++++=
++++++++
>>> drivers/pci/dwc/pcie-designware.c | 51 +++++
>>> drivers/pci/dwc/pcie-designware.h | 72 +++++++
>>> 5 files changed, 471 insertions(+)
>>> create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
>>>
> =
> <snip>
> =
>>> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-d=
esignware.c
>>> index 686945d..49b28c8 100644
>>> --- a/drivers/pci/dwc/pcie-designware.c
>>> +++ b/drivers/pci/dwc/pcie-designware.c
>>> @@ -173,6 +173,57 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci=
, int index, int type,
>>> dev_err(pci->dev, "iATU is not being enabled\n");
>>> }
>>> =
>>> +int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
>>> + u64 cpu_addr, enum dw_pcie_as_type as_type)
>>> +{
>>> + int type;
>>> + void __iomem *base =3D pci->dbi_base;
>>> +
>>> + dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4,
>>> + PCIE_ATU_REGION_INBOUND | index);
>>> + dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4,
>>> + lower_32_bits(cpu_addr));
>>> + dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4,
>>> + upper_32_bits(cpu_addr));
>>> +
>>> + switch (as_type) {
>>> + case DW_PCIE_AS_MEM:
>>> + type =3D PCIE_ATU_TYPE_MEM;
>>> + break;
>>> + case DW_PCIE_AS_IO:
>>> + type =3D PCIE_ATU_TYPE_IO;
>>> + break;
>>> + default:
>>> + return -EINVAL;
>>> + }
>>> +
>>> + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type);
>>> + dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4, PCIE_ATU_ENABLE |
>>> + PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
>>> + return 0;
>>> +}
>>> +
>>
>> This Atu programming is for PCI Cores <=3D 4.70. Please follow the same =
approach as:
>> https://urldefense.proofpoint.com/v2/url?u=3Dhttps-3A__git.kernel.org_cg=
it_linux_kernel_git_helgaas_pci.git_tree_drivers_pci_dwc_pcie-2Ddesignware.=
c-3Fh-3Dpci_host-2Ddesignware-23n95&d=3DDwID-g&c=3DDPL6_X_6JkXFx7AXWqB0tg&r=
=3Ds2fO0hii0OGNOv9qQy_HRXy-xAJUD1NNoEcc3io_kx0&m=3DMqqHFJBR0jj9ZQILcUJEd-CQ=
kTihuOSf69e-XxZJvRs&s=3DfY5N7Mt9iszsAI04DPm-cSC6cSE5P2axHUFQ9GOx-2A&e=3D =
> =
> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
Yes of course, I will send you the definition soon.
Thanks,
Joao
> =
> Thanks
> Kishon
> =
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^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support
2017-03-07 11:10 ` Joao Pinto
@ 2017-03-08 11:32 ` Joao Pinto
2017-03-08 11:35 ` Kishon Vijay Abraham I
0 siblings, 1 reply; 49+ messages in thread
From: Joao Pinto @ 2017-03-08 11:32 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Joao Pinto, Bjorn Helgaas, Jingoo Han
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
linux-omap, linux-arm-kernel
Hi Kishon,
>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
>
> Yes of course, I will send you the definition soon.
As promissed here is the definition for Inbound:
+/* register address builder */
+#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register) \
+ ((0x3 << 20) | (region << 9) | \
+ (0x1 << 8) | (register << 2))
Thanks,
Joao
>
> Thanks,
> Joao
>
>>
>> Thanks
>> Kishon
>>
>
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^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support
2017-03-08 11:32 ` Joao Pinto
@ 2017-03-08 11:35 ` Kishon Vijay Abraham I
2017-03-08 11:37 ` Joao Pinto
0 siblings, 1 reply; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-03-08 11:35 UTC (permalink / raw)
To: Joao Pinto, Bjorn Helgaas, Jingoo Han
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
linux-omap, linux-arm-kernel
Hi,
On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote:
>
> Hi Kishon,
>
>>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
>>
>> Yes of course, I will send you the definition soon.
>
> As promissed here is the definition for Inbound:
>
> +/* register address builder */
> +#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register) \
> + ((0x3 << 20) | (region << 9) | \
> + (0x1 << 8) | (register << 2))
Cool, thanks!
-Kishon
>
> Thanks,
> Joao
>
>>
>> Thanks,
>> Joao
>>
>>>
>>> Thanks
>>> Kishon
>>>
>>
>
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support
2017-03-08 11:35 ` Kishon Vijay Abraham I
@ 2017-03-08 11:37 ` Joao Pinto
2017-03-08 13:31 ` Kishon Vijay Abraham I
0 siblings, 1 reply; 49+ messages in thread
From: Joao Pinto @ 2017-03-08 11:37 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Joao Pinto, Bjorn Helgaas, Jingoo Han
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
linux-omap, linux-arm-kernel
=C0s 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu:
> Hi,
> =
> On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote:
>>
>> Hi Kishon,
>>
>>>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>>>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
>>>
>>> Yes of course, I will send you the definition soon.
>>
>> As promissed here is the definition for Inbound:
>>
>> +/* register address builder */
>> +#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register) \
>> + ((0x3 << 20) | (region << 9) | \
>> + (0x1 << 8) | (register << 2))
> =
> Cool, thanks!
No problem! If you have doubts, please let me know.
Thanks,
Joao
> =
> -Kishon
>>
>> Thanks,
>> Joao
>>
>>>
>>> Thanks,
>>> Joao
>>>
>>>>
>>>> Thanks
>>>> Kishon
>>>>
>>>
>>
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^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support
2017-03-08 11:37 ` Joao Pinto
@ 2017-03-08 13:31 ` Kishon Vijay Abraham I
2017-03-08 15:32 ` Joao Pinto
0 siblings, 1 reply; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-03-08 13:31 UTC (permalink / raw)
To: Joao Pinto, Bjorn Helgaas, Jingoo Han
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
linux-omap, linux-arm-kernel
Hi,
On Wednesday 08 March 2017 05:07 PM, Joao Pinto wrote:
> =C0s 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu:
>> Hi,
>>
>> On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote:
>>>
>>> Hi Kishon,
>>>
>>>>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>>>>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
>>>>
>>>> Yes of course, I will send you the definition soon.
>>>
>>> As promissed here is the definition for Inbound:
>>>
>>> +/* register address builder */
>>> +#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register) \
>>> + ((0x3 << 20) | (region << 9) | \
>>> + (0x1 << 8) | (register << 2))
>>
>> Cool, thanks!
> =
> No problem! If you have doubts, please let me know.
Okay, so this looks slightly different than the outbound macro since it tak=
es
the register argument. In the case of outbound PCIE_GET_ATU_OUTB_UNR_REG_OF=
FSET
returns the offset which was used like
dw_pcie_write_dbi(pci, base, offset + reg, 0x4, val);
How should the value from PCIE_GET_ATU_INB_UNR_REG_ADDR be used?
Thanks
Kishon
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support
2017-03-08 13:31 ` Kishon Vijay Abraham I
@ 2017-03-08 15:32 ` Joao Pinto
2017-03-08 15:33 ` Joao Pinto
2017-03-08 19:14 ` Christoph Hellwig
0 siblings, 2 replies; 49+ messages in thread
From: Joao Pinto @ 2017-03-08 15:32 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Joao Pinto, Bjorn Helgaas, Jingoo Han
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
linux-omap, linux-arm-kernel
=C0s 1:31 PM de 3/8/2017, Kishon Vijay Abraham I escreveu:
> Hi,
> =
> On Wednesday 08 March 2017 05:07 PM, Joao Pinto wrote:
>> =C0s 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu:
>>> Hi,
>>>
>>> On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote:
>>>>
>>>> Hi Kishon,
>>>>
>>>>>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>>>>>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
>>>>>
>>>>> Yes of course, I will send you the definition soon.
>>>>
>>>> As promissed here is the definition for Inbound:
>>>>
>>>> +/* register address builder */
>>>> +#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register) \
>>>> + ((0x3 << 20) | (region << 9) | \
>>>> + (0x1 << 8) | (register << 2))
>>>
>>> Cool, thanks!
>>
>> No problem! If you have doubts, please let me know.
> =
> Okay, so this looks slightly different than the outbound macro since it t=
akes
> the register argument. In the case of outbound PCIE_GET_ATU_OUTB_UNR_REG_=
OFFSET
> returns the offset which was used like
> dw_pcie_write_dbi(pci, base, offset + reg, 0x4, val);
> =
> How should the value from PCIE_GET_ATU_INB_UNR_REG_ADDR be used?
My original way was this one:
+/* Register address builder */
+#define PCIE_GET_ATU_OUTB_UNR_REG_ADDR(region, register) \
+ ((0x3 << 20) | (region << 9) | \
+ (register << 2))
Bjorn then converted to offset:
#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((0x3 << 20) | (region <<=
9))
and applied the <<2 shift to the ATU registers.
So you can use:
#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register) \
((0x3 << 20) | (region << 9) | \
(0x1 << 8)
Thanks.
> =
> Thanks
> Kishon
> =
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^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support
2017-03-08 15:32 ` Joao Pinto
@ 2017-03-08 15:33 ` Joao Pinto
2017-03-08 19:14 ` Christoph Hellwig
1 sibling, 0 replies; 49+ messages in thread
From: Joao Pinto @ 2017-03-08 15:33 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Joao Pinto, Bjorn Helgaas, Jingoo Han
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
linux-omap, linux-arm-kernel
=C0s 3:32 PM de 3/8/2017, Joao Pinto escreveu:
> =C0s 1:31 PM de 3/8/2017, Kishon Vijay Abraham I escreveu:
>> Hi,
>>
>> On Wednesday 08 March 2017 05:07 PM, Joao Pinto wrote:
>>> =C0s 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu:
>>>> Hi,
>>>>
>>>> On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote:
>>>>>
>>>>> Hi Kishon,
>>>>>
>>>>>>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>>>>>>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
>>>>>>
>>>>>> Yes of course, I will send you the definition soon.
>>>>>
>>>>> As promissed here is the definition for Inbound:
>>>>>
>>>>> +/* register address builder */
>>>>> +#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register) \
>>>>> + ((0x3 << 20) | (region << 9) | \
>>>>> + (0x1 << 8) | (register << 2))
>>>>
>>>> Cool, thanks!
>>>
>>> No problem! If you have doubts, please let me know.
>>
>> Okay, so this looks slightly different than the outbound macro since it =
takes
>> the register argument. In the case of outbound PCIE_GET_ATU_OUTB_UNR_REG=
_OFFSET
>> returns the offset which was used like
>> dw_pcie_write_dbi(pci, base, offset + reg, 0x4, val);
>>
>> How should the value from PCIE_GET_ATU_INB_UNR_REG_ADDR be used?
> =
> My original way was this one:
> =
> +/* Register address builder */
> +#define PCIE_GET_ATU_OUTB_UNR_REG_ADDR(region, register) \
> + ((0x3 << 20) | (region << 9) | \
> + (register << 2))
> =
> Bjorn then converted to offset:
> =
> #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((0x3 << 20) | (region =
<< 9))
> =
> and applied the <<2 shift to the ATU registers.
> =
> So you can use:
> =
> #define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register) \
> ((0x3 << 20) | (region << 9) | \
> (0x1 << 8)
> =
This one has the right name :)
#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region, register) \
((0x3 << 20) | (region << 9) | \
(0x1 << 8)
> Thanks.
> =
>>
>> Thanks
>> Kishon
>>
> =
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support
2017-03-08 15:32 ` Joao Pinto
2017-03-08 15:33 ` Joao Pinto
@ 2017-03-08 19:14 ` Christoph Hellwig
2017-03-09 11:55 ` Joao Pinto
1 sibling, 1 reply; 49+ messages in thread
From: Christoph Hellwig @ 2017-03-08 19:14 UTC (permalink / raw)
To: Joao Pinto
Cc: devicetree, linux-doc, Jingoo Han, nsekhar, linux-kernel,
Kishon Vijay Abraham I, linux-pci, Bjorn Helgaas, linux-omap,
linux-arm-kernel
On Wed, Mar 08, 2017 at 03:32:03PM +0000, Joao Pinto wrote:
> #define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register) \
> ((0x3 << 20) | (region << 9) | \
> (0x1 << 8)
Can you turn this and any similar macro into inline functions?
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^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support
2017-03-08 19:14 ` Christoph Hellwig
@ 2017-03-09 11:55 ` Joao Pinto
0 siblings, 0 replies; 49+ messages in thread
From: Joao Pinto @ 2017-03-09 11:55 UTC (permalink / raw)
To: Christoph Hellwig, Joao Pinto, Kishon Vijay Abraham I
Cc: devicetree, linux-doc, Jingoo Han, nsekhar, linux-kernel,
linux-pci, Bjorn Helgaas, linux-omap, linux-arm-kernel
Hi Christoph,
=C0s 7:14 PM de 3/8/2017, Christoph Hellwig escreveu:
> On Wed, Mar 08, 2017 at 03:32:03PM +0000, Joao Pinto wrote:
>> #define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register) \
>> ((0x3 << 20) | (region << 9) | \
>> (0x1 << 8)
> =
> Can you turn this and any similar macro into inline functions?
> =
Use an inline functions instead of macro is fine by me. In the initial patc=
h I
implemented as a macro since it only does simple bit shifts and nothing els=
e and
seemed simpler as a macro.
Thanks,
Joao
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^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 09/22] dt-bindings: PCI: Add dt bindings for pci designware EP mode
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
` (7 preceding siblings ...)
2017-02-17 9:50 ` [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-17 9:50 ` [PATCH v2 10/22] PCI: dwc: dra7xx: Facilitate wrapper and msi interrupts to be enabled independently Kishon Vijay Abraham I
` (12 subsequent siblings)
21 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
Kishon Vijay Abraham I, linux-omap, linux-arm-kernel
Add device tree binding documentation for pci designware EP mode.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
.../devicetree/bindings/pci/designware-pcie.txt | 26 ++++++++++++++------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 1392c70..b2480dd 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -6,30 +6,40 @@ Required properties:
- reg-names: Must be "config" for the PCIe configuration space.
(The old way of getting the configuration address space from "ranges"
is deprecated and should be avoided.)
+- num-lanes: number of lanes to use
+RC mode:
- #address-cells: set to <3>
- #size-cells: set to <2>
- device_type: set to "pci"
- ranges: ranges for the PCI memory and I/O regions
- #interrupt-cells: set to <1>
-- interrupt-map-mask and interrupt-map: standard PCI properties
- to define the mapping of the PCIe interface to interrupt
+- interrupt-map-mask and interrupt-map: standard PCI
+ properties to define the mapping of the PCIe interface to interrupt
numbers.
-- num-lanes: number of lanes to use
+EP mode:
+- num-ib-windows: number of inbound address translation
+ windows
+- num-ob-windows: number of outbound address translation
+ windows
Optional properties:
-- num-viewport: number of view ports configured in hardware. If a platform
- does not specify it, the driver assumes 2.
- num-lanes: number of lanes to use (this property should be specified unless
the link is brought already up in BIOS)
- reset-gpio: gpio pin number of power good signal
-- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
- specify this property, to keep backwards compatibility a range of 0x00-0xff
- is assumed if not present)
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- "pcie"
- "pcie_bus"
+RC mode:
+- num-viewport: number of view ports configured in
+ hardware. If a platform does not specify it, the driver assumes 2.
+- bus-range: PCI bus numbers covered (it is recommended
+ for new devicetrees to specify this property, to keep backwards
+ compatibility a range of 0x00-0xff is assumed if not present)
+EP mode:
+- max-functions: maximum number of functions that can be
+ configured
Example configuration:
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 10/22] PCI: dwc: dra7xx: Facilitate wrapper and msi interrupts to be enabled independently
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
` (8 preceding siblings ...)
2017-02-17 9:50 ` [PATCH v2 09/22] dt-bindings: PCI: Add dt bindings for pci designware EP mode Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-17 9:50 ` [PATCH v2 11/22] PCI: dwc: dra7xx: Add EP mode support Kishon Vijay Abraham I
` (11 subsequent siblings)
21 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: linux-pci, linux-doc, linux-kernel, devicetree, linux-omap,
linux-arm-kernel, nsekhar, Kishon Vijay Abraham I
No functional change. Split dra7xx_pcie_enable_interrupts into
dra7xx_pcie_enable_wrapper_interrupts and dra7xx_pcie_enable_msi_interrupts
so that wrapper interrupts and msi interrupts can be enabled independently.
This is in preparation for adding EP mode support to dra7xx driver since
EP mode doesn't have to enable msi_interrupts.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/dwc/pci-dra7xx.c | 24 ++++++++++++++++++------
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index c6fef0a..8d2d02f 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -140,18 +140,30 @@ static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
return dw_pcie_wait_for_link(pci);
}
-static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
+static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)
{
- dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
- ~INTERRUPTS);
- dra7xx_pcie_writel(dra7xx,
- PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, INTERRUPTS);
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
~LEG_EP_INTERRUPTS & ~MSI);
- dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
+
+ dra7xx_pcie_writel(dra7xx,
+ PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
MSI | LEG_EP_INTERRUPTS);
}
+static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx)
+{
+ dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
+ ~INTERRUPTS);
+ dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN,
+ INTERRUPTS);
+}
+
+static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
+{
+ dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
+ dra7xx_pcie_enable_msi_interrupts(dra7xx);
+}
+
static void dra7xx_pcie_host_init(struct pcie_port *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 11/22] PCI: dwc: dra7xx: Add EP mode support
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
` (9 preceding siblings ...)
2017-02-17 9:50 ` [PATCH v2 10/22] PCI: dwc: dra7xx: Facilitate wrapper and msi interrupts to be enabled independently Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-17 9:50 ` [PATCH v2 12/22] dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode Kishon Vijay Abraham I
` (10 subsequent siblings)
21 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
Kishon Vijay Abraham I, linux-omap, linux-arm-kernel
The PCIe controller integrated in dra7xx SoCs is capable of operating
in endpoint mode. Add endpoint mode support to dra7xx driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/dwc/Kconfig | 31 +++++-
drivers/pci/dwc/Makefile | 4 +-
drivers/pci/dwc/pci-dra7xx.c | 197 ++++++++++++++++++++++++++++++++++---
drivers/pci/dwc/pcie-designware.h | 7 ++
4 files changed, 221 insertions(+), 18 deletions(-)
diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
index 00335c7..96e6d17 100644
--- a/drivers/pci/dwc/Kconfig
+++ b/drivers/pci/dwc/Kconfig
@@ -16,14 +16,37 @@ config PCIE_DW_EP
config PCI_DRA7XX
bool "TI DRA7xx PCIe controller"
- depends on PCI
+ depends on (PCI && PCI_MSI_IRQ_DOMAIN) || PCI_ENDPOINT
depends on OF && HAS_IOMEM && TI_PIPE3
+ help
+ Enables support for the PCIe controller in the DRA7xx SoC. There
+ are two instances of PCIe controller in DRA7xx. This controller can
+ work either as EP or RC. In order to enable host specific features
+ PCI_DRA7XX_HOST must be selected and in order to enable device
+ specific features PCI_DRA7XX_EP must be selected. This uses
+ the Designware core.
+
+if PCI_DRA7XX
+
+config PCI_DRA7XX_HOST
+ bool "PCI DRA7xx Host Mode"
+ depends on PCI
depends on PCI_MSI_IRQ_DOMAIN
select PCIE_DW_HOST
+ default y
help
- Enables support for the PCIe controller in the DRA7xx SoC. There
- are two instances of PCIe controller in DRA7xx. This controller can
- act both as EP and RC. This reuses the Designware core.
+ Enables support for the PCIe controller in the DRA7xx SoC to work in
+ host mode.
+
+config PCI_DRA7XX_EP
+ bool "PCI DRA7xx Endpoint Mode"
+ depends on PCI_ENDPOINT
+ select PCIE_DW_EP
+ help
+ Enables support for the PCIe controller in the DRA7xx SoC to work in
+ endpoint mode.
+
+endif
config PCIE_DW_PLAT
bool "Platform bus based DesignWare PCIe Controller"
diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
index b38425d..f31a859 100644
--- a/drivers/pci/dwc/Makefile
+++ b/drivers/pci/dwc/Makefile
@@ -2,7 +2,9 @@ obj-$(CONFIG_PCIE_DW) += pcie-designware.o
obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
-obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
+ifneq ($(filter y,$(CONFIG_PCI_DRA7XX_HOST) $(CONFIG_PCI_DRA7XX_EP)),)
+ obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
+endif
obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 8d2d02f..47bb563 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -10,12 +10,14 @@
* published by the Free Software Foundation.
*/
+#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/init.h>
+#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/of_pci.h>
#include <linux/pci.h>
@@ -57,6 +59,11 @@
#define MSI BIT(4)
#define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
+#define PCIECTRL_TI_CONF_DEVICE_TYPE 0x0100
+#define DEVICE_TYPE_EP 0x0
+#define DEVICE_TYPE_LEG_EP 0x1
+#define DEVICE_TYPE_RC 0x4
+
#define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
#define LTSSM_EN 0x1
@@ -66,6 +73,13 @@
#define EXP_CAP_ID_OFFSET 0x70
+#define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124
+#define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128
+
+#define PCIECTRL_TI_CONF_MSI_XMT 0x012c
+#define MSI_REQ_GRANT BIT(0)
+#define MSI_VECTOR_SHIFT 7
+
struct dra7xx_pcie {
struct dw_pcie *pci;
void __iomem *base; /* DT ti_conf */
@@ -73,6 +87,11 @@ struct dra7xx_pcie {
struct phy **phy;
int link_gen;
struct irq_domain *irq_domain;
+ enum dw_pcie_device_mode mode;
+};
+
+struct dra7xx_pcie_of_data {
+ enum dw_pcie_device_mode mode;
};
#define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
@@ -101,9 +120,19 @@ static int dra7xx_pcie_link_up(struct dw_pcie *pci)
return !!(reg & LINK_UP);
}
-static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
+static void dra7xx_pcie_stop_link(struct dw_pcie *pci)
{
- struct dw_pcie *pci = dra7xx->pci;
+ struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
+ u32 reg;
+
+ reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
+ reg &= ~LTSSM_EN;
+ dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
+}
+
+static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
+{
+ struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
struct device *dev = pci->dev;
u32 reg;
u32 exp_cap_off = EXP_CAP_ID_OFFSET;
@@ -137,7 +166,7 @@ static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
reg |= LTSSM_EN;
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
- return dw_pcie_wait_for_link(pci);
+ return 0;
}
static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)
@@ -171,7 +200,8 @@ static void dra7xx_pcie_host_init(struct pcie_port *pp)
dw_pcie_setup_rc(pp);
- dra7xx_pcie_establish_link(dra7xx);
+ dra7xx_pcie_establish_link(pci);
+ dw_pcie_wait_for_link(pci);
dw_pcie_msi_init(pp);
dra7xx_pcie_enable_interrupts(dra7xx);
}
@@ -249,6 +279,7 @@ static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
struct dra7xx_pcie *dra7xx = arg;
struct dw_pcie *pci = dra7xx->pci;
struct device *dev = pci->dev;
+ struct dw_pcie_ep *ep = &pci->ep;
u32 reg;
reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
@@ -285,8 +316,11 @@ static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
if (reg & LINK_REQ_RST)
dev_dbg(dev, "Link Request Reset\n");
- if (reg & LINK_UP_EVT)
+ if (reg & LINK_UP_EVT) {
+ if (dra7xx->mode == DW_PCIE_EP_TYPE)
+ dw_pcie_ep_linkup(ep);
dev_dbg(dev, "Link-up state change\n");
+ }
if (reg & CFG_BME_EVT)
dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
@@ -299,6 +333,94 @@ static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
return IRQ_HANDLED;
}
+static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
+
+ dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
+}
+
+static void dra7xx_pcie_raise_legacy_irq(struct dra7xx_pcie *dra7xx)
+{
+ dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1);
+ mdelay(1);
+ dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_DEASSERT, 0x1);
+}
+
+static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
+ u8 interrupt_num)
+{
+ u32 reg;
+
+ reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT;
+ reg |= MSI_REQ_GRANT;
+ dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg);
+}
+
+static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep,
+ enum pci_epc_irq_type type, u8 interrupt_num)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
+
+ switch (type) {
+ case PCI_EPC_IRQ_LEGACY:
+ dra7xx_pcie_raise_legacy_irq(dra7xx);
+ break;
+ case PCI_EPC_IRQ_MSI:
+ dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num);
+ break;
+ default:
+ dev_err(pci->dev, "UNKNOWN IRQ type\n");
+ }
+
+ return 0;
+}
+
+static struct dw_pcie_ep_ops pcie_ep_ops = {
+ .ep_init = dra7xx_pcie_ep_init,
+ .raise_irq = dra7xx_pcie_raise_irq,
+};
+
+static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
+ struct platform_device *pdev)
+{
+ int ret;
+ struct dw_pcie_ep *ep;
+ struct resource *res;
+ struct device *dev = &pdev->dev;
+ struct dw_pcie *pci = dra7xx->pci;
+
+ ep = &pci->ep;
+ ep->ops = &pcie_ep_ops;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics");
+ pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
+ if (!pci->dbi_base)
+ return -ENOMEM;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics2");
+ pci->dbi_base2 = devm_ioremap(dev, res->start, resource_size(res));
+ if (!pci->dbi_base2)
+ return -ENOMEM;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
+ if (!res)
+ return -EINVAL;
+
+ ep->phys_base = res->start;
+ ep->addr_size = resource_size(res);
+
+ ret = dw_pcie_ep_init(ep);
+ if (ret) {
+ dev_err(dev, "failed to initialize endpoint\n");
+ return ret;
+ }
+
+ return 0;
+}
+
static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
struct platform_device *pdev)
{
@@ -342,6 +464,8 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
static const struct dw_pcie_ops dw_pcie_ops = {
.cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup,
+ .start_link = dra7xx_pcie_establish_link,
+ .stop_link = dra7xx_pcie_stop_link,
.link_up = dra7xx_pcie_link_up,
};
@@ -384,6 +508,26 @@ static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx)
return ret;
}
+static const struct dra7xx_pcie_of_data dra7xx_pcie_rc_of_data = {
+ .mode = DW_PCIE_RC_TYPE,
+};
+
+static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = {
+ .mode = DW_PCIE_EP_TYPE,
+};
+
+static const struct of_device_id of_dra7xx_pcie_match[] = {
+ {
+ .compatible = "ti,dra7-pcie",
+ .data = &dra7xx_pcie_rc_of_data,
+ },
+ {
+ .compatible = "ti,dra7-pcie-ep",
+ .data = &dra7xx_pcie_ep_of_data,
+ },
+ {},
+};
+
static int __init dra7xx_pcie_probe(struct platform_device *pdev)
{
u32 reg;
@@ -401,6 +545,16 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
struct device_node *np = dev->of_node;
char name[10];
struct gpio_desc *reset;
+ const struct of_device_id *match;
+ const struct dra7xx_pcie_of_data *data;
+ enum dw_pcie_device_mode mode;
+
+ match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev);
+ if (!match)
+ return -EINVAL;
+
+ data = (struct dra7xx_pcie_of_data *)match->data;
+ mode = (enum dw_pcie_device_mode)data->mode;
dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
if (!dra7xx)
@@ -486,9 +640,25 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
dra7xx->link_gen = 2;
- ret = dra7xx_add_pcie_port(dra7xx, pdev);
- if (ret < 0)
- goto err_gpio;
+ switch (mode) {
+ case DW_PCIE_RC_TYPE:
+ dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
+ DEVICE_TYPE_RC);
+ ret = dra7xx_add_pcie_port(dra7xx, pdev);
+ if (ret < 0)
+ goto err_gpio;
+ break;
+ case DW_PCIE_EP_TYPE:
+ dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
+ DEVICE_TYPE_EP);
+ ret = dra7xx_add_pcie_ep(dra7xx, pdev);
+ if (ret < 0)
+ goto err_gpio;
+ break;
+ default:
+ dev_err(dev, "INVALID device type %d\n", mode);
+ }
+ dra7xx->mode = mode;
return 0;
@@ -510,6 +680,9 @@ static int dra7xx_pcie_suspend(struct device *dev)
void __iomem *base = pci->dbi_base;
u32 val;
+ if (dra7xx->mode != DW_PCIE_RC_TYPE)
+ return 0;
+
/* clear MSE */
val = dw_pcie_read_dbi(pci, base, PCI_COMMAND, 0x4);
val &= ~PCI_COMMAND_MEMORY;
@@ -525,6 +698,9 @@ static int dra7xx_pcie_resume(struct device *dev)
void __iomem *base = pci->dbi_base;
u32 val;
+ if (dra7xx->mode != DW_PCIE_RC_TYPE)
+ return 0;
+
/* set MSE */
val = dw_pcie_read_dbi(pci, base, PCI_COMMAND, 0x4);
val |= PCI_COMMAND_MEMORY;
@@ -563,11 +739,6 @@ static int dra7xx_pcie_resume_noirq(struct device *dev)
dra7xx_pcie_resume_noirq)
};
-static const struct of_device_id of_dra7xx_pcie_match[] = {
- { .compatible = "ti,dra7-pcie", },
- {},
-};
-
static struct platform_driver dra7xx_pcie_driver = {
.driver = {
.name = "dra7-pcie",
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index 7476234..5679aa3 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -117,6 +117,13 @@ enum dw_pcie_region_type {
DW_PCIE_REGION_OUTBOUND,
};
+enum dw_pcie_device_mode {
+ DW_PCIE_UNKNOWN_TYPE,
+ DW_PCIE_EP_TYPE,
+ DW_PCIE_LEG_EP_TYPE,
+ DW_PCIE_RC_TYPE,
+};
+
struct dw_pcie_host_ops {
int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 12/22] dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
` (10 preceding siblings ...)
2017-02-17 9:50 ` [PATCH v2 11/22] PCI: dwc: dra7xx: Add EP mode support Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-17 9:50 ` [PATCH v2 13/22] PCI: dwc: dra7xx: Workaround for errata id i870 Kishon Vijay Abraham I
` (9 subsequent siblings)
21 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
Kishon Vijay Abraham I, linux-omap, linux-arm-kernel
Add device tree binding documentation for pci dra7xx EP mode.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Documentation/devicetree/bindings/pci/ti-pci.txt | 37 ++++++++++++++++++----
1 file changed, 30 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
index 60e2516..190828a 100644
--- a/Documentation/devicetree/bindings/pci/ti-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -1,17 +1,22 @@
TI PCI Controllers
PCIe Designware Controller
- - compatible: Should be "ti,dra7-pcie""
- - reg : Two register ranges as listed in the reg-names property
- - reg-names : The first entry must be "ti-conf" for the TI specific registers
- The second entry must be "rc-dbics" for the designware pcie
- registers
- The third entry must be "config" for the PCIe configuration space
+ - compatible: Should be "ti,dra7-pcie" for RC
+ Should be "ti,dra7-pcie-ep" for EP
- phys : list of PHY specifiers (used by generic PHY framework)
- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
number of PHYs as specified in *phys* property.
- ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
where <X> is the instance number of the pcie from the HW spec.
+ - num-lanes as specified in ../designware-pcie.txt
+
+HOST MODE
+=========
+ - reg : Two register ranges as listed in the reg-names property
+ - reg-names : The first entry must be "ti-conf" for the TI specific registers
+ The second entry must be "rc-dbics" for the designware pcie
+ registers
+ The third entry must be "config" for the PCIe configuration space
- interrupts : Two interrupt entries must be specified. The first one is for
main interrupt line and the second for MSI interrupt line.
- #address-cells,
@@ -19,13 +24,31 @@ PCIe Designware Controller
#interrupt-cells,
device_type,
ranges,
- num-lanes,
interrupt-map-mask,
interrupt-map : as specified in ../designware-pcie.txt
+DEVICE MODE
+===========
+ - reg : Four register ranges as listed in the reg-names property
+ - reg-names : "ti-conf" for the TI specific registers
+ "ep_dbics" for the standard configuration registers as
+ they are locally accessed within the DIF CS space
+ "ep_dbics2" for the standard configuration registers as
+ they are locally accessed within the DIF CS2 space
+ "addr_space" used to map remote RC address space
+ - interrupts : one interrupt entries must be specified for main interrupt.
+ - num-ib-windows : number of inbound address translation windows
+ - num-ob-windows : number of outbound address translation windows
+
Optional Property:
- gpios : Should be added if a gpio line is required to drive PERST# line
+NOTE: Two dt nodes may be added for each PCI controller; one for host
+mode and another for device mode. So in order for PCI to
+work in host mode, EP mode dt node should be disabled and in order to PCI to
+work in EP mode, host mode dt node should be disabled. And host mode and EP
+mode are mutually exclusive.
+
Example:
axi {
compatible = "simple-bus";
--
1.7.9.5
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 13/22] PCI: dwc: dra7xx: Workaround for errata id i870
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
` (11 preceding siblings ...)
2017-02-17 9:50 ` [PATCH v2 12/22] dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-17 9:50 ` [PATCH v2 14/22] dt-bindings: PCI: dra7xx: Add dt bindings to enable legacy mode Kishon Vijay Abraham I
` (8 subsequent siblings)
21 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
Kishon Vijay Abraham I, linux-omap, linux-arm-kernel
According to errata i870, access to the PCIe slave port
that are not 32-bit aligned will result in incorrect mapping
to TLP Address and Byte enable fields.
Accessing non 32-bit aligned data causes incorrect data in the target
buffer if memcpy is used. Implement the workaround for this
errata here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/dwc/pci-dra7xx.c | 50 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 47bb563..df11a49 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -26,6 +26,8 @@
#include <linux/pm_runtime.h>
#include <linux/resource.h>
#include <linux/types.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
#include "pcie-designware.h"
@@ -528,6 +530,48 @@ static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx)
{},
};
+/*
+ * dra7xx_pcie_ep_legacy_mode: workaround for AM572x/AM571x Errata i870
+ * @dra7xx: the dra7xx device where the workaround should be applied
+ *
+ * Access to the PCIe slave port that are not 32-bit aligned will result
+ * in incorrect mapping to TLP Address and Byte enable fields. Therefore,
+ * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or
+ * 0x3.
+ *
+ * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
+ */
+static int dra7xx_pcie_ep_legacy_mode(struct device *dev)
+{
+ int ret;
+ struct device_node *np = dev->of_node;
+ struct regmap *regmap;
+ unsigned int reg;
+ unsigned int field;
+
+ regmap = syscon_regmap_lookup_by_phandle(np, "syscon-legacy-mode");
+ if (IS_ERR(regmap)) {
+ dev_dbg(dev, "can't get syscon-legacy-mode\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32_index(np, "syscon-legacy-mode", 1, ®)) {
+ dev_err(dev, "couldn't get legacy mode register offset\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32_index(np, "syscon-legacy-mode", 2, &field)) {
+ dev_err(dev, "can't get bit field for setting legacy mode\n");
+ return -EINVAL;
+ }
+
+ ret = regmap_update_bits(regmap, reg, field, field);
+ if (ret)
+ dev_err(dev, "failed to set legacy mode\n");
+
+ return ret;
+}
+
static int __init dra7xx_pcie_probe(struct platform_device *pdev)
{
u32 reg;
@@ -644,6 +688,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
case DW_PCIE_RC_TYPE:
dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
DEVICE_TYPE_RC);
+
ret = dra7xx_add_pcie_port(dra7xx, pdev);
if (ret < 0)
goto err_gpio;
@@ -651,6 +696,11 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
case DW_PCIE_EP_TYPE:
dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
DEVICE_TYPE_EP);
+
+ ret = dra7xx_pcie_ep_legacy_mode(dev);
+ if (ret)
+ goto err_gpio;
+
ret = dra7xx_add_pcie_ep(dra7xx, pdev);
if (ret < 0)
goto err_gpio;
--
1.7.9.5
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 14/22] dt-bindings: PCI: dra7xx: Add dt bindings to enable legacy mode
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
` (12 preceding siblings ...)
2017-02-17 9:50 ` [PATCH v2 13/22] PCI: dwc: dra7xx: Workaround for errata id i870 Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-27 16:40 ` Rob Herring
2017-02-17 9:50 ` [PATCH v2 15/22] PCI: Add device IDs for DRA74x and DRA72x Kishon Vijay Abraham I
` (7 subsequent siblings)
21 siblings, 1 reply; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: linux-pci, linux-doc, linux-kernel, devicetree, linux-omap,
linux-arm-kernel, nsekhar, Kishon Vijay Abraham I
Update device tree binding documentation of TI's dra7xx PCI
controller to include property for enabling legacy mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Documentation/devicetree/bindings/pci/ti-pci.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
index 190828a..72ebe2b 100644
--- a/Documentation/devicetree/bindings/pci/ti-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -39,6 +39,10 @@ DEVICE MODE
- interrupts : one interrupt entries must be specified for main interrupt.
- num-ib-windows : number of inbound address translation windows
- num-ob-windows : number of outbound address translation windows
+ - syscon-legacy-mode: phandle to the syscon dt node. The 1st argument should
+ contain the register offset within syscon and the 2nd
+ argument should contain the bit field for setting the
+ legacy mode
Optional Property:
- gpios : Should be added if a gpio line is required to drive PERST# line
--
1.7.9.5
^ permalink raw reply related [flat|nested] 49+ messages in thread* Re: [PATCH v2 14/22] dt-bindings: PCI: dra7xx: Add dt bindings to enable legacy mode
2017-02-17 9:50 ` [PATCH v2 14/22] dt-bindings: PCI: dra7xx: Add dt bindings to enable legacy mode Kishon Vijay Abraham I
@ 2017-02-27 16:40 ` Rob Herring
2017-02-28 3:28 ` Kishon Vijay Abraham I
2017-03-06 9:56 ` Kishon Vijay Abraham I
0 siblings, 2 replies; 49+ messages in thread
From: Rob Herring @ 2017-02-27 16:40 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: devicetree, Joao Pinto, linux-doc, Jingoo Han, nsekhar,
linux-kernel, linux-pci, Bjorn Helgaas, linux-omap,
linux-arm-kernel
On Fri, Feb 17, 2017 at 03:20:34PM +0530, Kishon Vijay Abraham I wrote:
> Update device tree binding documentation of TI's dra7xx PCI
> controller to include property for enabling legacy mode.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> Documentation/devicetree/bindings/pci/ti-pci.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
> index 190828a..72ebe2b 100644
> --- a/Documentation/devicetree/bindings/pci/ti-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
> @@ -39,6 +39,10 @@ DEVICE MODE
> - interrupts : one interrupt entries must be specified for main interrupt.
> - num-ib-windows : number of inbound address translation windows
> - num-ob-windows : number of outbound address translation windows
> + - syscon-legacy-mode: phandle to the syscon dt node. The 1st argument should
> + contain the register offset within syscon and the 2nd
> + argument should contain the bit field for setting the
> + legacy mode
Vendor prefix needed and what does "legacy mode" mean? Perhaps name this
around what the mode is/does, not that it is legacy.
Rob
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 14/22] dt-bindings: PCI: dra7xx: Add dt bindings to enable legacy mode
2017-02-27 16:40 ` Rob Herring
@ 2017-02-28 3:28 ` Kishon Vijay Abraham I
2017-03-06 9:56 ` Kishon Vijay Abraham I
1 sibling, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-28 3:28 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, Joao Pinto, linux-doc, Jingoo Han, nsekhar,
linux-kernel, linux-pci, Bjorn Helgaas, linux-omap,
linux-arm-kernel
On Monday 27 February 2017 10:10 PM, Rob Herring wrote:
> On Fri, Feb 17, 2017 at 03:20:34PM +0530, Kishon Vijay Abraham I wrote:
>> Update device tree binding documentation of TI's dra7xx PCI
>> controller to include property for enabling legacy mode.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> Documentation/devicetree/bindings/pci/ti-pci.txt | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
>> index 190828a..72ebe2b 100644
>> --- a/Documentation/devicetree/bindings/pci/ti-pci.txt
>> +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
>> @@ -39,6 +39,10 @@ DEVICE MODE
>> - interrupts : one interrupt entries must be specified for main interrupt.
>> - num-ib-windows : number of inbound address translation windows
>> - num-ob-windows : number of outbound address translation windows
>> + - syscon-legacy-mode: phandle to the syscon dt node. The 1st argument should
>> + contain the register offset within syscon and the 2nd
>> + argument should contain the bit field for setting the
>> + legacy mode
>
> Vendor prefix needed and what does "legacy mode" mean? Perhaps name this
> around what the mode is/does, not that it is legacy.
All right, thanks!
-Kishon
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 14/22] dt-bindings: PCI: dra7xx: Add dt bindings to enable legacy mode
2017-02-27 16:40 ` Rob Herring
2017-02-28 3:28 ` Kishon Vijay Abraham I
@ 2017-03-06 9:56 ` Kishon Vijay Abraham I
1 sibling, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-03-06 9:56 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, Joao Pinto, linux-doc, Jingoo Han, nsekhar,
linux-kernel, linux-pci, Bjorn Helgaas, linux-omap,
linux-arm-kernel
Hi,
On Monday 27 February 2017 10:10 PM, Rob Herring wrote:
> On Fri, Feb 17, 2017 at 03:20:34PM +0530, Kishon Vijay Abraham I wrote:
>> Update device tree binding documentation of TI's dra7xx PCI
>> controller to include property for enabling legacy mode.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> Documentation/devicetree/bindings/pci/ti-pci.txt | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
>> index 190828a..72ebe2b 100644
>> --- a/Documentation/devicetree/bindings/pci/ti-pci.txt
>> +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
>> @@ -39,6 +39,10 @@ DEVICE MODE
>> - interrupts : one interrupt entries must be specified for main interrupt.
>> - num-ib-windows : number of inbound address translation windows
>> - num-ob-windows : number of outbound address translation windows
>> + - syscon-legacy-mode: phandle to the syscon dt node. The 1st argument should
>> + contain the register offset within syscon and the 2nd
>> + argument should contain the bit field for setting the
>> + legacy mode
>
> Vendor prefix needed and what does "legacy mode" mean? Perhaps name this
> around what the mode is/does, not that it is legacy.
sure, will fix that.
Thanks
Kishon
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 15/22] PCI: Add device IDs for DRA74x and DRA72x
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
` (13 preceding siblings ...)
2017-02-17 9:50 ` [PATCH v2 14/22] dt-bindings: PCI: dra7xx: Add dt bindings to enable legacy mode Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-17 9:50 ` [PATCH v2 16/22] misc: Add host side pci driver for pci test function device Kishon Vijay Abraham I
` (6 subsequent siblings)
21 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: linux-pci, linux-doc, linux-kernel, devicetree, linux-omap,
linux-arm-kernel, nsekhar, Kishon Vijay Abraham I
Add device IDs for DRA74x and DRA72x devices. These devices have
configurable PCI endpoint.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
include/linux/pci_ids.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 73dda0e..e8bbc4b 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -862,6 +862,8 @@
#define PCI_DEVICE_ID_TI_X620 0xac8d
#define PCI_DEVICE_ID_TI_X420 0xac8e
#define PCI_DEVICE_ID_TI_XX20_FM 0xac8f
+#define PCI_DEVICE_ID_TI_DRA74x 0xb500
+#define PCI_DEVICE_ID_TI_DRA72x 0xb501
#define PCI_VENDOR_ID_SONY 0x104d
--
1.7.9.5
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 16/22] misc: Add host side pci driver for pci test function device
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
` (14 preceding siblings ...)
2017-02-17 9:50 ` [PATCH v2 15/22] PCI: Add device IDs for DRA74x and DRA72x Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-17 9:50 ` [PATCH v2 17/22] Documentation: misc-devices: Add Documentation for pci-endpoint-test driver Kishon Vijay Abraham I
` (5 subsequent siblings)
21 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
Kishon Vijay Abraham I, linux-omap, linux-arm-kernel
Add PCI endpoint test driver that can verify base address
register, legacy interrupt/MSI interrupt and read/write/copy
buffers between host and device. The corresponding pci-epf-test
function driver should be used on the EP side.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/misc/Kconfig | 7 +
drivers/misc/Makefile | 1 +
drivers/misc/pci_endpoint_test.c | 534 ++++++++++++++++++++++++++++++++++++++
include/uapi/linux/Kbuild | 1 +
include/uapi/linux/pcitest.h | 19 ++
5 files changed, 562 insertions(+)
create mode 100644 drivers/misc/pci_endpoint_test.c
create mode 100644 include/uapi/linux/pcitest.h
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 64971ba..14a95a6 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -766,6 +766,13 @@ config PANEL_BOOT_MESSAGE
An empty message will only clear the display at driver init time. Any other
printf()-formatted message is valid with newline and escape codes.
+config PCI_ENDPOINT_TEST
+ depends on PCI || COMPILE_TEST
+ tristate "PCI Endpoint Test driver"
+ ---help---
+ Enable this configuration option to enable the host side test driver
+ for PCI Endpoint.
+
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 3198336..64a532ac2 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_ECHO) += echo/
obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o
obj-$(CONFIG_CXL_BASE) += cxl/
obj-$(CONFIG_PANEL) += panel.o
+obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o
lkdtm-$(CONFIG_LKDTM) += lkdtm_core.o
lkdtm-$(CONFIG_LKDTM) += lkdtm_bugs.o
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
new file mode 100644
index 0000000..8239ace
--- /dev/null
+++ b/drivers/misc/pci_endpoint_test.c
@@ -0,0 +1,534 @@
+/**
+ * Host side test driver to test endpoint functionality
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/crc32.h>
+#include <linux/delay.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/random.h>
+#include <linux/slab.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+
+#include <linux/pci_regs.h>
+
+#include <uapi/linux/pcitest.h>
+
+#define DRV_MODULE_NAME "pci-endpoint-test"
+
+#define PCI_ENDPOINT_TEST_MAGIC 0x0
+
+#define PCI_ENDPOINT_TEST_COMMAND 0x4
+#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
+#define COMMAND_RAISE_MSI_IRQ BIT(1)
+#define MSI_NUMBER_SHIFT 2
+/* 6 bits for MSI number */
+#define COMMAND_READ BIT(8)
+#define COMMAND_WRITE BIT(9)
+#define COMMAND_COPY BIT(10)
+
+#define PCI_ENDPOINT_TEST_STATUS 0x8
+#define STATUS_READ_SUCCESS BIT(0)
+#define STATUS_READ_FAIL BIT(1)
+#define STATUS_WRITE_SUCCESS BIT(2)
+#define STATUS_WRITE_FAIL BIT(3)
+#define STATUS_COPY_SUCCESS BIT(4)
+#define STATUS_COPY_FAIL BIT(5)
+#define STATUS_IRQ_RAISED BIT(6)
+#define STATUS_SRC_ADDR_INVALID BIT(7)
+#define STATUS_DST_ADDR_INVALID BIT(8)
+
+#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0xc
+#define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
+
+#define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
+#define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
+
+#define PCI_ENDPOINT_TEST_SIZE 0x1c
+#define PCI_ENDPOINT_TEST_CHECKSUM 0x20
+
+static DEFINE_IDA(pci_endpoint_test_ida);
+
+#define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
+ miscdev)
+enum pci_barno {
+ BAR_0,
+ BAR_1,
+ BAR_2,
+ BAR_3,
+ BAR_4,
+ BAR_5,
+};
+
+struct pci_endpoint_test {
+ struct pci_dev *pdev;
+ void __iomem *base;
+ void __iomem *bar[6];
+ struct completion irq_raised;
+ int last_irq;
+ /* mutex to protect the ioctls */
+ struct mutex mutex;
+ struct miscdevice miscdev;
+};
+
+static int bar_size[] = { 4, 512, 1024, 16384, 131072, 1048576 };
+
+static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
+ u32 offset)
+{
+ return readl(test->base + offset);
+}
+
+static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test,
+ u32 offset, u32 value)
+{
+ writel(value, test->base + offset);
+}
+
+static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test,
+ int bar, int offset)
+{
+ return readl(test->bar[bar] + offset);
+}
+
+static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test,
+ int bar, u32 offset, u32 value)
+{
+ writel(value, test->bar[bar] + offset);
+}
+
+static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
+{
+ struct pci_endpoint_test *test = dev_id;
+ u32 reg;
+
+ reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
+ if (reg & STATUS_IRQ_RAISED) {
+ test->last_irq = irq;
+ complete(&test->irq_raised);
+ reg &= ~STATUS_IRQ_RAISED;
+ }
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS,
+ reg);
+
+ return IRQ_HANDLED;
+}
+
+static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
+ enum pci_barno barno)
+{
+ int j;
+ u32 val;
+ int size;
+
+ if (!test->bar[barno])
+ return false;
+
+ size = bar_size[barno];
+
+ for (j = 0; j < size; j += 4)
+ pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);
+
+ for (j = 0; j < size; j += 4) {
+ val = pci_endpoint_test_bar_readl(test, barno, j);
+ if (val != 0xA0A0A0A0)
+ return false;
+ }
+
+ return true;
+}
+
+static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
+{
+ u32 val;
+
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
+ COMMAND_RAISE_LEGACY_IRQ);
+ val = wait_for_completion_timeout(&test->irq_raised,
+ msecs_to_jiffies(1000));
+ if (!val)
+ return false;
+
+ return true;
+}
+
+static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
+ u8 msi_num)
+{
+ u32 val;
+ struct pci_dev *pdev = test->pdev;
+
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
+ msi_num << MSI_NUMBER_SHIFT |
+ COMMAND_RAISE_MSI_IRQ);
+ val = wait_for_completion_timeout(&test->irq_raised,
+ msecs_to_jiffies(1000));
+ if (!val)
+ return false;
+
+ if (test->last_irq - pdev->irq == msi_num - 1)
+ return true;
+
+ return false;
+}
+
+static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size)
+{
+ bool ret = false;
+ void *src_addr;
+ void *dst_addr;
+ dma_addr_t src_phys_addr;
+ dma_addr_t dst_phys_addr;
+ struct pci_dev *pdev = test->pdev;
+ struct device *dev = &pdev->dev;
+ u32 src_crc32;
+ u32 dst_crc32;
+
+ src_addr = dma_alloc_coherent(dev, size, &src_phys_addr, GFP_KERNEL);
+ if (!src_addr) {
+ dev_err(dev, "failed to allocate source buffer\n");
+ ret = false;
+ goto err;
+ }
+
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
+ lower_32_bits(src_phys_addr));
+
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
+ upper_32_bits(src_phys_addr));
+
+ get_random_bytes(src_addr, size);
+ src_crc32 = crc32_le(~0, src_addr, size);
+
+ dst_addr = dma_alloc_coherent(dev, size, &dst_phys_addr, GFP_KERNEL);
+ if (!dst_addr) {
+ dev_err(dev, "failed to allocate destination address\n");
+ ret = false;
+ goto err_src_addr;
+ }
+
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
+ lower_32_bits(dst_phys_addr));
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
+ upper_32_bits(dst_phys_addr));
+
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
+ size);
+
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
+ 1 << MSI_NUMBER_SHIFT | COMMAND_COPY);
+
+ wait_for_completion(&test->irq_raised);
+
+ dst_crc32 = crc32_le(~0, dst_addr, size);
+ if (dst_crc32 == src_crc32)
+ ret = true;
+
+ dma_free_coherent(dev, size, dst_addr, dst_phys_addr);
+
+err_src_addr:
+ dma_free_coherent(dev, size, src_addr, src_phys_addr);
+
+err:
+ return ret;
+}
+
+static bool pci_endpoint_test_write(struct pci_endpoint_test *test, size_t size)
+{
+ bool ret = false;
+ u32 reg;
+ void *addr;
+ dma_addr_t phys_addr;
+ struct pci_dev *pdev = test->pdev;
+ struct device *dev = &pdev->dev;
+ u32 crc32;
+
+ addr = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL);
+ if (!addr) {
+ dev_err(dev, "failed to allocate address\n");
+ ret = false;
+ goto err;
+ }
+
+ get_random_bytes(addr, size);
+
+ crc32 = crc32_le(~0, addr, size);
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM,
+ crc32);
+
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
+ lower_32_bits(phys_addr));
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
+ upper_32_bits(phys_addr));
+
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
+
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
+ 1 << MSI_NUMBER_SHIFT | COMMAND_READ);
+
+ wait_for_completion(&test->irq_raised);
+
+ reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
+ if (reg & STATUS_READ_SUCCESS)
+ ret = true;
+
+ dma_free_coherent(dev, size, addr, phys_addr);
+
+err:
+ return ret;
+}
+
+static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size)
+{
+ bool ret = false;
+ void *addr;
+ dma_addr_t phys_addr;
+ struct pci_dev *pdev = test->pdev;
+ struct device *dev = &pdev->dev;
+ u32 crc32;
+
+ addr = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL);
+ if (!addr) {
+ dev_err(dev, "failed to allocate destination address\n");
+ ret = false;
+ goto err;
+ }
+
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
+ lower_32_bits(phys_addr));
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
+ upper_32_bits(phys_addr));
+
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
+
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
+ 1 << MSI_NUMBER_SHIFT | COMMAND_WRITE);
+
+ wait_for_completion(&test->irq_raised);
+
+ crc32 = crc32_le(~0, addr, size);
+ if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
+ ret = true;
+
+ dma_free_coherent(dev, size, addr, phys_addr);
+err:
+ return ret;
+}
+
+static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
+ unsigned long arg)
+{
+ int ret = -EINVAL;
+ enum pci_barno bar;
+ struct pci_endpoint_test *test = to_endpoint_test(file->private_data);
+
+ mutex_lock(&test->mutex);
+ switch (cmd) {
+ case PCITEST_BAR:
+ bar = arg;
+ if (bar < 0 || bar > 5)
+ goto ret;
+ ret = pci_endpoint_test_bar(test, bar);
+ break;
+ case PCITEST_LEGACY_IRQ:
+ ret = pci_endpoint_test_legacy_irq(test);
+ break;
+ case PCITEST_MSI:
+ ret = pci_endpoint_test_msi_irq(test, arg);
+ break;
+ case PCITEST_WRITE:
+ ret = pci_endpoint_test_write(test, arg);
+ break;
+ case PCITEST_READ:
+ ret = pci_endpoint_test_read(test, arg);
+ break;
+ case PCITEST_COPY:
+ ret = pci_endpoint_test_copy(test, arg);
+ break;
+ }
+
+ret:
+ mutex_unlock(&test->mutex);
+ return ret;
+}
+
+static const struct file_operations pci_endpoint_test_fops = {
+ .owner = THIS_MODULE,
+ .unlocked_ioctl = pci_endpoint_test_ioctl,
+};
+
+static int pci_endpoint_test_probe(struct pci_dev *pdev,
+ const struct pci_device_id *ent)
+{
+ int i;
+ int err;
+ int irq;
+ int id;
+ char name[20];
+ enum pci_barno bar;
+ void __iomem *base;
+ struct device *dev = &pdev->dev;
+ struct pci_endpoint_test *test;
+ struct miscdevice *misc_device;
+
+ if (pci_is_bridge(pdev))
+ return -ENODEV;
+
+ test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
+ if (!test)
+ return -ENOMEM;
+
+ test->pdev = pdev;
+ init_completion(&test->irq_raised);
+ mutex_init(&test->mutex);
+
+ err = pci_enable_device(pdev);
+ if (err) {
+ dev_err(dev, "Cannot enable PCI device\n");
+ return err;
+ }
+
+ err = pci_request_regions(pdev, DRV_MODULE_NAME);
+ if (err) {
+ dev_err(dev, "Cannot obtain PCI resources\n");
+ goto err_disable_pdev;
+ }
+
+ pci_set_master(pdev);
+
+ irq = pci_enable_msi_range(pdev, 1, 32);
+ if (irq < 0)
+ dev_err(dev, "failed to get MSI interrupts\n");
+
+ err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler,
+ IRQF_SHARED, DRV_MODULE_NAME, test);
+ if (err) {
+ dev_err(dev, "failed to request irq\n");
+ goto err_disable_msi;
+ }
+
+ for (i = 1; i < irq; i++) {
+ err = devm_request_irq(dev, pdev->irq + i,
+ pci_endpoint_test_irqhandler,
+ IRQF_SHARED, DRV_MODULE_NAME, test);
+ if (err)
+ dev_err(dev, "failed to request irq for MSI %d\n",
+ i + 1);
+ }
+
+ for (bar = BAR_0; bar <= BAR_5; bar++) {
+ base = pci_ioremap_bar(pdev, bar);
+ if (!base) {
+ dev_err(dev, "failed to read BAR%d\n", bar);
+ WARN_ON(bar == BAR_0);
+ }
+ test->bar[bar] = base;
+ }
+
+ test->base = test->bar[0];
+ if (!test->base) {
+ dev_err(dev, "Cannot perform PCI test without BAR0\n");
+ goto err_iounmap;
+ }
+
+ pci_set_drvdata(pdev, test);
+
+ id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
+ if (id < 0) {
+ dev_err(dev, "unable to get id\n");
+ goto err_iounmap;
+ }
+
+ snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
+ misc_device = &test->miscdev;
+ misc_device->minor = MISC_DYNAMIC_MINOR;
+ misc_device->name = name;
+ misc_device->fops = &pci_endpoint_test_fops,
+
+ err = misc_register(misc_device);
+ if (err) {
+ dev_err(dev, "failed to register device\n");
+ goto err_ida_remove;
+ }
+
+ return 0;
+
+err_ida_remove:
+ ida_simple_remove(&pci_endpoint_test_ida, id);
+
+err_iounmap:
+ for (bar = BAR_0; bar <= BAR_5; bar++) {
+ if (test->bar[bar])
+ pci_iounmap(pdev, test->bar[bar]);
+ }
+
+err_disable_msi:
+ pci_disable_msi(pdev);
+ pci_release_regions(pdev);
+
+err_disable_pdev:
+ pci_disable_device(pdev);
+
+ return err;
+}
+
+static void pci_endpoint_test_remove(struct pci_dev *pdev)
+{
+ int id;
+ enum pci_barno bar;
+ struct pci_endpoint_test *test = pci_get_drvdata(pdev);
+ struct miscdevice *misc_device = &test->miscdev;
+
+ if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1)
+ return;
+
+ misc_deregister(&test->miscdev);
+ ida_simple_remove(&pci_endpoint_test_ida, id);
+ for (bar = BAR_0; bar <= BAR_5; bar++) {
+ if (test->bar[bar])
+ pci_iounmap(pdev, test->bar[bar]);
+ }
+ pci_disable_msi(pdev);
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+}
+
+static const struct pci_device_id pci_endpoint_test_tbl[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
+ { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
+ { }
+};
+MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
+
+static struct pci_driver pci_endpoint_test_driver = {
+ .name = DRV_MODULE_NAME,
+ .id_table = pci_endpoint_test_tbl,
+ .probe = pci_endpoint_test_probe,
+ .remove = pci_endpoint_test_remove,
+};
+module_pci_driver(pci_endpoint_test_driver);
+
+MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
+MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/include/uapi/linux/Kbuild b/include/uapi/linux/Kbuild
index a8b93e6..f3c2769 100644
--- a/include/uapi/linux/Kbuild
+++ b/include/uapi/linux/Kbuild
@@ -329,6 +329,7 @@ header-y += parport.h
header-y += patchkey.h
header-y += pci.h
header-y += pci_regs.h
+header-y += pcitest.h
header-y += perf_event.h
header-y += personality.h
header-y += pfkeyv2.h
diff --git a/include/uapi/linux/pcitest.h b/include/uapi/linux/pcitest.h
new file mode 100644
index 0000000..a6aa10c
--- /dev/null
+++ b/include/uapi/linux/pcitest.h
@@ -0,0 +1,19 @@
+/**
+ * pcitest.h - PCI test uapi defines
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ */
+
+#ifndef __UAPI_LINUX_PCITEST_H
+#define __UAPI_LINUX_PCITEST_H
+
+#define PCITEST_BAR _IO('P', 0x1)
+#define PCITEST_LEGACY_IRQ _IO('P', 0x2)
+#define PCITEST_MSI _IOW('P', 0x3, int)
+#define PCITEST_WRITE _IOW('P', 0x4, unsigned long)
+#define PCITEST_READ _IOW('P', 0x5, unsigned long)
+#define PCITEST_COPY _IOW('P', 0x6, unsigned long)
+
+#endif /* __UAPI_LINUX_PCITEST_H */
--
1.7.9.5
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 17/22] Documentation: misc-devices: Add Documentation for pci-endpoint-test driver
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
` (15 preceding siblings ...)
2017-02-17 9:50 ` [PATCH v2 16/22] misc: Add host side pci driver for pci test function device Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-17 9:50 ` [PATCH v2 18/22] tools: PCI: Add a userspace tool to test PCI endpoint Kishon Vijay Abraham I
` (4 subsequent siblings)
21 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
Kishon Vijay Abraham I, linux-omap, linux-arm-kernel
Add Documentation for pci-endpoint-test driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Documentation/misc-devices/pci-endpoint-test.txt | 35 ++++++++++++++++++++++
1 file changed, 35 insertions(+)
create mode 100644 Documentation/misc-devices/pci-endpoint-test.txt
diff --git a/Documentation/misc-devices/pci-endpoint-test.txt b/Documentation/misc-devices/pci-endpoint-test.txt
new file mode 100644
index 0000000..4385718
--- /dev/null
+++ b/Documentation/misc-devices/pci-endpoint-test.txt
@@ -0,0 +1,35 @@
+Driver for PCI Endpoint Test Function
+
+This driver should be used as a host side driver if the root complex is
+connected to a configurable pci endpoint running *pci_epf_test* function
+driver configured according to [1].
+
+The "pci_endpoint_test" driver can be used to perform the following tests.
+
+The PCI driver for the test device performs the following tests
+ *) verifying addresses programmed in BAR
+ *) raise legacy IRQ
+ *) raise MSI IRQ
+ *) read data
+ *) write data
+ *) copy data
+
+This misc driver creates /dev/pci-endpoint-test.<num> for every
+*pci_epf_test* function connected to the root complex and "ioctls"
+should be used to perform the above tests.
+
+ioctl
+-----
+ PCITEST_BAR: Tests the BAR. The number of the BAR that has to be tested
+ should be passed as argument.
+ PCITEST_LEGACY_IRQ: Tests legacy IRQ
+ PCITEST_MSI: Tests message signalled interrupts. The MSI number that has
+ to be tested should be passed as argument.
+ PCITEST_WRITE: Perform write tests. The size of the buffer should be passed
+ as argument.
+ PCITEST_READ: Perform read tests. The size of the buffer should be passed
+ as argument.
+ PCITEST_COPY: Perform read tests. The size of the buffer should be passed
+ as argument.
+
+[1] -> Documentation/PCI/endpoint/function/binding/pci-test.txt
--
1.7.9.5
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 18/22] tools: PCI: Add a userspace tool to test PCI endpoint
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
` (16 preceding siblings ...)
2017-02-17 9:50 ` [PATCH v2 17/22] Documentation: misc-devices: Add Documentation for pci-endpoint-test driver Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-17 9:50 ` [PATCH v2 19/22] tools: PCI: Add sample test script to invoke pcitest Kishon Vijay Abraham I
` (3 subsequent siblings)
21 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: linux-pci, linux-doc, linux-kernel, devicetree, linux-omap,
linux-arm-kernel, nsekhar, Kishon Vijay Abraham I
Add a userspace tool to invoke the ioctls exposed by the
PCI endpoint test driver to perform various PCI tests.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
tools/pci/pcitest.c | 186 +++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 186 insertions(+)
create mode 100644 tools/pci/pcitest.c
diff --git a/tools/pci/pcitest.c b/tools/pci/pcitest.c
new file mode 100644
index 0000000..39b5b0b
--- /dev/null
+++ b/tools/pci/pcitest.c
@@ -0,0 +1,186 @@
+/**
+ * Userspace PCI Endpoint Test Module
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <errno.h>
+#include <fcntl.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/ioctl.h>
+#include <time.h>
+#include <unistd.h>
+
+#include <linux/pcitest.h>
+
+#define BILLION 1E9
+
+static char *result[] = { "NOT OKAY", "OKAY" };
+
+struct pci_test {
+ char *device;
+ char barnum;
+ bool legacyirq;
+ unsigned int msinum;
+ bool read;
+ bool write;
+ bool copy;
+ unsigned long size;
+};
+
+static int run_test(struct pci_test *test)
+{
+ long ret;
+ int fd;
+ struct timespec start, end;
+ double time;
+
+ fd = open(test->device, O_RDWR);
+ if (fd < 0) {
+ perror("can't open PCI Endpoint Test device");
+ return fd;
+ }
+
+ if (test->barnum >= 0 && test->barnum <= 5) {
+ ret = ioctl(fd, PCITEST_BAR, test->barnum);
+ fprintf(stdout, "BAR%d:\t\t", test->barnum);
+ if (ret < 0)
+ fprintf(stdout, "TEST FAILED\n");
+ else
+ fprintf(stdout, "%s\n", result[ret]);
+ }
+
+ if (test->legacyirq) {
+ ret = ioctl(fd, PCITEST_LEGACY_IRQ, 0);
+ fprintf(stdout, "LEGACY IRQ:\t");
+ if (ret < 0)
+ fprintf(stdout, "TEST FAILED\n");
+ else
+ fprintf(stdout, "%s\n", result[ret]);
+ }
+
+ if (test->msinum > 0 && test->msinum <= 32) {
+ ret = ioctl(fd, PCITEST_MSI, test->msinum);
+ fprintf(stdout, "MSI%d:\t\t", test->msinum);
+ if (ret < 0)
+ fprintf(stdout, "TEST FAILED\n");
+ else
+ fprintf(stdout, "%s\n", result[ret]);
+ }
+
+ if (test->write) {
+ ret = ioctl(fd, PCITEST_WRITE, test->size);
+ fprintf(stdout, "WRITE (%7ld bytes):\t\t", test->size);
+ if (ret < 0)
+ fprintf(stdout, "TEST FAILED\n");
+ else
+ fprintf(stdout, "%s\n", result[ret]);
+ }
+
+ if (test->read) {
+ ret = ioctl(fd, PCITEST_READ, test->size);
+ fprintf(stdout, "READ (%7ld bytes):\t\t", test->size);
+ if (ret < 0)
+ fprintf(stdout, "TEST FAILED\n");
+ else
+ fprintf(stdout, "%s\n", result[ret]);
+ }
+
+ if (test->copy) {
+ ret = ioctl(fd, PCITEST_COPY, test->size);
+ fprintf(stdout, "COPY (%7ld bytes):\t\t", test->size);
+ if (ret < 0)
+ fprintf(stdout, "TEST FAILED\n");
+ else
+ fprintf(stdout, "%s\n", result[ret]);
+ }
+
+ fflush(stdout);
+}
+
+int main(int argc, char **argv)
+{
+ int c;
+ struct pci_test *test;
+
+ test = calloc(1, sizeof(*test));
+ if (!test) {
+ perror("Fail to allocate memory for pci_test\n");
+ return -ENOMEM;
+ }
+
+ /* since '0' is a valid BAR number, initialize it to -1 */
+ test->barnum = -1;
+
+ /* set default size as 100KB */
+ test->size = 0x19000;
+
+ /* set default endpoint device */
+ test->device = "/dev/pci-endpoint-test.0";
+
+ while ((c = getopt(argc, argv, "D:b:m:lrwcs:")) != EOF)
+ switch (c) {
+ case 'D':
+ test->device = optarg;
+ continue;
+ case 'b':
+ test->barnum = atoi(optarg);
+ if (test->barnum < 0 || test->barnum > 5)
+ goto usage;
+ continue;
+ case 'l':
+ test->legacyirq = true;
+ continue;
+ case 'm':
+ test->msinum = atoi(optarg);
+ if (test->msinum < 1 || test->msinum > 32)
+ goto usage;
+ continue;
+ case 'r':
+ test->read = true;
+ continue;
+ case 'w':
+ test->write = true;
+ continue;
+ case 'c':
+ test->copy = true;
+ continue;
+ case 's':
+ test->size = strtoul(optarg, NULL, 0);
+ continue;
+ case '?':
+ case 'h':
+ default:
+usage:
+ fprintf(stderr,
+ "usage: %s [options]\n"
+ "Options:\n"
+ "\t-D <dev> pci endpoint test device {default: /dev/pci-endpoint-test.0}\n"
+ "\t-b <bar num> BAR test (bar number between 0..5)\n"
+ "\t-m <msi num> MSI test (msi number between 1..32)\n"
+ "\t-r Read buffer test\n"
+ "\t-w Write buffer test\n"
+ "\t-c Copy buffer test\n"
+ "\t-s <size> Size of buffer {default: 100KB}\n",
+ argv[0]);
+ return -EINVAL;
+ }
+
+ run_test(test);
+ return 0;
+}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 19/22] tools: PCI: Add sample test script to invoke pcitest
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
` (17 preceding siblings ...)
2017-02-17 9:50 ` [PATCH v2 18/22] tools: PCI: Add a userspace tool to test PCI endpoint Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-17 9:50 ` [PATCH v2 20/22] Documentation: PCI: Add userguide for PCI endpoint test function Kishon Vijay Abraham I
` (2 subsequent siblings)
21 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: linux-pci, linux-doc, linux-kernel, devicetree, linux-omap,
linux-arm-kernel, nsekhar, Kishon Vijay Abraham I
Add a simple test script that invokes the pcitest userspace tool
to perform all the PCI endpoint tests (BAR tests, interrupt tests,
read tests, write tests and copy tests).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
tools/pci/pcitest.sh | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
create mode 100644 tools/pci/pcitest.sh
diff --git a/tools/pci/pcitest.sh b/tools/pci/pcitest.sh
new file mode 100644
index 0000000..5442bbe
--- /dev/null
+++ b/tools/pci/pcitest.sh
@@ -0,0 +1,56 @@
+#!/bin/sh
+
+echo "BAR tests"
+echo
+
+bar=0
+
+while [ $bar -lt 6 ]
+do
+ pcitest -b $bar
+ bar=`expr $bar + 1`
+done
+echo
+
+echo "Interrupt tests"
+echo
+
+pcitest -l
+msi=1
+
+while [ $msi -lt 33 ]
+do
+ pcitest -m $msi
+ msi=`expr $msi + 1`
+done
+echo
+
+echo "Read Tests"
+echo
+
+pcitest -r -s 1
+pcitest -r -s 1024
+pcitest -r -s 1025
+pcitest -r -s 1024000
+pcitest -r -s 1024001
+echo
+
+echo "Write Tests"
+echo
+
+pcitest -w -s 1
+pcitest -w -s 1024
+pcitest -w -s 1025
+pcitest -w -s 1024000
+pcitest -w -s 1024001
+echo
+
+echo "Copy Tests"
+echo
+
+pcitest -c -s 1
+pcitest -c -s 1024
+pcitest -c -s 1025
+pcitest -c -s 1024000
+pcitest -c -s 1024001
+echo
--
1.7.9.5
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 20/22] Documentation: PCI: Add userguide for PCI endpoint test function
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
` (18 preceding siblings ...)
2017-02-17 9:50 ` [PATCH v2 19/22] tools: PCI: Add sample test script to invoke pcitest Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-17 9:50 ` [PATCH v2 21/22] MAINTAINERS: add PCI EP maintainer Kishon Vijay Abraham I
2017-02-17 9:50 ` [PATCH v2 22/22] ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP Kishon Vijay Abraham I
21 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: devicetree, linux-doc, linux-pci, nsekhar, linux-kernel,
Kishon Vijay Abraham I, linux-omap, linux-arm-kernel
Add documentation to help users use pci-epf-test function driver
and pci_endpoint_test host driver for testing PCI.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Documentation/PCI/endpoint/pci-test-howto.txt | 167 +++++++++++++++++++++++++
1 file changed, 167 insertions(+)
create mode 100644 Documentation/PCI/endpoint/pci-test-howto.txt
diff --git a/Documentation/PCI/endpoint/pci-test-howto.txt b/Documentation/PCI/endpoint/pci-test-howto.txt
new file mode 100644
index 0000000..4141b2b
--- /dev/null
+++ b/Documentation/PCI/endpoint/pci-test-howto.txt
@@ -0,0 +1,167 @@
+ PCI TEST USERGUIDE
+ Kishon Vijay Abraham I <kishon@ti.com>
+
+This document is a guide to help users use pci-epf-test function driver
+and pci_endpoint_test host driver for testing PCI. The list of steps to
+be followed in the host side and EP side is given below.
+
+1. Endpoint Device
+
+1.1 Endpoint Controller Devices
+
+To find the list of endpoint controller devices in the system:
+
+ # ls /sys/class/pci_epc/
+ 51000000.pcie_ep
+
+1.2 Endpoint Function Drivers
+
+To find the list of endpoint function drivers in the system:
+
+ # ls /sys/bus/pci-epf/drivers
+ pci_epf_test
+
+1.3 Creating pci-epf-test Device
+
+PCI endpoint function device can be created using the configfs. To create
+pci-epf-test device, the following commands can be used
+
+ # mount -t configfs none /sys/kernel/config
+ # cd /sys/kernel/config/pci_ep/
+ # mkdir dev
+ # mkdir dev/epf/pci_epf_test.0
+
+The "mkdir dev/epf/pci_epf_test.0" above creates the pci-epf-test function
+device. The name given to the directory preceding '.' should match with the
+name of the driver listed in '/sys/bus/pci-epf/drivers' in order for the
+device to be bound to the driver.
+
+The PCI endpoint framework populates the directory with configurable fields.
+
+ # ls dev/epf/pci_epf_test.0/
+ baseclass_code function revid vendorid
+ cache_line_size interrupt_pin subclass_code
+ deviceid peripheral subsys_id
+ epc progif_code subsys_vendor_id
+
+The pci endpoint function driver populates these entries with default values
+when the device is bound to the driver. The pci-epf-test driver populates
+vendorid with 0xffff and interrupt_pin with 0x0001
+
+ # cat dev/epf/pci_epf_test.0/vendorid
+ 0xffff
+ # cat dev/epf/pci_epf_test.0/interrupt_pin
+ 0x0001
+
+1.4 Configuring pci-epf-test Device
+
+The user can configure the pci-epf-test device using configfs entry. In order
+to change the vendorid and the number of MSI interrupts used by the function
+device, the following commands can be used.
+
+ # echo 0x104c > dev/epf/pci_epf_test.0/vendorid
+ # echo 0xb500 > dev/epf/pci_epf_test.0/deviceid
+ # echo 16 > dev/epf/pci_epf_test.0/msi_interrupts
+
+1.5 Binding pci-epf-test Device to EP Controller
+
+In order for the endpoint function device to be useful, it has to be bound to
+a PCI endpoint controller driver. Use the configfs to bind the function
+device to one of the controller driver present in the system.
+
+ # echo "51000000.pcie_ep" > dev/epc
+
+Once the above step is completed, the PCI endpoint is ready to establish a link
+with the host.
+
+2. Endpoint Device
+
+2.1 lspci Output
+
+Note that the devices listed here correspond to the value populated in 1.4 above
+
+ 00:00.0 PCI bridge: Texas Instruments Device 8888 (rev 01)
+ 01:00.0 Unassigned class [ff00]: Texas Instruments Device b500
+
+2.2 Using Endpoint Test function Device
+
+pcitest.sh added in tools/pci/ can be used to run all the default PCI endpoint
+tests. Before pcitest.sh can be used pcitest.c should be compiled using the
+following commands.
+
+ cd <kernel-dir>
+ make headers_install ARCH=arm
+ arm-linux-gnueabihf-gcc -Iusr/include tools/pci/pcitest.c -o pcitest
+ cp pcitest <rootfs>/usr/sbin/
+ cp tools/pci/pcitest.sh <rootfs>
+
+2.2.1 pcitest.sh Output
+ # ./pcitest.sh
+ BAR tests
+
+ BAR0: OKAY
+ BAR1: OKAY
+ BAR2: OKAY
+ BAR3: OKAY
+ BAR4: NOT OKAY
+ BAR5: NOT OKAY
+
+ Interrupt tests
+
+ LEGACY IRQ: NOT OKAY
+ MSI1: OKAY
+ MSI2: OKAY
+ MSI3: OKAY
+ MSI4: OKAY
+ MSI5: OKAY
+ MSI6: OKAY
+ MSI7: OKAY
+ MSI8: OKAY
+ MSI9: OKAY
+ MSI10: OKAY
+ MSI11: OKAY
+ MSI12: OKAY
+ MSI13: OKAY
+ MSI14: OKAY
+ MSI15: OKAY
+ MSI16: OKAY
+ MSI17: NOT OKAY
+ MSI18: NOT OKAY
+ MSI19: NOT OKAY
+ MSI20: NOT OKAY
+ MSI21: NOT OKAY
+ MSI22: NOT OKAY
+ MSI23: NOT OKAY
+ MSI24: NOT OKAY
+ MSI25: NOT OKAY
+ MSI26: NOT OKAY
+ MSI27: NOT OKAY
+ MSI28: NOT OKAY
+ MSI29: NOT OKAY
+ MSI30: NOT OKAY
+ MSI31: NOT OKAY
+ MSI32: NOT OKAY
+
+ Read Tests
+
+ READ ( 1 bytes): OKAY
+ READ ( 1024 bytes): OKAY
+ READ ( 1025 bytes): OKAY
+ READ (1024000 bytes): OKAY
+ READ (1024001 bytes): OKAY
+
+ Write Tests
+
+ WRITE ( 1 bytes): OKAY
+ WRITE ( 1024 bytes): OKAY
+ WRITE ( 1025 bytes): OKAY
+ WRITE (1024000 bytes): OKAY
+ WRITE (1024001 bytes): OKAY
+
+ Copy Tests
+
+ COPY ( 1 bytes): OKAY
+ COPY ( 1024 bytes): OKAY
+ COPY ( 1025 bytes): OKAY
+ COPY (1024000 bytes): OKAY
+ COPY (1024001 bytes): OKAY
--
1.7.9.5
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 21/22] MAINTAINERS: add PCI EP maintainer
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
` (19 preceding siblings ...)
2017-02-17 9:50 ` [PATCH v2 20/22] Documentation: PCI: Add userguide for PCI endpoint test function Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
2017-02-17 9:50 ` [PATCH v2 22/22] ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP Kishon Vijay Abraham I
21 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: linux-pci, linux-doc, linux-kernel, devicetree, linux-omap,
linux-arm-kernel, nsekhar, Kishon Vijay Abraham I
Add maintainer for the newly introduced PCI EP framework.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8672f18..62b86af 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9407,6 +9407,15 @@ F: include/linux/pci*
F: arch/x86/pci/
F: arch/x86/kernel/quirks.c
+PCI EP SUBSYSTEM
+M: Kishon Vijay Abraham I <kishon@ti.com>
+L: linux-pci@vger.kernel.org
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/kishon/pci-endpoint.git
+S: Supported
+F: drivers/pci/endpoint/
+F: drivers/misc/pci_endpoint_test.c
+F: tools/pci/
+
PCI DRIVER FOR ALTERA PCIE IP
M: Ley Foon Tan <lftan@altera.com>
L: rfi@lists.rocketboards.org (moderated for non-subscribers)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 22/22] ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP
2017-02-17 9:50 [PATCH v2 00/22] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I
` (20 preceding siblings ...)
2017-02-17 9:50 ` [PATCH v2 21/22] MAINTAINERS: add PCI EP maintainer Kishon Vijay Abraham I
@ 2017-02-17 9:50 ` Kishon Vijay Abraham I
21 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2017-02-17 9:50 UTC (permalink / raw)
To: Bjorn Helgaas, Jingoo Han, Joao Pinto
Cc: linux-pci, linux-doc, linux-kernel, devicetree, linux-omap,
linux-arm-kernel, nsekhar, Kishon Vijay Abraham I
The PCIe programming sequence in TRM suggests CLKSTCTRL of PCIe should
be set to SW_WKUP. There are no issues when CLKSTCTRL is set to HW_AUTO
in RC mode. However in EP mode, the host system is not able to access the
MEMSPACE and setting the CLKSTCTRL to SW_WKUP fixes it.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/mach-omap2/clockdomains7xx_data.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c
index 6c67965..67ebff8 100644
--- a/arch/arm/mach-omap2/clockdomains7xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains7xx_data.c
@@ -524,7 +524,7 @@
.dep_bit = DRA7XX_PCIE_STATDEP_SHIFT,
.wkdep_srcs = pcie_wkup_sleep_deps,
.sleepdep_srcs = pcie_wkup_sleep_deps,
- .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain atl_7xx_clkdm = {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 49+ messages in thread