From: vincentc@andestech.com (Vincent Chen) To: linux-riscv@lists.infradead.org Subject: [RFC 0/2] RISC-V: A proposal to add vendor-specific code Date: Wed, 31 Oct 2018 18:35:28 +0800 [thread overview] Message-ID: <1540982130-28248-1-git-send-email-vincentc@andestech.com> (raw) RISC-V permits each vendor to develop respective extension ISA based on RISC-V standard ISA. This means that these vendor-specific features may be compatible to their compiler and CPU. Therefore, each vendor may be considered a sub-architecture of RISC-V. Currently, vendors do not have the appropriate examples to add these specific features to the kernel. In this RFC set, we propose an infrastructure that vendor can easily hook their specific features into kernel. The first commit is the main body of this infrastructure. In the second commit, we provide a solution that allows dma_map_ops() to work without cache coherent agent support. Cache coherent agent is unsupported for low-end CPUs in the AndeStar RISC-V series. In order for Linux to run on these CPUs, we need this solution to overcome the limitation of cache coherent agent support. Hence, it also can be used as an example for the first commit. I am glad to discuss any ideas, so if you have any idea, please give me some feedback. Vincent Chen (2): RISC-V: An infrastructure to add vendor-specific code. RISC-V: make dma_map_ops work without cache coherent agent arch/riscv/Kconfig | 49 +++++ arch/riscv/Makefile | 6 + arch/riscv/include/asm/sbi.h | 6 + arch/riscv/include/asm/vendor-hook.h | 13 ++ arch/riscv/kernel/cpufeature.c | 5 + arch/riscv/kernel/setup.c | 6 +- arch/riscv/vendor-nds/Kconfig | 29 +++ arch/riscv/vendor-nds/Makefile | 1 + arch/riscv/vendor-nds/cache.c | 83 ++++++++ arch/riscv/vendor-nds/include/asm/csr.h | 32 +++ arch/riscv/vendor-nds/include/asm/dma-mapping.h | 24 +++ arch/riscv/vendor-nds/include/asm/proc.h | 17 ++ arch/riscv/vendor-nds/include/asm/sbi.h | 17 ++ arch/riscv/vendor-nds/include/asm/vendor-hook.h | 8 + arch/riscv/vendor-nds/noncoherent_dma.c | 254 +++++++++++++++++++++++ arch/riscv/vendor-nds/setup.c | 16 ++ 16 files changed, 565 insertions(+), 1 deletions(-) create mode 100644 arch/riscv/include/asm/vendor-hook.h create mode 100644 arch/riscv/vendor-nds/Kconfig create mode 100644 arch/riscv/vendor-nds/Makefile create mode 100644 arch/riscv/vendor-nds/cache.c create mode 100644 arch/riscv/vendor-nds/include/asm/csr.h create mode 100644 arch/riscv/vendor-nds/include/asm/dma-mapping.h create mode 100644 arch/riscv/vendor-nds/include/asm/proc.h create mode 100644 arch/riscv/vendor-nds/include/asm/sbi.h create mode 100644 arch/riscv/vendor-nds/include/asm/vendor-hook.h create mode 100644 arch/riscv/vendor-nds/noncoherent_dma.c create mode 100644 arch/riscv/vendor-nds/setup.c
WARNING: multiple messages have this Message-ID (diff)
From: Vincent Chen <vincentc@andestech.com> To: <palmer@sifive.com>, <aou@eecs.berkeley.edu> Cc: zong@andestech.com, arnd@arndb.de, alankao@andestech.com, greentime@andestech.com, linux-kernel@vger.kernel.org, vincentc@andestech.com, linux-riscv@lists.infradead.org, deanbo422@gmail.com Subject: [RFC 0/2] RISC-V: A proposal to add vendor-specific code Date: Wed, 31 Oct 2018 18:35:28 +0800 [thread overview] Message-ID: <1540982130-28248-1-git-send-email-vincentc@andestech.com> (raw) Message-ID: <20181031103528.UGpH_GiF5onaMlO369CLRzZSM59kqpCX_aO230XfY1M@z> (raw) RISC-V permits each vendor to develop respective extension ISA based on RISC-V standard ISA. This means that these vendor-specific features may be compatible to their compiler and CPU. Therefore, each vendor may be considered a sub-architecture of RISC-V. Currently, vendors do not have the appropriate examples to add these specific features to the kernel. In this RFC set, we propose an infrastructure that vendor can easily hook their specific features into kernel. The first commit is the main body of this infrastructure. In the second commit, we provide a solution that allows dma_map_ops() to work without cache coherent agent support. Cache coherent agent is unsupported for low-end CPUs in the AndeStar RISC-V series. In order for Linux to run on these CPUs, we need this solution to overcome the limitation of cache coherent agent support. Hence, it also can be used as an example for the first commit. I am glad to discuss any ideas, so if you have any idea, please give me some feedback. Vincent Chen (2): RISC-V: An infrastructure to add vendor-specific code. RISC-V: make dma_map_ops work without cache coherent agent arch/riscv/Kconfig | 49 +++++ arch/riscv/Makefile | 6 + arch/riscv/include/asm/sbi.h | 6 + arch/riscv/include/asm/vendor-hook.h | 13 ++ arch/riscv/kernel/cpufeature.c | 5 + arch/riscv/kernel/setup.c | 6 +- arch/riscv/vendor-nds/Kconfig | 29 +++ arch/riscv/vendor-nds/Makefile | 1 + arch/riscv/vendor-nds/cache.c | 83 ++++++++ arch/riscv/vendor-nds/include/asm/csr.h | 32 +++ arch/riscv/vendor-nds/include/asm/dma-mapping.h | 24 +++ arch/riscv/vendor-nds/include/asm/proc.h | 17 ++ arch/riscv/vendor-nds/include/asm/sbi.h | 17 ++ arch/riscv/vendor-nds/include/asm/vendor-hook.h | 8 + arch/riscv/vendor-nds/noncoherent_dma.c | 254 +++++++++++++++++++++++ arch/riscv/vendor-nds/setup.c | 16 ++ 16 files changed, 565 insertions(+), 1 deletions(-) create mode 100644 arch/riscv/include/asm/vendor-hook.h create mode 100644 arch/riscv/vendor-nds/Kconfig create mode 100644 arch/riscv/vendor-nds/Makefile create mode 100644 arch/riscv/vendor-nds/cache.c create mode 100644 arch/riscv/vendor-nds/include/asm/csr.h create mode 100644 arch/riscv/vendor-nds/include/asm/dma-mapping.h create mode 100644 arch/riscv/vendor-nds/include/asm/proc.h create mode 100644 arch/riscv/vendor-nds/include/asm/sbi.h create mode 100644 arch/riscv/vendor-nds/include/asm/vendor-hook.h create mode 100644 arch/riscv/vendor-nds/noncoherent_dma.c create mode 100644 arch/riscv/vendor-nds/setup.c _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next reply other threads:[~2018-10-31 10:35 UTC|newest] Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-10-31 10:35 Vincent Chen [this message] 2018-10-31 10:35 ` [RFC 0/2] RISC-V: A proposal to add vendor-specific code Vincent Chen 2018-10-31 10:35 ` [RFC 1/2] RISC-V: An infrastructure " Vincent Chen 2018-10-31 10:35 ` Vincent Chen 2018-10-31 10:35 ` [RFC 2/2] RISC-V: make dma_map_ops work without cache coherent agent Vincent Chen 2018-10-31 10:35 ` Vincent Chen 2018-10-31 11:16 ` [RFC 0/2] RISC-V: A proposal to add vendor-specific code Anup Patel 2018-10-31 11:16 ` Anup Patel 2018-10-31 11:45 ` Arnd Bergmann 2018-10-31 11:45 ` Arnd Bergmann 2018-10-31 14:17 ` Christoph Hellwig 2018-10-31 14:17 ` Christoph Hellwig 2018-11-01 0:55 ` Alan Kao 2018-11-01 0:55 ` Alan Kao 2018-11-01 17:50 ` Palmer Dabbelt 2018-11-01 17:50 ` Palmer Dabbelt 2018-11-02 0:41 ` Alan Kao 2018-11-02 0:41 ` Alan Kao 2018-10-31 17:27 ` Palmer Dabbelt 2018-10-31 17:27 ` Palmer Dabbelt 2018-10-31 19:17 ` Olof Johansson 2018-10-31 19:17 ` Olof Johansson 2018-11-01 17:48 ` Karsten Merker 2018-11-05 6:58 ` Vincent Chen 2018-11-05 6:58 ` Vincent Chen 2018-11-05 7:05 ` Christoph Hellwig 2018-11-05 7:05 ` Christoph Hellwig 2018-11-05 8:52 ` Arnd Bergmann 2018-11-05 8:52 ` Arnd Bergmann 2018-11-05 9:08 ` Christoph Hellwig 2018-11-05 9:08 ` Christoph Hellwig 2018-11-05 13:51 ` Arnd Bergmann 2018-11-05 13:51 ` Arnd Bergmann 2018-11-06 6:59 ` Christoph Hellwig 2018-11-06 6:59 ` Christoph Hellwig 2018-11-06 23:45 ` Palmer Dabbelt 2018-11-06 23:45 ` Palmer Dabbelt 2018-11-07 9:51 ` Arnd Bergmann 2018-11-07 9:51 ` Arnd Bergmann 2018-11-06 23:45 ` Palmer Dabbelt 2018-11-06 23:45 ` Palmer Dabbelt 2018-11-08 2:43 ` Vincent Chen 2018-11-08 2:43 ` Vincent Chen 2018-11-05 19:39 ` Nick Kossifidis 2018-11-05 19:39 ` Nick Kossifidis 2018-11-06 6:56 ` Christoph Hellwig 2018-11-06 6:56 ` Christoph Hellwig
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