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From: Palmer Dabbelt <palmer@sifive.com>
To: Arnd Bergmann <arnd@arndb.de>
Cc: vincentc@andestech.com, aou@eecs.berkeley.edu,
	alankao@andestech.com, greentime@andestech.com,
	zong@andestech.com, linux-kernel@vger.kernel.org,
	Christoph Hellwig <hch@infradead.org>,
	kito@andestech.com, linux-riscv@lists.infradead.org,
	deanbo422@gmail.com
Subject: Re: [RFC 0/2] RISC-V: A proposal to add vendor-specific code
Date: Tue, 06 Nov 2018 15:45:54 -0800 (PST)	[thread overview]
Message-ID: <mhng-19511b81-9f89-4a15-8b2f-d63779074fb4@palmer-si-x1c4> (raw)
Message-ID: <20181106234554.TYDmabd6uMVCvOOJIMpnPO5pbd_9Wl6qEuZlIOKbICQ@z> (raw)
In-Reply-To: <CAK8P3a2c98VVPArCkdAR=-nnDBq1gYRCLDDgQB71eGiTSRdb4A@mail.gmail.com>

On Mon, 05 Nov 2018 00:52:52 PST (-0800), Arnd Bergmann wrote:
> On 11/5/18, Christoph Hellwig <hch@infradead.org> wrote:
>> On Mon, Nov 05, 2018 at 02:58:07PM +0800, Vincent Chen wrote:
>>> Many thanks for kinds of comments. I quickly synthesize the comments and
>>> list them as below.
>>> 1. The kernel image shall include all vendor-specific code.
>>
>> I fundamentally disagree with this… and think it should be the contrary.
>>
>> 1. The kernel shall support no vendor specific instructions whatsoever,
>> period.
>
> I think what was meant above is
>
> 1. If a vendor extension requires kernel support, that support
> must be able to be built into a kernel image without breaking support
> for CPUs that do not have that extension, to allow building a single
> kernel image that works on all CPUs.

Yes.  I don't want anything that won't compile with upstream GCC, but I also 
don't want to have a Kconfig that says "make the kernel only work on $VENDOR's 
implementation".  I think this can be achieved, at least for the cases I've 
seen so far.

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  parent reply	other threads:[~2018-11-06 23:46 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-31 10:35 [RFC 0/2] RISC-V: A proposal to add vendor-specific code Vincent Chen
2018-10-31 10:35 ` Vincent Chen
2018-10-31 10:35 ` [RFC 1/2] RISC-V: An infrastructure " Vincent Chen
2018-10-31 10:35   ` Vincent Chen
2018-10-31 10:35 ` [RFC 2/2] RISC-V: make dma_map_ops work without cache coherent agent Vincent Chen
2018-10-31 10:35   ` Vincent Chen
2018-10-31 11:16 ` [RFC 0/2] RISC-V: A proposal to add vendor-specific code Anup Patel
2018-10-31 11:16   ` Anup Patel
2018-10-31 11:45   ` Arnd Bergmann
2018-10-31 11:45     ` Arnd Bergmann
2018-10-31 14:17   ` Christoph Hellwig
2018-10-31 14:17     ` Christoph Hellwig
2018-11-01  0:55     ` Alan Kao
2018-11-01  0:55       ` Alan Kao
2018-11-01 17:50       ` Palmer Dabbelt
2018-11-01 17:50         ` Palmer Dabbelt
2018-11-02  0:41         ` Alan Kao
2018-11-02  0:41           ` Alan Kao
2018-10-31 17:27   ` Palmer Dabbelt
2018-10-31 17:27     ` Palmer Dabbelt
2018-10-31 19:17     ` Olof Johansson
2018-10-31 19:17       ` Olof Johansson
2018-11-01 17:48     ` Karsten Merker
2018-11-05  6:58       ` Vincent Chen
2018-11-05  6:58         ` Vincent Chen
2018-11-05  7:05         ` Christoph Hellwig
2018-11-05  7:05           ` Christoph Hellwig
2018-11-05  8:52           ` Arnd Bergmann
2018-11-05  8:52             ` Arnd Bergmann
2018-11-05  9:08             ` Christoph Hellwig
2018-11-05  9:08               ` Christoph Hellwig
2018-11-05 13:51               ` Arnd Bergmann
2018-11-05 13:51                 ` Arnd Bergmann
2018-11-06  6:59                 ` Christoph Hellwig
2018-11-06  6:59                   ` Christoph Hellwig
2018-11-06 23:45             ` Palmer Dabbelt [this message]
2018-11-06 23:45               ` Palmer Dabbelt
2018-11-07  9:51               ` Arnd Bergmann
2018-11-07  9:51                 ` Arnd Bergmann
2018-11-06 23:45         ` Palmer Dabbelt
2018-11-06 23:45           ` Palmer Dabbelt
2018-11-08  2:43           ` Vincent Chen
2018-11-08  2:43             ` Vincent Chen
2018-11-05 19:39 ` Nick Kossifidis
2018-11-05 19:39   ` Nick Kossifidis
2018-11-06  6:56   ` Christoph Hellwig
2018-11-06  6:56     ` Christoph Hellwig

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