linux-riscv.lists.infradead.org archive mirror
 help / color / mirror / Atom feed
From: alankao@andestech.com (Alan Kao)
To: linux-riscv@lists.infradead.org
Subject: [RFC 0/2] RISC-V: A proposal to add vendor-specific code
Date: Fri, 2 Nov 2018 08:41:22 +0800	[thread overview]
Message-ID: <20181102004122.GA22741@andestech.com> (raw)
In-Reply-To: <mhng-22ded2c8-7f87-4acc-b017-627e369cf874@palmer-si-x1c4>

On Thu, Nov 01, 2018 at 10:50:04AM -0700, Palmer Dabbelt wrote:
> On Wed, 31 Oct 2018 17:55:42 PDT (-0700), alankao at andestech.com wrote:
> >On Wed, Oct 31, 2018 at 07:17:45AM -0700, Christoph Hellwig wrote:
> >>On Wed, Oct 31, 2018 at 04:46:10PM +0530, Anup Patel wrote:
> >>> I agree that we need a place for vendor-specific ISA extensions and
> >>> having vendor-specific directories is also good.
> >>
> >>The only sensible answer is that we should not allow vendor specific
> >>extensions in the kernel at all.  ...
> >
> >How can this even be possible if a extension includes an extra register
> >set as some domain-specific context?  In such a case, kernel should
> >at least process the context during any context switch, just like how it
> >deals with the FP context.
> 
> Ya, I think there are cases where vendor-specific extensions are going to be
> necessary to handle within the kernel.  Right now the only one I can think
> of is the performance counter stuff, where we explicitly allow
> vendor-specific counters as part of the ISA spec.
> 
> For stateful extensions, we currently have a standard mechanism where the XS
> bits get set in sstatus and the actual save/restore code is hidden behind an
> SBI call.  That call doesn't currently exist, but if we just go ahead and
> add one it should be easy to support this from within Linux.  We'll need to
> figure out how to enable these custom extensions from userspace, but that
> seems tractable as well.  We'll probably also want some fast-path for the V
> extension (and any other stateful standard extensions), but I think as long
> as the V extension adds a quick check for dirtiness then it's not a big
> deal.
> 
> Do you guys have stateful extensions?  We're trying really hard to avoid
> them at SiFive because they're a huge headache, so unless there's a
> compelling base of software using one I don't want to go add support if we
> can avoid it.

Currently no, but the future is hard to see.  As long as the extensible freedom
claimed by the RISC-V foundation remains true, such extensions may have their
role to play.  Don't worry now, I was just to give a example that in some 
possible vendor-specific cases the kernel cannot keep itself from involving.

WARNING: multiple messages have this Message-ID (diff)
From: Alan Kao <alankao@andestech.com>
To: Palmer Dabbelt <palmer@sifive.com>
Cc: zong@andestech.com, aou@eecs.berkeley.edu,
	Arnd Bergmann <arnd@arndb.de>,
	greentime@andestech.com, anup@brainfault.org,
	linux-kernel@vger.kernel.org,
	Christoph Hellwig <hch@infradead.org>,
	vincentc@andestech.com, linux-riscv@lists.infradead.org,
	deanbo422@gmail.com
Subject: Re: [RFC 0/2] RISC-V: A proposal to add vendor-specific code
Date: Fri, 2 Nov 2018 08:41:22 +0800	[thread overview]
Message-ID: <20181102004122.GA22741@andestech.com> (raw)
Message-ID: <20181102004122.vGOBQZwqy2VhSw1CyuKRuIsvsH-F90CnsOT9r17fk9Y@z> (raw)
In-Reply-To: <mhng-22ded2c8-7f87-4acc-b017-627e369cf874@palmer-si-x1c4>

On Thu, Nov 01, 2018 at 10:50:04AM -0700, Palmer Dabbelt wrote:
> On Wed, 31 Oct 2018 17:55:42 PDT (-0700), alankao@andestech.com wrote:
> >On Wed, Oct 31, 2018 at 07:17:45AM -0700, Christoph Hellwig wrote:
> >>On Wed, Oct 31, 2018 at 04:46:10PM +0530, Anup Patel wrote:
> >>> I agree that we need a place for vendor-specific ISA extensions and
> >>> having vendor-specific directories is also good.
> >>
> >>The only sensible answer is that we should not allow vendor specific
> >>extensions in the kernel at all.  ...
> >
> >How can this even be possible if a extension includes an extra register
> >set as some domain-specific context?  In such a case, kernel should
> >at least process the context during any context switch, just like how it
> >deals with the FP context.
> 
> Ya, I think there are cases where vendor-specific extensions are going to be
> necessary to handle within the kernel.  Right now the only one I can think
> of is the performance counter stuff, where we explicitly allow
> vendor-specific counters as part of the ISA spec.
> 
> For stateful extensions, we currently have a standard mechanism where the XS
> bits get set in sstatus and the actual save/restore code is hidden behind an
> SBI call.  That call doesn't currently exist, but if we just go ahead and
> add one it should be easy to support this from within Linux.  We'll need to
> figure out how to enable these custom extensions from userspace, but that
> seems tractable as well.  We'll probably also want some fast-path for the V
> extension (and any other stateful standard extensions), but I think as long
> as the V extension adds a quick check for dirtiness then it's not a big
> deal.
> 
> Do you guys have stateful extensions?  We're trying really hard to avoid
> them at SiFive because they're a huge headache, so unless there's a
> compelling base of software using one I don't want to go add support if we
> can avoid it.

Currently no, but the future is hard to see.  As long as the extensible freedom
claimed by the RISC-V foundation remains true, such extensions may have their
role to play.  Don't worry now, I was just to give a example that in some 
possible vendor-specific cases the kernel cannot keep itself from involving.


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2018-11-02  0:41 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-31 10:35 [RFC 0/2] RISC-V: A proposal to add vendor-specific code Vincent Chen
2018-10-31 10:35 ` Vincent Chen
2018-10-31 10:35 ` [RFC 1/2] RISC-V: An infrastructure " Vincent Chen
2018-10-31 10:35   ` Vincent Chen
2018-10-31 10:35 ` [RFC 2/2] RISC-V: make dma_map_ops work without cache coherent agent Vincent Chen
2018-10-31 10:35   ` Vincent Chen
2018-10-31 11:16 ` [RFC 0/2] RISC-V: A proposal to add vendor-specific code Anup Patel
2018-10-31 11:16   ` Anup Patel
2018-10-31 11:45   ` Arnd Bergmann
2018-10-31 11:45     ` Arnd Bergmann
2018-10-31 14:17   ` Christoph Hellwig
2018-10-31 14:17     ` Christoph Hellwig
2018-11-01  0:55     ` Alan Kao
2018-11-01  0:55       ` Alan Kao
2018-11-01 17:50       ` Palmer Dabbelt
2018-11-01 17:50         ` Palmer Dabbelt
2018-11-02  0:41         ` Alan Kao [this message]
2018-11-02  0:41           ` Alan Kao
2018-10-31 17:27   ` Palmer Dabbelt
2018-10-31 17:27     ` Palmer Dabbelt
2018-10-31 19:17     ` Olof Johansson
2018-10-31 19:17       ` Olof Johansson
2018-11-01 17:48     ` Karsten Merker
2018-11-05  6:58       ` Vincent Chen
2018-11-05  6:58         ` Vincent Chen
2018-11-05  7:05         ` Christoph Hellwig
2018-11-05  7:05           ` Christoph Hellwig
2018-11-05  8:52           ` Arnd Bergmann
2018-11-05  8:52             ` Arnd Bergmann
2018-11-05  9:08             ` Christoph Hellwig
2018-11-05  9:08               ` Christoph Hellwig
2018-11-05 13:51               ` Arnd Bergmann
2018-11-05 13:51                 ` Arnd Bergmann
2018-11-06  6:59                 ` Christoph Hellwig
2018-11-06  6:59                   ` Christoph Hellwig
2018-11-06 23:45             ` Palmer Dabbelt
2018-11-06 23:45               ` Palmer Dabbelt
2018-11-07  9:51               ` Arnd Bergmann
2018-11-07  9:51                 ` Arnd Bergmann
2018-11-06 23:45         ` Palmer Dabbelt
2018-11-06 23:45           ` Palmer Dabbelt
2018-11-08  2:43           ` Vincent Chen
2018-11-08  2:43             ` Vincent Chen
2018-11-05 19:39 ` Nick Kossifidis
2018-11-05 19:39   ` Nick Kossifidis
2018-11-06  6:56   ` Christoph Hellwig
2018-11-06  6:56     ` Christoph Hellwig

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20181102004122.GA22741@andestech.com \
    --to=alankao@andestech.com \
    --cc=linux-riscv@lists.infradead.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).