From: "Fenghua Yu" <fenghua.yu@intel.com>
To: "Thomas Gleixner" <tglx@linutronix.de>
Cc: "H. Peter Anvin" <h.peter.anvin@intel.com>,
"Ingo Molnar" <mingo@elte.hu>, "Tony Luck" <tony.luck@intel.com>,
"Peter Zijlstra" <peterz@infradead.org>,
"Stephane Eranian" <eranian@google.com>,
"Borislav Petkov" <bp@suse.de>,
"Dave Hansen" <dave.hansen@intel.com>,
"Nilay Vaish" <nilayvaish@gmail.com>, "Shaohua Li" <shli@fb.com>,
"David Carrillo-Cisneros" <davidcc@google.com>,
"Ravi V Shankar" <ravi.v.shankar@intel.com>,
"Sai Prakhya" <sai.praneeth.prakhya@intel.com>,
"Vikas Shivappa" <vikas.shivappa@linux.intel.com>,
"linux-kernel" <linux-kernel@vger.kernel.org>,
"x86" <x86@kernel.org>, "Fenghua Yu" <fenghua.yu@intel.com>
Subject: [PATCH v3 09/18] x86/cqm: Move PQR_ASSOC management code into generic code used by both CQM and CAT
Date: Fri, 7 Oct 2016 19:45:54 -0700 [thread overview]
Message-ID: <1475894763-64683-10-git-send-email-fenghua.yu@intel.com> (raw)
In-Reply-To: <1475894763-64683-1-git-send-email-fenghua.yu@intel.com>
From: Fenghua Yu <fenghua.yu@intel.com>
A CLOSID goes into effect when written to the PQR_ASSOC MSR. But this MSR
also contains the RMID used for preformance monitoring of cache occupancy
and memory bandwidth. Move the management code for this MSR out of
arch/x86/events/intel/cqm.c and into generic RDT code so we can coordinate
updates to the MSR.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
---
arch/x86/events/intel/cqm.c | 21 +--------------------
arch/x86/include/asm/intel_rdt_common.h | 21 +++++++++++++++++++++
2 files changed, 22 insertions(+), 20 deletions(-)
diff --git a/arch/x86/events/intel/cqm.c b/arch/x86/events/intel/cqm.c
index df86874..0c45cc8 100644
--- a/arch/x86/events/intel/cqm.c
+++ b/arch/x86/events/intel/cqm.c
@@ -24,32 +24,13 @@ static unsigned int cqm_l3_scale; /* supposedly cacheline size */
static bool cqm_enabled, mbm_enabled;
unsigned int mbm_socket_max;
-/**
- * struct intel_pqr_state - State cache for the PQR MSR
- * @rmid: The cached Resource Monitoring ID
- * @closid: The cached Class Of Service ID
- * @rmid_usecnt: The usage counter for rmid
- *
- * The upper 32 bits of MSR_IA32_PQR_ASSOC contain closid and the
- * lower 10 bits rmid. The update to MSR_IA32_PQR_ASSOC always
- * contains both parts, so we need to cache them.
- *
- * The cache also helps to avoid pointless updates if the value does
- * not change.
- */
-struct intel_pqr_state {
- u32 rmid;
- u32 closid;
- int rmid_usecnt;
-};
-
/*
* The cached intel_pqr_state is strictly per CPU and can never be
* updated from a remote CPU. Both functions which modify the state
* (intel_cqm_event_start and intel_cqm_event_stop) are called with
* interrupts disabled, which is sufficient for the protection.
*/
-static DEFINE_PER_CPU(struct intel_pqr_state, pqr_state);
+DEFINE_PER_CPU(struct intel_pqr_state, pqr_state);
static struct hrtimer *mbm_timers;
/**
* struct sample - mbm event's (local or total) data
diff --git a/arch/x86/include/asm/intel_rdt_common.h b/arch/x86/include/asm/intel_rdt_common.h
index e6e15cf..b31081b 100644
--- a/arch/x86/include/asm/intel_rdt_common.h
+++ b/arch/x86/include/asm/intel_rdt_common.h
@@ -3,4 +3,25 @@
#define MSR_IA32_PQR_ASSOC 0x0c8f
+/**
+ * struct intel_pqr_state - State cache for the PQR MSR
+ * @rmid: The cached Resource Monitoring ID
+ * @closid: The cached Class Of Service ID
+ * @rmid_usecnt: The usage counter for rmid
+ *
+ * The upper 32 bits of MSR_IA32_PQR_ASSOC contain closid and the
+ * lower 10 bits rmid. The update to MSR_IA32_PQR_ASSOC always
+ * contains both parts, so we need to cache them.
+ *
+ * The cache also helps to avoid pointless updates if the value does
+ * not change.
+ */
+struct intel_pqr_state {
+ u32 rmid;
+ u32 closid;
+ int rmid_usecnt;
+};
+
+DECLARE_PER_CPU(struct intel_pqr_state, pqr_state);
+
#endif /* _ASM_X86_INTEL_RDT_COMMON_H */
--
2.5.0
next prev parent reply other threads:[~2016-10-07 23:45 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-08 2:45 [PATCH v3 00/18] Intel Cache Allocation Technology Fenghua Yu
2016-10-07 23:54 ` [RFC PATCH 19/18] x86/intel_rdt: Add support for L2 cache allocation Luck, Tony
2016-10-08 2:45 ` [PATCH v3 01/18] Documentation, ABI: Add a document entry for cache id Fenghua Yu
2016-10-08 17:11 ` Nilay Vaish
2016-10-10 16:45 ` Luck, Tony
2016-10-11 16:48 ` Nilay Vaish
2016-10-08 2:45 ` [PATCH v3 02/18] cacheinfo: Introduce " Fenghua Yu
2016-10-08 17:10 ` Nilay Vaish
2016-10-08 2:45 ` [PATCH v3 03/18] x86, intel_cacheinfo: Enable cache id in x86 Fenghua Yu
2016-10-08 2:45 ` [PATCH v3 04/18] x86/intel_rdt: Feature discovery Fenghua Yu
2016-10-08 17:11 ` Nilay Vaish
2016-10-08 20:54 ` Fenghua Yu
2016-10-08 19:52 ` Borislav Petkov
2016-10-11 16:57 ` Nilay Vaish
2016-10-11 17:03 ` Borislav Petkov
2016-10-10 16:01 ` Dave Hansen
2016-10-10 16:18 ` Borislav Petkov
2016-10-08 2:45 ` [PATCH v3 05/18] Documentation, x86: Documentation for Intel resource allocation user interface Fenghua Yu
2016-10-08 17:12 ` Nilay Vaish
2016-10-08 20:33 ` Fenghua Yu
2016-10-10 17:19 ` Luck, Tony
2016-10-11 17:07 ` Nilay Vaish
2016-10-11 18:04 ` Luck, Tony
2016-10-08 2:45 ` [PATCH v3 06/18] x86/intel_rdt: Add CONFIG, Makefile, and basic initialization Fenghua Yu
2016-10-08 20:57 ` Borislav Petkov
2016-10-08 2:45 ` [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery Fenghua Yu
2016-10-09 11:41 ` Borislav Petkov
2016-10-09 17:09 ` Fenghua Yu
2016-10-09 16:28 ` Borislav Petkov
2016-10-10 18:55 ` Luck, Tony
2016-10-11 11:12 ` Borislav Petkov
2016-10-11 14:51 ` Luck, Tony
2016-10-08 2:45 ` [PATCH v3 08/18] x86/intel_rdt: Pick up L3 RDT parameters from CPUID Fenghua Yu
2016-10-08 2:45 ` Fenghua Yu [this message]
2016-10-08 2:45 ` [PATCH v3 10/18] x86/intel_rdt: Build structures for each resource based on cache topology Fenghua Yu
2016-10-09 21:57 ` Nilay Vaish
2016-10-08 2:45 ` [PATCH v3 11/18] x86/intel_rdt: Add basic resctrl filesystem support Fenghua Yu
2016-10-09 22:31 ` Nilay Vaish
2016-10-10 23:44 ` Luck, Tony
2016-10-08 2:45 ` [PATCH v3 12/18] x86/intel_rdt: Add "info" files to resctrl file system Fenghua Yu
2016-10-08 2:45 ` [PATCH v3 13/18] x86/intel_rdt: Add mkdir " Fenghua Yu
2016-10-10 17:51 ` Nilay Vaish
2016-10-08 2:45 ` [PATCH v3 14/18] x86/intel_rdt: Add cpus file Fenghua Yu
2016-10-08 2:46 ` [PATCH v3 15/18] x86/intel_rdt: Add tasks files Fenghua Yu
2016-10-08 2:46 ` [PATCH v3 16/18] x86/intel_rdt: Add schemata file Fenghua Yu
2016-10-08 2:46 ` [PATCH v3 17/18] x86/intel_rdt: Add scheduler hook Fenghua Yu
2016-10-08 2:46 ` [PATCH v3 18/18] MAINTAINERS: Add maintainer for Intel RDT resource allocation Fenghua Yu
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