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From: "Luck, Tony" <tony.luck@intel.com>
To: Fenghua Yu <fenghua.yu@intel.com>
Cc: Nilay Vaish <nilayvaish@gmail.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	"H. Peter Anvin" <h.peter.anvin@intel.com>,
	Ingo Molnar <mingo@elte.hu>,
	Peter Zijlstra <peterz@infradead.org>,
	Stephane Eranian <eranian@google.com>,
	Borislav Petkov <bp@suse.de>, Dave Hansen <dave.hansen@intel.com>,
	Shaohua Li <shli@fb.com>,
	David Carrillo-Cisneros <davidcc@google.com>,
	Ravi V Shankar <ravi.v.shankar@intel.com>,
	Sai Prakhya <sai.praneeth.prakhya@intel.com>,
	Vikas Shivappa <vikas.shivappa@linux.intel.com>,
	linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
Subject: Re: [PATCH v3 05/18] Documentation, x86: Documentation for Intel resource allocation user interface
Date: Mon, 10 Oct 2016 10:19:02 -0700	[thread overview]
Message-ID: <20161010171902.GA30774@intel.com> (raw)
In-Reply-To: <20161008203306.GA7672@linux.intel.com>

On Sat, Oct 08, 2016 at 01:33:06PM -0700, Fenghua Yu wrote:
> On Sat, Oct 08, 2016 at 12:12:07PM -0500, Nilay Vaish wrote:
> > On 7 October 2016 at 21:45, Fenghua Yu <fenghua.yu@intel.com> wrote:
> > > From: Fenghua Yu <fenghua.yu@intel.com>
> > >
> > > +L3 details (code and data prioritization disabled)
> > > +--------------------------------------------------
> > > +With CDP disabled the L3 schemata format is:
> > > +
> > > +       L3:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
> > > +
> > > +L3 details (CDP enabled via mount option to resctrl)
> > > +----------------------------------------------------
> > > +When CDP is enabled, you need to specify separate cache bit masks for
> > > +code and data access. The generic format is:
> > > +
> > > +       L3:<cache_id0>=<d_cbm>,<i_cbm>;<cache_id1>=<d_cbm>,<i_cbm>;...
> > 
> > Can we drop L3 here and instead say:
> > L<level>:<cache_id0>=<d_cbm>,<i_cbm>;<cache_id1>=<d_cbm>,<i_cbm>;...
> > 
> > and similarly for without CDP as well.
> 
> L3 and L2 are similar but different. L2 doesn't have CDP feature. It would
> be better to talk them separately here.
> 

Perhaps we should document the general form, and then show examples
for L3 (and later L2 and other resources as they are added). Note
in particular that other resources are not cache-like ... so the
pattern you see between L3 and L2 is short lived. Future resources
that can be controlled are not caches.

General form of a resource line is:

{resource type}:[{resource instanceM}={resource value};]*N

where "M" iterates over all online instances of this resource,
and "N" is the total number. [and the ";" is a separator, not a terminator,
but I'm not sure how to write that].

For the "L3" resource there are two formats for the value.
With CDP enabled:
	{d-cache bit mask},{i-cache bit mask}
with CDP disabled:
	{cache bit mask}

"L2" resource doesn't support CDP, so the only format is {cache bit mask}


The next resource coming will have values that are simple ranges {0 .. max}

-Tony

  reply	other threads:[~2016-10-10 17:20 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-08  2:45 [PATCH v3 00/18] Intel Cache Allocation Technology Fenghua Yu
2016-10-07 23:54 ` [RFC PATCH 19/18] x86/intel_rdt: Add support for L2 cache allocation Luck, Tony
2016-10-08  2:45 ` [PATCH v3 01/18] Documentation, ABI: Add a document entry for cache id Fenghua Yu
2016-10-08 17:11   ` Nilay Vaish
2016-10-10 16:45     ` Luck, Tony
2016-10-11 16:48       ` Nilay Vaish
2016-10-08  2:45 ` [PATCH v3 02/18] cacheinfo: Introduce " Fenghua Yu
2016-10-08 17:10   ` Nilay Vaish
2016-10-08  2:45 ` [PATCH v3 03/18] x86, intel_cacheinfo: Enable cache id in x86 Fenghua Yu
2016-10-08  2:45 ` [PATCH v3 04/18] x86/intel_rdt: Feature discovery Fenghua Yu
2016-10-08 17:11   ` Nilay Vaish
2016-10-08 20:54     ` Fenghua Yu
2016-10-08 19:52       ` Borislav Petkov
2016-10-11 16:57         ` Nilay Vaish
2016-10-11 17:03           ` Borislav Petkov
2016-10-10 16:01     ` Dave Hansen
2016-10-10 16:18       ` Borislav Petkov
2016-10-08  2:45 ` [PATCH v3 05/18] Documentation, x86: Documentation for Intel resource allocation user interface Fenghua Yu
2016-10-08 17:12   ` Nilay Vaish
2016-10-08 20:33     ` Fenghua Yu
2016-10-10 17:19       ` Luck, Tony [this message]
2016-10-11 17:07         ` Nilay Vaish
2016-10-11 18:04           ` Luck, Tony
2016-10-08  2:45 ` [PATCH v3 06/18] x86/intel_rdt: Add CONFIG, Makefile, and basic initialization Fenghua Yu
2016-10-08 20:57   ` Borislav Petkov
2016-10-08  2:45 ` [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery Fenghua Yu
2016-10-09 11:41   ` Borislav Petkov
2016-10-09 17:09     ` Fenghua Yu
2016-10-09 16:28       ` Borislav Petkov
2016-10-10 18:55         ` Luck, Tony
2016-10-11 11:12           ` Borislav Petkov
2016-10-11 14:51             ` Luck, Tony
2016-10-08  2:45 ` [PATCH v3 08/18] x86/intel_rdt: Pick up L3 RDT parameters from CPUID Fenghua Yu
2016-10-08  2:45 ` [PATCH v3 09/18] x86/cqm: Move PQR_ASSOC management code into generic code used by both CQM and CAT Fenghua Yu
2016-10-08  2:45 ` [PATCH v3 10/18] x86/intel_rdt: Build structures for each resource based on cache topology Fenghua Yu
2016-10-09 21:57   ` Nilay Vaish
2016-10-08  2:45 ` [PATCH v3 11/18] x86/intel_rdt: Add basic resctrl filesystem support Fenghua Yu
2016-10-09 22:31   ` Nilay Vaish
2016-10-10 23:44     ` Luck, Tony
2016-10-08  2:45 ` [PATCH v3 12/18] x86/intel_rdt: Add "info" files to resctrl file system Fenghua Yu
2016-10-08  2:45 ` [PATCH v3 13/18] x86/intel_rdt: Add mkdir " Fenghua Yu
2016-10-10 17:51   ` Nilay Vaish
2016-10-08  2:45 ` [PATCH v3 14/18] x86/intel_rdt: Add cpus file Fenghua Yu
2016-10-08  2:46 ` [PATCH v3 15/18] x86/intel_rdt: Add tasks files Fenghua Yu
2016-10-08  2:46 ` [PATCH v3 16/18] x86/intel_rdt: Add schemata file Fenghua Yu
2016-10-08  2:46 ` [PATCH v3 17/18] x86/intel_rdt: Add scheduler hook Fenghua Yu
2016-10-08  2:46 ` [PATCH v3 18/18] MAINTAINERS: Add maintainer for Intel RDT resource allocation Fenghua Yu

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