Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery

From: Fenghua Yu <fenghua.yu@intel.com>
To: Nilay Vaish <nilayvaish@gmail.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	"H. Peter Anvin" <h.peter.anvin@intel.com>,
	Ingo Molnar <mingo@elte.hu>, Tony Luck <tony.luck@intel.com>,
	Peter Zijlstra <peterz@infradead.org>,
	Stephane Eranian <eranian@google.com>,
	Borislav Petkov <bp@suse.de>, Dave Hansen <dave.hansen@intel.com>,
	Shaohua Li <shli@fb.com>,
	David Carrillo-Cisneros <davidcc@google.com>,
	Ravi V Shankar <ravi.v.shankar@intel.com>,
	Sai Prakhya <sai.praneeth.prakhya@intel.com>,
	Vikas Shivappa <vikas.shivappa@linux.intel.com>,
	linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
Subject: Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery
Date: Sat, 8 Oct 2016 13:54:54 -0700	[thread overview]
Message-ID: <20161008205454.GB7672@linux.intel.com> (raw)
In-Reply-To: <CACbG309kJa-6pAB_7K4GaJEPB7Tw0fQxd=_5+oWtZm1kCaAtHA@mail.gmail.com>

On Sat, Oct 08, 2016 at 12:11:22PM -0500, Nilay Vaish wrote:
> On 7 October 2016 at 21:45, Fenghua Yu <fenghua.yu@intel.com> wrote:
> > From: Fenghua Yu <fenghua.yu@intel.com>
> >
> > Check CPUID leaves for all the Resource Director Technology (RDT)
> > Cache Allocation Technology (CAT) bits.
> >
> > Prescence of allocation features:
> 
> Presence
> 
> > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> > index 92a8308..64dd8274 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -196,6 +196,10 @@
> >
> >  #define X86_FEATURE_INTEL_PT   ( 7*32+15) /* Intel Processor Trace */
> >
> > +#define X86_FEATURE_CAT_L3     ( 7*32+16) /* Cache Allocation Technology L3 */
> > +#define X86_FEATURE_CAT_L2     ( 7*32+17) /* Cache Allocation Technology L2 */
> > +#define X86_FEATURE_CDP_L3     ( 7*32+18) /* Code and Data Prioritization L3 */
> > +
> >  /* Virtualization flags: Linux defined, word 8 */
> >  #define X86_FEATURE_TPR_SHADOW  ( 8*32+ 0) /* Intel TPR Shadow */
> >  #define X86_FEATURE_VNMI        ( 8*32+ 1) /* Intel Virtual NMI */
> > @@ -220,6 +224,7 @@
> >  #define X86_FEATURE_RTM                ( 9*32+11) /* Restricted Transactional Memory */
> >  #define X86_FEATURE_CQM                ( 9*32+12) /* Cache QoS Monitoring */
> >  #define X86_FEATURE_MPX                ( 9*32+14) /* Memory Protection Extension */
> > +#define X86_FEATURE_RDT_A      ( 9*32+15) /* Resource Director Technology Allocation */
> >  #define X86_FEATURE_AVX512F    ( 9*32+16) /* AVX-512 Foundation */
> >  #define X86_FEATURE_AVX512DQ   ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */
> >  #define X86_FEATURE_RDSEED     ( 9*32+18) /* The RDSEED instruction */
> 
> I think these #defines are specific to Intel.  I would prefer if we
> have _INTEL_ somewhere in them.

Is adding "Intel" in comment good?

+#define X86_FEATURE_CAT_L3     ( 7*32+16) /* Intel Cache Allocation Technology L3 */
+#define X86_FEATURE_CAT_L2     ( 7*32+17) /* Intel Cache Allocation Technology L2 */
+#define X86_FEATURE_CDP_L3     ( 7*32+18) /* Intel Code and Data Prioritization L3 */

Thanks.

-Fenghua