From: Nilay Vaish <nilayvaish@gmail.com>
To: "Luck, Tony" <tony.luck@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
"H. Peter Anvin" <h.peter.anvin@intel.com>,
Ingo Molnar <mingo@elte.hu>,
Peter Zijlstra <peterz@infradead.org>,
Stephane Eranian <eranian@google.com>,
Borislav Petkov <bp@suse.de>, Dave Hansen <dave.hansen@intel.com>,
Shaohua Li <shli@fb.com>,
David Carrillo-Cisneros <davidcc@google.com>,
Ravi V Shankar <ravi.v.shankar@intel.com>,
Sai Prakhya <sai.praneeth.prakhya@intel.com>,
Vikas Shivappa <vikas.shivappa@linux.intel.com>,
linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
Subject: Re: [PATCH v3 01/18] Documentation, ABI: Add a document entry for cache id
Date: Tue, 11 Oct 2016 11:48:56 -0500 [thread overview]
Message-ID: <CACbG308vJ45kM6G22Rketr+BZRrrCa_1R3gg4XNxiMRWtLC1gg@mail.gmail.com> (raw)
In-Reply-To: <20161010164543.GA30442@intel.com>
On 10 October 2016 at 11:45, Luck, Tony <tony.luck@intel.com> wrote:
> On Sat, Oct 08, 2016 at 12:11:08PM -0500, Nilay Vaish wrote:
>> On 7 October 2016 at 21:45, Fenghua Yu <fenghua.yu@intel.com> wrote:
>> > From: Fenghua Yu <fenghua.yu@intel.com>
>
>> > + caches typically exist per core, but there may not be a
>> > + power of two cores on a socket, so these caches may be
>> > + numbered 0, 1, 2, 3, 4, 5, 8, 9, 10, ...
>> > +
>>
>> While it is ok that the caches are not numbered contiguously, it is
>> unclear how this is related to number of cores on a socket being a
>> power of 2 or not.
>
> That's a side effect of the x86 algorithm to generate the unique ID
> which uses a shift to put the socket number in some upper bits while
> leaving the "id within a socket" in the low bits.
>
> I don't think it worth documenting here, but I noticed that we don't
> keep the IDs within a core contguous either. On my 24 core Broadwell
> they are not 0 ... 23 then a gap from 24 to 31. I actually have on
> socket 0:
>
> 0, 1, 2, 3, 4, 5
> 8, 9, 10, 11, 12, 13
> 16, 17, 18, 19, 20, 21
> 24, 25, 26, 27, 28, 29
>
Thanks for the info.
--
Nilay
next prev parent reply other threads:[~2016-10-11 16:49 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-08 2:45 [PATCH v3 00/18] Intel Cache Allocation Technology Fenghua Yu
2016-10-07 23:54 ` [RFC PATCH 19/18] x86/intel_rdt: Add support for L2 cache allocation Luck, Tony
2016-10-08 2:45 ` [PATCH v3 01/18] Documentation, ABI: Add a document entry for cache id Fenghua Yu
2016-10-08 17:11 ` Nilay Vaish
2016-10-10 16:45 ` Luck, Tony
2016-10-11 16:48 ` Nilay Vaish [this message]
2016-10-08 2:45 ` [PATCH v3 02/18] cacheinfo: Introduce " Fenghua Yu
2016-10-08 17:10 ` Nilay Vaish
2016-10-08 2:45 ` [PATCH v3 03/18] x86, intel_cacheinfo: Enable cache id in x86 Fenghua Yu
2016-10-08 2:45 ` [PATCH v3 04/18] x86/intel_rdt: Feature discovery Fenghua Yu
2016-10-08 17:11 ` Nilay Vaish
2016-10-08 20:54 ` Fenghua Yu
2016-10-08 19:52 ` Borislav Petkov
2016-10-11 16:57 ` Nilay Vaish
2016-10-11 17:03 ` Borislav Petkov
2016-10-10 16:01 ` Dave Hansen
2016-10-10 16:18 ` Borislav Petkov
2016-10-08 2:45 ` [PATCH v3 05/18] Documentation, x86: Documentation for Intel resource allocation user interface Fenghua Yu
2016-10-08 17:12 ` Nilay Vaish
2016-10-08 20:33 ` Fenghua Yu
2016-10-10 17:19 ` Luck, Tony
2016-10-11 17:07 ` Nilay Vaish
2016-10-11 18:04 ` Luck, Tony
2016-10-08 2:45 ` [PATCH v3 06/18] x86/intel_rdt: Add CONFIG, Makefile, and basic initialization Fenghua Yu
2016-10-08 20:57 ` Borislav Petkov
2016-10-08 2:45 ` [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery Fenghua Yu
2016-10-09 11:41 ` Borislav Petkov
2016-10-09 17:09 ` Fenghua Yu
2016-10-09 16:28 ` Borislav Petkov
2016-10-10 18:55 ` Luck, Tony
2016-10-11 11:12 ` Borislav Petkov
2016-10-11 14:51 ` Luck, Tony
2016-10-08 2:45 ` [PATCH v3 08/18] x86/intel_rdt: Pick up L3 RDT parameters from CPUID Fenghua Yu
2016-10-08 2:45 ` [PATCH v3 09/18] x86/cqm: Move PQR_ASSOC management code into generic code used by both CQM and CAT Fenghua Yu
2016-10-08 2:45 ` [PATCH v3 10/18] x86/intel_rdt: Build structures for each resource based on cache topology Fenghua Yu
2016-10-09 21:57 ` Nilay Vaish
2016-10-08 2:45 ` [PATCH v3 11/18] x86/intel_rdt: Add basic resctrl filesystem support Fenghua Yu
2016-10-09 22:31 ` Nilay Vaish
2016-10-10 23:44 ` Luck, Tony
2016-10-08 2:45 ` [PATCH v3 12/18] x86/intel_rdt: Add "info" files to resctrl file system Fenghua Yu
2016-10-08 2:45 ` [PATCH v3 13/18] x86/intel_rdt: Add mkdir " Fenghua Yu
2016-10-10 17:51 ` Nilay Vaish
2016-10-08 2:45 ` [PATCH v3 14/18] x86/intel_rdt: Add cpus file Fenghua Yu
2016-10-08 2:46 ` [PATCH v3 15/18] x86/intel_rdt: Add tasks files Fenghua Yu
2016-10-08 2:46 ` [PATCH v3 16/18] x86/intel_rdt: Add schemata file Fenghua Yu
2016-10-08 2:46 ` [PATCH v3 17/18] x86/intel_rdt: Add scheduler hook Fenghua Yu
2016-10-08 2:46 ` [PATCH v3 18/18] MAINTAINERS: Add maintainer for Intel RDT resource allocation Fenghua Yu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CACbG308vJ45kM6G22Rketr+BZRrrCa_1R3gg4XNxiMRWtLC1gg@mail.gmail.com \
--to=nilayvaish@gmail.com \
--cc=bp@suse.de \
--cc=dave.hansen@intel.com \
--cc=davidcc@google.com \
--cc=eranian@google.com \
--cc=fenghua.yu@intel.com \
--cc=h.peter.anvin@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@elte.hu \
--cc=peterz@infradead.org \
--cc=ravi.v.shankar@intel.com \
--cc=sai.praneeth.prakhya@intel.com \
--cc=shli@fb.com \
--cc=tglx@linutronix.de \
--cc=tony.luck@intel.com \
--cc=vikas.shivappa@linux.intel.com \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).