[PATCH v6 00/14] mmc: Add support to Marvell Xenon SD Host Controller

[PATCH v6 00/14] mmc: Add support to Marvell Xenon SD Host Controller

[Gregory CLEMENT]

Hello,

This the sixth version of the series adding support for the SDHCI
Xenon controller. It can be currently found on the Armada 37xx and the
Armada 7K/8K but will be also used in more Marvell SoC (and not only
the mvebu ones actually).

Most of the following changes had been discussed on the mailing list,
except the new compatible string.

It occurred that the xenon controller was integrated in a different
way in the AP806 and the CP110 which both are part of the Armada 7K/8K
SoCs. For example the Xenon controller in CP110 doesn't not support
HS200.

v5->v6:

- Add a generic "mmc-card" parse in core layer.

- Fix the spelling issues in Xenon dt binding doc and drivers.

- Remove descriptions to common mmc properties from Xenon dt binding
  doc.

- Split compatible string "marvell,armada-8k-sdhci" into
 "marvell,armada-ap806-sdhci" and "marvell,armada-cp110-sdhci".

- Also updates the example in Xenon dt binding doc.

- Remove unnecessary dependency on MMC_SDHCI from Xenon entry in
  Kconfig.

- Move Xenon specific dt parse into a separate function.

- Adjust warnings and condition check in Xenon PHY setting, to remove
 fragile hs200->hs400/hs400->hs200 sequence check function.

- Enable PHY Slow Mode in MMC_TIMING_LEGACY timing if PHY Slow Mode is
 required in dts.

- Add a patch allowing dts backwards compatible for the clock

v4->v5:

- Remove the patch to export sdhci_execute_tuning(). It is already
  exported in v4.10.

- Introduce a patch adding a missing clock for the sdhci controller
  present on the CP master for A7K/A8K. There is no build dependency
  but obviously this patch is need to use the sdhci controller present
  on the CP part.

- Adjust Xenon return setup, to avoid being overwritten by
   sdhci_add_host().

- Change Xenon register definition prefix to "XENON_".

-  Fix typos in Xenon driver and dt-binding docs.

- Change compatible string "marvell,armada-7000-sdhci" to
  "marvell,armada-8k-sdhci". Actually the Armada 7K SoCs are a subset
  of the Armada 8K SoCs. Moreover, the use of the '000' is not
  consistent with all the other compatible string already used for the
  Armada 7K/8K family.

- Added the Tested-by from Russell King on an Armada 8K based board.

v3 -> v4:
For this version a few change have been done:
- fixes 2 bug  reported by kbuild-bot
  - remove extra of_node_put()
  - convert 0 in false for function returning boolean

- add a device tree node for the sdhci controller present on the CP
  master for A7K/A8K. It also led to rename the sdhci0 node on AP to
  ap_sdhci0 to make a distinction with the one present on CP master.

v2 -> v3
I think that now most (if not all) the remarks had been taking into
account since the second version. According to Ziji Hu, here are the
following changes:
" Changes in V3:
  Adjust and improve Xenon DT bindings. Move some caps setting from driver into
  DT. Use mmc-card sub-node to represent eMMC type.
  Remove PHY Sampling Fixed Delay Line scan in lower speed mode.
  Improve Xenon probe and ->init_card() functions.
  Export sdhci_enable_sdio_irq() and implement own SDIO IRQ control.
  Split PHY patch into two smaller patches.
  Temporarily remove AXI clock before its implementation is improved."

Besides this changes I also
- Removed the sdhci-xenon-phy.h and moved its content in the
shc-xenon-phy.c file.
- Fixed the tuning-count usage
- Managed the error case for clk_prepare_enable

For the record the change from v1 was:
" Changes in V2:
  rebase on v4.9-rc2.
  Re-write Xenon bindings. Ajust Xenon DT property naming.
  Add a new DT property to indicate eMMC card type, instead of using
  variable card_candidate.
  Clear quirks SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 in Xenon platform data
  Add support to HS400 retuning."

Thanks,

Gregory

Gregory CLEMENT (4):
  clk: apn806: Turn the eMMC clock as optional for dts backwards compatible
  arm64: dts: marvell: add eMMC support for Armada 37xx
  arm64: dts: marvell: add sdhci support for Armada 7K/8K
  arm64: configs: enable SDHCI driver for Xenon

Hu Ziji (9):
  mmc: core: Add mmc-card dt sub-node parse in core layer
  mmc: sdhci: Export sdhci_set_ios() from sdhci.c
  mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.c
  mmc: sdhci: Export sdhci_enable_sdio_irq() from sdhci.c
  dt: bindings: Add bindings for Marvell Xenon SD Host Controller
  mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality
  mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC
  mmc: sdhci-xenon: Add SoC PHY PAD voltage control
  MAINTAINERS: add entry for Marvell Xenon MMC Host Controller drivers

Konstantin Porotchkin (1):
  clk: apn806: Add eMMC clock to system controller driver

 Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt | 172 +-
 MAINTAINERS                                                   |   7 +-
 arch/arm64/boot/dts/marvell/armada-3720-db.dts                |  16 +-
 arch/arm64/boot/dts/marvell/armada-37xx.dtsi                  |  11 +-
 arch/arm64/boot/dts/marvell/armada-7040-db.dts                |  14 +-
 arch/arm64/boot/dts/marvell/armada-8040-db.dts                |  20 +-
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi                 |  14 +-
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi          |  11 +-
 arch/arm64/configs/defconfig                                  |   1 +-
 drivers/clk/mvebu/ap806-system-controller.c                   |  21 +-
 drivers/mmc/core/mmc.c                                        |  24 +-
 drivers/mmc/host/Kconfig                                      |   9 +-
 drivers/mmc/host/Makefile                                     |   3 +-
 drivers/mmc/host/sdhci-xenon-phy.c                            | 865 +++++++-
 drivers/mmc/host/sdhci-xenon.c                                | 605 +++++-
 drivers/mmc/host/sdhci-xenon.h                                | 109 +-
 drivers/mmc/host/sdhci.c                                      |  11 +-
 drivers/mmc/host/sdhci.h                                      |   4 +-
 include/linux/mmc/core.h                                      |   2 +-
 19 files changed, 1913 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
 create mode 100644 drivers/mmc/host/sdhci-xenon-phy.c
 create mode 100644 drivers/mmc/host/sdhci-xenon.c
 create mode 100644 drivers/mmc/host/sdhci-xenon.h

base-commit: 0c744ea4f77d72b3dcebb7a8f2684633ec79be88
-- 
git-series 0.9.1

[PATCH v6 01/14] clk: apn806: Add eMMC clock to system controller driver

[Gregory CLEMENT]

From: Konstantin Porotchkin <kostap@marvell.com>

Add fixed clock of 400MHz to system controller driver.  This clock is
used as SD/eMMC clock source.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Omri Itach <omrii@marvell.com>
Reviewed-by: Hanna Hawa <hannah@marvell.com>
[fixed up conflicts, added error handling --rmk]
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi |  3 ++-
 drivers/clk/mvebu/ap806-system-controller.c   | 15 ++++++++++++++-
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index a749ba2edec4..5019c8f4acd0 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -235,7 +235,8 @@
 				#clock-cells = <1>;
 				clock-output-names = "ap-cpu-cluster-0",
 						     "ap-cpu-cluster-1",
-						     "ap-fixed", "ap-mss";
+						     "ap-fixed", "ap-mss",
+						     "ap-emmc";
 				reg = <0x6f4000 0x1000>;
 			};
 		};
diff --git a/drivers/clk/mvebu/ap806-system-controller.c b/drivers/clk/mvebu/ap806-system-controller.c
index 8181b919f062..0a785076b0c6 100644
--- a/drivers/clk/mvebu/ap806-system-controller.c
+++ b/drivers/clk/mvebu/ap806-system-controller.c
@@ -23,7 +23,7 @@
 #define AP806_SAR_REG			0x400
 #define AP806_SAR_CLKFREQ_MODE_MASK	0x1f
 
-#define AP806_CLK_NUM			4
+#define AP806_CLK_NUM			5
 
 static struct clk *ap806_clks[AP806_CLK_NUM];
 
@@ -117,6 +117,17 @@ static int ap806_syscon_clk_probe(struct platform_device *pdev)
 		goto fail3;
 	}
 
+	/* eMMC Clock is fixed clock divided by 3 */
+	of_property_read_string_index(np, "clock-output-names",
+				      4, &name);
+	ap806_clks[4] = clk_register_fixed_factor(NULL, name, fixedclk_name,
+						  0, 1, 3);
+	if (IS_ERR(ap806_clks[4])) {
+		ret = PTR_ERR(ap806_clks[4]);
+		goto fail4;
+	}
+
+	of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
 	ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
 	if (ret)
 		goto fail_clk_add;
@@ -124,6 +135,8 @@ static int ap806_syscon_clk_probe(struct platform_device *pdev)
 	return 0;
 
 fail_clk_add:
+	clk_unregister_fixed_factor(ap806_clks[4]);
+fail4:
 	clk_unregister_fixed_factor(ap806_clks[3]);
 fail3:
 	clk_unregister_fixed_rate(ap806_clks[2]);
-- 
git-series 0.9.1

[PATCH v6 02/14] clk: apn806: Turn the eMMC clock as optional for dts backwards compatible

[Gregory CLEMENT]

First version of the binding didn't have the eMMC clock. This patch
allows to not registering the eMMC clock if it is not present in the
device tree. Then the device tree can be backwards compatible.

Suggested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/clk/mvebu/ap806-system-controller.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/mvebu/ap806-system-controller.c b/drivers/clk/mvebu/ap806-system-controller.c
index 0a785076b0c6..a5459abbc314 100644
--- a/drivers/clk/mvebu/ap806-system-controller.c
+++ b/drivers/clk/mvebu/ap806-system-controller.c
@@ -118,13 +118,19 @@ static int ap806_syscon_clk_probe(struct platform_device *pdev)
 	}
 
 	/* eMMC Clock is fixed clock divided by 3 */
-	of_property_read_string_index(np, "clock-output-names",
-				      4, &name);
-	ap806_clks[4] = clk_register_fixed_factor(NULL, name, fixedclk_name,
-						  0, 1, 3);
-	if (IS_ERR(ap806_clks[4])) {
-		ret = PTR_ERR(ap806_clks[4]);
-		goto fail4;
+	if (of_property_read_string_index(np, "clock-output-names",
+					  4, &name)) {
+		ap806_clk_data.clk_num--;
+		dev_warn(&pdev->dev,
+			 "eMMC clock mising: update the device tree!\n");
+	} else {
+		ap806_clks[4] = clk_register_fixed_factor(NULL, name,
+							  fixedclk_name,
+							  0, 1, 3);
+		if (IS_ERR(ap806_clks[4])) {
+			ret = PTR_ERR(ap806_clks[4]);
+			goto fail4;
+		}
 	}
 
 	of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
-- 
git-series 0.9.1

[PATCH v6 03/14] mmc: core: Add mmc-card dt sub-node parse in core layer

[Gregory CLEMENT]

From: Hu Ziji <huziji@marvell.com>

Some vendor host, like Xenon, can support multiple types.
In dts, use mmc-card dt sub-node to indicate eMMC is in use.

Add a generic mmc-card parse function in mmc core layer.
If mmc-card sub-node is detected, set eMMC common caps, such as
MMC_CAP_NONREMOVABLE, MMC_CAP2_NO_SD and MMC_CAP2_NO_SDIO.

Since it is likely that struct mmc_card is not allocated yet when
this mmc-card parse function is called, it will return true if
mmc-card sub-node is detected. Otherwise, return false.
It can help vendor host determine if the card type is eMMC.

Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/mmc/core/mmc.c   | 24 ++++++++++++++++++++++++
 include/linux/mmc/core.h |  2 ++
 2 files changed, 26 insertions(+)

diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index b61b52f9da3d..dc480006a303 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -2111,6 +2111,30 @@ static const struct mmc_bus_ops mmc_ops = {
 };
 
 /*
+ * Parse mmc-card dt sub-node and set eMMC common caps
+ * if mmc-card exists.
+ * If mmc-card is detected, return true.
+ * Otherwise, return false.
+ */
+bool mmc_of_parse_mmc_card(struct mmc_host *host)
+{
+	struct device_node *np;
+	bool ret = false;
+
+	np = mmc_of_find_child_device(host, 0);
+	if (np && of_device_is_compatible(np, "mmc-card")) {
+		/* mmc-card sub-node indicates eMMC card is in use. */
+		host->caps |= MMC_CAP_NONREMOVABLE;
+		host->caps2 |= MMC_CAP2_NO_SDIO | MMC_CAP2_NO_SD;
+		ret = true;
+	}
+
+	of_node_put(np);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(mmc_of_parse_mmc_card);
+
+/*
  * Starting point for MMC card init.
  */
 int mmc_attach_mmc(struct mmc_host *host)
diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h
index e33cc748dcfe..1b27323f3b6e 100644
--- a/include/linux/mmc/core.h
+++ b/include/linux/mmc/core.h
@@ -234,4 +234,6 @@ struct device_node;
 extern u32 mmc_vddrange_to_ocrmask(int vdd_min, int vdd_max);
 extern int mmc_of_parse_voltage(struct device_node *np, u32 *mask);
 
+extern bool mmc_of_parse_mmc_card(struct mmc_host *host);
+
 #endif /* LINUX_MMC_CORE_H */
-- 
git-series 0.9.1

Re: [PATCH v6 03/14] mmc: core: Add mmc-card dt sub-node parse in core layer

[Ulf Hansson]

On 14 February 2017 at 18:01, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:
> From: Hu Ziji <huziji@marvell.com>
>
> Some vendor host, like Xenon, can support multiple types.
> In dts, use mmc-card dt sub-node to indicate eMMC is in use.
>
> Add a generic mmc-card parse function in mmc core layer.
> If mmc-card sub-node is detected, set eMMC common caps, such as
> MMC_CAP_NONREMOVABLE, MMC_CAP2_NO_SD and MMC_CAP2_NO_SDIO.
>
> Since it is likely that struct mmc_card is not allocated yet when
> this mmc-card parse function is called, it will return true if
> mmc-card sub-node is detected. Otherwise, return false.
> It can help vendor host determine if the card type is eMMC.
>
> Signed-off-by: Hu Ziji <huziji@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
>  drivers/mmc/core/mmc.c   | 24 ++++++++++++++++++++++++
>  include/linux/mmc/core.h |  2 ++
>  2 files changed, 26 insertions(+)
>
> diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
> index b61b52f9da3d..dc480006a303 100644
> --- a/drivers/mmc/core/mmc.c
> +++ b/drivers/mmc/core/mmc.c
> @@ -2111,6 +2111,30 @@ static const struct mmc_bus_ops mmc_ops = {
>  };
>
>  /*
> + * Parse mmc-card dt sub-node and set eMMC common caps
> + * if mmc-card exists.
> + * If mmc-card is detected, return true.
> + * Otherwise, return false.
> + */
> +bool mmc_of_parse_mmc_card(struct mmc_host *host)
> +{
> +       struct device_node *np;
> +       bool ret = false;
> +
> +       np = mmc_of_find_child_device(host, 0);

There are already some places in the mmc core where child nodes are
being parsed. You may have a look for mmc_of_find_child_device() and
find the callers of it.

Additionally, we need a generic method of how to describe in DT, when
an mmc host controller has more than one mmc slot. This will also be
done using child nodes.

So, before starting hacking on this, it seems like we need some
consolidation of the code. In principle, I would like to move the APIs
for parsing of the child nodes into host.c, along with existing
mmc_of_parse() function.

> +       if (np && of_device_is_compatible(np, "mmc-card")) {
> +               /* mmc-card sub-node indicates eMMC card is in use. */
> +               host->caps |= MMC_CAP_NONREMOVABLE;
> +               host->caps2 |= MMC_CAP2_NO_SDIO | MMC_CAP2_NO_SD;
> +               ret = true;
> +       }
> +

So instead of providing a new mmc OF parse API, let's make
mmc_of_parse() call another internal function which deals with child
node parsing.

> +       of_node_put(np);
> +       return ret;
> +}
> +EXPORT_SYMBOL_GPL(mmc_of_parse_mmc_card);
> +
> +/*
>   * Starting point for MMC card init.
>   */
>  int mmc_attach_mmc(struct mmc_host *host)
> diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h
> index e33cc748dcfe..1b27323f3b6e 100644
> --- a/include/linux/mmc/core.h
> +++ b/include/linux/mmc/core.h
> @@ -234,4 +234,6 @@ struct device_node;
>  extern u32 mmc_vddrange_to_ocrmask(int vdd_min, int vdd_max);
>  extern int mmc_of_parse_voltage(struct device_node *np, u32 *mask);
>
> +extern bool mmc_of_parse_mmc_card(struct mmc_host *host);
> +
>  #endif /* LINUX_MMC_CORE_H */
> --
> git-series 0.9.1

If you didn't quite understand my comments, then please tell me. Then
I can help out cooking some patches for you.

Kind regards
Uffe

Re: [PATCH v6 03/14] mmc: core: Add mmc-card dt sub-node parse in core layer

[Ziji Hu]

Hi Ulf,

On 2017/3/15 20:43, Ulf Hansson wrote:
> On 14 February 2017 at 18:01, Gregory CLEMENT
> <gregory.clement@free-electrons.com> wrote:
>> From: Hu Ziji <huziji@marvell.com>
>>
>> Some vendor host, like Xenon, can support multiple types.
>> In dts, use mmc-card dt sub-node to indicate eMMC is in use.
>>
>> Add a generic mmc-card parse function in mmc core layer.
>> If mmc-card sub-node is detected, set eMMC common caps, such as
>> MMC_CAP_NONREMOVABLE, MMC_CAP2_NO_SD and MMC_CAP2_NO_SDIO.
>>
>> Since it is likely that struct mmc_card is not allocated yet when
>> this mmc-card parse function is called, it will return true if
>> mmc-card sub-node is detected. Otherwise, return false.
>> It can help vendor host determine if the card type is eMMC.
>>
<snip>
>> +bool mmc_of_parse_mmc_card(struct mmc_host *host)
>> +{
>> +       struct device_node *np;
>> +       bool ret = false;
>> +
>> +       np = mmc_of_find_child_device(host, 0);
> 
> There are already some places in the mmc core where child nodes are
> being parsed. You may have a look for mmc_of_find_child_device() and
> find the callers of it.
> 
> Additionally, we need a generic method of how to describe in DT, when
> an mmc host controller has more than one mmc slot. This will also be
> done using child nodes.
> 

	I'd like to confirm if you require a universal child node
	parsing function to deal with all the child node use cases.
	It might be a little difficult to us.

> So, before starting hacking on this, it seems like we need some
> consolidation of the code. In principle, I would like to move the APIs
> for parsing of the child nodes into host.c, along with existing
> mmc_of_parse() function.
> 

	I guess that your requirement is like:
	int mmc_of_pars(struct mmc_host *host)
	{

		...

		np = mmc_of_find_child_device(host, 0);
		if (np && of_device_is_compatible(np, "mmc-card")) {
			...
		}

		...

	}
	Am I correct?

	Actually, I previously tried this implementation.
	But I found that it is difficult to return eMMC card type information
	to our vendor driver. Our Xenon driver expects to know if the device
	is eMMC card through this parse.

>> +       if (np && of_device_is_compatible(np, "mmc-card")) {
>> +               /* mmc-card sub-node indicates eMMC card is in use. */
>> +               host->caps |= MMC_CAP_NONREMOVABLE;
>> +               host->caps2 |= MMC_CAP2_NO_SDIO | MMC_CAP2_NO_SD;
>> +               ret = true;
>> +       }
>> +
> 
> So instead of providing a new mmc OF parse API, let's make
> mmc_of_parse() call another internal function which deals with child
> node parsing.
> 
>> +       of_node_put(np);
>> +       return ret;
>> +}
>> +EXPORT_SYMBOL_GPL(mmc_of_parse_mmc_card);
>> +
>> +/*
>>   * Starting point for MMC card init.
>>   */
>>  int mmc_attach_mmc(struct mmc_host *host)
>> diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h
>> index e33cc748dcfe..1b27323f3b6e 100644
>> --- a/include/linux/mmc/core.h
>> +++ b/include/linux/mmc/core.h
>> @@ -234,4 +234,6 @@ struct device_node;
>>  extern u32 mmc_vddrange_to_ocrmask(int vdd_min, int vdd_max);
>>  extern int mmc_of_parse_voltage(struct device_node *np, u32 *mask);
>>
>> +extern bool mmc_of_parse_mmc_card(struct mmc_host *host);
>> +
>>  #endif /* LINUX_MMC_CORE_H */
>> --
>> git-series 0.9.1
> 
> If you didn't quite understand my comments, then please tell me. Then
> I can help out cooking some patches for you.

	Thanks a lot. Actually I'm not sure if our implementation to detect
	eMMC card type can meet your requirement of child node parsing.
	Please help provide me some examples or patches.

	Thank you.

Best regards,
Hu Ziji

> 
> Kind regards
> Uffe
> 

Re: [PATCH v6 03/14] mmc: core: Add mmc-card dt sub-node parse in core layer

[Gregory CLEMENT]

Hi Ulf,
 
 On mer., mars 15 2017, Ulf Hansson <ulf.hansson@linaro.org> wrote:

> On 14 February 2017 at 18:01, Gregory CLEMENT
> <gregory.clement@free-electrons.com> wrote:
>> From: Hu Ziji <huziji@marvell.com>
>>
>> Some vendor host, like Xenon, can support multiple types.
>> In dts, use mmc-card dt sub-node to indicate eMMC is in use.
>>
>> Add a generic mmc-card parse function in mmc core layer.
>> If mmc-card sub-node is detected, set eMMC common caps, such as
>> MMC_CAP_NONREMOVABLE, MMC_CAP2_NO_SD and MMC_CAP2_NO_SDIO.
>>
>> Since it is likely that struct mmc_card is not allocated yet when
>> this mmc-card parse function is called, it will return true if
>> mmc-card sub-node is detected. Otherwise, return false.
>> It can help vendor host determine if the card type is eMMC.
>>
>> Signed-off-by: Hu Ziji <huziji@marvell.com>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
>> ---
>>  drivers/mmc/core/mmc.c   | 24 ++++++++++++++++++++++++
>>  include/linux/mmc/core.h |  2 ++
>>  2 files changed, 26 insertions(+)
>>
>> diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
>> index b61b52f9da3d..dc480006a303 100644
>> --- a/drivers/mmc/core/mmc.c
>> +++ b/drivers/mmc/core/mmc.c
>> @@ -2111,6 +2111,30 @@ static const struct mmc_bus_ops mmc_ops = {
>>  };
>>
>>  /*
>> + * Parse mmc-card dt sub-node and set eMMC common caps
>> + * if mmc-card exists.
>> + * If mmc-card is detected, return true.
>> + * Otherwise, return false.
>> + */
>> +bool mmc_of_parse_mmc_card(struct mmc_host *host)
>> +{
>> +       struct device_node *np;
>> +       bool ret = false;
>> +
>> +       np = mmc_of_find_child_device(host, 0);
>
> There are already some places in the mmc core where child nodes are
> being parsed. You may have a look for mmc_of_find_child_device() and
> find the callers of it.

mmc_of_find_child_device is called in 3 places:

 - in mmc_add_card() from drivers/mmc/core/bus.c to populate the of_node
   field of card->dev. Here we don't care of the mmc-card property

 - in mmc_decode_ext_csd() from drivers/mmc/core/mmc.c, here the purpose
   is exactly to check if the mmc-card property is present so we could
   replace it by mmc_of_parse_mmc_card().

 - in sdio_set_of_node from drivers/mmc/core/sdio_bus.c to populate the
   of_node field of func->dev. Here again, we don't care of the mmc-card
   property

So in one case we could use the same function but for the 2 other cases
continue to use mmc_of_find_child_device() alone make sens.

>
> Additionally, we need a generic method of how to describe in DT, when
> an mmc host controller has more than one mmc slot. This will also be
> done using child nodes.
>
> So, before starting hacking on this, it seems like we need some
> consolidation of the code. In principle, I would like to move the APIs
> for parsing of the child nodes into host.c, along with existing
> mmc_of_parse() function.

I understand that you want consolidate this subsystem but it seems
beyond the this series. I would not want that the merge of this driver
will be delayed more because of it. We submitted the first version 5
month ago now, made several changes and we will reach the 7th
version. Along these version we also already contribute to improve the
mmc subsystem. I agree to work on the change you want, but I would like
not depending of it to merge this series.

We will address all the other comment on v6 from you and Andrian for a
v7. And for this patch we can:

 - keep it as is and only modify the mmc_decode_ext_csd() to use
   mmc_of_find_child_device().

 - Moving it back inside our driver waiting for a better API in the mmc
   subsystem.

What would be your preference?

>
>> +       if (np && of_device_is_compatible(np, "mmc-card")) {
>> +               /* mmc-card sub-node indicates eMMC card is in use. */
>> +               host->caps |= MMC_CAP_NONREMOVABLE;
>> +               host->caps2 |= MMC_CAP2_NO_SDIO | MMC_CAP2_NO_SD;
>> +               ret = true;
>> +       }
>> +
>
> So instead of providing a new mmc OF parse API, let's make
> mmc_of_parse() call another internal function which deals with child
> node parsing.

As the driver need to know if the card is an emmc then we need to alos
expose this information in one of the mmc structure, waht about "struct
mmc_host"?

Thanks,

Gregory


>
>> +       of_node_put(np);
>> +       return ret;
>> +}
>> +EXPORT_SYMBOL_GPL(mmc_of_parse_mmc_card);
>> +
>> +/*
>>   * Starting point for MMC card init.
>>   */
>>  int mmc_attach_mmc(struct mmc_host *host)
>> diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h
>> index e33cc748dcfe..1b27323f3b6e 100644
>> --- a/include/linux/mmc/core.h
>> +++ b/include/linux/mmc/core.h
>> @@ -234,4 +234,6 @@ struct device_node;
>>  extern u32 mmc_vddrange_to_ocrmask(int vdd_min, int vdd_max);
>>  extern int mmc_of_parse_voltage(struct device_node *np, u32 *mask);
>>
>> +extern bool mmc_of_parse_mmc_card(struct mmc_host *host);
>> +
>>  #endif /* LINUX_MMC_CORE_H */
>> --
>> git-series 0.9.1
>
> If you didn't quite understand my comments, then please tell me. Then
> I can help out cooking some patches for you.
>
> Kind regards
> Uffe

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v6 04/14] mmc: sdhci: Export sdhci_set_ios() from sdhci.c

[Gregory CLEMENT]

From: Hu Ziji <huziji@marvell.com>

Export sdhci_set_ios() in sdhci.c.
Thus vendor sdhci driver can implement its own set_ios() routine.

Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/mmc/host/sdhci.c | 3 ++-
 drivers/mmc/host/sdhci.h | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 23909804ffb8..0e9ed0fadff9 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1570,7 +1570,7 @@ void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
 }
 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
 
-static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 {
 	struct sdhci_host *host = mmc_priv(mmc);
 	unsigned long flags;
@@ -1730,6 +1730,7 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 	mmiowb();
 	spin_unlock_irqrestore(&host->lock, flags);
 }
+EXPORT_SYMBOL_GPL(sdhci_set_ios);
 
 static int sdhci_get_cd(struct mmc_host *mmc)
 {
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 0b66f210ae82..3563c0c384ca 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -691,6 +691,7 @@ void sdhci_set_bus_width(struct sdhci_host *host, int width);
 void sdhci_reset(struct sdhci_host *host, u8 mask);
 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
+void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 
 #ifdef CONFIG_PM
 extern int sdhci_suspend_host(struct sdhci_host *host);
-- 
git-series 0.9.1

Re: [PATCH v6 04/14] mmc: sdhci: Export sdhci_set_ios() from sdhci.c

[Adrian Hunter]

On 14/02/17 19:01, Gregory CLEMENT wrote:
> From: Hu Ziji <huziji@marvell.com>
> 
> Export sdhci_set_ios() in sdhci.c.
> Thus vendor sdhci driver can implement its own set_ios() routine.
> 
> Signed-off-by: Hu Ziji <huziji@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci.c | 3 ++-
>  drivers/mmc/host/sdhci.h | 1 +
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 23909804ffb8..0e9ed0fadff9 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1570,7 +1570,7 @@ void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
>  }
>  EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
>  
> -static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
> +void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>  {
>  	struct sdhci_host *host = mmc_priv(mmc);
>  	unsigned long flags;
> @@ -1730,6 +1730,7 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>  	mmiowb();
>  	spin_unlock_irqrestore(&host->lock, flags);
>  }
> +EXPORT_SYMBOL_GPL(sdhci_set_ios);
>  
>  static int sdhci_get_cd(struct mmc_host *mmc)
>  {
> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
> index 0b66f210ae82..3563c0c384ca 100644
> --- a/drivers/mmc/host/sdhci.h
> +++ b/drivers/mmc/host/sdhci.h
> @@ -691,6 +691,7 @@ void sdhci_set_bus_width(struct sdhci_host *host, int width);
>  void sdhci_reset(struct sdhci_host *host, u8 mask);
>  void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
>  int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
> +void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
>  
>  #ifdef CONFIG_PM
>  extern int sdhci_suspend_host(struct sdhci_host *host);
> 

[PATCH v6 05/14] mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.c

[Gregory CLEMENT]

From: Hu Ziji <huziji@marvell.com>

Export sdhci_start_signal_voltage_switch() from sdhci.c.
Thus vendor sdhci driver can implement its own signal voltage
switch routine.

Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/mmc/host/sdhci.c | 5 +++--
 drivers/mmc/host/sdhci.h | 2 ++
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 0e9ed0fadff9..d2338dc362f4 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1839,8 +1839,8 @@ static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
 	spin_unlock_irqrestore(&host->lock, flags);
 }
 
-static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
-					     struct mmc_ios *ios)
+int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+				      struct mmc_ios *ios)
 {
 	struct sdhci_host *host = mmc_priv(mmc);
 	u16 ctrl;
@@ -1932,6 +1932,7 @@ static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
 		return 0;
 	}
 }
+EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
 
 static int sdhci_card_busy(struct mmc_host *mmc)
 {
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 3563c0c384ca..e4a07543a12b 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -692,6 +692,8 @@ void sdhci_reset(struct sdhci_host *host, u8 mask);
 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
+int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+				      struct mmc_ios *ios);
 
 #ifdef CONFIG_PM
 extern int sdhci_suspend_host(struct sdhci_host *host);
-- 
git-series 0.9.1

Re: [PATCH v6 05/14] mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.c

[Adrian Hunter]

On 14/02/17 19:01, Gregory CLEMENT wrote:
> From: Hu Ziji <huziji@marvell.com>
> 
> Export sdhci_start_signal_voltage_switch() from sdhci.c.
> Thus vendor sdhci driver can implement its own signal voltage
> switch routine.
> 
> Signed-off-by: Hu Ziji <huziji@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci.c | 5 +++--
>  drivers/mmc/host/sdhci.h | 2 ++
>  2 files changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 0e9ed0fadff9..d2338dc362f4 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1839,8 +1839,8 @@ static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
>  	spin_unlock_irqrestore(&host->lock, flags);
>  }
>  
> -static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
> -					     struct mmc_ios *ios)
> +int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
> +				      struct mmc_ios *ios)
>  {
>  	struct sdhci_host *host = mmc_priv(mmc);
>  	u16 ctrl;
> @@ -1932,6 +1932,7 @@ static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
>  		return 0;
>  	}
>  }
> +EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
>  
>  static int sdhci_card_busy(struct mmc_host *mmc)
>  {
> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
> index 3563c0c384ca..e4a07543a12b 100644
> --- a/drivers/mmc/host/sdhci.h
> +++ b/drivers/mmc/host/sdhci.h
> @@ -692,6 +692,8 @@ void sdhci_reset(struct sdhci_host *host, u8 mask);
>  void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
>  int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
>  void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
> +int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
> +				      struct mmc_ios *ios);
>  
>  #ifdef CONFIG_PM
>  extern int sdhci_suspend_host(struct sdhci_host *host);
> 

[PATCH v6 06/14] mmc: sdhci: Export sdhci_enable_sdio_irq() from sdhci.c

[Gregory CLEMENT]

From: Hu Ziji <huziji@marvell.com>

Export sdhci_enable_sdio_irq() from sdhci.c.
Thus vendor SDHC driver can implement its specific SDIO irq
control.

Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/mmc/host/sdhci.c | 3 ++-
 drivers/mmc/host/sdhci.h | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index d2338dc362f4..9a4fda81ff81 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1824,7 +1824,7 @@ static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
 	}
 }
 
-static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
 {
 	struct sdhci_host *host = mmc_priv(mmc);
 	unsigned long flags;
@@ -1838,6 +1838,7 @@ static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
 	sdhci_enable_sdio_irq_nolock(host, enable);
 	spin_unlock_irqrestore(&host->lock, flags);
 }
+EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
 
 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
 				      struct mmc_ios *ios)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index e4a07543a12b..609783364941 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -694,6 +694,7 @@ int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
 				      struct mmc_ios *ios);
+void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
 
 #ifdef CONFIG_PM
 extern int sdhci_suspend_host(struct sdhci_host *host);
-- 
git-series 0.9.1

Re: [PATCH v6 06/14] mmc: sdhci: Export sdhci_enable_sdio_irq() from sdhci.c

[Adrian Hunter]

On 14/02/17 19:01, Gregory CLEMENT wrote:
> From: Hu Ziji <huziji@marvell.com>
> 
> Export sdhci_enable_sdio_irq() from sdhci.c.
> Thus vendor SDHC driver can implement its specific SDIO irq
> control.
> 
> Signed-off-by: Hu Ziji <huziji@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci.c | 3 ++-
>  drivers/mmc/host/sdhci.h | 1 +
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index d2338dc362f4..9a4fda81ff81 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1824,7 +1824,7 @@ static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
>  	}
>  }
>  
> -static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
> +void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
>  {
>  	struct sdhci_host *host = mmc_priv(mmc);
>  	unsigned long flags;
> @@ -1838,6 +1838,7 @@ static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
>  	sdhci_enable_sdio_irq_nolock(host, enable);
>  	spin_unlock_irqrestore(&host->lock, flags);
>  }
> +EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
>  
>  int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
>  				      struct mmc_ios *ios)
> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
> index e4a07543a12b..609783364941 100644
> --- a/drivers/mmc/host/sdhci.h
> +++ b/drivers/mmc/host/sdhci.h
> @@ -694,6 +694,7 @@ int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
>  void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
>  int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
>  				      struct mmc_ios *ios);
> +void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
>  
>  #ifdef CONFIG_PM
>  extern int sdhci_suspend_host(struct sdhci_host *host);
> 

[PATCH v6 07/14] dt: bindings: Add bindings for Marvell Xenon SD Host Controller

[Gregory CLEMENT]

From: Hu Ziji <huziji@marvell.com>

Marvell Xenon SDHC can support eMMC/SD/SDIO.
Add Xenon-specific properties.
Also add properties for Xenon PHY setting.

Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt | 172 +++++++-
 1 file changed, 172 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt

diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
new file mode 100644
index 000000000000..eabee8b64db6
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
@@ -0,0 +1,172 @@
+Marvell Xenon SDHCI Controller device tree bindings
+This file documents differences between the core mmc properties
+described by mmc.txt and the properties used by the Xenon implementation.
+
+Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
+Each SDHC is independent and owns independent resources, such as register sets,
+clock and PHY.
+Each SDHC should have an independent device tree node.
+
+Required Properties:
+- compatible: should be one of the following
+  - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
+  Must provide a second register area and marvell,pad-type.
+  - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
+  - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
+
+- clocks:
+  Array of clocks required for SDHC.
+  Require at least input clock for Xenon IP core.
+
+- clock-names:
+  Array of names corresponding to clocks property.
+  The input clock for Xenon IP core should be named as "core".
+
+- reg:
+  * For "marvell,armada-3700-sdhci", two register areas.
+    The first one for Xenon IP register. The second one for the Armada 3700 SoC
+    PHY PAD Voltage Control register.
+    Please follow the examples with compatible "marvell,armada-3700-sdhci"
+    in below.
+    Please also check property marvell,pad-type in below.
+
+  * For other compatible strings, one register area for Xenon IP.
+
+Optional Properties:
+- marvell,xenon-sdhc-id:
+  Indicate the corresponding bit index of current SDHC in
+  SDHC System Operation Control Register Bit[7:0].
+  Set/clear the corresponding bit to enable/disable current SDHC.
+  If Xenon IP contains only one SDHC, this property is optional.
+
+- marvell,xenon-phy-type:
+  Xenon support multiple types of PHYs.
+  To select eMMC 5.1 PHY, set:
+  marvell,xenon-phy-type = "emmc 5.1 phy"
+  eMMC 5.1 PHY is the default choice if this property is not provided.
+  To select eMMC 5.0 PHY, set:
+  marvell,xenon-phy-type = "emmc 5.0 phy"
+
+  All those types of PHYs can support eMMC, SD and SDIO.
+  Please note that this property only presents the type of PHY.
+  It doesn't stand for the entire SDHC type or property.
+  For example, "emmc 5.1 phy" doesn't mean that this Xenon SDHC only
+  supports eMMC 5.1.
+
+- marvell,xenon-phy-znr:
+  Set PHY ZNR value.
+  Only available for eMMC PHY.
+  Valid range = [0:0x1F].
+  ZNR is set as 0xF by default if this property is not provided.
+
+- marvell,xenon-phy-zpr:
+  Set PHY ZPR value.
+  Only available for eMMC PHY.
+  Valid range = [0:0x1F].
+  ZPR is set as 0xF by default if this property is not provided.
+
+- marvell,xenon-phy-nr-success-tun:
+  Set the number of required consecutive successful sampling points
+  used to identify a valid sampling window, in tuning process.
+  Valid range = [1:7].
+  Set as 0x4 by default if this property is not provided.
+
+- marvell,xenon-phy-tun-step-divider:
+  Set the divider for calculating TUN_STEP.
+  Set as 64 by default if this property is not provided.
+
+- marvell,xenon-phy-slow-mode:
+  If this property is selected, transfers will bypass PHY.
+  Only available when bus frequency lower than 55MHz in SDR mode.
+  Disabled by default. Please only try this property if timing issues
+  always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,
+  SD Default Speed and HS mode and eMMC legacy speed mode.
+
+- marvell,xenon-tun-count:
+  Xenon SDHC SoC usually doesn't provide re-tuning counter in
+  Capabilities Register 3 Bit[11:8].
+  This property provides the re-tuning counter.
+  If this property is not set, default re-tuning counter will
+  be set as 0x9 in driver.
+
+- marvell,pad-type:
+  Type of Armada 3700 SoC PHY PAD Voltage Controller register.
+  Only valid when "marvell,armada-3700-sdhci" is selected.
+  Two types: "sd" and "fixed-1-8v".
+  If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning and is
+  switched to 1.8V when later in higher speed mode.
+  If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for eMMC.
+  Please follow the examples with compatible "marvell,armada-3700-sdhci"
+  in below.
+
+Example:
+- For eMMC:
+
+	sdhci@aa0000 {
+		compatible = "marvell,armada-ap806-sdhci";
+		reg = <0xaa0000 0x1000>;
+		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
+		clocks = <&emmc_clk>;
+		clock-names = "core";
+		bus-width = <4>;
+		marvell,xenon-phy-slow-mode;
+		marvell,xenon-tun-count = <11>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+		apm_mmccard: mmccard@0 {
+			compatible = "mmc-card";
+			reg = <0>;
+		};
+	};
+
+- For SD/SDIO:
+
+	sdhci@ab0000 {
+		compatible = "marvell,armada-cp110-sdhci";
+		reg = <0xab0000 0x1000>;
+		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
+		vqmmc-supply = <&sd_regulator>;
+		clocks = <&sdclk>;
+		clock-names = "core";
+		bus-width = <4>;
+		marvell,xenon-tun-count = <9>;
+	};
+
+- For eMMC with compatible "marvell,armada-3700-sdhci":
+
+	sdhci@aa0000 {
+		compatible = "marvell,armada-3700-sdhci";
+		reg = <0xaa0000 0x1000>,
+		      <phy_addr 0x4>;
+		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
+		clocks = <&emmcclk>;
+		clock-names = "core";
+		bus-width = <8>;
+		mmc-ddr-1_8v;
+		mmc-hs400-1_8v;
+
+		marvell,pad-type = "fixed-1-8v";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+		mmccard: mmccard@0 {
+			compatible = "mmc-card";
+			reg = <0>;
+		};
+	};
+
+- For SD/SDIO with compatible "marvell,armada-3700-sdhci":
+
+	sdhci@ab0000 {
+		compatible = "marvell,armada-3700-sdhci";
+		reg = <0xab0000 0x1000>,
+		      <phy_addr 0x4>;
+		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
+		vqmmc-supply = <&sd_regulator>;
+		clocks = <&sdclk>;
+		clock-names = "core";
+		bus-width = <4>;
+
+		marvell,pad-type = "sd";
+	};
-- 
git-series 0.9.1

Re: [PATCH v6 07/14] dt: bindings: Add bindings for Marvell Xenon SD Host Controller

[Rob Herring]

On Tue, Feb 14, 2017 at 06:01:47PM +0100, Gregory CLEMENT wrote:
> From: Hu Ziji <huziji@marvell.com>
> 
> Marvell Xenon SDHC can support eMMC/SD/SDIO.
> Add Xenon-specific properties.
> Also add properties for Xenon PHY setting.
> 
> Signed-off-by: Hu Ziji <huziji@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
>  Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt | 172 +++++++-
>  1 file changed, 172 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v6 07/14] dt: bindings: Add bindings for Marvell Xenon SD Host Controller

[Ulf Hansson]

[...]

> +
> +Example:
> +- For eMMC:
> +
> +       sdhci@aa0000 {
> +               compatible = "marvell,armada-ap806-sdhci";
> +               reg = <0xaa0000 0x1000>;
> +               interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
> +               clocks = <&emmc_clk>;
> +               clock-names = "core";
> +               bus-width = <4>;
> +               marvell,xenon-phy-slow-mode;
> +               marvell,xenon-tun-count = <11>;

There's no vmmc-supply here.

How do you control power to the eMMC card?

> +
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               apm_mmccard: mmccard@0 {
> +                       compatible = "mmc-card";
> +                       reg = <0>;
> +               };
> +       };
> +
> +- For SD/SDIO:
> +
> +       sdhci@ab0000 {
> +               compatible = "marvell,armada-cp110-sdhci";
> +               reg = <0xab0000 0x1000>;
> +               interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
> +               vqmmc-supply = <&sd_regulator>;

I guess you know vqmmc is for the I/O voltage.

Again, how do you power the SD/SDIO card? No vmmc?

> +               clocks = <&sdclk>;
> +               clock-names = "core";
> +               bus-width = <4>;
> +               marvell,xenon-tun-count = <9>;
> +       };
> +
> +- For eMMC with compatible "marvell,armada-3700-sdhci":
> +
> +       sdhci@aa0000 {
> +               compatible = "marvell,armada-3700-sdhci";
> +               reg = <0xaa0000 0x1000>,
> +                     <phy_addr 0x4>;
> +               interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
> +               clocks = <&emmcclk>;
> +               clock-names = "core";
> +               bus-width = <8>;
> +               mmc-ddr-1_8v;
> +               mmc-hs400-1_8v;

Again, no vmmc?

> +
> +               marvell,pad-type = "fixed-1-8v";
> +
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               mmccard: mmccard@0 {
> +                       compatible = "mmc-card";
> +                       reg = <0>;
> +               };
> +       };
> +
> +- For SD/SDIO with compatible "marvell,armada-3700-sdhci":
> +
> +       sdhci@ab0000 {
> +               compatible = "marvell,armada-3700-sdhci";
> +               reg = <0xab0000 0x1000>,
> +                     <phy_addr 0x4>;
> +               interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
> +               vqmmc-supply = <&sd_regulator>;

Again, no vmmc?

> +               clocks = <&sdclk>;
> +               clock-names = "core";
> +               bus-width = <4>;
> +
> +               marvell,pad-type = "sd";
> +       };
> --
> git-series 0.9.1


Kind regards
Uffe

Re: [EXT] Re: [PATCH v6 07/14] dt: bindings: Add bindings for Marvell Xenon SD Host Controller

[Ziji Hu]

Hi Ulf,

On 2017/3/15 20:48, Ulf Hansson wrote:
> [...]
> 
>> +
>> +Example:
>> +- For eMMC:
>> +
>> +       sdhci@aa0000 {
>> +               compatible = "marvell,armada-ap806-sdhci";
>> +               reg = <0xaa0000 0x1000>;
>> +               interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
>> +               clocks = <&emmc_clk>;
>> +               clock-names = "core";
>> +               bus-width = <4>;
>> +               marvell,xenon-phy-slow-mode;
>> +               marvell,xenon-tun-count = <11>;
> 
> There's no vmmc-supply here.
> 
> How do you control power to the eMMC card?
> 

	Sorry for the delayed reply.
	Just confirmed with the engineers.

	It seems that there is a regulator.
	I will ask for a complete node example.

>> +
>> +               #address-cells = <1>;
>> +               #size-cells = <0>;
>> +               apm_mmccard: mmccard@0 {
>> +                       compatible = "mmc-card";
>> +                       reg = <0>;
>> +               };
>> +       };
>> +
>> +- For SD/SDIO:
>> +
>> +       sdhci@ab0000 {
>> +               compatible = "marvell,armada-cp110-sdhci";
>> +               reg = <0xab0000 0x1000>;
>> +               interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
>> +               vqmmc-supply = <&sd_regulator>;
> 
> I guess you know vqmmc is for the I/O voltage.
> 
> Again, how do you power the SD/SDIO card? No vmmc?

	The vmmc-supply regulator does exist according to the engineer.
	I will ask them to provide a complete one.

> 
>> +               clocks = <&sdclk>;
>> +               clock-names = "core";
>> +               bus-width = <4>;
>> +               marvell,xenon-tun-count = <9>;
>> +       };
>> +
>> +- For eMMC with compatible "marvell,armada-3700-sdhci":
>> +
>> +       sdhci@aa0000 {
>> +               compatible = "marvell,armada-3700-sdhci";
>> +               reg = <0xaa0000 0x1000>,
>> +                     <phy_addr 0x4>;
>> +               interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
>> +               clocks = <&emmcclk>;
>> +               clock-names = "core";
>> +               bus-width = <8>;
>> +               mmc-ddr-1_8v;
>> +               mmc-hs400-1_8v;
> 
> Again, no vmmc?
> 

	The engineer told me the power to eMMC card is fixed on this platform.
	They don't implement a specific regulator for eMMC core power.

>> +
>> +               marvell,pad-type = "fixed-1-8v";
>> +
>> +               #address-cells = <1>;
>> +               #size-cells = <0>;
>> +               mmccard: mmccard@0 {
>> +                       compatible = "mmc-card";
>> +                       reg = <0>;
>> +               };
>> +       };
>> +
>> +- For SD/SDIO with compatible "marvell,armada-3700-sdhci":
>> +
>> +       sdhci@ab0000 {
>> +               compatible = "marvell,armada-3700-sdhci";
>> +               reg = <0xab0000 0x1000>,
>> +                     <phy_addr 0x4>;
>> +               interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
>> +               vqmmc-supply = <&sd_regulator>;
> 
> Again, no vmmc?
> 
	
	It seems that the core power to SD is also fixed.

>> +               clocks = <&sdclk>;
>> +               clock-names = "core";
>> +               bus-width = <4>;
>> +
>> +               marvell,pad-type = "sd";
>> +       };
>> --
>> git-series 0.9.1
> 
> 
> Kind regards
> Uffe
> 

[PATCH v6 08/14] mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality

[Gregory CLEMENT]

From: Hu Ziji <huziji@marvell.com>

Add Xenon eMMC/SD/SDIO host controller core functionality.
Add Xenon specific initialization process.
Add Xenon specific mmc_host_ops APIs.
Add Xenon specific register definitions.

Add CONFIG_MMC_SDHCI_XENON support in drivers/mmc/host/Kconfig.

Marvell Xenon SDHC conforms to SD Physical Layer Specification
Version 3.01 and is designed according to the guidelines provided
in the SD Host Controller Standard Specification Version 3.00.

Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/mmc/host/Kconfig       |   9 +-
 drivers/mmc/host/Makefile      |   3 +-
 drivers/mmc/host/sdhci-xenon.c | 602 ++++++++++++++++++++++++++++++++++-
 drivers/mmc/host/sdhci-xenon.h |  70 ++++-
 4 files changed, 684 insertions(+)
 create mode 100644 drivers/mmc/host/sdhci-xenon.c
 create mode 100644 drivers/mmc/host/sdhci-xenon.h

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 2eb97014dc3f..1c1a88bfbdad 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -819,3 +819,12 @@ config MMC_SDHCI_BRCMSTB
 	  Broadcom STB SoCs.
 
 	  If unsure, say Y.
+
+config MMC_SDHCI_XENON
+	tristate "Marvell Xenon eMMC/SD/SDIO SDHCI driver"
+	depends on MMC_SDHCI_PLTFM
+	help
+	  This selects Marvell Xenon eMMC/SD/SDIO SDHCI.
+	  If you have a machine with integrated Marvell Xenon SDHC IP,
+	  say Y or M here.
+	  If unsure, say N.
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index ccc9c4cba154..b0a2ab4b256e 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -82,3 +82,6 @@ obj-$(CONFIG_MMC_SDHCI_BRCMSTB)		+= sdhci-brcmstb.o
 ifeq ($(CONFIG_CB710_DEBUG),y)
 	CFLAGS-cb710-mmc	+= -DDEBUG
 endif
+
+obj-$(CONFIG_MMC_SDHCI_XENON)	+= sdhci-xenon-driver.o
+sdhci-xenon-driver-y		+= sdhci-xenon.o
diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
new file mode 100644
index 000000000000..e633f803907a
--- /dev/null
+++ b/drivers/mmc/host/sdhci-xenon.c
@@ -0,0 +1,602 @@
+/*
+ * Driver for Marvell Xenon SDHC as a platform device
+ *
+ * Copyright (C) 2016 Marvell, All Rights Reserved.
+ *
+ * Author:	Hu Ziji <huziji@marvell.com>
+ * Date:	2016-8-24
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * Inspired by Jisheng Zhang <jszhang@marvell.com>
+ * Special thanks to Video BG4 project team.
+ */
+
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/of.h>
+
+#include "sdhci-pltfm.h"
+#include "sdhci-xenon.h"
+
+static int enable_xenon_internal_clk(struct sdhci_host *host)
+{
+	u32 reg;
+	u8 timeout;
+
+	reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
+	reg |= SDHCI_CLOCK_INT_EN;
+	sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL);
+	/* Wait max 20 ms */
+	timeout = 20;
+	while (!((reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
+			& SDHCI_CLOCK_INT_STABLE)) {
+		if (timeout == 0) {
+			pr_err("%s: Internal clock never stabilised.\n",
+			       mmc_hostname(host->mmc));
+			return -ETIMEDOUT;
+		}
+		timeout--;
+		mdelay(1);
+	}
+
+	return 0;
+}
+
+/* Set SDCLK-off-while-idle */
+static void xenon_set_sdclk_off_idle(struct sdhci_host *host,
+				     unsigned char sdhc_id, bool enable)
+{
+	u32 reg;
+	u32 mask;
+
+	reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
+	/* Get the bit shift basing on the SDHC index */
+	mask = (0x1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sdhc_id));
+	if (enable)
+		reg |= mask;
+	else
+		reg &= ~mask;
+
+	sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
+}
+
+/* Enable/Disable the Auto Clock Gating function */
+static void xenon_set_acg(struct sdhci_host *host, bool enable)
+{
+	u32 reg;
+
+	reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
+	if (enable)
+		reg &= ~XENON_AUTO_CLKGATE_DISABLE_MASK;
+	else
+		reg |= XENON_AUTO_CLKGATE_DISABLE_MASK;
+	sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
+}
+
+/* Enable this SDHC */
+static void xenon_enable_sdhc(struct sdhci_host *host,
+			      unsigned char sdhc_id)
+{
+	u32 reg;
+
+	reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
+	reg |= (BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
+	sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
+
+	/*
+	 * Manually set the flag which all the card types require,
+	 * including SD, eMMC, SDIO
+	 */
+	host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
+}
+
+/* Disable this SDHC */
+static void xenon_disable_sdhc(struct sdhci_host *host,
+			       unsigned char sdhc_id)
+{
+	u32 reg;
+
+	reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
+	reg &= ~(BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
+	sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
+}
+
+/* Enable Parallel Transfer Mode */
+static void xenon_enable_sdhc_parallel_tran(struct sdhci_host *host,
+					    unsigned char sdhc_id)
+{
+	u32 reg;
+
+	reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
+	reg |= BIT(sdhc_id);
+	sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
+}
+
+/* Mask command conflict error */
+static void xenon_mask_cmd_conflict_err(struct sdhci_host *host)
+{
+	u32  reg;
+
+	reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
+	reg |= XENON_MASK_CMD_CONFLICT_ERR;
+	sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
+}
+
+static void xenon_sdhc_retune_setup(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	u32 reg;
+
+	/* Disable the Re-Tuning Request functionality */
+	reg = sdhci_readl(host, XENON_SLOT_RETUNING_REQ_CTRL);
+	reg &= ~XENON_RETUNING_COMPATIBLE;
+	sdhci_writel(host, reg, XENON_SLOT_RETUNING_REQ_CTRL);
+
+	/* Disable the Re-tuning Interrupt */
+	reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
+	reg &= ~SDHCI_INT_RETUNE;
+	sdhci_writel(host, reg, SDHCI_SIGNAL_ENABLE);
+	reg = sdhci_readl(host, SDHCI_INT_ENABLE);
+	reg &= ~SDHCI_INT_RETUNE;
+	sdhci_writel(host, reg, SDHCI_INT_ENABLE);
+
+	/* Force to use Tuning Mode 1 */
+	host->tuning_mode = SDHCI_TUNING_MODE_1;
+	/* Set re-tuning period */
+	host->tuning_count = 1 << (priv->tuning_count - 1);
+}
+
+/*
+ * Operations inside struct sdhci_ops
+ */
+/* Recover the Register Setting cleared during SOFTWARE_RESET_ALL */
+static void sdhci_xenon_reset_exit(struct sdhci_host *host,
+				   unsigned char sdhc_id, u8 mask)
+{
+	/* Only SOFTWARE RESET ALL will clear the register setting */
+	if (!(mask & SDHCI_RESET_ALL))
+		return;
+
+	/* Disable tuning request and auto-retuning again */
+	xenon_sdhc_retune_setup(host);
+
+	xenon_set_acg(host, true);
+
+	xenon_set_sdclk_off_idle(host, sdhc_id, false);
+
+	xenon_mask_cmd_conflict_err(host);
+}
+
+static void sdhci_xenon_reset(struct sdhci_host *host, u8 mask)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+
+	sdhci_reset(host, mask);
+	sdhci_xenon_reset_exit(host, priv->sdhc_id, mask);
+}
+
+/*
+ * Xenon defines different values for HS200 and HS400
+ * in Host_Control_2
+ */
+static void xenon_set_uhs_signaling(struct sdhci_host *host,
+				    unsigned int timing)
+{
+	u16 ctrl_2;
+
+	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+	/* Select Bus Speed Mode for host */
+	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+	if (timing == MMC_TIMING_MMC_HS200)
+		ctrl_2 |= XENON_CTRL_HS200;
+	else if (timing == MMC_TIMING_UHS_SDR104)
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
+	else if (timing == MMC_TIMING_UHS_SDR12)
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
+	else if (timing == MMC_TIMING_UHS_SDR25)
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
+	else if (timing == MMC_TIMING_UHS_SDR50)
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
+	else if ((timing == MMC_TIMING_UHS_DDR50) ||
+		 (timing == MMC_TIMING_MMC_DDR52))
+		ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
+	else if (timing == MMC_TIMING_MMC_HS400)
+		ctrl_2 |= XENON_CTRL_HS400;
+	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+}
+
+static const struct sdhci_ops sdhci_xenon_ops = {
+	.set_clock		= sdhci_set_clock,
+	.set_bus_width		= sdhci_set_bus_width,
+	.reset			= sdhci_xenon_reset,
+	.set_uhs_signaling	= xenon_set_uhs_signaling,
+	.get_max_clock		= sdhci_pltfm_clk_get_max_clock,
+};
+
+static const struct sdhci_pltfm_data sdhci_xenon_pdata = {
+	.ops = &sdhci_xenon_ops,
+	.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
+		  SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
+		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
+};
+
+/*
+ * Xenon Specific Operations in mmc_host_ops
+ */
+static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	unsigned long flags;
+	u32 reg;
+
+	/*
+	 * HS400/HS200/eMMC HS doesn't have Preset Value register.
+	 * However, sdhci_set_ios will read HS400/HS200 Preset register.
+	 * Disable Preset Value register for HS400/HS200.
+	 * eMMC HS with preset_enabled set will trigger a bug in
+	 * get_preset_value().
+	 */
+	spin_lock_irqsave(&host->lock, flags);
+	if ((ios->timing == MMC_TIMING_MMC_HS400) ||
+	    (ios->timing == MMC_TIMING_MMC_HS200) ||
+	    (ios->timing == MMC_TIMING_MMC_HS)) {
+		host->preset_enabled = false;
+		host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
+		host->flags &= ~SDHCI_PV_ENABLED;
+
+		reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+		reg &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
+		sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
+	} else {
+		host->quirks2 &= ~SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
+	}
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	sdhci_set_ios(mmc, ios);
+
+	if (host->clock > XENON_DEFAULT_SDCLK_FREQ) {
+		spin_lock_irqsave(&host->lock, flags);
+		xenon_set_sdclk_off_idle(host, priv->sdhc_id, true);
+		spin_unlock_irqrestore(&host->lock, flags);
+	}
+}
+
+static int xenon_emmc_signal_voltage_switch(struct mmc_host *mmc,
+					    struct mmc_ios *ios)
+{
+	unsigned char voltage = ios->signal_voltage;
+	struct sdhci_host *host = mmc_priv(mmc);
+	unsigned char voltage_code;
+	u32 ctrl;
+
+	if ((voltage == MMC_SIGNAL_VOLTAGE_330) ||
+	    (voltage == MMC_SIGNAL_VOLTAGE_180)) {
+		if (voltage == MMC_SIGNAL_VOLTAGE_330)
+			voltage_code = XENON_EMMC_VCCQ_3_3V;
+		else if (voltage == MMC_SIGNAL_VOLTAGE_180)
+			voltage_code = XENON_EMMC_VCCQ_1_8V;
+
+		/*
+		 * This host is for eMMC, XENON self-defined
+		 * eMMC control register should be accessed
+		 * instead of Host Control 2
+		 */
+		ctrl = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
+		ctrl &= ~XENON_EMMC_VCCQ_MASK;
+		ctrl |= voltage_code;
+		sdhci_writel(host, ctrl, XENON_SLOT_EMMC_CTRL);
+
+		/* There is no standard to determine this waiting period */
+		usleep_range(1000, 2000);
+
+		/* Check whether io voltage switch is done */
+		ctrl = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
+		ctrl &= XENON_EMMC_VCCQ_MASK;
+		/*
+		 * This bit is set only when regulator feeds back
+		 * the voltage switch results to Xenon SDHC.
+		 * However, in actaul implementation, regulator might not
+		 * provide this feedback.
+		 * Thus we shall not rely on this bit to determine
+		 * if switch failed.
+		 * If the bit is not set, just throw a message.
+		 * Besides, error code should not be returned.
+		 */
+		if (ctrl != voltage_code)
+			dev_info(mmc_dev(mmc), "fail to detect eMMC signal voltage stable\n");
+		return 0;
+	}
+
+	dev_err(mmc_dev(mmc), "Unsupported signal voltage: %d\n", voltage);
+	return -EINVAL;
+}
+
+static int xenon_start_signal_voltage_switch(struct mmc_host *mmc,
+					     struct mmc_ios *ios)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+
+	/*
+	 * Before SD/SDIO set signal voltage, SD bus clock should be
+	 * disabled. However, sdhci_set_clock will also disable the Internal
+	 * clock in mmc_set_signal_voltage().
+	 * If Internal clock is disabled, the 3.3V/1.8V bit can not be updated.
+	 * Thus here manually enable internal clock.
+	 *
+	 * After switch completes, it is unnecessary to disable internal clock,
+	 * since keeping internal clock active obeys SD spec.
+	 */
+	enable_xenon_internal_clk(host);
+
+	if (priv->init_card_type == MMC_TYPE_MMC)
+		return xenon_emmc_signal_voltage_switch(mmc, ios);
+
+	return sdhci_start_signal_voltage_switch(mmc, ios);
+}
+
+/*
+ * Update card type.
+ * priv->init_card_type will be used in PHY timing adjustment.
+ */
+static void xenon_init_card(struct mmc_host *mmc, struct mmc_card *card)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+
+	/* Update card type*/
+	priv->init_card_type = card->type;
+}
+
+static int xenon_execute_tuning(struct mmc_host *mmc, u32 opcode)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+
+	if (host->timing == MMC_TIMING_UHS_DDR50)
+		return 0;
+
+	/*
+	 * Currently force Xenon driver back to support mode 1 only,
+	 * even though Xenon might claim to support mode 2 or mode 3.
+	 * It requires more time to test mode 2/mode 3 on more platforms.
+	 */
+	if (host->tuning_mode != SDHCI_TUNING_MODE_1)
+		xenon_sdhc_retune_setup(host);
+
+	return sdhci_execute_tuning(mmc, opcode);
+}
+
+static void xenon_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	u32 reg;
+	u8 sdhc_id = priv->sdhc_id;
+
+	sdhci_enable_sdio_irq(mmc, enable);
+
+	if (enable) {
+		/*
+		 * Set SDIO Card Inserted indication
+		 * to enable detecting SDIO async irq.
+		 */
+		reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
+		reg |= (1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
+		sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
+	} else {
+		/* Clear SDIO Card Inserted indication */
+		reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
+		reg &= ~(1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
+		sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
+	}
+}
+
+static void xenon_replace_mmc_host_ops(struct sdhci_host *host)
+{
+	host->mmc_host_ops.set_ios = xenon_set_ios;
+	host->mmc_host_ops.start_signal_voltage_switch =
+			xenon_start_signal_voltage_switch;
+	host->mmc_host_ops.init_card = xenon_init_card;
+	host->mmc_host_ops.execute_tuning = xenon_execute_tuning;
+	host->mmc_host_ops.enable_sdio_irq = xenon_enable_sdio_irq;
+}
+
+/*
+ * Parse Xenon specific DT properties:
+ * init_card_type: check whether this SDHC is for eMMC
+ * sdhc-id: the index of current SDHC.
+ *	    Refer to XENON_SYS_CFG_INFO register
+ * tun-count: the interval between re-tuning
+ */
+static int xenon_probe_dt(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct sdhci_host *host = platform_get_drvdata(pdev);
+	struct mmc_host *mmc = host->mmc;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	u32 sdhc_id, nr_sdhc;
+	u32 tuning_count;
+
+	/* Disable HS200 on Armada AP806 */
+	if (of_device_is_compatible(np, "marvell,armada-ap806-sdhci"))
+		host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
+
+	priv->init_card_type = XENON_CARD_TYPE_UNKNOWN;
+	/* Check if mmc-card sub-node exists */
+	if (mmc_of_parse_mmc_card(mmc)) {
+		priv->init_card_type = MMC_TYPE_MMC;
+		/*
+		 * Force to clear BUS_TEST to
+		 * skip bus_test_pre and bus_test_post
+		 */
+		mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST;
+	}
+
+	priv->sdhc_id = 0x0;
+	if (!of_property_read_u32(np, "marvell,xenon-sdhc-id", &sdhc_id)) {
+		nr_sdhc = sdhci_readl(host, XENON_SYS_CFG_INFO);
+		nr_sdhc &= XENON_NR_SUPPORTED_SLOT_MASK;
+		if (unlikely(sdhc_id > nr_sdhc)) {
+			dev_err(mmc_dev(mmc), "SDHC Index %d exceeds Number of SDHCs %d\n",
+				sdhc_id, nr_sdhc);
+			return -EINVAL;
+		}
+	}
+
+	tuning_count = XENON_DEF_TUNING_COUNT;
+	if (!of_property_read_u32(np, "marvell,xenon-tun-count",
+				  &tuning_count)) {
+		if (unlikely(tuning_count >= XENON_TMR_RETUN_NO_PRESENT)) {
+			dev_err(mmc_dev(mmc), "Wrong Re-tuning Count. Set default value %d\n",
+				XENON_DEF_TUNING_COUNT);
+			tuning_count = XENON_DEF_TUNING_COUNT;
+		}
+	}
+	priv->tuning_count = tuning_count;
+
+	return 0;
+}
+
+static int xenon_sdhc_probe(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	u8 sdhc_id = priv->sdhc_id;
+
+	/* Enable SDHC */
+	xenon_enable_sdhc(host, sdhc_id);
+
+	/* Enable ACG */
+	xenon_set_acg(host, true);
+
+	/* Enable Parallel Transfer Mode */
+	xenon_enable_sdhc_parallel_tran(host, sdhc_id);
+
+	xenon_mask_cmd_conflict_err(host);
+
+	return 0;
+}
+
+static void xenon_sdhc_remove(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	u8 sdhc_id = priv->sdhc_id;
+
+	/* disable SDHC */
+	xenon_disable_sdhc(host, sdhc_id);
+}
+
+static int sdhci_xenon_probe(struct platform_device *pdev)
+{
+	struct sdhci_pltfm_host *pltfm_host;
+	struct sdhci_host *host;
+	struct sdhci_xenon_priv *priv;
+	int err;
+
+	host = sdhci_pltfm_init(pdev, &sdhci_xenon_pdata,
+				sizeof(struct sdhci_xenon_priv));
+	if (IS_ERR(host))
+		return PTR_ERR(host);
+
+	pltfm_host = sdhci_priv(host);
+	priv = sdhci_pltfm_priv(pltfm_host);
+
+	xenon_set_acg(host, false);
+
+	/*
+	 * Link Xenon specific mmc_host_ops function,
+	 * to replace standard ones in sdhci_ops.
+	 */
+	xenon_replace_mmc_host_ops(host);
+
+	pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
+	if (IS_ERR(pltfm_host->clk)) {
+		err = PTR_ERR(pltfm_host->clk);
+		dev_err(&pdev->dev, "Failed to setup input clk: %d\n", err);
+		goto free_pltfm;
+	}
+	err = clk_prepare_enable(pltfm_host->clk);
+	if (err)
+		goto free_pltfm;
+
+	err = mmc_of_parse(host->mmc);
+	if (err)
+		goto err_clk;
+
+	sdhci_get_of_property(pdev);
+
+	/* Xenon specific dt parse */
+	err = xenon_probe_dt(pdev);
+	if (err)
+		goto err_clk;
+
+	err = xenon_sdhc_probe(host);
+	if (err)
+		goto err_clk;
+
+	err = sdhci_add_host(host);
+	if (err)
+		goto remove_sdhc;
+
+	return 0;
+
+remove_sdhc:
+	xenon_sdhc_remove(host);
+err_clk:
+	clk_disable_unprepare(pltfm_host->clk);
+free_pltfm:
+	sdhci_pltfm_free(pdev);
+	return err;
+}
+
+static int sdhci_xenon_remove(struct platform_device *pdev)
+{
+	struct sdhci_host *host = platform_get_drvdata(pdev);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+
+	xenon_sdhc_remove(host);
+
+	sdhci_remove_host(host, 0);
+
+	clk_disable_unprepare(pltfm_host->clk);
+
+	sdhci_pltfm_free(pdev);
+
+	return 0;
+}
+
+static const struct of_device_id sdhci_xenon_dt_ids[] = {
+	{ .compatible = "marvell,armada-ap806-sdhci",},
+	{ .compatible = "marvell,armada-cp110-sdhci",},
+	{ .compatible = "marvell,armada-3700-sdhci",},
+	{}
+};
+MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids);
+
+static struct platform_driver sdhci_xenon_driver = {
+	.driver	= {
+		.name	= "xenon-sdhci",
+		.of_match_table = sdhci_xenon_dt_ids,
+		.pm = &sdhci_pltfm_pmops,
+	},
+	.probe	= sdhci_xenon_probe,
+	.remove	= sdhci_xenon_remove,
+};
+
+module_platform_driver(sdhci_xenon_driver);
+
+MODULE_DESCRIPTION("SDHCI platform driver for Marvell Xenon SDHC");
+MODULE_AUTHOR("Hu Ziji <huziji@marvell.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h
new file mode 100644
index 000000000000..69de711db9eb
--- /dev/null
+++ b/drivers/mmc/host/sdhci-xenon.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2016 Marvell, All Rights Reserved.
+ *
+ * Author:	Hu Ziji <huziji@marvell.com>
+ * Date:	2016-8-24
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ */
+#ifndef SDHCI_XENON_H_
+#define SDHCI_XENON_H_
+
+/* Register Offset of Xenon SDHC self-defined register */
+#define XENON_SYS_CFG_INFO			0x0104
+#define XENON_SLOT_TYPE_SDIO_SHIFT		24
+#define XENON_NR_SUPPORTED_SLOT_MASK		0x7
+
+#define XENON_SYS_OP_CTRL			0x0108
+#define XENON_AUTO_CLKGATE_DISABLE_MASK		BIT(20)
+#define XENON_SDCLK_IDLEOFF_ENABLE_SHIFT	8
+#define XENON_SLOT_ENABLE_SHIFT			0
+
+#define XENON_SYS_EXT_OP_CTRL			0x010C
+#define XENON_MASK_CMD_CONFLICT_ERR		BIT(8)
+
+#define XENON_SLOT_EMMC_CTRL			0x0130
+#define XENON_EMMC_VCCQ_MASK			0x3
+#define XENON_EMMC_VCCQ_1_8V			0x1
+#define XENON_EMMC_VCCQ_3_3V			0x3
+
+#define XENON_SLOT_RETUNING_REQ_CTRL		0x0144
+/* retuning compatible */
+#define XENON_RETUNING_COMPATIBLE		0x1
+
+/* Tuning Parameter */
+#define XENON_TMR_RETUN_NO_PRESENT		0xF
+#define XENON_DEF_TUNING_COUNT			0x9
+
+#define XENON_DEFAULT_SDCLK_FREQ		400000
+
+/* Xenon specific Mode Select value */
+#define XENON_CTRL_HS200			0x5
+#define XENON_CTRL_HS400			0x6
+
+/* Indicate Card Type is not clear yet */
+#define XENON_CARD_TYPE_UNKNOWN			0xF
+
+struct sdhci_xenon_priv {
+	unsigned char	tuning_count;
+	/* idx of SDHC */
+	u8		sdhc_id;
+
+	/*
+	 * eMMC/SD/SDIO require different PHY settings or
+	 * voltage control. It's necessary for Xenon driver to
+	 * recognize card type during, or even before initialization.
+	 * However, mmc_host->card is not available yet at that time.
+	 * This field records the card type during init.
+	 * For eMMC, it is updated in dt parse. For SD/SDIO, it is
+	 * updated in xenon_init_card().
+	 *
+	 * It is only valid during initialization after it is updated.
+	 * Do not access this variable in normal transfers after
+	 * initialization completes.
+	 */
+	unsigned int	init_card_type;
+};
+
+#endif
-- 
git-series 0.9.1

Re: [PATCH v6 08/14] mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality

[Ulf Hansson]

On 14 February 2017 at 18:01, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:
> From: Hu Ziji <huziji@marvell.com>
>
> Add Xenon eMMC/SD/SDIO host controller core functionality.
> Add Xenon specific initialization process.
> Add Xenon specific mmc_host_ops APIs.
> Add Xenon specific register definitions.
>
> Add CONFIG_MMC_SDHCI_XENON support in drivers/mmc/host/Kconfig.
>
> Marvell Xenon SDHC conforms to SD Physical Layer Specification
> Version 3.01 and is designed according to the guidelines provided
> in the SD Host Controller Standard Specification Version 3.00.
>
> Signed-off-by: Hu Ziji <huziji@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
>  drivers/mmc/host/Kconfig       |   9 +-
>  drivers/mmc/host/Makefile      |   3 +-
>  drivers/mmc/host/sdhci-xenon.c | 602 ++++++++++++++++++++++++++++++++++-
>  drivers/mmc/host/sdhci-xenon.h |  70 ++++-
>  4 files changed, 684 insertions(+)
>  create mode 100644 drivers/mmc/host/sdhci-xenon.c
>  create mode 100644 drivers/mmc/host/sdhci-xenon.h
>
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 2eb97014dc3f..1c1a88bfbdad 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -819,3 +819,12 @@ config MMC_SDHCI_BRCMSTB
>           Broadcom STB SoCs.
>
>           If unsure, say Y.
> +
> +config MMC_SDHCI_XENON
> +       tristate "Marvell Xenon eMMC/SD/SDIO SDHCI driver"
> +       depends on MMC_SDHCI_PLTFM
> +       help
> +         This selects Marvell Xenon eMMC/SD/SDIO SDHCI.
> +         If you have a machine with integrated Marvell Xenon SDHC IP,

/s/SDHC/SDHCI

> +         say Y or M here.
> +         If unsure, say N.
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index ccc9c4cba154..b0a2ab4b256e 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -82,3 +82,6 @@ obj-$(CONFIG_MMC_SDHCI_BRCMSTB)               += sdhci-brcmstb.o
>  ifeq ($(CONFIG_CB710_DEBUG),y)
>         CFLAGS-cb710-mmc        += -DDEBUG
>  endif
> +
> +obj-$(CONFIG_MMC_SDHCI_XENON)  += sdhci-xenon-driver.o
> +sdhci-xenon-driver-y           += sdhci-xenon.o

Why not only this:
obj-$(CONFIG_MMC_SDHCI_XENON) += sdhci-xenon.o

> diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
> new file mode 100644
> index 000000000000..e633f803907a
> --- /dev/null
> +++ b/drivers/mmc/host/sdhci-xenon.c
> @@ -0,0 +1,602 @@
> +/*
> + * Driver for Marvell Xenon SDHC as a platform device
> + *
> + * Copyright (C) 2016 Marvell, All Rights Reserved.
> + *
> + * Author:     Hu Ziji <huziji@marvell.com>
> + * Date:       2016-8-24
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * Inspired by Jisheng Zhang <jszhang@marvell.com>
> + * Special thanks to Video BG4 project team.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +
> +#include "sdhci-pltfm.h"
> +#include "sdhci-xenon.h"
> +
> +static int enable_xenon_internal_clk(struct sdhci_host *host)

[...]

> +/* Set SDCLK-off-while-idle */
> +static void xenon_set_sdclk_off_idle(struct sdhci_host *host,
> +                                    unsigned char sdhc_id, bool enable)

[...]

> +/* Recover the Register Setting cleared during SOFTWARE_RESET_ALL */
> +static void sdhci_xenon_reset_exit(struct sdhci_host *host,
> +                                  unsigned char sdhc_id, u8 mask)

[...]

ff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h
> new file mode 100644
> index 000000000000..69de711db9eb
> --- /dev/null
> +++ b/drivers/mmc/host/sdhci-xenon.h

You should probably put all this in the c-file instead. That is how
most other sdhci variants does it.

[...]

Overall this looks good to me, however I think Adrian needs to have a
quick look as well.

One additional very minor nitpick. Perhaps you can align on the
function names prefix, as those currently varies between "whatever",
"xenon_" and "sdhci_xenon_".

Kind regards
Uffe

Re: [PATCH v6 08/14] mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality

[Ziji Hu]

Hi Ulf,

On 2017/3/15 21:11, Ulf Hansson wrote:
> On 14 February 2017 at 18:01, Gregory CLEMENT
> <gregory.clement@free-electrons.com> wrote:
>> From: Hu Ziji <huziji@marvell.com>
<snip>
>> +config MMC_SDHCI_XENON
>> +       tristate "Marvell Xenon eMMC/SD/SDIO SDHCI driver"
>> +       depends on MMC_SDHCI_PLTFM
>> +       help
>> +         This selects Marvell Xenon eMMC/SD/SDIO SDHCI.
>> +         If you have a machine with integrated Marvell Xenon SDHC IP,
> 
> /s/SDHC/SDHCI
> 

	Sorry. I don't get your point.
	Could you please give more detailed comments?

>> +         say Y or M here.
>> +         If unsure, say N.
>> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
>> index ccc9c4cba154..b0a2ab4b256e 100644
>> --- a/drivers/mmc/host/Makefile
>> +++ b/drivers/mmc/host/Makefile
>> @@ -82,3 +82,6 @@ obj-$(CONFIG_MMC_SDHCI_BRCMSTB)               += sdhci-brcmstb.o
>>  ifeq ($(CONFIG_CB710_DEBUG),y)
>>         CFLAGS-cb710-mmc        += -DDEBUG
>>  endif
>> +
>> +obj-$(CONFIG_MMC_SDHCI_XENON)  += sdhci-xenon-driver.o
>> +sdhci-xenon-driver-y           += sdhci-xenon.o
> 
> Why not only this:
> obj-$(CONFIG_MMC_SDHCI_XENON) += sdhci-xenon.o
> 

	Yes. Will try.

>> diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
>> new file mode 100644
<snip>
> 
> ff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h
>> new file mode 100644
>> index 000000000000..69de711db9eb
>> --- /dev/null
>> +++ b/drivers/mmc/host/sdhci-xenon.h
> 
> You should probably put all this in the c-file instead. That is how
> most other sdhci variants does it.
> 

	Unfortunately, we have some registers like XENON_SLOT_EMMC_CTRL
	which are accessed by both sdhci-xenon.c and sdhci-xenon-phy.c

> [...]
> 
> Overall this looks good to me, however I think Adrian needs to have a
> quick look as well.
> 
> One additional very minor nitpick. Perhaps you can align on the
> function names prefix, as those currently varies between "whatever",
> "xenon_" and "sdhci_xenon_".
> 
	Sure. Will fix them as you request.

	Thank you.

Best regards,
Hu Ziji

> Kind regards
> Uffe
> 

Re: [PATCH v6 08/14] mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality

[Jisheng Zhang]

Hi Ziji

On Wed, 15 Mar 2017 21:58:43 +0800 Ziji Hu wrote:

> Hi Ulf,
> 
> On 2017/3/15 21:11, Ulf Hansson wrote:
> > On 14 February 2017 at 18:01, Gregory CLEMENT
> > <gregory.clement@free-electrons.com> wrote:  
> >> From: Hu Ziji <huziji@marvell.com>  
> <snip>
> >> +config MMC_SDHCI_XENON
> >> +       tristate "Marvell Xenon eMMC/SD/SDIO SDHCI driver"
> >> +       depends on MMC_SDHCI_PLTFM
> >> +       help
> >> +         This selects Marvell Xenon eMMC/SD/SDIO SDHCI.
> >> +         If you have a machine with integrated Marvell Xenon SDHC IP,  
> > 
> > /s/SDHC/SDHCI
> >   
> 
> 	Sorry. I don't get your point.
> 	Could you please give more detailed comments?

Ulf want you to s/SDHC/SDHCI in the line "If you have .....", I.E
change the line to:
If you have a machine with integrated Marvell Xenon SDHCI IP,

Thanks,
Jisheng

Re: [PATCH v6 08/14] mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality

[Adrian Hunter]

On 14/02/17 19:01, Gregory CLEMENT wrote:
> From: Hu Ziji <huziji@marvell.com>
> 
> Add Xenon eMMC/SD/SDIO host controller core functionality.
> Add Xenon specific initialization process.
> Add Xenon specific mmc_host_ops APIs.
> Add Xenon specific register definitions.
> 
> Add CONFIG_MMC_SDHCI_XENON support in drivers/mmc/host/Kconfig.
> 
> Marvell Xenon SDHC conforms to SD Physical Layer Specification
> Version 3.01 and is designed according to the guidelines provided
> in the SD Host Controller Standard Specification Version 3.00.
> 
> Signed-off-by: Hu Ziji <huziji@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

A few minor comments below.

> ---
>  drivers/mmc/host/Kconfig       |   9 +-
>  drivers/mmc/host/Makefile      |   3 +-
>  drivers/mmc/host/sdhci-xenon.c | 602 ++++++++++++++++++++++++++++++++++-
>  drivers/mmc/host/sdhci-xenon.h |  70 ++++-
>  4 files changed, 684 insertions(+)
>  create mode 100644 drivers/mmc/host/sdhci-xenon.c
>  create mode 100644 drivers/mmc/host/sdhci-xenon.h
> 
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 2eb97014dc3f..1c1a88bfbdad 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -819,3 +819,12 @@ config MMC_SDHCI_BRCMSTB
>  	  Broadcom STB SoCs.
>  
>  	  If unsure, say Y.
> +
> +config MMC_SDHCI_XENON
> +	tristate "Marvell Xenon eMMC/SD/SDIO SDHCI driver"
> +	depends on MMC_SDHCI_PLTFM
> +	help
> +	  This selects Marvell Xenon eMMC/SD/SDIO SDHCI.
> +	  If you have a machine with integrated Marvell Xenon SDHC IP,
> +	  say Y or M here.
> +	  If unsure, say N.
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index ccc9c4cba154..b0a2ab4b256e 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -82,3 +82,6 @@ obj-$(CONFIG_MMC_SDHCI_BRCMSTB)		+= sdhci-brcmstb.o
>  ifeq ($(CONFIG_CB710_DEBUG),y)
>  	CFLAGS-cb710-mmc	+= -DDEBUG
>  endif
> +
> +obj-$(CONFIG_MMC_SDHCI_XENON)	+= sdhci-xenon-driver.o
> +sdhci-xenon-driver-y		+= sdhci-xenon.o
> diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
> new file mode 100644
> index 000000000000..e633f803907a
> --- /dev/null
> +++ b/drivers/mmc/host/sdhci-xenon.c
> @@ -0,0 +1,602 @@
> +/*
> + * Driver for Marvell Xenon SDHC as a platform device
> + *
> + * Copyright (C) 2016 Marvell, All Rights Reserved.
> + *
> + * Author:	Hu Ziji <huziji@marvell.com>
> + * Date:	2016-8-24
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * Inspired by Jisheng Zhang <jszhang@marvell.com>
> + * Special thanks to Video BG4 project team.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +
> +#include "sdhci-pltfm.h"
> +#include "sdhci-xenon.h"
> +
> +static int enable_xenon_internal_clk(struct sdhci_host *host)
> +{
> +	u32 reg;
> +	u8 timeout;
> +
> +	reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
> +	reg |= SDHCI_CLOCK_INT_EN;
> +	sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL);
> +	/* Wait max 20 ms */
> +	timeout = 20;
> +	while (!((reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
> +			& SDHCI_CLOCK_INT_STABLE)) {
> +		if (timeout == 0) {
> +			pr_err("%s: Internal clock never stabilised.\n",
> +			       mmc_hostname(host->mmc));
> +			return -ETIMEDOUT;
> +		}
> +		timeout--;
> +		mdelay(1);

If it takes a lot less than 1 ms this can waste time.  See recent patch
"mmc: sdhci: Optimize delay loops"

> +	}
> +
> +	return 0;
> +}
> +
> +/* Set SDCLK-off-while-idle */
> +static void xenon_set_sdclk_off_idle(struct sdhci_host *host,
> +				     unsigned char sdhc_id, bool enable)
> +{
> +	u32 reg;
> +	u32 mask;
> +
> +	reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
> +	/* Get the bit shift basing on the SDHC index */
> +	mask = (0x1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sdhc_id));
> +	if (enable)
> +		reg |= mask;
> +	else
> +		reg &= ~mask;
> +
> +	sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
> +}
> +
> +/* Enable/Disable the Auto Clock Gating function */
> +static void xenon_set_acg(struct sdhci_host *host, bool enable)
> +{
> +	u32 reg;
> +
> +	reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
> +	if (enable)
> +		reg &= ~XENON_AUTO_CLKGATE_DISABLE_MASK;
> +	else
> +		reg |= XENON_AUTO_CLKGATE_DISABLE_MASK;
> +	sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
> +}
> +
> +/* Enable this SDHC */
> +static void xenon_enable_sdhc(struct sdhci_host *host,
> +			      unsigned char sdhc_id)
> +{
> +	u32 reg;
> +
> +	reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
> +	reg |= (BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
> +	sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
> +
> +	/*
> +	 * Manually set the flag which all the card types require,
> +	 * including SD, eMMC, SDIO
> +	 */
> +	host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
> +}
> +
> +/* Disable this SDHC */
> +static void xenon_disable_sdhc(struct sdhci_host *host,
> +			       unsigned char sdhc_id)
> +{
> +	u32 reg;
> +
> +	reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
> +	reg &= ~(BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
> +	sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
> +}
> +
> +/* Enable Parallel Transfer Mode */
> +static void xenon_enable_sdhc_parallel_tran(struct sdhci_host *host,
> +					    unsigned char sdhc_id)
> +{
> +	u32 reg;
> +
> +	reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
> +	reg |= BIT(sdhc_id);
> +	sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
> +}
> +
> +/* Mask command conflict error */
> +static void xenon_mask_cmd_conflict_err(struct sdhci_host *host)
> +{
> +	u32  reg;
> +
> +	reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
> +	reg |= XENON_MASK_CMD_CONFLICT_ERR;
> +	sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
> +}
> +
> +static void xenon_sdhc_retune_setup(struct sdhci_host *host)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	u32 reg;
> +
> +	/* Disable the Re-Tuning Request functionality */
> +	reg = sdhci_readl(host, XENON_SLOT_RETUNING_REQ_CTRL);
> +	reg &= ~XENON_RETUNING_COMPATIBLE;
> +	sdhci_writel(host, reg, XENON_SLOT_RETUNING_REQ_CTRL);
> +
> +	/* Disable the Re-tuning Interrupt */
> +	reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
> +	reg &= ~SDHCI_INT_RETUNE;
> +	sdhci_writel(host, reg, SDHCI_SIGNAL_ENABLE);
> +	reg = sdhci_readl(host, SDHCI_INT_ENABLE);
> +	reg &= ~SDHCI_INT_RETUNE;
> +	sdhci_writel(host, reg, SDHCI_INT_ENABLE);
> +
> +	/* Force to use Tuning Mode 1 */
> +	host->tuning_mode = SDHCI_TUNING_MODE_1;
> +	/* Set re-tuning period */
> +	host->tuning_count = 1 << (priv->tuning_count - 1);
> +}
> +
> +/*
> + * Operations inside struct sdhci_ops
> + */
> +/* Recover the Register Setting cleared during SOFTWARE_RESET_ALL */
> +static void sdhci_xenon_reset_exit(struct sdhci_host *host,
> +				   unsigned char sdhc_id, u8 mask)
> +{
> +	/* Only SOFTWARE RESET ALL will clear the register setting */
> +	if (!(mask & SDHCI_RESET_ALL))
> +		return;
> +
> +	/* Disable tuning request and auto-retuning again */
> +	xenon_sdhc_retune_setup(host);
> +
> +	xenon_set_acg(host, true);
> +
> +	xenon_set_sdclk_off_idle(host, sdhc_id, false);
> +
> +	xenon_mask_cmd_conflict_err(host);
> +}
> +
> +static void sdhci_xenon_reset(struct sdhci_host *host, u8 mask)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +
> +	sdhci_reset(host, mask);
> +	sdhci_xenon_reset_exit(host, priv->sdhc_id, mask);
> +}
> +
> +/*
> + * Xenon defines different values for HS200 and HS400
> + * in Host_Control_2
> + */
> +static void xenon_set_uhs_signaling(struct sdhci_host *host,
> +				    unsigned int timing)
> +{
> +	u16 ctrl_2;
> +
> +	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
> +	/* Select Bus Speed Mode for host */
> +	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
> +	if (timing == MMC_TIMING_MMC_HS200)
> +		ctrl_2 |= XENON_CTRL_HS200;
> +	else if (timing == MMC_TIMING_UHS_SDR104)
> +		ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
> +	else if (timing == MMC_TIMING_UHS_SDR12)
> +		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
> +	else if (timing == MMC_TIMING_UHS_SDR25)
> +		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
> +	else if (timing == MMC_TIMING_UHS_SDR50)
> +		ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
> +	else if ((timing == MMC_TIMING_UHS_DDR50) ||
> +		 (timing == MMC_TIMING_MMC_DDR52))
> +		ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
> +	else if (timing == MMC_TIMING_MMC_HS400)
> +		ctrl_2 |= XENON_CTRL_HS400;
> +	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
> +}
> +
> +static const struct sdhci_ops sdhci_xenon_ops = {
> +	.set_clock		= sdhci_set_clock,
> +	.set_bus_width		= sdhci_set_bus_width,
> +	.reset			= sdhci_xenon_reset,
> +	.set_uhs_signaling	= xenon_set_uhs_signaling,
> +	.get_max_clock		= sdhci_pltfm_clk_get_max_clock,
> +};
> +
> +static const struct sdhci_pltfm_data sdhci_xenon_pdata = {
> +	.ops = &sdhci_xenon_ops,
> +	.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
> +		  SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
> +		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
> +};
> +
> +/*
> + * Xenon Specific Operations in mmc_host_ops
> + */
> +static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
> +{
> +	struct sdhci_host *host = mmc_priv(mmc);
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	unsigned long flags;
> +	u32 reg;
> +
> +	/*
> +	 * HS400/HS200/eMMC HS doesn't have Preset Value register.
> +	 * However, sdhci_set_ios will read HS400/HS200 Preset register.
> +	 * Disable Preset Value register for HS400/HS200.
> +	 * eMMC HS with preset_enabled set will trigger a bug in
> +	 * get_preset_value().
> +	 */
> +	spin_lock_irqsave(&host->lock, flags);

We are no longer using the spin lock in set_ios.  See recent patch "mmc:
sdhci: Do not use spin lock in set_ios paths"

> +	if ((ios->timing == MMC_TIMING_MMC_HS400) ||
> +	    (ios->timing == MMC_TIMING_MMC_HS200) ||
> +	    (ios->timing == MMC_TIMING_MMC_HS)) {
> +		host->preset_enabled = false;
> +		host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
> +		host->flags &= ~SDHCI_PV_ENABLED;
> +
> +		reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
> +		reg &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
> +		sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
> +	} else {
> +		host->quirks2 &= ~SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
> +	}
> +	spin_unlock_irqrestore(&host->lock, flags);
> +
> +	sdhci_set_ios(mmc, ios);
> +
> +	if (host->clock > XENON_DEFAULT_SDCLK_FREQ) {
> +		spin_lock_irqsave(&host->lock, flags);
> +		xenon_set_sdclk_off_idle(host, priv->sdhc_id, true);
> +		spin_unlock_irqrestore(&host->lock, flags);
> +	}
> +}
> +
> +static int xenon_emmc_signal_voltage_switch(struct mmc_host *mmc,
> +					    struct mmc_ios *ios)
> +{
> +	unsigned char voltage = ios->signal_voltage;
> +	struct sdhci_host *host = mmc_priv(mmc);
> +	unsigned char voltage_code;
> +	u32 ctrl;
> +
> +	if ((voltage == MMC_SIGNAL_VOLTAGE_330) ||
> +	    (voltage == MMC_SIGNAL_VOLTAGE_180)) {
> +		if (voltage == MMC_SIGNAL_VOLTAGE_330)
> +			voltage_code = XENON_EMMC_VCCQ_3_3V;
> +		else if (voltage == MMC_SIGNAL_VOLTAGE_180)
> +			voltage_code = XENON_EMMC_VCCQ_1_8V;
> +
> +		/*
> +		 * This host is for eMMC, XENON self-defined
> +		 * eMMC control register should be accessed
> +		 * instead of Host Control 2
> +		 */
> +		ctrl = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
> +		ctrl &= ~XENON_EMMC_VCCQ_MASK;
> +		ctrl |= voltage_code;
> +		sdhci_writel(host, ctrl, XENON_SLOT_EMMC_CTRL);
> +
> +		/* There is no standard to determine this waiting period */
> +		usleep_range(1000, 2000);
> +
> +		/* Check whether io voltage switch is done */
> +		ctrl = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
> +		ctrl &= XENON_EMMC_VCCQ_MASK;
> +		/*
> +		 * This bit is set only when regulator feeds back
> +		 * the voltage switch results to Xenon SDHC.
> +		 * However, in actaul implementation, regulator might not

actaul -> actual

> +		 * provide this feedback.
> +		 * Thus we shall not rely on this bit to determine
> +		 * if switch failed.
> +		 * If the bit is not set, just throw a message.
> +		 * Besides, error code should not be returned.
> +		 */
> +		if (ctrl != voltage_code)
> +			dev_info(mmc_dev(mmc), "fail to detect eMMC signal voltage stable\n");
> +		return 0;
> +	}
> +
> +	dev_err(mmc_dev(mmc), "Unsupported signal voltage: %d\n", voltage);
> +	return -EINVAL;
> +}
> +
> +static int xenon_start_signal_voltage_switch(struct mmc_host *mmc,
> +					     struct mmc_ios *ios)
> +{
> +	struct sdhci_host *host = mmc_priv(mmc);
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +
> +	/*
> +	 * Before SD/SDIO set signal voltage, SD bus clock should be
> +	 * disabled. However, sdhci_set_clock will also disable the Internal
> +	 * clock in mmc_set_signal_voltage().
> +	 * If Internal clock is disabled, the 3.3V/1.8V bit can not be updated.
> +	 * Thus here manually enable internal clock.
> +	 *
> +	 * After switch completes, it is unnecessary to disable internal clock,
> +	 * since keeping internal clock active obeys SD spec.
> +	 */
> +	enable_xenon_internal_clk(host);
> +
> +	if (priv->init_card_type == MMC_TYPE_MMC)
> +		return xenon_emmc_signal_voltage_switch(mmc, ios);
> +
> +	return sdhci_start_signal_voltage_switch(mmc, ios);
> +}
> +
> +/*
> + * Update card type.
> + * priv->init_card_type will be used in PHY timing adjustment.
> + */
> +static void xenon_init_card(struct mmc_host *mmc, struct mmc_card *card)
> +{
> +	struct sdhci_host *host = mmc_priv(mmc);
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +
> +	/* Update card type*/
> +	priv->init_card_type = card->type;
> +}
> +
> +static int xenon_execute_tuning(struct mmc_host *mmc, u32 opcode)
> +{
> +	struct sdhci_host *host = mmc_priv(mmc);
> +
> +	if (host->timing == MMC_TIMING_UHS_DDR50)
> +		return 0;
> +
> +	/*
> +	 * Currently force Xenon driver back to support mode 1 only,
> +	 * even though Xenon might claim to support mode 2 or mode 3.
> +	 * It requires more time to test mode 2/mode 3 on more platforms.
> +	 */
> +	if (host->tuning_mode != SDHCI_TUNING_MODE_1)
> +		xenon_sdhc_retune_setup(host);
> +
> +	return sdhci_execute_tuning(mmc, opcode);
> +}
> +
> +static void xenon_enable_sdio_irq(struct mmc_host *mmc, int enable)
> +{
> +	struct sdhci_host *host = mmc_priv(mmc);
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	u32 reg;
> +	u8 sdhc_id = priv->sdhc_id;
> +
> +	sdhci_enable_sdio_irq(mmc, enable);
> +
> +	if (enable) {
> +		/*
> +		 * Set SDIO Card Inserted indication
> +		 * to enable detecting SDIO async irq.
> +		 */
> +		reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
> +		reg |= (1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
> +		sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
> +	} else {
> +		/* Clear SDIO Card Inserted indication */
> +		reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
> +		reg &= ~(1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
> +		sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
> +	}
> +}
> +
> +static void xenon_replace_mmc_host_ops(struct sdhci_host *host)
> +{
> +	host->mmc_host_ops.set_ios = xenon_set_ios;
> +	host->mmc_host_ops.start_signal_voltage_switch =
> +			xenon_start_signal_voltage_switch;
> +	host->mmc_host_ops.init_card = xenon_init_card;
> +	host->mmc_host_ops.execute_tuning = xenon_execute_tuning;
> +	host->mmc_host_ops.enable_sdio_irq = xenon_enable_sdio_irq;
> +}
> +
> +/*
> + * Parse Xenon specific DT properties:
> + * init_card_type: check whether this SDHC is for eMMC
> + * sdhc-id: the index of current SDHC.
> + *	    Refer to XENON_SYS_CFG_INFO register
> + * tun-count: the interval between re-tuning
> + */
> +static int xenon_probe_dt(struct platform_device *pdev)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	struct sdhci_host *host = platform_get_drvdata(pdev);
> +	struct mmc_host *mmc = host->mmc;
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	u32 sdhc_id, nr_sdhc;
> +	u32 tuning_count;
> +
> +	/* Disable HS200 on Armada AP806 */
> +	if (of_device_is_compatible(np, "marvell,armada-ap806-sdhci"))
> +		host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
> +
> +	priv->init_card_type = XENON_CARD_TYPE_UNKNOWN;
> +	/* Check if mmc-card sub-node exists */
> +	if (mmc_of_parse_mmc_card(mmc)) {
> +		priv->init_card_type = MMC_TYPE_MMC;
> +		/*
> +		 * Force to clear BUS_TEST to
> +		 * skip bus_test_pre and bus_test_post
> +		 */
> +		mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST;
> +	}
> +
> +	priv->sdhc_id = 0x0;
> +	if (!of_property_read_u32(np, "marvell,xenon-sdhc-id", &sdhc_id)) {
> +		nr_sdhc = sdhci_readl(host, XENON_SYS_CFG_INFO);
> +		nr_sdhc &= XENON_NR_SUPPORTED_SLOT_MASK;
> +		if (unlikely(sdhc_id > nr_sdhc)) {
> +			dev_err(mmc_dev(mmc), "SDHC Index %d exceeds Number of SDHCs %d\n",
> +				sdhc_id, nr_sdhc);
> +			return -EINVAL;
> +		}
> +	}
> +
> +	tuning_count = XENON_DEF_TUNING_COUNT;
> +	if (!of_property_read_u32(np, "marvell,xenon-tun-count",
> +				  &tuning_count)) {
> +		if (unlikely(tuning_count >= XENON_TMR_RETUN_NO_PRESENT)) {
> +			dev_err(mmc_dev(mmc), "Wrong Re-tuning Count. Set default value %d\n",
> +				XENON_DEF_TUNING_COUNT);
> +			tuning_count = XENON_DEF_TUNING_COUNT;
> +		}
> +	}
> +	priv->tuning_count = tuning_count;
> +
> +	return 0;
> +}
> +
> +static int xenon_sdhc_probe(struct sdhci_host *host)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	u8 sdhc_id = priv->sdhc_id;
> +
> +	/* Enable SDHC */
> +	xenon_enable_sdhc(host, sdhc_id);
> +
> +	/* Enable ACG */
> +	xenon_set_acg(host, true);
> +
> +	/* Enable Parallel Transfer Mode */
> +	xenon_enable_sdhc_parallel_tran(host, sdhc_id);
> +
> +	xenon_mask_cmd_conflict_err(host);
> +
> +	return 0;
> +}
> +
> +static void xenon_sdhc_remove(struct sdhci_host *host)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	u8 sdhc_id = priv->sdhc_id;
> +
> +	/* disable SDHC */
> +	xenon_disable_sdhc(host, sdhc_id);
> +}
> +
> +static int sdhci_xenon_probe(struct platform_device *pdev)
> +{
> +	struct sdhci_pltfm_host *pltfm_host;
> +	struct sdhci_host *host;
> +	struct sdhci_xenon_priv *priv;
> +	int err;
> +
> +	host = sdhci_pltfm_init(pdev, &sdhci_xenon_pdata,
> +				sizeof(struct sdhci_xenon_priv));
> +	if (IS_ERR(host))
> +		return PTR_ERR(host);
> +
> +	pltfm_host = sdhci_priv(host);
> +	priv = sdhci_pltfm_priv(pltfm_host);
> +
> +	xenon_set_acg(host, false);
> +
> +	/*
> +	 * Link Xenon specific mmc_host_ops function,
> +	 * to replace standard ones in sdhci_ops.
> +	 */
> +	xenon_replace_mmc_host_ops(host);
> +
> +	pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
> +	if (IS_ERR(pltfm_host->clk)) {
> +		err = PTR_ERR(pltfm_host->clk);
> +		dev_err(&pdev->dev, "Failed to setup input clk: %d\n", err);
> +		goto free_pltfm;
> +	}
> +	err = clk_prepare_enable(pltfm_host->clk);
> +	if (err)
> +		goto free_pltfm;
> +
> +	err = mmc_of_parse(host->mmc);
> +	if (err)
> +		goto err_clk;
> +
> +	sdhci_get_of_property(pdev);
> +
> +	/* Xenon specific dt parse */
> +	err = xenon_probe_dt(pdev);
> +	if (err)
> +		goto err_clk;
> +
> +	err = xenon_sdhc_probe(host);
> +	if (err)
> +		goto err_clk;
> +
> +	err = sdhci_add_host(host);
> +	if (err)
> +		goto remove_sdhc;
> +
> +	return 0;
> +
> +remove_sdhc:
> +	xenon_sdhc_remove(host);
> +err_clk:
> +	clk_disable_unprepare(pltfm_host->clk);
> +free_pltfm:
> +	sdhci_pltfm_free(pdev);
> +	return err;
> +}
> +
> +static int sdhci_xenon_remove(struct platform_device *pdev)
> +{
> +	struct sdhci_host *host = platform_get_drvdata(pdev);
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +
> +	xenon_sdhc_remove(host);
> +
> +	sdhci_remove_host(host, 0);
> +
> +	clk_disable_unprepare(pltfm_host->clk);
> +
> +	sdhci_pltfm_free(pdev);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id sdhci_xenon_dt_ids[] = {
> +	{ .compatible = "marvell,armada-ap806-sdhci",},
> +	{ .compatible = "marvell,armada-cp110-sdhci",},
> +	{ .compatible = "marvell,armada-3700-sdhci",},
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids);
> +
> +static struct platform_driver sdhci_xenon_driver = {
> +	.driver	= {
> +		.name	= "xenon-sdhci",
> +		.of_match_table = sdhci_xenon_dt_ids,
> +		.pm = &sdhci_pltfm_pmops,
> +	},
> +	.probe	= sdhci_xenon_probe,
> +	.remove	= sdhci_xenon_remove,
> +};
> +
> +module_platform_driver(sdhci_xenon_driver);
> +
> +MODULE_DESCRIPTION("SDHCI platform driver for Marvell Xenon SDHC");
> +MODULE_AUTHOR("Hu Ziji <huziji@marvell.com>");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h
> new file mode 100644
> index 000000000000..69de711db9eb
> --- /dev/null
> +++ b/drivers/mmc/host/sdhci-xenon.h
> @@ -0,0 +1,70 @@
> +/*
> + * Copyright (C) 2016 Marvell, All Rights Reserved.
> + *
> + * Author:	Hu Ziji <huziji@marvell.com>
> + * Date:	2016-8-24
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + */
> +#ifndef SDHCI_XENON_H_
> +#define SDHCI_XENON_H_
> +
> +/* Register Offset of Xenon SDHC self-defined register */
> +#define XENON_SYS_CFG_INFO			0x0104
> +#define XENON_SLOT_TYPE_SDIO_SHIFT		24
> +#define XENON_NR_SUPPORTED_SLOT_MASK		0x7
> +
> +#define XENON_SYS_OP_CTRL			0x0108
> +#define XENON_AUTO_CLKGATE_DISABLE_MASK		BIT(20)
> +#define XENON_SDCLK_IDLEOFF_ENABLE_SHIFT	8
> +#define XENON_SLOT_ENABLE_SHIFT			0
> +
> +#define XENON_SYS_EXT_OP_CTRL			0x010C
> +#define XENON_MASK_CMD_CONFLICT_ERR		BIT(8)
> +
> +#define XENON_SLOT_EMMC_CTRL			0x0130
> +#define XENON_EMMC_VCCQ_MASK			0x3
> +#define XENON_EMMC_VCCQ_1_8V			0x1
> +#define XENON_EMMC_VCCQ_3_3V			0x3
> +
> +#define XENON_SLOT_RETUNING_REQ_CTRL		0x0144
> +/* retuning compatible */
> +#define XENON_RETUNING_COMPATIBLE		0x1
> +
> +/* Tuning Parameter */
> +#define XENON_TMR_RETUN_NO_PRESENT		0xF
> +#define XENON_DEF_TUNING_COUNT			0x9
> +
> +#define XENON_DEFAULT_SDCLK_FREQ		400000
> +
> +/* Xenon specific Mode Select value */
> +#define XENON_CTRL_HS200			0x5
> +#define XENON_CTRL_HS400			0x6
> +
> +/* Indicate Card Type is not clear yet */
> +#define XENON_CARD_TYPE_UNKNOWN			0xF
> +
> +struct sdhci_xenon_priv {
> +	unsigned char	tuning_count;
> +	/* idx of SDHC */
> +	u8		sdhc_id;
> +
> +	/*
> +	 * eMMC/SD/SDIO require different PHY settings or
> +	 * voltage control. It's necessary for Xenon driver to
> +	 * recognize card type during, or even before initialization.
> +	 * However, mmc_host->card is not available yet at that time.
> +	 * This field records the card type during init.
> +	 * For eMMC, it is updated in dt parse. For SD/SDIO, it is
> +	 * updated in xenon_init_card().
> +	 *
> +	 * It is only valid during initialization after it is updated.
> +	 * Do not access this variable in normal transfers after
> +	 * initialization completes.
> +	 */
> +	unsigned int	init_card_type;
> +};
> +
> +#endif
> 

[PATCH v6 09/14] mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC

[Gregory CLEMENT]

From: Hu Ziji <huziji@marvell.com>

Marvell Xenon eMMC/SD/SDIO Host Controller contains PHY.
Multiple types of PHYs are supported.

Add support to multiple types of PHYs init and configuration.
Add register definitions of PHYs.

Xenon PHY cannot fit in kernel common PHY framework.
Xenon SDHC PHY register is a part of Xenon SDHC register set.
Besides, MMC initialization has to call several PHY functions to
complete timing setting.
Those PHY setting functions have to access SDHC registers and know
current MMC setting, such as bus width, clock frequency and
speed mode.
As a result, implement Xenon PHY in MMC host directory.

Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/mmc/host/Makefile          |   2 +-
 drivers/mmc/host/sdhci-xenon-phy.c | 751 ++++++++++++++++++++++++++++++-
 drivers/mmc/host/sdhci-xenon.c     |   3 +-
 drivers/mmc/host/sdhci-xenon.h     |  37 +-
 4 files changed, 791 insertions(+), 2 deletions(-)
 create mode 100644 drivers/mmc/host/sdhci-xenon-phy.c

diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index b0a2ab4b256e..893b48db5513 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -84,4 +84,4 @@ ifeq ($(CONFIG_CB710_DEBUG),y)
 endif
 
 obj-$(CONFIG_MMC_SDHCI_XENON)	+= sdhci-xenon-driver.o
-sdhci-xenon-driver-y		+= sdhci-xenon.o
+sdhci-xenon-driver-y		+= sdhci-xenon.o sdhci-xenon-phy.o
diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c
new file mode 100644
index 000000000000..c26ba3a180a0
--- /dev/null
+++ b/drivers/mmc/host/sdhci-xenon-phy.c
@@ -0,0 +1,751 @@
+/*
+ * PHY support for Xenon SDHC
+ *
+ * Copyright (C) 2016 Marvell, All Rights Reserved.
+ *
+ * Author:	Hu Ziji <huziji@marvell.com>
+ * Date:	2016-8-24
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ */
+
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/of_address.h>
+
+#include "sdhci-pltfm.h"
+#include "sdhci-xenon.h"
+
+/* Register base for eMMC PHY 5.0 Version */
+#define XENON_EMMC_5_0_PHY_REG_BASE		0x0160
+/* Register base for eMMC PHY 5.1 Version */
+#define XENON_EMMC_PHY_REG_BASE			0x0170
+
+#define XENON_EMMC_PHY_TIMING_ADJUST		XENON_EMMC_PHY_REG_BASE
+#define XENON_EMMC_5_0_PHY_TIMING_ADJUST	XENON_EMMC_5_0_PHY_REG_BASE
+#define XENON_TIMING_ADJUST_SLOW_MODE		BIT(29)
+#define XENON_TIMING_ADJUST_SDIO_MODE		BIT(28)
+#define XENON_OUTPUT_QSN_PHASE_SELECT		BIT(17)
+#define XENON_SAMPL_INV_QSP_PHASE_SELECT	BIT(18)
+#define XENON_SAMPL_INV_QSP_PHASE_SELECT_SHIFT	18
+#define XENON_PHY_INITIALIZAION			BIT(31)
+#define XENON_WAIT_CYCLE_BEFORE_USING_MASK	0xF
+#define XENON_WAIT_CYCLE_BEFORE_USING_SHIFT	12
+#define XENON_FC_SYNC_EN_DURATION_MASK		0xF
+#define XENON_FC_SYNC_EN_DURATION_SHIFT		8
+#define XENON_FC_SYNC_RST_EN_DURATION_MASK	0xF
+#define XENON_FC_SYNC_RST_EN_DURATION_SHIFT	4
+#define XENON_FC_SYNC_RST_DURATION_MASK		0xF
+#define XENON_FC_SYNC_RST_DURATION_SHIFT	0
+
+#define XENON_EMMC_PHY_FUNC_CONTROL		(XENON_EMMC_PHY_REG_BASE + 0x4)
+#define XENON_EMMC_5_0_PHY_FUNC_CONTROL		\
+	(XENON_EMMC_5_0_PHY_REG_BASE + 0x4)
+#define XENON_ASYNC_DDRMODE_MASK		BIT(23)
+#define XENON_ASYNC_DDRMODE_SHIFT		23
+#define XENON_CMD_DDR_MODE			BIT(16)
+#define XENON_DQ_DDR_MODE_SHIFT			8
+#define XENON_DQ_DDR_MODE_MASK			0xFF
+#define XENON_DQ_ASYNC_MODE			BIT(4)
+
+#define XENON_EMMC_PHY_PAD_CONTROL		(XENON_EMMC_PHY_REG_BASE + 0x8)
+#define XENON_EMMC_5_0_PHY_PAD_CONTROL		\
+	(XENON_EMMC_5_0_PHY_REG_BASE + 0x8)
+#define XENON_REC_EN_SHIFT			24
+#define XENON_REC_EN_MASK			0xF
+#define XENON_FC_DQ_RECEN			BIT(24)
+#define XENON_FC_CMD_RECEN			BIT(25)
+#define XENON_FC_QSP_RECEN			BIT(26)
+#define XENON_FC_QSN_RECEN			BIT(27)
+#define XENON_OEN_QSN				BIT(28)
+#define XENON_AUTO_RECEN_CTRL			BIT(30)
+#define XENON_FC_ALL_CMOS_RECEIVER		0xF000
+
+#define XENON_EMMC5_FC_QSP_PD			BIT(18)
+#define XENON_EMMC5_FC_QSP_PU			BIT(22)
+#define XENON_EMMC5_FC_CMD_PD			BIT(17)
+#define XENON_EMMC5_FC_CMD_PU			BIT(21)
+#define XENON_EMMC5_FC_DQ_PD			BIT(16)
+#define XENON_EMMC5_FC_DQ_PU			BIT(20)
+
+#define XENON_EMMC_PHY_PAD_CONTROL1		(XENON_EMMC_PHY_REG_BASE + 0xC)
+#define XENON_EMMC5_1_FC_QSP_PD			BIT(9)
+#define XENON_EMMC5_1_FC_QSP_PU			BIT(25)
+#define XENON_EMMC5_1_FC_CMD_PD			BIT(8)
+#define XENON_EMMC5_1_FC_CMD_PU			BIT(24)
+#define XENON_EMMC5_1_FC_DQ_PD			0xFF
+#define XENON_EMMC5_1_FC_DQ_PU			(0xFF << 16)
+
+#define XENON_EMMC_PHY_PAD_CONTROL2		(XENON_EMMC_PHY_REG_BASE + 0x10)
+#define XENON_EMMC_5_0_PHY_PAD_CONTROL2		\
+	(XENON_EMMC_5_0_PHY_REG_BASE + 0xC)
+#define XENON_ZNR_MASK				0x1F
+#define XENON_ZNR_SHIFT				8
+#define XENON_ZPR_MASK				0x1F
+/* Preferred ZNR and ZPR value vary between different boards.
+ * The specific ZNR and ZPR value should be defined here
+ * according to board actual timing.
+ */
+#define XENON_ZNR_DEF_VALUE			0xF
+#define XENON_ZPR_DEF_VALUE			0xF
+
+#define XENON_EMMC_PHY_DLL_CONTROL		(XENON_EMMC_PHY_REG_BASE + 0x14)
+#define XENON_EMMC_5_0_PHY_DLL_CONTROL		\
+	(XENON_EMMC_5_0_PHY_REG_BASE + 0x10)
+#define XENON_DLL_ENABLE			BIT(31)
+#define XENON_DLL_UPDATE_STROBE_5_0		BIT(30)
+#define XENON_DLL_REFCLK_SEL			BIT(30)
+#define XENON_DLL_UPDATE			BIT(23)
+#define XENON_DLL_PHSEL1_SHIFT			24
+#define XENON_DLL_PHSEL0_SHIFT			16
+#define XENON_DLL_PHASE_MASK			0x3F
+#define XENON_DLL_PHASE_90_DEGREE		0x1F
+#define XENON_DLL_FAST_LOCK			BIT(5)
+#define XENON_DLL_GAIN2X			BIT(3)
+#define XENON_DLL_BYPASS_EN			BIT(0)
+
+#define XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST	\
+	(XENON_EMMC_5_0_PHY_REG_BASE + 0x14)
+#define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST	(XENON_EMMC_PHY_REG_BASE + 0x18)
+#define XENON_LOGIC_TIMING_VALUE		0x00AA8977
+
+/*
+ * List offset of PHY registers and some special register values
+ * in eMMC PHY 5.0 or eMMC PHY 5.1
+ */
+struct xenon_emmc_phy_regs {
+	/* Offset of Timing Adjust register */
+	u16 timing_adj;
+	/* Offset of Func Control register */
+	u16 func_ctrl;
+	/* Offset of Pad Control register */
+	u16 pad_ctrl;
+	/* Offset of Pad Control register 2 */
+	u16 pad_ctrl2;
+	/* Offset of DLL Control register */
+	u16 dll_ctrl;
+	/* Offset of Logic Timing Adjust register */
+	u16 logic_timing_adj;
+	/* DLL Update Enable bit */
+	u32 dll_update;
+};
+
+static const char * const phy_types[] = {
+	"emmc 5.0 phy",
+	"emmc 5.1 phy"
+};
+
+enum phy_type_enum {
+	EMMC_5_0_PHY,
+	EMMC_5_1_PHY,
+	NR_PHY_TYPES
+};
+
+static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = {
+	.timing_adj	= XENON_EMMC_5_0_PHY_TIMING_ADJUST,
+	.func_ctrl	= XENON_EMMC_5_0_PHY_FUNC_CONTROL,
+	.pad_ctrl	= XENON_EMMC_5_0_PHY_PAD_CONTROL,
+	.pad_ctrl2	= XENON_EMMC_5_0_PHY_PAD_CONTROL2,
+	.dll_ctrl	= XENON_EMMC_5_0_PHY_DLL_CONTROL,
+	.logic_timing_adj = XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST,
+	.dll_update	= XENON_DLL_UPDATE_STROBE_5_0,
+};
+
+static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs = {
+	.timing_adj	= XENON_EMMC_PHY_TIMING_ADJUST,
+	.func_ctrl	= XENON_EMMC_PHY_FUNC_CONTROL,
+	.pad_ctrl	= XENON_EMMC_PHY_PAD_CONTROL,
+	.pad_ctrl2	= XENON_EMMC_PHY_PAD_CONTROL2,
+	.dll_ctrl	= XENON_EMMC_PHY_DLL_CONTROL,
+	.logic_timing_adj = XENON_EMMC_PHY_LOGIC_TIMING_ADJUST,
+	.dll_update	= XENON_DLL_UPDATE,
+};
+
+/*
+ * eMMC PHY configuration and operations
+ */
+struct emmc_phy_params {
+	bool	slow_mode;
+
+	u8	znr;
+	u8	zpr;
+
+	/* Nr of consecutive Sampling Points of a Valid Sampling Window */
+	u8	nr_tun_times;
+	/* Divider for calculating Tuning Step */
+	u8	tun_step_divider;
+};
+
+static int alloc_emmc_phy(struct sdhci_xenon_priv *priv)
+{
+	struct emmc_phy_params *params;
+
+	params = kzalloc(sizeof(*params), GFP_KERNEL);
+	if (!params)
+		return -ENOMEM;
+
+	priv->phy_params = params;
+	if (priv->phy_type == EMMC_5_0_PHY)
+		priv->emmc_phy_regs = &xenon_emmc_5_0_phy_regs;
+	else
+		priv->emmc_phy_regs = &xenon_emmc_5_1_phy_regs;
+
+	return 0;
+}
+
+/*
+ * eMMC 5.0/5.1 PHY init/re-init.
+ * eMMC PHY init should be executed after:
+ * 1. SDCLK frequency changes.
+ * 2. SDCLK is stopped and re-enabled.
+ * 3. config in emmc_phy_regs->timing_adj and emmc_phy_regs->func_ctrl
+ * are changed
+ */
+static int emmc_phy_init(struct sdhci_host *host)
+{
+	u32 reg;
+	u32 wait, clock;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
+
+	reg = sdhci_readl(host, phy_regs->timing_adj);
+	reg |= XENON_PHY_INITIALIZAION;
+	sdhci_writel(host, reg, phy_regs->timing_adj);
+
+	/* Add duration of FC_SYNC_RST */
+	wait = ((reg >> XENON_FC_SYNC_RST_DURATION_SHIFT) &
+			XENON_FC_SYNC_RST_DURATION_MASK);
+	/* Add interval between FC_SYNC_EN and FC_SYNC_RST */
+	wait += ((reg >> XENON_FC_SYNC_RST_EN_DURATION_SHIFT) &
+			XENON_FC_SYNC_RST_EN_DURATION_MASK);
+	/* Add duration of asserting FC_SYNC_EN */
+	wait += ((reg >> XENON_FC_SYNC_EN_DURATION_SHIFT) &
+			XENON_FC_SYNC_EN_DURATION_MASK);
+	/* Add duration of waiting for PHY */
+	wait += ((reg >> XENON_WAIT_CYCLE_BEFORE_USING_SHIFT) &
+			XENON_WAIT_CYCLE_BEFORE_USING_MASK);
+	/* 4 additional bus clock and 4 AXI bus clock are required */
+	wait += 8;
+	wait <<= 20;
+
+	clock = host->clock;
+	if (!clock)
+		/* Use the possibly slowest bus frequency value */
+		clock = XENON_LOWEST_SDCLK_FREQ;
+	/* get the wait time */
+	wait /= clock;
+	wait++;
+	/* wait for host eMMC PHY init completes */
+	udelay(wait);
+
+	reg = sdhci_readl(host, phy_regs->timing_adj);
+	reg &= XENON_PHY_INITIALIZAION;
+	if (reg) {
+		dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n",
+			wait);
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+/*
+ * Enable eMMC PHY HW DLL
+ * DLL should be enabled and stable before HS200/SDR104 tuning,
+ * and before HS400 data strobe setting.
+ */
+static int emmc_phy_enable_dll(struct sdhci_host *host)
+{
+	u32 reg;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
+	u8 timeout;
+
+	if (WARN_ON(host->clock <= MMC_HIGH_52_MAX_DTR))
+		return -EINVAL;
+
+	reg = sdhci_readl(host, phy_regs->dll_ctrl);
+	if (reg & XENON_DLL_ENABLE)
+		return 0;
+
+	/* Enable DLL */
+	reg = sdhci_readl(host, phy_regs->dll_ctrl);
+	reg |= (XENON_DLL_ENABLE | XENON_DLL_FAST_LOCK);
+
+	/*
+	 * Set Phase as 90 degree, which is most common value.
+	 * Might set another value if necessary.
+	 * The granularity is 1 degree.
+	 */
+	reg &= ~((XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL0_SHIFT) |
+		 (XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL1_SHIFT));
+	reg |= ((XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL0_SHIFT) |
+		(XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL1_SHIFT));
+
+	reg &= ~XENON_DLL_BYPASS_EN;
+	reg |= phy_regs->dll_update;
+	if (priv->phy_type == EMMC_5_1_PHY)
+		reg &= ~XENON_DLL_REFCLK_SEL;
+	sdhci_writel(host, reg, phy_regs->dll_ctrl);
+
+	/* Wait max 32 ms */
+	timeout = 32;
+	while (!(sdhci_readw(host, XENON_SLOT_EXT_PRESENT_STATE) &
+		XENON_DLL_LOCK_STATE)) {
+		if (!timeout) {
+			dev_err(mmc_dev(host->mmc), "Wait for DLL Lock time-out\n");
+			return -ETIMEDOUT;
+		}
+		timeout--;
+		mdelay(1);
+	}
+	return 0;
+}
+
+/*
+ * Config to eMMC PHY to prepare for tuning.
+ * Enable HW DLL and set the TUNING_STEP
+ */
+static int emmc_phy_config_tuning(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	struct emmc_phy_params *params = priv->phy_params;
+	u32 reg, tuning_step;
+	int ret;
+	unsigned long flags;
+
+	if (host->clock <= MMC_HIGH_52_MAX_DTR)
+		return -EINVAL;
+
+	spin_lock_irqsave(&host->lock, flags);
+
+	ret = emmc_phy_enable_dll(host);
+	if (ret) {
+		spin_unlock_irqrestore(&host->lock, flags);
+		return ret;
+	}
+
+	/* Achieve TUNING_STEP with HW DLL help */
+	reg = sdhci_readl(host, XENON_SLOT_DLL_CUR_DLY_VAL);
+	tuning_step = reg / params->tun_step_divider;
+	if (unlikely(tuning_step > XENON_TUNING_STEP_MASK)) {
+		dev_warn(mmc_dev(host->mmc),
+			 "HS200 TUNING_STEP %d is larger than MAX value\n",
+			 tuning_step);
+		tuning_step = XENON_TUNING_STEP_MASK;
+	}
+
+	/* Set TUNING_STEP for later tuning */
+	reg = sdhci_readl(host, XENON_SLOT_OP_STATUS_CTRL);
+	reg &= ~(XENON_TUN_CONSECUTIVE_TIMES_MASK <<
+		 XENON_TUN_CONSECUTIVE_TIMES_SHIFT);
+	reg |= (params->nr_tun_times << XENON_TUN_CONSECUTIVE_TIMES_SHIFT);
+	reg &= ~(XENON_TUNING_STEP_MASK << XENON_TUNING_STEP_SHIFT);
+	reg |= (tuning_step << XENON_TUNING_STEP_SHIFT);
+	sdhci_writel(host, reg, XENON_SLOT_OP_STATUS_CTRL);
+
+	spin_unlock_irqrestore(&host->lock, flags);
+	return 0;
+}
+
+static void __emmc_phy_disable_data_strobe(struct sdhci_host *host)
+{
+	u32 reg;
+
+	/* Disable SDHC Data Strobe */
+	reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
+	reg &= ~XENON_ENABLE_DATA_STROBE;
+	sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL);
+}
+
+/* Set HS400 Data Strobe */
+static void emmc_phy_strobe_delay_adj(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	unsigned long flags;
+	u32 reg;
+
+	if (WARN_ON(host->timing != MMC_TIMING_MMC_HS400))
+		return;
+
+	if (host->clock <= MMC_HIGH_52_MAX_DTR)
+		return;
+
+	dev_dbg(mmc_dev(host->mmc), "starts HS400 strobe delay adjustment\n");
+
+	spin_lock_irqsave(&host->lock, flags);
+
+	emmc_phy_enable_dll(host);
+
+	/* Enable SDHC Data Strobe */
+	reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
+	reg |= XENON_ENABLE_DATA_STROBE;
+	sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL);
+
+	/* Set Data Strobe Pull down */
+	if (priv->phy_type == EMMC_5_0_PHY) {
+		reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
+		reg |= XENON_EMMC5_FC_QSP_PD;
+		reg &= ~XENON_EMMC5_FC_QSP_PU;
+		sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
+	} else {
+		reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
+		reg |= XENON_EMMC5_1_FC_QSP_PD;
+		reg &= ~XENON_EMMC5_1_FC_QSP_PU;
+		sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
+	}
+	spin_unlock_irqrestore(&host->lock, flags);
+}
+
+/*
+ * If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz)
+ * in SDR mode, enable Slow Mode to bypass eMMC PHY.
+ * SDIO slower SDR mode also requires Slow Mode.
+ *
+ * If Slow Mode is enabled, return true.
+ * Otherwise, return false.
+ */
+static bool emmc_phy_slow_mode(struct sdhci_host *host,
+			       unsigned char timing)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	struct emmc_phy_params *params = priv->phy_params;
+	struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
+	u32 reg;
+
+	if (host->clock > MMC_HIGH_52_MAX_DTR)
+		return false;
+
+	reg = sdhci_readl(host, phy_regs->timing_adj);
+	/* Enable Slow Mode for SDIO in slower SDR mode */
+	if ((priv->init_card_type == MMC_TYPE_SDIO) &&
+	    ((timing == MMC_TIMING_UHS_SDR25) ||
+	     (timing == MMC_TIMING_UHS_SDR12) ||
+	     (timing == MMC_TIMING_SD_HS))) {
+		reg |= XENON_TIMING_ADJUST_SLOW_MODE;
+		sdhci_writel(host, reg, phy_regs->timing_adj);
+		return true;
+	}
+
+	/* Check if Slow Mode is required in lower speed mode in SDR mode */
+	if (((timing == MMC_TIMING_UHS_SDR25) ||
+	     (timing == MMC_TIMING_UHS_SDR12) ||
+	     (timing == MMC_TIMING_SD_HS) ||
+	     (timing == MMC_TIMING_MMC_HS)) && params->slow_mode) {
+		reg |= XENON_TIMING_ADJUST_SLOW_MODE;
+		sdhci_writel(host, reg, phy_regs->timing_adj);
+		return true;
+	}
+
+	reg &= ~XENON_TIMING_ADJUST_SLOW_MODE;
+	sdhci_writel(host, reg, phy_regs->timing_adj);
+	return false;
+}
+
+/*
+ * Set-up eMMC 5.0/5.1 PHY.
+ * Specific configuration depends on the current speed mode in use.
+ */
+static void emmc_phy_set(struct sdhci_host *host,
+			 unsigned char timing)
+{
+	u32 reg;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	struct emmc_phy_params *params = priv->phy_params;
+	struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
+	unsigned long flags;
+
+	dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting starts\n");
+
+	spin_lock_irqsave(&host->lock, flags);
+
+	/* Setup pad, set bit[28] and bits[26:24] */
+	reg = sdhci_readl(host, phy_regs->pad_ctrl);
+	reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN |
+		XENON_FC_QSP_RECEN | XENON_OEN_QSN);
+	/* All FC_XX_RECEIVCE should be set as CMOS Type */
+	reg |= XENON_FC_ALL_CMOS_RECEIVER;
+	sdhci_writel(host, reg, phy_regs->pad_ctrl);
+
+	/* Set CMD and DQ Pull Up */
+	if (priv->phy_type == EMMC_5_0_PHY) {
+		reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
+		reg |= (XENON_EMMC5_FC_CMD_PU | XENON_EMMC5_FC_DQ_PU);
+		reg &= ~(XENON_EMMC5_FC_CMD_PD | XENON_EMMC5_FC_DQ_PD);
+		sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
+	} else {
+		reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
+		reg |= (XENON_EMMC5_1_FC_CMD_PU | XENON_EMMC5_1_FC_DQ_PU);
+		reg &= ~(XENON_EMMC5_1_FC_CMD_PD | XENON_EMMC5_1_FC_DQ_PD);
+		sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
+	}
+
+	if (timing == MMC_TIMING_LEGACY) {
+		/*
+		 * If Slow Mode is required, enable Slow Mode by default
+		 * in early init phase to avoid any potential issue.
+		 */
+		if (params->slow_mode) {
+			reg = sdhci_readl(host, phy_regs->timing_adj);
+			reg |= XENON_TIMING_ADJUST_SLOW_MODE;
+			sdhci_writel(host, reg, phy_regs->timing_adj);
+		}
+		goto phy_init;
+	}
+
+	/*
+	 * FIXME: should depends on the specific board timing.
+	 */
+	if ((timing == MMC_TIMING_MMC_HS400) ||
+	    (timing == MMC_TIMING_MMC_HS200) ||
+	    (timing == MMC_TIMING_UHS_SDR50) ||
+	    (timing == MMC_TIMING_UHS_SDR104) ||
+	    (timing == MMC_TIMING_UHS_DDR50) ||
+	    (timing == MMC_TIMING_UHS_SDR25) ||
+	    (timing == MMC_TIMING_MMC_DDR52)) {
+		reg = sdhci_readl(host, phy_regs->timing_adj);
+		reg &= ~XENON_OUTPUT_QSN_PHASE_SELECT;
+		sdhci_writel(host, reg, phy_regs->timing_adj);
+	}
+
+	/*
+	 * If SDIO card, set SDIO Mode
+	 * Otherwise, clear SDIO Mode
+	 */
+	reg = sdhci_readl(host, phy_regs->timing_adj);
+	if (priv->init_card_type == MMC_TYPE_SDIO)
+		reg |= XENON_TIMING_ADJUST_SDIO_MODE;
+	else
+		reg &= ~XENON_TIMING_ADJUST_SDIO_MODE;
+	sdhci_writel(host, reg, phy_regs->timing_adj);
+
+	if (emmc_phy_slow_mode(host, timing))
+		goto phy_init;
+
+	/*
+	 * Set preferred ZNR and ZPR value
+	 * The ZNR and ZPR value vary between different boards.
+	 * Define them both in sdhci-xenon-emmc-phy.h.
+	 */
+	reg = sdhci_readl(host, phy_regs->pad_ctrl2);
+	reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK);
+	reg |= ((params->znr << XENON_ZNR_SHIFT) | params->zpr);
+	sdhci_writel(host, reg, phy_regs->pad_ctrl2);
+
+	/*
+	 * When setting EMMC_PHY_FUNC_CONTROL register,
+	 * SD clock should be disabled
+	 */
+	reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
+	reg &= ~SDHCI_CLOCK_CARD_EN;
+	sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
+
+	reg = sdhci_readl(host, phy_regs->func_ctrl);
+	if ((timing == MMC_TIMING_UHS_DDR50) ||
+	    (timing == MMC_TIMING_MMC_HS400) ||
+	    (timing == MMC_TIMING_MMC_DDR52))
+		reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
+		       XENON_CMD_DDR_MODE;
+	else
+		reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
+			 XENON_CMD_DDR_MODE);
+
+	if (timing == MMC_TIMING_MMC_HS400)
+		reg &= ~XENON_DQ_ASYNC_MODE;
+	else
+		reg |= XENON_DQ_ASYNC_MODE;
+	sdhci_writel(host, reg, phy_regs->func_ctrl);
+
+	/* Enable bus clock */
+	reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
+	reg |= SDHCI_CLOCK_CARD_EN;
+	sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
+
+	if (timing == MMC_TIMING_MMC_HS400)
+		/* Hardware team recommend a value for HS400 */
+		sdhci_writel(host, XENON_LOGIC_TIMING_VALUE,
+			     phy_regs->logic_timing_adj);
+	else
+		__emmc_phy_disable_data_strobe(host);
+
+phy_init:
+	emmc_phy_init(host);
+
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n");
+}
+
+static int emmc_phy_parse_param_dt(struct sdhci_host *host,
+				   struct device_node *np,
+				   struct emmc_phy_params *params)
+{
+	u32 value;
+
+	if (of_property_read_bool(np, "marvell,xenon-phy-slow-mode"))
+		params->slow_mode = true;
+	else
+		params->slow_mode = false;
+
+	if (!of_property_read_u32(np, "marvell,xenon-phy-znr", &value))
+		params->znr = value & XENON_ZNR_MASK;
+	else
+		params->znr = XENON_ZNR_DEF_VALUE;
+
+	if (!of_property_read_u32(np, "marvell,xenon-phy-zpr", &value))
+		params->zpr = value & XENON_ZPR_MASK;
+	else
+		params->zpr = XENON_ZPR_DEF_VALUE;
+
+	if (!of_property_read_u32(np, "marvell,xenon-phy-nr-success-tun",
+				  &value))
+		params->nr_tun_times = value & XENON_TUN_CONSECUTIVE_TIMES_MASK;
+	else
+		params->nr_tun_times = XENON_TUN_CONSECUTIVE_TIMES;
+
+	if (!of_property_read_u32(np, "marvell,xenon-phy-tun-step-divider",
+				  &value))
+		params->tun_step_divider = value & 0xFF;
+	else
+		params->tun_step_divider = XENON_TUNING_STEP_DIVIDER;
+
+	return 0;
+}
+
+/*
+ * Setting PHY when card is working in High Speed Mode.
+ * HS400 set data strobe line.
+ * HS200/SDR104 set tuning config to prepare for tuning.
+ */
+static int xenon_hs_delay_adj(struct sdhci_host *host)
+{
+	int ret = 0;
+
+	if (WARN_ON(host->clock <= XENON_DEFAULT_SDCLK_FREQ))
+		return -EINVAL;
+
+	if (host->timing == MMC_TIMING_MMC_HS400) {
+		emmc_phy_strobe_delay_adj(host);
+		return 0;
+	}
+
+	if ((host->timing == MMC_TIMING_MMC_HS200) ||
+	    (host->timing == MMC_TIMING_UHS_SDR104))
+		return emmc_phy_config_tuning(host);
+
+	/*
+	 * DDR Mode requires driver to scan Sampling Fixed Delay Line,
+	 * to find out a perfect operation sampling point.
+	 * It is hard to implement such a scan in host driver since initiating
+	 * commands by host driver is not safe.
+	 * Thus so far just keep PHY Sampling Fixed Delay in default value
+	 * in DDR mode.
+	 *
+	 * If any timing issue occurs in DDR mode on Marvell products,
+	 * please contact maintainer to ask for internal support in Marvell.
+	 */
+	if ((host->timing == MMC_TIMING_MMC_DDR52) ||
+	    (host->timing == MMC_TIMING_UHS_DDR50))
+		dev_warn_once(mmc_dev(host->mmc), "Timing issue might occur in DDR mode\n");
+	return ret;
+}
+
+/*
+ * Adjust PHY setting.
+ * PHY setting should be adjusted when SDCLK frequency, Bus Width
+ * or Speed Mode is changed.
+ * Additional config are required when card is working in High Speed mode,
+ * after leaving Legacy Mode.
+ */
+int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	int ret = 0;
+
+	if (!host->clock) {
+		priv->clock = 0;
+		return 0;
+	}
+
+	/*
+	 * The timing, frequency or bus width is changed,
+	 * better to set eMMC PHY based on current setting
+	 * and adjust Xenon SDHC delay.
+	 */
+	if ((host->clock == priv->clock) &&
+	    (ios->bus_width == priv->bus_width) &&
+	    (ios->timing == priv->timing))
+		return 0;
+
+	emmc_phy_set(host, ios->timing);
+
+	/* Update the record */
+	priv->bus_width = ios->bus_width;
+
+	priv->timing = ios->timing;
+	priv->clock = host->clock;
+
+	/* Legacy mode is a special case */
+	if (ios->timing == MMC_TIMING_LEGACY)
+		return 0;
+
+	if (host->clock > XENON_DEFAULT_SDCLK_FREQ)
+		ret = xenon_hs_delay_adj(host);
+	return ret;
+}
+
+static void clean_emmc_phy(struct sdhci_xenon_priv *priv)
+{
+	kfree(priv->phy_params);
+}
+
+static int add_xenon_phy(struct device_node *np, struct sdhci_host *host,
+			 const char *phy_name)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	int i, ret;
+
+	for (i = 0; i < NR_PHY_TYPES; i++) {
+		if (!strcmp(phy_name, phy_types[i])) {
+			priv->phy_type = i;
+			break;
+		}
+	}
+	if (i == NR_PHY_TYPES) {
+		dev_err(mmc_dev(host->mmc),
+			"Unable to determine PHY name %s. Use default eMMC 5.1 PHY\n",
+			phy_name);
+		priv->phy_type = EMMC_5_1_PHY;
+	}
+
+	ret = alloc_emmc_phy(priv);
+	if (ret)
+		return ret;
+
+	ret = emmc_phy_parse_param_dt(host, np, priv->phy_params);
+	if (ret)
+		clean_emmc_phy(priv);
+
+	return ret;
+}
+
+int xenon_phy_parse_dt(struct device_node *np, struct sdhci_host *host)
+{
+	const char *phy_type = NULL;
+
+	if (!of_property_read_string(np, "marvell,xenon-phy-type", &phy_type))
+		return add_xenon_phy(np, host, phy_type);
+
+	dev_info(mmc_dev(host->mmc), "Fail to get Xenon PHY type. Use default eMMC 5.1 PHY\n");
+	return add_xenon_phy(np, host, "emmc 5.1 phy");
+}
diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
index e633f803907a..99c18cad6460 100644
--- a/drivers/mmc/host/sdhci-xenon.c
+++ b/drivers/mmc/host/sdhci-xenon.c
@@ -260,6 +260,7 @@ static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 	spin_unlock_irqrestore(&host->lock, flags);
 
 	sdhci_set_ios(mmc, ios);
+	xenon_phy_adj(host, ios);
 
 	if (host->clock > XENON_DEFAULT_SDCLK_FREQ) {
 		spin_lock_irqsave(&host->lock, flags);
@@ -465,7 +466,7 @@ static int xenon_probe_dt(struct platform_device *pdev)
 	}
 	priv->tuning_count = tuning_count;
 
-	return 0;
+	return xenon_phy_parse_dt(np, host);
 }
 
 static int xenon_sdhc_probe(struct sdhci_host *host)
diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h
index 69de711db9eb..e87639774bca 100644
--- a/drivers/mmc/host/sdhci-xenon.h
+++ b/drivers/mmc/host/sdhci-xenon.h
@@ -24,7 +24,17 @@
 #define XENON_SYS_EXT_OP_CTRL			0x010C
 #define XENON_MASK_CMD_CONFLICT_ERR		BIT(8)
 
+#define XENON_SLOT_OP_STATUS_CTRL		0x0128
+
+#define XENON_TUN_CONSECUTIVE_TIMES_SHIFT	16
+#define XENON_TUN_CONSECUTIVE_TIMES_MASK	0x7
+#define XENON_TUN_CONSECUTIVE_TIMES		0x4
+#define XENON_TUNING_STEP_SHIFT			12
+#define XENON_TUNING_STEP_MASK			0xF
+#define XENON_TUNING_STEP_DIVIDER		BIT(6)
+
 #define XENON_SLOT_EMMC_CTRL			0x0130
+#define XENON_ENABLE_DATA_STROBE		BIT(24)
 #define XENON_EMMC_VCCQ_MASK			0x3
 #define XENON_EMMC_VCCQ_1_8V			0x1
 #define XENON_EMMC_VCCQ_3_3V			0x3
@@ -33,11 +43,17 @@
 /* retuning compatible */
 #define XENON_RETUNING_COMPATIBLE		0x1
 
+#define XENON_SLOT_EXT_PRESENT_STATE		0x014C
+#define XENON_DLL_LOCK_STATE			0x1
+
+#define XENON_SLOT_DLL_CUR_DLY_VAL		0x0150
+
 /* Tuning Parameter */
 #define XENON_TMR_RETUN_NO_PRESENT		0xF
 #define XENON_DEF_TUNING_COUNT			0x9
 
 #define XENON_DEFAULT_SDCLK_FREQ		400000
+#define XENON_LOWEST_SDCLK_FREQ			100000
 
 /* Xenon specific Mode Select value */
 #define XENON_CTRL_HS200			0x5
@@ -65,6 +81,27 @@ struct sdhci_xenon_priv {
 	 * initialization completes.
 	 */
 	unsigned int	init_card_type;
+
+	/*
+	 * The bus_width, timing, and clock fields in below
+	 * record the current ios setting of Xenon SDHC.
+	 * Driver will adjust PHY setting if any change to
+	 * ios affects PHY timing.
+	 */
+	unsigned char	bus_width;
+	unsigned char	timing;
+	unsigned int	clock;
+
+	int		phy_type;
+	/*
+	 * Contains board-specific PHY parameters
+	 * passed from device tree.
+	 */
+	void		*phy_params;
+	struct xenon_emmc_phy_regs *emmc_phy_regs;
 };
 
+int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios);
+int xenon_phy_parse_dt(struct device_node *np,
+		       struct sdhci_host *host);
 #endif
-- 
git-series 0.9.1

Re: [PATCH v6 09/14] mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC

[Ulf Hansson]

On 14 February 2017 at 18:01, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:
> From: Hu Ziji <huziji@marvell.com>
>
> Marvell Xenon eMMC/SD/SDIO Host Controller contains PHY.
> Multiple types of PHYs are supported.
>
> Add support to multiple types of PHYs init and configuration.
> Add register definitions of PHYs.
>
> Xenon PHY cannot fit in kernel common PHY framework.
> Xenon SDHC PHY register is a part of Xenon SDHC register set.
> Besides, MMC initialization has to call several PHY functions to
> complete timing setting.
> Those PHY setting functions have to access SDHC registers and know
> current MMC setting, such as bus width, clock frequency and
> speed mode.
> As a result, implement Xenon PHY in MMC host directory.
>
> Signed-off-by: Hu Ziji <huziji@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
>  drivers/mmc/host/Makefile          |   2 +-
>  drivers/mmc/host/sdhci-xenon-phy.c | 751 ++++++++++++++++++++++++++++++-
>  drivers/mmc/host/sdhci-xenon.c     |   3 +-
>  drivers/mmc/host/sdhci-xenon.h     |  37 +-
>  4 files changed, 791 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/mmc/host/sdhci-xenon-phy.c

I see, you put the phy implementation in a separate file. I guess that
makes sense. However, I leave the decision for Adrian.

Anyway, in such case I guess the extended Makefile options and the
separate header files makes sense.

>
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index b0a2ab4b256e..893b48db5513 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -84,4 +84,4 @@ ifeq ($(CONFIG_CB710_DEBUG),y)
>  endif
>
>  obj-$(CONFIG_MMC_SDHCI_XENON)  += sdhci-xenon-driver.o
> -sdhci-xenon-driver-y           += sdhci-xenon.o
> +sdhci-xenon-driver-y           += sdhci-xenon.o sdhci-xenon-phy.o
> diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c
> new file mode 100644
> index 000000000000..c26ba3a180a0
> --- /dev/null
> +++ b/drivers/mmc/host/sdhci-xenon-phy.c

[...]

> +/*
> + * eMMC PHY configuration and operations
> + */
> +struct emmc_phy_params {

Perhaps prefix the struct name with "xenon_".

> +       bool    slow_mode;
> +
> +       u8      znr;
> +       u8      zpr;
> +
> +       /* Nr of consecutive Sampling Points of a Valid Sampling Window */
> +       u8      nr_tun_times;
> +       /* Divider for calculating Tuning Step */
> +       u8      tun_step_divider;
> +};
> +
> +static int alloc_emmc_phy(struct sdhci_xenon_priv *priv)
> +{
> +       struct emmc_phy_params *params;
> +
> +       params = kzalloc(sizeof(*params), GFP_KERNEL);

Why not using devm_kzalloc()?

[...]

> +
> +/*
> + * If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz)
> + * in SDR mode, enable Slow Mode to bypass eMMC PHY.
> + * SDIO slower SDR mode also requires Slow Mode.
> + *
> + * If Slow Mode is enabled, return true.
> + * Otherwise, return false.
> + */
> +static bool emmc_phy_slow_mode(struct sdhci_host *host,
> +                              unsigned char timing)
> +{
> +       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +       struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +       struct emmc_phy_params *params = priv->phy_params;
> +       struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
> +       u32 reg;
> +
> +       if (host->clock > MMC_HIGH_52_MAX_DTR)
> +               return false;
> +
> +       reg = sdhci_readl(host, phy_regs->timing_adj);
> +       /* Enable Slow Mode for SDIO in slower SDR mode */
> +       if ((priv->init_card_type == MMC_TYPE_SDIO) &&
> +           ((timing == MMC_TIMING_UHS_SDR25) ||
> +            (timing == MMC_TIMING_UHS_SDR12) ||
> +            (timing == MMC_TIMING_SD_HS))) {
> +               reg |= XENON_TIMING_ADJUST_SLOW_MODE;
> +               sdhci_writel(host, reg, phy_regs->timing_adj);
> +               return true;
> +       }
> +
> +       /* Check if Slow Mode is required in lower speed mode in SDR mode */
> +       if (((timing == MMC_TIMING_UHS_SDR25) ||
> +            (timing == MMC_TIMING_UHS_SDR12) ||
> +            (timing == MMC_TIMING_SD_HS) ||
> +            (timing == MMC_TIMING_MMC_HS)) && params->slow_mode) {
> +               reg |= XENON_TIMING_ADJUST_SLOW_MODE;
> +               sdhci_writel(host, reg, phy_regs->timing_adj);
> +               return true;
> +       }
> +

Two quite similar if statement. Can you perhaps combine them to avoid
code duplication.

> +       reg &= ~XENON_TIMING_ADJUST_SLOW_MODE;
> +       sdhci_writel(host, reg, phy_regs->timing_adj);
> +       return false;
> +}
> +
> +/*
> + * Set-up eMMC 5.0/5.1 PHY.
> + * Specific configuration depends on the current speed mode in use.
> + */
> +static void emmc_phy_set(struct sdhci_host *host,
> +                        unsigned char timing)
> +{
> +       u32 reg;
> +       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +       struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +       struct emmc_phy_params *params = priv->phy_params;
> +       struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
> +       unsigned long flags;
> +
> +       dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting starts\n");
> +
> +       spin_lock_irqsave(&host->lock, flags);
> +
> +       /* Setup pad, set bit[28] and bits[26:24] */
> +       reg = sdhci_readl(host, phy_regs->pad_ctrl);
> +       reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN |
> +               XENON_FC_QSP_RECEN | XENON_OEN_QSN);
> +       /* All FC_XX_RECEIVCE should be set as CMOS Type */
> +       reg |= XENON_FC_ALL_CMOS_RECEIVER;
> +       sdhci_writel(host, reg, phy_regs->pad_ctrl);
> +
> +       /* Set CMD and DQ Pull Up */
> +       if (priv->phy_type == EMMC_5_0_PHY) {
> +               reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
> +               reg |= (XENON_EMMC5_FC_CMD_PU | XENON_EMMC5_FC_DQ_PU);
> +               reg &= ~(XENON_EMMC5_FC_CMD_PD | XENON_EMMC5_FC_DQ_PD);
> +               sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
> +       } else {
> +               reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
> +               reg |= (XENON_EMMC5_1_FC_CMD_PU | XENON_EMMC5_1_FC_DQ_PU);
> +               reg &= ~(XENON_EMMC5_1_FC_CMD_PD | XENON_EMMC5_1_FC_DQ_PD);
> +               sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
> +       }
> +
> +       if (timing == MMC_TIMING_LEGACY) {
> +               /*
> +                * If Slow Mode is required, enable Slow Mode by default
> +                * in early init phase to avoid any potential issue.
> +                */
> +               if (params->slow_mode) {
> +                       reg = sdhci_readl(host, phy_regs->timing_adj);
> +                       reg |= XENON_TIMING_ADJUST_SLOW_MODE;
> +                       sdhci_writel(host, reg, phy_regs->timing_adj);
> +               }
> +               goto phy_init;
> +       }
> +
> +       /*
> +        * FIXME: should depends on the specific board timing.
> +        */
> +       if ((timing == MMC_TIMING_MMC_HS400) ||
> +           (timing == MMC_TIMING_MMC_HS200) ||
> +           (timing == MMC_TIMING_UHS_SDR50) ||
> +           (timing == MMC_TIMING_UHS_SDR104) ||
> +           (timing == MMC_TIMING_UHS_DDR50) ||
> +           (timing == MMC_TIMING_UHS_SDR25) ||
> +           (timing == MMC_TIMING_MMC_DDR52)) {
> +               reg = sdhci_readl(host, phy_regs->timing_adj);
> +               reg &= ~XENON_OUTPUT_QSN_PHASE_SELECT;
> +               sdhci_writel(host, reg, phy_regs->timing_adj);
> +       }
> +
> +       /*
> +        * If SDIO card, set SDIO Mode
> +        * Otherwise, clear SDIO Mode
> +        */
> +       reg = sdhci_readl(host, phy_regs->timing_adj);
> +       if (priv->init_card_type == MMC_TYPE_SDIO)
> +               reg |= XENON_TIMING_ADJUST_SDIO_MODE;
> +       else
> +               reg &= ~XENON_TIMING_ADJUST_SDIO_MODE;
> +       sdhci_writel(host, reg, phy_regs->timing_adj);
> +
> +       if (emmc_phy_slow_mode(host, timing))
> +               goto phy_init;
> +
> +       /*
> +        * Set preferred ZNR and ZPR value
> +        * The ZNR and ZPR value vary between different boards.
> +        * Define them both in sdhci-xenon-emmc-phy.h.
> +        */
> +       reg = sdhci_readl(host, phy_regs->pad_ctrl2);
> +       reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK);
> +       reg |= ((params->znr << XENON_ZNR_SHIFT) | params->zpr);
> +       sdhci_writel(host, reg, phy_regs->pad_ctrl2);
> +
> +       /*
> +        * When setting EMMC_PHY_FUNC_CONTROL register,
> +        * SD clock should be disabled
> +        */
> +       reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
> +       reg &= ~SDHCI_CLOCK_CARD_EN;
> +       sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
> +
> +       reg = sdhci_readl(host, phy_regs->func_ctrl);
> +       if ((timing == MMC_TIMING_UHS_DDR50) ||
> +           (timing == MMC_TIMING_MMC_HS400) ||
> +           (timing == MMC_TIMING_MMC_DDR52))
> +               reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
> +                      XENON_CMD_DDR_MODE;
> +       else
> +               reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
> +                        XENON_CMD_DDR_MODE);
> +
> +       if (timing == MMC_TIMING_MMC_HS400)
> +               reg &= ~XENON_DQ_ASYNC_MODE;
> +       else
> +               reg |= XENON_DQ_ASYNC_MODE;
> +       sdhci_writel(host, reg, phy_regs->func_ctrl);
> +
> +       /* Enable bus clock */
> +       reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
> +       reg |= SDHCI_CLOCK_CARD_EN;
> +       sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
> +
> +       if (timing == MMC_TIMING_MMC_HS400)
> +               /* Hardware team recommend a value for HS400 */
> +               sdhci_writel(host, XENON_LOGIC_TIMING_VALUE,
> +                            phy_regs->logic_timing_adj);
> +       else
> +               __emmc_phy_disable_data_strobe(host);
> +
> +phy_init:
> +       emmc_phy_init(host);
> +
> +       spin_unlock_irqrestore(&host->lock, flags);
> +
> +       dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n");

Again you are checking the MMC_TIMING_* in several if statements.
Perhaps you can use switch statement instead and build a couple of
different register variables, that you use when reading/writing
afterwards.

> +}
> +
> +static int emmc_phy_parse_param_dt(struct sdhci_host *host,
> +                                  struct device_node *np,
> +                                  struct emmc_phy_params *params)
> +{
> +       u32 value;
> +
> +       if (of_property_read_bool(np, "marvell,xenon-phy-slow-mode"))
> +               params->slow_mode = true;
> +       else
> +               params->slow_mode = false;
> +
> +       if (!of_property_read_u32(np, "marvell,xenon-phy-znr", &value))
> +               params->znr = value & XENON_ZNR_MASK;
> +       else
> +               params->znr = XENON_ZNR_DEF_VALUE;
> +
> +       if (!of_property_read_u32(np, "marvell,xenon-phy-zpr", &value))
> +               params->zpr = value & XENON_ZPR_MASK;
> +       else
> +               params->zpr = XENON_ZPR_DEF_VALUE;
> +
> +       if (!of_property_read_u32(np, "marvell,xenon-phy-nr-success-tun",
> +                                 &value))
> +               params->nr_tun_times = value & XENON_TUN_CONSECUTIVE_TIMES_MASK;
> +       else
> +               params->nr_tun_times = XENON_TUN_CONSECUTIVE_TIMES;
> +
> +       if (!of_property_read_u32(np, "marvell,xenon-phy-tun-step-divider",
> +                                 &value))
> +               params->tun_step_divider = value & 0xFF;
> +       else
> +               params->tun_step_divider = XENON_TUNING_STEP_DIVIDER;
> +
> +       return 0;

Instead of all these if-else, let's start by assigning default values
instead. This makes the code more readable.

> +}
> +
> +/*
> + * Setting PHY when card is working in High Speed Mode.
> + * HS400 set data strobe line.
> + * HS200/SDR104 set tuning config to prepare for tuning.
> + */
> +static int xenon_hs_delay_adj(struct sdhci_host *host)
> +{
> +       int ret = 0;
> +
> +       if (WARN_ON(host->clock <= XENON_DEFAULT_SDCLK_FREQ))
> +               return -EINVAL;
> +
> +       if (host->timing == MMC_TIMING_MMC_HS400) {
> +               emmc_phy_strobe_delay_adj(host);
> +               return 0;
> +       }
> +
> +       if ((host->timing == MMC_TIMING_MMC_HS200) ||
> +           (host->timing == MMC_TIMING_UHS_SDR104))
> +               return emmc_phy_config_tuning(host);
> +
> +       /*
> +        * DDR Mode requires driver to scan Sampling Fixed Delay Line,
> +        * to find out a perfect operation sampling point.
> +        * It is hard to implement such a scan in host driver since initiating
> +        * commands by host driver is not safe.
> +        * Thus so far just keep PHY Sampling Fixed Delay in default value
> +        * in DDR mode.
> +        *
> +        * If any timing issue occurs in DDR mode on Marvell products,
> +        * please contact maintainer to ask for internal support in Marvell.
> +        */
> +       if ((host->timing == MMC_TIMING_MMC_DDR52) ||
> +           (host->timing == MMC_TIMING_UHS_DDR50))
> +               dev_warn_once(mmc_dev(host->mmc), "Timing issue might occur in DDR mode\n");

Please consider a to convert to use a switch statment instead of the
several if statements.

> +       return ret;
> +}
> +

[...]

> +
> +static int add_xenon_phy(struct device_node *np, struct sdhci_host *host,
> +                        const char *phy_name)
> +{
> +       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +       struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +       int i, ret;
> +
> +       for (i = 0; i < NR_PHY_TYPES; i++) {
> +               if (!strcmp(phy_name, phy_types[i])) {
> +                       priv->phy_type = i;
> +                       break;
> +               }
> +       }
> +       if (i == NR_PHY_TYPES) {
> +               dev_err(mmc_dev(host->mmc),
> +                       "Unable to determine PHY name %s. Use default eMMC 5.1 PHY\n",
> +                       phy_name);
> +               priv->phy_type = EMMC_5_1_PHY;
> +       }
> +
> +       ret = alloc_emmc_phy(priv);
> +       if (ret)
> +               return ret;
> +
> +       ret = emmc_phy_parse_param_dt(host, np, priv->phy_params);
> +       if (ret)
> +               clean_emmc_phy(priv);
> +
> +       return ret;
> +}
> +
> +int xenon_phy_parse_dt(struct device_node *np, struct sdhci_host *host)
> +{
> +       const char *phy_type = NULL;
> +
> +       if (!of_property_read_string(np, "marvell,xenon-phy-type", &phy_type))
> +               return add_xenon_phy(np, host, phy_type);
> +
> +       dev_info(mmc_dev(host->mmc), "Fail to get Xenon PHY type. Use default eMMC 5.1 PHY\n");

Isn't there already a dev_err() being printed for this case. You
probably only need one.

> +       return add_xenon_phy(np, host, "emmc 5.1 phy");
> +}

[...]

Kind regards
Uffe

Re: [PATCH v6 09/14] mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC

[Ziji Hu]

Hi Ulf,

On 2017/3/15 21:39, Ulf Hansson wrote:
> On 14 February 2017 at 18:01, Gregory CLEMENT
> <gregory.clement@free-electrons.com> wrote:
>> From: Hu Ziji <huziji@marvell.com>
>>
<snip>
>> +
>> +       /*
>> +        * FIXME: should depends on the specific board timing.
>> +        */
>> +       if ((timing == MMC_TIMING_MMC_HS400) ||
>> +           (timing == MMC_TIMING_MMC_HS200) ||
>> +           (timing == MMC_TIMING_UHS_SDR50) ||
>> +           (timing == MMC_TIMING_UHS_SDR104) ||
>> +           (timing == MMC_TIMING_UHS_DDR50) ||
>> +           (timing == MMC_TIMING_UHS_SDR25) ||
>> +           (timing == MMC_TIMING_MMC_DDR52)) {
>> +               reg = sdhci_readl(host, phy_regs->timing_adj);
>> +               reg &= ~XENON_OUTPUT_QSN_PHASE_SELECT;
>> +               sdhci_writel(host, reg, phy_regs->timing_adj);
>> +       }
>> +
<snip>
>> +
>> +       reg = sdhci_readl(host, phy_regs->func_ctrl);
>> +       if ((timing == MMC_TIMING_UHS_DDR50) ||
>> +           (timing == MMC_TIMING_MMC_HS400) ||
>> +           (timing == MMC_TIMING_MMC_DDR52))
>> +               reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
>> +                      XENON_CMD_DDR_MODE;
>> +       else
>> +               reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
>> +                        XENON_CMD_DDR_MODE);
<snip>
> 
> Again you are checking the MMC_TIMING_* in several if statements.
> Perhaps you can use switch statement instead and build a couple of
> different register variables, that you use when reading/writing
> afterwards.
> 

	Sorry. I don't quite understand your comment.
	Do you mean combine all the related  register settings
	under a specific MMC_TIMING_*?

	swhich (timing) {
	case MMC_TIMING_HS400:
		config reg_1;
		config reg_2;
		...
	case MMC_TIMING_HS200:
		config reg_2;
		config reg_3
		..
	case ...
	};

	I have a little concern that there might be a lot
	of duplicate register settings. Some PHY operations are
	irrelevant to the speed mode. They have to be executed in
	a particular sequence in all speed modes.

>> +}
>> +
>> +static int emmc_phy_parse_param_dt(struct sdhci_host *host,
>> +                                  struct device_node *np,
>> +                                  struct emmc_phy_params *params)
>> +{
>> +       u32 value;
>> +
>> +       if (of_property_read_bool(np, "marvell,xenon-phy-slow-mode"))
>> +               params->slow_mode = true;
>> +       else
>> +               params->slow_mode = false;
>> +
>> +       if (!of_property_read_u32(np, "marvell,xenon-phy-znr", &value))
>> +               params->znr = value & XENON_ZNR_MASK;
>> +       else
>> +               params->znr = XENON_ZNR_DEF_VALUE;
>> +
>> +       if (!of_property_read_u32(np, "marvell,xenon-phy-zpr", &value))
>> +               params->zpr = value & XENON_ZPR_MASK;
>> +       else
>> +               params->zpr = XENON_ZPR_DEF_VALUE;
>> +
>> +       if (!of_property_read_u32(np, "marvell,xenon-phy-nr-success-tun",
>> +                                 &value))
>> +               params->nr_tun_times = value & XENON_TUN_CONSECUTIVE_TIMES_MASK;
>> +       else
>> +               params->nr_tun_times = XENON_TUN_CONSECUTIVE_TIMES;
>> +
>> +       if (!of_property_read_u32(np, "marvell,xenon-phy-tun-step-divider",
>> +                                 &value))
>> +               params->tun_step_divider = value & 0xFF;
>> +       else
>> +               params->tun_step_divider = XENON_TUNING_STEP_DIVIDER;
>> +
>> +       return 0;
> 
> Instead of all these if-else, let's start by assigning default values
> instead. This makes the code more readable.
> 
	Sure. I'll change it.
	
>> +}
>> +
>> +/*
>> + * Setting PHY when card is working in High Speed Mode.
>> + * HS400 set data strobe line.
>> + * HS200/SDR104 set tuning config to prepare for tuning.
>> + */
>> +static int xenon_hs_delay_adj(struct sdhci_host *host)
>> +{
>> +       int ret = 0;
>> +
>> +       if (WARN_ON(host->clock <= XENON_DEFAULT_SDCLK_FREQ))
>> +               return -EINVAL;
>> +
>> +       if (host->timing == MMC_TIMING_MMC_HS400) {
>> +               emmc_phy_strobe_delay_adj(host);
>> +               return 0;
>> +       }
>> +
>> +       if ((host->timing == MMC_TIMING_MMC_HS200) ||
>> +           (host->timing == MMC_TIMING_UHS_SDR104))
>> +               return emmc_phy_config_tuning(host);
>> +
>> +       /*
>> +        * DDR Mode requires driver to scan Sampling Fixed Delay Line,
>> +        * to find out a perfect operation sampling point.
>> +        * It is hard to implement such a scan in host driver since initiating
>> +        * commands by host driver is not safe.
>> +        * Thus so far just keep PHY Sampling Fixed Delay in default value
>> +        * in DDR mode.
>> +        *
>> +        * If any timing issue occurs in DDR mode on Marvell products,
>> +        * please contact maintainer to ask for internal support in Marvell.
>> +        */
>> +       if ((host->timing == MMC_TIMING_MMC_DDR52) ||
>> +           (host->timing == MMC_TIMING_UHS_DDR50))
>> +               dev_warn_once(mmc_dev(host->mmc), "Timing issue might occur in DDR mode\n");
> 
> Please consider a to convert to use a switch statment instead of the
> several if statements.
> 

	It is a good idea to use switch here.

>> +       return ret;
>> +}
>> +
> 
<snip>
>> +int xenon_phy_parse_dt(struct device_node *np, struct sdhci_host *host)
>> +{
>> +       const char *phy_type = NULL;
>> +
>> +       if (!of_property_read_string(np, "marvell,xenon-phy-type", &phy_type))
>> +               return add_xenon_phy(np, host, phy_type);
>> +
>> +       dev_info(mmc_dev(host->mmc), "Fail to get Xenon PHY type. Use default eMMC 5.1 PHY\n");
> 
> Isn't there already a dev_err() being printed for this case. You
> probably only need one.

	By default, "emmc 5.1 phy" is used on most of our products.
	Thus this dt property is an optional one.
	I can remove this dev_info.

> 
>> +       return add_xenon_phy(np, host, "emmc 5.1 phy");
>> +}
> 
> [...]
> 
> Kind regards
> Uffe
> 

Re: [PATCH v6 09/14] mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC

[Adrian Hunter]

On 14/02/17 19:01, Gregory CLEMENT wrote:
> From: Hu Ziji <huziji@marvell.com>
> 
> Marvell Xenon eMMC/SD/SDIO Host Controller contains PHY.
> Multiple types of PHYs are supported.
> 
> Add support to multiple types of PHYs init and configuration.
> Add register definitions of PHYs.
> 
> Xenon PHY cannot fit in kernel common PHY framework.
> Xenon SDHC PHY register is a part of Xenon SDHC register set.
> Besides, MMC initialization has to call several PHY functions to
> complete timing setting.
> Those PHY setting functions have to access SDHC registers and know
> current MMC setting, such as bus width, clock frequency and
> speed mode.
> As a result, implement Xenon PHY in MMC host directory.
> 
> Signed-off-by: Hu Ziji <huziji@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

A couple of minor comments below.

> ---
>  drivers/mmc/host/Makefile          |   2 +-
>  drivers/mmc/host/sdhci-xenon-phy.c | 751 ++++++++++++++++++++++++++++++-
>  drivers/mmc/host/sdhci-xenon.c     |   3 +-
>  drivers/mmc/host/sdhci-xenon.h     |  37 +-
>  4 files changed, 791 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/mmc/host/sdhci-xenon-phy.c
> 
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index b0a2ab4b256e..893b48db5513 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -84,4 +84,4 @@ ifeq ($(CONFIG_CB710_DEBUG),y)
>  endif
>  
>  obj-$(CONFIG_MMC_SDHCI_XENON)	+= sdhci-xenon-driver.o
> -sdhci-xenon-driver-y		+= sdhci-xenon.o
> +sdhci-xenon-driver-y		+= sdhci-xenon.o sdhci-xenon-phy.o
> diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c
> new file mode 100644
> index 000000000000..c26ba3a180a0
> --- /dev/null
> +++ b/drivers/mmc/host/sdhci-xenon-phy.c
> @@ -0,0 +1,751 @@
> +/*
> + * PHY support for Xenon SDHC
> + *
> + * Copyright (C) 2016 Marvell, All Rights Reserved.
> + *
> + * Author:	Hu Ziji <huziji@marvell.com>
> + * Date:	2016-8-24
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + */
> +
> +#include <linux/slab.h>
> +#include <linux/delay.h>
> +#include <linux/of_address.h>
> +
> +#include "sdhci-pltfm.h"
> +#include "sdhci-xenon.h"
> +
> +/* Register base for eMMC PHY 5.0 Version */
> +#define XENON_EMMC_5_0_PHY_REG_BASE		0x0160
> +/* Register base for eMMC PHY 5.1 Version */
> +#define XENON_EMMC_PHY_REG_BASE			0x0170
> +
> +#define XENON_EMMC_PHY_TIMING_ADJUST		XENON_EMMC_PHY_REG_BASE
> +#define XENON_EMMC_5_0_PHY_TIMING_ADJUST	XENON_EMMC_5_0_PHY_REG_BASE
> +#define XENON_TIMING_ADJUST_SLOW_MODE		BIT(29)
> +#define XENON_TIMING_ADJUST_SDIO_MODE		BIT(28)
> +#define XENON_OUTPUT_QSN_PHASE_SELECT		BIT(17)
> +#define XENON_SAMPL_INV_QSP_PHASE_SELECT	BIT(18)
> +#define XENON_SAMPL_INV_QSP_PHASE_SELECT_SHIFT	18
> +#define XENON_PHY_INITIALIZAION			BIT(31)
> +#define XENON_WAIT_CYCLE_BEFORE_USING_MASK	0xF
> +#define XENON_WAIT_CYCLE_BEFORE_USING_SHIFT	12
> +#define XENON_FC_SYNC_EN_DURATION_MASK		0xF
> +#define XENON_FC_SYNC_EN_DURATION_SHIFT		8
> +#define XENON_FC_SYNC_RST_EN_DURATION_MASK	0xF
> +#define XENON_FC_SYNC_RST_EN_DURATION_SHIFT	4
> +#define XENON_FC_SYNC_RST_DURATION_MASK		0xF
> +#define XENON_FC_SYNC_RST_DURATION_SHIFT	0
> +
> +#define XENON_EMMC_PHY_FUNC_CONTROL		(XENON_EMMC_PHY_REG_BASE + 0x4)
> +#define XENON_EMMC_5_0_PHY_FUNC_CONTROL		\
> +	(XENON_EMMC_5_0_PHY_REG_BASE + 0x4)
> +#define XENON_ASYNC_DDRMODE_MASK		BIT(23)
> +#define XENON_ASYNC_DDRMODE_SHIFT		23
> +#define XENON_CMD_DDR_MODE			BIT(16)
> +#define XENON_DQ_DDR_MODE_SHIFT			8
> +#define XENON_DQ_DDR_MODE_MASK			0xFF
> +#define XENON_DQ_ASYNC_MODE			BIT(4)
> +
> +#define XENON_EMMC_PHY_PAD_CONTROL		(XENON_EMMC_PHY_REG_BASE + 0x8)
> +#define XENON_EMMC_5_0_PHY_PAD_CONTROL		\
> +	(XENON_EMMC_5_0_PHY_REG_BASE + 0x8)
> +#define XENON_REC_EN_SHIFT			24
> +#define XENON_REC_EN_MASK			0xF
> +#define XENON_FC_DQ_RECEN			BIT(24)
> +#define XENON_FC_CMD_RECEN			BIT(25)
> +#define XENON_FC_QSP_RECEN			BIT(26)
> +#define XENON_FC_QSN_RECEN			BIT(27)
> +#define XENON_OEN_QSN				BIT(28)
> +#define XENON_AUTO_RECEN_CTRL			BIT(30)
> +#define XENON_FC_ALL_CMOS_RECEIVER		0xF000
> +
> +#define XENON_EMMC5_FC_QSP_PD			BIT(18)
> +#define XENON_EMMC5_FC_QSP_PU			BIT(22)
> +#define XENON_EMMC5_FC_CMD_PD			BIT(17)
> +#define XENON_EMMC5_FC_CMD_PU			BIT(21)
> +#define XENON_EMMC5_FC_DQ_PD			BIT(16)
> +#define XENON_EMMC5_FC_DQ_PU			BIT(20)
> +
> +#define XENON_EMMC_PHY_PAD_CONTROL1		(XENON_EMMC_PHY_REG_BASE + 0xC)
> +#define XENON_EMMC5_1_FC_QSP_PD			BIT(9)
> +#define XENON_EMMC5_1_FC_QSP_PU			BIT(25)
> +#define XENON_EMMC5_1_FC_CMD_PD			BIT(8)
> +#define XENON_EMMC5_1_FC_CMD_PU			BIT(24)
> +#define XENON_EMMC5_1_FC_DQ_PD			0xFF
> +#define XENON_EMMC5_1_FC_DQ_PU			(0xFF << 16)
> +
> +#define XENON_EMMC_PHY_PAD_CONTROL2		(XENON_EMMC_PHY_REG_BASE + 0x10)
> +#define XENON_EMMC_5_0_PHY_PAD_CONTROL2		\
> +	(XENON_EMMC_5_0_PHY_REG_BASE + 0xC)
> +#define XENON_ZNR_MASK				0x1F
> +#define XENON_ZNR_SHIFT				8
> +#define XENON_ZPR_MASK				0x1F
> +/* Preferred ZNR and ZPR value vary between different boards.
> + * The specific ZNR and ZPR value should be defined here
> + * according to board actual timing.
> + */
> +#define XENON_ZNR_DEF_VALUE			0xF
> +#define XENON_ZPR_DEF_VALUE			0xF
> +
> +#define XENON_EMMC_PHY_DLL_CONTROL		(XENON_EMMC_PHY_REG_BASE + 0x14)
> +#define XENON_EMMC_5_0_PHY_DLL_CONTROL		\
> +	(XENON_EMMC_5_0_PHY_REG_BASE + 0x10)
> +#define XENON_DLL_ENABLE			BIT(31)
> +#define XENON_DLL_UPDATE_STROBE_5_0		BIT(30)
> +#define XENON_DLL_REFCLK_SEL			BIT(30)
> +#define XENON_DLL_UPDATE			BIT(23)
> +#define XENON_DLL_PHSEL1_SHIFT			24
> +#define XENON_DLL_PHSEL0_SHIFT			16
> +#define XENON_DLL_PHASE_MASK			0x3F
> +#define XENON_DLL_PHASE_90_DEGREE		0x1F
> +#define XENON_DLL_FAST_LOCK			BIT(5)
> +#define XENON_DLL_GAIN2X			BIT(3)
> +#define XENON_DLL_BYPASS_EN			BIT(0)
> +
> +#define XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST	\
> +	(XENON_EMMC_5_0_PHY_REG_BASE + 0x14)
> +#define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST	(XENON_EMMC_PHY_REG_BASE + 0x18)
> +#define XENON_LOGIC_TIMING_VALUE		0x00AA8977
> +
> +/*
> + * List offset of PHY registers and some special register values
> + * in eMMC PHY 5.0 or eMMC PHY 5.1
> + */
> +struct xenon_emmc_phy_regs {
> +	/* Offset of Timing Adjust register */
> +	u16 timing_adj;
> +	/* Offset of Func Control register */
> +	u16 func_ctrl;
> +	/* Offset of Pad Control register */
> +	u16 pad_ctrl;
> +	/* Offset of Pad Control register 2 */
> +	u16 pad_ctrl2;
> +	/* Offset of DLL Control register */
> +	u16 dll_ctrl;
> +	/* Offset of Logic Timing Adjust register */
> +	u16 logic_timing_adj;
> +	/* DLL Update Enable bit */
> +	u32 dll_update;
> +};
> +
> +static const char * const phy_types[] = {
> +	"emmc 5.0 phy",
> +	"emmc 5.1 phy"
> +};
> +
> +enum phy_type_enum {
> +	EMMC_5_0_PHY,
> +	EMMC_5_1_PHY,
> +	NR_PHY_TYPES
> +};
> +
> +static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = {
> +	.timing_adj	= XENON_EMMC_5_0_PHY_TIMING_ADJUST,
> +	.func_ctrl	= XENON_EMMC_5_0_PHY_FUNC_CONTROL,
> +	.pad_ctrl	= XENON_EMMC_5_0_PHY_PAD_CONTROL,
> +	.pad_ctrl2	= XENON_EMMC_5_0_PHY_PAD_CONTROL2,
> +	.dll_ctrl	= XENON_EMMC_5_0_PHY_DLL_CONTROL,
> +	.logic_timing_adj = XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST,
> +	.dll_update	= XENON_DLL_UPDATE_STROBE_5_0,
> +};
> +
> +static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs = {
> +	.timing_adj	= XENON_EMMC_PHY_TIMING_ADJUST,
> +	.func_ctrl	= XENON_EMMC_PHY_FUNC_CONTROL,
> +	.pad_ctrl	= XENON_EMMC_PHY_PAD_CONTROL,
> +	.pad_ctrl2	= XENON_EMMC_PHY_PAD_CONTROL2,
> +	.dll_ctrl	= XENON_EMMC_PHY_DLL_CONTROL,
> +	.logic_timing_adj = XENON_EMMC_PHY_LOGIC_TIMING_ADJUST,
> +	.dll_update	= XENON_DLL_UPDATE,
> +};
> +
> +/*
> + * eMMC PHY configuration and operations
> + */
> +struct emmc_phy_params {
> +	bool	slow_mode;
> +
> +	u8	znr;
> +	u8	zpr;
> +
> +	/* Nr of consecutive Sampling Points of a Valid Sampling Window */
> +	u8	nr_tun_times;
> +	/* Divider for calculating Tuning Step */
> +	u8	tun_step_divider;
> +};
> +
> +static int alloc_emmc_phy(struct sdhci_xenon_priv *priv)
> +{
> +	struct emmc_phy_params *params;
> +
> +	params = kzalloc(sizeof(*params), GFP_KERNEL);
> +	if (!params)
> +		return -ENOMEM;
> +
> +	priv->phy_params = params;

Doesn't phy_params need to be freed e.g. when sdhci_xenon_remove is called()?

> +	if (priv->phy_type == EMMC_5_0_PHY)
> +		priv->emmc_phy_regs = &xenon_emmc_5_0_phy_regs;
> +	else
> +		priv->emmc_phy_regs = &xenon_emmc_5_1_phy_regs;
> +
> +	return 0;
> +}
> +
> +/*
> + * eMMC 5.0/5.1 PHY init/re-init.
> + * eMMC PHY init should be executed after:
> + * 1. SDCLK frequency changes.
> + * 2. SDCLK is stopped and re-enabled.
> + * 3. config in emmc_phy_regs->timing_adj and emmc_phy_regs->func_ctrl
> + * are changed
> + */
> +static int emmc_phy_init(struct sdhci_host *host)
> +{
> +	u32 reg;
> +	u32 wait, clock;
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
> +
> +	reg = sdhci_readl(host, phy_regs->timing_adj);
> +	reg |= XENON_PHY_INITIALIZAION;
> +	sdhci_writel(host, reg, phy_regs->timing_adj);
> +
> +	/* Add duration of FC_SYNC_RST */
> +	wait = ((reg >> XENON_FC_SYNC_RST_DURATION_SHIFT) &
> +			XENON_FC_SYNC_RST_DURATION_MASK);
> +	/* Add interval between FC_SYNC_EN and FC_SYNC_RST */
> +	wait += ((reg >> XENON_FC_SYNC_RST_EN_DURATION_SHIFT) &
> +			XENON_FC_SYNC_RST_EN_DURATION_MASK);
> +	/* Add duration of asserting FC_SYNC_EN */
> +	wait += ((reg >> XENON_FC_SYNC_EN_DURATION_SHIFT) &
> +			XENON_FC_SYNC_EN_DURATION_MASK);
> +	/* Add duration of waiting for PHY */
> +	wait += ((reg >> XENON_WAIT_CYCLE_BEFORE_USING_SHIFT) &
> +			XENON_WAIT_CYCLE_BEFORE_USING_MASK);
> +	/* 4 additional bus clock and 4 AXI bus clock are required */
> +	wait += 8;
> +	wait <<= 20;
> +
> +	clock = host->clock;
> +	if (!clock)
> +		/* Use the possibly slowest bus frequency value */
> +		clock = XENON_LOWEST_SDCLK_FREQ;
> +	/* get the wait time */
> +	wait /= clock;
> +	wait++;
> +	/* wait for host eMMC PHY init completes */
> +	udelay(wait);
> +
> +	reg = sdhci_readl(host, phy_regs->timing_adj);
> +	reg &= XENON_PHY_INITIALIZAION;
> +	if (reg) {
> +		dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n",
> +			wait);
> +		return -ETIMEDOUT;
> +	}
> +
> +	return 0;
> +}
> +
> +/*
> + * Enable eMMC PHY HW DLL
> + * DLL should be enabled and stable before HS200/SDR104 tuning,
> + * and before HS400 data strobe setting.
> + */
> +static int emmc_phy_enable_dll(struct sdhci_host *host)
> +{
> +	u32 reg;
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
> +	u8 timeout;
> +
> +	if (WARN_ON(host->clock <= MMC_HIGH_52_MAX_DTR))
> +		return -EINVAL;
> +
> +	reg = sdhci_readl(host, phy_regs->dll_ctrl);
> +	if (reg & XENON_DLL_ENABLE)
> +		return 0;
> +
> +	/* Enable DLL */
> +	reg = sdhci_readl(host, phy_regs->dll_ctrl);
> +	reg |= (XENON_DLL_ENABLE | XENON_DLL_FAST_LOCK);
> +
> +	/*
> +	 * Set Phase as 90 degree, which is most common value.
> +	 * Might set another value if necessary.
> +	 * The granularity is 1 degree.
> +	 */
> +	reg &= ~((XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL0_SHIFT) |
> +		 (XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL1_SHIFT));
> +	reg |= ((XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL0_SHIFT) |
> +		(XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL1_SHIFT));
> +
> +	reg &= ~XENON_DLL_BYPASS_EN;
> +	reg |= phy_regs->dll_update;
> +	if (priv->phy_type == EMMC_5_1_PHY)
> +		reg &= ~XENON_DLL_REFCLK_SEL;
> +	sdhci_writel(host, reg, phy_regs->dll_ctrl);
> +
> +	/* Wait max 32 ms */
> +	timeout = 32;
> +	while (!(sdhci_readw(host, XENON_SLOT_EXT_PRESENT_STATE) &
> +		XENON_DLL_LOCK_STATE)) {
> +		if (!timeout) {
> +			dev_err(mmc_dev(host->mmc), "Wait for DLL Lock time-out\n");
> +			return -ETIMEDOUT;
> +		}
> +		timeout--;
> +		mdelay(1);
> +	}
> +	return 0;
> +}
> +
> +/*
> + * Config to eMMC PHY to prepare for tuning.
> + * Enable HW DLL and set the TUNING_STEP
> + */
> +static int emmc_phy_config_tuning(struct sdhci_host *host)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	struct emmc_phy_params *params = priv->phy_params;
> +	u32 reg, tuning_step;
> +	int ret;
> +	unsigned long flags;
> +
> +	if (host->clock <= MMC_HIGH_52_MAX_DTR)
> +		return -EINVAL;
> +
> +	spin_lock_irqsave(&host->lock, flags);

I have eliminated the spin lock from set_ios and reduced its usage in
sdhci_execute_tuning.  You might want to review whether you really need the
spin lock here and elsewhere in this file.

> +
> +	ret = emmc_phy_enable_dll(host);
> +	if (ret) {
> +		spin_unlock_irqrestore(&host->lock, flags);
> +		return ret;
> +	}
> +
> +	/* Achieve TUNING_STEP with HW DLL help */
> +	reg = sdhci_readl(host, XENON_SLOT_DLL_CUR_DLY_VAL);
> +	tuning_step = reg / params->tun_step_divider;
> +	if (unlikely(tuning_step > XENON_TUNING_STEP_MASK)) {
> +		dev_warn(mmc_dev(host->mmc),
> +			 "HS200 TUNING_STEP %d is larger than MAX value\n",
> +			 tuning_step);
> +		tuning_step = XENON_TUNING_STEP_MASK;
> +	}
> +
> +	/* Set TUNING_STEP for later tuning */
> +	reg = sdhci_readl(host, XENON_SLOT_OP_STATUS_CTRL);
> +	reg &= ~(XENON_TUN_CONSECUTIVE_TIMES_MASK <<
> +		 XENON_TUN_CONSECUTIVE_TIMES_SHIFT);
> +	reg |= (params->nr_tun_times << XENON_TUN_CONSECUTIVE_TIMES_SHIFT);
> +	reg &= ~(XENON_TUNING_STEP_MASK << XENON_TUNING_STEP_SHIFT);
> +	reg |= (tuning_step << XENON_TUNING_STEP_SHIFT);
> +	sdhci_writel(host, reg, XENON_SLOT_OP_STATUS_CTRL);
> +
> +	spin_unlock_irqrestore(&host->lock, flags);
> +	return 0;
> +}
> +
> +static void __emmc_phy_disable_data_strobe(struct sdhci_host *host)
> +{
> +	u32 reg;
> +
> +	/* Disable SDHC Data Strobe */
> +	reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
> +	reg &= ~XENON_ENABLE_DATA_STROBE;
> +	sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL);
> +}
> +
> +/* Set HS400 Data Strobe */
> +static void emmc_phy_strobe_delay_adj(struct sdhci_host *host)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	unsigned long flags;
> +	u32 reg;
> +
> +	if (WARN_ON(host->timing != MMC_TIMING_MMC_HS400))
> +		return;
> +
> +	if (host->clock <= MMC_HIGH_52_MAX_DTR)
> +		return;
> +
> +	dev_dbg(mmc_dev(host->mmc), "starts HS400 strobe delay adjustment\n");
> +
> +	spin_lock_irqsave(&host->lock, flags);
> +
> +	emmc_phy_enable_dll(host);
> +
> +	/* Enable SDHC Data Strobe */
> +	reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
> +	reg |= XENON_ENABLE_DATA_STROBE;
> +	sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL);
> +
> +	/* Set Data Strobe Pull down */
> +	if (priv->phy_type == EMMC_5_0_PHY) {
> +		reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
> +		reg |= XENON_EMMC5_FC_QSP_PD;
> +		reg &= ~XENON_EMMC5_FC_QSP_PU;
> +		sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
> +	} else {
> +		reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
> +		reg |= XENON_EMMC5_1_FC_QSP_PD;
> +		reg &= ~XENON_EMMC5_1_FC_QSP_PU;
> +		sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
> +	}
> +	spin_unlock_irqrestore(&host->lock, flags);
> +}
> +
> +/*
> + * If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz)
> + * in SDR mode, enable Slow Mode to bypass eMMC PHY.
> + * SDIO slower SDR mode also requires Slow Mode.
> + *
> + * If Slow Mode is enabled, return true.
> + * Otherwise, return false.
> + */
> +static bool emmc_phy_slow_mode(struct sdhci_host *host,
> +			       unsigned char timing)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	struct emmc_phy_params *params = priv->phy_params;
> +	struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
> +	u32 reg;
> +
> +	if (host->clock > MMC_HIGH_52_MAX_DTR)
> +		return false;
> +
> +	reg = sdhci_readl(host, phy_regs->timing_adj);
> +	/* Enable Slow Mode for SDIO in slower SDR mode */
> +	if ((priv->init_card_type == MMC_TYPE_SDIO) &&
> +	    ((timing == MMC_TIMING_UHS_SDR25) ||
> +	     (timing == MMC_TIMING_UHS_SDR12) ||
> +	     (timing == MMC_TIMING_SD_HS))) {
> +		reg |= XENON_TIMING_ADJUST_SLOW_MODE;
> +		sdhci_writel(host, reg, phy_regs->timing_adj);
> +		return true;
> +	}
> +
> +	/* Check if Slow Mode is required in lower speed mode in SDR mode */
> +	if (((timing == MMC_TIMING_UHS_SDR25) ||
> +	     (timing == MMC_TIMING_UHS_SDR12) ||
> +	     (timing == MMC_TIMING_SD_HS) ||
> +	     (timing == MMC_TIMING_MMC_HS)) && params->slow_mode) {
> +		reg |= XENON_TIMING_ADJUST_SLOW_MODE;
> +		sdhci_writel(host, reg, phy_regs->timing_adj);
> +		return true;
> +	}
> +
> +	reg &= ~XENON_TIMING_ADJUST_SLOW_MODE;
> +	sdhci_writel(host, reg, phy_regs->timing_adj);
> +	return false;
> +}
> +
> +/*
> + * Set-up eMMC 5.0/5.1 PHY.
> + * Specific configuration depends on the current speed mode in use.
> + */
> +static void emmc_phy_set(struct sdhci_host *host,
> +			 unsigned char timing)
> +{
> +	u32 reg;
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	struct emmc_phy_params *params = priv->phy_params;
> +	struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
> +	unsigned long flags;
> +
> +	dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting starts\n");
> +
> +	spin_lock_irqsave(&host->lock, flags);
> +
> +	/* Setup pad, set bit[28] and bits[26:24] */
> +	reg = sdhci_readl(host, phy_regs->pad_ctrl);
> +	reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN |
> +		XENON_FC_QSP_RECEN | XENON_OEN_QSN);
> +	/* All FC_XX_RECEIVCE should be set as CMOS Type */
> +	reg |= XENON_FC_ALL_CMOS_RECEIVER;
> +	sdhci_writel(host, reg, phy_regs->pad_ctrl);
> +
> +	/* Set CMD and DQ Pull Up */
> +	if (priv->phy_type == EMMC_5_0_PHY) {
> +		reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
> +		reg |= (XENON_EMMC5_FC_CMD_PU | XENON_EMMC5_FC_DQ_PU);
> +		reg &= ~(XENON_EMMC5_FC_CMD_PD | XENON_EMMC5_FC_DQ_PD);
> +		sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
> +	} else {
> +		reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
> +		reg |= (XENON_EMMC5_1_FC_CMD_PU | XENON_EMMC5_1_FC_DQ_PU);
> +		reg &= ~(XENON_EMMC5_1_FC_CMD_PD | XENON_EMMC5_1_FC_DQ_PD);
> +		sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
> +	}
> +
> +	if (timing == MMC_TIMING_LEGACY) {
> +		/*
> +		 * If Slow Mode is required, enable Slow Mode by default
> +		 * in early init phase to avoid any potential issue.
> +		 */
> +		if (params->slow_mode) {
> +			reg = sdhci_readl(host, phy_regs->timing_adj);
> +			reg |= XENON_TIMING_ADJUST_SLOW_MODE;
> +			sdhci_writel(host, reg, phy_regs->timing_adj);
> +		}
> +		goto phy_init;
> +	}
> +
> +	/*
> +	 * FIXME: should depends on the specific board timing.
> +	 */
> +	if ((timing == MMC_TIMING_MMC_HS400) ||
> +	    (timing == MMC_TIMING_MMC_HS200) ||
> +	    (timing == MMC_TIMING_UHS_SDR50) ||
> +	    (timing == MMC_TIMING_UHS_SDR104) ||
> +	    (timing == MMC_TIMING_UHS_DDR50) ||
> +	    (timing == MMC_TIMING_UHS_SDR25) ||
> +	    (timing == MMC_TIMING_MMC_DDR52)) {
> +		reg = sdhci_readl(host, phy_regs->timing_adj);
> +		reg &= ~XENON_OUTPUT_QSN_PHASE_SELECT;
> +		sdhci_writel(host, reg, phy_regs->timing_adj);
> +	}
> +
> +	/*
> +	 * If SDIO card, set SDIO Mode
> +	 * Otherwise, clear SDIO Mode
> +	 */
> +	reg = sdhci_readl(host, phy_regs->timing_adj);
> +	if (priv->init_card_type == MMC_TYPE_SDIO)
> +		reg |= XENON_TIMING_ADJUST_SDIO_MODE;
> +	else
> +		reg &= ~XENON_TIMING_ADJUST_SDIO_MODE;
> +	sdhci_writel(host, reg, phy_regs->timing_adj);
> +
> +	if (emmc_phy_slow_mode(host, timing))
> +		goto phy_init;
> +
> +	/*
> +	 * Set preferred ZNR and ZPR value
> +	 * The ZNR and ZPR value vary between different boards.
> +	 * Define them both in sdhci-xenon-emmc-phy.h.
> +	 */
> +	reg = sdhci_readl(host, phy_regs->pad_ctrl2);
> +	reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK);
> +	reg |= ((params->znr << XENON_ZNR_SHIFT) | params->zpr);
> +	sdhci_writel(host, reg, phy_regs->pad_ctrl2);
> +
> +	/*
> +	 * When setting EMMC_PHY_FUNC_CONTROL register,
> +	 * SD clock should be disabled
> +	 */
> +	reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
> +	reg &= ~SDHCI_CLOCK_CARD_EN;
> +	sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
> +
> +	reg = sdhci_readl(host, phy_regs->func_ctrl);
> +	if ((timing == MMC_TIMING_UHS_DDR50) ||
> +	    (timing == MMC_TIMING_MMC_HS400) ||
> +	    (timing == MMC_TIMING_MMC_DDR52))
> +		reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
> +		       XENON_CMD_DDR_MODE;
> +	else
> +		reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |
> +			 XENON_CMD_DDR_MODE);
> +
> +	if (timing == MMC_TIMING_MMC_HS400)
> +		reg &= ~XENON_DQ_ASYNC_MODE;
> +	else
> +		reg |= XENON_DQ_ASYNC_MODE;
> +	sdhci_writel(host, reg, phy_regs->func_ctrl);
> +
> +	/* Enable bus clock */
> +	reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
> +	reg |= SDHCI_CLOCK_CARD_EN;
> +	sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
> +
> +	if (timing == MMC_TIMING_MMC_HS400)
> +		/* Hardware team recommend a value for HS400 */
> +		sdhci_writel(host, XENON_LOGIC_TIMING_VALUE,
> +			     phy_regs->logic_timing_adj);
> +	else
> +		__emmc_phy_disable_data_strobe(host);
> +
> +phy_init:
> +	emmc_phy_init(host);
> +
> +	spin_unlock_irqrestore(&host->lock, flags);
> +
> +	dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n");
> +}
> +
> +static int emmc_phy_parse_param_dt(struct sdhci_host *host,
> +				   struct device_node *np,
> +				   struct emmc_phy_params *params)
> +{
> +	u32 value;
> +
> +	if (of_property_read_bool(np, "marvell,xenon-phy-slow-mode"))
> +		params->slow_mode = true;
> +	else
> +		params->slow_mode = false;
> +
> +	if (!of_property_read_u32(np, "marvell,xenon-phy-znr", &value))
> +		params->znr = value & XENON_ZNR_MASK;
> +	else
> +		params->znr = XENON_ZNR_DEF_VALUE;
> +
> +	if (!of_property_read_u32(np, "marvell,xenon-phy-zpr", &value))
> +		params->zpr = value & XENON_ZPR_MASK;
> +	else
> +		params->zpr = XENON_ZPR_DEF_VALUE;
> +
> +	if (!of_property_read_u32(np, "marvell,xenon-phy-nr-success-tun",
> +				  &value))
> +		params->nr_tun_times = value & XENON_TUN_CONSECUTIVE_TIMES_MASK;
> +	else
> +		params->nr_tun_times = XENON_TUN_CONSECUTIVE_TIMES;
> +
> +	if (!of_property_read_u32(np, "marvell,xenon-phy-tun-step-divider",
> +				  &value))
> +		params->tun_step_divider = value & 0xFF;
> +	else
> +		params->tun_step_divider = XENON_TUNING_STEP_DIVIDER;
> +
> +	return 0;
> +}
> +
> +/*
> + * Setting PHY when card is working in High Speed Mode.
> + * HS400 set data strobe line.
> + * HS200/SDR104 set tuning config to prepare for tuning.
> + */
> +static int xenon_hs_delay_adj(struct sdhci_host *host)
> +{
> +	int ret = 0;
> +
> +	if (WARN_ON(host->clock <= XENON_DEFAULT_SDCLK_FREQ))
> +		return -EINVAL;
> +
> +	if (host->timing == MMC_TIMING_MMC_HS400) {
> +		emmc_phy_strobe_delay_adj(host);
> +		return 0;
> +	}
> +
> +	if ((host->timing == MMC_TIMING_MMC_HS200) ||
> +	    (host->timing == MMC_TIMING_UHS_SDR104))
> +		return emmc_phy_config_tuning(host);
> +
> +	/*
> +	 * DDR Mode requires driver to scan Sampling Fixed Delay Line,
> +	 * to find out a perfect operation sampling point.
> +	 * It is hard to implement such a scan in host driver since initiating
> +	 * commands by host driver is not safe.
> +	 * Thus so far just keep PHY Sampling Fixed Delay in default value
> +	 * in DDR mode.
> +	 *
> +	 * If any timing issue occurs in DDR mode on Marvell products,
> +	 * please contact maintainer to ask for internal support in Marvell.
> +	 */
> +	if ((host->timing == MMC_TIMING_MMC_DDR52) ||
> +	    (host->timing == MMC_TIMING_UHS_DDR50))
> +		dev_warn_once(mmc_dev(host->mmc), "Timing issue might occur in DDR mode\n");
> +	return ret;
> +}
> +
> +/*
> + * Adjust PHY setting.
> + * PHY setting should be adjusted when SDCLK frequency, Bus Width
> + * or Speed Mode is changed.
> + * Additional config are required when card is working in High Speed mode,
> + * after leaving Legacy Mode.
> + */
> +int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	int ret = 0;
> +
> +	if (!host->clock) {
> +		priv->clock = 0;
> +		return 0;
> +	}
> +
> +	/*
> +	 * The timing, frequency or bus width is changed,
> +	 * better to set eMMC PHY based on current setting
> +	 * and adjust Xenon SDHC delay.
> +	 */
> +	if ((host->clock == priv->clock) &&
> +	    (ios->bus_width == priv->bus_width) &&
> +	    (ios->timing == priv->timing))
> +		return 0;
> +
> +	emmc_phy_set(host, ios->timing);
> +
> +	/* Update the record */
> +	priv->bus_width = ios->bus_width;
> +
> +	priv->timing = ios->timing;
> +	priv->clock = host->clock;
> +
> +	/* Legacy mode is a special case */
> +	if (ios->timing == MMC_TIMING_LEGACY)
> +		return 0;
> +
> +	if (host->clock > XENON_DEFAULT_SDCLK_FREQ)
> +		ret = xenon_hs_delay_adj(host);
> +	return ret;
> +}
> +
> +static void clean_emmc_phy(struct sdhci_xenon_priv *priv)
> +{
> +	kfree(priv->phy_params);
> +}
> +
> +static int add_xenon_phy(struct device_node *np, struct sdhci_host *host,
> +			 const char *phy_name)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	int i, ret;
> +
> +	for (i = 0; i < NR_PHY_TYPES; i++) {
> +		if (!strcmp(phy_name, phy_types[i])) {
> +			priv->phy_type = i;
> +			break;
> +		}
> +	}
> +	if (i == NR_PHY_TYPES) {
> +		dev_err(mmc_dev(host->mmc),
> +			"Unable to determine PHY name %s. Use default eMMC 5.1 PHY\n",
> +			phy_name);
> +		priv->phy_type = EMMC_5_1_PHY;
> +	}
> +
> +	ret = alloc_emmc_phy(priv);
> +	if (ret)
> +		return ret;
> +
> +	ret = emmc_phy_parse_param_dt(host, np, priv->phy_params);
> +	if (ret)
> +		clean_emmc_phy(priv);
> +
> +	return ret;
> +}
> +
> +int xenon_phy_parse_dt(struct device_node *np, struct sdhci_host *host)
> +{
> +	const char *phy_type = NULL;
> +
> +	if (!of_property_read_string(np, "marvell,xenon-phy-type", &phy_type))
> +		return add_xenon_phy(np, host, phy_type);
> +
> +	dev_info(mmc_dev(host->mmc), "Fail to get Xenon PHY type. Use default eMMC 5.1 PHY\n");
> +	return add_xenon_phy(np, host, "emmc 5.1 phy");
> +}
> diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
> index e633f803907a..99c18cad6460 100644
> --- a/drivers/mmc/host/sdhci-xenon.c
> +++ b/drivers/mmc/host/sdhci-xenon.c
> @@ -260,6 +260,7 @@ static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>  	spin_unlock_irqrestore(&host->lock, flags);
>  
>  	sdhci_set_ios(mmc, ios);
> +	xenon_phy_adj(host, ios);
>  
>  	if (host->clock > XENON_DEFAULT_SDCLK_FREQ) {
>  		spin_lock_irqsave(&host->lock, flags);
> @@ -465,7 +466,7 @@ static int xenon_probe_dt(struct platform_device *pdev)
>  	}
>  	priv->tuning_count = tuning_count;
>  
> -	return 0;
> +	return xenon_phy_parse_dt(np, host);
>  }
>  
>  static int xenon_sdhc_probe(struct sdhci_host *host)
> diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h
> index 69de711db9eb..e87639774bca 100644
> --- a/drivers/mmc/host/sdhci-xenon.h
> +++ b/drivers/mmc/host/sdhci-xenon.h
> @@ -24,7 +24,17 @@
>  #define XENON_SYS_EXT_OP_CTRL			0x010C
>  #define XENON_MASK_CMD_CONFLICT_ERR		BIT(8)
>  
> +#define XENON_SLOT_OP_STATUS_CTRL		0x0128
> +
> +#define XENON_TUN_CONSECUTIVE_TIMES_SHIFT	16
> +#define XENON_TUN_CONSECUTIVE_TIMES_MASK	0x7
> +#define XENON_TUN_CONSECUTIVE_TIMES		0x4
> +#define XENON_TUNING_STEP_SHIFT			12
> +#define XENON_TUNING_STEP_MASK			0xF
> +#define XENON_TUNING_STEP_DIVIDER		BIT(6)
> +
>  #define XENON_SLOT_EMMC_CTRL			0x0130
> +#define XENON_ENABLE_DATA_STROBE		BIT(24)
>  #define XENON_EMMC_VCCQ_MASK			0x3
>  #define XENON_EMMC_VCCQ_1_8V			0x1
>  #define XENON_EMMC_VCCQ_3_3V			0x3
> @@ -33,11 +43,17 @@
>  /* retuning compatible */
>  #define XENON_RETUNING_COMPATIBLE		0x1
>  
> +#define XENON_SLOT_EXT_PRESENT_STATE		0x014C
> +#define XENON_DLL_LOCK_STATE			0x1
> +
> +#define XENON_SLOT_DLL_CUR_DLY_VAL		0x0150
> +
>  /* Tuning Parameter */
>  #define XENON_TMR_RETUN_NO_PRESENT		0xF
>  #define XENON_DEF_TUNING_COUNT			0x9
>  
>  #define XENON_DEFAULT_SDCLK_FREQ		400000
> +#define XENON_LOWEST_SDCLK_FREQ			100000
>  
>  /* Xenon specific Mode Select value */
>  #define XENON_CTRL_HS200			0x5
> @@ -65,6 +81,27 @@ struct sdhci_xenon_priv {
>  	 * initialization completes.
>  	 */
>  	unsigned int	init_card_type;
> +
> +	/*
> +	 * The bus_width, timing, and clock fields in below
> +	 * record the current ios setting of Xenon SDHC.
> +	 * Driver will adjust PHY setting if any change to
> +	 * ios affects PHY timing.
> +	 */
> +	unsigned char	bus_width;
> +	unsigned char	timing;
> +	unsigned int	clock;
> +
> +	int		phy_type;
> +	/*
> +	 * Contains board-specific PHY parameters
> +	 * passed from device tree.
> +	 */
> +	void		*phy_params;
> +	struct xenon_emmc_phy_regs *emmc_phy_regs;
>  };
>  
> +int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios);
> +int xenon_phy_parse_dt(struct device_node *np,
> +		       struct sdhci_host *host);
>  #endif
> 

[PATCH v6 10/14] mmc: sdhci-xenon: Add SoC PHY PAD voltage control

[Gregory CLEMENT]

From: Hu Ziji <huziji@marvell.com>

Some SoCs have PHY PAD outside Xenon IP.
PHY PAD voltage should match signalling voltage in use.

Add generic SoC PHY PAD voltage control interface.
Implement Aramda-3700 SoC PHY PAD voltage control.

Signed-off-by: Hu Ziji <huziji@marvell.com>
Tested-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/mmc/host/sdhci-xenon-phy.c | 116 +++++++++++++++++++++++++++++-
 drivers/mmc/host/sdhci-xenon.c     |   2 +-
 drivers/mmc/host/sdhci-xenon.h     |   2 +-
 3 files changed, 119 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c
index c26ba3a180a0..c3b7e9a21f6b 100644
--- a/drivers/mmc/host/sdhci-xenon-phy.c
+++ b/drivers/mmc/host/sdhci-xenon-phy.c
@@ -143,6 +143,27 @@ enum phy_type_enum {
 	NR_PHY_TYPES
 };
 
+enum soc_pad_ctrl_type {
+	SOC_PAD_SD,
+	SOC_PAD_FIXED_1_8V,
+};
+
+struct soc_pad_ctrl_table {
+	const char *soc;
+	void (*set_soc_pad)(struct sdhci_host *host,
+			    unsigned char signal_voltage);
+};
+
+struct soc_pad_ctrl {
+	/* Register address of SoC PHY PAD ctrl */
+	void __iomem	*reg;
+	/* SoC PHY PAD ctrl type */
+	enum soc_pad_ctrl_type pad_type;
+	/* SoC specific operation to set SoC PHY PAD */
+	void (*set_soc_pad)(struct sdhci_host *host,
+			    unsigned char signal_voltage);
+};
+
 static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = {
 	.timing_adj	= XENON_EMMC_5_0_PHY_TIMING_ADJUST,
 	.func_ctrl	= XENON_EMMC_5_0_PHY_FUNC_CONTROL,
@@ -176,6 +197,8 @@ struct emmc_phy_params {
 	u8	nr_tun_times;
 	/* Divider for calculating Tuning Step */
 	u8	tun_step_divider;
+
+	struct soc_pad_ctrl pad_ctrl;
 };
 
 static int alloc_emmc_phy(struct sdhci_xenon_priv *priv)
@@ -252,6 +275,45 @@ static int emmc_phy_init(struct sdhci_host *host)
 	return 0;
 }
 
+#define ARMADA_3700_SOC_PAD_1_8V	0x1
+#define ARMADA_3700_SOC_PAD_3_3V	0x0
+
+static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host,
+					    unsigned char signal_voltage)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	struct emmc_phy_params *params = priv->phy_params;
+
+	if (params->pad_ctrl.pad_type == SOC_PAD_FIXED_1_8V) {
+		writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg);
+	} else if (params->pad_ctrl.pad_type == SOC_PAD_SD) {
+		if (signal_voltage == MMC_SIGNAL_VOLTAGE_180)
+			writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg);
+		else if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
+			writel(ARMADA_3700_SOC_PAD_3_3V, params->pad_ctrl.reg);
+	}
+}
+
+/*
+ * Set SoC PHY voltage PAD control register,
+ * according to the operation voltage on PAD.
+ * The detailed operation depends on SoC implementation.
+ */
+static void emmc_phy_set_soc_pad(struct sdhci_host *host,
+				 unsigned char signal_voltage)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	struct emmc_phy_params *params = priv->phy_params;
+
+	if (!params->pad_ctrl.reg)
+		return;
+
+	if (params->pad_ctrl.set_soc_pad)
+		params->pad_ctrl.set_soc_pad(host, signal_voltage);
+}
+
 /*
  * Enable eMMC PHY HW DLL
  * DLL should be enabled and stable before HS200/SDR104 tuning,
@@ -584,6 +646,51 @@ static void emmc_phy_set(struct sdhci_host *host,
 	dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n");
 }
 
+static int get_dt_pad_ctrl_data(struct sdhci_host *host,
+				struct device_node *np,
+				struct emmc_phy_params *params)
+{
+	int ret = 0;
+	const char *name;
+	struct resource iomem;
+
+	if (of_device_is_compatible(np, "marvell,armada-3700-sdhci"))
+		params->pad_ctrl.set_soc_pad = armada_3700_soc_pad_voltage_set;
+	else
+		return 0;
+
+	if (of_address_to_resource(np, 1, &iomem)) {
+		dev_err(mmc_dev(host->mmc), "Unable to find SoC PAD ctrl register address for %s\n",
+			np->name);
+		return -EINVAL;
+	}
+
+	params->pad_ctrl.reg = devm_ioremap_resource(mmc_dev(host->mmc),
+						     &iomem);
+	if (IS_ERR(params->pad_ctrl.reg)) {
+		dev_err(mmc_dev(host->mmc), "Unable to get SoC PHY PAD ctrl register for %s\n",
+			np->name);
+		return PTR_ERR(params->pad_ctrl.reg);
+	}
+
+	ret = of_property_read_string(np, "marvell,pad-type", &name);
+	if (ret) {
+		dev_err(mmc_dev(host->mmc), "Unable to determine SoC PHY PAD ctrl type\n");
+		return ret;
+	}
+	if (!strcmp(name, "sd")) {
+		params->pad_ctrl.pad_type = SOC_PAD_SD;
+	} else if (!strcmp(name, "fixed-1-8v")) {
+		params->pad_ctrl.pad_type = SOC_PAD_FIXED_1_8V;
+	} else {
+		dev_err(mmc_dev(host->mmc), "Unsupported SoC PHY PAD ctrl type %s\n",
+			name);
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
 static int emmc_phy_parse_param_dt(struct sdhci_host *host,
 				   struct device_node *np,
 				   struct emmc_phy_params *params)
@@ -617,7 +724,14 @@ static int emmc_phy_parse_param_dt(struct sdhci_host *host,
 	else
 		params->tun_step_divider = XENON_TUNING_STEP_DIVIDER;
 
-	return 0;
+	return get_dt_pad_ctrl_data(host, np, params);
+}
+
+/* Set SoC PHY Voltage PAD */
+void xenon_soc_pad_ctrl(struct sdhci_host *host,
+			unsigned char signal_voltage)
+{
+	emmc_phy_set_soc_pad(host, signal_voltage);
 }
 
 /*
diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
index 99c18cad6460..f344d9fb0a1b 100644
--- a/drivers/mmc/host/sdhci-xenon.c
+++ b/drivers/mmc/host/sdhci-xenon.c
@@ -338,6 +338,8 @@ static int xenon_start_signal_voltage_switch(struct mmc_host *mmc,
 	 */
 	enable_xenon_internal_clk(host);
 
+	xenon_soc_pad_ctrl(host, ios->signal_voltage);
+
 	if (priv->init_card_type == MMC_TYPE_MMC)
 		return xenon_emmc_signal_voltage_switch(mmc, ios);
 
diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h
index e87639774bca..57e7cb463413 100644
--- a/drivers/mmc/host/sdhci-xenon.h
+++ b/drivers/mmc/host/sdhci-xenon.h
@@ -104,4 +104,6 @@ struct sdhci_xenon_priv {
 int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios);
 int xenon_phy_parse_dt(struct device_node *np,
 		       struct sdhci_host *host);
+void xenon_soc_pad_ctrl(struct sdhci_host *host,
+			unsigned char signal_voltage);
 #endif
-- 
git-series 0.9.1

Re: [PATCH v6 10/14] mmc: sdhci-xenon: Add SoC PHY PAD voltage control

[Adrian Hunter]

On 14/02/17 19:01, Gregory CLEMENT wrote:
> From: Hu Ziji <huziji@marvell.com>
> 
> Some SoCs have PHY PAD outside Xenon IP.
> PHY PAD voltage should match signalling voltage in use.
> 
> Add generic SoC PHY PAD voltage control interface.
> Implement Aramda-3700 SoC PHY PAD voltage control.
> 
> Signed-off-by: Hu Ziji <huziji@marvell.com>
> Tested-by: Russell King <rmk+kernel@armlinux.org.uk>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
>  drivers/mmc/host/sdhci-xenon-phy.c | 116 +++++++++++++++++++++++++++++-
>  drivers/mmc/host/sdhci-xenon.c     |   2 +-
>  drivers/mmc/host/sdhci-xenon.h     |   2 +-
>  3 files changed, 119 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c
> index c26ba3a180a0..c3b7e9a21f6b 100644
> --- a/drivers/mmc/host/sdhci-xenon-phy.c
> +++ b/drivers/mmc/host/sdhci-xenon-phy.c
> @@ -143,6 +143,27 @@ enum phy_type_enum {
>  	NR_PHY_TYPES
>  };
>  
> +enum soc_pad_ctrl_type {
> +	SOC_PAD_SD,
> +	SOC_PAD_FIXED_1_8V,
> +};
> +
> +struct soc_pad_ctrl_table {
> +	const char *soc;
> +	void (*set_soc_pad)(struct sdhci_host *host,
> +			    unsigned char signal_voltage);
> +};

Is soc_pad_ctrl_table used?

> +
> +struct soc_pad_ctrl {
> +	/* Register address of SoC PHY PAD ctrl */
> +	void __iomem	*reg;
> +	/* SoC PHY PAD ctrl type */
> +	enum soc_pad_ctrl_type pad_type;
> +	/* SoC specific operation to set SoC PHY PAD */
> +	void (*set_soc_pad)(struct sdhci_host *host,
> +			    unsigned char signal_voltage);
> +};
> +
>  static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = {
>  	.timing_adj	= XENON_EMMC_5_0_PHY_TIMING_ADJUST,
>  	.func_ctrl	= XENON_EMMC_5_0_PHY_FUNC_CONTROL,
> @@ -176,6 +197,8 @@ struct emmc_phy_params {
>  	u8	nr_tun_times;
>  	/* Divider for calculating Tuning Step */
>  	u8	tun_step_divider;
> +
> +	struct soc_pad_ctrl pad_ctrl;
>  };
>  
>  static int alloc_emmc_phy(struct sdhci_xenon_priv *priv)
> @@ -252,6 +275,45 @@ static int emmc_phy_init(struct sdhci_host *host)
>  	return 0;
>  }
>  
> +#define ARMADA_3700_SOC_PAD_1_8V	0x1
> +#define ARMADA_3700_SOC_PAD_3_3V	0x0
> +
> +static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host,
> +					    unsigned char signal_voltage)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	struct emmc_phy_params *params = priv->phy_params;
> +
> +	if (params->pad_ctrl.pad_type == SOC_PAD_FIXED_1_8V) {
> +		writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg);
> +	} else if (params->pad_ctrl.pad_type == SOC_PAD_SD) {
> +		if (signal_voltage == MMC_SIGNAL_VOLTAGE_180)
> +			writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg);
> +		else if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
> +			writel(ARMADA_3700_SOC_PAD_3_3V, params->pad_ctrl.reg);
> +	}
> +}
> +
> +/*
> + * Set SoC PHY voltage PAD control register,
> + * according to the operation voltage on PAD.
> + * The detailed operation depends on SoC implementation.
> + */
> +static void emmc_phy_set_soc_pad(struct sdhci_host *host,
> +				 unsigned char signal_voltage)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	struct emmc_phy_params *params = priv->phy_params;
> +
> +	if (!params->pad_ctrl.reg)
> +		return;
> +
> +	if (params->pad_ctrl.set_soc_pad)
> +		params->pad_ctrl.set_soc_pad(host, signal_voltage);
> +}
> +
>  /*
>   * Enable eMMC PHY HW DLL
>   * DLL should be enabled and stable before HS200/SDR104 tuning,
> @@ -584,6 +646,51 @@ static void emmc_phy_set(struct sdhci_host *host,
>  	dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n");
>  }
>  
> +static int get_dt_pad_ctrl_data(struct sdhci_host *host,
> +				struct device_node *np,
> +				struct emmc_phy_params *params)
> +{
> +	int ret = 0;
> +	const char *name;
> +	struct resource iomem;
> +
> +	if (of_device_is_compatible(np, "marvell,armada-3700-sdhci"))
> +		params->pad_ctrl.set_soc_pad = armada_3700_soc_pad_voltage_set;
> +	else
> +		return 0;
> +
> +	if (of_address_to_resource(np, 1, &iomem)) {
> +		dev_err(mmc_dev(host->mmc), "Unable to find SoC PAD ctrl register address for %s\n",
> +			np->name);
> +		return -EINVAL;
> +	}
> +
> +	params->pad_ctrl.reg = devm_ioremap_resource(mmc_dev(host->mmc),
> +						     &iomem);
> +	if (IS_ERR(params->pad_ctrl.reg)) {
> +		dev_err(mmc_dev(host->mmc), "Unable to get SoC PHY PAD ctrl register for %s\n",
> +			np->name);
> +		return PTR_ERR(params->pad_ctrl.reg);
> +	}
> +
> +	ret = of_property_read_string(np, "marvell,pad-type", &name);
> +	if (ret) {
> +		dev_err(mmc_dev(host->mmc), "Unable to determine SoC PHY PAD ctrl type\n");
> +		return ret;
> +	}
> +	if (!strcmp(name, "sd")) {
> +		params->pad_ctrl.pad_type = SOC_PAD_SD;
> +	} else if (!strcmp(name, "fixed-1-8v")) {
> +		params->pad_ctrl.pad_type = SOC_PAD_FIXED_1_8V;
> +	} else {
> +		dev_err(mmc_dev(host->mmc), "Unsupported SoC PHY PAD ctrl type %s\n",
> +			name);
> +		return -EINVAL;
> +	}
> +
> +	return ret;
> +}
> +
>  static int emmc_phy_parse_param_dt(struct sdhci_host *host,
>  				   struct device_node *np,
>  				   struct emmc_phy_params *params)
> @@ -617,7 +724,14 @@ static int emmc_phy_parse_param_dt(struct sdhci_host *host,
>  	else
>  		params->tun_step_divider = XENON_TUNING_STEP_DIVIDER;
>  
> -	return 0;
> +	return get_dt_pad_ctrl_data(host, np, params);
> +}
> +
> +/* Set SoC PHY Voltage PAD */
> +void xenon_soc_pad_ctrl(struct sdhci_host *host,
> +			unsigned char signal_voltage)
> +{
> +	emmc_phy_set_soc_pad(host, signal_voltage);
>  }
>  
>  /*
> diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
> index 99c18cad6460..f344d9fb0a1b 100644
> --- a/drivers/mmc/host/sdhci-xenon.c
> +++ b/drivers/mmc/host/sdhci-xenon.c
> @@ -338,6 +338,8 @@ static int xenon_start_signal_voltage_switch(struct mmc_host *mmc,
>  	 */
>  	enable_xenon_internal_clk(host);
>  
> +	xenon_soc_pad_ctrl(host, ios->signal_voltage);
> +
>  	if (priv->init_card_type == MMC_TYPE_MMC)
>  		return xenon_emmc_signal_voltage_switch(mmc, ios);
>  
> diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h
> index e87639774bca..57e7cb463413 100644
> --- a/drivers/mmc/host/sdhci-xenon.h
> +++ b/drivers/mmc/host/sdhci-xenon.h
> @@ -104,4 +104,6 @@ struct sdhci_xenon_priv {
>  int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios);
>  int xenon_phy_parse_dt(struct device_node *np,
>  		       struct sdhci_host *host);
> +void xenon_soc_pad_ctrl(struct sdhci_host *host,
> +			unsigned char signal_voltage);
>  #endif
> 

[PATCH v6 11/14] MAINTAINERS: add entry for Marvell Xenon MMC Host Controller drivers

[Gregory CLEMENT]

From: Hu Ziji <huziji@marvell.com>

Add maintainer entry for Marvell Xenon eMMC/SD/SDIO
Host Controller drivers.

Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 MAINTAINERS | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index cfff2c9e3d94..f4fea77165d5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7757,6 +7757,13 @@ M:	Nicolas Pitre <nico@fluxnic.net>
 S:	Odd Fixes
 F:	drivers/mmc/host/mvsdio.*
 
+MARVELL XENON MMC/SD/SDIO HOST CONTROLLER DRIVER
+M:	Ziji Hu <huziji@marvell.com>
+L:	linux-mmc@vger.kernel.org
+S:	Supported
+F:	drivers/mmc/host/sdhci-xenon*
+F:	Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
+
 MATROX FRAMEBUFFER DRIVER
 L:	linux-fbdev@vger.kernel.org
 S:	Orphan
-- 
git-series 0.9.1

[PATCH v6 12/14] arm64: dts: marvell: add eMMC support for Armada 37xx

[Gregory CLEMENT]

Add the eMMC support for Armada 37xx SoC and enable it in the Armada 3720
DB board.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm64/boot/dts/marvell/armada-3720-db.dts | 16 ++++++++++++++++
 arch/arm64/boot/dts/marvell/armada-37xx.dtsi   | 11 +++++++++++
 2 files changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 89de0a751093..118796b325e5 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -72,6 +72,22 @@
 	status = "okay";
 };
 
+&sdhci0 {
+	non-removable;
+	bus-width = <8>;
+	mmc-ddr-1_8v;
+	mmc-hs400-1_8v;
+	marvell,pad-type = "fixed-1-8v";
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+	mmccard: mmccard@0 {
+		compatible = "mmc-card";
+		reg = <0>;
+	};
+};
+
 /* CON31 */
 &usb3 {
 	status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index bab5c6ff5745..966b6f030bfa 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -184,6 +184,17 @@
 				};
 			};
 
+			sdhci0: sdhci@d8000 {
+				compatible = "marvell,armada-3700-sdhci",
+				"marvell,sdhci-xenon";
+				reg = <0xd8000 0x300
+				       0x17808 0x4>;
+				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&nb_periph_clk 0>;
+				clock-names = "core";
+				status = "disabled";
+			};
+
 			sata: sata@e0000 {
 				compatible = "marvell,armada-3700-ahci";
 				reg = <0xe0000 0x2000>;
-- 
git-series 0.9.1

[PATCH v6 13/14] arm64: dts: marvell: add sdhci support for Armada 7K/8K

[Gregory CLEMENT]

Also enable it on the Armada 7040 DB and Armada 8040 DB boards.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm64/boot/dts/marvell/armada-7040-db.dts       | 14 +++++++++-
 arch/arm64/boot/dts/marvell/armada-8040-db.dts       | 20 +++++++++++++-
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi        | 11 +++++++-
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 11 +++++++-
 4 files changed, 56 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 070b589680c5..6adbfcd26369 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -146,3 +146,17 @@
 &cpm_usb3_1 {
 	status = "okay";
 };
+
+&ap_sdhci0 {
+	status = "okay";
+	bus-width = <4>;
+	no-1-8-v;
+	non-removable;
+};
+
+&cpm_sdhci0 {
+	status = "okay";
+	bus-width = <4>;
+	no-1-8-v;
+	non-removable;
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 6e6f182fb297..ab16082d9fbf 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -148,3 +148,23 @@
 &cps_usb3_1 {
 	status = "okay";
 };
+
+&ap_sdhci0 {
+	status = "okay";
+	bus-width = <4>;
+	non-removable;
+};
+
+&cpm_sdhci0 {
+	status = "okay";
+	bus-width = <8>;
+	non-removable;
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+	mmccard: mmccard@0 {
+		compatible = "mmc-card";
+		reg = <0>;
+	};
+
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 5019c8f4acd0..fe41bf9c301e 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -229,6 +229,17 @@
 
 			};
 
+			ap_sdhci0: sdhci@6e0000 {
+				compatible = "marvell,armada-ap806-sdhci";
+				reg = <0x6e0000 0x300>;
+				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+				clock-names = "core";
+				clocks = <&ap_syscon 4>;
+				dma-coherent;
+				marvell,xenon-phy-slow-mode;
+				status = "disabled";
+			};
+
 			ap_syscon: system-controller@6f4000 {
 				compatible = "marvell,ap806-system-controller",
 					     "syscon";
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index 05222f749a45..8ff545dc4195 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -172,6 +172,17 @@
 				clocks = <&cpm_syscon0 1 25>;
 				status = "okay";
 			};
+
+			cpm_sdhci0: sdhci@780000 {
+				compatible = "marvell,armada-cp110-sdhci";
+				reg = <0x780000 0x300>;
+				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+				clock-names = "core";
+				clocks = <&cpm_syscon0 1 4>;
+				dma-coherent;
+				status = "disabled";
+			};
+
 		};
 
 		cpm_pcie0: pcie@f2600000 {
-- 
git-series 0.9.1

[PATCH v6 14/14] arm64: configs: enable SDHCI driver for Xenon

[Gregory CLEMENT]

This patch enables the driver for the SDHCI controller found on the
Marvell Armada 3700 and 7K/8K ARM64 SoCs.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 869dded0f09f..341fc631f598 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -390,6 +390,7 @@ CONFIG_MMC_DW_EXYNOS=y
 CONFIG_MMC_DW_K3=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SUNXI=y
+CONFIG_MMC_SDHCI_XENON=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
-- 
git-series 0.9.1

Re: [PATCH v6 00/14] mmc: Add support to Marvell Xenon SD Host Controller

[Gregory CLEMENT]

Hi Ulf,
 
 On mar., févr. 14 2017, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:

> Hello,
>
> This the sixth version of the series adding support for the SDHCI
> Xenon controller. It can be currently found on the Armada 37xx and the
> Armada 7K/8K but will be also used in more Marvell SoC (and not only
> the mvebu ones actually).
>
> Most of the following changes had been discussed on the mailing list,
> except the new compatible string.
>

I think that with this version we addressed all the concerns expressed
about the previous version. Do you think that you will be able to apply
this series for 4.11 or do you still see any issues?

Thanks,

Gregory


> It occurred that the xenon controller was integrated in a different
> way in the AP806 and the CP110 which both are part of the Armada 7K/8K
> SoCs. For example the Xenon controller in CP110 doesn't not support
> HS200.
>
> v5->v6:
>
> - Add a generic "mmc-card" parse in core layer.
>
> - Fix the spelling issues in Xenon dt binding doc and drivers.
>
> - Remove descriptions to common mmc properties from Xenon dt binding
>   doc.
>
> - Split compatible string "marvell,armada-8k-sdhci" into
>  "marvell,armada-ap806-sdhci" and "marvell,armada-cp110-sdhci".
>
> - Also updates the example in Xenon dt binding doc.
>
> - Remove unnecessary dependency on MMC_SDHCI from Xenon entry in
>   Kconfig.
>
> - Move Xenon specific dt parse into a separate function.
>
> - Adjust warnings and condition check in Xenon PHY setting, to remove
>  fragile hs200->hs400/hs400->hs200 sequence check function.
>
> - Enable PHY Slow Mode in MMC_TIMING_LEGACY timing if PHY Slow Mode is
>  required in dts.
>
> - Add a patch allowing dts backwards compatible for the clock
>
> v4->v5:
>
> - Remove the patch to export sdhci_execute_tuning(). It is already
>   exported in v4.10.
>
> - Introduce a patch adding a missing clock for the sdhci controller
>   present on the CP master for A7K/A8K. There is no build dependency
>   but obviously this patch is need to use the sdhci controller present
>   on the CP part.
>
> - Adjust Xenon return setup, to avoid being overwritten by
>    sdhci_add_host().
>
> - Change Xenon register definition prefix to "XENON_".
>
> -  Fix typos in Xenon driver and dt-binding docs.
>
> - Change compatible string "marvell,armada-7000-sdhci" to
>   "marvell,armada-8k-sdhci". Actually the Armada 7K SoCs are a subset
>   of the Armada 8K SoCs. Moreover, the use of the '000' is not
>   consistent with all the other compatible string already used for the
>   Armada 7K/8K family.
>
> - Added the Tested-by from Russell King on an Armada 8K based board.
>
> v3 -> v4:
> For this version a few change have been done:
> - fixes 2 bug  reported by kbuild-bot
>   - remove extra of_node_put()
>   - convert 0 in false for function returning boolean
>
> - add a device tree node for the sdhci controller present on the CP
>   master for A7K/A8K. It also led to rename the sdhci0 node on AP to
>   ap_sdhci0 to make a distinction with the one present on CP master.
>
> v2 -> v3
> I think that now most (if not all) the remarks had been taking into
> account since the second version. According to Ziji Hu, here are the
> following changes:
> " Changes in V3:
>   Adjust and improve Xenon DT bindings. Move some caps setting from driver into
>   DT. Use mmc-card sub-node to represent eMMC type.
>   Remove PHY Sampling Fixed Delay Line scan in lower speed mode.
>   Improve Xenon probe and ->init_card() functions.
>   Export sdhci_enable_sdio_irq() and implement own SDIO IRQ control.
>   Split PHY patch into two smaller patches.
>   Temporarily remove AXI clock before its implementation is improved."
>
> Besides this changes I also
> - Removed the sdhci-xenon-phy.h and moved its content in the
> shc-xenon-phy.c file.
> - Fixed the tuning-count usage
> - Managed the error case for clk_prepare_enable
>
> For the record the change from v1 was:
> " Changes in V2:
>   rebase on v4.9-rc2.
>   Re-write Xenon bindings. Ajust Xenon DT property naming.
>   Add a new DT property to indicate eMMC card type, instead of using
>   variable card_candidate.
>   Clear quirks SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 in Xenon platform data
>   Add support to HS400 retuning."
>
> Thanks,
>
> Gregory
>
> Gregory CLEMENT (4):
>   clk: apn806: Turn the eMMC clock as optional for dts backwards compatible
>   arm64: dts: marvell: add eMMC support for Armada 37xx
>   arm64: dts: marvell: add sdhci support for Armada 7K/8K
>   arm64: configs: enable SDHCI driver for Xenon
>
> Hu Ziji (9):
>   mmc: core: Add mmc-card dt sub-node parse in core layer
>   mmc: sdhci: Export sdhci_set_ios() from sdhci.c
>   mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.c
>   mmc: sdhci: Export sdhci_enable_sdio_irq() from sdhci.c
>   dt: bindings: Add bindings for Marvell Xenon SD Host Controller
>   mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality
>   mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC
>   mmc: sdhci-xenon: Add SoC PHY PAD voltage control
>   MAINTAINERS: add entry for Marvell Xenon MMC Host Controller drivers
>
> Konstantin Porotchkin (1):
>   clk: apn806: Add eMMC clock to system controller driver
>
>  Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt | 172 +-
>  MAINTAINERS                                                   |   7 +-
>  arch/arm64/boot/dts/marvell/armada-3720-db.dts                |  16 +-
>  arch/arm64/boot/dts/marvell/armada-37xx.dtsi                  |  11 +-
>  arch/arm64/boot/dts/marvell/armada-7040-db.dts                |  14 +-
>  arch/arm64/boot/dts/marvell/armada-8040-db.dts                |  20 +-
>  arch/arm64/boot/dts/marvell/armada-ap806.dtsi                 |  14 +-
>  arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi          |  11 +-
>  arch/arm64/configs/defconfig                                  |   1 +-
>  drivers/clk/mvebu/ap806-system-controller.c                   |  21 +-
>  drivers/mmc/core/mmc.c                                        |  24 +-
>  drivers/mmc/host/Kconfig                                      |   9 +-
>  drivers/mmc/host/Makefile                                     |   3 +-
>  drivers/mmc/host/sdhci-xenon-phy.c                            | 865 +++++++-
>  drivers/mmc/host/sdhci-xenon.c                                | 605 +++++-
>  drivers/mmc/host/sdhci-xenon.h                                | 109 +-
>  drivers/mmc/host/sdhci.c                                      |  11 +-
>  drivers/mmc/host/sdhci.h                                      |   4 +-
>  include/linux/mmc/core.h                                      |   2 +-
>  19 files changed, 1913 insertions(+), 6 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
>  create mode 100644 drivers/mmc/host/sdhci-xenon-phy.c
>  create mode 100644 drivers/mmc/host/sdhci-xenon.c
>  create mode 100644 drivers/mmc/host/sdhci-xenon.h
>
> base-commit: 0c744ea4f77d72b3dcebb7a8f2684633ec79be88
> -- 
> git-series 0.9.1

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH v6 00/14] mmc: Add support to Marvell Xenon SD Host Controller

[Ulf Hansson]

On 20 February 2017 at 17:59, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:
> Hi Ulf,
>
>  On mar., févr. 14 2017, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:
>
>> Hello,
>>
>> This the sixth version of the series adding support for the SDHCI
>> Xenon controller. It can be currently found on the Armada 37xx and the
>> Armada 7K/8K but will be also used in more Marvell SoC (and not only
>> the mvebu ones actually).
>>
>> Most of the following changes had been discussed on the mailing list,
>> except the new compatible string.
>>
>
> I think that with this version we addressed all the concerns expressed
> about the previous version. Do you think that you will be able to apply
> this series for 4.11 or do you still see any issues?
>
> Thanks,
>
> Gregory

We are in the merge window for v4.11, so new material is out of the
question. I am preparing the PR to Linus as this very moment.

Anyway, I will look into the series as soon as I can.

Kind regards
Uffe

Re: [PATCH v6 00/14] mmc: Add support to Marvell Xenon SD Host Controller

[Ziji Hu]

Hi Ulf,

On 2017/2/21 3:32, Ulf Hansson wrote:
> On 20 February 2017 at 17:59, Gregory CLEMENT
> <gregory.clement@free-electrons.com> wrote:
>> Hi Ulf,
>>
>>  On mar., févr. 14 2017, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:
>>
>>> Hello,
>>>
>>> This the sixth version of the series adding support for the SDHCI
>>> Xenon controller. It can be currently found on the Armada 37xx and the
>>> Armada 7K/8K but will be also used in more Marvell SoC (and not only
>>> the mvebu ones actually).
>>>
>>> Most of the following changes had been discussed on the mailing list,
>>> except the new compatible string.
>>>
>>
>> I think that with this version we addressed all the concerns expressed
>> about the previous version. Do you think that you will be able to apply
>> this series for 4.11 or do you still see any issues?
>>
>> Thanks,
>>
>> Gregory
> 
> We are in the merge window for v4.11, so new material is out of the
> question. I am preparing the PR to Linus as this very moment.
> 
> Anyway, I will look into the series as soon as I can.

	Could you please take a look at our patch set?
	Very sorry for pushing you, but your comment is very important to us.

	Thank you.

Best regards,
Hu Ziji

> 
> Kind regards
> Uffe
> 

Re: [PATCH v6 00/14] mmc: Add support to Marvell Xenon SD Host Controller

[Gregory CLEMENT]

Hi Ulf,
 
 On lun., févr. 20 2017, Ulf Hansson <ulf.hansson@linaro.org> wrote:

> On 20 February 2017 at 17:59, Gregory CLEMENT
> <gregory.clement@free-electrons.com> wrote:
>> Hi Ulf,
>>
>>  On mar., févr. 14 2017, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:
>>
>>> Hello,
>>>
>>> This the sixth version of the series adding support for the SDHCI
>>> Xenon controller. It can be currently found on the Armada 37xx and the
>>> Armada 7K/8K but will be also used in more Marvell SoC (and not only
>>> the mvebu ones actually).
>>>
>>> Most of the following changes had been discussed on the mailing list,
>>> except the new compatible string.
>>>
>>
>> I think that with this version we addressed all the concerns expressed
>> about the previous version. Do you think that you will be able to apply
>> this series for 4.11 or do you still see any issues?
>>
>> Thanks,
>>
>> Gregory
>
> We are in the merge window for v4.11, so new material is out of the
> question. I am preparing the PR to Linus as this very moment.

v4.11-rc1 was released last week, do you want that I rebase the series
ontop of it ?

On our side we made several tests of this version of the driver on
various hardware and everything works as expected. We only notice some
configuration to update for the dts on some board but it didn't impact
the driver itself.

Gregory


>
> Anyway, I will look into the series as soon as I can.
>
> Kind regards
> Uffe
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH v6 00/14] mmc: Add support to Marvell Xenon SD Host Controller

[Russell King - ARM Linux]

On Tue, Feb 14, 2017 at 06:01:40PM +0100, Gregory CLEMENT wrote:
> Hello,
> 
> This the sixth version of the series adding support for the SDHCI
> Xenon controller. It can be currently found on the Armada 37xx and the
> Armada 7K/8K but will be also used in more Marvell SoC (and not only
> the mvebu ones actually).
> 
> Most of the following changes had been discussed on the mailing list,
> except the new compatible string.
> 
> It occurred that the xenon controller was integrated in a different
> way in the AP806 and the CP110 which both are part of the Armada 7K/8K
> SoCs. For example the Xenon controller in CP110 doesn't not support
> HS200.

Seems to continnue to work on the Macchiatobin board.

Tested-by: Russell King <rmk+kernel@armlinux.org.uk>

Thanks.

-- 
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.