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From: Andrea Arcangeli <aarcange@redhat.com>
To: Dave Hansen <dave.hansen@intel.com>
Cc: Jiri Kosina <jikos@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Tim Chen <tim.c.chen@linux.intel.com>,
	Tom Lendacky <thomas.lendacky@amd.com>,
	Ingo Molnar <mingo@redhat.com>,
	Peter Zijlstra <peterz@infradead.org>,
	Josh Poimboeuf <jpoimboe@redhat.com>,
	David Woodhouse <dwmw@amazon.co.uk>,
	Andi Kleen <ak@linux.intel.com>,
	Casey Schaufler <casey.schaufler@intel.com>,
	Asit Mallick <asit.k.mallick@intel.com>,
	Arjan van de Ven <arjan@linux.intel.com>,
	Jon Masters <jcm@redhat.com>, Waiman Long <longman9394@gmail.com>,
	LKML <linux-kernel@vger.kernel.org>,
	x86@kernel.org, Willy Tarreau <w@1wt.eu>
Subject: Re: [Patch v5 11/16] x86/speculation: Add Spectre v2 app to app protection modes
Date: Mon, 19 Nov 2018 18:16:49 -0500	[thread overview]
Message-ID: <20181119231649.GI29258@redhat.com> (raw)
In-Reply-To: <4d102977-f516-e0b3-b728-e318e36c1449@intel.com>

On Mon, Nov 19, 2018 at 01:33:08PM -0800, Dave Hansen wrote:
> On 11/19/18 11:32 AM, Andrea Arcangeli wrote:
> > The specs don't say if by making it immune from BTB mistraining, it
> > also could prevent to mistrain the BTB in order to attack what's
> > outside the SECCOMP jail. Probably it won't and I doubt we can rely on
> > it even if some implementation could do that.
> 
> I just talked with Andi and Tim about this.  The *current* spec for
> STIBP[1] states that it bidirectional: setting it on one thread provides
> mitigation against any threads attacking any other thread on the core.
                     ^^^                   ^^^
> 
> This means that it provides protection for victims being in and out of
> SECCOMP jail when the attacker is either in or out of SECCOMP jail.
> 
> However, the current spec[1], differs from the *original* spec PDF that
> Intel released last year.  Both are correct in that they describe all
> current (Intel) implementations of STIBP.  However, the new
> _description_ of STIBP is stronger than it was originally.
> 
> Here's the current description:
> 
> > Setting ... STIBP ... on a logical processor prevents the predicted
> > targets of indirect branches on any logical processor of that core
                                    ^^^
> > from being controlled by software that executes (or executed
> > previously) on another logical processor of the same core.
                   ^^^^^^^
> 
> 1.
> https://software.intel.com/security-software-guidance/insights/deep-dive-single-thread-indirect-branch-predictors

I'm not used to official specs in a "insight & deep dive"
blog-post-like webpage, so I didn't notice this deep dive detail.

You use "any" vs "any" but the spec you quoted still says "any" vs
"another".

If I shall take the above literally it still means that if I set STIBP
inside SECCOMP, as long as it's set, it prevents indirect branches of
all siblings to be controlled from code outside the SECCOMP jail
running in another sibling (or that run previously in another
sibling). I.e. the "deep dive" stronger semantics of STIBP just mean
the code outside SECCOMP cannot attack itself while the code inside
SECCOMP runs and keeps STIBP set.

So you may want to ask why it wasn't written as your "any" vs "any" email:

Setting ... STIBP ... on a logical processor prevents the predicted
targets of indirect branches on any logical processor of that core
from being controlled by software that executes (or executed
previously) on any logical processor of the same core.

A s/another/any/ is still missing to match your exact interpretation,
otherwise it still seems a gray area and I've no idea why it wasn't
written as "any" which would clear any risk for misunderstanding and
instead it kind of uses a word that matches the somewhat more strict
pdf specs.

If this is clarified the concern that remains is that lots of
potentially performance critical stuff runs under SECCOMP but of
course it changes everything in terms of possibly enabling STIBP under
SECCOMP by default, it certainly would make more sense then.

Thanks,
Andrea

  reply	other threads:[~2018-11-19 23:16 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-17  1:53 [Patch v5 00/16] Provide task property based options to enable Spectre v2 userspace-userspace protection Tim Chen
2018-11-17  1:53 ` [Patch v5 01/16] x86/speculation: Clean up spectre_v2_parse_cmdline() Tim Chen
2018-11-17  1:53 ` [Patch v5 02/16] x86/speculation: Remove unnecessary ret variable in cpu_show_common() Tim Chen
2018-11-17  1:53 ` [Patch v5 03/16] x86/speculation: Reorganize cpu_show_common() Tim Chen
2018-11-17  1:53 ` [Patch v5 04/16] x86/speculation: Add X86_FEATURE_USE_IBRS_ENHANCED Tim Chen
2018-11-17  1:53 ` [Patch v5 05/16] x86/speculation: Disable STIBP when enhanced IBRS is in use Tim Chen
2018-11-17  1:53 ` [Patch v5 06/16] x86/speculation: Rename SSBD update functions Tim Chen
2018-11-17  1:53 ` [Patch v5 07/16] x86/speculation: Reorganize speculation control MSRs update Tim Chen
2018-11-17  1:53 ` [Patch v5 08/16] smt: Create cpu_smt_enabled static key for SMT specific code Tim Chen
2018-11-19 12:58   ` Thomas Gleixner
2018-11-19 20:50     ` Tim Chen
2018-11-19 14:57   ` Peter Zijlstra
2018-11-19 18:08     ` Tim Chen
2018-11-19 19:03       ` Thomas Gleixner
2018-11-19 19:25         ` Tim Chen
2018-11-17  1:53 ` [Patch v5 09/16] x86/smt: Convert cpu_smt_control check to cpu_smt_enabled static key Tim Chen
2018-11-19 12:48   ` Thomas Gleixner
2018-11-19 12:59     ` Thomas Gleixner
2018-11-17  1:53 ` [Patch v5 10/16] x86/speculation: Turn on or off STIBP according to a task's TIF_STIBP Tim Chen
2018-11-17  1:53 ` [Patch v5 11/16] x86/speculation: Add Spectre v2 app to app protection modes Tim Chen
2018-11-17  9:47   ` Jiri Kosina
2018-11-18 22:59     ` Jiri Kosina
2018-11-19 13:36       ` Thomas Gleixner
2018-11-19 13:49         ` Jiri Kosina
2018-11-19 13:51           ` Thomas Gleixner
2018-11-19 14:00             ` Jiri Kosina
2018-11-19 18:31               ` Tim Chen
2018-11-19 19:32           ` Andrea Arcangeli
2018-11-19 19:39             ` Jiri Kosina
2018-11-19 21:40               ` Andrea Arcangeli
2018-11-19 21:33             ` Dave Hansen
2018-11-19 23:16               ` Andrea Arcangeli [this message]
2018-11-19 23:25                 ` Dave Hansen
2018-11-19 23:45                   ` Andrea Arcangeli
2018-11-20  0:22                 ` Thomas Gleixner
2018-11-19 13:32   ` Thomas Gleixner
2018-11-20  0:08     ` Tim Chen
2018-11-20  0:30       ` Thomas Gleixner
2018-11-20  1:14         ` Tim Chen
2018-11-20  1:17         ` Andi Kleen
2018-11-19 15:00   ` Thomas Gleixner
2018-11-19 18:27     ` Tim Chen
2018-11-19 18:31       ` Jiri Kosina
2018-11-19 20:21   ` Thomas Gleixner
2018-11-19 22:44     ` Tim Chen
2018-11-19 20:46   ` Thomas Gleixner
2018-11-19 20:55     ` Jiri Kosina
2018-11-19 21:12       ` Thomas Gleixner
2018-11-19 22:48       ` Tim Chen
2018-11-19 23:01         ` Thomas Gleixner
2018-11-19 23:23           ` Jiri Kosina
2018-11-20  0:00             ` Thomas Gleixner
2018-11-20  0:24               ` Tim Chen
2018-11-19 23:39           ` Dave Hansen
2018-11-19 23:49             ` Jiri Kosina
2018-11-20  0:02               ` Thomas Gleixner
2018-11-17  1:53 ` [Patch v5 12/16] x86/speculation: Create PRCTL interface to restrict indirect branch speculation Tim Chen
2018-11-17  9:53   ` Jiri Kosina
2018-11-19 18:29     ` Tim Chen
2018-11-17  1:53 ` [Patch v5 13/16] security: Update speculation restriction of a process when modifying its dumpability Tim Chen
2018-11-17  1:53 ` [Patch v5 14/16] x86/speculation: Use STIBP to restrict speculation on non-dumpable task Tim Chen
2018-11-17  1:53 ` [Patch v5 15/16] x86/speculation: Update comment on TIF_SSBD Tim Chen
2018-11-17  1:53 ` [Patch v5 16/16] x86: Group thread info flags by functionality Tim Chen
2018-11-17  9:34 ` [Patch v5 00/16] Provide task property based options to enable Spectre v2 userspace-userspace protection Jiri Kosina

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