qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
* [PULL 00/12] riscv-to-apply queue
@ 2020-10-23 15:16 Alistair Francis
  2020-10-23 15:16 ` [PULL 01/12] riscv: Convert interrupt logs to use qemu_log_mask() Alistair Francis
                   ` (12 more replies)
  0 siblings, 13 replies; 23+ messages in thread
From: Alistair Francis @ 2020-10-23 15:16 UTC (permalink / raw)
  To: qemu-devel, peter.maydell; +Cc: alistair23, Alistair Francis

The following changes since commit 4c5b97bfd0dd54dc27717ae8d1cd10e14eef1430:

  Merge remote-tracking branch 'remotes/kraxel/tags/modules-20201022-pull-request' into staging (2020-10-22 12:33:21 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201023

for you to fetch changes up to 51b6c1bbc3dd1b139a9e9b021d87bcfd7d82299e:

  hw/misc/sifive_u_otp: Add backend drive support (2020-10-22 12:00:50 -0700)

----------------------------------------------------------------
A collection of RISC-V fixes for the next QEMU release.

This includes:
 - Improvements to logging output
 - Hypervisor instruction fixups
 - The ability to load a noMMU kernel
 - SiFive OTP support

----------------------------------------------------------------
Alistair Francis (5):
      riscv: Convert interrupt logs to use qemu_log_mask()
      hw/riscv: sifive_u: Allow specifying the CPU
      hw/riscv: Return the end address of the loaded firmware
      hw/riscv: Add a riscv_is_32_bit() function
      hw/riscv: Load the kernel after the firmware

Bin Meng (1):
      hw/intc: Move sifive_plic.h to the include directory

Georg Kotheimer (3):
      target/riscv: Fix update of hstatus.SPVP
      target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt
      target/riscv: Fix implementation of HLVX.WU instruction

Green Wan (2):
      hw/misc/sifive_u_otp: Add write function and write-once protection
      hw/misc/sifive_u_otp: Add backend drive support

Yifei Jiang (1):
      target/riscv: raise exception to HS-mode at get_physical_address

 {hw => include/hw}/intc/sifive_plic.h |  0
 include/hw/misc/sifive_u_otp.h        |  5 ++
 include/hw/riscv/boot.h               | 13 +++--
 include/hw/riscv/sifive_u.h           |  1 +
 target/riscv/cpu.h                    | 10 ++--
 hw/misc/sifive_u_otp.c                | 95 ++++++++++++++++++++++++++++++++++-
 hw/riscv/boot.c                       | 56 +++++++++++++++------
 hw/riscv/opentitan.c                  |  3 +-
 hw/riscv/sifive_e.c                   |  3 +-
 hw/riscv/sifive_u.c                   | 28 ++++++++---
 hw/riscv/spike.c                      | 11 ++--
 hw/riscv/virt.c                       | 11 ++--
 target/riscv/cpu_helper.c             | 50 +++++++++++++-----
 target/riscv/op_helper.c              |  7 ++-
 14 files changed, 238 insertions(+), 55 deletions(-)
 rename {hw => include/hw}/intc/sifive_plic.h (100%)


^ permalink raw reply	[flat|nested] 23+ messages in thread
* [PULL 00/12] riscv-to-apply queue
@ 2021-01-17 21:53 Alistair Francis
  2021-01-18 12:03 ` Peter Maydell
  0 siblings, 1 reply; 23+ messages in thread
From: Alistair Francis @ 2021-01-17 21:53 UTC (permalink / raw)
  To: peter.maydell, qemu-devel; +Cc: Alistair Francis

The following changes since commit 825a215c003cd028e26c7d19aa5049d957345f43:

  Merge remote-tracking branch 'remotes/kraxel/tags/audio-20210115-pull-request' into staging (2021-01-15 22:21:21 +0000)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210117-3

for you to fetch changes up to a8259b53230782f5e0a0d66013655c4ed5d71b7e:

  riscv: Pass RISCVHartArrayState by pointer (2021-01-16 14:34:46 -0800)

----------------------------------------------------------------
First RISC-V PR for 6.0

This PR:
 - Fixes some issues with the m25p80
 - Improves GDB support for RISC-V
 - Fixes some Linux boot issues, specifiaclly 32-bit boot failures
 - Enforces PMP exceptions correctly
 - Fixes some Coverity issues

----------------------------------------------------------------
Alistair Francis (1):
      riscv: Pass RISCVHartArrayState by pointer

Atish Patra (2):
      RISC-V: Place DTB at 3GB boundary instead of 4GB
      target/riscv/pmp: Raise exception if no PMP entry is configured

Bin Meng (6):
      hw/block: m25p80: Don't write to flash if write is disabled
      hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
      target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
      target/riscv: Add CSR name in the CSR function table
      target/riscv: Generate the GDB XML file for CSR registers dynamically
      target/riscv: Remove built-in GDB XML files for CSRs

Green Wan (1):
      hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite

Sylvain Pelissier (1):
      gdb: riscv: Add target description

Xuzhou Cheng (1):
      hw/block: m25p80: Implement AAI-WP command support for SST flashes

 default-configs/targets/riscv32-linux-user.mak |   2 +-
 default-configs/targets/riscv32-softmmu.mak    |   2 +-
 default-configs/targets/riscv64-linux-user.mak |   2 +-
 default-configs/targets/riscv64-softmmu.mak    |   2 +-
 include/hw/riscv/boot.h                        |   6 +-
 target/riscv/cpu.h                             |  11 +
 target/riscv/pmp.h                             |   1 +
 hw/block/m25p80.c                              |  74 ++++++
 hw/misc/sifive_u_otp.c                         |  31 ++-
 hw/riscv/boot.c                                |  18 +-
 hw/riscv/sifive_u.c                            |  16 +-
 hw/riscv/spike.c                               |   8 +-
 hw/riscv/virt.c                                |   8 +-
 target/riscv/cpu.c                             |  25 ++
 target/riscv/csr.c                             | 342 ++++++++++++++++++-------
 target/riscv/gdbstub.c                         | 308 ++++------------------
 target/riscv/op_helper.c                       |   5 +
 target/riscv/pmp.c                             |   4 +-
 gdb-xml/riscv-32bit-csr.xml                    | 250 ------------------
 gdb-xml/riscv-64bit-csr.xml                    | 250 ------------------
 20 files changed, 463 insertions(+), 902 deletions(-)
 delete mode 100644 gdb-xml/riscv-32bit-csr.xml
 delete mode 100644 gdb-xml/riscv-64bit-csr.xml


^ permalink raw reply	[flat|nested] 23+ messages in thread
* [PULL 00/12] riscv-to-apply queue
@ 2022-09-23  4:06 Alistair Francis
  2022-09-26 19:28 ` Stefan Hajnoczi
  0 siblings, 1 reply; 23+ messages in thread
From: Alistair Francis @ 2022-09-23  4:06 UTC (permalink / raw)
  To: qemu-devel; +Cc: alistair23, Alistair Francis

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 6160d8ff81fb9fba70f5dad88d43ffd0fa44984c:

  Merge tag 'edgar/xilinx-next-2022-09-21.for-upstream' of https://github.com/edgarigl/qemu into staging (2022-09-22 13:24:28 -0400)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git pull-riscv-to-apply-20220923-2

for you to fetch changes up to a4260684f8e2c8722d1feae0d41d956fc4109007:

  hw/riscv/sifive_e: Fix inheritance of SiFiveEState (2022-09-23 09:11:34 +1000)

----------------------------------------------------------------
Second RISC-V PR for QEMU 7.2

* Fixup typos and register addresses for Ibex SPI
* Cleanup the RISC-V virt machine documentation
* Remove the sideleg and sedeleg CSR macros
* Fix the CSR check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}
* Remove fixed numbering from GDB xml feature files
* Allow setting the resetvec for the OpenTitan machine
* Check the correct exception cause in vector GDB stub
* Fix inheritance of SiFiveEState

----------------------------------------------------------------
Alex Bennée (1):
      docs/system: clean up code escape for riscv virt platform

Alistair Francis (3):
      target/riscv: Set the CPU resetvec directly
      hw/riscv: opentitan: Fixup resetvec
      hw/riscv: opentitan: Expose the resetvec as a SoC property

Andrew Burgess (2):
      target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml
      target/riscv: remove fixed numbering from GDB xml feature files

Bernhard Beschow (1):
      hw/riscv/sifive_e: Fix inheritance of SiFiveEState

Frank Chang (1):
      target/riscv: Check the correct exception cause in vector GDB stub

Rahul Pathak (1):
      target/riscv: Remove sideleg and sedeleg

Weiwei Li (1):
      target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}

Wilfred Mallawa (2):
      hw/ssi: ibex_spi: fixup typos in ibex_spi_host
      hw/ssi: ibex_spi: update reg addr

 docs/system/riscv/virt.rst   | 13 +++++++++----
 include/hw/riscv/opentitan.h |  2 ++
 include/hw/riscv/sifive_e.h  |  3 ++-
 target/riscv/cpu.h           |  3 +--
 target/riscv/cpu_bits.h      |  2 --
 disas/riscv.c                |  2 --
 hw/riscv/opentitan.c         |  8 +++++++-
 hw/ssi/ibex_spi_host.c       |  8 ++++----
 target/riscv/cpu.c           | 13 +++----------
 target/riscv/csr.c           | 13 +++++++++----
 target/riscv/gdbstub.c       | 36 ++++--------------------------------
 target/riscv/machine.c       |  6 +++---
 gdb-xml/riscv-32bit-cpu.xml  |  6 +-----
 gdb-xml/riscv-32bit-fpu.xml  | 10 +---------
 gdb-xml/riscv-64bit-cpu.xml  |  6 +-----
 gdb-xml/riscv-64bit-fpu.xml  | 10 +---------
 16 files changed, 48 insertions(+), 93 deletions(-)


^ permalink raw reply	[flat|nested] 23+ messages in thread
end of thread, other threads:[~2022-09-26 21:19 UTC | newest]

Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-23 15:16 [PULL 00/12] riscv-to-apply queue Alistair Francis
2020-10-23 15:16 ` [PULL 01/12] riscv: Convert interrupt logs to use qemu_log_mask() Alistair Francis
2020-10-23 15:16 ` [PULL 02/12] hw/intc: Move sifive_plic.h to the include directory Alistair Francis
2020-10-23 15:16 ` [PULL 03/12] target/riscv: Fix update of hstatus.SPVP Alistair Francis
2020-10-23 15:16 ` [PULL 04/12] target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt Alistair Francis
2020-10-23 15:16 ` [PULL 05/12] target/riscv: Fix implementation of HLVX.WU instruction Alistair Francis
2020-10-23 15:16 ` [PULL 06/12] hw/riscv: sifive_u: Allow specifying the CPU Alistair Francis
2020-10-23 15:16 ` [PULL 07/12] hw/riscv: Return the end address of the loaded firmware Alistair Francis
2020-10-23 15:16 ` [PULL 08/12] hw/riscv: Add a riscv_is_32_bit() function Alistair Francis
2020-10-23 15:16 ` [PULL 09/12] hw/riscv: Load the kernel after the firmware Alistair Francis
2020-10-23 15:16 ` [PULL 10/12] target/riscv: raise exception to HS-mode at get_physical_address Alistair Francis
2020-10-23 15:16 ` [PULL 11/12] hw/misc/sifive_u_otp: Add write function and write-once protection Alistair Francis
2020-10-23 15:16 ` [PULL 12/12] hw/misc/sifive_u_otp: Add backend drive support Alistair Francis
2020-11-02 17:49   ` Peter Maydell
2020-11-03 15:41     ` Alistair Francis
2020-11-04  8:19       ` Green Wan
2020-10-26 13:16 ` [PULL 00/12] riscv-to-apply queue Peter Maydell
2021-01-17 21:53 Alistair Francis
2021-01-18 12:03 ` Peter Maydell
2022-09-23  4:06 Alistair Francis
2022-09-26 19:28 ` Stefan Hajnoczi
2022-09-26 20:59   ` Alistair Francis
2022-09-26 21:04     ` Stefan Hajnoczi

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).