* [PATCH v4 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-11-01 8:59 ` Bin Meng
2021-10-26 6:42 ` [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs Anup Patel
` (20 subsequent siblings)
21 siblings, 1 reply; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra,
Alistair Francis, Bin Meng
We should be returning illegal instruction trap when RV64 HS-mode tries
to access RV32 HS-mode CSR.
Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions")
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 69e4d65fcd..9dfc9b5eba 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -181,7 +181,7 @@ static RISCVException hmode(CPURISCVState *env, int csrno)
static RISCVException hmode32(CPURISCVState *env, int csrno)
{
if (riscv_cpu_mxl(env) != MXL_RV32) {
- if (riscv_cpu_virt_enabled(env)) {
+ if (!riscv_cpu_virt_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
} else {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH v4 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
2021-10-26 6:42 ` [PATCH v4 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Anup Patel
@ 2021-11-01 8:59 ` Bin Meng
0 siblings, 0 replies; 41+ messages in thread
From: Bin Meng @ 2021-11-01 8:59 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt
On Tue, Oct 26, 2021 at 2:43 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> We should be returning illegal instruction trap when RV64 HS-mode tries
> to access RV32 HS-mode CSR.
>
> Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions")
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/csr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
2021-10-26 6:42 ` [PATCH v4 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-11-02 6:52 ` Bin Meng
2021-10-26 6:42 ` [PATCH v4 03/22] target/riscv: Implement hgeie and hgeip CSRs Anup Patel
` (19 subsequent siblings)
21 siblings, 1 reply; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra,
Alistair Francis, Bin Meng
A hypervsior can optionally take guest external interrupts using
SGEIP bit of hip and hie CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 3 ++-
target/riscv/cpu_bits.h | 3 +++
target/riscv/csr.c | 18 +++++++++++-------
3 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 788fa0b11c..0460a3972b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -365,6 +365,7 @@ static void riscv_cpu_reset(DeviceState *dev)
env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
}
env->mcause = 0;
+ env->miclaim = MIP_SGEIP;
env->pc = env->resetvec;
env->two_stage_lookup = false;
#endif
@@ -598,7 +599,7 @@ static void riscv_cpu_init(Object *obj)
cpu_set_cpustate_pointers(cpu);
#ifndef CONFIG_USER_ONLY
- qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12);
+ qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX);
#endif /* CONFIG_USER_ONLY */
}
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index cffcd3a5df..8a5a4cde95 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -498,6 +498,8 @@ typedef enum RISCVException {
#define IRQ_S_EXT 9
#define IRQ_VS_EXT 10
#define IRQ_M_EXT 11
+#define IRQ_S_GEXT 12
+#define IRQ_LOCAL_MAX 13
/* mip masks */
#define MIP_USIP (1 << IRQ_U_SOFT)
@@ -512,6 +514,7 @@ typedef enum RISCVException {
#define MIP_SEIP (1 << IRQ_S_EXT)
#define MIP_VSEIP (1 << IRQ_VS_EXT)
#define MIP_MEIP (1 << IRQ_M_EXT)
+#define MIP_SGEIP (1 << IRQ_S_GEXT)
/* sip masks */
#define SIP_SSIP MIP_SSIP
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9dfc9b5eba..9a0a0c0679 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -408,12 +408,13 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
#define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
#define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
+#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS)
static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
VS_MODE_INTERRUPTS;
static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
- VS_MODE_INTERRUPTS;
+ HS_MODE_INTERRUPTS;
#define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
(1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
(1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
@@ -673,7 +674,7 @@ static RISCVException write_mideleg(CPURISCVState *env, int csrno,
{
env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
if (riscv_has_ext(env, RVH)) {
- env->mideleg |= VS_MODE_INTERRUPTS;
+ env->mideleg |= HS_MODE_INTERRUPTS;
}
return RISCV_EXCP_NONE;
}
@@ -689,6 +690,9 @@ static RISCVException write_mie(CPURISCVState *env, int csrno,
target_ulong val)
{
env->mie = (env->mie & ~all_ints) | (val & all_ints);
+ if (!riscv_has_ext(env, RVH)) {
+ env->mie &= ~MIP_SGEIP;
+ }
return RISCV_EXCP_NONE;
}
@@ -984,7 +988,7 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno,
}
if (ret_value) {
- *ret_value &= env->mideleg;
+ *ret_value &= env->mideleg & S_MODE_INTERRUPTS;
}
return ret;
}
@@ -1102,7 +1106,7 @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
write_mask & hvip_writable_mask);
if (ret_value) {
- *ret_value &= hvip_writable_mask;
+ *ret_value &= VS_MODE_INTERRUPTS;
}
return ret;
}
@@ -1115,7 +1119,7 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
write_mask & hip_writable_mask);
if (ret_value) {
- *ret_value &= hip_writable_mask;
+ *ret_value &= HS_MODE_INTERRUPTS;
}
return ret;
}
@@ -1123,14 +1127,14 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
static RISCVException read_hie(CPURISCVState *env, int csrno,
target_ulong *val)
{
- *val = env->mie & VS_MODE_INTERRUPTS;
+ *val = env->mie & HS_MODE_INTERRUPTS;
return RISCV_EXCP_NONE;
}
static RISCVException write_hie(CPURISCVState *env, int csrno,
target_ulong val)
{
- target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
+ target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_MODE_INTERRUPTS);
return write_mie(env, CSR_MIE, newval);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs
2021-10-26 6:42 ` [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs Anup Patel
@ 2021-11-02 6:52 ` Bin Meng
2021-11-02 10:24 ` Anup Patel
0 siblings, 1 reply; 41+ messages in thread
From: Bin Meng @ 2021-11-02 6:52 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt
On Tue, Oct 26, 2021 at 2:43 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> A hypervsior can optionally take guest external interrupts using
typo: hypervisor
> SGEIP bit of hip and hie CSRs.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 3 ++-
> target/riscv/cpu_bits.h | 3 +++
> target/riscv/csr.c | 18 +++++++++++-------
> 3 files changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 788fa0b11c..0460a3972b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -365,6 +365,7 @@ static void riscv_cpu_reset(DeviceState *dev)
> env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
> }
> env->mcause = 0;
> + env->miclaim = MIP_SGEIP;
> env->pc = env->resetvec;
> env->two_stage_lookup = false;
> #endif
> @@ -598,7 +599,7 @@ static void riscv_cpu_init(Object *obj)
> cpu_set_cpustate_pointers(cpu);
>
> #ifndef CONFIG_USER_ONLY
> - qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12);
> + qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX);
> #endif /* CONFIG_USER_ONLY */
> }
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index cffcd3a5df..8a5a4cde95 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -498,6 +498,8 @@ typedef enum RISCVException {
> #define IRQ_S_EXT 9
> #define IRQ_VS_EXT 10
> #define IRQ_M_EXT 11
> +#define IRQ_S_GEXT 12
> +#define IRQ_LOCAL_MAX 13
The IRQ_LOCAL_MAX should be XLEN long, not 13.
>
> /* mip masks */
> #define MIP_USIP (1 << IRQ_U_SOFT)
> @@ -512,6 +514,7 @@ typedef enum RISCVException {
> #define MIP_SEIP (1 << IRQ_S_EXT)
> #define MIP_VSEIP (1 << IRQ_VS_EXT)
> #define MIP_MEIP (1 << IRQ_M_EXT)
> +#define MIP_SGEIP (1 << IRQ_S_GEXT)
>
> /* sip masks */
> #define SIP_SSIP MIP_SSIP
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 9dfc9b5eba..9a0a0c0679 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -408,12 +408,13 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
> #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
> #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
> #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
> +#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS)
>
> static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
> VS_MODE_INTERRUPTS;
> static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
> static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
> - VS_MODE_INTERRUPTS;
> + HS_MODE_INTERRUPTS;
> #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
> (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
> (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
> @@ -673,7 +674,7 @@ static RISCVException write_mideleg(CPURISCVState *env, int csrno,
> {
> env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
> if (riscv_has_ext(env, RVH)) {
> - env->mideleg |= VS_MODE_INTERRUPTS;
> + env->mideleg |= HS_MODE_INTERRUPTS;
> }
> return RISCV_EXCP_NONE;
> }
> @@ -689,6 +690,9 @@ static RISCVException write_mie(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> env->mie = (env->mie & ~all_ints) | (val & all_ints);
> + if (!riscv_has_ext(env, RVH)) {
> + env->mie &= ~MIP_SGEIP;
> + }
> return RISCV_EXCP_NONE;
> }
>
> @@ -984,7 +988,7 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno,
> }
>
> if (ret_value) {
> - *ret_value &= env->mideleg;
> + *ret_value &= env->mideleg & S_MODE_INTERRUPTS;
> }
> return ret;
> }
> @@ -1102,7 +1106,7 @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
> write_mask & hvip_writable_mask);
>
> if (ret_value) {
> - *ret_value &= hvip_writable_mask;
> + *ret_value &= VS_MODE_INTERRUPTS;
> }
> return ret;
> }
> @@ -1115,7 +1119,7 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
> write_mask & hip_writable_mask);
>
> if (ret_value) {
> - *ret_value &= hip_writable_mask;
> + *ret_value &= HS_MODE_INTERRUPTS;
> }
> return ret;
> }
> @@ -1123,14 +1127,14 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
> static RISCVException read_hie(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> - *val = env->mie & VS_MODE_INTERRUPTS;
> + *val = env->mie & HS_MODE_INTERRUPTS;
> return RISCV_EXCP_NONE;
> }
>
> static RISCVException write_hie(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> - target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
> + target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_MODE_INTERRUPTS);
> return write_mie(env, CSR_MIE, newval);
> }
>
Regards,
Bin
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs
2021-11-02 6:52 ` Bin Meng
@ 2021-11-02 10:24 ` Anup Patel
2021-11-02 10:52 ` Bin Meng
0 siblings, 1 reply; 41+ messages in thread
From: Anup Patel @ 2021-11-02 10:24 UTC (permalink / raw)
To: Bin Meng
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt
On Tue, Nov 2, 2021 at 12:22 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Tue, Oct 26, 2021 at 2:43 PM Anup Patel <anup.patel@wdc.com> wrote:
> >
> > A hypervsior can optionally take guest external interrupts using
>
> typo: hypervisor
Okay, I will update.
>
> > SGEIP bit of hip and hie CSRs.
> >
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > target/riscv/cpu.c | 3 ++-
> > target/riscv/cpu_bits.h | 3 +++
> > target/riscv/csr.c | 18 +++++++++++-------
> > 3 files changed, 16 insertions(+), 8 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 788fa0b11c..0460a3972b 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -365,6 +365,7 @@ static void riscv_cpu_reset(DeviceState *dev)
> > env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
> > }
> > env->mcause = 0;
> > + env->miclaim = MIP_SGEIP;
> > env->pc = env->resetvec;
> > env->two_stage_lookup = false;
> > #endif
> > @@ -598,7 +599,7 @@ static void riscv_cpu_init(Object *obj)
> > cpu_set_cpustate_pointers(cpu);
> >
> > #ifndef CONFIG_USER_ONLY
> > - qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12);
> > + qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX);
> > #endif /* CONFIG_USER_ONLY */
> > }
> >
> > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > index cffcd3a5df..8a5a4cde95 100644
> > --- a/target/riscv/cpu_bits.h
> > +++ b/target/riscv/cpu_bits.h
> > @@ -498,6 +498,8 @@ typedef enum RISCVException {
> > #define IRQ_S_EXT 9
> > #define IRQ_VS_EXT 10
> > #define IRQ_M_EXT 11
> > +#define IRQ_S_GEXT 12
> > +#define IRQ_LOCAL_MAX 13
>
> The IRQ_LOCAL_MAX should be XLEN long, not 13.
The IRQ_LOCAL_MAX here represents local interrupts
standardized by the RISC-V privilege spec. This value
will change only when more local interrupts are
standardized by the RISC-V privilege spec.
>
> >
> > /* mip masks */
> > #define MIP_USIP (1 << IRQ_U_SOFT)
> > @@ -512,6 +514,7 @@ typedef enum RISCVException {
> > #define MIP_SEIP (1 << IRQ_S_EXT)
> > #define MIP_VSEIP (1 << IRQ_VS_EXT)
> > #define MIP_MEIP (1 << IRQ_M_EXT)
> > +#define MIP_SGEIP (1 << IRQ_S_GEXT)
> >
> > /* sip masks */
> > #define SIP_SSIP MIP_SSIP
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index 9dfc9b5eba..9a0a0c0679 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -408,12 +408,13 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
> > #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
> > #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
> > #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
> > +#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS)
> >
> > static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
> > VS_MODE_INTERRUPTS;
> > static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
> > static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
> > - VS_MODE_INTERRUPTS;
> > + HS_MODE_INTERRUPTS;
> > #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
> > (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
> > (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
> > @@ -673,7 +674,7 @@ static RISCVException write_mideleg(CPURISCVState *env, int csrno,
> > {
> > env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
> > if (riscv_has_ext(env, RVH)) {
> > - env->mideleg |= VS_MODE_INTERRUPTS;
> > + env->mideleg |= HS_MODE_INTERRUPTS;
> > }
> > return RISCV_EXCP_NONE;
> > }
> > @@ -689,6 +690,9 @@ static RISCVException write_mie(CPURISCVState *env, int csrno,
> > target_ulong val)
> > {
> > env->mie = (env->mie & ~all_ints) | (val & all_ints);
> > + if (!riscv_has_ext(env, RVH)) {
> > + env->mie &= ~MIP_SGEIP;
> > + }
> > return RISCV_EXCP_NONE;
> > }
> >
> > @@ -984,7 +988,7 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno,
> > }
> >
> > if (ret_value) {
> > - *ret_value &= env->mideleg;
> > + *ret_value &= env->mideleg & S_MODE_INTERRUPTS;
> > }
> > return ret;
> > }
> > @@ -1102,7 +1106,7 @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
> > write_mask & hvip_writable_mask);
> >
> > if (ret_value) {
> > - *ret_value &= hvip_writable_mask;
> > + *ret_value &= VS_MODE_INTERRUPTS;
> > }
> > return ret;
> > }
> > @@ -1115,7 +1119,7 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
> > write_mask & hip_writable_mask);
> >
> > if (ret_value) {
> > - *ret_value &= hip_writable_mask;
> > + *ret_value &= HS_MODE_INTERRUPTS;
> > }
> > return ret;
> > }
> > @@ -1123,14 +1127,14 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
> > static RISCVException read_hie(CPURISCVState *env, int csrno,
> > target_ulong *val)
> > {
> > - *val = env->mie & VS_MODE_INTERRUPTS;
> > + *val = env->mie & HS_MODE_INTERRUPTS;
> > return RISCV_EXCP_NONE;
> > }
> >
> > static RISCVException write_hie(CPURISCVState *env, int csrno,
> > target_ulong val)
> > {
> > - target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
> > + target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_MODE_INTERRUPTS);
> > return write_mie(env, CSR_MIE, newval);
> > }
> >
>
> Regards,
> Bin
Regards,
Anup
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs
2021-11-02 10:24 ` Anup Patel
@ 2021-11-02 10:52 ` Bin Meng
2021-11-03 5:30 ` Anup Patel
0 siblings, 1 reply; 41+ messages in thread
From: Bin Meng @ 2021-11-02 10:52 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt
On Tue, Nov 2, 2021 at 6:24 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Tue, Nov 2, 2021 at 12:22 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > On Tue, Oct 26, 2021 at 2:43 PM Anup Patel <anup.patel@wdc.com> wrote:
> > >
> > > A hypervsior can optionally take guest external interrupts using
> >
> > typo: hypervisor
>
> Okay, I will update.
>
> >
> > > SGEIP bit of hip and hie CSRs.
> > >
> > > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > > ---
> > > target/riscv/cpu.c | 3 ++-
> > > target/riscv/cpu_bits.h | 3 +++
> > > target/riscv/csr.c | 18 +++++++++++-------
> > > 3 files changed, 16 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > index 788fa0b11c..0460a3972b 100644
> > > --- a/target/riscv/cpu.c
> > > +++ b/target/riscv/cpu.c
> > > @@ -365,6 +365,7 @@ static void riscv_cpu_reset(DeviceState *dev)
> > > env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
> > > }
> > > env->mcause = 0;
> > > + env->miclaim = MIP_SGEIP;
> > > env->pc = env->resetvec;
> > > env->two_stage_lookup = false;
> > > #endif
> > > @@ -598,7 +599,7 @@ static void riscv_cpu_init(Object *obj)
> > > cpu_set_cpustate_pointers(cpu);
> > >
> > > #ifndef CONFIG_USER_ONLY
> > > - qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12);
> > > + qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX);
> > > #endif /* CONFIG_USER_ONLY */
> > > }
> > >
> > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > > index cffcd3a5df..8a5a4cde95 100644
> > > --- a/target/riscv/cpu_bits.h
> > > +++ b/target/riscv/cpu_bits.h
> > > @@ -498,6 +498,8 @@ typedef enum RISCVException {
> > > #define IRQ_S_EXT 9
> > > #define IRQ_VS_EXT 10
> > > #define IRQ_M_EXT 11
> > > +#define IRQ_S_GEXT 12
> > > +#define IRQ_LOCAL_MAX 13
> >
> > The IRQ_LOCAL_MAX should be XLEN long, not 13.
>
> The IRQ_LOCAL_MAX here represents local interrupts
> standardized by the RISC-V privilege spec. This value
The standardardized IRQ number is 16.
> will change only when more local interrupts are
> standardized by the RISC-V privilege spec.
We should leave room for platform / custom IRQ as it is already
defined by the priv spec.
Regards,
Bin
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs
2021-11-02 10:52 ` Bin Meng
@ 2021-11-03 5:30 ` Anup Patel
0 siblings, 0 replies; 41+ messages in thread
From: Anup Patel @ 2021-11-03 5:30 UTC (permalink / raw)
To: Bin Meng
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt
On Tue, Nov 2, 2021 at 4:22 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Tue, Nov 2, 2021 at 6:24 PM Anup Patel <anup@brainfault.org> wrote:
> >
> > On Tue, Nov 2, 2021 at 12:22 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > On Tue, Oct 26, 2021 at 2:43 PM Anup Patel <anup.patel@wdc.com> wrote:
> > > >
> > > > A hypervsior can optionally take guest external interrupts using
> > >
> > > typo: hypervisor
> >
> > Okay, I will update.
> >
> > >
> > > > SGEIP bit of hip and hie CSRs.
> > > >
> > > > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > > > ---
> > > > target/riscv/cpu.c | 3 ++-
> > > > target/riscv/cpu_bits.h | 3 +++
> > > > target/riscv/csr.c | 18 +++++++++++-------
> > > > 3 files changed, 16 insertions(+), 8 deletions(-)
> > > >
> > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > > index 788fa0b11c..0460a3972b 100644
> > > > --- a/target/riscv/cpu.c
> > > > +++ b/target/riscv/cpu.c
> > > > @@ -365,6 +365,7 @@ static void riscv_cpu_reset(DeviceState *dev)
> > > > env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
> > > > }
> > > > env->mcause = 0;
> > > > + env->miclaim = MIP_SGEIP;
> > > > env->pc = env->resetvec;
> > > > env->two_stage_lookup = false;
> > > > #endif
> > > > @@ -598,7 +599,7 @@ static void riscv_cpu_init(Object *obj)
> > > > cpu_set_cpustate_pointers(cpu);
> > > >
> > > > #ifndef CONFIG_USER_ONLY
> > > > - qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12);
> > > > + qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX);
> > > > #endif /* CONFIG_USER_ONLY */
> > > > }
> > > >
> > > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > > > index cffcd3a5df..8a5a4cde95 100644
> > > > --- a/target/riscv/cpu_bits.h
> > > > +++ b/target/riscv/cpu_bits.h
> > > > @@ -498,6 +498,8 @@ typedef enum RISCVException {
> > > > #define IRQ_S_EXT 9
> > > > #define IRQ_VS_EXT 10
> > > > #define IRQ_M_EXT 11
> > > > +#define IRQ_S_GEXT 12
> > > > +#define IRQ_LOCAL_MAX 13
> > >
> > > The IRQ_LOCAL_MAX should be XLEN long, not 13.
> >
> > The IRQ_LOCAL_MAX here represents local interrupts
> > standardized by the RISC-V privilege spec. This value
>
> The standardardized IRQ number is 16.
Max local IRQ as 13 is more conservative and better (IMO)
because we are not including any undefined local IRQ.
I also totally fine changing max local IRQ to 16 as well.
>
> > will change only when more local interrupts are
> > standardized by the RISC-V privilege spec.
>
> We should leave room for platform / custom IRQ as it is already
> defined by the priv spec.
custom local IRQs are not going to be accepted in the first 16 local
IRQs.
The AIA spec defines a sparse numbering scheme for both
standard/custom local IRQs beyond 16. The AIA spec will also
maintain a table of defined local IRQs.
IMO, we should deal with custom local IRQs as when they show
up and standard local IRQs should always get first class treatment.
Regards,
Anup
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v4 03/22] target/riscv: Implement hgeie and hgeip CSRs
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
2021-10-26 6:42 ` [PATCH v4 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Anup Patel
2021-10-26 6:42 ` [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts Anup Patel
` (18 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra,
Alistair Francis, Bin Meng
The hgeie and hgeip CSRs are required for emulating an external
interrupt controller capable of injecting virtual external
interrupt to Guest/VM running at VS-level.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 61 ++++++++++++++++++++++++++++-----------
target/riscv/cpu.h | 5 ++++
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 36 +++++++++++++++++++++--
target/riscv/csr.c | 43 ++++++++++++++++++---------
target/riscv/machine.c | 6 ++--
6 files changed, 117 insertions(+), 35 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0460a3972b..8042c4ebcf 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -570,23 +570,49 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
static void riscv_cpu_set_irq(void *opaque, int irq, int level)
{
RISCVCPU *cpu = RISCV_CPU(opaque);
+ CPURISCVState *env = &cpu->env;
- switch (irq) {
- case IRQ_U_SOFT:
- case IRQ_S_SOFT:
- case IRQ_VS_SOFT:
- case IRQ_M_SOFT:
- case IRQ_U_TIMER:
- case IRQ_S_TIMER:
- case IRQ_VS_TIMER:
- case IRQ_M_TIMER:
- case IRQ_U_EXT:
- case IRQ_S_EXT:
- case IRQ_VS_EXT:
- case IRQ_M_EXT:
- riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
- break;
- default:
+ if (irq < IRQ_LOCAL_MAX) {
+ switch (irq) {
+ case IRQ_U_SOFT:
+ case IRQ_S_SOFT:
+ case IRQ_VS_SOFT:
+ case IRQ_M_SOFT:
+ case IRQ_U_TIMER:
+ case IRQ_S_TIMER:
+ case IRQ_VS_TIMER:
+ case IRQ_M_TIMER:
+ case IRQ_U_EXT:
+ case IRQ_S_EXT:
+ case IRQ_VS_EXT:
+ case IRQ_M_EXT:
+ riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) {
+ /* Require H-extension for handling guest local interrupts */
+ if (!riscv_has_ext(env, RVH)) {
+ g_assert_not_reached();
+ }
+
+ /* Compute bit position in HGEIP CSR */
+ irq = irq - IRQ_LOCAL_MAX + 1;
+ if (env->geilen < irq) {
+ g_assert_not_reached();
+ }
+
+ /* Update HGEIP CSR */
+ env->hgeip &= ~((target_ulong)1 << irq);
+ if (level) {
+ env->hgeip |= (target_ulong)1 << irq;
+ }
+
+ /* Update mip.SGEIP bit */
+ riscv_cpu_update_mip(cpu, MIP_SGEIP,
+ BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
+ } else {
g_assert_not_reached();
}
}
@@ -599,7 +625,8 @@ static void riscv_cpu_init(Object *obj)
cpu_set_cpustate_pointers(cpu);
#ifndef CONFIG_USER_ONLY
- qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX);
+ qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
+ IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
#endif /* CONFIG_USER_ONLY */
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a33dc30be8..bbf469f079 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -148,6 +148,7 @@ struct CPURISCVState {
target_ulong priv;
/* This contains QEMU specific information about the virt state. */
target_ulong virt;
+ target_ulong geilen;
target_ulong resetvec;
target_ulong mhartid;
@@ -185,6 +186,8 @@ struct CPURISCVState {
target_ulong htval;
target_ulong htinst;
target_ulong hgatp;
+ target_ulong hgeie;
+ target_ulong hgeip;
uint64_t htimedelta;
/* Virtual CSRs */
@@ -337,6 +340,8 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
+target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
+void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8a5a4cde95..335e0193a9 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -500,6 +500,7 @@ typedef enum RISCVException {
#define IRQ_M_EXT 11
#define IRQ_S_GEXT 12
#define IRQ_LOCAL_MAX 13
+#define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1)
/* mip masks */
#define MIP_USIP (1 << IRQ_U_SOFT)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 0d1132f39d..bb7ac9890b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -125,7 +125,10 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
target_ulong pending = env->mip & env->mie &
~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
- target_ulong vspending = (env->mip & env->mie &
+ target_ulong vsgemask =
+ (target_ulong)1 << get_field(env->hstatus, HSTATUS_VGEIN);
+ target_ulong vsgein = (env->hgeip & vsgemask) ? MIP_VSEIP : 0;
+ target_ulong vspending = ((env->mip | vsgein) & env->mie &
(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP));
target_ulong mie = env->priv < PRV_M ||
@@ -241,6 +244,28 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
}
}
+target_ulong riscv_cpu_get_geilen(CPURISCVState *env)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return 0;
+ }
+
+ return env->geilen;
+}
+
+void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return;
+ }
+
+ if (geilen > (TARGET_LONG_BITS - 1)) {
+ return;
+ }
+
+ env->geilen = geilen;
+}
+
bool riscv_cpu_virt_enabled(CPURISCVState *env)
{
if (!riscv_has_ext(env, RVH)) {
@@ -302,9 +327,14 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
{
CPURISCVState *env = &cpu->env;
CPUState *cs = CPU(cpu);
- uint32_t old = env->mip;
+ uint32_t gein, vsgein = 0, old = env->mip;
bool locked = false;
+ if (riscv_cpu_virt_enabled(env)) {
+ gein = get_field(env->hstatus, HSTATUS_VGEIN);
+ vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
+ }
+
if (!qemu_mutex_iothread_locked()) {
locked = true;
qemu_mutex_lock_iothread();
@@ -312,7 +342,7 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
env->mip = (env->mip & ~mask) | (value & mask);
- if (env->mip) {
+ if (env->mip | vsgein) {
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9a0a0c0679..7ff285282b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -793,7 +793,7 @@ static RISCVException rmw_mip(CPURISCVState *env, int csrno,
RISCVCPU *cpu = env_archcpu(env);
/* Allow software control of delegable interrupts not claimed by hardware */
target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
- uint32_t old_mip;
+ uint32_t gin, old_mip;
if (mask) {
old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
@@ -801,6 +801,11 @@ static RISCVException rmw_mip(CPURISCVState *env, int csrno,
old_mip = env->mip;
}
+ if (csrno != CSR_HVIP) {
+ gin = get_field(env->hstatus, HSTATUS_VGEIN);
+ old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0;
+ }
+
if (ret_value) {
*ret_value = old_mip;
}
@@ -963,7 +968,7 @@ static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
target_ulong new_value, target_ulong write_mask)
{
/* Shift the S bits to their VS bit location in mip */
- int ret = rmw_mip(env, 0, ret_value, new_value << 1,
+ int ret = rmw_mip(env, csrno, ret_value, new_value << 1,
(write_mask << 1) & vsip_writable_mask & env->hideleg);
if (ret_value) {
@@ -983,7 +988,7 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno,
if (riscv_cpu_virt_enabled(env)) {
ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
} else {
- ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
+ ret = rmw_mip(env, csrno, ret_value, new_value,
write_mask & env->mideleg & sip_writable_mask);
}
@@ -1102,7 +1107,7 @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
- int ret = rmw_mip(env, 0, ret_value, new_value,
+ int ret = rmw_mip(env, csrno, ret_value, new_value,
write_mask & hvip_writable_mask);
if (ret_value) {
@@ -1115,7 +1120,7 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
- int ret = rmw_mip(env, 0, ret_value, new_value,
+ int ret = rmw_mip(env, csrno, ret_value, new_value,
write_mask & hip_writable_mask);
if (ret_value) {
@@ -1152,15 +1157,27 @@ static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
-static RISCVException write_hgeie(CPURISCVState *env, int csrno,
- target_ulong val)
+static RISCVException read_hgeie(CPURISCVState *env, int csrno,
+ target_ulong *val)
{
if (val) {
- qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+ *val = env->hgeie;
}
return RISCV_EXCP_NONE;
}
+static RISCVException write_hgeie(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ /* Only GEILEN:1 bits implemented and BIT0 is never implemented */
+ val &= ((((target_ulong)1) << env->geilen) - 1) << 1;
+ env->hgeie = val;
+ /* Update mip.SGEIP bit */
+ riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP,
+ BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_htval(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -1188,11 +1205,11 @@ static RISCVException write_htinst(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
-static RISCVException write_hgeip(CPURISCVState *env, int csrno,
- target_ulong val)
+static RISCVException read_hgeip(CPURISCVState *env, int csrno,
+ target_ulong *val)
{
if (val) {
- qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+ *val = env->hgeip;
}
return RISCV_EXCP_NONE;
}
@@ -1619,10 +1636,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip },
[CSR_HIE] = { "hie", hmode, read_hie, write_hie },
[CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren },
- [CSR_HGEIE] = { "hgeie", hmode, read_zero, write_hgeie },
+ [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie },
[CSR_HTVAL] = { "htval", hmode, read_htval, write_htval },
[CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst },
- [CSR_HGEIP] = { "hgeip", hmode, read_zero, write_hgeip },
+ [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, NULL },
[CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp },
[CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta },
[CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index f64b2a96c1..fe99ec7304 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -102,8 +102,8 @@ static const VMStateDescription vmstate_vector = {
static const VMStateDescription vmstate_hyper = {
.name = "cpu/hyper",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.needed = hyper_needed,
.fields = (VMStateField[]) {
VMSTATE_UINTTL(env.hstatus, RISCVCPU),
@@ -113,6 +113,8 @@ static const VMStateDescription vmstate_hyper = {
VMSTATE_UINTTL(env.htval, RISCVCPU),
VMSTATE_UINTTL(env.htinst, RISCVCPU),
VMSTATE_UINTTL(env.hgatp, RISCVCPU),
+ VMSTATE_UINTTL(env.hgeie, RISCVCPU),
+ VMSTATE_UINTTL(env.hgeip, RISCVCPU),
VMSTATE_UINT64(env.htimedelta, RISCVCPU),
VMSTATE_UINT64(env.vsstatus, RISCVCPU),
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
` (2 preceding siblings ...)
2021-10-26 6:42 ` [PATCH v4 03/22] target/riscv: Implement hgeie and hgeip CSRs Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-10-31 23:35 ` Alistair Francis
2021-10-26 6:42 ` [PATCH v4 05/22] target/riscv: Allow setting CPU feature from machine/device emulation Anup Patel
` (17 subsequent siblings)
21 siblings, 1 reply; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra, Bin Meng
The guest external interrupts from an interrupt controller are
delivered only when the Guest/VM is running (i.e. V=1). This means
any guest external interrupt which is triggered while the Guest/VM
is not running (i.e. V=0) will be missed on QEMU resulting in Guest
with sluggish response to serial console input and other I/O events.
To solve this, we check and inject interrupt after setting V=1.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
target/riscv/cpu_helper.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index bb7ac9890b..04df3792a8 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -287,6 +287,19 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
}
env->virt = set_field(env->virt, VIRT_ONOFF, enable);
+
+ if (enable) {
+ /*
+ * The guest external interrupts from an interrupt controller are
+ * delivered only when the Guest/VM is running (i.e. V=1). This means
+ * any guest external interrupt which is triggered while the Guest/VM
+ * is not running (i.e. V=0) will be missed on QEMU resulting in guest
+ * with sluggish response to serial console input and other I/O events.
+ *
+ * To solve this, we check and inject interrupt after setting V=1.
+ */
+ riscv_cpu_update_mip(env_archcpu(env), 0, 0);
+ }
}
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env)
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts
2021-10-26 6:42 ` [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts Anup Patel
@ 2021-10-31 23:35 ` Alistair Francis
0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2021-10-31 23:35 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt, Bin Meng
On Tue, Oct 26, 2021 at 5:41 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> The guest external interrupts from an interrupt controller are
> delivered only when the Guest/VM is running (i.e. V=1). This means
> any guest external interrupt which is triggered while the Guest/VM
> is not running (i.e. V=0) will be missed on QEMU resulting in Guest
> with sluggish response to serial console input and other I/O events.
>
> To solve this, we check and inject interrupt after setting V=1.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_helper.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index bb7ac9890b..04df3792a8 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -287,6 +287,19 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
> }
>
> env->virt = set_field(env->virt, VIRT_ONOFF, enable);
> +
> + if (enable) {
> + /*
> + * The guest external interrupts from an interrupt controller are
> + * delivered only when the Guest/VM is running (i.e. V=1). This means
> + * any guest external interrupt which is triggered while the Guest/VM
> + * is not running (i.e. V=0) will be missed on QEMU resulting in guest
> + * with sluggish response to serial console input and other I/O events.
> + *
> + * To solve this, we check and inject interrupt after setting V=1.
> + */
> + riscv_cpu_update_mip(env_archcpu(env), 0, 0);
> + }
> }
>
> bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env)
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v4 05/22] target/riscv: Allow setting CPU feature from machine/device emulation
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
` (3 preceding siblings ...)
2021-10-26 6:42 ` [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 06/22] target/riscv: Add AIA cpu feature Anup Patel
` (16 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra,
Alistair Francis, Bin Meng
The machine or device emulation should be able to force set certain
CPU features because:
1) We can have certain CPU features which are in-general optional
but implemented by RISC-V CPUs on the machine.
2) We can have devices which require a certain CPU feature. For example,
AIA IMSIC devices expect AIA CSRs implemented by RISC-V CPUs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 11 +++--------
target/riscv/cpu.h | 5 +++++
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8042c4ebcf..69d6b5eb36 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -124,11 +124,6 @@ static void set_vext_version(CPURISCVState *env, int vext_ver)
env->vext_ver = vext_ver;
}
-static void set_feature(CPURISCVState *env, int feature)
-{
- env->features |= (1ULL << feature);
-}
-
static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
{
#ifndef CONFIG_USER_ONLY
@@ -425,18 +420,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
if (cpu->cfg.mmu) {
- set_feature(env, RISCV_FEATURE_MMU);
+ riscv_set_feature(env, RISCV_FEATURE_MMU);
}
if (cpu->cfg.pmp) {
- set_feature(env, RISCV_FEATURE_PMP);
+ riscv_set_feature(env, RISCV_FEATURE_PMP);
/*
* Enhanced PMP should only be available
* on harts with PMP support
*/
if (cpu->cfg.epmp) {
- set_feature(env, RISCV_FEATURE_EPMP);
+ riscv_set_feature(env, RISCV_FEATURE_EPMP);
}
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bbf469f079..cc035a8897 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -326,6 +326,11 @@ static inline bool riscv_feature(CPURISCVState *env, int feature)
return env->features & (1ULL << feature);
}
+static inline void riscv_set_feature(CPURISCVState *env, int feature)
+{
+ env->features |= (1ULL << feature);
+}
+
#include "cpu_user.h"
extern const char * const riscv_int_regnames[];
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v4 06/22] target/riscv: Add AIA cpu feature
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
` (4 preceding siblings ...)
2021-10-26 6:42 ` [PATCH v4 05/22] target/riscv: Allow setting CPU feature from machine/device emulation Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs Anup Patel
` (15 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra,
Alistair Francis, Bin Meng
We define a CPU feature for AIA CSR support in RISC-V CPUs which
can be set by machine/device emulation. The RISC-V CSR emulation
will also check this feature for emulating AIA CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index cc035a8897..7182fadd21 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -74,7 +74,8 @@ enum {
RISCV_FEATURE_MMU,
RISCV_FEATURE_PMP,
RISCV_FEATURE_EPMP,
- RISCV_FEATURE_MISA
+ RISCV_FEATURE_MISA,
+ RISCV_FEATURE_AIA
};
#define PRIV_VERSION_1_10_0 0x00011000
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
` (5 preceding siblings ...)
2021-10-26 6:42 ` [PATCH v4 06/22] target/riscv: Add AIA cpu feature Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-11-01 6:55 ` Alistair Francis
2021-10-26 6:42 ` [PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback Anup Patel
` (14 subsequent siblings)
21 siblings, 1 reply; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra, Bin Meng
The RISC-V AIA specification extends RISC-V local interrupts and
introduces new CSRs. This patch adds defines for the new AIA CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
target/riscv/cpu_bits.h | 128 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 128 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 335e0193a9..0a79784d99 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -160,6 +160,31 @@
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
+/* Machine-Level Window to Indirectly Accessed Registers (AIA) */
+#define CSR_MISELECT 0x350
+#define CSR_MIREG 0x351
+
+/* Machine-Level Interrupts (AIA) */
+#define CSR_MTOPI 0xfb0
+
+/* Machine-Level IMSIC Interface (AIA) */
+#define CSR_MSETEIPNUM 0x358
+#define CSR_MCLREIPNUM 0x359
+#define CSR_MSETEIENUM 0x35a
+#define CSR_MCLREIENUM 0x35b
+#define CSR_MTOPEI 0x35c
+
+/* Virtual Interrupts for Supervisor Level (AIA) */
+#define CSR_MVIEN 0x308
+#define CSR_MVIP 0x309
+
+/* Machine-Level High-Half CSRs (AIA) */
+#define CSR_MIDELEGH 0x313
+#define CSR_MIEH 0x314
+#define CSR_MVIENH 0x318
+#define CSR_MVIPH 0x319
+#define CSR_MIPH 0x354
+
/* Supervisor Trap Setup */
#define CSR_SSTATUS 0x100
#define CSR_SEDELEG 0x102
@@ -179,6 +204,24 @@
#define CSR_SPTBR 0x180
#define CSR_SATP 0x180
+/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
+#define CSR_SISELECT 0x150
+#define CSR_SIREG 0x151
+
+/* Supervisor-Level Interrupts (AIA) */
+#define CSR_STOPI 0xdb0
+
+/* Supervisor-Level IMSIC Interface (AIA) */
+#define CSR_SSETEIPNUM 0x158
+#define CSR_SCLREIPNUM 0x159
+#define CSR_SSETEIENUM 0x15a
+#define CSR_SCLREIENUM 0x15b
+#define CSR_STOPEI 0x15c
+
+/* Supervisor-Level High-Half CSRs (AIA) */
+#define CSR_SIEH 0x114
+#define CSR_SIPH 0x154
+
/* Hpervisor CSRs */
#define CSR_HSTATUS 0x600
#define CSR_HEDELEG 0x602
@@ -209,6 +252,35 @@
#define CSR_MTINST 0x34a
#define CSR_MTVAL2 0x34b
+/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
+#define CSR_HVIEN 0x608
+#define CSR_HVICTL 0x609
+#define CSR_HVIPRIO1 0x646
+#define CSR_HVIPRIO2 0x647
+
+/* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */
+#define CSR_VSISELECT 0x250
+#define CSR_VSIREG 0x251
+
+/* VS-Level Interrupts (H-extension with AIA) */
+#define CSR_VSTOPI 0xeb0
+
+/* VS-Level IMSIC Interface (H-extension with AIA) */
+#define CSR_VSSETEIPNUM 0x258
+#define CSR_VSCLREIPNUM 0x259
+#define CSR_VSSETEIENUM 0x25a
+#define CSR_VSCLREIENUM 0x25b
+#define CSR_VSTOPEI 0x25c
+
+/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
+#define CSR_HIDELEGH 0x613
+#define CSR_HVIENH 0x618
+#define CSR_HVIPH 0x655
+#define CSR_HVIPRIO1H 0x656
+#define CSR_HVIPRIO2H 0x657
+#define CSR_VSIEH 0x214
+#define CSR_VSIPH 0x254
+
/* Enhanced Physical Memory Protection (ePMP) */
#define CSR_MSECCFG 0x747
#define CSR_MSECCFGH 0x757
@@ -529,4 +601,60 @@ typedef enum RISCVException {
#define MIE_UTIE (1 << IRQ_U_TIMER)
#define MIE_SSIE (1 << IRQ_S_SOFT)
#define MIE_USIE (1 << IRQ_U_SOFT)
+
+/* MISELECT, SISELECT, and VSISELECT bits (AIA) */
+#define ISELECT_IPRIO0 0x30
+#define ISELECT_IPRIO15 0x3f
+#define ISELECT_IMSIC_EIDELIVERY 0x70
+#define ISELECT_IMSIC_EITHRESHOLD 0x72
+#define ISELECT_IMSIC_EIP0 0x80
+#define ISELECT_IMSIC_EIP63 0xbf
+#define ISELECT_IMSIC_EIE0 0xc0
+#define ISELECT_IMSIC_EIE63 0xff
+#define ISELECT_IMSIC_FIRST ISELECT_IMSIC_EIDELIVERY
+#define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63
+#define ISELECT_MASK 0x1ff
+
+/* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */
+#define ISELECT_IMSIC_TOPEI (ISELECT_MASK + 1)
+
+/* IMSIC bits (AIA) */
+#define IMSIC_TOPEI_IID_SHIFT 16
+#define IMSIC_TOPEI_IID_MASK 0x7ff
+#define IMSIC_TOPEI_IPRIO_MASK 0x7ff
+#define IMSIC_EIPx_BITS 32
+#define IMSIC_EIEx_BITS 32
+
+/* MTOPI and STOPI bits (AIA) */
+#define TOPI_IID_SHIFT 16
+#define TOPI_IID_MASK 0xfff
+#define TOPI_IPRIO_MASK 0xff
+
+/* Interrupt priority bits (AIA) */
+#define IPRIO_IRQ_BITS 8
+#define IPRIO_MMAXIPRIO 255
+#define IPRIO_DEFAULT_MMAXIPRIO 15
+#define IPRIO_DEFAULT_VS (IPRIO_DEFAULT_MMAXIPRIO - 4)
+#define IPRIO_DEFAULT_SGEXT (IPRIO_DEFAULT_MMAXIPRIO - 5)
+#define IPRIO_DEFAULT_S (IPRIO_DEFAULT_MMAXIPRIO - 6)
+#define IPRIO_DEFAULT_M (IPRIO_DEFAULT_MMAXIPRIO - 7)
+#define IPRIO_DEFAULT_U(_i) (((_i) >> 4) & 0x3)
+#define IPRIO_DEFAULT_L(_i) ((_i) & 0xf)
+#define IPRIO_DEFAULT_16_23(_i) \
+ (IPRIO_DEFAULT_MMAXIPRIO - (IPRIO_DEFAULT_L(_i) >> 1))
+#define IPRIO_DEFAULT_24_31(_i) \
+ (IPRIO_DEFAULT_MMAXIPRIO - (4 + (IPRIO_DEFAULT_L(_i) >> 1)))
+#define IPRIO_DEFAULT_32_47(_i) \
+ (IPRIO_DEFAULT_MMAXIPRIO - (IPRIO_DEFAULT_L(_i) >> 2))
+#define IPRIO_DEFAULT_48_63(_i) \
+ (IPRIO_DEFAULT_MMAXIPRIO - (8 + (IPRIO_DEFAULT_L(_i) >> 2)))
+
+/* HVICTL bits (AIA) */
+#define HVICTL_VTI 0x40000000
+#define HVICTL_IID 0x0fff0000
+#define HVICTL_IPRIOM 0x00000100
+#define HVICTL_IPRIO 0x000000ff
+#define HVICTL_VALID_MASK \
+ (HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO)
+
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs
2021-10-26 6:42 ` [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs Anup Patel
@ 2021-11-01 6:55 ` Alistair Francis
2021-11-01 7:57 ` Anup Patel
0 siblings, 1 reply; 41+ messages in thread
From: Alistair Francis @ 2021-11-01 6:55 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt, Bin Meng
On Tue, Oct 26, 2021 at 5:01 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> The RISC-V AIA specification extends RISC-V local interrupts and
> introduces new CSRs. This patch adds defines for the new AIA CSRs.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
What's the status of these CSR addresses being finalised?
Alistair
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs
2021-11-01 6:55 ` Alistair Francis
@ 2021-11-01 7:57 ` Anup Patel
2021-11-03 5:57 ` Alistair Francis
0 siblings, 1 reply; 41+ messages in thread
From: Anup Patel @ 2021-11-01 7:57 UTC (permalink / raw)
To: Alistair Francis
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt, Bin Meng
On Mon, Nov 1, 2021 at 12:26 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Tue, Oct 26, 2021 at 5:01 PM Anup Patel <anup.patel@wdc.com> wrote:
> >
> > The RISC-V AIA specification extends RISC-V local interrupts and
> > introduces new CSRs. This patch adds defines for the new AIA CSRs.
> >
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
>
> What's the status of these CSR addresses being finalised?
These CSR addresses have not changed since the past 2 months.
Overall, the AIA spec has been in stable state for quite some time
without much changes or objections.
Regards,
Anup
>
> Alistair
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs
2021-11-01 7:57 ` Anup Patel
@ 2021-11-03 5:57 ` Alistair Francis
0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2021-11-03 5:57 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt, Bin Meng
On Mon, Nov 1, 2021 at 5:57 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Mon, Nov 1, 2021 at 12:26 PM Alistair Francis <alistair23@gmail.com> wrote:
> >
> > On Tue, Oct 26, 2021 at 5:01 PM Anup Patel <anup.patel@wdc.com> wrote:
> > >
> > > The RISC-V AIA specification extends RISC-V local interrupts and
> > > introduces new CSRs. This patch adds defines for the new AIA CSRs.
> > >
> > > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> >
> > What's the status of these CSR addresses being finalised?
>
> These CSR addresses have not changed since the past 2 months.
>
> Overall, the AIA spec has been in stable state for quite some time
> without much changes or objections.
Let's at least get a CSR address request submitted so we can start to
finalise on the addresses.
Alistair
>
> Regards,
> Anup
>
> >
> > Alistair
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
` (6 preceding siblings ...)
2021-10-26 6:42 ` [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-11-04 4:52 ` Alistair Francis
2021-10-26 6:42 ` [PATCH v4 09/22] target/riscv: Implement AIA local interrupt priorities Anup Patel
` (13 subsequent siblings)
21 siblings, 1 reply; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra, Bin Meng
The AIA device emulation (such as AIA IMSIC) should be able to set
(or provide) AIA ireg read-modify-write callback for each privilege
level of a RISC-V HART.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
target/riscv/cpu.h | 19 +++++++++++++++++++
target/riscv/cpu_helper.c | 14 ++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7182fadd21..ef4298dc69 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -239,6 +239,18 @@ struct CPURISCVState {
uint64_t (*rdtime_fn)(uint32_t);
uint32_t rdtime_fn_arg;
+ /* machine specific AIA ireg read-modify-write callback */
+#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein) \
+ ((((__vgein) & 0x3f) << 24) | (((__virt) & 0x1) << 20) | \
+ (((__priv) & 0x3) << 16) | (__isel & 0xffff))
+#define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff)
+#define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3)
+#define AIA_IREG_VIRT(__ireg) (((__ireg) >> 20) & 0x1)
+#define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 24) & 0x3f)
+ int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg,
+ target_ulong *val, target_ulong new_val, target_ulong write_mask);
+ void *aia_ireg_rmw_fn_arg[4];
+
/* True if in debugger mode. */
bool debugger;
#endif
@@ -380,6 +392,13 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
uint32_t arg);
+void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
+ int (*rmw_fn)(void *arg,
+ target_ulong reg,
+ target_ulong *val,
+ target_ulong new_val,
+ target_ulong write_mask),
+ void *rmw_fn_arg);
#endif
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 04df3792a8..d70def1da8 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -375,6 +375,20 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
env->rdtime_fn_arg = arg;
}
+void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
+ int (*rmw_fn)(void *arg,
+ target_ulong reg,
+ target_ulong *val,
+ target_ulong new_val,
+ target_ulong write_mask),
+ void *rmw_fn_arg)
+{
+ if (priv <= PRV_M) {
+ env->aia_ireg_rmw_fn[priv] = rmw_fn;
+ env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg;
+ }
+}
+
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
{
if (newpriv > PRV_M) {
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback
2021-10-26 6:42 ` [PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback Anup Patel
@ 2021-11-04 4:52 ` Alistair Francis
2021-12-07 10:08 ` Anup Patel
0 siblings, 1 reply; 41+ messages in thread
From: Alistair Francis @ 2021-11-04 4:52 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt, Bin Meng
On Tue, Oct 26, 2021 at 6:00 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> The AIA device emulation (such as AIA IMSIC) should be able to set
> (or provide) AIA ireg read-modify-write callback for each privilege
> level of a RISC-V HART.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> target/riscv/cpu.h | 19 +++++++++++++++++++
> target/riscv/cpu_helper.c | 14 ++++++++++++++
> 2 files changed, 33 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7182fadd21..ef4298dc69 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -239,6 +239,18 @@ struct CPURISCVState {
> uint64_t (*rdtime_fn)(uint32_t);
> uint32_t rdtime_fn_arg;
>
> + /* machine specific AIA ireg read-modify-write callback */
> +#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein) \
> + ((((__vgein) & 0x3f) << 24) | (((__virt) & 0x1) << 20) | \
> + (((__priv) & 0x3) << 16) | (__isel & 0xffff))
> +#define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff)
> +#define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3)
> +#define AIA_IREG_VIRT(__ireg) (((__ireg) >> 20) & 0x1)
> +#define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 24) & 0x3f)
These should be added when they are used
Alistair
> + int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg,
> + target_ulong *val, target_ulong new_val, target_ulong write_mask);
> + void *aia_ireg_rmw_fn_arg[4];
> +
> /* True if in debugger mode. */
> bool debugger;
> #endif
> @@ -380,6 +392,13 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
> #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
> void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
> uint32_t arg);
> +void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
> + int (*rmw_fn)(void *arg,
> + target_ulong reg,
> + target_ulong *val,
> + target_ulong new_val,
> + target_ulong write_mask),
> + void *rmw_fn_arg);
> #endif
> void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 04df3792a8..d70def1da8 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -375,6 +375,20 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
> env->rdtime_fn_arg = arg;
> }
>
> +void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
> + int (*rmw_fn)(void *arg,
> + target_ulong reg,
> + target_ulong *val,
> + target_ulong new_val,
> + target_ulong write_mask),
> + void *rmw_fn_arg)
> +{
> + if (priv <= PRV_M) {
> + env->aia_ireg_rmw_fn[priv] = rmw_fn;
> + env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg;
> + }
> +}
> +
> void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
> {
> if (newpriv > PRV_M) {
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback
2021-11-04 4:52 ` Alistair Francis
@ 2021-12-07 10:08 ` Anup Patel
0 siblings, 0 replies; 41+ messages in thread
From: Anup Patel @ 2021-12-07 10:08 UTC (permalink / raw)
To: Alistair Francis
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt, Bin Meng
On Thu, Nov 4, 2021 at 10:23 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Tue, Oct 26, 2021 at 6:00 PM Anup Patel <anup.patel@wdc.com> wrote:
> >
> > The AIA device emulation (such as AIA IMSIC) should be able to set
> > (or provide) AIA ireg read-modify-write callback for each privilege
> > level of a RISC-V HART.
> >
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
> > target/riscv/cpu.h | 19 +++++++++++++++++++
> > target/riscv/cpu_helper.c | 14 ++++++++++++++
> > 2 files changed, 33 insertions(+)
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index 7182fadd21..ef4298dc69 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -239,6 +239,18 @@ struct CPURISCVState {
> > uint64_t (*rdtime_fn)(uint32_t);
> > uint32_t rdtime_fn_arg;
> >
> > + /* machine specific AIA ireg read-modify-write callback */
> > +#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein) \
> > + ((((__vgein) & 0x3f) << 24) | (((__virt) & 0x1) << 20) | \
> > + (((__priv) & 0x3) << 16) | (__isel & 0xffff))
> > +#define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff)
> > +#define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3)
> > +#define AIA_IREG_VIRT(__ireg) (((__ireg) >> 20) & 0x1)
> > +#define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 24) & 0x3f)
>
> These should be added when they are used
Actually, these define help us encode/decode AIA indirect register number
passed as "reg" parameter to aia_ireg_rmw_fn() below.
Regards,
Anup
>
> Alistair
>
> > + int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg,
> > + target_ulong *val, target_ulong new_val, target_ulong write_mask);
> > + void *aia_ireg_rmw_fn_arg[4];
> > +
> > /* True if in debugger mode. */
> > bool debugger;
> > #endif
> > @@ -380,6 +392,13 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
> > #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
> > void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
> > uint32_t arg);
> > +void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
> > + int (*rmw_fn)(void *arg,
> > + target_ulong reg,
> > + target_ulong *val,
> > + target_ulong new_val,
> > + target_ulong write_mask),
> > + void *rmw_fn_arg);
> > #endif
> > void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
> >
> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> > index 04df3792a8..d70def1da8 100644
> > --- a/target/riscv/cpu_helper.c
> > +++ b/target/riscv/cpu_helper.c
> > @@ -375,6 +375,20 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
> > env->rdtime_fn_arg = arg;
> > }
> >
> > +void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
> > + int (*rmw_fn)(void *arg,
> > + target_ulong reg,
> > + target_ulong *val,
> > + target_ulong new_val,
> > + target_ulong write_mask),
> > + void *rmw_fn_arg)
> > +{
> > + if (priv <= PRV_M) {
> > + env->aia_ireg_rmw_fn[priv] = rmw_fn;
> > + env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg;
> > + }
> > +}
> > +
> > void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
> > {
> > if (newpriv > PRV_M) {
> > --
> > 2.25.1
> >
> >
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v4 09/22] target/riscv: Implement AIA local interrupt priorities
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
` (7 preceding siblings ...)
2021-10-26 6:42 ` [PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Anup Patel
` (12 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra, Bin Meng
The AIA spec defines programmable 8-bit priority for each local interrupt
at M-level, S-level and VS-level so we extend local interrupt processing
to consider AIA interrupt priorities. The AIA CSRs which help software
configure local interrupt priorities will be added by subsequent patches.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
target/riscv/cpu.c | 19 +++
target/riscv/cpu.h | 12 ++
target/riscv/cpu_helper.c | 241 +++++++++++++++++++++++++++++++++-----
target/riscv/machine.c | 3 +
4 files changed, 245 insertions(+), 30 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 69d6b5eb36..0006989c39 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -341,6 +341,10 @@ void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
static void riscv_cpu_reset(DeviceState *dev)
{
+#ifndef CONFIG_USER_ONLY
+ uint8_t iprio;
+ int i, irq, rdzero;
+#endif
CPUState *cs = CPU(dev);
RISCVCPU *cpu = RISCV_CPU(cs);
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
@@ -363,6 +367,21 @@ static void riscv_cpu_reset(DeviceState *dev)
env->miclaim = MIP_SGEIP;
env->pc = env->resetvec;
env->two_stage_lookup = false;
+
+ /* Initialized default priorities of local interrupts. */
+ for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
+ iprio = riscv_cpu_default_priority(i);
+ env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio;
+ env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio;
+ env->hviprio[i] = 0;
+ }
+ i = 0;
+ while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) {
+ if (!rdzero) {
+ env->hviprio[irq] = env->miprio[irq];
+ }
+ i++;
+ }
#endif
cs->exception_index = RISCV_EXCP_NONE;
env->load_res = -1;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ef4298dc69..c47e57efc8 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -179,6 +179,10 @@ struct CPURISCVState {
target_ulong mcause;
target_ulong mtval; /* since: priv-1.10.0 */
+ /* Machine and Supervisor interrupt priorities */
+ uint8_t miprio[64];
+ uint8_t siprio[64];
+
/* Hypervisor CSRs */
target_ulong hstatus;
target_ulong hedeleg;
@@ -191,6 +195,9 @@ struct CPURISCVState {
target_ulong hgeip;
uint64_t htimedelta;
+ /* Hypervisor controlled virtual interrupt priorities */
+ uint8_t hviprio[64];
+
/* Virtual CSRs */
/*
* For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
@@ -357,6 +364,11 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, void *opaque);
int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
+uint8_t riscv_cpu_default_priority(int irq);
+int riscv_cpu_mirq_pending(CPURISCVState *env);
+int riscv_cpu_sirq_pending(CPURISCVState *env);
+int riscv_cpu_vsirq_pending(CPURISCVState *env);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d70def1da8..73ebce1efd 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -115,47 +115,228 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
}
#ifndef CONFIG_USER_ONLY
+
+/*
+ * The HS-mode is allowed to configure priority only for the
+ * following VS-mode local interrupts:
+ *
+ * 0 (Reserved interrupt, reads as zero)
+ * 1 Supervisor software interrupt
+ * 4 (Reserved interrupt, reads as zero)
+ * 5 Supervisor timer interrupt
+ * 8 (Reserved interrupt, reads as zero)
+ * 13 (Reserved interrupt)
+ * 14 "
+ * 15 "
+ * 16 "
+ * 18 Debug/trace interrupt
+ * 20 (Reserved interrupt)
+ * 22 "
+ * 24 "
+ * 26 "
+ * 28 "
+ * 30 (Reserved for standard reporting of bus or system errors)
+ */
+
+static int hviprio_index2irq[] =
+ { 0, 1, 4, 5, 8, 13, 14, 15, 16, 18, 20, 22, 24, 26, 28, 30 };
+static int hviprio_index2rdzero[] =
+ { 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
+
+int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero)
+{
+ if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) {
+ return -EINVAL;
+ }
+
+ if (out_irq) {
+ *out_irq = hviprio_index2irq[index];
+ }
+
+ if (out_rdzero) {
+ *out_rdzero = hviprio_index2rdzero[index];
+ }
+
+ return 0;
+}
+
+uint8_t riscv_cpu_default_priority(int irq)
+{
+ int u, l;
+ uint8_t iprio = IPRIO_MMAXIPRIO;
+
+ if (irq < 0 || irq > 63) {
+ return iprio;
+ }
+
+ /*
+ * Default priorities of local interrupts are defined in the
+ * RISC-V Advanced Interrupt Architecture specification.
+ *
+ * ----------------------------------------------------------------
+ * Default |
+ * Priority | Major Interrupt Numbers
+ * ----------------------------------------------------------------
+ * Highest | 63 (3f), 62 (3e), 31 (1f), 30 (1e), 61 (3d), 60 (3c),
+ * | 59 (3b), 58 (3a), 29 (1d), 28 (1c), 57 (39), 56 (38),
+ * | 55 (37), 54 (36), 27 (1b), 26 (1a), 53 (35), 52 (34),
+ * | 51 (33), 50 (32), 25 (19), 24 (18), 49 (31), 48 (30)
+ * |
+ * | 11 (0b), 3 (03), 7 (07)
+ * | 9 (09), 1 (01), 5 (05)
+ * | 12 (0c)
+ * | 10 (0a), 2 (02), 6 (06)
+ * |
+ * | 47 (2f), 46 (2e), 23 (17), 22 (16), 45 (2d), 44 (2c),
+ * | 43 (2b), 42 (2a), 21 (15), 20 (14), 41 (29), 40 (28),
+ * | 39 (27), 38 (26), 19 (13), 18 (12), 37 (25), 36 (24),
+ * Lowest | 35 (23), 34 (22), 17 (11), 16 (10), 33 (21), 32 (20)
+ * ----------------------------------------------------------------
+ */
+
+ u = IPRIO_DEFAULT_U(irq);
+ l = IPRIO_DEFAULT_L(irq);
+ if (u == 0) {
+ if (irq == IRQ_VS_EXT || irq == IRQ_VS_TIMER ||
+ irq == IRQ_VS_SOFT) {
+ iprio = IPRIO_DEFAULT_VS;
+ } else if (irq == IRQ_S_GEXT) {
+ iprio = IPRIO_DEFAULT_SGEXT;
+ } else if (irq == IRQ_S_EXT || irq == IRQ_S_TIMER ||
+ irq == IRQ_S_SOFT) {
+ iprio = IPRIO_DEFAULT_S;
+ } else if (irq == IRQ_M_EXT || irq == IRQ_M_TIMER ||
+ irq == IRQ_M_SOFT) {
+ iprio = IPRIO_DEFAULT_M;
+ } else {
+ iprio = IPRIO_DEFAULT_VS;
+ }
+ } else if (u == 1) {
+ if (l < 8) {
+ iprio = IPRIO_DEFAULT_16_23(irq);
+ } else {
+ iprio = IPRIO_DEFAULT_24_31(irq);
+ }
+ } else if (u == 2) {
+ iprio = IPRIO_DEFAULT_32_47(irq);
+ } else if (u == 3) {
+ iprio = IPRIO_DEFAULT_48_63(irq);
+ }
+
+ return iprio;
+}
+
+static int riscv_cpu_pending_to_irq(CPURISCVState *env,
+ uint64_t pending, uint8_t *iprio)
+{
+ int irq, best_irq = RISCV_EXCP_NONE;
+ unsigned int prio, best_prio = UINT_MAX;
+
+ if (!pending) {
+ return RISCV_EXCP_NONE;
+ }
+
+ irq = ctz64(pending);
+ if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+ return irq;
+ }
+
+ pending = pending >> irq;
+ while (pending) {
+ prio = iprio[irq];
+ if (!prio) {
+ prio = (riscv_cpu_default_priority(irq) < IPRIO_DEFAULT_M) ?
+ 1 : IPRIO_MMAXIPRIO;
+ }
+ if ((pending & 0x1) && (prio < best_prio)) {
+ best_irq = irq;
+ best_prio = prio;
+ }
+ irq++;
+ pending = pending >> 1;
+ }
+
+ return best_irq;
+}
+
+static uint64_t riscv_cpu_all_pending(CPURISCVState *env)
+{
+ uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN);
+ uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
+
+ return (env->mip | vsgein) & env->mie;
+}
+
+int riscv_cpu_mirq_pending(CPURISCVState *env)
+{
+ uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg &
+ ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
+
+ return riscv_cpu_pending_to_irq(env, irqs, env->miprio);
+}
+
+int riscv_cpu_sirq_pending(CPURISCVState *env)
+{
+ uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
+ ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
+
+ return riscv_cpu_pending_to_irq(env, irqs, env->siprio);
+}
+
+int riscv_cpu_vsirq_pending(CPURISCVState *env)
+{
+ uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
+ (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
+
+ return riscv_cpu_pending_to_irq(env, irqs >> 1, env->hviprio);
+}
+
static int riscv_cpu_local_irq_pending(CPURISCVState *env)
{
- target_ulong irqs;
-
- target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
- target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
- target_ulong hs_mstatus_sie = get_field(env->mstatus_hs, MSTATUS_SIE);
-
- target_ulong pending = env->mip & env->mie &
- ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
- target_ulong vsgemask =
- (target_ulong)1 << get_field(env->hstatus, HSTATUS_VGEIN);
- target_ulong vsgein = (env->hgeip & vsgemask) ? MIP_VSEIP : 0;
- target_ulong vspending = ((env->mip | vsgein) & env->mie &
- (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP));
-
- target_ulong mie = env->priv < PRV_M ||
- (env->priv == PRV_M && mstatus_mie);
- target_ulong sie = env->priv < PRV_S ||
- (env->priv == PRV_S && mstatus_sie);
- target_ulong hs_sie = env->priv < PRV_S ||
- (env->priv == PRV_S && hs_mstatus_sie);
+ int virq;
+ uint64_t irqs, pending, mie, sie, vsie;
+ /* Determine interrupt enable state of all privilege modes */
if (riscv_cpu_virt_enabled(env)) {
- target_ulong pending_hs_irq = pending & -hs_sie;
+ mie = 1;
+ sie = 1;
+ vsie = (env->priv < PRV_S) ||
+ (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
+ } else {
+ mie = (env->priv < PRV_M) ||
+ (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE));
+ sie = (env->priv < PRV_S) ||
+ (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
+ vsie = 0;
+ }
- if (pending_hs_irq) {
- riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP);
- return ctz64(pending_hs_irq);
- }
+ /* Determine all pending interrupts */
+ pending = riscv_cpu_all_pending(env);
- pending = vspending;
+ /* Check M-mode interrupts */
+ irqs = pending & ~env->mideleg & -mie &
+ ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
+ if (irqs) {
+ return riscv_cpu_pending_to_irq(env, irqs, env->miprio);
}
- irqs = (pending & ~env->mideleg & -mie) | (pending & env->mideleg & -sie);
+ /* Check HS-mode interrupts */
+ irqs = pending & env->mideleg & -sie &
+ ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
+ if (irqs) {
+ return riscv_cpu_pending_to_irq(env, irqs, env->siprio);
+ }
+ /* Check VS-mode interrupts */
+ irqs = pending & env->hideleg & -vsie &
+ (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
if (irqs) {
- return ctz64(irqs); /* since non-zero */
- } else {
- return RISCV_EXCP_NONE; /* indicates no pending interrupt */
+ virq = riscv_cpu_pending_to_irq(env, irqs >> 1, env->hviprio);
+ return (virq <= 0) ? virq : virq + 1;
}
+
+ /* Indicate no pending interrupt */
+ return RISCV_EXCP_NONE;
}
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index fe99ec7304..a7102220b6 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -116,6 +116,7 @@ static const VMStateDescription vmstate_hyper = {
VMSTATE_UINTTL(env.hgeie, RISCVCPU),
VMSTATE_UINTTL(env.hgeip, RISCVCPU),
VMSTATE_UINT64(env.htimedelta, RISCVCPU),
+ VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),
VMSTATE_UINT64(env.vsstatus, RISCVCPU),
VMSTATE_UINTTL(env.vstvec, RISCVCPU),
@@ -147,6 +148,8 @@ const VMStateDescription vmstate_riscv_cpu = {
.fields = (VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
+ VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64),
+ VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64),
VMSTATE_UINTTL(env.pc, RISCVCPU),
VMSTATE_UINTTL(env.load_res, RISCVCPU),
VMSTATE_UINTTL(env.load_val, RISCVCPU),
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v4 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
` (8 preceding siblings ...)
2021-10-26 6:42 ` [PATCH v4 09/22] target/riscv: Implement AIA local interrupt priorities Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-11-04 4:43 ` Alistair Francis
2021-10-26 6:42 ` [PATCH v4 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs Anup Patel
` (11 subsequent siblings)
21 siblings, 1 reply; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra, Bin Meng
The AIA specification adds new CSRs for RV32 so that RISC-V hart can
support 64 local interrupts on both RV32 and RV64.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
target/riscv/cpu.h | 14 +-
target/riscv/cpu_helper.c | 10 +-
target/riscv/csr.c | 560 +++++++++++++++++++++++++++++++-------
target/riscv/machine.c | 10 +-
4 files changed, 474 insertions(+), 120 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c47e57efc8..718a95e864 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -159,12 +159,12 @@ struct CPURISCVState {
*/
uint64_t mstatus;
- target_ulong mip;
+ uint64_t mip;
- uint32_t miclaim;
+ uint64_t miclaim;
- target_ulong mie;
- target_ulong mideleg;
+ uint64_t mie;
+ uint64_t mideleg;
target_ulong satp; /* since: priv-1.10.0 */
target_ulong stval;
@@ -186,7 +186,7 @@ struct CPURISCVState {
/* Hypervisor CSRs */
target_ulong hstatus;
target_ulong hedeleg;
- target_ulong hideleg;
+ uint64_t hideleg;
target_ulong hcounteren;
target_ulong htval;
target_ulong htinst;
@@ -399,8 +399,8 @@ void riscv_cpu_list(void);
#ifndef CONFIG_USER_ONLY
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
-int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
-uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
+int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
+uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
uint32_t arg);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 73ebce1efd..416b11f85c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -506,7 +506,7 @@ bool riscv_cpu_two_stage_lookup(int mmu_idx)
return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK;
}
-int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
+int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
{
CPURISCVState *env = &cpu->env;
if (env->miclaim & interrupts) {
@@ -517,11 +517,11 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
}
}
-uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
+uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value)
{
CPURISCVState *env = &cpu->env;
CPUState *cs = CPU(cpu);
- uint32_t gein, vsgein = 0, old = env->mip;
+ uint64_t gein, vsgein = 0, old = env->mip;
bool locked = false;
if (riscv_cpu_virt_enabled(env)) {
@@ -1244,7 +1244,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
*/
bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
- target_ulong deleg = async ? env->mideleg : env->medeleg;
+ uint64_t deleg = async ? env->mideleg : env->medeleg;
bool write_tval = false;
target_ulong tval = 0;
target_ulong htval = 0;
@@ -1311,7 +1311,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
/* handle the trap in S-mode */
if (riscv_has_ext(env, RVH)) {
- target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
+ uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
if (env->two_stage_lookup && write_tval) {
/*
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 7ff285282b..3a7d89ac34 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -153,6 +153,15 @@ static RISCVException any32(CPURISCVState *env, int csrno)
}
+static int aia_any32(CPURISCVState *env, int csrno)
+{
+ if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ return any32(env, csrno);
+}
+
static RISCVException smode(CPURISCVState *env, int csrno)
{
if (riscv_has_ext(env, RVS)) {
@@ -162,6 +171,24 @@ static RISCVException smode(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+static int smode32(CPURISCVState *env, int csrno)
+{
+ if (riscv_cpu_mxl(env) != MXL_RV32) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ return smode(env, csrno);
+}
+
+static int aia_smode32(CPURISCVState *env, int csrno)
+{
+ if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ return smode32(env, csrno);
+}
+
static RISCVException hmode(CPURISCVState *env, int csrno)
{
if (riscv_has_ext(env, RVS) &&
@@ -192,6 +219,15 @@ static RISCVException hmode32(CPURISCVState *env, int csrno)
}
+static int aia_hmode32(CPURISCVState *env, int csrno)
+{
+ if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ return hmode32(env, csrno);
+}
+
static RISCVException pmp(CPURISCVState *env, int csrno)
{
if (riscv_feature(env, RISCV_FEATURE_PMP)) {
@@ -405,15 +441,15 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
/* Machine constants */
-#define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
-#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
-#define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
-#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS)
+#define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP))
+#define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP))
+#define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
+#define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
-static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
+static const uint64_t delegable_ints = S_MODE_INTERRUPTS |
VS_MODE_INTERRUPTS;
-static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
-static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
+static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS;
+static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
HS_MODE_INTERRUPTS;
#define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
(1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
@@ -662,40 +698,107 @@ static RISCVException write_medeleg(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
-static RISCVException read_mideleg(CPURISCVState *env, int csrno,
- target_ulong *val)
+static RISCVException rmw_mideleg64(CPURISCVState *env, int csrno,
+ uint64_t *ret_val,
+ uint64_t new_val, uint64_t wr_mask)
{
- *val = env->mideleg;
- return RISCV_EXCP_NONE;
-}
+ uint64_t mask = wr_mask & delegable_ints;
+
+ if (ret_val) {
+ *ret_val = env->mideleg;
+ }
+
+ env->mideleg = (env->mideleg & ~mask) | (new_val & mask);
-static RISCVException write_mideleg(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
if (riscv_has_ext(env, RVH)) {
env->mideleg |= HS_MODE_INTERRUPTS;
}
+
return RISCV_EXCP_NONE;
}
-static RISCVException read_mie(CPURISCVState *env, int csrno,
- target_ulong *val)
+static RISCVException rmw_mideleg(CPURISCVState *env, int csrno,
+ target_ulong *ret_val,
+ target_ulong new_val, target_ulong wr_mask)
{
- *val = env->mie;
- return RISCV_EXCP_NONE;
+ uint64_t rval;
+ RISCVException ret;
+
+ ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask);
+ if (ret_val) {
+ *ret_val = rval;
+ }
+
+ return ret;
}
-static RISCVException write_mie(CPURISCVState *env, int csrno,
- target_ulong val)
+static RISCVException rmw_midelegh(CPURISCVState *env, int csrno,
+ target_ulong *ret_val,
+ target_ulong new_val,
+ target_ulong wr_mask)
{
- env->mie = (env->mie & ~all_ints) | (val & all_ints);
+ uint64_t rval;
+ RISCVException ret;
+
+ ret = rmw_mideleg64(env, csrno, &rval,
+ ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
+ if (ret_val) {
+ *ret_val = rval >> 32;
+ }
+
+ return ret;
+}
+
+static RISCVException rmw_mie64(CPURISCVState *env, int csrno,
+ uint64_t *ret_val,
+ uint64_t new_val, uint64_t wr_mask)
+{
+ uint64_t mask = wr_mask & all_ints;
+
+ if (ret_val) {
+ *ret_val = env->mie;
+ }
+
+ env->mie = (env->mie & ~mask) | (new_val & mask);
+
if (!riscv_has_ext(env, RVH)) {
- env->mie &= ~MIP_SGEIP;
+ env->mie &= ~((uint64_t)MIP_SGEIP);
}
+
return RISCV_EXCP_NONE;
}
+static RISCVException rmw_mie(CPURISCVState *env, int csrno,
+ target_ulong *ret_val,
+ target_ulong new_val, target_ulong wr_mask)
+{
+ uint64_t rval;
+ RISCVException ret;
+
+ ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask);
+ if (ret_val) {
+ *ret_val = rval;
+ }
+
+ return ret;
+}
+
+static RISCVException rmw_mieh(CPURISCVState *env, int csrno,
+ target_ulong *ret_val,
+ target_ulong new_val, target_ulong wr_mask)
+{
+ uint64_t rval;
+ RISCVException ret;
+
+ ret = rmw_mie64(env, csrno, &rval,
+ ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
+ if (ret_val) {
+ *ret_val = rval >> 32;
+ }
+
+ return ret;
+}
+
static RISCVException read_mtvec(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -786,17 +889,17 @@ static RISCVException write_mtval(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
-static RISCVException rmw_mip(CPURISCVState *env, int csrno,
- target_ulong *ret_value,
- target_ulong new_value, target_ulong write_mask)
+static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
+ uint64_t *ret_val,
+ uint64_t new_val, uint64_t wr_mask)
{
RISCVCPU *cpu = env_archcpu(env);
/* Allow software control of delegable interrupts not claimed by hardware */
- target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
- uint32_t gin, old_mip;
+ uint64_t old_mip, mask = wr_mask & delegable_ints & ~env->miclaim;
+ uint32_t gin;
if (mask) {
- old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
+ old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask));
} else {
old_mip = env->mip;
}
@@ -806,13 +909,44 @@ static RISCVException rmw_mip(CPURISCVState *env, int csrno,
old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0;
}
- if (ret_value) {
- *ret_value = old_mip;
+ if (ret_val) {
+ *ret_val = old_mip;
}
return RISCV_EXCP_NONE;
}
+static RISCVException rmw_mip(CPURISCVState *env, int csrno,
+ target_ulong *ret_val,
+ target_ulong new_val, target_ulong wr_mask)
+{
+ uint64_t rval;
+ RISCVException ret;
+
+ ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask);
+ if (ret_val) {
+ *ret_val = rval;
+ }
+
+ return ret;
+}
+
+static RISCVException rmw_miph(CPURISCVState *env, int csrno,
+ target_ulong *ret_val,
+ target_ulong new_val, target_ulong wr_mask)
+{
+ uint64_t rval;
+ RISCVException ret;
+
+ ret = rmw_mip64(env, csrno, &rval,
+ ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
+ if (ret_val) {
+ *ret_val = rval >> 32;
+ }
+
+ return ret;
+}
+
/* Supervisor Trap Setup */
static RISCVException read_sstatus(CPURISCVState *env, int csrno,
target_ulong *val)
@@ -832,45 +966,112 @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno,
return write_mstatus(env, CSR_MSTATUS, newval);
}
-static RISCVException read_vsie(CPURISCVState *env, int csrno,
- target_ulong *val)
+static RISCVException rmw_vsie64(CPURISCVState *env, int csrno,
+ uint64_t *ret_val,
+ uint64_t new_val, uint64_t wr_mask)
{
- /* Shift the VS bits to their S bit location in vsie */
- *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
- return RISCV_EXCP_NONE;
+ RISCVException ret;
+ uint64_t rval, vsbits, mask = env->hideleg & VS_MODE_INTERRUPTS;
+
+ /* Bring VS-level bits to correct position */
+ vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
+ new_val &= ~(VS_MODE_INTERRUPTS >> 1);
+ new_val |= vsbits << 1;
+ vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
+ wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
+ wr_mask |= vsbits << 1;
+
+ ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask);
+ if (ret_val) {
+ rval &= mask;
+ vsbits = rval & VS_MODE_INTERRUPTS;
+ rval &= ~VS_MODE_INTERRUPTS;
+ *ret_val = rval | (vsbits >> 1);
+ }
+
+ return ret;
}
-static RISCVException read_sie(CPURISCVState *env, int csrno,
- target_ulong *val)
+static RISCVException rmw_vsie(CPURISCVState *env, int csrno,
+ target_ulong *ret_val,
+ target_ulong new_val, target_ulong wr_mask)
{
- if (riscv_cpu_virt_enabled(env)) {
- read_vsie(env, CSR_VSIE, val);
- } else {
- *val = env->mie & env->mideleg;
+ uint64_t rval;
+ RISCVException ret;
+
+ ret = rmw_vsie64(env, csrno, &rval, new_val, wr_mask);
+ if (ret_val) {
+ *ret_val = rval;
}
- return RISCV_EXCP_NONE;
+
+ return ret;
}
-static RISCVException write_vsie(CPURISCVState *env, int csrno,
- target_ulong val)
+static RISCVException rmw_vsieh(CPURISCVState *env, int csrno,
+ target_ulong *ret_val,
+ target_ulong new_val, target_ulong wr_mask)
{
- /* Shift the S bits to their VS bit location in mie */
- target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
- ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
- return write_mie(env, CSR_MIE, newval);
+ uint64_t rval;
+ RISCVException ret;
+
+ ret = rmw_vsie64(env, csrno, &rval,
+ ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
+ if (ret_val) {
+ *ret_val = rval >> 32;
+ }
+
+ return ret;
}
-static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
+static RISCVException rmw_sie64(CPURISCVState *env, int csrno,
+ uint64_t *ret_val,
+ uint64_t new_val, uint64_t wr_mask)
{
+ RISCVException ret;
+ uint64_t mask = env->mideleg & S_MODE_INTERRUPTS;
+
if (riscv_cpu_virt_enabled(env)) {
- write_vsie(env, CSR_VSIE, val);
+ ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask);
} else {
- target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
- (val & S_MODE_INTERRUPTS);
- write_mie(env, CSR_MIE, newval);
+ ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask);
}
- return RISCV_EXCP_NONE;
+ if (ret_val) {
+ *ret_val &= mask;
+ }
+
+ return ret;
+}
+
+static RISCVException rmw_sie(CPURISCVState *env, int csrno,
+ target_ulong *ret_val,
+ target_ulong new_val, target_ulong wr_mask)
+{
+ uint64_t rval;
+ RISCVException ret;
+
+ ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask);
+ if (ret_val) {
+ *ret_val = rval;
+ }
+
+ return ret;
+}
+
+static RISCVException rmw_sieh(CPURISCVState *env, int csrno,
+ target_ulong *ret_val,
+ target_ulong new_val, target_ulong wr_mask)
+{
+ uint64_t rval;
+ RISCVException ret;
+
+ ret = rmw_sie64(env, csrno, &rval,
+ ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
+ if (ret_val) {
+ *ret_val = rval >> 32;
+ }
+
+ return ret;
}
static RISCVException read_stvec(CPURISCVState *env, int csrno,
@@ -963,38 +1164,111 @@ static RISCVException write_stval(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException rmw_vsip64(CPURISCVState *env, int csrno,
+ uint64_t *ret_val,
+ uint64_t new_val, uint64_t wr_mask)
+{
+ RISCVException ret;
+ uint64_t rval, vsbits, mask = env->hideleg & vsip_writable_mask;
+
+ /* Bring VS-level bits to correct position */
+ vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
+ new_val &= ~(VS_MODE_INTERRUPTS >> 1);
+ new_val |= vsbits << 1;
+ vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
+ wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
+ wr_mask |= vsbits << 1;
+
+ ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask);
+ if (ret_val) {
+ rval &= mask;
+ vsbits = rval & VS_MODE_INTERRUPTS;
+ rval &= ~VS_MODE_INTERRUPTS;
+ *ret_val = rval | (vsbits >> 1);
+ }
+
+ return ret;
+}
+
static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
- target_ulong *ret_value,
- target_ulong new_value, target_ulong write_mask)
+ target_ulong *ret_val,
+ target_ulong new_val, target_ulong wr_mask)
{
- /* Shift the S bits to their VS bit location in mip */
- int ret = rmw_mip(env, csrno, ret_value, new_value << 1,
- (write_mask << 1) & vsip_writable_mask & env->hideleg);
+ uint64_t rval;
+ RISCVException ret;
- if (ret_value) {
- *ret_value &= VS_MODE_INTERRUPTS;
- /* Shift the VS bits to their S bit location in vsip */
- *ret_value >>= 1;
+ ret = rmw_vsip64(env, csrno, &rval, new_val, wr_mask);
+ if (ret_val) {
+ *ret_val = rval;
}
+
return ret;
}
-static RISCVException rmw_sip(CPURISCVState *env, int csrno,
- target_ulong *ret_value,
- target_ulong new_value, target_ulong write_mask)
+static RISCVException rmw_vsiph(CPURISCVState *env, int csrno,
+ target_ulong *ret_val,
+ target_ulong new_val, target_ulong wr_mask)
{
- int ret;
+ uint64_t rval;
+ RISCVException ret;
+
+ ret = rmw_vsip64(env, csrno, &rval,
+ ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
+ if (ret_val) {
+ *ret_val = rval >> 32;
+ }
+
+ return ret;
+}
+
+static RISCVException rmw_sip64(CPURISCVState *env, int csrno,
+ uint64_t *ret_val,
+ uint64_t new_val, uint64_t wr_mask)
+{
+ RISCVException ret;
+ uint64_t mask = env->mideleg & sip_writable_mask;
if (riscv_cpu_virt_enabled(env)) {
- ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
+ ret = rmw_vsip64(env, CSR_VSIE, ret_val, new_val, wr_mask);
} else {
- ret = rmw_mip(env, csrno, ret_value, new_value,
- write_mask & env->mideleg & sip_writable_mask);
+ ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask);
}
- if (ret_value) {
- *ret_value &= env->mideleg & S_MODE_INTERRUPTS;
+ if (ret_val) {
+ *ret_val &= env->mideleg & S_MODE_INTERRUPTS;
+ }
+
+ return ret;
+}
+
+static RISCVException rmw_sip(CPURISCVState *env, int csrno,
+ target_ulong *ret_val,
+ target_ulong new_val, target_ulong wr_mask)
+{
+ uint64_t rval;
+ RISCVException ret;
+
+ ret = rmw_sip64(env, csrno, &rval, new_val, wr_mask);
+ if (ret_val) {
+ *ret_val = rval;
}
+
+ return ret;
+}
+
+static RISCVException rmw_siph(CPURISCVState *env, int csrno,
+ target_ulong *ret_val,
+ target_ulong new_val, target_ulong wr_mask)
+{
+ uint64_t rval;
+ RISCVException ret;
+
+ ret = rmw_sip64(env, csrno, &rval,
+ ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
+ if (ret_val) {
+ *ret_val = rval >> 32;
+ }
+
return ret;
}
@@ -1089,30 +1363,94 @@ static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
-static RISCVException read_hideleg(CPURISCVState *env, int csrno,
- target_ulong *val)
+static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno,
+ uint64_t *ret_val,
+ uint64_t new_val, uint64_t wr_mask)
{
- *val = env->hideleg;
+ uint64_t mask = wr_mask & vs_delegable_ints;
+
+ if (ret_val) {
+ *ret_val = env->hideleg & vs_delegable_ints;
+ }
+
+ env->hideleg = (env->hideleg & ~mask) | (new_val & mask);
return RISCV_EXCP_NONE;
}
-static RISCVException write_hideleg(CPURISCVState *env, int csrno,
- target_ulong val)
+static RISCVException rmw_hideleg(CPURISCVState *env, int csrno,
+ target_ulong *ret_val,
+ target_ulong new_val, target_ulong wr_mask)
{
- env->hideleg = val & vs_delegable_ints;
- return RISCV_EXCP_NONE;
+ uint64_t rval;
+ RISCVException ret;
+
+ ret = rmw_hideleg64(env, csrno, &rval, new_val, wr_mask);
+ if (ret_val) {
+ *ret_val = rval;
+ }
+
+ return ret;
+}
+
+static RISCVException rmw_hidelegh(CPURISCVState *env, int csrno,
+ target_ulong *ret_val,
+ target_ulong new_val, target_ulong wr_mask)
+{
+ uint64_t rval;
+ RISCVException ret;
+
+ ret = rmw_hideleg64(env, csrno, &rval,
+ ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
+ if (ret_val) {
+ *ret_val = rval >> 32;
+ }
+
+ return ret;
+}
+
+static RISCVException rmw_hvip64(CPURISCVState *env, int csrno,
+ uint64_t *ret_val,
+ uint64_t new_val, uint64_t wr_mask)
+{
+ RISCVException ret;
+
+ ret = rmw_mip64(env, csrno, ret_val, new_val,
+ wr_mask & hvip_writable_mask);
+ if (ret_val) {
+ *ret_val &= VS_MODE_INTERRUPTS;
+ }
+
+ return ret;
}
static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
- target_ulong *ret_value,
- target_ulong new_value, target_ulong write_mask)
+ target_ulong *ret_val,
+ target_ulong new_val, target_ulong wr_mask)
{
- int ret = rmw_mip(env, csrno, ret_value, new_value,
- write_mask & hvip_writable_mask);
+ uint64_t rval;
+ RISCVException ret;
- if (ret_value) {
- *ret_value &= VS_MODE_INTERRUPTS;
+ ret = rmw_hvip64(env, csrno, &rval, new_val, wr_mask);
+ if (ret_val) {
+ *ret_val = rval;
+ }
+
+ return ret;
+}
+
+static RISCVException rmw_hviph(CPURISCVState *env, int csrno,
+ target_ulong *ret_val,
+ target_ulong new_val, target_ulong wr_mask)
+{
+ uint64_t rval;
+ RISCVException ret;
+
+ ret = rmw_hvip64(env, csrno, &rval,
+ ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
+ if (ret_val) {
+ *ret_val = rval >> 32;
}
+
return ret;
}
@@ -1129,18 +1467,19 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
return ret;
}
-static RISCVException read_hie(CPURISCVState *env, int csrno,
- target_ulong *val)
+static RISCVException rmw_hie(CPURISCVState *env, int csrno,
+ target_ulong *ret_val,
+ target_ulong new_val, target_ulong wr_mask)
{
- *val = env->mie & HS_MODE_INTERRUPTS;
- return RISCV_EXCP_NONE;
-}
+ uint64_t rval;
+ RISCVException ret;
-static RISCVException write_hie(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_MODE_INTERRUPTS);
- return write_mie(env, CSR_MIE, newval);
+ ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERRUPTS);
+ if (ret_val) {
+ *ret_val = rval & HS_MODE_INTERRUPTS;
+ }
+
+ return ret;
}
static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
@@ -1598,9 +1937,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* Machine Trap Setup */
[CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus },
[CSR_MISA] = { "misa", any, read_misa, write_misa },
- [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg },
+ [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg },
[CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg },
- [CSR_MIE] = { "mie", any, read_mie, write_mie },
+ [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie },
[CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec },
[CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren },
@@ -1613,9 +1952,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval },
[CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
+ /* Machine-Level High-Half CSRs (AIA) */
+ [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
+ [CSR_MIEH] = { "mieh", aia_any32, NULL, NULL, rmw_mieh },
+ [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph },
+
/* Supervisor Trap Setup */
[CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus },
- [CSR_SIE] = { "sie", smode, read_sie, write_sie },
+ [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie },
[CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },
[CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
@@ -1629,12 +1973,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* Supervisor Protection and Translation */
[CSR_SATP] = { "satp", smode, read_satp, write_satp },
+ /* Supervisor-Level High-Half CSRs (AIA) */
+ [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
+ [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph },
+
[CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus },
[CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg },
- [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg },
+ [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg },
[CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip },
[CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip },
- [CSR_HIE] = { "hie", hmode, read_hie, write_hie },
+ [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie },
[CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren },
[CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie },
[CSR_HTVAL] = { "htval", hmode, read_htval, write_htval },
@@ -1646,7 +1994,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus },
[CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip },
- [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie },
+ [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie },
[CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec },
[CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch },
[CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc },
@@ -1657,6 +2005,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 },
[CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst },
+ /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
+ [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh },
+ [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph },
+ [CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh },
+ [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph },
+
/* Physical Memory Protection */
[CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg },
[CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index a7102220b6..7356d70be6 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -108,7 +108,7 @@ static const VMStateDescription vmstate_hyper = {
.fields = (VMStateField[]) {
VMSTATE_UINTTL(env.hstatus, RISCVCPU),
VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
- VMSTATE_UINTTL(env.hideleg, RISCVCPU),
+ VMSTATE_UINT64(env.hideleg, RISCVCPU),
VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
VMSTATE_UINTTL(env.htval, RISCVCPU),
VMSTATE_UINTTL(env.htinst, RISCVCPU),
@@ -168,10 +168,10 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.resetvec, RISCVCPU),
VMSTATE_UINTTL(env.mhartid, RISCVCPU),
VMSTATE_UINT64(env.mstatus, RISCVCPU),
- VMSTATE_UINTTL(env.mip, RISCVCPU),
- VMSTATE_UINT32(env.miclaim, RISCVCPU),
- VMSTATE_UINTTL(env.mie, RISCVCPU),
- VMSTATE_UINTTL(env.mideleg, RISCVCPU),
+ VMSTATE_UINT64(env.mip, RISCVCPU),
+ VMSTATE_UINT64(env.miclaim, RISCVCPU),
+ VMSTATE_UINT64(env.mie, RISCVCPU),
+ VMSTATE_UINT64(env.mideleg, RISCVCPU),
VMSTATE_UINTTL(env.satp, RISCVCPU),
VMSTATE_UINTTL(env.stval, RISCVCPU),
VMSTATE_UINTTL(env.medeleg, RISCVCPU),
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH v4 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
2021-10-26 6:42 ` [PATCH v4 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Anup Patel
@ 2021-11-04 4:43 ` Alistair Francis
2021-12-09 6:14 ` Anup Patel
0 siblings, 1 reply; 41+ messages in thread
From: Alistair Francis @ 2021-11-04 4:43 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt, Bin Meng
On Tue, Oct 26, 2021 at 5:10 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> The AIA specification adds new CSRs for RV32 so that RISC-V hart can
> support 64 local interrupts on both RV32 and RV64.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> target/riscv/cpu.h | 14 +-
> target/riscv/cpu_helper.c | 10 +-
> target/riscv/csr.c | 560 +++++++++++++++++++++++++++++++-------
> target/riscv/machine.c | 10 +-
> 4 files changed, 474 insertions(+), 120 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index c47e57efc8..718a95e864 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -159,12 +159,12 @@ struct CPURISCVState {
> */
> uint64_t mstatus;
>
> - target_ulong mip;
> + uint64_t mip;
>
> - uint32_t miclaim;
> + uint64_t miclaim;
>
> - target_ulong mie;
> - target_ulong mideleg;
> + uint64_t mie;
> + uint64_t mideleg;
>
> target_ulong satp; /* since: priv-1.10.0 */
> target_ulong stval;
> @@ -186,7 +186,7 @@ struct CPURISCVState {
> /* Hypervisor CSRs */
> target_ulong hstatus;
> target_ulong hedeleg;
> - target_ulong hideleg;
> + uint64_t hideleg;
> target_ulong hcounteren;
> target_ulong htval;
> target_ulong htinst;
> @@ -399,8 +399,8 @@ void riscv_cpu_list(void);
> #ifndef CONFIG_USER_ONLY
> bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
> void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
> -int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
> -uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
> +int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
> +uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value);
> #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
> void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
> uint32_t arg);
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 73ebce1efd..416b11f85c 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -506,7 +506,7 @@ bool riscv_cpu_two_stage_lookup(int mmu_idx)
> return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK;
> }
>
> -int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
> +int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
> {
> CPURISCVState *env = &cpu->env;
> if (env->miclaim & interrupts) {
> @@ -517,11 +517,11 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
> }
> }
>
> -uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
> +uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value)
> {
> CPURISCVState *env = &cpu->env;
> CPUState *cs = CPU(cpu);
> - uint32_t gein, vsgein = 0, old = env->mip;
> + uint64_t gein, vsgein = 0, old = env->mip;
> bool locked = false;
>
> if (riscv_cpu_virt_enabled(env)) {
> @@ -1244,7 +1244,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> */
> bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
> target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
> - target_ulong deleg = async ? env->mideleg : env->medeleg;
> + uint64_t deleg = async ? env->mideleg : env->medeleg;
> bool write_tval = false;
> target_ulong tval = 0;
> target_ulong htval = 0;
> @@ -1311,7 +1311,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
> /* handle the trap in S-mode */
> if (riscv_has_ext(env, RVH)) {
> - target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
> + uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
>
> if (env->two_stage_lookup && write_tval) {
> /*
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 7ff285282b..3a7d89ac34 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -153,6 +153,15 @@ static RISCVException any32(CPURISCVState *env, int csrno)
>
> }
>
> +static int aia_any32(CPURISCVState *env, int csrno)
> +{
> + if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + return any32(env, csrno);
> +}
> +
> static RISCVException smode(CPURISCVState *env, int csrno)
> {
> if (riscv_has_ext(env, RVS)) {
> @@ -162,6 +171,24 @@ static RISCVException smode(CPURISCVState *env, int csrno)
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> +static int smode32(CPURISCVState *env, int csrno)
> +{
> + if (riscv_cpu_mxl(env) != MXL_RV32) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + return smode(env, csrno);
> +}
> +
> +static int aia_smode32(CPURISCVState *env, int csrno)
> +{
> + if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + return smode32(env, csrno);
> +}
> +
> static RISCVException hmode(CPURISCVState *env, int csrno)
> {
> if (riscv_has_ext(env, RVS) &&
> @@ -192,6 +219,15 @@ static RISCVException hmode32(CPURISCVState *env, int csrno)
>
> }
>
> +static int aia_hmode32(CPURISCVState *env, int csrno)
> +{
> + if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + return hmode32(env, csrno);
> +}
> +
> static RISCVException pmp(CPURISCVState *env, int csrno)
> {
> if (riscv_feature(env, RISCV_FEATURE_PMP)) {
> @@ -405,15 +441,15 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
>
> /* Machine constants */
>
> -#define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
> -#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
> -#define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
> -#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS)
> +#define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP))
> +#define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP))
> +#define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
> +#define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
>
> -static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
> +static const uint64_t delegable_ints = S_MODE_INTERRUPTS |
> VS_MODE_INTERRUPTS;
> -static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
> -static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
> +static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS;
> +static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
> HS_MODE_INTERRUPTS;
> #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
> (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
> @@ -662,40 +698,107 @@ static RISCVException write_medeleg(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> -static RISCVException read_mideleg(CPURISCVState *env, int csrno,
> - target_ulong *val)
> +static RISCVException rmw_mideleg64(CPURISCVState *env, int csrno,
> + uint64_t *ret_val,
> + uint64_t new_val, uint64_t wr_mask)
> {
> - *val = env->mideleg;
> - return RISCV_EXCP_NONE;
> -}
> + uint64_t mask = wr_mask & delegable_ints;
> +
> + if (ret_val) {
> + *ret_val = env->mideleg;
> + }
> +
> + env->mideleg = (env->mideleg & ~mask) | (new_val & mask);
>
> -static RISCVException write_mideleg(CPURISCVState *env, int csrno,
> - target_ulong val)
> -{
> - env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
> if (riscv_has_ext(env, RVH)) {
> env->mideleg |= HS_MODE_INTERRUPTS;
> }
> +
> return RISCV_EXCP_NONE;
> }
>
> -static RISCVException read_mie(CPURISCVState *env, int csrno,
> - target_ulong *val)
> +static RISCVException rmw_mideleg(CPURISCVState *env, int csrno,
> + target_ulong *ret_val,
> + target_ulong new_val, target_ulong wr_mask)
> {
> - *val = env->mie;
> - return RISCV_EXCP_NONE;
> + uint64_t rval;
> + RISCVException ret;
> +
> + ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask);
> + if (ret_val) {
> + *ret_val = rval;
> + }
> +
> + return ret;
> }
>
> -static RISCVException write_mie(CPURISCVState *env, int csrno,
> - target_ulong val)
> +static RISCVException rmw_midelegh(CPURISCVState *env, int csrno,
> + target_ulong *ret_val,
> + target_ulong new_val,
> + target_ulong wr_mask)
> {
> - env->mie = (env->mie & ~all_ints) | (val & all_ints);
> + uint64_t rval;
> + RISCVException ret;
> +
> + ret = rmw_mideleg64(env, csrno, &rval,
> + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
> + if (ret_val) {
> + *ret_val = rval >> 32;
> + }
> +
> + return ret;
> +}
> +
> +static RISCVException rmw_mie64(CPURISCVState *env, int csrno,
> + uint64_t *ret_val,
> + uint64_t new_val, uint64_t wr_mask)
> +{
> + uint64_t mask = wr_mask & all_ints;
> +
> + if (ret_val) {
> + *ret_val = env->mie;
> + }
> +
> + env->mie = (env->mie & ~mask) | (new_val & mask);
> +
> if (!riscv_has_ext(env, RVH)) {
> - env->mie &= ~MIP_SGEIP;
> + env->mie &= ~((uint64_t)MIP_SGEIP);
> }
> +
> return RISCV_EXCP_NONE;
> }
>
> +static RISCVException rmw_mie(CPURISCVState *env, int csrno,
> + target_ulong *ret_val,
> + target_ulong new_val, target_ulong wr_mask)
> +{
> + uint64_t rval;
> + RISCVException ret;
> +
> + ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask);
> + if (ret_val) {
> + *ret_val = rval;
> + }
> +
> + return ret;
> +}
> +
> +static RISCVException rmw_mieh(CPURISCVState *env, int csrno,
> + target_ulong *ret_val,
> + target_ulong new_val, target_ulong wr_mask)
> +{
> + uint64_t rval;
> + RISCVException ret;
> +
> + ret = rmw_mie64(env, csrno, &rval,
> + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
> + if (ret_val) {
> + *ret_val = rval >> 32;
> + }
> +
> + return ret;
> +}
> +
> static RISCVException read_mtvec(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> @@ -786,17 +889,17 @@ static RISCVException write_mtval(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> -static RISCVException rmw_mip(CPURISCVState *env, int csrno,
> - target_ulong *ret_value,
> - target_ulong new_value, target_ulong write_mask)
> +static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
> + uint64_t *ret_val,
> + uint64_t new_val, uint64_t wr_mask)
> {
> RISCVCPU *cpu = env_archcpu(env);
> /* Allow software control of delegable interrupts not claimed by hardware */
> - target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
> - uint32_t gin, old_mip;
> + uint64_t old_mip, mask = wr_mask & delegable_ints & ~env->miclaim;
> + uint32_t gin;
>
> if (mask) {
> - old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
> + old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask));
> } else {
> old_mip = env->mip;
> }
> @@ -806,13 +909,44 @@ static RISCVException rmw_mip(CPURISCVState *env, int csrno,
> old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0;
> }
>
> - if (ret_value) {
> - *ret_value = old_mip;
> + if (ret_val) {
> + *ret_val = old_mip;
> }
>
> return RISCV_EXCP_NONE;
> }
>
> +static RISCVException rmw_mip(CPURISCVState *env, int csrno,
> + target_ulong *ret_val,
> + target_ulong new_val, target_ulong wr_mask)
> +{
> + uint64_t rval;
> + RISCVException ret;
> +
> + ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask);
> + if (ret_val) {
> + *ret_val = rval;
> + }
> +
> + return ret;
> +}
> +
> +static RISCVException rmw_miph(CPURISCVState *env, int csrno,
> + target_ulong *ret_val,
> + target_ulong new_val, target_ulong wr_mask)
> +{
> + uint64_t rval;
> + RISCVException ret;
> +
> + ret = rmw_mip64(env, csrno, &rval,
> + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
> + if (ret_val) {
> + *ret_val = rval >> 32;
> + }
> +
> + return ret;
> +}
> +
> /* Supervisor Trap Setup */
> static RISCVException read_sstatus(CPURISCVState *env, int csrno,
> target_ulong *val)
> @@ -832,45 +966,112 @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno,
> return write_mstatus(env, CSR_MSTATUS, newval);
> }
>
> -static RISCVException read_vsie(CPURISCVState *env, int csrno,
> - target_ulong *val)
> +static RISCVException rmw_vsie64(CPURISCVState *env, int csrno,
> + uint64_t *ret_val,
> + uint64_t new_val, uint64_t wr_mask)
> {
> - /* Shift the VS bits to their S bit location in vsie */
> - *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
> - return RISCV_EXCP_NONE;
> + RISCVException ret;
> + uint64_t rval, vsbits, mask = env->hideleg & VS_MODE_INTERRUPTS;
> +
> + /* Bring VS-level bits to correct position */
> + vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
> + new_val &= ~(VS_MODE_INTERRUPTS >> 1);
> + new_val |= vsbits << 1;
> + vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
> + wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
> + wr_mask |= vsbits << 1;
> +
> + ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask);
> + if (ret_val) {
> + rval &= mask;
> + vsbits = rval & VS_MODE_INTERRUPTS;
> + rval &= ~VS_MODE_INTERRUPTS;
> + *ret_val = rval | (vsbits >> 1);
> + }
> +
> + return ret;
> }
>
> -static RISCVException read_sie(CPURISCVState *env, int csrno,
> - target_ulong *val)
> +static RISCVException rmw_vsie(CPURISCVState *env, int csrno,
> + target_ulong *ret_val,
> + target_ulong new_val, target_ulong wr_mask)
> {
> - if (riscv_cpu_virt_enabled(env)) {
> - read_vsie(env, CSR_VSIE, val);
> - } else {
> - *val = env->mie & env->mideleg;
> + uint64_t rval;
> + RISCVException ret;
> +
> + ret = rmw_vsie64(env, csrno, &rval, new_val, wr_mask);
> + if (ret_val) {
> + *ret_val = rval;
> }
> - return RISCV_EXCP_NONE;
> +
> + return ret;
> }
>
> -static RISCVException write_vsie(CPURISCVState *env, int csrno,
> - target_ulong val)
> +static RISCVException rmw_vsieh(CPURISCVState *env, int csrno,
> + target_ulong *ret_val,
> + target_ulong new_val, target_ulong wr_mask)
> {
> - /* Shift the S bits to their VS bit location in mie */
> - target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
> - ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
> - return write_mie(env, CSR_MIE, newval);
> + uint64_t rval;
> + RISCVException ret;
> +
> + ret = rmw_vsie64(env, csrno, &rval,
> + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
> + if (ret_val) {
> + *ret_val = rval >> 32;
> + }
> +
> + return ret;
> }
>
> -static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
> +static RISCVException rmw_sie64(CPURISCVState *env, int csrno,
> + uint64_t *ret_val,
> + uint64_t new_val, uint64_t wr_mask)
> {
> + RISCVException ret;
> + uint64_t mask = env->mideleg & S_MODE_INTERRUPTS;
> +
> if (riscv_cpu_virt_enabled(env)) {
> - write_vsie(env, CSR_VSIE, val);
> + ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask);
> } else {
> - target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
> - (val & S_MODE_INTERRUPTS);
> - write_mie(env, CSR_MIE, newval);
> + ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask);
> }
>
> - return RISCV_EXCP_NONE;
> + if (ret_val) {
> + *ret_val &= mask;
> + }
> +
> + return ret;
> +}
> +
> +static RISCVException rmw_sie(CPURISCVState *env, int csrno,
> + target_ulong *ret_val,
> + target_ulong new_val, target_ulong wr_mask)
> +{
> + uint64_t rval;
> + RISCVException ret;
> +
> + ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask);
> + if (ret_val) {
> + *ret_val = rval;
> + }
> +
> + return ret;
> +}
> +
> +static RISCVException rmw_sieh(CPURISCVState *env, int csrno,
> + target_ulong *ret_val,
> + target_ulong new_val, target_ulong wr_mask)
> +{
> + uint64_t rval;
> + RISCVException ret;
> +
> + ret = rmw_sie64(env, csrno, &rval,
> + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
> + if (ret_val) {
> + *ret_val = rval >> 32;
> + }
> +
> + return ret;
> }
>
> static RISCVException read_stvec(CPURISCVState *env, int csrno,
> @@ -963,38 +1164,111 @@ static RISCVException write_stval(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> +static RISCVException rmw_vsip64(CPURISCVState *env, int csrno,
> + uint64_t *ret_val,
> + uint64_t new_val, uint64_t wr_mask)
> +{
> + RISCVException ret;
> + uint64_t rval, vsbits, mask = env->hideleg & vsip_writable_mask;
> +
> + /* Bring VS-level bits to correct position */
> + vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
> + new_val &= ~(VS_MODE_INTERRUPTS >> 1);
> + new_val |= vsbits << 1;
> + vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
> + wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
> + wr_mask |= vsbits << 1;
> +
> + ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask);
> + if (ret_val) {
> + rval &= mask;
> + vsbits = rval & VS_MODE_INTERRUPTS;
> + rval &= ~VS_MODE_INTERRUPTS;
> + *ret_val = rval | (vsbits >> 1);
> + }
> +
> + return ret;
> +}
> +
> static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
> - target_ulong *ret_value,
> - target_ulong new_value, target_ulong write_mask)
> + target_ulong *ret_val,
> + target_ulong new_val, target_ulong wr_mask)
> {
> - /* Shift the S bits to their VS bit location in mip */
> - int ret = rmw_mip(env, csrno, ret_value, new_value << 1,
> - (write_mask << 1) & vsip_writable_mask & env->hideleg);
> + uint64_t rval;
> + RISCVException ret;
>
> - if (ret_value) {
> - *ret_value &= VS_MODE_INTERRUPTS;
> - /* Shift the VS bits to their S bit location in vsip */
> - *ret_value >>= 1;
> + ret = rmw_vsip64(env, csrno, &rval, new_val, wr_mask);
> + if (ret_val) {
> + *ret_val = rval;
> }
> +
> return ret;
> }
>
> -static RISCVException rmw_sip(CPURISCVState *env, int csrno,
> - target_ulong *ret_value,
> - target_ulong new_value, target_ulong write_mask)
> +static RISCVException rmw_vsiph(CPURISCVState *env, int csrno,
> + target_ulong *ret_val,
> + target_ulong new_val, target_ulong wr_mask)
> {
> - int ret;
> + uint64_t rval;
> + RISCVException ret;
> +
> + ret = rmw_vsip64(env, csrno, &rval,
> + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
> + if (ret_val) {
> + *ret_val = rval >> 32;
> + }
> +
> + return ret;
> +}
> +
> +static RISCVException rmw_sip64(CPURISCVState *env, int csrno,
> + uint64_t *ret_val,
> + uint64_t new_val, uint64_t wr_mask)
> +{
> + RISCVException ret;
> + uint64_t mask = env->mideleg & sip_writable_mask;
>
> if (riscv_cpu_virt_enabled(env)) {
> - ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
> + ret = rmw_vsip64(env, CSR_VSIE, ret_val, new_val, wr_mask);
Why change the csrno to CSR_VSIE?
Alistair
> } else {
> - ret = rmw_mip(env, csrno, ret_value, new_value,
> - write_mask & env->mideleg & sip_writable_mask);
> + ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask);
> }
>
> - if (ret_value) {
> - *ret_value &= env->mideleg & S_MODE_INTERRUPTS;
> + if (ret_val) {
> + *ret_val &= env->mideleg & S_MODE_INTERRUPTS;
> + }
> +
> + return ret;
> +}
> +
> +static RISCVException rmw_sip(CPURISCVState *env, int csrno,
> + target_ulong *ret_val,
> + target_ulong new_val, target_ulong wr_mask)
> +{
> + uint64_t rval;
> + RISCVException ret;
> +
> + ret = rmw_sip64(env, csrno, &rval, new_val, wr_mask);
> + if (ret_val) {
> + *ret_val = rval;
> }
> +
> + return ret;
> +}
> +
> +static RISCVException rmw_siph(CPURISCVState *env, int csrno,
> + target_ulong *ret_val,
> + target_ulong new_val, target_ulong wr_mask)
> +{
> + uint64_t rval;
> + RISCVException ret;
> +
> + ret = rmw_sip64(env, csrno, &rval,
> + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
> + if (ret_val) {
> + *ret_val = rval >> 32;
> + }
> +
> return ret;
> }
>
> @@ -1089,30 +1363,94 @@ static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> -static RISCVException read_hideleg(CPURISCVState *env, int csrno,
> - target_ulong *val)
> +static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno,
> + uint64_t *ret_val,
> + uint64_t new_val, uint64_t wr_mask)
> {
> - *val = env->hideleg;
> + uint64_t mask = wr_mask & vs_delegable_ints;
> +
> + if (ret_val) {
> + *ret_val = env->hideleg & vs_delegable_ints;
> + }
> +
> + env->hideleg = (env->hideleg & ~mask) | (new_val & mask);
> return RISCV_EXCP_NONE;
> }
>
> -static RISCVException write_hideleg(CPURISCVState *env, int csrno,
> - target_ulong val)
> +static RISCVException rmw_hideleg(CPURISCVState *env, int csrno,
> + target_ulong *ret_val,
> + target_ulong new_val, target_ulong wr_mask)
> {
> - env->hideleg = val & vs_delegable_ints;
> - return RISCV_EXCP_NONE;
> + uint64_t rval;
> + RISCVException ret;
> +
> + ret = rmw_hideleg64(env, csrno, &rval, new_val, wr_mask);
> + if (ret_val) {
> + *ret_val = rval;
> + }
> +
> + return ret;
> +}
> +
> +static RISCVException rmw_hidelegh(CPURISCVState *env, int csrno,
> + target_ulong *ret_val,
> + target_ulong new_val, target_ulong wr_mask)
> +{
> + uint64_t rval;
> + RISCVException ret;
> +
> + ret = rmw_hideleg64(env, csrno, &rval,
> + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
> + if (ret_val) {
> + *ret_val = rval >> 32;
> + }
> +
> + return ret;
> +}
> +
> +static RISCVException rmw_hvip64(CPURISCVState *env, int csrno,
> + uint64_t *ret_val,
> + uint64_t new_val, uint64_t wr_mask)
> +{
> + RISCVException ret;
> +
> + ret = rmw_mip64(env, csrno, ret_val, new_val,
> + wr_mask & hvip_writable_mask);
> + if (ret_val) {
> + *ret_val &= VS_MODE_INTERRUPTS;
> + }
> +
> + return ret;
> }
>
> static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
> - target_ulong *ret_value,
> - target_ulong new_value, target_ulong write_mask)
> + target_ulong *ret_val,
> + target_ulong new_val, target_ulong wr_mask)
> {
> - int ret = rmw_mip(env, csrno, ret_value, new_value,
> - write_mask & hvip_writable_mask);
> + uint64_t rval;
> + RISCVException ret;
>
> - if (ret_value) {
> - *ret_value &= VS_MODE_INTERRUPTS;
> + ret = rmw_hvip64(env, csrno, &rval, new_val, wr_mask);
> + if (ret_val) {
> + *ret_val = rval;
> + }
> +
> + return ret;
> +}
> +
> +static RISCVException rmw_hviph(CPURISCVState *env, int csrno,
> + target_ulong *ret_val,
> + target_ulong new_val, target_ulong wr_mask)
> +{
> + uint64_t rval;
> + RISCVException ret;
> +
> + ret = rmw_hvip64(env, csrno, &rval,
> + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
> + if (ret_val) {
> + *ret_val = rval >> 32;
> }
> +
> return ret;
> }
>
> @@ -1129,18 +1467,19 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
> return ret;
> }
>
> -static RISCVException read_hie(CPURISCVState *env, int csrno,
> - target_ulong *val)
> +static RISCVException rmw_hie(CPURISCVState *env, int csrno,
> + target_ulong *ret_val,
> + target_ulong new_val, target_ulong wr_mask)
> {
> - *val = env->mie & HS_MODE_INTERRUPTS;
> - return RISCV_EXCP_NONE;
> -}
> + uint64_t rval;
> + RISCVException ret;
>
> -static RISCVException write_hie(CPURISCVState *env, int csrno,
> - target_ulong val)
> -{
> - target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_MODE_INTERRUPTS);
> - return write_mie(env, CSR_MIE, newval);
> + ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERRUPTS);
> + if (ret_val) {
> + *ret_val = rval & HS_MODE_INTERRUPTS;
> + }
> +
> + return ret;
> }
>
> static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
> @@ -1598,9 +1937,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> /* Machine Trap Setup */
> [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus },
> [CSR_MISA] = { "misa", any, read_misa, write_misa },
> - [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg },
> + [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg },
> [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg },
> - [CSR_MIE] = { "mie", any, read_mie, write_mie },
> + [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie },
> [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec },
> [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren },
>
> @@ -1613,9 +1952,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval },
> [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
>
> + /* Machine-Level High-Half CSRs (AIA) */
> + [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
> + [CSR_MIEH] = { "mieh", aia_any32, NULL, NULL, rmw_mieh },
> + [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph },
> +
> /* Supervisor Trap Setup */
> [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus },
> - [CSR_SIE] = { "sie", smode, read_sie, write_sie },
> + [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie },
> [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },
> [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
>
> @@ -1629,12 +1973,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> /* Supervisor Protection and Translation */
> [CSR_SATP] = { "satp", smode, read_satp, write_satp },
>
> + /* Supervisor-Level High-Half CSRs (AIA) */
> + [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
> + [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph },
> +
> [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus },
> [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg },
> - [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg },
> + [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg },
> [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip },
> [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip },
> - [CSR_HIE] = { "hie", hmode, read_hie, write_hie },
> + [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie },
> [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren },
> [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie },
> [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval },
> @@ -1646,7 +1994,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>
> [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus },
> [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip },
> - [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie },
> + [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie },
> [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec },
> [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch },
> [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc },
> @@ -1657,6 +2005,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 },
> [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst },
>
> + /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
> + [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh },
> + [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph },
> + [CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh },
> + [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph },
> +
> /* Physical Memory Protection */
> [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg },
> [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index a7102220b6..7356d70be6 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -108,7 +108,7 @@ static const VMStateDescription vmstate_hyper = {
> .fields = (VMStateField[]) {
> VMSTATE_UINTTL(env.hstatus, RISCVCPU),
> VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
> - VMSTATE_UINTTL(env.hideleg, RISCVCPU),
> + VMSTATE_UINT64(env.hideleg, RISCVCPU),
> VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
> VMSTATE_UINTTL(env.htval, RISCVCPU),
> VMSTATE_UINTTL(env.htinst, RISCVCPU),
> @@ -168,10 +168,10 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINTTL(env.resetvec, RISCVCPU),
> VMSTATE_UINTTL(env.mhartid, RISCVCPU),
> VMSTATE_UINT64(env.mstatus, RISCVCPU),
> - VMSTATE_UINTTL(env.mip, RISCVCPU),
> - VMSTATE_UINT32(env.miclaim, RISCVCPU),
> - VMSTATE_UINTTL(env.mie, RISCVCPU),
> - VMSTATE_UINTTL(env.mideleg, RISCVCPU),
> + VMSTATE_UINT64(env.mip, RISCVCPU),
> + VMSTATE_UINT64(env.miclaim, RISCVCPU),
> + VMSTATE_UINT64(env.mie, RISCVCPU),
> + VMSTATE_UINT64(env.mideleg, RISCVCPU),
> VMSTATE_UINTTL(env.satp, RISCVCPU),
> VMSTATE_UINTTL(env.stval, RISCVCPU),
> VMSTATE_UINTTL(env.medeleg, RISCVCPU),
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v4 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
2021-11-04 4:43 ` Alistair Francis
@ 2021-12-09 6:14 ` Anup Patel
0 siblings, 0 replies; 41+ messages in thread
From: Anup Patel @ 2021-12-09 6:14 UTC (permalink / raw)
To: Alistair Francis
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt, Bin Meng
On Thu, Nov 4, 2021 at 10:13 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Tue, Oct 26, 2021 at 5:10 PM Anup Patel <anup.patel@wdc.com> wrote:
> >
> > The AIA specification adds new CSRs for RV32 so that RISC-V hart can
> > support 64 local interrupts on both RV32 and RV64.
> >
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
> > target/riscv/cpu.h | 14 +-
> > target/riscv/cpu_helper.c | 10 +-
> > target/riscv/csr.c | 560 +++++++++++++++++++++++++++++++-------
> > target/riscv/machine.c | 10 +-
> > 4 files changed, 474 insertions(+), 120 deletions(-)
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index c47e57efc8..718a95e864 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -159,12 +159,12 @@ struct CPURISCVState {
> > */
> > uint64_t mstatus;
> >
> > - target_ulong mip;
> > + uint64_t mip;
> >
> > - uint32_t miclaim;
> > + uint64_t miclaim;
> >
> > - target_ulong mie;
> > - target_ulong mideleg;
> > + uint64_t mie;
> > + uint64_t mideleg;
> >
> > target_ulong satp; /* since: priv-1.10.0 */
> > target_ulong stval;
> > @@ -186,7 +186,7 @@ struct CPURISCVState {
> > /* Hypervisor CSRs */
> > target_ulong hstatus;
> > target_ulong hedeleg;
> > - target_ulong hideleg;
> > + uint64_t hideleg;
> > target_ulong hcounteren;
> > target_ulong htval;
> > target_ulong htinst;
> > @@ -399,8 +399,8 @@ void riscv_cpu_list(void);
> > #ifndef CONFIG_USER_ONLY
> > bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
> > void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
> > -int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
> > -uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
> > +int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
> > +uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value);
> > #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
> > void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
> > uint32_t arg);
> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> > index 73ebce1efd..416b11f85c 100644
> > --- a/target/riscv/cpu_helper.c
> > +++ b/target/riscv/cpu_helper.c
> > @@ -506,7 +506,7 @@ bool riscv_cpu_two_stage_lookup(int mmu_idx)
> > return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK;
> > }
> >
> > -int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
> > +int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
> > {
> > CPURISCVState *env = &cpu->env;
> > if (env->miclaim & interrupts) {
> > @@ -517,11 +517,11 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
> > }
> > }
> >
> > -uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
> > +uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value)
> > {
> > CPURISCVState *env = &cpu->env;
> > CPUState *cs = CPU(cpu);
> > - uint32_t gein, vsgein = 0, old = env->mip;
> > + uint64_t gein, vsgein = 0, old = env->mip;
> > bool locked = false;
> >
> > if (riscv_cpu_virt_enabled(env)) {
> > @@ -1244,7 +1244,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> > */
> > bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
> > target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
> > - target_ulong deleg = async ? env->mideleg : env->medeleg;
> > + uint64_t deleg = async ? env->mideleg : env->medeleg;
> > bool write_tval = false;
> > target_ulong tval = 0;
> > target_ulong htval = 0;
> > @@ -1311,7 +1311,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> > cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
> > /* handle the trap in S-mode */
> > if (riscv_has_ext(env, RVH)) {
> > - target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
> > + uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
> >
> > if (env->two_stage_lookup && write_tval) {
> > /*
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index 7ff285282b..3a7d89ac34 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -153,6 +153,15 @@ static RISCVException any32(CPURISCVState *env, int csrno)
> >
> > }
> >
> > +static int aia_any32(CPURISCVState *env, int csrno)
> > +{
> > + if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
> > + return RISCV_EXCP_ILLEGAL_INST;
> > + }
> > +
> > + return any32(env, csrno);
> > +}
> > +
> > static RISCVException smode(CPURISCVState *env, int csrno)
> > {
> > if (riscv_has_ext(env, RVS)) {
> > @@ -162,6 +171,24 @@ static RISCVException smode(CPURISCVState *env, int csrno)
> > return RISCV_EXCP_ILLEGAL_INST;
> > }
> >
> > +static int smode32(CPURISCVState *env, int csrno)
> > +{
> > + if (riscv_cpu_mxl(env) != MXL_RV32) {
> > + return RISCV_EXCP_ILLEGAL_INST;
> > + }
> > +
> > + return smode(env, csrno);
> > +}
> > +
> > +static int aia_smode32(CPURISCVState *env, int csrno)
> > +{
> > + if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
> > + return RISCV_EXCP_ILLEGAL_INST;
> > + }
> > +
> > + return smode32(env, csrno);
> > +}
> > +
> > static RISCVException hmode(CPURISCVState *env, int csrno)
> > {
> > if (riscv_has_ext(env, RVS) &&
> > @@ -192,6 +219,15 @@ static RISCVException hmode32(CPURISCVState *env, int csrno)
> >
> > }
> >
> > +static int aia_hmode32(CPURISCVState *env, int csrno)
> > +{
> > + if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
> > + return RISCV_EXCP_ILLEGAL_INST;
> > + }
> > +
> > + return hmode32(env, csrno);
> > +}
> > +
> > static RISCVException pmp(CPURISCVState *env, int csrno)
> > {
> > if (riscv_feature(env, RISCV_FEATURE_PMP)) {
> > @@ -405,15 +441,15 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
> >
> > /* Machine constants */
> >
> > -#define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
> > -#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
> > -#define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
> > -#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS)
> > +#define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP))
> > +#define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP))
> > +#define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
> > +#define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
> >
> > -static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
> > +static const uint64_t delegable_ints = S_MODE_INTERRUPTS |
> > VS_MODE_INTERRUPTS;
> > -static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
> > -static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
> > +static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS;
> > +static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
> > HS_MODE_INTERRUPTS;
> > #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
> > (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
> > @@ -662,40 +698,107 @@ static RISCVException write_medeleg(CPURISCVState *env, int csrno,
> > return RISCV_EXCP_NONE;
> > }
> >
> > -static RISCVException read_mideleg(CPURISCVState *env, int csrno,
> > - target_ulong *val)
> > +static RISCVException rmw_mideleg64(CPURISCVState *env, int csrno,
> > + uint64_t *ret_val,
> > + uint64_t new_val, uint64_t wr_mask)
> > {
> > - *val = env->mideleg;
> > - return RISCV_EXCP_NONE;
> > -}
> > + uint64_t mask = wr_mask & delegable_ints;
> > +
> > + if (ret_val) {
> > + *ret_val = env->mideleg;
> > + }
> > +
> > + env->mideleg = (env->mideleg & ~mask) | (new_val & mask);
> >
> > -static RISCVException write_mideleg(CPURISCVState *env, int csrno,
> > - target_ulong val)
> > -{
> > - env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
> > if (riscv_has_ext(env, RVH)) {
> > env->mideleg |= HS_MODE_INTERRUPTS;
> > }
> > +
> > return RISCV_EXCP_NONE;
> > }
> >
> > -static RISCVException read_mie(CPURISCVState *env, int csrno,
> > - target_ulong *val)
> > +static RISCVException rmw_mideleg(CPURISCVState *env, int csrno,
> > + target_ulong *ret_val,
> > + target_ulong new_val, target_ulong wr_mask)
> > {
> > - *val = env->mie;
> > - return RISCV_EXCP_NONE;
> > + uint64_t rval;
> > + RISCVException ret;
> > +
> > + ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask);
> > + if (ret_val) {
> > + *ret_val = rval;
> > + }
> > +
> > + return ret;
> > }
> >
> > -static RISCVException write_mie(CPURISCVState *env, int csrno,
> > - target_ulong val)
> > +static RISCVException rmw_midelegh(CPURISCVState *env, int csrno,
> > + target_ulong *ret_val,
> > + target_ulong new_val,
> > + target_ulong wr_mask)
> > {
> > - env->mie = (env->mie & ~all_ints) | (val & all_ints);
> > + uint64_t rval;
> > + RISCVException ret;
> > +
> > + ret = rmw_mideleg64(env, csrno, &rval,
> > + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
> > + if (ret_val) {
> > + *ret_val = rval >> 32;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static RISCVException rmw_mie64(CPURISCVState *env, int csrno,
> > + uint64_t *ret_val,
> > + uint64_t new_val, uint64_t wr_mask)
> > +{
> > + uint64_t mask = wr_mask & all_ints;
> > +
> > + if (ret_val) {
> > + *ret_val = env->mie;
> > + }
> > +
> > + env->mie = (env->mie & ~mask) | (new_val & mask);
> > +
> > if (!riscv_has_ext(env, RVH)) {
> > - env->mie &= ~MIP_SGEIP;
> > + env->mie &= ~((uint64_t)MIP_SGEIP);
> > }
> > +
> > return RISCV_EXCP_NONE;
> > }
> >
> > +static RISCVException rmw_mie(CPURISCVState *env, int csrno,
> > + target_ulong *ret_val,
> > + target_ulong new_val, target_ulong wr_mask)
> > +{
> > + uint64_t rval;
> > + RISCVException ret;
> > +
> > + ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask);
> > + if (ret_val) {
> > + *ret_val = rval;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static RISCVException rmw_mieh(CPURISCVState *env, int csrno,
> > + target_ulong *ret_val,
> > + target_ulong new_val, target_ulong wr_mask)
> > +{
> > + uint64_t rval;
> > + RISCVException ret;
> > +
> > + ret = rmw_mie64(env, csrno, &rval,
> > + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
> > + if (ret_val) {
> > + *ret_val = rval >> 32;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > static RISCVException read_mtvec(CPURISCVState *env, int csrno,
> > target_ulong *val)
> > {
> > @@ -786,17 +889,17 @@ static RISCVException write_mtval(CPURISCVState *env, int csrno,
> > return RISCV_EXCP_NONE;
> > }
> >
> > -static RISCVException rmw_mip(CPURISCVState *env, int csrno,
> > - target_ulong *ret_value,
> > - target_ulong new_value, target_ulong write_mask)
> > +static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
> > + uint64_t *ret_val,
> > + uint64_t new_val, uint64_t wr_mask)
> > {
> > RISCVCPU *cpu = env_archcpu(env);
> > /* Allow software control of delegable interrupts not claimed by hardware */
> > - target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
> > - uint32_t gin, old_mip;
> > + uint64_t old_mip, mask = wr_mask & delegable_ints & ~env->miclaim;
> > + uint32_t gin;
> >
> > if (mask) {
> > - old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
> > + old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask));
> > } else {
> > old_mip = env->mip;
> > }
> > @@ -806,13 +909,44 @@ static RISCVException rmw_mip(CPURISCVState *env, int csrno,
> > old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0;
> > }
> >
> > - if (ret_value) {
> > - *ret_value = old_mip;
> > + if (ret_val) {
> > + *ret_val = old_mip;
> > }
> >
> > return RISCV_EXCP_NONE;
> > }
> >
> > +static RISCVException rmw_mip(CPURISCVState *env, int csrno,
> > + target_ulong *ret_val,
> > + target_ulong new_val, target_ulong wr_mask)
> > +{
> > + uint64_t rval;
> > + RISCVException ret;
> > +
> > + ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask);
> > + if (ret_val) {
> > + *ret_val = rval;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static RISCVException rmw_miph(CPURISCVState *env, int csrno,
> > + target_ulong *ret_val,
> > + target_ulong new_val, target_ulong wr_mask)
> > +{
> > + uint64_t rval;
> > + RISCVException ret;
> > +
> > + ret = rmw_mip64(env, csrno, &rval,
> > + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
> > + if (ret_val) {
> > + *ret_val = rval >> 32;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > /* Supervisor Trap Setup */
> > static RISCVException read_sstatus(CPURISCVState *env, int csrno,
> > target_ulong *val)
> > @@ -832,45 +966,112 @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno,
> > return write_mstatus(env, CSR_MSTATUS, newval);
> > }
> >
> > -static RISCVException read_vsie(CPURISCVState *env, int csrno,
> > - target_ulong *val)
> > +static RISCVException rmw_vsie64(CPURISCVState *env, int csrno,
> > + uint64_t *ret_val,
> > + uint64_t new_val, uint64_t wr_mask)
> > {
> > - /* Shift the VS bits to their S bit location in vsie */
> > - *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
> > - return RISCV_EXCP_NONE;
> > + RISCVException ret;
> > + uint64_t rval, vsbits, mask = env->hideleg & VS_MODE_INTERRUPTS;
> > +
> > + /* Bring VS-level bits to correct position */
> > + vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
> > + new_val &= ~(VS_MODE_INTERRUPTS >> 1);
> > + new_val |= vsbits << 1;
> > + vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
> > + wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
> > + wr_mask |= vsbits << 1;
> > +
> > + ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask);
> > + if (ret_val) {
> > + rval &= mask;
> > + vsbits = rval & VS_MODE_INTERRUPTS;
> > + rval &= ~VS_MODE_INTERRUPTS;
> > + *ret_val = rval | (vsbits >> 1);
> > + }
> > +
> > + return ret;
> > }
> >
> > -static RISCVException read_sie(CPURISCVState *env, int csrno,
> > - target_ulong *val)
> > +static RISCVException rmw_vsie(CPURISCVState *env, int csrno,
> > + target_ulong *ret_val,
> > + target_ulong new_val, target_ulong wr_mask)
> > {
> > - if (riscv_cpu_virt_enabled(env)) {
> > - read_vsie(env, CSR_VSIE, val);
> > - } else {
> > - *val = env->mie & env->mideleg;
> > + uint64_t rval;
> > + RISCVException ret;
> > +
> > + ret = rmw_vsie64(env, csrno, &rval, new_val, wr_mask);
> > + if (ret_val) {
> > + *ret_val = rval;
> > }
> > - return RISCV_EXCP_NONE;
> > +
> > + return ret;
> > }
> >
> > -static RISCVException write_vsie(CPURISCVState *env, int csrno,
> > - target_ulong val)
> > +static RISCVException rmw_vsieh(CPURISCVState *env, int csrno,
> > + target_ulong *ret_val,
> > + target_ulong new_val, target_ulong wr_mask)
> > {
> > - /* Shift the S bits to their VS bit location in mie */
> > - target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
> > - ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
> > - return write_mie(env, CSR_MIE, newval);
> > + uint64_t rval;
> > + RISCVException ret;
> > +
> > + ret = rmw_vsie64(env, csrno, &rval,
> > + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
> > + if (ret_val) {
> > + *ret_val = rval >> 32;
> > + }
> > +
> > + return ret;
> > }
> >
> > -static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
> > +static RISCVException rmw_sie64(CPURISCVState *env, int csrno,
> > + uint64_t *ret_val,
> > + uint64_t new_val, uint64_t wr_mask)
> > {
> > + RISCVException ret;
> > + uint64_t mask = env->mideleg & S_MODE_INTERRUPTS;
> > +
> > if (riscv_cpu_virt_enabled(env)) {
> > - write_vsie(env, CSR_VSIE, val);
> > + ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask);
> > } else {
> > - target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
> > - (val & S_MODE_INTERRUPTS);
> > - write_mie(env, CSR_MIE, newval);
> > + ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask);
> > }
> >
> > - return RISCV_EXCP_NONE;
> > + if (ret_val) {
> > + *ret_val &= mask;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static RISCVException rmw_sie(CPURISCVState *env, int csrno,
> > + target_ulong *ret_val,
> > + target_ulong new_val, target_ulong wr_mask)
> > +{
> > + uint64_t rval;
> > + RISCVException ret;
> > +
> > + ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask);
> > + if (ret_val) {
> > + *ret_val = rval;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static RISCVException rmw_sieh(CPURISCVState *env, int csrno,
> > + target_ulong *ret_val,
> > + target_ulong new_val, target_ulong wr_mask)
> > +{
> > + uint64_t rval;
> > + RISCVException ret;
> > +
> > + ret = rmw_sie64(env, csrno, &rval,
> > + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
> > + if (ret_val) {
> > + *ret_val = rval >> 32;
> > + }
> > +
> > + return ret;
> > }
> >
> > static RISCVException read_stvec(CPURISCVState *env, int csrno,
> > @@ -963,38 +1164,111 @@ static RISCVException write_stval(CPURISCVState *env, int csrno,
> > return RISCV_EXCP_NONE;
> > }
> >
> > +static RISCVException rmw_vsip64(CPURISCVState *env, int csrno,
> > + uint64_t *ret_val,
> > + uint64_t new_val, uint64_t wr_mask)
> > +{
> > + RISCVException ret;
> > + uint64_t rval, vsbits, mask = env->hideleg & vsip_writable_mask;
> > +
> > + /* Bring VS-level bits to correct position */
> > + vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
> > + new_val &= ~(VS_MODE_INTERRUPTS >> 1);
> > + new_val |= vsbits << 1;
> > + vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
> > + wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
> > + wr_mask |= vsbits << 1;
> > +
> > + ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask);
> > + if (ret_val) {
> > + rval &= mask;
> > + vsbits = rval & VS_MODE_INTERRUPTS;
> > + rval &= ~VS_MODE_INTERRUPTS;
> > + *ret_val = rval | (vsbits >> 1);
> > + }
> > +
> > + return ret;
> > +}
> > +
> > static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
> > - target_ulong *ret_value,
> > - target_ulong new_value, target_ulong write_mask)
> > + target_ulong *ret_val,
> > + target_ulong new_val, target_ulong wr_mask)
> > {
> > - /* Shift the S bits to their VS bit location in mip */
> > - int ret = rmw_mip(env, csrno, ret_value, new_value << 1,
> > - (write_mask << 1) & vsip_writable_mask & env->hideleg);
> > + uint64_t rval;
> > + RISCVException ret;
> >
> > - if (ret_value) {
> > - *ret_value &= VS_MODE_INTERRUPTS;
> > - /* Shift the VS bits to their S bit location in vsip */
> > - *ret_value >>= 1;
> > + ret = rmw_vsip64(env, csrno, &rval, new_val, wr_mask);
> > + if (ret_val) {
> > + *ret_val = rval;
> > }
> > +
> > return ret;
> > }
> >
> > -static RISCVException rmw_sip(CPURISCVState *env, int csrno,
> > - target_ulong *ret_value,
> > - target_ulong new_value, target_ulong write_mask)
> > +static RISCVException rmw_vsiph(CPURISCVState *env, int csrno,
> > + target_ulong *ret_val,
> > + target_ulong new_val, target_ulong wr_mask)
> > {
> > - int ret;
> > + uint64_t rval;
> > + RISCVException ret;
> > +
> > + ret = rmw_vsip64(env, csrno, &rval,
> > + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
> > + if (ret_val) {
> > + *ret_val = rval >> 32;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static RISCVException rmw_sip64(CPURISCVState *env, int csrno,
> > + uint64_t *ret_val,
> > + uint64_t new_val, uint64_t wr_mask)
> > +{
> > + RISCVException ret;
> > + uint64_t mask = env->mideleg & sip_writable_mask;
> >
> > if (riscv_cpu_virt_enabled(env)) {
> > - ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
> > + ret = rmw_vsip64(env, CSR_VSIE, ret_val, new_val, wr_mask);
>
> Why change the csrno to CSR_VSIE?
Thanks for catching, this is a typo. I will fix it in next revision.
Regards,
Anup
>
> Alistair
>
> > } else {
> > - ret = rmw_mip(env, csrno, ret_value, new_value,
> > - write_mask & env->mideleg & sip_writable_mask);
> > + ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask);
> > }
> >
> > - if (ret_value) {
> > - *ret_value &= env->mideleg & S_MODE_INTERRUPTS;
> > + if (ret_val) {
> > + *ret_val &= env->mideleg & S_MODE_INTERRUPTS;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static RISCVException rmw_sip(CPURISCVState *env, int csrno,
> > + target_ulong *ret_val,
> > + target_ulong new_val, target_ulong wr_mask)
> > +{
> > + uint64_t rval;
> > + RISCVException ret;
> > +
> > + ret = rmw_sip64(env, csrno, &rval, new_val, wr_mask);
> > + if (ret_val) {
> > + *ret_val = rval;
> > }
> > +
> > + return ret;
> > +}
> > +
> > +static RISCVException rmw_siph(CPURISCVState *env, int csrno,
> > + target_ulong *ret_val,
> > + target_ulong new_val, target_ulong wr_mask)
> > +{
> > + uint64_t rval;
> > + RISCVException ret;
> > +
> > + ret = rmw_sip64(env, csrno, &rval,
> > + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
> > + if (ret_val) {
> > + *ret_val = rval >> 32;
> > + }
> > +
> > return ret;
> > }
> >
> > @@ -1089,30 +1363,94 @@ static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
> > return RISCV_EXCP_NONE;
> > }
> >
> > -static RISCVException read_hideleg(CPURISCVState *env, int csrno,
> > - target_ulong *val)
> > +static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno,
> > + uint64_t *ret_val,
> > + uint64_t new_val, uint64_t wr_mask)
> > {
> > - *val = env->hideleg;
> > + uint64_t mask = wr_mask & vs_delegable_ints;
> > +
> > + if (ret_val) {
> > + *ret_val = env->hideleg & vs_delegable_ints;
> > + }
> > +
> > + env->hideleg = (env->hideleg & ~mask) | (new_val & mask);
> > return RISCV_EXCP_NONE;
> > }
> >
> > -static RISCVException write_hideleg(CPURISCVState *env, int csrno,
> > - target_ulong val)
> > +static RISCVException rmw_hideleg(CPURISCVState *env, int csrno,
> > + target_ulong *ret_val,
> > + target_ulong new_val, target_ulong wr_mask)
> > {
> > - env->hideleg = val & vs_delegable_ints;
> > - return RISCV_EXCP_NONE;
> > + uint64_t rval;
> > + RISCVException ret;
> > +
> > + ret = rmw_hideleg64(env, csrno, &rval, new_val, wr_mask);
> > + if (ret_val) {
> > + *ret_val = rval;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static RISCVException rmw_hidelegh(CPURISCVState *env, int csrno,
> > + target_ulong *ret_val,
> > + target_ulong new_val, target_ulong wr_mask)
> > +{
> > + uint64_t rval;
> > + RISCVException ret;
> > +
> > + ret = rmw_hideleg64(env, csrno, &rval,
> > + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
> > + if (ret_val) {
> > + *ret_val = rval >> 32;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static RISCVException rmw_hvip64(CPURISCVState *env, int csrno,
> > + uint64_t *ret_val,
> > + uint64_t new_val, uint64_t wr_mask)
> > +{
> > + RISCVException ret;
> > +
> > + ret = rmw_mip64(env, csrno, ret_val, new_val,
> > + wr_mask & hvip_writable_mask);
> > + if (ret_val) {
> > + *ret_val &= VS_MODE_INTERRUPTS;
> > + }
> > +
> > + return ret;
> > }
> >
> > static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
> > - target_ulong *ret_value,
> > - target_ulong new_value, target_ulong write_mask)
> > + target_ulong *ret_val,
> > + target_ulong new_val, target_ulong wr_mask)
> > {
> > - int ret = rmw_mip(env, csrno, ret_value, new_value,
> > - write_mask & hvip_writable_mask);
> > + uint64_t rval;
> > + RISCVException ret;
> >
> > - if (ret_value) {
> > - *ret_value &= VS_MODE_INTERRUPTS;
> > + ret = rmw_hvip64(env, csrno, &rval, new_val, wr_mask);
> > + if (ret_val) {
> > + *ret_val = rval;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static RISCVException rmw_hviph(CPURISCVState *env, int csrno,
> > + target_ulong *ret_val,
> > + target_ulong new_val, target_ulong wr_mask)
> > +{
> > + uint64_t rval;
> > + RISCVException ret;
> > +
> > + ret = rmw_hvip64(env, csrno, &rval,
> > + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
> > + if (ret_val) {
> > + *ret_val = rval >> 32;
> > }
> > +
> > return ret;
> > }
> >
> > @@ -1129,18 +1467,19 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
> > return ret;
> > }
> >
> > -static RISCVException read_hie(CPURISCVState *env, int csrno,
> > - target_ulong *val)
> > +static RISCVException rmw_hie(CPURISCVState *env, int csrno,
> > + target_ulong *ret_val,
> > + target_ulong new_val, target_ulong wr_mask)
> > {
> > - *val = env->mie & HS_MODE_INTERRUPTS;
> > - return RISCV_EXCP_NONE;
> > -}
> > + uint64_t rval;
> > + RISCVException ret;
> >
> > -static RISCVException write_hie(CPURISCVState *env, int csrno,
> > - target_ulong val)
> > -{
> > - target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_MODE_INTERRUPTS);
> > - return write_mie(env, CSR_MIE, newval);
> > + ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERRUPTS);
> > + if (ret_val) {
> > + *ret_val = rval & HS_MODE_INTERRUPTS;
> > + }
> > +
> > + return ret;
> > }
> >
> > static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
> > @@ -1598,9 +1937,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> > /* Machine Trap Setup */
> > [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus },
> > [CSR_MISA] = { "misa", any, read_misa, write_misa },
> > - [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg },
> > + [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg },
> > [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg },
> > - [CSR_MIE] = { "mie", any, read_mie, write_mie },
> > + [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie },
> > [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec },
> > [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren },
> >
> > @@ -1613,9 +1952,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> > [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval },
> > [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
> >
> > + /* Machine-Level High-Half CSRs (AIA) */
> > + [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
> > + [CSR_MIEH] = { "mieh", aia_any32, NULL, NULL, rmw_mieh },
> > + [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph },
> > +
> > /* Supervisor Trap Setup */
> > [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus },
> > - [CSR_SIE] = { "sie", smode, read_sie, write_sie },
> > + [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie },
> > [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },
> > [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
> >
> > @@ -1629,12 +1973,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> > /* Supervisor Protection and Translation */
> > [CSR_SATP] = { "satp", smode, read_satp, write_satp },
> >
> > + /* Supervisor-Level High-Half CSRs (AIA) */
> > + [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
> > + [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph },
> > +
> > [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus },
> > [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg },
> > - [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg },
> > + [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg },
> > [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip },
> > [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip },
> > - [CSR_HIE] = { "hie", hmode, read_hie, write_hie },
> > + [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie },
> > [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren },
> > [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie },
> > [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval },
> > @@ -1646,7 +1994,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> >
> > [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus },
> > [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip },
> > - [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie },
> > + [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie },
> > [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec },
> > [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch },
> > [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc },
> > @@ -1657,6 +2005,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> > [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 },
> > [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst },
> >
> > + /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
> > + [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh },
> > + [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph },
> > + [CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh },
> > + [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph },
> > +
> > /* Physical Memory Protection */
> > [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg },
> > [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
> > diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> > index a7102220b6..7356d70be6 100644
> > --- a/target/riscv/machine.c
> > +++ b/target/riscv/machine.c
> > @@ -108,7 +108,7 @@ static const VMStateDescription vmstate_hyper = {
> > .fields = (VMStateField[]) {
> > VMSTATE_UINTTL(env.hstatus, RISCVCPU),
> > VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
> > - VMSTATE_UINTTL(env.hideleg, RISCVCPU),
> > + VMSTATE_UINT64(env.hideleg, RISCVCPU),
> > VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
> > VMSTATE_UINTTL(env.htval, RISCVCPU),
> > VMSTATE_UINTTL(env.htinst, RISCVCPU),
> > @@ -168,10 +168,10 @@ const VMStateDescription vmstate_riscv_cpu = {
> > VMSTATE_UINTTL(env.resetvec, RISCVCPU),
> > VMSTATE_UINTTL(env.mhartid, RISCVCPU),
> > VMSTATE_UINT64(env.mstatus, RISCVCPU),
> > - VMSTATE_UINTTL(env.mip, RISCVCPU),
> > - VMSTATE_UINT32(env.miclaim, RISCVCPU),
> > - VMSTATE_UINTTL(env.mie, RISCVCPU),
> > - VMSTATE_UINTTL(env.mideleg, RISCVCPU),
> > + VMSTATE_UINT64(env.mip, RISCVCPU),
> > + VMSTATE_UINT64(env.miclaim, RISCVCPU),
> > + VMSTATE_UINT64(env.mie, RISCVCPU),
> > + VMSTATE_UINT64(env.mideleg, RISCVCPU),
> > VMSTATE_UINTTL(env.satp, RISCVCPU),
> > VMSTATE_UINTTL(env.stval, RISCVCPU),
> > VMSTATE_UINTTL(env.medeleg, RISCVCPU),
> > --
> > 2.25.1
> >
> >
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v4 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
` (9 preceding siblings ...)
2021-10-26 6:42 ` [PATCH v4 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-11-04 4:49 ` Alistair Francis
2021-10-26 6:42 ` [PATCH v4 12/22] target/riscv: Implement AIA interrupt filtering CSRs Anup Patel
` (10 subsequent siblings)
21 siblings, 1 reply; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra, Bin Meng
The AIA hvictl and hviprioX CSRs allow hypervisor to control
interrupts visible at VS-level. This patch implements AIA hvictl
and hviprioX CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/csr.c | 126 +++++++++++++++++++++++++++++++++++++++++
target/riscv/machine.c | 2 +
3 files changed, 129 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 718a95e864..21d9c536ef 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -196,6 +196,7 @@ struct CPURISCVState {
uint64_t htimedelta;
/* Hypervisor controlled virtual interrupt priorities */
+ target_ulong hvictl;
uint8_t hviprio[64];
/* Virtual CSRs */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 3a7d89ac34..46d0cabbde 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -219,6 +219,15 @@ static RISCVException hmode32(CPURISCVState *env, int csrno)
}
+static int aia_hmode(CPURISCVState *env, int csrno)
+{
+ if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ return hmode(env, csrno);
+}
+
static int aia_hmode32(CPURISCVState *env, int csrno)
{
if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
@@ -1031,6 +1040,9 @@ static RISCVException rmw_sie64(CPURISCVState *env, int csrno,
uint64_t mask = env->mideleg & S_MODE_INTERRUPTS;
if (riscv_cpu_virt_enabled(env)) {
+ if (env->hvictl & HVICTL_VTI) {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask);
} else {
ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask);
@@ -1229,6 +1241,9 @@ static RISCVException rmw_sip64(CPURISCVState *env, int csrno,
uint64_t mask = env->mideleg & sip_writable_mask;
if (riscv_cpu_virt_enabled(env)) {
+ if (env->hvictl & HVICTL_VTI) {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
ret = rmw_vsip64(env, CSR_VSIE, ret_val, new_val, wr_mask);
} else {
ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask);
@@ -1615,6 +1630,110 @@ static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->hvictl;
+ return RISCV_EXCP_NONE;
+}
+
+static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->hvictl = val & HVICTL_VALID_MASK;
+ return RISCV_EXCP_NONE;
+}
+
+static int read_hvipriox(CPURISCVState *env, int first_index,
+ uint8_t *iprio, target_ulong *val)
+{
+ int i, irq, rdzero, num_irqs = 4 * (TARGET_LONG_BITS / 32);
+
+ /* First index has to be multiple of numbe of irqs per register */
+ if (first_index % num_irqs) {
+ return (riscv_cpu_virt_enabled(env)) ?
+ RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ /* Fill-up return value */
+ *val = 0;
+ for (i = 0; i < num_irqs; i++) {
+ if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
+ continue;
+ }
+ if (rdzero) {
+ continue;
+ }
+ *val |= ((target_ulong)iprio[irq]) << (i * 8);
+ }
+
+ return RISCV_EXCP_NONE;
+}
+
+static int write_hvipriox(CPURISCVState *env, int first_index,
+ uint8_t *iprio, target_ulong val)
+{
+ int i, irq, rdzero, num_irqs = 4 * (TARGET_LONG_BITS / 32);
+
+ /* First index has to be multiple of numbe of irqs per register */
+ if (first_index % num_irqs) {
+ return (riscv_cpu_virt_enabled(env)) ?
+ RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ /* Fill-up priority arrary */
+ for (i = 0; i < num_irqs; i++) {
+ if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
+ continue;
+ }
+ if (rdzero) {
+ iprio[irq] = 0;
+ } else {
+ iprio[irq] = (val >> (i * 8)) & 0xff;
+ }
+ }
+
+ return RISCV_EXCP_NONE;
+}
+
+static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ return read_hvipriox(env, 0, env->hviprio, val);
+}
+
+static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val)
+{
+ return write_hvipriox(env, 0, env->hviprio, val);
+}
+
+static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ return read_hvipriox(env, 4, env->hviprio, val);
+}
+
+static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val)
+{
+ return write_hvipriox(env, 4, env->hviprio, val);
+}
+
+static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ return read_hvipriox(env, 8, env->hviprio, val);
+}
+
+static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val)
+{
+ return write_hvipriox(env, 8, env->hviprio, val);
+}
+
+static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ return read_hvipriox(env, 12, env->hviprio, val);
+}
+
+static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val)
+{
+ return write_hvipriox(env, 12, env->hviprio, val);
+}
+
/* Virtual CSR Registers */
static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
target_ulong *val)
@@ -2005,9 +2124,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 },
[CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst },
+ /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
+ [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, write_hvictl },
+ [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 },
+ [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 },
+
/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
[CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh },
[CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph },
+ [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, write_hviprio1h },
+ [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, write_hviprio2h },
[CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh },
[CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph },
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 7356d70be6..bc20960260 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -116,6 +116,8 @@ static const VMStateDescription vmstate_hyper = {
VMSTATE_UINTTL(env.hgeie, RISCVCPU),
VMSTATE_UINTTL(env.hgeip, RISCVCPU),
VMSTATE_UINT64(env.htimedelta, RISCVCPU),
+
+ VMSTATE_UINTTL(env.hvictl, RISCVCPU),
VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),
VMSTATE_UINT64(env.vsstatus, RISCVCPU),
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH v4 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs
2021-10-26 6:42 ` [PATCH v4 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs Anup Patel
@ 2021-11-04 4:49 ` Alistair Francis
2021-12-09 6:44 ` Anup Patel
0 siblings, 1 reply; 41+ messages in thread
From: Alistair Francis @ 2021-11-04 4:49 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt, Bin Meng
On Tue, Oct 26, 2021 at 5:39 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> The AIA hvictl and hviprioX CSRs allow hypervisor to control
> interrupts visible at VS-level. This patch implements AIA hvictl
> and hviprioX CSRs.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> target/riscv/cpu.h | 1 +
> target/riscv/csr.c | 126 +++++++++++++++++++++++++++++++++++++++++
> target/riscv/machine.c | 2 +
> 3 files changed, 129 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 718a95e864..21d9c536ef 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -196,6 +196,7 @@ struct CPURISCVState {
> uint64_t htimedelta;
>
> /* Hypervisor controlled virtual interrupt priorities */
> + target_ulong hvictl;
> uint8_t hviprio[64];
>
> /* Virtual CSRs */
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 3a7d89ac34..46d0cabbde 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -219,6 +219,15 @@ static RISCVException hmode32(CPURISCVState *env, int csrno)
>
> }
>
> +static int aia_hmode(CPURISCVState *env, int csrno)
> +{
> + if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + return hmode(env, csrno);
> +}
> +
> static int aia_hmode32(CPURISCVState *env, int csrno)
> {
> if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
> @@ -1031,6 +1040,9 @@ static RISCVException rmw_sie64(CPURISCVState *env, int csrno,
> uint64_t mask = env->mideleg & S_MODE_INTERRUPTS;
>
> if (riscv_cpu_virt_enabled(env)) {
> + if (env->hvictl & HVICTL_VTI) {
> + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> + }
> ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask);
> } else {
> ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask);
> @@ -1229,6 +1241,9 @@ static RISCVException rmw_sip64(CPURISCVState *env, int csrno,
> uint64_t mask = env->mideleg & sip_writable_mask;
>
> if (riscv_cpu_virt_enabled(env)) {
> + if (env->hvictl & HVICTL_VTI) {
> + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> + }
> ret = rmw_vsip64(env, CSR_VSIE, ret_val, new_val, wr_mask);
> } else {
> ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask);
> @@ -1615,6 +1630,110 @@ static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> +static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + *val = env->hvictl;
> + return RISCV_EXCP_NONE;
> +}
> +
> +static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + env->hvictl = val & HVICTL_VALID_MASK;
> + return RISCV_EXCP_NONE;
> +}
> +
> +static int read_hvipriox(CPURISCVState *env, int first_index,
> + uint8_t *iprio, target_ulong *val)
> +{
> + int i, irq, rdzero, num_irqs = 4 * (TARGET_LONG_BITS / 32);
You should be checking the CPUs xlen instead of using the hardcoded
TARGET_LONG_BITS here.
Alistair
> +
> + /* First index has to be multiple of numbe of irqs per register */
> + if (first_index % num_irqs) {
> + return (riscv_cpu_virt_enabled(env)) ?
> + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + /* Fill-up return value */
> + *val = 0;
> + for (i = 0; i < num_irqs; i++) {
> + if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
> + continue;
> + }
> + if (rdzero) {
> + continue;
> + }
> + *val |= ((target_ulong)iprio[irq]) << (i * 8);
> + }
> +
> + return RISCV_EXCP_NONE;
> +}
> +
> +static int write_hvipriox(CPURISCVState *env, int first_index,
> + uint8_t *iprio, target_ulong val)
> +{
> + int i, irq, rdzero, num_irqs = 4 * (TARGET_LONG_BITS / 32);
> +
> + /* First index has to be multiple of numbe of irqs per register */
> + if (first_index % num_irqs) {
> + return (riscv_cpu_virt_enabled(env)) ?
> + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + /* Fill-up priority arrary */
> + for (i = 0; i < num_irqs; i++) {
> + if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
> + continue;
> + }
> + if (rdzero) {
> + iprio[irq] = 0;
> + } else {
> + iprio[irq] = (val >> (i * 8)) & 0xff;
> + }
> + }
> +
> + return RISCV_EXCP_NONE;
> +}
> +
> +static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + return read_hvipriox(env, 0, env->hviprio, val);
> +}
> +
> +static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + return write_hvipriox(env, 0, env->hviprio, val);
> +}
> +
> +static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + return read_hvipriox(env, 4, env->hviprio, val);
> +}
> +
> +static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + return write_hvipriox(env, 4, env->hviprio, val);
> +}
> +
> +static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + return read_hvipriox(env, 8, env->hviprio, val);
> +}
> +
> +static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + return write_hvipriox(env, 8, env->hviprio, val);
> +}
> +
> +static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + return read_hvipriox(env, 12, env->hviprio, val);
> +}
> +
> +static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + return write_hvipriox(env, 12, env->hviprio, val);
> +}
> +
> /* Virtual CSR Registers */
> static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
> target_ulong *val)
> @@ -2005,9 +2124,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 },
> [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst },
>
> + /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
> + [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, write_hvictl },
> + [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 },
> + [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 },
> +
> /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
> [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh },
> [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph },
> + [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, write_hviprio1h },
> + [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, write_hviprio2h },
> [CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh },
> [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph },
>
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 7356d70be6..bc20960260 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -116,6 +116,8 @@ static const VMStateDescription vmstate_hyper = {
> VMSTATE_UINTTL(env.hgeie, RISCVCPU),
> VMSTATE_UINTTL(env.hgeip, RISCVCPU),
> VMSTATE_UINT64(env.htimedelta, RISCVCPU),
> +
> + VMSTATE_UINTTL(env.hvictl, RISCVCPU),
> VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),
>
> VMSTATE_UINT64(env.vsstatus, RISCVCPU),
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v4 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs
2021-11-04 4:49 ` Alistair Francis
@ 2021-12-09 6:44 ` Anup Patel
0 siblings, 0 replies; 41+ messages in thread
From: Anup Patel @ 2021-12-09 6:44 UTC (permalink / raw)
To: Alistair Francis
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt, Bin Meng
On Thu, Nov 4, 2021 at 10:19 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Tue, Oct 26, 2021 at 5:39 PM Anup Patel <anup.patel@wdc.com> wrote:
> >
> > The AIA hvictl and hviprioX CSRs allow hypervisor to control
> > interrupts visible at VS-level. This patch implements AIA hvictl
> > and hviprioX CSRs.
> >
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
> > target/riscv/cpu.h | 1 +
> > target/riscv/csr.c | 126 +++++++++++++++++++++++++++++++++++++++++
> > target/riscv/machine.c | 2 +
> > 3 files changed, 129 insertions(+)
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index 718a95e864..21d9c536ef 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -196,6 +196,7 @@ struct CPURISCVState {
> > uint64_t htimedelta;
> >
> > /* Hypervisor controlled virtual interrupt priorities */
> > + target_ulong hvictl;
> > uint8_t hviprio[64];
> >
> > /* Virtual CSRs */
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index 3a7d89ac34..46d0cabbde 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -219,6 +219,15 @@ static RISCVException hmode32(CPURISCVState *env, int csrno)
> >
> > }
> >
> > +static int aia_hmode(CPURISCVState *env, int csrno)
> > +{
> > + if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
> > + return RISCV_EXCP_ILLEGAL_INST;
> > + }
> > +
> > + return hmode(env, csrno);
> > +}
> > +
> > static int aia_hmode32(CPURISCVState *env, int csrno)
> > {
> > if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
> > @@ -1031,6 +1040,9 @@ static RISCVException rmw_sie64(CPURISCVState *env, int csrno,
> > uint64_t mask = env->mideleg & S_MODE_INTERRUPTS;
> >
> > if (riscv_cpu_virt_enabled(env)) {
> > + if (env->hvictl & HVICTL_VTI) {
> > + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> > + }
> > ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask);
> > } else {
> > ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask);
> > @@ -1229,6 +1241,9 @@ static RISCVException rmw_sip64(CPURISCVState *env, int csrno,
> > uint64_t mask = env->mideleg & sip_writable_mask;
> >
> > if (riscv_cpu_virt_enabled(env)) {
> > + if (env->hvictl & HVICTL_VTI) {
> > + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> > + }
> > ret = rmw_vsip64(env, CSR_VSIE, ret_val, new_val, wr_mask);
> > } else {
> > ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask);
> > @@ -1615,6 +1630,110 @@ static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
> > return RISCV_EXCP_NONE;
> > }
> >
> > +static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val)
> > +{
> > + *val = env->hvictl;
> > + return RISCV_EXCP_NONE;
> > +}
> > +
> > +static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val)
> > +{
> > + env->hvictl = val & HVICTL_VALID_MASK;
> > + return RISCV_EXCP_NONE;
> > +}
> > +
> > +static int read_hvipriox(CPURISCVState *env, int first_index,
> > + uint8_t *iprio, target_ulong *val)
> > +{
> > + int i, irq, rdzero, num_irqs = 4 * (TARGET_LONG_BITS / 32);
>
> You should be checking the CPUs xlen instead of using the hardcoded
> TARGET_LONG_BITS here.
Sure, I will update and use CPU xlen.
Regards,
Anup
>
> Alistair
>
> > +
> > + /* First index has to be multiple of numbe of irqs per register */
> > + if (first_index % num_irqs) {
> > + return (riscv_cpu_virt_enabled(env)) ?
> > + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
> > + }
> > +
> > + /* Fill-up return value */
> > + *val = 0;
> > + for (i = 0; i < num_irqs; i++) {
> > + if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
> > + continue;
> > + }
> > + if (rdzero) {
> > + continue;
> > + }
> > + *val |= ((target_ulong)iprio[irq]) << (i * 8);
> > + }
> > +
> > + return RISCV_EXCP_NONE;
> > +}
> > +
> > +static int write_hvipriox(CPURISCVState *env, int first_index,
> > + uint8_t *iprio, target_ulong val)
> > +{
> > + int i, irq, rdzero, num_irqs = 4 * (TARGET_LONG_BITS / 32);
> > +
> > + /* First index has to be multiple of numbe of irqs per register */
> > + if (first_index % num_irqs) {
> > + return (riscv_cpu_virt_enabled(env)) ?
> > + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
> > + }
> > +
> > + /* Fill-up priority arrary */
> > + for (i = 0; i < num_irqs; i++) {
> > + if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
> > + continue;
> > + }
> > + if (rdzero) {
> > + iprio[irq] = 0;
> > + } else {
> > + iprio[irq] = (val >> (i * 8)) & 0xff;
> > + }
> > + }
> > +
> > + return RISCV_EXCP_NONE;
> > +}
> > +
> > +static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val)
> > +{
> > + return read_hvipriox(env, 0, env->hviprio, val);
> > +}
> > +
> > +static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val)
> > +{
> > + return write_hvipriox(env, 0, env->hviprio, val);
> > +}
> > +
> > +static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val)
> > +{
> > + return read_hvipriox(env, 4, env->hviprio, val);
> > +}
> > +
> > +static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val)
> > +{
> > + return write_hvipriox(env, 4, env->hviprio, val);
> > +}
> > +
> > +static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val)
> > +{
> > + return read_hvipriox(env, 8, env->hviprio, val);
> > +}
> > +
> > +static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val)
> > +{
> > + return write_hvipriox(env, 8, env->hviprio, val);
> > +}
> > +
> > +static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val)
> > +{
> > + return read_hvipriox(env, 12, env->hviprio, val);
> > +}
> > +
> > +static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val)
> > +{
> > + return write_hvipriox(env, 12, env->hviprio, val);
> > +}
> > +
> > /* Virtual CSR Registers */
> > static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
> > target_ulong *val)
> > @@ -2005,9 +2124,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> > [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 },
> > [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst },
> >
> > + /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
> > + [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, write_hvictl },
> > + [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 },
> > + [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 },
> > +
> > /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
> > [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh },
> > [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph },
> > + [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, write_hviprio1h },
> > + [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, write_hviprio2h },
> > [CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh },
> > [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph },
> >
> > diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> > index 7356d70be6..bc20960260 100644
> > --- a/target/riscv/machine.c
> > +++ b/target/riscv/machine.c
> > @@ -116,6 +116,8 @@ static const VMStateDescription vmstate_hyper = {
> > VMSTATE_UINTTL(env.hgeie, RISCVCPU),
> > VMSTATE_UINTTL(env.hgeip, RISCVCPU),
> > VMSTATE_UINT64(env.htimedelta, RISCVCPU),
> > +
> > + VMSTATE_UINTTL(env.hvictl, RISCVCPU),
> > VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),
> >
> > VMSTATE_UINT64(env.vsstatus, RISCVCPU),
> > --
> > 2.25.1
> >
> >
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v4 12/22] target/riscv: Implement AIA interrupt filtering CSRs
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
` (10 preceding siblings ...)
2021-10-26 6:42 ` [PATCH v4 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-11-04 4:51 ` Alistair Francis
2021-10-26 6:42 ` [PATCH v4 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Anup Patel
` (9 subsequent siblings)
21 siblings, 1 reply; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra, Bin Meng
The AIA specificaiton adds interrupt filtering support for M-mode
and HS-mode. Using AIA interrupt filtering M-mode and H-mode can
take local interrupt 13 or above and selectively inject same local
interrupt to lower privilege modes.
At the moment, we don't have any local interrupts above 12 so we
add dummy implementation (i.e. read zero and ignore write) of AIA
interrupt filtering CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
target/riscv/csr.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 46d0cabbde..43ae444774 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -153,6 +153,15 @@ static RISCVException any32(CPURISCVState *env, int csrno)
}
+static int aia_any(CPURISCVState *env, int csrno)
+{
+ if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ return any(env, csrno);
+}
+
static int aia_any32(CPURISCVState *env, int csrno)
{
if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
@@ -515,6 +524,12 @@ static RISCVException read_zero(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException write_ignore(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mhartid(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -2071,9 +2086,15 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval },
[CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
+ /* Virtual Interrupts for Supervisor Level (AIA) */
+ [CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore },
+ [CSR_MVIP] = { "mvip", aia_any, read_zero, write_ignore },
+
/* Machine-Level High-Half CSRs (AIA) */
[CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
[CSR_MIEH] = { "mieh", aia_any32, NULL, NULL, rmw_mieh },
+ [CSR_MVIENH] = { "mvienh", aia_any32, read_zero, write_ignore },
+ [CSR_MVIPH] = { "mviph", aia_any32, read_zero, write_ignore },
[CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph },
/* Supervisor Trap Setup */
@@ -2125,12 +2146,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst },
/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
+ [CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore },
[CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, write_hvictl },
[CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 },
[CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 },
/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
[CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh },
+ [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, write_ignore },
[CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph },
[CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, write_hviprio1h },
[CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, write_hviprio2h },
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH v4 12/22] target/riscv: Implement AIA interrupt filtering CSRs
2021-10-26 6:42 ` [PATCH v4 12/22] target/riscv: Implement AIA interrupt filtering CSRs Anup Patel
@ 2021-11-04 4:51 ` Alistair Francis
0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2021-11-04 4:51 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt, Bin Meng
On Tue, Oct 26, 2021 at 5:44 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> The AIA specificaiton adds interrupt filtering support for M-mode
> and HS-mode. Using AIA interrupt filtering M-mode and H-mode can
> take local interrupt 13 or above and selectively inject same local
> interrupt to lower privilege modes.
>
> At the moment, we don't have any local interrupts above 12 so we
> add dummy implementation (i.e. read zero and ignore write) of AIA
> interrupt filtering CSRs.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 46d0cabbde..43ae444774 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -153,6 +153,15 @@ static RISCVException any32(CPURISCVState *env, int csrno)
>
> }
>
> +static int aia_any(CPURISCVState *env, int csrno)
> +{
> + if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + return any(env, csrno);
> +}
> +
> static int aia_any32(CPURISCVState *env, int csrno)
> {
> if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
> @@ -515,6 +524,12 @@ static RISCVException read_zero(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> +static RISCVException write_ignore(CPURISCVState *env, int csrno,
> + target_ulong val)
> +{
> + return RISCV_EXCP_NONE;
> +}
> +
> static RISCVException read_mhartid(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> @@ -2071,9 +2086,15 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval },
> [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
>
> + /* Virtual Interrupts for Supervisor Level (AIA) */
> + [CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore },
> + [CSR_MVIP] = { "mvip", aia_any, read_zero, write_ignore },
> +
> /* Machine-Level High-Half CSRs (AIA) */
> [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
> [CSR_MIEH] = { "mieh", aia_any32, NULL, NULL, rmw_mieh },
> + [CSR_MVIENH] = { "mvienh", aia_any32, read_zero, write_ignore },
> + [CSR_MVIPH] = { "mviph", aia_any32, read_zero, write_ignore },
> [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph },
>
> /* Supervisor Trap Setup */
> @@ -2125,12 +2146,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst },
>
> /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
> + [CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore },
> [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, write_hvictl },
> [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 },
> [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 },
>
> /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
> [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh },
> + [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, write_ignore },
> [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph },
> [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, write_hviprio1h },
> [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, write_hviprio2h },
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v4 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
` (11 preceding siblings ...)
2021-10-26 6:42 ` [PATCH v4 12/22] target/riscv: Implement AIA interrupt filtering CSRs Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 14/22] target/riscv: Implement AIA xiselect and xireg CSRs Anup Patel
` (8 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra, Bin Meng
The AIA specification introduces new [m|s|vs]topi CSRs for
reporting pending local IRQ number and associated IRQ priority.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
target/riscv/csr.c | 154 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 154 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 43ae444774..69e857d1e5 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -189,6 +189,15 @@ static int smode32(CPURISCVState *env, int csrno)
return smode(env, csrno);
}
+static int aia_smode(CPURISCVState *env, int csrno)
+{
+ if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ return smode(env, csrno);
+}
+
static int aia_smode32(CPURISCVState *env, int csrno)
{
if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
@@ -823,6 +832,28 @@ static RISCVException rmw_mieh(CPURISCVState *env, int csrno,
return ret;
}
+static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ int irq;
+ uint8_t iprio;
+
+ irq = riscv_cpu_mirq_pending(env);
+ if (irq <= 0 || irq > 63) {
+ *val = 0;
+ } else {
+ iprio = env->miprio[irq];
+ if (!iprio) {
+ if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_M) {
+ iprio = IPRIO_MMAXIPRIO;
+ }
+ }
+ *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT;
+ *val |= iprio;
+ }
+
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mtvec(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -1352,6 +1383,120 @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ int irq, ret;
+ target_ulong topei;
+ uint64_t vseip, vsgein;
+ uint32_t iid, iprio, hviid, hviprio, gein;
+#define VSTOPI_NUM_SRCS 5
+ uint32_t s, scount = 0, siid[VSTOPI_NUM_SRCS], siprio[VSTOPI_NUM_SRCS];
+
+ gein = get_field(env->hstatus, HSTATUS_VGEIN);
+ hviid = get_field(env->hvictl, HVICTL_IID);
+ hviprio = get_field(env->hvictl, HVICTL_IPRIO);
+
+ if (gein) {
+ vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
+ vseip = env->mie & (env->mip | vsgein) & MIP_VSEIP;
+ if (gein <= env->geilen && vseip) {
+ siid[scount] = IRQ_S_EXT;
+ siprio[scount] = IPRIO_MMAXIPRIO + 1;
+ if (env->aia_ireg_rmw_fn[PRV_S]) {
+ /*
+ * Call machine specific IMSIC register emulation for
+ * reading TOPEI.
+ */
+ ret = env->aia_ireg_rmw_fn[PRV_S](
+ env->aia_ireg_rmw_fn_arg[PRV_S],
+ AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, PRV_S, true, gein),
+ &topei, 0, 0);
+ if (!ret && topei) {
+ siprio[scount] = topei & IMSIC_TOPEI_IPRIO_MASK;
+ }
+ }
+ scount++;
+ }
+ } else {
+ if (hviid == IRQ_S_EXT && hviprio) {
+ siid[scount] = IRQ_S_EXT;
+ siprio[scount] = hviprio;
+ scount++;
+ }
+ }
+
+ if (env->hvictl & HVICTL_VTI) {
+ if (hviid != IRQ_S_EXT) {
+ siid[scount] = hviid;
+ siprio[scount] = hviprio;
+ scount++;
+ }
+ } else {
+ irq = riscv_cpu_vsirq_pending(env);
+ if (irq != IRQ_S_EXT && 0 < irq && irq <= 63) {
+ siid[scount] = irq;
+ siprio[scount] = env->hviprio[irq];
+ scount++;
+ }
+ }
+
+ iid = 0;
+ iprio = UINT_MAX;
+ for (s = 0; s < scount; s++) {
+ if (siprio[s] < iprio) {
+ iid = siid[s];
+ iprio = siprio[s];
+ }
+ }
+
+ if (iid) {
+ if (env->hvictl & HVICTL_IPRIOM) {
+ if (iprio > IPRIO_MMAXIPRIO) {
+ iprio = IPRIO_MMAXIPRIO;
+ }
+ if (!iprio) {
+ if (riscv_cpu_default_priority(iid) > IPRIO_DEFAULT_S) {
+ iprio = IPRIO_MMAXIPRIO;
+ }
+ }
+ } else {
+ iprio = 1;
+ }
+ } else {
+ iprio = 0;
+ }
+
+ *val = (iid & TOPI_IID_MASK) << TOPI_IID_SHIFT;
+ *val |= iprio;
+ return RISCV_EXCP_NONE;
+}
+
+static int read_stopi(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ int irq;
+ uint8_t iprio;
+
+ if (riscv_cpu_virt_enabled(env)) {
+ return read_vstopi(env, CSR_VSTOPI, val);
+ }
+
+ irq = riscv_cpu_sirq_pending(env);
+ if (irq <= 0 || irq > 63) {
+ *val = 0;
+ } else {
+ iprio = env->siprio[irq];
+ if (!iprio) {
+ if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_S) {
+ iprio = IPRIO_MMAXIPRIO;
+ }
+ }
+ *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT;
+ *val |= iprio;
+ }
+
+ return RISCV_EXCP_NONE;
+}
+
/* Hypervisor Extensions */
static RISCVException read_hstatus(CPURISCVState *env, int csrno,
target_ulong *val)
@@ -2086,6 +2231,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval },
[CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
+ /* Machine-Level Interrupts (AIA) */
+ [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi },
+
/* Virtual Interrupts for Supervisor Level (AIA) */
[CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore },
[CSR_MVIP] = { "mvip", aia_any, read_zero, write_ignore },
@@ -2113,6 +2261,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* Supervisor Protection and Translation */
[CSR_SATP] = { "satp", smode, read_satp, write_satp },
+ /* Supervisor-Level Interrupts (AIA) */
+ [CSR_STOPI] = { "stopi", aia_smode, read_stopi },
+
/* Supervisor-Level High-Half CSRs (AIA) */
[CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
[CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph },
@@ -2151,6 +2302,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 },
[CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 },
+ /* VS-Level Interrupts (H-extension with AIA) */
+ [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
+
/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
[CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh },
[CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, write_ignore },
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v4 14/22] target/riscv: Implement AIA xiselect and xireg CSRs
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
` (12 preceding siblings ...)
2021-10-26 6:42 ` [PATCH v4 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-11-04 4:56 ` Alistair Francis
2021-10-26 6:42 ` [PATCH v4 15/22] target/riscv: Implement AIA IMSIC interface CSRs Anup Patel
` (7 subsequent siblings)
21 siblings, 1 reply; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra, Bin Meng
The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
which allow indirect access to interrupt priority arrays and per-HART
IMSIC registers. This patch implements AIA xiselect and xireg CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
target/riscv/cpu.h | 7 ++
target/riscv/csr.c | 174 +++++++++++++++++++++++++++++++++++++++++
target/riscv/machine.c | 3 +
3 files changed, 184 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 21d9c536ef..bf688eb1ea 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -183,6 +183,10 @@ struct CPURISCVState {
uint8_t miprio[64];
uint8_t siprio[64];
+ /* AIA CSRs */
+ target_ulong miselect;
+ target_ulong siselect;
+
/* Hypervisor CSRs */
target_ulong hstatus;
target_ulong hedeleg;
@@ -212,6 +216,9 @@ struct CPURISCVState {
target_ulong vstval;
target_ulong vsatp;
+ /* AIA VS-mode CSRs */
+ target_ulong vsiselect;
+
target_ulong mtval2;
target_ulong mtinst;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 69e857d1e5..e72220fd0f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -854,6 +854,168 @@ static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val)
return RISCV_EXCP_NONE;
}
+static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
+{
+ if (!riscv_cpu_virt_enabled(env)) {
+ return csrno;
+ }
+
+ switch (csrno) {
+ case CSR_SISELECT:
+ return CSR_VSISELECT;
+ case CSR_SIREG:
+ return CSR_VSIREG;
+ default:
+ return csrno;
+ };
+}
+
+static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val,
+ target_ulong new_val, target_ulong wr_mask)
+{
+ target_ulong *iselect;
+
+ /* Translate CSR number for VS-mode */
+ csrno = aia_xlate_vs_csrno(env, csrno);
+
+ /* Find the iselect CSR based on CSR number */
+ switch (csrno) {
+ case CSR_MISELECT:
+ iselect = &env->miselect;
+ break;
+ case CSR_SISELECT:
+ iselect = &env->siselect;
+ break;
+ case CSR_VSISELECT:
+ iselect = &env->vsiselect;
+ break;
+ default:
+ return RISCV_EXCP_ILLEGAL_INST;
+ };
+
+ if (val) {
+ *val = *iselect;
+ }
+
+ wr_mask &= ISELECT_MASK;
+ if (wr_mask) {
+ *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask);
+ }
+
+ return RISCV_EXCP_NONE;
+}
+
+static int rmw_iprio(target_ulong iselect, uint8_t *iprio,
+ target_ulong *val, target_ulong new_val,
+ target_ulong wr_mask, int ext_irq_no)
+{
+ int i, firq, nirqs;
+ target_ulong old_val;
+
+ if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) {
+ return -EINVAL;
+ }
+#if TARGET_LONG_BITS == 64
+ if (iselect & 0x1) {
+ return -EINVAL;
+ }
+#endif
+
+ nirqs = 4 * (TARGET_LONG_BITS / 32);
+ firq = ((iselect - ISELECT_IPRIO0) / (TARGET_LONG_BITS / 32)) * (nirqs);
+
+ old_val = 0;
+ for (i = 0; i < nirqs; i++) {
+ old_val |= ((target_ulong)iprio[firq + i]) << (IPRIO_IRQ_BITS * i);
+ }
+
+ if (val) {
+ *val = old_val;
+ }
+
+ if (wr_mask) {
+ new_val = (old_val & ~wr_mask) | (new_val & wr_mask);
+ for (i = 0; i < nirqs; i++) {
+ /*
+ * M-level and S-level external IRQ priority always read-only
+ * zero. This means default priority order is always preferred
+ * for M-level and S-level external IRQs.
+ */
+ if ((firq + i) == ext_irq_no) {
+ continue;
+ }
+ iprio[firq + i] = (new_val >> (IPRIO_IRQ_BITS * i)) & 0xff;
+ }
+ }
+
+ return 0;
+}
+
+static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
+ target_ulong new_val, target_ulong wr_mask)
+{
+ bool virt;
+ uint8_t *iprio;
+ int ret = -EINVAL;
+ target_ulong priv, isel, vgein;
+
+ /* Translate CSR number for VS-mode */
+ csrno = aia_xlate_vs_csrno(env, csrno);
+
+ /* Decode register details from CSR number */
+ virt = false;
+ switch (csrno) {
+ case CSR_MIREG:
+ iprio = env->miprio;
+ isel = env->miselect;
+ priv = PRV_M;
+ break;
+ case CSR_SIREG:
+ iprio = env->siprio;
+ isel = env->siselect;
+ priv = PRV_S;
+ break;
+ case CSR_VSIREG:
+ iprio = env->hviprio;
+ isel = env->vsiselect;
+ priv = PRV_S;
+ virt = true;
+ break;
+ default:
+ goto done;
+ };
+
+ /* Find the selected guest interrupt file */
+ vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
+
+ if (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) {
+ /* Local interrupt priority registers not available for VS-mode */
+ if (!virt) {
+ ret = rmw_iprio(isel, iprio, val, new_val, wr_mask,
+ (priv == PRV_M) ? IRQ_M_EXT : IRQ_S_EXT);
+ }
+ } else if (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST) {
+ /* IMSIC registers only available when machine implements it. */
+ if (env->aia_ireg_rmw_fn[priv]) {
+ /* Selected guest interrupt file should not be zero */
+ if (virt && (!vgein || env->geilen < vgein)) {
+ goto done;
+ }
+ /* Call machine specific IMSIC register emulation */
+ ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
+ AIA_MAKE_IREG(isel, priv, virt, vgein),
+ val, new_val, wr_mask);
+ }
+ }
+
+done:
+ if (ret) {
+ return (riscv_cpu_virt_enabled(env) && virt) ?
+ RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
+ }
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mtvec(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -2231,6 +2393,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval },
[CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
+ /* Machine-Level Window to Indirectly Accessed Registers (AIA) */
+ [CSR_MISELECT] = { "miselect", aia_any, NULL, NULL, rmw_xiselect },
+ [CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg },
+
/* Machine-Level Interrupts (AIA) */
[CSR_MTOPI] = { "mtopi", aia_any, read_mtopi },
@@ -2261,6 +2427,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* Supervisor Protection and Translation */
[CSR_SATP] = { "satp", smode, read_satp, write_satp },
+ /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
+ [CSR_SISELECT] = { "siselect", aia_smode, NULL, NULL, rmw_xiselect },
+ [CSR_SIREG] = { "sireg", aia_smode, NULL, NULL, rmw_xireg },
+
/* Supervisor-Level Interrupts (AIA) */
[CSR_STOPI] = { "stopi", aia_smode, read_stopi },
@@ -2302,6 +2472,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 },
[CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 },
+ /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */
+ [CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, rmw_xiselect },
+ [CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg },
+
/* VS-Level Interrupts (H-extension with AIA) */
[CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index bc20960260..821e05d934 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -127,6 +127,7 @@ static const VMStateDescription vmstate_hyper = {
VMSTATE_UINTTL(env.vscause, RISCVCPU),
VMSTATE_UINTTL(env.vstval, RISCVCPU),
VMSTATE_UINTTL(env.vsatp, RISCVCPU),
+ VMSTATE_UINTTL(env.vsiselect, RISCVCPU),
VMSTATE_UINTTL(env.mtval2, RISCVCPU),
VMSTATE_UINTTL(env.mtinst, RISCVCPU),
@@ -184,6 +185,8 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.mepc, RISCVCPU),
VMSTATE_UINTTL(env.mcause, RISCVCPU),
VMSTATE_UINTTL(env.mtval, RISCVCPU),
+ VMSTATE_UINTTL(env.miselect, RISCVCPU),
+ VMSTATE_UINTTL(env.siselect, RISCVCPU),
VMSTATE_UINTTL(env.scounteren, RISCVCPU),
VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
VMSTATE_UINTTL(env.sscratch, RISCVCPU),
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH v4 14/22] target/riscv: Implement AIA xiselect and xireg CSRs
2021-10-26 6:42 ` [PATCH v4 14/22] target/riscv: Implement AIA xiselect and xireg CSRs Anup Patel
@ 2021-11-04 4:56 ` Alistair Francis
2021-12-09 11:15 ` Anup Patel
0 siblings, 1 reply; 41+ messages in thread
From: Alistair Francis @ 2021-11-04 4:56 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt, Bin Meng
On Tue, Oct 26, 2021 at 6:08 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
> which allow indirect access to interrupt priority arrays and per-HART
> IMSIC registers. This patch implements AIA xiselect and xireg CSRs.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> target/riscv/cpu.h | 7 ++
> target/riscv/csr.c | 174 +++++++++++++++++++++++++++++++++++++++++
> target/riscv/machine.c | 3 +
> 3 files changed, 184 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 21d9c536ef..bf688eb1ea 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -183,6 +183,10 @@ struct CPURISCVState {
> uint8_t miprio[64];
> uint8_t siprio[64];
>
> + /* AIA CSRs */
> + target_ulong miselect;
> + target_ulong siselect;
> +
> /* Hypervisor CSRs */
> target_ulong hstatus;
> target_ulong hedeleg;
> @@ -212,6 +216,9 @@ struct CPURISCVState {
> target_ulong vstval;
> target_ulong vsatp;
>
> + /* AIA VS-mode CSRs */
> + target_ulong vsiselect;
> +
> target_ulong mtval2;
> target_ulong mtinst;
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 69e857d1e5..e72220fd0f 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -854,6 +854,168 @@ static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val)
> return RISCV_EXCP_NONE;
> }
>
> +static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
> +{
> + if (!riscv_cpu_virt_enabled(env)) {
> + return csrno;
> + }
> +
> + switch (csrno) {
> + case CSR_SISELECT:
> + return CSR_VSISELECT;
> + case CSR_SIREG:
> + return CSR_VSIREG;
> + default:
> + return csrno;
> + };
> +}
> +
> +static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val,
> + target_ulong new_val, target_ulong wr_mask)
> +{
> + target_ulong *iselect;
> +
> + /* Translate CSR number for VS-mode */
> + csrno = aia_xlate_vs_csrno(env, csrno);
> +
> + /* Find the iselect CSR based on CSR number */
> + switch (csrno) {
> + case CSR_MISELECT:
> + iselect = &env->miselect;
> + break;
> + case CSR_SISELECT:
> + iselect = &env->siselect;
> + break;
> + case CSR_VSISELECT:
> + iselect = &env->vsiselect;
> + break;
> + default:
> + return RISCV_EXCP_ILLEGAL_INST;
> + };
> +
> + if (val) {
> + *val = *iselect;
> + }
> +
> + wr_mask &= ISELECT_MASK;
> + if (wr_mask) {
> + *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask);
> + }
> +
> + return RISCV_EXCP_NONE;
> +}
> +
> +static int rmw_iprio(target_ulong iselect, uint8_t *iprio,
> + target_ulong *val, target_ulong new_val,
> + target_ulong wr_mask, int ext_irq_no)
> +{
> + int i, firq, nirqs;
> + target_ulong old_val;
> +
> + if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) {
> + return -EINVAL;
> + }
> +#if TARGET_LONG_BITS == 64
> + if (iselect & 0x1) {
> + return -EINVAL;
> + }
> +#endif
> +
> + nirqs = 4 * (TARGET_LONG_BITS / 32);
> + firq = ((iselect - ISELECT_IPRIO0) / (TARGET_LONG_BITS / 32)) * (nirqs);
Don't use TARGET_LONG_BITS, this should be checked at runtime instead
Alistair
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v4 14/22] target/riscv: Implement AIA xiselect and xireg CSRs
2021-11-04 4:56 ` Alistair Francis
@ 2021-12-09 11:15 ` Anup Patel
0 siblings, 0 replies; 41+ messages in thread
From: Anup Patel @ 2021-12-09 11:15 UTC (permalink / raw)
To: Alistair Francis
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt, Bin Meng
On Thu, Nov 4, 2021 at 10:26 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Tue, Oct 26, 2021 at 6:08 PM Anup Patel <anup.patel@wdc.com> wrote:
> >
> > The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
> > which allow indirect access to interrupt priority arrays and per-HART
> > IMSIC registers. This patch implements AIA xiselect and xireg CSRs.
> >
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
> > target/riscv/cpu.h | 7 ++
> > target/riscv/csr.c | 174 +++++++++++++++++++++++++++++++++++++++++
> > target/riscv/machine.c | 3 +
> > 3 files changed, 184 insertions(+)
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index 21d9c536ef..bf688eb1ea 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -183,6 +183,10 @@ struct CPURISCVState {
> > uint8_t miprio[64];
> > uint8_t siprio[64];
> >
> > + /* AIA CSRs */
> > + target_ulong miselect;
> > + target_ulong siselect;
> > +
> > /* Hypervisor CSRs */
> > target_ulong hstatus;
> > target_ulong hedeleg;
> > @@ -212,6 +216,9 @@ struct CPURISCVState {
> > target_ulong vstval;
> > target_ulong vsatp;
> >
> > + /* AIA VS-mode CSRs */
> > + target_ulong vsiselect;
> > +
> > target_ulong mtval2;
> > target_ulong mtinst;
> >
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index 69e857d1e5..e72220fd0f 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -854,6 +854,168 @@ static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val)
> > return RISCV_EXCP_NONE;
> > }
> >
> > +static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
> > +{
> > + if (!riscv_cpu_virt_enabled(env)) {
> > + return csrno;
> > + }
> > +
> > + switch (csrno) {
> > + case CSR_SISELECT:
> > + return CSR_VSISELECT;
> > + case CSR_SIREG:
> > + return CSR_VSIREG;
> > + default:
> > + return csrno;
> > + };
> > +}
> > +
> > +static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val,
> > + target_ulong new_val, target_ulong wr_mask)
> > +{
> > + target_ulong *iselect;
> > +
> > + /* Translate CSR number for VS-mode */
> > + csrno = aia_xlate_vs_csrno(env, csrno);
> > +
> > + /* Find the iselect CSR based on CSR number */
> > + switch (csrno) {
> > + case CSR_MISELECT:
> > + iselect = &env->miselect;
> > + break;
> > + case CSR_SISELECT:
> > + iselect = &env->siselect;
> > + break;
> > + case CSR_VSISELECT:
> > + iselect = &env->vsiselect;
> > + break;
> > + default:
> > + return RISCV_EXCP_ILLEGAL_INST;
> > + };
> > +
> > + if (val) {
> > + *val = *iselect;
> > + }
> > +
> > + wr_mask &= ISELECT_MASK;
> > + if (wr_mask) {
> > + *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask);
> > + }
> > +
> > + return RISCV_EXCP_NONE;
> > +}
> > +
> > +static int rmw_iprio(target_ulong iselect, uint8_t *iprio,
> > + target_ulong *val, target_ulong new_val,
> > + target_ulong wr_mask, int ext_irq_no)
> > +{
> > + int i, firq, nirqs;
> > + target_ulong old_val;
> > +
> > + if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) {
> > + return -EINVAL;
> > + }
> > +#if TARGET_LONG_BITS == 64
> > + if (iselect & 0x1) {
> > + return -EINVAL;
> > + }
> > +#endif
> > +
> > + nirqs = 4 * (TARGET_LONG_BITS / 32);
> > + firq = ((iselect - ISELECT_IPRIO0) / (TARGET_LONG_BITS / 32)) * (nirqs);
>
> Don't use TARGET_LONG_BITS, this should be checked at runtime instead
Okay, I will update this.
Regards,
Anup
>
> Alistair
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v4 15/22] target/riscv: Implement AIA IMSIC interface CSRs
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
` (13 preceding siblings ...)
2021-10-26 6:42 ` [PATCH v4 14/22] target/riscv: Implement AIA xiselect and xireg CSRs Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 16/22] hw/riscv: virt: Use AIA INTC compatible string when available Anup Patel
` (6 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra, Bin Meng
The AIA specification defines IMSIC interface CSRs for easy access
to the per-HART IMSIC registers without using indirect xiselect and
xireg CSRs. This patch implements the AIA IMSIC interface CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
target/riscv/csr.c | 199 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 199 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e72220fd0f..19fe5b76e0 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -865,6 +865,16 @@ static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
return CSR_VSISELECT;
case CSR_SIREG:
return CSR_VSIREG;
+ case CSR_SSETEIPNUM:
+ return CSR_VSSETEIPNUM;
+ case CSR_SCLREIPNUM:
+ return CSR_VSCLREIPNUM;
+ case CSR_SSETEIENUM:
+ return CSR_VSSETEIENUM;
+ case CSR_SCLREIENUM:
+ return CSR_VSCLREIENUM;
+ case CSR_STOPEI:
+ return CSR_VSTOPEI;
default:
return csrno;
};
@@ -1016,6 +1026,174 @@ done:
return RISCV_EXCP_NONE;
}
+static int rmw_xsetclreinum(CPURISCVState *env, int csrno, target_ulong *val,
+ target_ulong new_val, target_ulong wr_mask)
+{
+ int ret = -EINVAL;
+ bool set, pend, virt;
+ target_ulong priv, isel, vgein, nval, wmask;
+
+ /* Translate CSR number for VS-mode */
+ csrno = aia_xlate_vs_csrno(env, csrno);
+
+ /* Decode register details from CSR number */
+ virt = set = pend = false;
+ switch (csrno) {
+ case CSR_MSETEIPNUM:
+ priv = PRV_M;
+ set = true;
+ break;
+ case CSR_MCLREIPNUM:
+ priv = PRV_M;
+ pend = true;
+ break;
+ case CSR_MSETEIENUM:
+ priv = PRV_M;
+ set = true;
+ break;
+ case CSR_MCLREIENUM:
+ priv = PRV_M;
+ break;
+ case CSR_SSETEIPNUM:
+ priv = PRV_S;
+ set = true;
+ pend = true;
+ break;
+ case CSR_SCLREIPNUM:
+ priv = PRV_S;
+ pend = true;
+ break;
+ case CSR_SSETEIENUM:
+ priv = PRV_S;
+ set = true;
+ break;
+ case CSR_SCLREIENUM:
+ priv = PRV_S;
+ break;
+ case CSR_VSSETEIPNUM:
+ priv = PRV_S;
+ virt = true;
+ set = true;
+ pend = true;
+ break;
+ case CSR_VSCLREIPNUM:
+ priv = PRV_S;
+ virt = true;
+ pend = true;
+ break;
+ case CSR_VSSETEIENUM:
+ priv = PRV_S;
+ virt = true;
+ set = true;
+ break;
+ case CSR_VSCLREIENUM:
+ priv = PRV_S;
+ virt = true;
+ break;
+ default:
+ goto done;
+ };
+
+ /* IMSIC CSRs only available when machine implements IMSIC. */
+ if (!env->aia_ireg_rmw_fn[priv]) {
+ goto done;
+ }
+
+ /* Find the selected guest interrupt file */
+ vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
+
+ /* Selected guest interrupt file should be valid */
+ if (virt && (!vgein || env->geilen < vgein)) {
+ goto done;
+ }
+
+ /* Set/Clear CSRs always read zero */
+ if (val) {
+ *val = 0;
+ }
+
+ if (wr_mask) {
+ /* Get interrupt number */
+ new_val &= wr_mask;
+
+ /* Find target interrupt pending/enable register */
+ isel = (new_val / TARGET_LONG_BITS);
+ isel *= (TARGET_LONG_BITS / IMSIC_EIPx_BITS);
+ isel += (pend) ? ISELECT_IMSIC_EIP0 : ISELECT_IMSIC_EIE0;
+
+ /* Find the interrupt bit to be set/clear */
+ wmask = ((target_ulong)1) << (new_val % TARGET_LONG_BITS);
+ nval = (set) ? wmask : 0;
+
+ /* Call machine specific IMSIC register emulation */
+ ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
+ AIA_MAKE_IREG(isel, priv, virt, vgein),
+ NULL, nval, wmask);
+ } else {
+ ret = 0;
+ }
+
+done:
+ if (ret) {
+ return (riscv_cpu_virt_enabled(env) && virt) ?
+ RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
+ }
+ return RISCV_EXCP_NONE;
+}
+
+static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val,
+ target_ulong new_val, target_ulong wr_mask)
+{
+ bool virt;
+ int ret = -EINVAL;
+ target_ulong priv, vgein;
+
+ /* Translate CSR number for VS-mode */
+ csrno = aia_xlate_vs_csrno(env, csrno);
+
+ /* Decode register details from CSR number */
+ virt = false;
+ switch (csrno) {
+ case CSR_MTOPEI:
+ priv = PRV_M;
+ break;
+ case CSR_STOPEI:
+ priv = PRV_S;
+ break;
+ case CSR_VSTOPEI:
+ priv = PRV_S;
+ virt = true;
+ break;
+ default:
+ goto done;
+ };
+
+ /* IMSIC CSRs only available when machine implements IMSIC. */
+ if (!env->aia_ireg_rmw_fn[priv]) {
+ goto done;
+ }
+
+ /* Find the selected guest interrupt file */
+ vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
+
+ /* Selected guest interrupt file should be valid */
+ if (virt && (!vgein || env->geilen < vgein)) {
+ goto done;
+ }
+
+ /* Call machine specific IMSIC register emulation for TOPEI */
+ ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
+ AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein),
+ val, new_val, wr_mask);
+
+done:
+ if (ret) {
+ return (riscv_cpu_virt_enabled(env) && virt) ?
+ RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
+ }
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mtvec(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -2400,6 +2578,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* Machine-Level Interrupts (AIA) */
[CSR_MTOPI] = { "mtopi", aia_any, read_mtopi },
+ /* Machine-Level IMSIC Interface (AIA) */
+ [CSR_MSETEIPNUM] = { "mseteipnum", aia_any, NULL, NULL, rmw_xsetclreinum },
+ [CSR_MCLREIPNUM] = { "mclreipnum", aia_any, NULL, NULL, rmw_xsetclreinum },
+ [CSR_MSETEIENUM] = { "mseteienum", aia_any, NULL, NULL, rmw_xsetclreinum },
+ [CSR_MCLREIENUM] = { "mclreienum", aia_any, NULL, NULL, rmw_xsetclreinum },
+ [CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei },
+
/* Virtual Interrupts for Supervisor Level (AIA) */
[CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore },
[CSR_MVIP] = { "mvip", aia_any, read_zero, write_ignore },
@@ -2434,6 +2619,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* Supervisor-Level Interrupts (AIA) */
[CSR_STOPI] = { "stopi", aia_smode, read_stopi },
+ /* Supervisor-Level IMSIC Interface (AIA) */
+ [CSR_SSETEIPNUM] = { "sseteipnum", aia_smode, NULL, NULL, rmw_xsetclreinum },
+ [CSR_SCLREIPNUM] = { "sclreipnum", aia_smode, NULL, NULL, rmw_xsetclreinum },
+ [CSR_SSETEIENUM] = { "sseteienum", aia_smode, NULL, NULL, rmw_xsetclreinum },
+ [CSR_SCLREIENUM] = { "sclreienum", aia_smode, NULL, NULL, rmw_xsetclreinum },
+ [CSR_STOPEI] = { "stopei", aia_smode, NULL, NULL, rmw_xtopei },
+
/* Supervisor-Level High-Half CSRs (AIA) */
[CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
[CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph },
@@ -2479,6 +2671,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* VS-Level Interrupts (H-extension with AIA) */
[CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
+ /* VS-Level IMSIC Interface (H-extension with AIA) */
+ [CSR_VSSETEIPNUM] = { "vsseteipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
+ [CSR_VSCLREIPNUM] = { "vsclreipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
+ [CSR_VSSETEIENUM] = { "vsseteienum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
+ [CSR_VSCLREIENUM] = { "vsclreienum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
+ [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei },
+
/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
[CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh },
[CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, write_ignore },
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v4 16/22] hw/riscv: virt: Use AIA INTC compatible string when available
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
` (14 preceding siblings ...)
2021-10-26 6:42 ` [PATCH v4 15/22] target/riscv: Implement AIA IMSIC interface CSRs Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 17/22] target/riscv: Allow users to force enable AIA CSRs in HART Anup Patel
` (5 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra,
Alistair Francis, Bin Meng
We should use the AIA INTC compatible string in the CPU INTC
DT nodes when the CPUs support AIA feature. This will allow
Linux INTC driver to use AIA local interrupt CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index b3b431c847..83f784bdee 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -211,8 +211,17 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
qemu_fdt_add_subnode(mc->fdt, intc_name);
qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle",
intc_phandles[cpu]);
- qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
- "riscv,cpu-intc");
+ if (riscv_feature(&s->soc[socket].harts[cpu].env,
+ RISCV_FEATURE_AIA)) {
+ static const char * const compat[2] = {
+ "riscv,cpu-intc-aia", "riscv,cpu-intc"
+ };
+ qemu_fdt_setprop_string_array(mc->fdt, name, "compatible",
+ (char **)&compat, ARRAY_SIZE(compat));
+ } else {
+ qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
+ "riscv,cpu-intc");
+ }
qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v4 17/22] target/riscv: Allow users to force enable AIA CSRs in HART
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
` (15 preceding siblings ...)
2021-10-26 6:42 ` [PATCH v4 16/22] hw/riscv: virt: Use AIA INTC compatible string when available Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 18/22] hw/intc: Add RISC-V AIA APLIC device emulation Anup Patel
` (4 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra,
Alistair Francis, Bin Meng
We add "x-aia" command-line option for RISC-V HART using which
allows users to force enable CPU AIA CSRs without changing the
interrupt controller available in RISC-V machine.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 5 +++++
target/riscv/cpu.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0006989c39..d88a2bd766 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -454,6 +454,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
}
+ if (cpu->cfg.aia) {
+ riscv_set_feature(env, RISCV_FEATURE_AIA);
+ }
+
set_resetvec(env, cpu->cfg.resetvec);
/* Validate that MISA_MXL is set properly. */
@@ -676,6 +680,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
+ DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
DEFINE_PROP_END_OF_LIST(),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bf688eb1ea..b7a9506544 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -340,6 +340,7 @@ struct RISCVCPU {
bool mmu;
bool pmp;
bool epmp;
+ bool aia;
uint64_t resetvec;
} cfg;
};
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v4 18/22] hw/intc: Add RISC-V AIA APLIC device emulation
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
` (16 preceding siblings ...)
2021-10-26 6:42 ` [PATCH v4 17/22] target/riscv: Allow users to force enable AIA CSRs in HART Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine Anup Patel
` (3 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra, Bin Meng
The RISC-V AIA (Advanced Interrupt Architecture) defines a new
interrupt controller for wired interrupts called APLIC (Advanced
Platform Level Interrupt Controller). The APLIC is capabable of
forwarding wired interupts to RISC-V HARTs directly or as MSIs
(Message Signaled Interupts).
This patch adds device emulation for RISC-V AIA APLIC.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
hw/intc/Kconfig | 3 +
hw/intc/meson.build | 1 +
hw/intc/riscv_aplic.c | 970 ++++++++++++++++++++++++++++++++++
include/hw/intc/riscv_aplic.h | 73 +++
4 files changed, 1047 insertions(+)
create mode 100644 hw/intc/riscv_aplic.c
create mode 100644 include/hw/intc/riscv_aplic.h
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 78aed93c45..1592623233 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -65,6 +65,9 @@ config LOONGSON_LIOINTC
config RISCV_ACLINT
bool
+config RISCV_APLIC
+ bool
+
config SIFIVE_PLIC
bool
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index c89d2ca180..77b068f673 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -47,6 +47,7 @@ specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
specific_ss.add(when: 'CONFIG_SH_INTC', if_true: files('sh_intc.c'))
specific_ss.add(when: 'CONFIG_RISCV_ACLINT', if_true: files('riscv_aclint.c'))
+specific_ss.add(when: 'CONFIG_RISCV_APLIC', if_true: files('riscv_aplic.c'))
specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XICS'],
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
new file mode 100644
index 0000000000..f4b8828dac
--- /dev/null
+++ b/hw/intc/riscv_aplic.c
@@ -0,0 +1,970 @@
+/*
+ * RISC-V APLIC (Advanced Platform Level Interrupt Controller)
+ *
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/error-report.h"
+#include "qemu/bswap.h"
+#include "exec/address-spaces.h"
+#include "hw/sysbus.h"
+#include "hw/pci/msi.h"
+#include "hw/boards.h"
+#include "hw/qdev-properties.h"
+#include "hw/intc/riscv_aplic.h"
+#include "hw/irq.h"
+#include "target/riscv/cpu.h"
+#include "sysemu/sysemu.h"
+#include "migration/vmstate.h"
+
+#define APLIC_MAX_IDC (1UL << 14)
+#define APLIC_MAX_SOURCE 1024
+#define APLIC_MIN_IPRIO_BITS 1
+#define APLIC_MAX_IPRIO_BITS 8
+#define APLIC_MAX_CHILDREN 1024
+
+#define APLIC_DOMAINCFG 0x0000
+#define APLIC_DOMAINCFG_IE (1 << 8)
+#define APLIC_DOMAINCFG_DM (1 << 2)
+#define APLIC_DOMAINCFG_BE (1 << 0)
+
+#define APLIC_SOURCECFG_BASE 0x0004
+#define APLIC_SOURCECFG_D (1 << 10)
+#define APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff
+#define APLIC_SOURCECFG_SM_MASK 0x00000007
+#define APLIC_SOURCECFG_SM_INACTIVE 0x0
+#define APLIC_SOURCECFG_SM_DETACH 0x1
+#define APLIC_SOURCECFG_SM_EDGE_RISE 0x4
+#define APLIC_SOURCECFG_SM_EDGE_FALL 0x5
+#define APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6
+#define APLIC_SOURCECFG_SM_LEVEL_LOW 0x7
+
+#define APLIC_MMSICFGADDR 0x1bc0
+#define APLIC_MMSICFGADDRH 0x1bc4
+#define APLIC_SMSICFGADDR 0x1bc8
+#define APLIC_SMSICFGADDRH 0x1bcc
+
+#define APLIC_xMSICFGADDRH_L (1UL << 31)
+#define APLIC_xMSICFGADDRH_HHXS_MASK 0x1f
+#define APLIC_xMSICFGADDRH_HHXS_SHIFT 24
+#define APLIC_xMSICFGADDRH_LHXS_MASK 0x7
+#define APLIC_xMSICFGADDRH_LHXS_SHIFT 20
+#define APLIC_xMSICFGADDRH_HHXW_MASK 0x7
+#define APLIC_xMSICFGADDRH_HHXW_SHIFT 16
+#define APLIC_xMSICFGADDRH_LHXW_MASK 0xf
+#define APLIC_xMSICFGADDRH_LHXW_SHIFT 12
+#define APLIC_xMSICFGADDRH_BAPPN_MASK 0xfff
+
+#define APLIC_xMSICFGADDR_PPN_SHIFT 12
+
+#define APLIC_xMSICFGADDR_PPN_HART(__lhxs) \
+ ((1UL << (__lhxs)) - 1)
+
+#define APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) \
+ ((1UL << (__lhxw)) - 1)
+#define APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs) \
+ ((__lhxs))
+#define APLIC_xMSICFGADDR_PPN_LHX(__lhxw, __lhxs) \
+ (APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) << \
+ APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs))
+
+#define APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) \
+ ((1UL << (__hhxw)) - 1)
+#define APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs) \
+ ((__hhxs) + APLIC_xMSICFGADDR_PPN_SHIFT)
+#define APLIC_xMSICFGADDR_PPN_HHX(__hhxw, __hhxs) \
+ (APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) << \
+ APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs))
+
+#define APLIC_xMSICFGADDRH_VALID_MASK \
+ (APLIC_xMSICFGADDRH_L | \
+ (APLIC_xMSICFGADDRH_HHXS_MASK << APLIC_xMSICFGADDRH_HHXS_SHIFT) | \
+ (APLIC_xMSICFGADDRH_LHXS_MASK << APLIC_xMSICFGADDRH_LHXS_SHIFT) | \
+ (APLIC_xMSICFGADDRH_HHXW_MASK << APLIC_xMSICFGADDRH_HHXW_SHIFT) | \
+ (APLIC_xMSICFGADDRH_LHXW_MASK << APLIC_xMSICFGADDRH_LHXW_SHIFT) | \
+ APLIC_xMSICFGADDRH_BAPPN_MASK)
+
+#define APLIC_SETIP_BASE 0x1c00
+#define APLIC_SETIPNUM 0x1cdc
+
+#define APLIC_CLRIP_BASE 0x1d00
+#define APLIC_CLRIPNUM 0x1ddc
+
+#define APLIC_SETIE_BASE 0x1e00
+#define APLIC_SETIENUM 0x1edc
+
+#define APLIC_CLRIE_BASE 0x1f00
+#define APLIC_CLRIENUM 0x1fdc
+
+#define APLIC_SETIPNUM_LE 0x2000
+#define APLIC_SETIPNUM_BE 0x2004
+
+#define APLIC_ISTATE_PENDING (1U << 0)
+#define APLIC_ISTATE_ENABLED (1U << 1)
+#define APLIC_ISTATE_ENPEND (APLIC_ISTATE_ENABLED | \
+ APLIC_ISTATE_PENDING)
+#define APLIC_ISTATE_INPUT (1U << 8)
+
+#define APLIC_GENMSI 0x3000
+
+#define APLIC_TARGET_BASE 0x3004
+#define APLIC_TARGET_HART_IDX_SHIFT 18
+#define APLIC_TARGET_HART_IDX_MASK 0x3fff
+#define APLIC_TARGET_GUEST_IDX_SHIFT 12
+#define APLIC_TARGET_GUEST_IDX_MASK 0x3f
+#define APLIC_TARGET_IPRIO_MASK 0xff
+#define APLIC_TARGET_EIID_MASK 0x7ff
+
+#define APLIC_IDC_BASE 0x4000
+#define APLIC_IDC_SIZE 32
+
+#define APLIC_IDC_IDELIVERY 0x00
+
+#define APLIC_IDC_IFORCE 0x04
+
+#define APLIC_IDC_ITHRESHOLD 0x08
+
+#define APLIC_IDC_TOPI 0x18
+#define APLIC_IDC_TOPI_ID_SHIFT 16
+#define APLIC_IDC_TOPI_ID_MASK 0x3ff
+#define APLIC_IDC_TOPI_PRIO_MASK 0xff
+
+#define APLIC_IDC_CLAIMI 0x1c
+
+static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic,
+ uint32_t word)
+{
+ uint32_t i, irq, ret = 0;
+
+ for (i = 0; i < 32; i++) {
+ irq = word * 32 + i;
+ if (!irq || aplic->num_irqs <= irq) {
+ continue;
+ }
+
+ ret |= ((aplic->state[irq] & APLIC_ISTATE_INPUT) ? 1 : 0) << i;
+ }
+
+ return ret;
+}
+
+static uint32_t riscv_aplic_read_pending_word(RISCVAPLICState *aplic,
+ uint32_t word)
+{
+ uint32_t i, irq, ret = 0;
+
+ for (i = 0; i < 32; i++) {
+ irq = word * 32 + i;
+ if (!irq || aplic->num_irqs <= irq) {
+ continue;
+ }
+
+ ret |= ((aplic->state[irq] & APLIC_ISTATE_PENDING) ? 1 : 0) << i;
+ }
+
+ return ret;
+}
+
+static void riscv_aplic_set_pending_raw(RISCVAPLICState *aplic,
+ uint32_t irq, bool pending)
+{
+ if (pending) {
+ aplic->state[irq] |= APLIC_ISTATE_PENDING;
+ } else {
+ aplic->state[irq] &= ~APLIC_ISTATE_PENDING;
+ }
+}
+
+static void riscv_aplic_set_pending(RISCVAPLICState *aplic,
+ uint32_t irq, bool pending)
+{
+ uint32_t sourcecfg, sm;
+
+ if ((irq <= 0) || (aplic->num_irqs <= irq)) {
+ return;
+ }
+
+ sourcecfg = aplic->sourcecfg[irq];
+ if (sourcecfg & APLIC_SOURCECFG_D) {
+ return;
+ }
+
+ sm = sourcecfg & APLIC_SOURCECFG_SM_MASK;
+ if ((sm == APLIC_SOURCECFG_SM_INACTIVE) ||
+ (!aplic->msimode && ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) ||
+ (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)))) {
+ return;
+ }
+
+ riscv_aplic_set_pending_raw(aplic, irq, pending);
+}
+
+static void riscv_aplic_set_pending_word(RISCVAPLICState *aplic,
+ uint32_t word, uint32_t value,
+ bool pending)
+{
+ uint32_t i, irq;
+
+ for (i = 0; i < 32; i++) {
+ irq = word * 32 + i;
+ if (!irq || aplic->num_irqs <= irq) {
+ continue;
+ }
+
+ if (value & (1U << i)) {
+ riscv_aplic_set_pending(aplic, irq, pending);
+ }
+ }
+}
+
+static uint32_t riscv_aplic_read_enabled_word(RISCVAPLICState *aplic,
+ int word)
+{
+ uint32_t i, irq, ret = 0;
+
+ for (i = 0; i < 32; i++) {
+ irq = word * 32 + i;
+ if (!irq || aplic->num_irqs <= irq) {
+ continue;
+ }
+
+ ret |= ((aplic->state[irq] & APLIC_ISTATE_ENABLED) ? 1 : 0) << i;
+ }
+
+ return ret;
+}
+
+static void riscv_aplic_set_enabled_raw(RISCVAPLICState *aplic,
+ uint32_t irq, bool enabled)
+{
+ if (enabled) {
+ aplic->state[irq] |= APLIC_ISTATE_ENABLED;
+ } else {
+ aplic->state[irq] &= ~APLIC_ISTATE_ENABLED;
+ }
+}
+
+static void riscv_aplic_set_enabled(RISCVAPLICState *aplic,
+ uint32_t irq, bool enabled)
+{
+ uint32_t sourcecfg, sm;
+
+ if ((irq <= 0) || (aplic->num_irqs <= irq)) {
+ return;
+ }
+
+ sourcecfg = aplic->sourcecfg[irq];
+ if (sourcecfg & APLIC_SOURCECFG_D) {
+ return;
+ }
+
+ sm = sourcecfg & APLIC_SOURCECFG_SM_MASK;
+ if (sm == APLIC_SOURCECFG_SM_INACTIVE) {
+ return;
+ }
+
+ riscv_aplic_set_enabled_raw(aplic, irq, enabled);
+}
+
+static void riscv_aplic_set_enabled_word(RISCVAPLICState *aplic,
+ uint32_t word, uint32_t value,
+ bool enabled)
+{
+ uint32_t i, irq;
+
+ for (i = 0; i < 32; i++) {
+ irq = word * 32 + i;
+ if (!irq || aplic->num_irqs <= irq) {
+ continue;
+ }
+
+ if (value & (1U << i)) {
+ riscv_aplic_set_enabled(aplic, irq, enabled);
+ }
+ }
+}
+
+static void riscv_aplic_msi_send(RISCVAPLICState *aplic,
+ uint32_t hart_idx, uint32_t guest_idx,
+ uint32_t eiid)
+{
+ uint64_t addr;
+ MemTxResult result;
+ RISCVAPLICState *aplic_m;
+ uint32_t lhxs, lhxw, hhxs, hhxw, group_idx, msicfgaddr, msicfgaddrH;
+
+ aplic_m = aplic;
+ while (aplic_m && !aplic_m->mmode) {
+ aplic_m = aplic_m->parent;
+ }
+ if (!aplic_m) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: m-level APLIC not found\n",
+ __func__);
+ return;
+ }
+
+ if (aplic->mmode) {
+ msicfgaddr = aplic_m->mmsicfgaddr;
+ msicfgaddrH = aplic_m->mmsicfgaddrH;
+ } else {
+ msicfgaddr = aplic_m->smsicfgaddr;
+ msicfgaddrH = aplic_m->smsicfgaddrH;
+ }
+
+ lhxs = (msicfgaddrH >> APLIC_xMSICFGADDRH_LHXS_SHIFT) &
+ APLIC_xMSICFGADDRH_LHXS_MASK;
+ lhxw = (msicfgaddrH >> APLIC_xMSICFGADDRH_LHXW_SHIFT) &
+ APLIC_xMSICFGADDRH_LHXW_MASK;
+ hhxs = (msicfgaddrH >> APLIC_xMSICFGADDRH_HHXS_SHIFT) &
+ APLIC_xMSICFGADDRH_HHXS_MASK;
+ hhxw = (msicfgaddrH >> APLIC_xMSICFGADDRH_HHXW_SHIFT) &
+ APLIC_xMSICFGADDRH_HHXW_MASK;
+
+ group_idx = hart_idx >> lhxw;
+ hart_idx &= APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw);
+
+ addr = msicfgaddr;
+ addr |= ((uint64_t)(msicfgaddrH & APLIC_xMSICFGADDRH_BAPPN_MASK)) << 32;
+ addr |= ((uint64_t)(group_idx & APLIC_xMSICFGADDR_PPN_HHX_MASK(hhxw))) <<
+ APLIC_xMSICFGADDR_PPN_HHX_SHIFT(hhxs);
+ addr |= ((uint64_t)(hart_idx & APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw))) <<
+ APLIC_xMSICFGADDR_PPN_LHX_SHIFT(lhxs);
+ addr |= (uint64_t)(guest_idx & APLIC_xMSICFGADDR_PPN_HART(lhxs));
+ addr <<= APLIC_xMSICFGADDR_PPN_SHIFT;
+
+ address_space_stl_le(&address_space_memory, addr,
+ eiid, MEMTXATTRS_UNSPECIFIED, &result);
+ if (result != MEMTX_OK) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: MSI write failed for "
+ "hart_index=%d guest_index=%d eiid=%d\n",
+ __func__, hart_idx, guest_idx, eiid);
+ }
+}
+
+static void riscv_aplic_msi_irq_update(RISCVAPLICState *aplic, uint32_t irq)
+{
+ uint32_t hart_idx, guest_idx, eiid;
+
+ if (!aplic->msimode || (aplic->num_irqs <= irq) ||
+ !(aplic->domaincfg & APLIC_DOMAINCFG_IE)) {
+ return;
+ }
+
+ if ((aplic->state[irq] & APLIC_ISTATE_ENPEND) != APLIC_ISTATE_ENPEND) {
+ return;
+ }
+
+ riscv_aplic_set_pending_raw(aplic, irq, false);
+
+ hart_idx = aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT;
+ hart_idx &= APLIC_TARGET_HART_IDX_MASK;
+ if (aplic->mmode) {
+ /* M-level APLIC ignores guest_index */
+ guest_idx = 0;
+ } else {
+ guest_idx = aplic->target[irq] >> APLIC_TARGET_GUEST_IDX_SHIFT;
+ guest_idx &= APLIC_TARGET_GUEST_IDX_MASK;
+ }
+ eiid = aplic->target[irq] & APLIC_TARGET_EIID_MASK;
+ riscv_aplic_msi_send(aplic, hart_idx, guest_idx, eiid);
+}
+
+static uint32_t riscv_aplic_idc_topi(RISCVAPLICState *aplic, uint32_t idc)
+{
+ uint32_t best_irq, best_iprio;
+ uint32_t irq, iprio, ihartidx, ithres;
+
+ if (aplic->num_harts <= idc) {
+ return 0;
+ }
+
+ ithres = aplic->ithreshold[idc];
+ if (!ithres) {
+ return 0;
+ }
+
+ best_irq = best_iprio = UINT32_MAX;
+ for (irq = 1; irq < aplic->num_irqs; irq++) {
+ if ((aplic->state[irq] & APLIC_ISTATE_ENPEND) !=
+ APLIC_ISTATE_ENPEND) {
+ continue;
+ }
+
+ ihartidx = aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT;
+ ihartidx &= APLIC_TARGET_HART_IDX_MASK;
+ if (ihartidx != idc) {
+ continue;
+ }
+
+ iprio = aplic->target[irq] & aplic->iprio_mask;
+ if (iprio >= ithres) {
+ continue;
+ }
+
+ if (iprio < best_iprio) {
+ best_irq = irq;
+ best_iprio = iprio;
+ }
+ }
+
+ if (best_irq < aplic->num_irqs && best_iprio <= aplic->iprio_mask) {
+ return (best_irq << APLIC_IDC_TOPI_ID_SHIFT) | best_iprio;
+ }
+
+ return 0;
+}
+
+static void riscv_aplic_idc_update(RISCVAPLICState *aplic, uint32_t idc)
+{
+ uint32_t topi;
+
+ if (aplic->msimode || aplic->num_harts <= idc) {
+ return;
+ }
+
+ topi = riscv_aplic_idc_topi(aplic, idc);
+ if ((aplic->domaincfg & APLIC_DOMAINCFG_IE) &&
+ aplic->idelivery[idc] &&
+ (aplic->iforce[idc] || topi)) {
+ qemu_irq_raise(aplic->external_irqs[idc]);
+ } else {
+ qemu_irq_lower(aplic->external_irqs[idc]);
+ }
+}
+
+static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState *aplic, uint32_t idc)
+{
+ uint32_t irq, state, sm, topi = riscv_aplic_idc_topi(aplic, idc);
+
+ if (!topi) {
+ aplic->iforce[idc] = 0;
+ return 0;
+ }
+
+ irq = (topi >> APLIC_IDC_TOPI_ID_SHIFT) & APLIC_IDC_TOPI_ID_MASK;
+ sm = aplic->sourcecfg[irq] & APLIC_SOURCECFG_SM_MASK;
+ state = aplic->state[irq];
+ riscv_aplic_set_pending_raw(aplic, irq, false);
+ if ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) &&
+ (state & APLIC_ISTATE_INPUT)) {
+ riscv_aplic_set_pending_raw(aplic, irq, true);
+ } else if ((sm == APLIC_SOURCECFG_SM_LEVEL_LOW) &&
+ !(state & APLIC_ISTATE_INPUT)) {
+ riscv_aplic_set_pending_raw(aplic, irq, true);
+ }
+ riscv_aplic_idc_update(aplic, idc);
+
+ return topi;
+}
+
+static void riscv_aplic_request(void *opaque, int irq, int level)
+{
+ bool update = false;
+ RISCVAPLICState *aplic = opaque;
+ uint32_t sourcecfg, childidx, state, idc;
+
+ assert((0 < irq) && (irq < aplic->num_irqs));
+
+ sourcecfg = aplic->sourcecfg[irq];
+ if (sourcecfg & APLIC_SOURCECFG_D) {
+ childidx = sourcecfg & APLIC_SOURCECFG_CHILDIDX_MASK;
+ if (childidx < aplic->num_children) {
+ riscv_aplic_request(aplic->children[childidx], irq, level);
+ }
+ return;
+ }
+
+ state = aplic->state[irq];
+ switch (sourcecfg & APLIC_SOURCECFG_SM_MASK) {
+ case APLIC_SOURCECFG_SM_EDGE_RISE:
+ if ((level > 0) && !(state & APLIC_ISTATE_INPUT) &&
+ !(state & APLIC_ISTATE_PENDING)) {
+ riscv_aplic_set_pending_raw(aplic, irq, true);
+ update = true;
+ }
+ break;
+ case APLIC_SOURCECFG_SM_EDGE_FALL:
+ if ((level <= 0) && (state & APLIC_ISTATE_INPUT) &&
+ !(state & APLIC_ISTATE_PENDING)) {
+ riscv_aplic_set_pending_raw(aplic, irq, true);
+ update = true;
+ }
+ break;
+ case APLIC_SOURCECFG_SM_LEVEL_HIGH:
+ if ((level > 0) && !(state & APLIC_ISTATE_PENDING)) {
+ riscv_aplic_set_pending_raw(aplic, irq, true);
+ update = true;
+ }
+ break;
+ case APLIC_SOURCECFG_SM_LEVEL_LOW:
+ if ((level <= 0) && !(state & APLIC_ISTATE_PENDING)) {
+ riscv_aplic_set_pending_raw(aplic, irq, true);
+ update = true;
+ }
+ break;
+ default:
+ break;
+ }
+
+ if (level <= 0) {
+ aplic->state[irq] &= ~APLIC_ISTATE_INPUT;
+ } else {
+ aplic->state[irq] |= APLIC_ISTATE_INPUT;
+ }
+
+ if (update) {
+ if (aplic->msimode) {
+ riscv_aplic_msi_irq_update(aplic, irq);
+ } else {
+ idc = aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT;
+ idc &= APLIC_TARGET_HART_IDX_MASK;
+ riscv_aplic_idc_update(aplic, idc);
+ }
+ }
+}
+
+static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size)
+{
+ uint32_t irq, word, idc;
+ RISCVAPLICState *aplic = opaque;
+
+ /* Reads must be 4 byte words */
+ if ((addr & 0x3) != 0) {
+ goto err;
+ }
+
+ if (addr == APLIC_DOMAINCFG) {
+ return aplic->domaincfg | (aplic->msimode ? APLIC_DOMAINCFG_DM : 0);
+ } else if ((APLIC_SOURCECFG_BASE <= addr) &&
+ (addr < (APLIC_SOURCECFG_BASE + (aplic->num_irqs - 1) * 4))) {
+ irq = ((addr - APLIC_SOURCECFG_BASE) >> 2) + 1;
+ return aplic->sourcecfg[irq];
+ } else if (aplic->mmode && aplic->msimode &&
+ (addr == APLIC_MMSICFGADDR)) {
+ return aplic->mmsicfgaddr;
+ } else if (aplic->mmode && aplic->msimode &&
+ (addr == APLIC_MMSICFGADDRH)) {
+ return aplic->mmsicfgaddrH;
+ } else if (aplic->mmode && aplic->msimode &&
+ (addr == APLIC_SMSICFGADDR)) {
+ /* Registers SMSICFGADDR and SMSICFGADDRH are implemented only if:
+ * (a) the interrupt domain is at machine level
+ * (b) the domain???s harts implement supervisor mode
+ * (c) the domain has one or more child supervisor-level domains
+ * that support MSI delivery mode (domaincfg.DM is not read-
+ * only zero in at least one of the supervisor-level child
+ * domains).
+ */
+ return (aplic->num_children) ? aplic->smsicfgaddr : 0;
+ } else if (aplic->mmode && aplic->msimode &&
+ (addr == APLIC_SMSICFGADDRH)) {
+ return (aplic->num_children) ? aplic->smsicfgaddrH : 0;
+ } else if ((APLIC_SETIP_BASE <= addr) &&
+ (addr < (APLIC_SETIP_BASE + aplic->bitfield_words * 4))) {
+ word = (addr - APLIC_SETIP_BASE) >> 2;
+ return riscv_aplic_read_pending_word(aplic, word);
+ } else if (addr == APLIC_SETIPNUM) {
+ return 0;
+ } else if ((APLIC_CLRIP_BASE <= addr) &&
+ (addr < (APLIC_CLRIP_BASE + aplic->bitfield_words * 4))) {
+ word = (addr - APLIC_CLRIP_BASE) >> 2;
+ return riscv_aplic_read_input_word(aplic, word);
+ } else if (addr == APLIC_CLRIPNUM) {
+ return 0;
+ } else if ((APLIC_SETIE_BASE <= addr) &&
+ (addr < (APLIC_SETIE_BASE + aplic->bitfield_words * 4))) {
+ word = (addr - APLIC_SETIE_BASE) >> 2;
+ return riscv_aplic_read_enabled_word(aplic, word);
+ } else if (addr == APLIC_SETIENUM) {
+ return 0;
+ } else if ((APLIC_CLRIE_BASE <= addr) &&
+ (addr < (APLIC_CLRIE_BASE + aplic->bitfield_words * 4))) {
+ return 0;
+ } else if (addr == APLIC_CLRIENUM) {
+ return 0;
+ } else if (addr == APLIC_SETIPNUM_LE) {
+ return 0;
+ } else if (addr == APLIC_SETIPNUM_BE) {
+ return 0;
+ } else if (addr == APLIC_GENMSI) {
+ return (aplic->msimode) ? aplic->genmsi : 0;
+ } else if ((APLIC_TARGET_BASE <= addr) &&
+ (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) {
+ irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1;
+ return aplic->target[irq];
+ } else if (!aplic->msimode && (APLIC_IDC_BASE <= addr) &&
+ (addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE))) {
+ idc = (addr - APLIC_IDC_BASE) / APLIC_IDC_SIZE;
+ switch (addr - (APLIC_IDC_BASE + idc * APLIC_IDC_SIZE)) {
+ case APLIC_IDC_IDELIVERY:
+ return aplic->idelivery[idc];
+ case APLIC_IDC_IFORCE:
+ return aplic->iforce[idc];
+ case APLIC_IDC_ITHRESHOLD:
+ return aplic->ithreshold[idc];
+ case APLIC_IDC_TOPI:
+ return riscv_aplic_idc_topi(aplic, idc);
+ case APLIC_IDC_CLAIMI:
+ return riscv_aplic_idc_claimi(aplic, idc);
+ default:
+ goto err;
+ };
+ }
+
+err:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
+ return 0;
+}
+
+static void riscv_aplic_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ RISCVAPLICState *aplic = opaque;
+ uint32_t irq, word, idc = UINT32_MAX;
+
+ /* Writes must be 4 byte words */
+ if ((addr & 0x3) != 0) {
+ goto err;
+ }
+
+ if (addr == APLIC_DOMAINCFG) {
+ /* Only IE bit writeable at the moment */
+ value &= APLIC_DOMAINCFG_IE;
+ aplic->domaincfg = value;
+ } else if ((APLIC_SOURCECFG_BASE <= addr) &&
+ (addr < (APLIC_SOURCECFG_BASE + (aplic->num_irqs - 1) * 4))) {
+ irq = ((addr - APLIC_SOURCECFG_BASE) >> 2) + 1;
+ if (!aplic->num_children && (value & APLIC_SOURCECFG_D)) {
+ value = 0;
+ }
+ if (value & APLIC_SOURCECFG_D) {
+ value &= (APLIC_SOURCECFG_D | APLIC_SOURCECFG_CHILDIDX_MASK);
+ } else {
+ value &= (APLIC_SOURCECFG_D | APLIC_SOURCECFG_SM_MASK);
+ }
+ aplic->sourcecfg[irq] = value;
+ if ((aplic->sourcecfg[irq] & APLIC_SOURCECFG_D) ||
+ (aplic->sourcecfg[irq] == 0)) {
+ riscv_aplic_set_pending_raw(aplic, irq, false);
+ riscv_aplic_set_enabled_raw(aplic, irq, false);
+ }
+ } else if (aplic->mmode && aplic->msimode &&
+ (addr == APLIC_MMSICFGADDR)) {
+ if (!(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
+ aplic->mmsicfgaddr = value;
+ }
+ } else if (aplic->mmode && aplic->msimode &&
+ (addr == APLIC_MMSICFGADDRH)) {
+ if (!(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
+ aplic->mmsicfgaddrH = value & APLIC_xMSICFGADDRH_VALID_MASK;
+ }
+ } else if (aplic->mmode && aplic->msimode &&
+ (addr == APLIC_SMSICFGADDR)) {
+ /* Registers SMSICFGADDR and SMSICFGADDRH are implemented only if:
+ * (a) the interrupt domain is at machine level
+ * (b) the domain???s harts implement supervisor mode
+ * (c) the domain has one or more child supervisor-level domains
+ * that support MSI delivery mode (domaincfg.DM is not read-
+ * only zero in at least one of the supervisor-level child
+ * domains).
+ */
+ if (aplic->num_children &&
+ !(aplic->smsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
+ aplic->smsicfgaddr = value;
+ }
+ } else if (aplic->mmode && aplic->msimode &&
+ (addr == APLIC_SMSICFGADDRH)) {
+ if (aplic->num_children &&
+ !(aplic->smsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
+ aplic->smsicfgaddrH = value & APLIC_xMSICFGADDRH_VALID_MASK;
+ }
+ } else if ((APLIC_SETIP_BASE <= addr) &&
+ (addr < (APLIC_SETIP_BASE + aplic->bitfield_words * 4))) {
+ word = (addr - APLIC_SETIP_BASE) >> 2;
+ riscv_aplic_set_pending_word(aplic, word, value, true);
+ } else if (addr == APLIC_SETIPNUM) {
+ riscv_aplic_set_pending(aplic, value, true);
+ } else if ((APLIC_CLRIP_BASE <= addr) &&
+ (addr < (APLIC_CLRIP_BASE + aplic->bitfield_words * 4))) {
+ word = (addr - APLIC_CLRIP_BASE) >> 2;
+ riscv_aplic_set_pending_word(aplic, word, value, false);
+ } else if (addr == APLIC_CLRIPNUM) {
+ riscv_aplic_set_pending(aplic, value, false);
+ } else if ((APLIC_SETIE_BASE <= addr) &&
+ (addr < (APLIC_SETIE_BASE + aplic->bitfield_words * 4))) {
+ word = (addr - APLIC_SETIE_BASE) >> 2;
+ riscv_aplic_set_enabled_word(aplic, word, value, true);
+ } else if (addr == APLIC_SETIENUM) {
+ riscv_aplic_set_enabled(aplic, value, true);
+ } else if ((APLIC_CLRIE_BASE <= addr) &&
+ (addr < (APLIC_CLRIE_BASE + aplic->bitfield_words * 4))) {
+ word = (addr - APLIC_CLRIE_BASE) >> 2;
+ riscv_aplic_set_enabled_word(aplic, word, value, false);
+ } else if (addr == APLIC_CLRIENUM) {
+ riscv_aplic_set_enabled(aplic, value, false);
+ } else if (addr == APLIC_SETIPNUM_LE) {
+ riscv_aplic_set_pending(aplic, value, true);
+ } else if (addr == APLIC_SETIPNUM_BE) {
+ riscv_aplic_set_pending(aplic, bswap32(value), true);
+ } else if (addr == APLIC_GENMSI) {
+ if (aplic->msimode) {
+ aplic->genmsi = value & ~(APLIC_TARGET_GUEST_IDX_MASK <<
+ APLIC_TARGET_GUEST_IDX_SHIFT);
+ riscv_aplic_msi_send(aplic,
+ value >> APLIC_TARGET_HART_IDX_SHIFT,
+ 0,
+ value & APLIC_TARGET_EIID_MASK);
+ }
+ } else if ((APLIC_TARGET_BASE <= addr) &&
+ (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) {
+ irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1;
+ if (aplic->msimode) {
+ aplic->target[irq] = value;
+ } else {
+ aplic->target[irq] = (value & ~APLIC_TARGET_IPRIO_MASK) |
+ (value & aplic->iprio_mask);
+ }
+ } else if (!aplic->msimode && (APLIC_IDC_BASE <= addr) &&
+ (addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE))) {
+ idc = (addr - APLIC_IDC_BASE) / APLIC_IDC_SIZE;
+ switch (addr - (APLIC_IDC_BASE + idc * APLIC_IDC_SIZE)) {
+ case APLIC_IDC_IDELIVERY:
+ aplic->idelivery[idc] = value & 0x1;
+ break;
+ case APLIC_IDC_IFORCE:
+ aplic->iforce[idc] = value & 0x1;
+ break;
+ case APLIC_IDC_ITHRESHOLD:
+ aplic->ithreshold[idc] = value & aplic->iprio_mask;
+ break;
+ default:
+ goto err;
+ };
+ } else {
+ goto err;
+ }
+
+ if (aplic->msimode) {
+ for (irq = 1; irq < aplic->num_irqs; irq++) {
+ riscv_aplic_msi_irq_update(aplic, irq);
+ }
+ } else {
+ if (idc == UINT32_MAX) {
+ for (idc = 0; idc < aplic->num_harts; idc++) {
+ riscv_aplic_idc_update(aplic, idc);
+ }
+ } else {
+ riscv_aplic_idc_update(aplic, idc);
+ }
+ }
+
+ return;
+
+err:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
+}
+
+static const MemoryRegionOps riscv_aplic_ops = {
+ .read = riscv_aplic_read,
+ .write = riscv_aplic_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
+};
+
+static void riscv_aplic_realize(DeviceState *dev, Error **errp)
+{
+ uint32_t i;
+ RISCVAPLICState *aplic = RISCV_APLIC(dev);
+
+ aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
+ aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
+ aplic->state = g_new(uint32_t, aplic->num_irqs);
+ aplic->target = g_new0(uint32_t, aplic->num_irqs);
+ aplic->idelivery = g_new0(uint32_t, aplic->num_harts);
+ aplic->iforce = g_new0(uint32_t, aplic->num_harts);
+ aplic->ithreshold = g_new0(uint32_t, aplic->num_harts);
+
+ memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, aplic,
+ TYPE_RISCV_APLIC, aplic->aperture_size);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio);
+
+ /* Only root APLICs have hardware IRQ lines. All non-root APLICs
+ * have IRQ lines delegated by their parent APLIC.
+ */
+ if (!aplic->parent) {
+ qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
+ }
+
+ /* Create output IRQ lines for non-MSI mode */
+ if (!aplic->msimode) {
+ aplic->external_irqs = g_malloc(sizeof(qemu_irq) * aplic->num_harts);
+ qdev_init_gpio_out(dev, aplic->external_irqs, aplic->num_harts);
+
+ /* Claim the CPU interrupt to be triggered by this APLIC */
+ for (i = 0; i < aplic->num_harts; i++) {
+ RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(aplic->hartid_base + i));
+ if (riscv_cpu_claim_interrupts(cpu,
+ (aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
+ error_report("%s already claimed",
+ (aplic->mmode) ? "MEIP" : "SEIP");
+ exit(1);
+ }
+ }
+ }
+
+ msi_nonbroken = true;
+}
+
+static Property riscv_aplic_properties[] = {
+ DEFINE_PROP_UINT32("aperture-size", RISCVAPLICState, aperture_size, 0),
+ DEFINE_PROP_UINT32("hartid-base", RISCVAPLICState, hartid_base, 0),
+ DEFINE_PROP_UINT32("num-harts", RISCVAPLICState, num_harts, 0),
+ DEFINE_PROP_UINT32("iprio-mask", RISCVAPLICState, iprio_mask, 0),
+ DEFINE_PROP_UINT32("num-irqs", RISCVAPLICState, num_irqs, 0),
+ DEFINE_PROP_BOOL("msimode", RISCVAPLICState, msimode, 0),
+ DEFINE_PROP_BOOL("mmode", RISCVAPLICState, mmode, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static const VMStateDescription vmstate_riscv_aplic = {
+ .name = "riscv_aplic",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(domaincfg, RISCVAPLICState),
+ VMSTATE_UINT32(mmsicfgaddr, RISCVAPLICState),
+ VMSTATE_UINT32(mmsicfgaddrH, RISCVAPLICState),
+ VMSTATE_UINT32(smsicfgaddr, RISCVAPLICState),
+ VMSTATE_UINT32(smsicfgaddrH, RISCVAPLICState),
+ VMSTATE_UINT32(genmsi, RISCVAPLICState),
+ VMSTATE_VARRAY_UINT32(sourcecfg, RISCVAPLICState,
+ num_irqs, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(state, RISCVAPLICState,
+ num_irqs, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(target, RISCVAPLICState,
+ num_irqs, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(idelivery, RISCVAPLICState,
+ num_harts, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(iforce, RISCVAPLICState,
+ num_harts, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(ithreshold, RISCVAPLICState,
+ num_harts, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void riscv_aplic_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ device_class_set_props(dc, riscv_aplic_properties);
+ dc->realize = riscv_aplic_realize;
+ dc->vmsd = &vmstate_riscv_aplic;
+}
+
+static const TypeInfo riscv_aplic_info = {
+ .name = TYPE_RISCV_APLIC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(RISCVAPLICState),
+ .class_init = riscv_aplic_class_init,
+};
+
+static void riscv_aplic_register_types(void)
+{
+ type_register_static(&riscv_aplic_info);
+}
+
+type_init(riscv_aplic_register_types)
+
+/*
+ * Add a APLIC device to another APLIC device as child for
+ * interrupt delegation.
+ */
+void riscv_aplic_add_child(DeviceState *parent, DeviceState *child)
+{
+ RISCVAPLICState *caplic, *paplic;
+
+ assert(parent && child);
+ caplic = RISCV_APLIC(child);
+ paplic = RISCV_APLIC(parent);
+
+ assert(paplic->num_irqs == caplic->num_irqs);
+ assert(paplic->num_children <= QEMU_APLIC_MAX_CHILDREN);
+
+ caplic->parent = paplic;
+ paplic->children[paplic->num_children] = caplic;
+ paplic->num_children++;
+}
+
+/*
+ * Create APLIC device.
+ */
+DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
+ uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
+ uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent)
+{
+ DeviceState *dev = qdev_new(TYPE_RISCV_APLIC);
+ uint32_t i;
+
+ assert(num_harts < APLIC_MAX_IDC);
+ assert((APLIC_IDC_BASE + (num_harts * APLIC_IDC_SIZE)) <= size);
+ assert(num_sources < APLIC_MAX_SOURCE);
+ assert(APLIC_MIN_IPRIO_BITS <= iprio_bits);
+ assert(iprio_bits <= APLIC_MAX_IPRIO_BITS);
+
+ qdev_prop_set_uint32(dev, "aperture-size", size);
+ qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
+ qdev_prop_set_uint32(dev, "num-harts", num_harts);
+ qdev_prop_set_uint32(dev, "iprio-mask", ((1U << iprio_bits) - 1));
+ qdev_prop_set_uint32(dev, "num-irqs", num_sources + 1);
+ qdev_prop_set_bit(dev, "msimode", msimode);
+ qdev_prop_set_bit(dev, "mmode", mmode);
+
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+
+ if (parent) {
+ riscv_aplic_add_child(parent, dev);
+ }
+
+ if (!msimode) {
+ for (i = 0; i < num_harts; i++) {
+ CPUState *cpu = qemu_get_cpu(hartid_base + i);
+
+ qdev_connect_gpio_out_named(dev, NULL, i,
+ qdev_get_gpio_in(DEVICE(cpu),
+ (mmode) ? IRQ_M_EXT : IRQ_S_EXT));
+ }
+ }
+
+ return dev;
+}
diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h
new file mode 100644
index 0000000000..d96d7b38c1
--- /dev/null
+++ b/include/hw/intc/riscv_aplic.h
@@ -0,0 +1,73 @@
+/*
+ * RISC-V APLIC (Advanced Platform Level Interrupt Controller) interface
+ *
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_RISCV_APLIC_H
+#define HW_RISCV_APLIC_H
+
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+#define TYPE_RISCV_APLIC "riscv.aplic"
+
+typedef struct RISCVAPLICState RISCVAPLICState;
+DECLARE_INSTANCE_CHECKER(RISCVAPLICState, RISCV_APLIC, TYPE_RISCV_APLIC)
+
+struct RISCVAPLICState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ qemu_irq *external_irqs;
+
+ /*< public >*/
+ MemoryRegion mmio;
+ uint32_t bitfield_words;
+ uint32_t domaincfg;
+ uint32_t mmsicfgaddr;
+ uint32_t mmsicfgaddrH;
+ uint32_t smsicfgaddr;
+ uint32_t smsicfgaddrH;
+ uint32_t genmsi;
+ uint32_t *sourcecfg;
+ uint32_t *state;
+ uint32_t *target;
+ uint32_t *idelivery;
+ uint32_t *iforce;
+ uint32_t *ithreshold;
+
+ /* topology */
+#define QEMU_APLIC_MAX_CHILDREN 16
+ struct RISCVAPLICState *parent;
+ struct RISCVAPLICState *children[QEMU_APLIC_MAX_CHILDREN];
+ uint16_t num_children;
+
+ /* config */
+ uint32_t aperture_size;
+ uint32_t hartid_base;
+ uint32_t num_harts;
+ uint32_t iprio_mask;
+ uint32_t num_irqs;
+ bool msimode;
+ bool mmode;
+};
+
+void riscv_aplic_add_child(DeviceState *parent, DeviceState *child);
+
+DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
+ uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
+ uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent);
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v4 19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
` (17 preceding siblings ...)
2021-10-26 6:42 ` [PATCH v4 18/22] hw/intc: Add RISC-V AIA APLIC device emulation Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 20/22] hw/intc: Add RISC-V AIA IMSIC device emulation Anup Patel
` (2 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra, Bin Meng
We extend virt machine to emulate AIA APLIC devices only when
"aia=aplic" parameter is passed along with machine name in QEMU
command-line. When "aia=none" or not specified then we fallback
to original PLIC device emulation.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
hw/riscv/Kconfig | 1 +
hw/riscv/virt.c | 293 ++++++++++++++++++++++++++++++++--------
include/hw/riscv/virt.h | 26 +++-
3 files changed, 260 insertions(+), 60 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index d2d869aaad..c30bb7cb6c 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -42,6 +42,7 @@ config RISCV_VIRT
select PFLASH_CFI01
select SERIAL
select RISCV_ACLINT
+ select RISCV_APLIC
select SIFIVE_PLIC
select SIFIVE_TEST
select VIRTIO_MMIO
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 83f784bdee..4e21b485aa 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -33,6 +33,7 @@
#include "hw/riscv/boot.h"
#include "hw/riscv/numa.h"
#include "hw/intc/riscv_aclint.h"
+#include "hw/intc/riscv_aplic.h"
#include "hw/intc/sifive_plic.h"
#include "hw/misc/sifive_test.h"
#include "chardev/char.h"
@@ -51,6 +52,8 @@ static const MemMapEntry virt_memmap[] = {
[VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 },
[VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
[VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
+ [VIRT_APLIC_M] = { 0xc000000, 0x8000 },
+ [VIRT_APLIC_S] = { 0xd000000, 0x8000 },
[VIRT_UART0] = { 0x10000000, 0x100 },
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
[VIRT_FW_CFG] = { 0x10100000, 0x18 },
@@ -132,12 +135,13 @@ static void virt_flash_map(RISCVVirtState *s,
sysmem);
}
-static void create_pcie_irq_map(void *fdt, char *nodename,
- uint32_t plic_phandle)
+static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename,
+ uint32_t irqchip_phandle)
{
int pin, dev;
- uint32_t
- full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
+ uint32_t irq_map_stride = 0;
+ uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS *
+ FDT_MAX_INT_MAP_WIDTH] = {};
uint32_t *irq_map = full_irq_map;
/* This code creates a standard swizzle of interrupts such that
@@ -155,23 +159,31 @@ static void create_pcie_irq_map(void *fdt, char *nodename,
int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
int i = 0;
+ /* Fill PCI address cells */
irq_map[i] = cpu_to_be32(devfn << 8);
-
i += FDT_PCI_ADDR_CELLS;
- irq_map[i] = cpu_to_be32(pin + 1);
+ /* Fill PCI Interrupt cells */
+ irq_map[i] = cpu_to_be32(pin + 1);
i += FDT_PCI_INT_CELLS;
- irq_map[i++] = cpu_to_be32(plic_phandle);
- i += FDT_PLIC_ADDR_CELLS;
- irq_map[i] = cpu_to_be32(irq_nr);
-
- irq_map += FDT_INT_MAP_WIDTH;
+ /* Fill interrupt controller phandle and cells */
+ irq_map[i++] = cpu_to_be32(irqchip_phandle);
+ irq_map[i++] = cpu_to_be32(irq_nr);
+ if (s->aia_type != VIRT_AIA_TYPE_NONE) {
+ irq_map[i++] = cpu_to_be32(0x4);
+ }
+
+ if (!irq_map_stride) {
+ irq_map_stride = i;
+ }
+ irq_map += irq_map_stride;
}
}
- qemu_fdt_setprop(fdt, nodename, "interrupt-map",
- full_irq_map, sizeof(full_irq_map));
+ qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map,
+ GPEX_NUM_IRQS * GPEX_NUM_IRQS *
+ irq_map_stride * sizeof(uint32_t));
qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
0x1800, 0, 0, 0x7);
@@ -394,8 +406,6 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
qemu_fdt_add_subnode(mc->fdt, plic_name);
- qemu_fdt_setprop_cell(mc->fdt, plic_name,
- "#address-cells", FDT_PLIC_ADDR_CELLS);
qemu_fdt_setprop_cell(mc->fdt, plic_name,
"#interrupt-cells", FDT_PLIC_INT_CELLS);
qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible",
@@ -415,6 +425,76 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
g_free(plic_cells);
}
+static void create_fdt_socket_aia(RISCVVirtState *s,
+ const MemMapEntry *memmap, int socket,
+ uint32_t *phandle, uint32_t *intc_phandles,
+ uint32_t *aplic_phandles)
+{
+ int cpu;
+ char *aplic_name;
+ uint32_t *aplic_cells;
+ unsigned long aplic_addr;
+ MachineState *mc = MACHINE(s);
+ uint32_t aplic_m_phandle, aplic_s_phandle;
+
+ aplic_m_phandle = (*phandle)++;
+ aplic_s_phandle = (*phandle)++;
+ aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
+
+ /* M-level APLIC node */
+ for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
+ aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
+ aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
+ }
+ aplic_addr = memmap[VIRT_APLIC_M].base +
+ (memmap[VIRT_APLIC_M].size * socket);
+ aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
+ qemu_fdt_add_subnode(mc->fdt, aplic_name);
+ qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic");
+ qemu_fdt_setprop_cell(mc->fdt, aplic_name,
+ "#interrupt-cells", FDT_APLIC_INT_CELLS);
+ qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
+ aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
+ qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
+ 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size);
+ qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
+ VIRT_IRQCHIP_NUM_SOURCES);
+ qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children",
+ aplic_s_phandle);
+ qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate",
+ 0x1, VIRT_IRQCHIP_NUM_SOURCES, aplic_s_phandle);
+ riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
+ qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle);
+ g_free(aplic_name);
+
+ /* S-level APLIC node */
+ for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
+ aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
+ aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
+ }
+ aplic_addr = memmap[VIRT_APLIC_S].base +
+ (memmap[VIRT_APLIC_S].size * socket);
+ aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
+ qemu_fdt_add_subnode(mc->fdt, aplic_name);
+ qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic");
+ qemu_fdt_setprop_cell(mc->fdt, aplic_name,
+ "#interrupt-cells", FDT_APLIC_INT_CELLS);
+ qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
+ aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
+ qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
+ 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size);
+ qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
+ VIRT_IRQCHIP_NUM_SOURCES);
+ riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
+ qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
+ g_free(aplic_name);
+
+ g_free(aplic_cells);
+ aplic_phandles[socket] = aplic_s_phandle;
+}
+
static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
bool is_32_bit, uint32_t *phandle,
uint32_t *irq_mmio_phandle,
@@ -451,8 +531,13 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
create_fdt_socket_clint(s, memmap, socket, intc_phandles);
}
- create_fdt_socket_plic(s, memmap, socket, phandle,
- intc_phandles, xplic_phandles);
+ if (s->aia_type == VIRT_AIA_TYPE_NONE) {
+ create_fdt_socket_plic(s, memmap, socket, phandle,
+ intc_phandles, xplic_phandles);
+ } else {
+ create_fdt_socket_aia(s, memmap, socket, phandle,
+ intc_phandles, xplic_phandles);
+ }
g_free(intc_phandles);
g_free(clust_name);
@@ -493,7 +578,13 @@ static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
0x0, memmap[VIRT_VIRTIO].size);
qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
irq_virtio_phandle);
- qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", VIRTIO_IRQ + i);
+ if (s->aia_type == VIRT_AIA_TYPE_NONE) {
+ qemu_fdt_setprop_cell(mc->fdt, name, "interrupts",
+ VIRTIO_IRQ + i);
+ } else {
+ qemu_fdt_setprop_cells(mc->fdt, name, "interrupts",
+ VIRTIO_IRQ + i, 0x4);
+ }
g_free(name);
}
}
@@ -531,7 +622,7 @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
2, virt_high_pcie_memmap.base,
2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
- create_pcie_irq_map(mc->fdt, name, irq_pcie_phandle);
+ create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle);
g_free(name);
}
@@ -590,7 +681,11 @@ static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap,
0x0, memmap[VIRT_UART0].size);
qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400);
qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle);
- qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ);
+ if (s->aia_type == VIRT_AIA_TYPE_NONE) {
+ qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ);
+ } else {
+ qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4);
+ }
qemu_fdt_add_subnode(mc->fdt, "/chosen");
qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name);
@@ -611,7 +706,11 @@ static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap,
0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size);
qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
irq_mmio_phandle);
- qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ);
+ if (s->aia_type == VIRT_AIA_TYPE_NONE) {
+ qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ);
+ } else {
+ qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4);
+ }
g_free(name);
}
@@ -692,7 +791,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
hwaddr high_mmio_base,
hwaddr high_mmio_size,
hwaddr pio_base,
- DeviceState *plic)
+ DeviceState *irqchip)
{
DeviceState *dev;
MemoryRegion *ecam_alias, *ecam_reg;
@@ -726,7 +825,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
for (i = 0; i < GPEX_NUM_IRQS; i++) {
- irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
+ irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
@@ -775,18 +874,75 @@ static char *plic_hart_config_string(int hart_count)
return g_strjoinv(",", (char **)vals);
}
+static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket,
+ int base_hartid, int hart_count)
+{
+ DeviceState *ret;
+ char *plic_hart_config;
+
+ /* Per-socket PLIC hart topology configuration string */
+ plic_hart_config = plic_hart_config_string(hart_count);
+
+ /* Per-socket PLIC */
+ ret = sifive_plic_create(
+ memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size,
+ plic_hart_config, hart_count, base_hartid,
+ VIRT_IRQCHIP_NUM_SOURCES,
+ ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1),
+ VIRT_PLIC_PRIORITY_BASE,
+ VIRT_PLIC_PENDING_BASE,
+ VIRT_PLIC_ENABLE_BASE,
+ VIRT_PLIC_ENABLE_STRIDE,
+ VIRT_PLIC_CONTEXT_BASE,
+ VIRT_PLIC_CONTEXT_STRIDE,
+ memmap[VIRT_PLIC].size);
+
+ g_free(plic_hart_config);
+
+ return ret;
+}
+
+static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type,
+ const MemMapEntry *memmap, int socket,
+ int base_hartid, int hart_count)
+{
+ DeviceState *aplic_m;
+
+ /* Per-socket M-level APLIC */
+ aplic_m = riscv_aplic_create(
+ memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size,
+ memmap[VIRT_APLIC_M].size,
+ base_hartid, hart_count,
+ VIRT_IRQCHIP_NUM_SOURCES,
+ VIRT_IRQCHIP_NUM_PRIO_BITS,
+ false, true, NULL);
+
+ if (aplic_m) {
+ /* Per-socket S-level APLIC */
+ riscv_aplic_create(
+ memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size,
+ memmap[VIRT_APLIC_S].size,
+ base_hartid, hart_count,
+ VIRT_IRQCHIP_NUM_SOURCES,
+ VIRT_IRQCHIP_NUM_PRIO_BITS,
+ false, false, aplic_m);
+ }
+
+ return aplic_m;
+}
+
static void virt_machine_init(MachineState *machine)
{
const MemMapEntry *memmap = virt_memmap;
RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
- char *plic_hart_config, *soc_name;
+ char *soc_name;
target_ulong start_addr = memmap[VIRT_DRAM].base;
target_ulong firmware_end_addr, kernel_start_addr;
uint32_t fdt_load_addr;
uint64_t kernel_entry;
- DeviceState *mmio_plic, *virtio_plic, *pcie_plic;
+ DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip;
int i, base_hartid, hart_count;
/* Check socket count limit */
@@ -797,7 +953,7 @@ static void virt_machine_init(MachineState *machine)
}
/* Initialize sockets */
- mmio_plic = virtio_plic = pcie_plic = NULL;
+ mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL;
for (i = 0; i < riscv_socket_count(machine); i++) {
if (!riscv_socket_check_hartids(machine, i)) {
error_report("discontinuous hartids in socket%d", i);
@@ -847,36 +1003,27 @@ static void virt_machine_init(MachineState *machine)
base_hartid, hart_count, true);
}
- /* Per-socket PLIC hart topology configuration string */
- plic_hart_config = plic_hart_config_string(hart_count);
-
- /* Per-socket PLIC */
- s->plic[i] = sifive_plic_create(
- memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size,
- plic_hart_config, hart_count, base_hartid,
- VIRT_PLIC_NUM_SOURCES,
- VIRT_PLIC_NUM_PRIORITIES,
- VIRT_PLIC_PRIORITY_BASE,
- VIRT_PLIC_PENDING_BASE,
- VIRT_PLIC_ENABLE_BASE,
- VIRT_PLIC_ENABLE_STRIDE,
- VIRT_PLIC_CONTEXT_BASE,
- VIRT_PLIC_CONTEXT_STRIDE,
- memmap[VIRT_PLIC].size);
- g_free(plic_hart_config);
+ /* Per-socket interrupt controller */
+ if (s->aia_type == VIRT_AIA_TYPE_NONE) {
+ s->irqchip[i] = virt_create_plic(memmap, i,
+ base_hartid, hart_count);
+ } else {
+ s->irqchip[i] = virt_create_aia(s->aia_type, memmap, i,
+ base_hartid, hart_count);
+ }
- /* Try to use different PLIC instance based device type */
+ /* Try to use different IRQCHIP instance based device type */
if (i == 0) {
- mmio_plic = s->plic[i];
- virtio_plic = s->plic[i];
- pcie_plic = s->plic[i];
+ mmio_irqchip = s->irqchip[i];
+ virtio_irqchip = s->irqchip[i];
+ pcie_irqchip = s->irqchip[i];
}
if (i == 1) {
- virtio_plic = s->plic[i];
- pcie_plic = s->plic[i];
+ virtio_irqchip = s->irqchip[i];
+ pcie_irqchip = s->irqchip[i];
}
if (i == 2) {
- pcie_plic = s->plic[i];
+ pcie_irqchip = s->irqchip[i];
}
}
@@ -975,7 +1122,7 @@ static void virt_machine_init(MachineState *machine)
for (i = 0; i < VIRTIO_COUNT; i++) {
sysbus_create_simple("virtio-mmio",
memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
- qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i));
+ qdev_get_gpio_in(DEVICE(virtio_irqchip), VIRTIO_IRQ + i));
}
gpex_pcie_init(system_memory,
@@ -986,14 +1133,14 @@ static void virt_machine_init(MachineState *machine)
virt_high_pcie_memmap.base,
virt_high_pcie_memmap.size,
memmap[VIRT_PCIE_PIO].base,
- DEVICE(pcie_plic));
+ DEVICE(pcie_irqchip));
serial_mm_init(system_memory, memmap[VIRT_UART0].base,
- 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
+ 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193,
serial_hd(0), DEVICE_LITTLE_ENDIAN);
sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
- qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ));
+ qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ));
virt_flash_create(s);
@@ -1009,6 +1156,37 @@ static void virt_machine_instance_init(Object *obj)
{
}
+static char *virt_get_aia(Object *obj, Error **errp)
+{
+ RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
+ const char *val;
+
+ switch (s->aia_type) {
+ case VIRT_AIA_TYPE_APLIC:
+ val = "aplic";
+ break;
+ default:
+ val = "none";
+ break;
+ };
+
+ return g_strdup(val);
+}
+
+static void virt_set_aia(Object *obj, const char *val, Error **errp)
+{
+ RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
+
+ if (!strcmp(val, "none")) {
+ s->aia_type = VIRT_AIA_TYPE_NONE;
+ } else if (!strcmp(val, "aplic")) {
+ s->aia_type = VIRT_AIA_TYPE_APLIC;
+ } else {
+ error_setg(errp, "Invalid AIA interrupt controller type");
+ error_append_hint(errp, "Valid values are none, and aplic.\n");
+ }
+}
+
static bool virt_get_aclint(Object *obj, Error **errp)
{
MachineState *ms = MACHINE(obj);
@@ -1047,6 +1225,13 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
object_class_property_set_description(oc, "aclint",
"Set on/off to enable/disable "
"emulating ACLINT devices");
+
+ object_class_property_add_str(oc, "aia", virt_get_aia,
+ virt_set_aia);
+ object_class_property_set_description(oc, "aia",
+ "Set type of AIA interrupt "
+ "conttoller. Valid values are "
+ "none, and aplic.");
}
static const TypeInfo virt_machine_typeinfo = {
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index d9105c1886..a26ef4a295 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -32,18 +32,24 @@ typedef struct RISCVVirtState RISCVVirtState;
DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE,
TYPE_RISCV_VIRT_MACHINE)
+typedef enum RISCVVirtAIAType {
+ VIRT_AIA_TYPE_NONE=0,
+ VIRT_AIA_TYPE_APLIC,
+} RISCVVirtAIAType;
+
struct RISCVVirtState {
/*< private >*/
MachineState parent;
/*< public >*/
RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
- DeviceState *plic[VIRT_SOCKETS_MAX];
+ DeviceState *irqchip[VIRT_SOCKETS_MAX];
PFlashCFI01 *flash[2];
FWCfgState *fw_cfg;
int fdt_size;
bool have_aclint;
+ RISCVVirtAIAType aia_type;
};
enum {
@@ -54,6 +60,8 @@ enum {
VIRT_CLINT,
VIRT_ACLINT_SSWI,
VIRT_PLIC,
+ VIRT_APLIC_M,
+ VIRT_APLIC_S,
VIRT_UART0,
VIRT_VIRTIO,
VIRT_FW_CFG,
@@ -73,9 +81,10 @@ enum {
VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
};
+#define VIRT_IRQCHIP_NUM_SOURCES 127
+#define VIRT_IRQCHIP_NUM_PRIO_BITS 3
+
#define VIRT_PLIC_HART_CONFIG "MS"
-#define VIRT_PLIC_NUM_SOURCES 127
-#define VIRT_PLIC_NUM_PRIORITIES 7
#define VIRT_PLIC_PRIORITY_BASE 0x04
#define VIRT_PLIC_PENDING_BASE 0x1000
#define VIRT_PLIC_ENABLE_BASE 0x2000
@@ -87,9 +96,14 @@ enum {
#define FDT_PCI_ADDR_CELLS 3
#define FDT_PCI_INT_CELLS 1
-#define FDT_PLIC_ADDR_CELLS 0
#define FDT_PLIC_INT_CELLS 1
-#define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \
- FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS)
+#define FDT_APLIC_INT_CELLS 2
+#define FDT_MAX_INT_CELLS 2
+#define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
+ 1 + FDT_MAX_INT_CELLS)
+#define FDT_PLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
+ 1 + FDT_PLIC_INT_CELLS)
+#define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
+ 1 + FDT_APLIC_INT_CELLS)
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v4 20/22] hw/intc: Add RISC-V AIA IMSIC device emulation
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
` (18 preceding siblings ...)
2021-10-26 6:42 ` [PATCH v4 19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Anup Patel
2021-10-26 6:42 ` [PATCH v4 22/22] docs/system: riscv: Document AIA options for " Anup Patel
21 siblings, 0 replies; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra, Bin Meng
The RISC-V AIA (Advanced Interrupt Architecture) defines a new
interrupt controller for MSIs (message signal interrupts) called
IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC
is per-HART device and also suppport virtualizaiton of MSIs using
dedicated VS-level guest interrupt files.
This patch adds device emulation for RISC-V AIA IMSIC which
supports M-level, S-level, and VS-level MSIs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
hw/intc/Kconfig | 3 +
hw/intc/meson.build | 1 +
hw/intc/riscv_imsic.c | 443 ++++++++++++++++++++++++++++++++++
include/hw/intc/riscv_imsic.h | 68 ++++++
4 files changed, 515 insertions(+)
create mode 100644 hw/intc/riscv_imsic.c
create mode 100644 include/hw/intc/riscv_imsic.h
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 1592623233..0bb3166110 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -68,6 +68,9 @@ config RISCV_ACLINT
config RISCV_APLIC
bool
+config RISCV_IMSIC
+ bool
+
config SIFIVE_PLIC
bool
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 77b068f673..bcfd7758a9 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -48,6 +48,7 @@ specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
specific_ss.add(when: 'CONFIG_SH_INTC', if_true: files('sh_intc.c'))
specific_ss.add(when: 'CONFIG_RISCV_ACLINT', if_true: files('riscv_aclint.c'))
specific_ss.add(when: 'CONFIG_RISCV_APLIC', if_true: files('riscv_aplic.c'))
+specific_ss.add(when: 'CONFIG_RISCV_IMSIC', if_true: files('riscv_imsic.c'))
specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XICS'],
diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
new file mode 100644
index 0000000000..f33e35986b
--- /dev/null
+++ b/hw/intc/riscv_imsic.c
@@ -0,0 +1,443 @@
+/*
+ * RISC-V IMSIC (Incoming Message Signaled Interrupt Controller)
+ *
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/error-report.h"
+#include "qemu/bswap.h"
+#include "exec/address-spaces.h"
+#include "hw/sysbus.h"
+#include "hw/pci/msi.h"
+#include "hw/boards.h"
+#include "hw/qdev-properties.h"
+#include "hw/intc/riscv_imsic.h"
+#include "hw/irq.h"
+#include "target/riscv/cpu.h"
+#include "target/riscv/cpu_bits.h"
+#include "sysemu/sysemu.h"
+#include "migration/vmstate.h"
+
+#define IMSIC_MMIO_PAGE_LE 0x00
+#define IMSIC_MMIO_PAGE_BE 0x04
+
+#define IMSIC_MIN_ID ((IMSIC_EIPx_BITS * 2) - 1)
+#define IMSIC_MAX_ID (IMSIC_TOPEI_IID_MASK)
+
+#define IMSIC_EISTATE_PENDING (1U << 0)
+#define IMSIC_EISTATE_ENABLED (1U << 1)
+#define IMSIC_EISTATE_ENPEND (IMSIC_EISTATE_ENABLED | \
+ IMSIC_EISTATE_PENDING)
+
+static uint32_t riscv_imsic_topei(RISCVIMSICState *imsic, uint32_t page)
+{
+ uint32_t i, max_irq, base;
+
+ base = page * imsic->num_irqs;
+ max_irq = (imsic->num_irqs < imsic->eithreshold[page]) ?
+ imsic->num_irqs : imsic->eithreshold[page];
+ for (i = 1; i < max_irq; i++) {
+ if ((imsic->eistate[base + i] & IMSIC_EISTATE_ENPEND) ==
+ IMSIC_EISTATE_ENPEND) {
+ return (i << IMSIC_TOPEI_IID_SHIFT) | i;
+ }
+ }
+
+ return 0;
+}
+
+static void riscv_imsic_update(RISCVIMSICState *imsic, uint32_t page)
+{
+ if (imsic->eidelivery[page] && riscv_imsic_topei(imsic, page)) {
+ qemu_irq_raise(imsic->external_irqs[page]);
+ } else {
+ qemu_irq_lower(imsic->external_irqs[page]);
+ }
+}
+
+static int riscv_imsic_eidelivery_rmw(RISCVIMSICState *imsic, uint32_t page,
+ target_ulong *val,
+ target_ulong new_val,
+ target_ulong wr_mask)
+{
+ target_ulong old_val = imsic->eidelivery[page];
+
+ if (val) {
+ *val = old_val;
+ }
+
+ wr_mask &= 0x1;
+ imsic->eidelivery[page] = (old_val & ~wr_mask) | (new_val & wr_mask);
+
+ riscv_imsic_update(imsic, page);
+ return 0;
+}
+
+static int riscv_imsic_eithreshold_rmw(RISCVIMSICState *imsic, uint32_t page,
+ target_ulong *val,
+ target_ulong new_val,
+ target_ulong wr_mask)
+{
+ target_ulong old_val = imsic->eithreshold[page];
+
+ if (val) {
+ *val = old_val;
+ }
+
+ wr_mask &= IMSIC_MAX_ID;
+ imsic->eithreshold[page] = (old_val & ~wr_mask) | (new_val & wr_mask);
+
+ riscv_imsic_update(imsic, page);
+ return 0;
+}
+
+static int riscv_imsic_topei_rmw(RISCVIMSICState *imsic, uint32_t page,
+ target_ulong *val, target_ulong new_val,
+ target_ulong wr_mask)
+{
+ uint32_t base, topei = riscv_imsic_topei(imsic, page);
+
+ /* Read pending and enabled interrupt with highest priority */
+ if (val) {
+ *val = topei;
+ }
+
+ /* Writes ignore value and clear top pending interrupt */
+ if (topei && wr_mask) {
+ topei >>= IMSIC_TOPEI_IID_SHIFT;
+ base = page * imsic->num_irqs;
+ if (topei) {
+ imsic->eistate[base + topei] &= ~IMSIC_EISTATE_PENDING;
+ }
+
+ riscv_imsic_update(imsic, page);
+ }
+
+ return 0;
+}
+
+static int riscv_imsic_eix_rmw(RISCVIMSICState *imsic, uint32_t page,
+ uint32_t num, bool pend, target_ulong *val,
+ target_ulong new_val, target_ulong wr_mask)
+{
+ uint32_t i, base;
+ target_ulong mask;
+ uint32_t state = (pend) ? IMSIC_EISTATE_PENDING : IMSIC_EISTATE_ENABLED;
+
+#if TARGET_LONG_BITS == 64
+ if (num & 0x1) {
+ return -EINVAL;
+ }
+ num >>= 1;
+#endif
+
+ if (num >= (imsic->num_irqs / TARGET_LONG_BITS)) {
+ return -EINVAL;
+ }
+ base = (page * imsic->num_irqs) + (num * TARGET_LONG_BITS);
+
+ if (val) {
+ *val = 0;
+ for (i = 0; i < TARGET_LONG_BITS; i++) {
+ mask = (target_ulong)1 << i;
+ *val |= (imsic->eistate[base + i] & state) ? mask : 0;
+ }
+ }
+
+ for (i = 0; i < TARGET_LONG_BITS; i++) {
+ /* Bit0 of eip0 and eie0 are read-only zero */
+ if (!num && !i) {
+ continue;
+ }
+
+ mask = (target_ulong)1 << i;
+ if (wr_mask & mask) {
+ if (new_val & mask) {
+ imsic->eistate[base + i] |= state;
+ } else {
+ imsic->eistate[base + i] &= ~state;
+ }
+ }
+ }
+
+ riscv_imsic_update(imsic, page);
+ return 0;
+}
+
+static int riscv_imsic_rmw(void *arg, target_ulong reg, target_ulong *val,
+ target_ulong new_val, target_ulong wr_mask)
+{
+ RISCVIMSICState *imsic = arg;
+ uint32_t isel, priv, virt, vgein, page;
+
+ priv = AIA_IREG_PRIV(reg);
+ virt = AIA_IREG_VIRT(reg);
+ isel = AIA_IREG_ISEL(reg);
+ vgein = AIA_IREG_VGEIN(reg);
+
+ if (imsic->mmode) {
+ if (priv == PRV_M && !virt) {
+ page = 0;
+ } else {
+ goto err;
+ }
+ } else {
+ if (priv == PRV_S) {
+ if (virt) {
+ if (vgein && vgein < imsic->num_pages) {
+ page = vgein;
+ } else {
+ goto err;
+ }
+ } else {
+ page = 0;
+ }
+ } else {
+ goto err;
+ }
+ }
+
+ switch (isel) {
+ case ISELECT_IMSIC_EIDELIVERY:
+ return riscv_imsic_eidelivery_rmw(imsic, page, val,
+ new_val, wr_mask);
+ case ISELECT_IMSIC_EITHRESHOLD:
+ return riscv_imsic_eithreshold_rmw(imsic, page, val,
+ new_val, wr_mask);
+ case ISELECT_IMSIC_TOPEI:
+ return riscv_imsic_topei_rmw(imsic, page, val, new_val, wr_mask);
+ case ISELECT_IMSIC_EIP0 ... ISELECT_IMSIC_EIP63:
+ return riscv_imsic_eix_rmw(imsic, page, isel - ISELECT_IMSIC_EIP0,
+ true, val, new_val, wr_mask);
+ case ISELECT_IMSIC_EIE0 ... ISELECT_IMSIC_EIE63:
+ return riscv_imsic_eix_rmw(imsic, page, isel - ISELECT_IMSIC_EIE0,
+ false, val, new_val, wr_mask);
+ default:
+ break;
+ };
+
+err:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Invalid register priv=%d virt=%d isel=%d vgein=%d\n",
+ __func__, priv, virt, isel, vgein);
+ return -EINVAL;
+}
+
+static uint64_t riscv_imsic_read(void *opaque, hwaddr addr, unsigned size)
+{
+ RISCVIMSICState *imsic = opaque;
+
+ /* Reads must be 4 byte words */
+ if ((addr & 0x3) != 0) {
+ goto err;
+ }
+
+ /* Reads cannot be out of range */
+ if (addr > IMSIC_MMIO_SIZE(imsic->num_pages)) {
+ goto err;
+ }
+
+ return 0;
+
+err:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
+ return 0;
+}
+
+static void riscv_imsic_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ RISCVIMSICState *imsic = opaque;
+ uint32_t page;
+
+ /* Writes must be 4 byte words */
+ if ((addr & 0x3) != 0) {
+ goto err;
+ }
+
+ /* Writes cannot be out of range */
+ if (addr > IMSIC_MMIO_SIZE(imsic->num_pages)) {
+ goto err;
+ }
+
+ /* Writes only supported for MSI little-endian registers */
+ page = addr >> IMSIC_MMIO_PAGE_SHIFT;
+ if ((addr & (IMSIC_MMIO_PAGE_SZ - 1)) == IMSIC_MMIO_PAGE_LE) {
+ if (value && (value < imsic->num_irqs)) {
+ imsic->eistate[(page * imsic->num_irqs) + value] |=
+ IMSIC_EISTATE_PENDING;
+ }
+ }
+
+ /* Update CPU external interrupt status */
+ riscv_imsic_update(imsic, page);
+
+ return;
+
+err:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
+}
+
+static const MemoryRegionOps riscv_imsic_ops = {
+ .read = riscv_imsic_read,
+ .write = riscv_imsic_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
+};
+
+static void riscv_imsic_realize(DeviceState *dev, Error **errp)
+{
+ RISCVIMSICState *imsic = RISCV_IMSIC(dev);
+ RISCVCPU *rcpu = RISCV_CPU(qemu_get_cpu(imsic->hartid));
+ CPUState *cpu = qemu_get_cpu(imsic->hartid);
+ CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
+
+ imsic->num_eistate = imsic->num_pages * imsic->num_irqs;
+ imsic->eidelivery = g_new0(uint32_t, imsic->num_pages);
+ imsic->eithreshold = g_new0(uint32_t, imsic->num_pages);
+ imsic->eistate = g_new0(uint32_t, imsic->num_eistate);
+
+ memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops,
+ imsic, TYPE_RISCV_IMSIC,
+ IMSIC_MMIO_SIZE(imsic->num_pages));
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &imsic->mmio);
+
+ /* Claim the CPU interrupt to be triggered by this IMSIC */
+ if (riscv_cpu_claim_interrupts(rcpu,
+ (imsic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
+ error_report("%s already claimed",
+ (imsic->mmode) ? "MEIP" : "SEIP");
+ exit(1);
+ }
+
+ /* Create output IRQ lines */
+ imsic->external_irqs = g_malloc(sizeof(qemu_irq) * imsic->num_pages);
+ qdev_init_gpio_out(dev, imsic->external_irqs, imsic->num_pages);
+
+ /* Force select AIA feature and setup CSR read-modify-write callback */
+ if (env) {
+ riscv_set_feature(env, RISCV_FEATURE_AIA);
+ if (!imsic->mmode) {
+ riscv_cpu_set_geilen(env, imsic->num_pages - 1);
+ }
+ riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S,
+ riscv_imsic_rmw, imsic);
+ }
+
+ msi_nonbroken = true;
+}
+
+static Property riscv_imsic_properties[] = {
+ DEFINE_PROP_BOOL("mmode", RISCVIMSICState, mmode, 0),
+ DEFINE_PROP_UINT32("hartid", RISCVIMSICState, hartid, 0),
+ DEFINE_PROP_UINT32("num-pages", RISCVIMSICState, num_pages, 0),
+ DEFINE_PROP_UINT32("num-irqs", RISCVIMSICState, num_irqs, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static const VMStateDescription vmstate_riscv_imsic = {
+ .name = "riscv_imsic",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_VARRAY_UINT32(eidelivery, RISCVIMSICState,
+ num_pages, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(eithreshold, RISCVIMSICState,
+ num_pages, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(eistate, RISCVIMSICState,
+ num_eistate, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void riscv_imsic_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ device_class_set_props(dc, riscv_imsic_properties);
+ dc->realize = riscv_imsic_realize;
+ dc->vmsd = &vmstate_riscv_imsic;
+}
+
+static const TypeInfo riscv_imsic_info = {
+ .name = TYPE_RISCV_IMSIC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(RISCVIMSICState),
+ .class_init = riscv_imsic_class_init,
+};
+
+static void riscv_imsic_register_types(void)
+{
+ type_register_static(&riscv_imsic_info);
+}
+
+type_init(riscv_imsic_register_types)
+
+/*
+ * Create IMSIC device.
+ */
+DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode,
+ uint32_t num_pages, uint32_t num_ids)
+{
+ DeviceState *dev = qdev_new(TYPE_RISCV_IMSIC);
+ CPUState *cpu = qemu_get_cpu(hartid);
+ uint32_t i;
+
+ assert(!(addr & (IMSIC_MMIO_PAGE_SZ - 1)));
+ if (mmode) {
+ assert(num_pages == 1);
+ } else {
+ assert(num_pages >= 1 && num_pages <= (IRQ_LOCAL_GUEST_MAX + 1));
+ }
+ assert(IMSIC_MIN_ID <= num_ids);
+ assert(num_ids <= IMSIC_MAX_ID);
+ assert((num_ids & IMSIC_MIN_ID) == IMSIC_MIN_ID);
+
+ qdev_prop_set_bit(dev, "mmode", mmode);
+ qdev_prop_set_uint32(dev, "hartid", hartid);
+ qdev_prop_set_uint32(dev, "num-pages", num_pages);
+ qdev_prop_set_uint32(dev, "num-irqs", num_ids + 1);
+
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+
+ for (i = 0; i < num_pages; i++) {
+ if (!i) {
+ qdev_connect_gpio_out_named(dev, NULL, i,
+ qdev_get_gpio_in(DEVICE(cpu),
+ (mmode) ? IRQ_M_EXT : IRQ_S_EXT));
+ } else {
+ qdev_connect_gpio_out_named(dev, NULL, i,
+ qdev_get_gpio_in(DEVICE(cpu),
+ IRQ_LOCAL_MAX + i - 1));
+ }
+ }
+
+ return dev;
+}
diff --git a/include/hw/intc/riscv_imsic.h b/include/hw/intc/riscv_imsic.h
new file mode 100644
index 0000000000..58c2aaa8dc
--- /dev/null
+++ b/include/hw/intc/riscv_imsic.h
@@ -0,0 +1,68 @@
+/*
+ * RISC-V IMSIC (Incoming Message Signal Interrupt Controller) interface
+ *
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_RISCV_IMSIC_H
+#define HW_RISCV_IMSIC_H
+
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+#define TYPE_RISCV_IMSIC "riscv.imsic"
+
+typedef struct RISCVIMSICState RISCVIMSICState;
+DECLARE_INSTANCE_CHECKER(RISCVIMSICState, RISCV_IMSIC, TYPE_RISCV_IMSIC)
+
+#define IMSIC_MMIO_PAGE_SHIFT 12
+#define IMSIC_MMIO_PAGE_SZ (1UL << IMSIC_MMIO_PAGE_SHIFT)
+#define IMSIC_MMIO_SIZE(__num_pages) ((__num_pages) * IMSIC_MMIO_PAGE_SZ)
+
+#define IMSIC_MMIO_HART_GUEST_MAX_BTIS 6
+#define IMSIC_MMIO_GROUP_MIN_SHIFT 24
+
+#define IMSIC_HART_NUM_GUESTS(__guest_bits) \
+ (1U << (__guest_bits))
+#define IMSIC_HART_SIZE(__guest_bits) \
+ (IMSIC_HART_NUM_GUESTS(__guest_bits) * IMSIC_MMIO_PAGE_SZ)
+#define IMSIC_GROUP_NUM_HARTS(__hart_bits) \
+ (1U << (__hart_bits))
+#define IMSIC_GROUP_SIZE(__hart_bits, __guest_bits) \
+ (IMSIC_GROUP_NUM_HARTS(__hart_bits) * IMSIC_HART_SIZE(__guest_bits))
+
+struct RISCVIMSICState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ qemu_irq *external_irqs;
+
+ /*< public >*/
+ MemoryRegion mmio;
+ uint32_t num_eistate;
+ uint32_t *eidelivery;
+ uint32_t *eithreshold;
+ uint32_t *eistate;
+
+ /* config */
+ bool mmode;
+ uint32_t hartid;
+ uint32_t num_pages;
+ uint32_t num_irqs;
+};
+
+DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode,
+ uint32_t num_pages, uint32_t num_ids);
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v4 21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
` (19 preceding siblings ...)
2021-10-26 6:42 ` [PATCH v4 20/22] hw/intc: Add RISC-V AIA IMSIC device emulation Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 22/22] docs/system: riscv: Document AIA options for " Anup Patel
21 siblings, 0 replies; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra, Bin Meng
We extend virt machine to emulate both AIA IMSIC and AIA APLIC
devices only when "aia=aplic-imsic" parameter is passed along
with machine name in the QEMU command-line. The AIA IMSIC is
only a per-HART MSI controller so we use AIA APLIC in MSI-mode
to forward all wired interrupts as MSIs to the AIA IMSIC.
We also provide "aia-guests=<xyz>" parameter which can be used
to specify number of VS-level AIA IMSIC Guests MMIO pages for
each HART.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
hw/riscv/Kconfig | 1 +
hw/riscv/virt.c | 430 ++++++++++++++++++++++++++++++++--------
include/hw/riscv/virt.h | 16 +-
3 files changed, 363 insertions(+), 84 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index c30bb7cb6c..91bb9d21c4 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -43,6 +43,7 @@ config RISCV_VIRT
select SERIAL
select RISCV_ACLINT
select RISCV_APLIC
+ select RISCV_IMSIC
select SIFIVE_PLIC
select SIFIVE_TEST
select VIRTIO_MMIO
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4e21b485aa..4dcabcc8ef 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -34,6 +34,7 @@
#include "hw/riscv/numa.h"
#include "hw/intc/riscv_aclint.h"
#include "hw/intc/riscv_aplic.h"
+#include "hw/intc/riscv_imsic.h"
#include "hw/intc/sifive_plic.h"
#include "hw/misc/sifive_test.h"
#include "chardev/char.h"
@@ -43,6 +44,13 @@
#include "hw/pci-host/gpex.h"
#include "hw/display/ramfb.h"
+#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
+#define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \
+ VIRT_IMSIC_GROUP_MAX_SIZE)
+#if 0x4000000 < VIRT_IMSIC_MAX_SIZE
+#error "Can't accomodate IMSIC in address space"
+#endif
+
static const MemMapEntry virt_memmap[] = {
[VIRT_DEBUG] = { 0x0, 0x100 },
[VIRT_MROM] = { 0x1000, 0xf000 },
@@ -58,6 +66,8 @@ static const MemMapEntry virt_memmap[] = {
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
[VIRT_FW_CFG] = { 0x10100000, 0x18 },
[VIRT_FLASH] = { 0x20000000, 0x4000000 },
+ [VIRT_IMSIC_M] = { 0x24000000, 0x4000000 },
+ [VIRT_IMSIC_S] = { 0x28000000, 0x4000000 },
[VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
[VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
[VIRT_DRAM] = { 0x80000000, 0x0 },
@@ -309,7 +319,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
{
int cpu;
char *name;
- unsigned long addr;
+ unsigned long addr, size;
uint32_t aclint_cells_size;
uint32_t *aclint_mswi_cells;
uint32_t *aclint_sswi_cells;
@@ -330,29 +340,38 @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
}
aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2;
- addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
- name = g_strdup_printf("/soc/mswi@%lx", addr);
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-mswi");
- qemu_fdt_setprop_cells(mc->fdt, name, "reg",
- 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
- qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
- aclint_mswi_cells, aclint_cells_size);
- qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
- qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
- riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
- g_free(name);
+ if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
+ addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
+ name = g_strdup_printf("/soc/mswi@%lx", addr);
+ qemu_fdt_add_subnode(mc->fdt, name);
+ qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+ "riscv,aclint-mswi");
+ qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
+ qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
+ aclint_mswi_cells, aclint_cells_size);
+ qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
+ riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
+ g_free(name);
+ }
- addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE +
- (memmap[VIRT_CLINT].size * socket);
+ if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
+ addr = memmap[VIRT_CLINT].base +
+ (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket);
+ size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE;
+ } else {
+ addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE +
+ (memmap[VIRT_CLINT].size * socket);
+ size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE;
+ }
name = g_strdup_printf("/soc/mtimer@%lx", addr);
qemu_fdt_add_subnode(mc->fdt, name);
qemu_fdt_setprop_string(mc->fdt, name, "compatible",
"riscv,aclint-mtimer");
qemu_fdt_setprop_cells(mc->fdt, name, "reg",
0x0, addr + RISCV_ACLINT_DEFAULT_MTIME,
- 0x0, memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE -
- RISCV_ACLINT_DEFAULT_MTIME,
+ 0x0, size - RISCV_ACLINT_DEFAULT_MTIME,
0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
0x0, RISCV_ACLINT_DEFAULT_MTIME);
qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
@@ -360,19 +379,22 @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
g_free(name);
- addr = memmap[VIRT_ACLINT_SSWI].base +
- (memmap[VIRT_ACLINT_SSWI].size * socket);
- name = g_strdup_printf("/soc/sswi@%lx", addr);
- qemu_fdt_add_subnode(mc->fdt, name);
- qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-sswi");
- qemu_fdt_setprop_cells(mc->fdt, name, "reg",
- 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size);
- qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
- aclint_sswi_cells, aclint_cells_size);
- qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
- qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
- riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
- g_free(name);
+ if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
+ addr = memmap[VIRT_ACLINT_SSWI].base +
+ (memmap[VIRT_ACLINT_SSWI].size * socket);
+ name = g_strdup_printf("/soc/sswi@%lx", addr);
+ qemu_fdt_add_subnode(mc->fdt, name);
+ qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+ "riscv,aclint-sswi");
+ qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size);
+ qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
+ aclint_sswi_cells, aclint_cells_size);
+ qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
+ riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
+ g_free(name);
+ }
g_free(aclint_mswi_cells);
g_free(aclint_mtimer_cells);
@@ -425,10 +447,145 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
g_free(plic_cells);
}
-static void create_fdt_socket_aia(RISCVVirtState *s,
- const MemMapEntry *memmap, int socket,
- uint32_t *phandle, uint32_t *intc_phandles,
- uint32_t *aplic_phandles)
+static uint32_t imsic_num_bits(uint32_t count)
+{
+ uint32_t ret = 0;
+
+ while (BIT(ret) < count) {
+ ret++;
+ }
+
+ return ret;
+}
+
+static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
+ uint32_t *phandle, uint32_t *intc_phandles,
+ uint32_t *msi_m_phandle, uint32_t *msi_s_phandle)
+{
+ int cpu, socket;
+ char *imsic_name;
+ MachineState *mc = MACHINE(s);
+ uint32_t imsic_max_hart_per_socket, imsic_guest_bits;
+ uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size;
+
+ *msi_m_phandle = (*phandle)++;
+ *msi_s_phandle = (*phandle)++;
+ imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2);
+ imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4);
+
+ /* M-level IMSIC node */
+ for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
+ imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
+ imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
+ }
+ imsic_max_hart_per_socket = 0;
+ for (socket = 0; socket < riscv_socket_count(mc); socket++) {
+ imsic_addr = memmap[VIRT_IMSIC_M].base +
+ socket * VIRT_IMSIC_GROUP_MAX_SIZE;
+ imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts;
+ imsic_regs[socket * 4 + 0] = 0;
+ imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);
+ imsic_regs[socket * 4 + 2] = 0;
+ imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);
+ if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
+ imsic_max_hart_per_socket = s->soc[socket].num_harts;
+ }
+ }
+ imsic_name = g_strdup_printf("/soc/imsics@%lx",
+ memmap[VIRT_IMSIC_M].base);
+ qemu_fdt_add_subnode(mc->fdt, imsic_name);
+ qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible",
+ "riscv,imsics");
+ qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells",
+ FDT_IMSIC_INT_CELLS);
+ qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller",
+ NULL, 0);
+ qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller",
+ NULL, 0);
+ qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
+ imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
+ qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
+ riscv_socket_count(mc) * sizeof(uint32_t) * 4);
+ qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
+ VIRT_IRQCHIP_NUM_MSIS);
+ qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-range",
+ VIRT_IRQCHIP_BASE_IPI, VIRT_IRQCHIP_NUM_IPIS);
+ if (riscv_socket_count(mc) > 1) {
+ qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
+ imsic_num_bits(imsic_max_hart_per_socket));
+ qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
+ imsic_num_bits(riscv_socket_count(mc)));
+ qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
+ IMSIC_MMIO_GROUP_MIN_SHIFT);
+ }
+ qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle);
+ g_free(imsic_name);
+
+ /* S-level IMSIC node */
+ for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
+ imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
+ imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
+ }
+ imsic_guest_bits = imsic_num_bits(s->aia_guests + 1);
+ imsic_max_hart_per_socket = 0;
+ for (socket = 0; socket < riscv_socket_count(mc); socket++) {
+ imsic_addr = memmap[VIRT_IMSIC_S].base +
+ socket * VIRT_IMSIC_GROUP_MAX_SIZE;
+ imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) *
+ s->soc[socket].num_harts;
+ imsic_regs[socket * 4 + 0] = 0;
+ imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);
+ imsic_regs[socket * 4 + 2] = 0;
+ imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);
+ if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
+ imsic_max_hart_per_socket = s->soc[socket].num_harts;
+ }
+ }
+ imsic_name = g_strdup_printf("/soc/imsics@%lx",
+ memmap[VIRT_IMSIC_S].base);
+ qemu_fdt_add_subnode(mc->fdt, imsic_name);
+ qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible",
+ "riscv,imsics");
+ qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells",
+ FDT_IMSIC_INT_CELLS);
+ qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller",
+ NULL, 0);
+ qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller",
+ NULL, 0);
+ qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
+ imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
+ qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
+ riscv_socket_count(mc) * sizeof(uint32_t) * 4);
+ qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
+ VIRT_IRQCHIP_NUM_MSIS);
+ qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-range",
+ VIRT_IRQCHIP_BASE_IPI, VIRT_IRQCHIP_NUM_IPIS);
+ if (imsic_guest_bits) {
+ qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits",
+ imsic_guest_bits);
+ }
+ if (riscv_socket_count(mc) > 1) {
+ qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
+ imsic_num_bits(imsic_max_hart_per_socket));
+ qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
+ imsic_num_bits(riscv_socket_count(mc)));
+ qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
+ IMSIC_MMIO_GROUP_MIN_SHIFT);
+ }
+ qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle);
+ g_free(imsic_name);
+
+ g_free(imsic_regs);
+ g_free(imsic_cells);
+}
+
+static void create_fdt_socket_aplic(RISCVVirtState *s,
+ const MemMapEntry *memmap, int socket,
+ uint32_t msi_m_phandle,
+ uint32_t msi_s_phandle,
+ uint32_t *phandle,
+ uint32_t *intc_phandles,
+ uint32_t *aplic_phandles)
{
int cpu;
char *aplic_name;
@@ -454,8 +611,13 @@ static void create_fdt_socket_aia(RISCVVirtState *s,
qemu_fdt_setprop_cell(mc->fdt, aplic_name,
"#interrupt-cells", FDT_APLIC_INT_CELLS);
qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
- qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
- aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
+ if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
+ qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
+ aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
+ } else {
+ qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent",
+ msi_m_phandle);
+ }
qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size);
qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
@@ -481,8 +643,13 @@ static void create_fdt_socket_aia(RISCVVirtState *s,
qemu_fdt_setprop_cell(mc->fdt, aplic_name,
"#interrupt-cells", FDT_APLIC_INT_CELLS);
qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
- qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
- aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
+ if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
+ qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
+ aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
+ } else {
+ qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent",
+ msi_s_phandle);
+ }
qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size);
qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
@@ -499,13 +666,14 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
bool is_32_bit, uint32_t *phandle,
uint32_t *irq_mmio_phandle,
uint32_t *irq_pcie_phandle,
- uint32_t *irq_virtio_phandle)
+ uint32_t *irq_virtio_phandle,
+ uint32_t *msi_pcie_phandle)
{
- int socket;
char *clust_name;
- uint32_t *intc_phandles;
+ int socket, phandle_pos;
MachineState *mc = MACHINE(s);
- uint32_t xplic_phandles[MAX_NODES];
+ uint32_t msi_m_phandle = 0, msi_s_phandle = 0;
+ uint32_t *intc_phandles, xplic_phandles[MAX_NODES];
qemu_fdt_add_subnode(mc->fdt, "/cpus");
qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency",
@@ -514,35 +682,53 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1);
qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map");
+ intc_phandles = g_new0(uint32_t, mc->smp.cpus);
+
+ phandle_pos = mc->smp.cpus;
for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
+ phandle_pos -= s->soc[socket].num_harts;
+
clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
qemu_fdt_add_subnode(mc->fdt, clust_name);
- intc_phandles = g_new0(uint32_t, s->soc[socket].num_harts);
-
create_fdt_socket_cpus(s, socket, clust_name, phandle,
- is_32_bit, intc_phandles);
+ is_32_bit, &intc_phandles[phandle_pos]);
create_fdt_socket_memory(s, memmap, socket);
+ g_free(clust_name);
+
if (s->have_aclint) {
- create_fdt_socket_aclint(s, memmap, socket, intc_phandles);
+ create_fdt_socket_aclint(s, memmap, socket,
+ &intc_phandles[phandle_pos]);
} else {
- create_fdt_socket_clint(s, memmap, socket, intc_phandles);
+ create_fdt_socket_clint(s, memmap, socket,
+ &intc_phandles[phandle_pos]);
}
+ }
+
+ if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
+ create_fdt_imsic(s, memmap, phandle, intc_phandles,
+ &msi_m_phandle, &msi_s_phandle);
+ *msi_pcie_phandle = msi_s_phandle;
+ }
+
+ phandle_pos = mc->smp.cpus;
+ for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
+ phandle_pos -= s->soc[socket].num_harts;
if (s->aia_type == VIRT_AIA_TYPE_NONE) {
create_fdt_socket_plic(s, memmap, socket, phandle,
- intc_phandles, xplic_phandles);
+ &intc_phandles[phandle_pos], xplic_phandles);
} else {
- create_fdt_socket_aia(s, memmap, socket, phandle,
- intc_phandles, xplic_phandles);
+ create_fdt_socket_aplic(s, memmap, socket,
+ msi_m_phandle, msi_s_phandle, phandle,
+ &intc_phandles[phandle_pos], xplic_phandles);
}
-
- g_free(intc_phandles);
- g_free(clust_name);
}
+ g_free(intc_phandles);
+
for (socket = 0; socket < riscv_socket_count(mc); socket++) {
if (socket == 0) {
*irq_mmio_phandle = xplic_phandles[socket];
@@ -590,7 +776,8 @@ static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
}
static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
- uint32_t irq_pcie_phandle)
+ uint32_t irq_pcie_phandle,
+ uint32_t msi_pcie_phandle)
{
char *name;
MachineState *mc = MACHINE(s);
@@ -610,6 +797,9 @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0,
memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0);
+ if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
+ qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle);
+ }
qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0,
memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges",
@@ -735,7 +925,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
uint64_t mem_size, const char *cmdline, bool is_32_bit)
{
MachineState *mc = MACHINE(s);
- uint32_t phandle = 1, irq_mmio_phandle = 1;
+ uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
if (mc->dtb) {
@@ -765,11 +955,12 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2);
create_fdt_sockets(s, memmap, is_32_bit, &phandle,
- &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle);
+ &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle,
+ &msi_pcie_phandle);
create_fdt_virtio(s, memmap, irq_virtio_phandle);
- create_fdt_pcie(s, memmap, irq_pcie_phandle);
+ create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle);
create_fdt_reset(s, memmap, &phandle);
@@ -902,30 +1093,55 @@ static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket,
return ret;
}
-static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type,
+static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
const MemMapEntry *memmap, int socket,
int base_hartid, int hart_count)
{
+ int i;
+ hwaddr addr;
+ uint32_t guest_bits;
DeviceState *aplic_m;
+ bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false;
+
+ if (msimode) {
+ /* Per-socket M-level IMSICs */
+ addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
+ for (i = 0; i < hart_count; i++) {
+ riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),
+ base_hartid + i, true, 1,
+ VIRT_IRQCHIP_NUM_MSIS);
+ }
+
+ /* Per-socket S-level IMSICs */
+ guest_bits = imsic_num_bits(aia_guests + 1);
+ addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
+ for (i = 0; i < hart_count; i++) {
+ riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits),
+ base_hartid + i, false, 1 + aia_guests,
+ VIRT_IRQCHIP_NUM_MSIS);
+ }
+ }
/* Per-socket M-level APLIC */
aplic_m = riscv_aplic_create(
memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size,
memmap[VIRT_APLIC_M].size,
- base_hartid, hart_count,
+ (msimode) ? 0 : base_hartid,
+ (msimode) ? 0 : hart_count,
VIRT_IRQCHIP_NUM_SOURCES,
VIRT_IRQCHIP_NUM_PRIO_BITS,
- false, true, NULL);
+ msimode, true, NULL);
if (aplic_m) {
/* Per-socket S-level APLIC */
riscv_aplic_create(
memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size,
memmap[VIRT_APLIC_S].size,
- base_hartid, hart_count,
+ (msimode) ? 0 : base_hartid,
+ (msimode) ? 0 : hart_count,
VIRT_IRQCHIP_NUM_SOURCES,
VIRT_IRQCHIP_NUM_PRIO_BITS,
- false, false, aplic_m);
+ msimode, false, aplic_m);
}
return aplic_m;
@@ -984,23 +1200,38 @@ static void virt_machine_init(MachineState *machine)
hart_count, &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
- /* Per-socket CLINT */
- riscv_aclint_swi_create(
- memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
- base_hartid, hart_count, false);
- riscv_aclint_mtimer_create(
- memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size +
- RISCV_ACLINT_SWI_SIZE,
- RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
- RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
- RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
-
- /* Per-socket ACLINT SSWI */
if (s->have_aclint) {
+ if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
+ /* Per-socket ACLINT MTIMER */
+ riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
+ i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
+ RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
+ RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
+ RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
+ } else {
+ /* Per-socket ACLINT MSWI, MTIMER, and SSWI */
+ riscv_aclint_swi_create(memmap[VIRT_CLINT].base +
+ i * memmap[VIRT_CLINT].size,
+ base_hartid, hart_count, false);
+ riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
+ i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE,
+ RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
+ RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
+ RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
+ riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base +
+ i * memmap[VIRT_ACLINT_SSWI].size,
+ base_hartid, hart_count, true);
+ }
+ } else {
+ /* Per-socket SiFive CLINT */
riscv_aclint_swi_create(
- memmap[VIRT_ACLINT_SSWI].base +
- i * memmap[VIRT_ACLINT_SSWI].size,
- base_hartid, hart_count, true);
+ memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
+ base_hartid, hart_count, false);
+ riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
+ i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE,
+ RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
+ RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
+ RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
}
/* Per-socket interrupt controller */
@@ -1008,8 +1239,9 @@ static void virt_machine_init(MachineState *machine)
s->irqchip[i] = virt_create_plic(memmap, i,
base_hartid, hart_count);
} else {
- s->irqchip[i] = virt_create_aia(s->aia_type, memmap, i,
- base_hartid, hart_count);
+ s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests,
+ memmap, i, base_hartid,
+ hart_count);
}
/* Try to use different IRQCHIP instance based device type */
@@ -1156,6 +1388,27 @@ static void virt_machine_instance_init(Object *obj)
{
}
+static char *virt_get_aia_guests(Object *obj, Error **errp)
+{
+ RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
+ char val[32];
+
+ sprintf(val, "%d", s->aia_guests);
+ return g_strdup(val);
+}
+
+static void virt_set_aia_guests(Object *obj, const char *val, Error **errp)
+{
+ RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
+
+ s->aia_guests = atoi(val);
+ if (s->aia_guests < 0 || s->aia_guests > IRQ_LOCAL_GUEST_MAX) {
+ error_setg(errp, "Invalid number of AIA IMSIC guests");
+ error_append_hint(errp, "Valid values be between 0 and 31 (for RV32) "
+ "or between 0 and 63 (for RV64).\n");
+ }
+}
+
static char *virt_get_aia(Object *obj, Error **errp)
{
RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
@@ -1165,6 +1418,9 @@ static char *virt_get_aia(Object *obj, Error **errp)
case VIRT_AIA_TYPE_APLIC:
val = "aplic";
break;
+ case VIRT_AIA_TYPE_APLIC_IMSIC:
+ val = "aplic-imsic";
+ break;
default:
val = "none";
break;
@@ -1181,9 +1437,12 @@ static void virt_set_aia(Object *obj, const char *val, Error **errp)
s->aia_type = VIRT_AIA_TYPE_NONE;
} else if (!strcmp(val, "aplic")) {
s->aia_type = VIRT_AIA_TYPE_APLIC;
+ } else if (!strcmp(val, "aplic-imsic")) {
+ s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC;
} else {
error_setg(errp, "Invalid AIA interrupt controller type");
- error_append_hint(errp, "Valid values are none, and aplic.\n");
+ error_append_hint(errp, "Valid values are none, aplic, and "
+ "aplic-imsic.\n");
}
}
@@ -1231,7 +1490,16 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
object_class_property_set_description(oc, "aia",
"Set type of AIA interrupt "
"conttoller. Valid values are "
- "none, and aplic.");
+ "none, aplic, and aplic-imsic.");
+
+ object_class_property_add_str(oc, "aia-guests",
+ virt_get_aia_guests,
+ virt_set_aia_guests);
+ object_class_property_set_description(oc, "aia-guests",
+ "Set number of guest MMIO pages "
+ "for AIA IMSIC. Valid value should "
+ "be between 0 and 31 (for RV32) or "
+ "between 0 and 63 (for RV64).");
}
static const TypeInfo virt_machine_typeinfo = {
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index a26ef4a295..a20b80dd1d 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -24,8 +24,10 @@
#include "hw/block/flash.h"
#include "qom/object.h"
-#define VIRT_CPUS_MAX 8
-#define VIRT_SOCKETS_MAX 8
+#define VIRT_CPUS_MAX_BITS 3
+#define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS)
+#define VIRT_SOCKETS_MAX_BITS 2
+#define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS)
#define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
typedef struct RISCVVirtState RISCVVirtState;
@@ -35,6 +37,7 @@ DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE,
typedef enum RISCVVirtAIAType {
VIRT_AIA_TYPE_NONE=0,
VIRT_AIA_TYPE_APLIC,
+ VIRT_AIA_TYPE_APLIC_IMSIC,
} RISCVVirtAIAType;
struct RISCVVirtState {
@@ -50,6 +53,7 @@ struct RISCVVirtState {
int fdt_size;
bool have_aclint;
RISCVVirtAIAType aia_type;
+ int aia_guests;
};
enum {
@@ -65,6 +69,8 @@ enum {
VIRT_UART0,
VIRT_VIRTIO,
VIRT_FW_CFG,
+ VIRT_IMSIC_M,
+ VIRT_IMSIC_S,
VIRT_FLASH,
VIRT_DRAM,
VIRT_PCIE_MMIO,
@@ -81,7 +87,10 @@ enum {
VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
};
-#define VIRT_IRQCHIP_NUM_SOURCES 127
+#define VIRT_IRQCHIP_BASE_IPI 1
+#define VIRT_IRQCHIP_NUM_IPIS 7
+#define VIRT_IRQCHIP_NUM_MSIS 255
+#define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV
#define VIRT_IRQCHIP_NUM_PRIO_BITS 3
#define VIRT_PLIC_HART_CONFIG "MS"
@@ -98,6 +107,7 @@ enum {
#define FDT_PCI_INT_CELLS 1
#define FDT_PLIC_INT_CELLS 1
#define FDT_APLIC_INT_CELLS 2
+#define FDT_IMSIC_INT_CELLS 0
#define FDT_MAX_INT_CELLS 2
#define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
1 + FDT_MAX_INT_CELLS)
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v4 22/22] docs/system: riscv: Document AIA options for virt machine
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
` (20 preceding siblings ...)
2021-10-26 6:42 ` [PATCH v4 21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Anup Patel
@ 2021-10-26 6:42 ` Anup Patel
21 siblings, 0 replies; 41+ messages in thread
From: Anup Patel @ 2021-10-26 6:42 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra,
Alistair Francis, Bin Meng
We have two new machine options "aia" and "aia-guests" available
for the RISC-V virt machine so let's document these options.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/riscv/virt.rst | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index fa016584bf..373645513a 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -63,6 +63,22 @@ The following machine-specific options are supported:
When this option is "on", ACLINT devices will be emulated instead of
SiFive CLINT. When not specified, this option is assumed to be "off".
+- aia=[none|aplic|aplic-imsic]
+
+ This option allows selecting interrupt controller defined by the AIA
+ (advanced interrupt architecture) specification. The "aia=aplic" selects
+ APLIC (advanced platform level interrupt controller) to handle wired
+ interrupts whereas the "aia=aplic-imsic" selects APLIC and IMSIC (incoming
+ message signaled interrupt controller) to handle both wired interrupts and
+ MSIs. When not specified, this option is assumed to be "none" which selects
+ SiFive PLIC to handle wired interrupts.
+
+- aia-guests=nnn
+
+ The number of per-HART VS-level AIA IMSIC pages to be emulated for a guest
+ having AIA IMSIC (i.e. "aia=aplic-imsic" selected). When not specified,
+ the default number of per-HART VS-level AIA IMSIC pages is 0.
+
Running Linux kernel
--------------------
--
2.25.1
^ permalink raw reply related [flat|nested] 41+ messages in thread