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From: haibo.chen@nxp.com
To: ashish.kumar@nxp.com, yogeshgaur.83@gmail.com,
	broonie@kernel.org, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, han.xu@nxp.com,
	singh.kuldeep87k@gmail.com, tudor.ambarus@microchip.com,
	p.yadav@ti.com, michael@walle.cc, miquel.raynal@bootlin.com,
	richard@nod.at, vigneshr@ti.com, shawnguo@kernel.org,
	s.hauer@pengutronix.de, kernel@pengutronix.de
Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-mtd@lists.infradead.org,
	festevam@gmail.com, linux-imx@nxp.com,
	linux-arm-kernel@lists.infradead.org, haibo.chen@nxp.com,
	zhengxunli@mxic.com.tw
Subject: [PATCH 09/11] mtd: spi-nor: macronix: add mx25uw51345g OPI mode support
Date: Tue,  5 Jul 2022 17:11:41 +0800	[thread overview]
Message-ID: <1657012303-6464-9-git-send-email-haibo.chen@nxp.com> (raw)
In-Reply-To: <1657012303-6464-1-git-send-email-haibo.chen@nxp.com>

From: Haibo Chen <haibo.chen@nxp.com>

mx25uw51345g has a special OPI DTR read command id, so add this
special fixup.
For RDID under OPI DTR mode, the dummy need to enlarge to 20 cycles,
otherwise can't get correct ID value.

Acked-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 drivers/mtd/spi-nor/macronix.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index b4f4d8185cce..99140fc9305b 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -13,6 +13,7 @@
 #define SPINOR_REG_MXIC_CR2_MODE	0x00000000	/* For setting octal DTR mode */
 #define SPINOR_REG_MXIC_OPI_DTR_EN	0x2		/* Enable Octal DTR */
 #define SPINOR_REG_MXIC_SPI_EN		0x0		/* Enable SPI */
+#define SPINOR_OP_OPI_DTR_RD		0xEE		/* OPI DTR first read opcode */
 
 static int
 mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
@@ -117,6 +118,19 @@ static struct spi_nor_fixups octaflash_fixups = {
 	.default_init = octaflash_default_init,
 };
 
+static void mx25uw51345g_post_sfdp_fixup(struct spi_nor *nor)
+{
+	nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
+	spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR],
+				  0, 20, SPINOR_OP_OPI_DTR_RD,
+				  SNOR_PROTO_8_8_8_DTR);
+}
+
+static struct spi_nor_fixups mx25uw51345g_fixups = {
+	.default_init = octaflash_default_init,
+	.post_sfdp = mx25uw51345g_post_sfdp_fixup,
+};
+
 static const struct flash_info macronix_nor_parts[] = {
 	/* Macronix */
 	{ "mx25l512e",   INFO(0xc22010, 0, 64 * 1024,   1)
@@ -264,7 +278,7 @@ static const struct flash_info macronix_nor_parts[] = {
 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
 			      SPI_NOR_OCTAL_DTR_PP)
 		FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
-		.fixups = &octaflash_fixups },
+		.fixups = &mx25uw51345g_fixups },
 	{ "mx25um25645g", INFO(0xc28039, 0, 8 * 1024, 4096)
 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
 			      SPI_NOR_OCTAL_DTR_PP)
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: haibo.chen@nxp.com
To: ashish.kumar@nxp.com, yogeshgaur.83@gmail.com,
	broonie@kernel.org, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, han.xu@nxp.com,
	singh.kuldeep87k@gmail.com, tudor.ambarus@microchip.com,
	p.yadav@ti.com, michael@walle.cc, miquel.raynal@bootlin.com,
	richard@nod.at, vigneshr@ti.com, shawnguo@kernel.org,
	s.hauer@pengutronix.de, kernel@pengutronix.de
Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-mtd@lists.infradead.org,
	festevam@gmail.com, linux-imx@nxp.com,
	linux-arm-kernel@lists.infradead.org, haibo.chen@nxp.com,
	zhengxunli@mxic.com.tw
Subject: [PATCH 09/11] mtd: spi-nor: macronix: add mx25uw51345g OPI mode support
Date: Tue,  5 Jul 2022 17:11:41 +0800	[thread overview]
Message-ID: <1657012303-6464-9-git-send-email-haibo.chen@nxp.com> (raw)
In-Reply-To: <1657012303-6464-1-git-send-email-haibo.chen@nxp.com>

From: Haibo Chen <haibo.chen@nxp.com>

mx25uw51345g has a special OPI DTR read command id, so add this
special fixup.
For RDID under OPI DTR mode, the dummy need to enlarge to 20 cycles,
otherwise can't get correct ID value.

Acked-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 drivers/mtd/spi-nor/macronix.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index b4f4d8185cce..99140fc9305b 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -13,6 +13,7 @@
 #define SPINOR_REG_MXIC_CR2_MODE	0x00000000	/* For setting octal DTR mode */
 #define SPINOR_REG_MXIC_OPI_DTR_EN	0x2		/* Enable Octal DTR */
 #define SPINOR_REG_MXIC_SPI_EN		0x0		/* Enable SPI */
+#define SPINOR_OP_OPI_DTR_RD		0xEE		/* OPI DTR first read opcode */
 
 static int
 mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
@@ -117,6 +118,19 @@ static struct spi_nor_fixups octaflash_fixups = {
 	.default_init = octaflash_default_init,
 };
 
+static void mx25uw51345g_post_sfdp_fixup(struct spi_nor *nor)
+{
+	nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
+	spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR],
+				  0, 20, SPINOR_OP_OPI_DTR_RD,
+				  SNOR_PROTO_8_8_8_DTR);
+}
+
+static struct spi_nor_fixups mx25uw51345g_fixups = {
+	.default_init = octaflash_default_init,
+	.post_sfdp = mx25uw51345g_post_sfdp_fixup,
+};
+
 static const struct flash_info macronix_nor_parts[] = {
 	/* Macronix */
 	{ "mx25l512e",   INFO(0xc22010, 0, 64 * 1024,   1)
@@ -264,7 +278,7 @@ static const struct flash_info macronix_nor_parts[] = {
 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
 			      SPI_NOR_OCTAL_DTR_PP)
 		FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
-		.fixups = &octaflash_fixups },
+		.fixups = &mx25uw51345g_fixups },
 	{ "mx25um25645g", INFO(0xc28039, 0, 8 * 1024, 4096)
 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
 			      SPI_NOR_OCTAL_DTR_PP)
-- 
2.25.1


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: haibo.chen@nxp.com
To: ashish.kumar@nxp.com, yogeshgaur.83@gmail.com,
	broonie@kernel.org, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, han.xu@nxp.com,
	singh.kuldeep87k@gmail.com, tudor.ambarus@microchip.com,
	p.yadav@ti.com, michael@walle.cc, miquel.raynal@bootlin.com,
	richard@nod.at, vigneshr@ti.com, shawnguo@kernel.org,
	s.hauer@pengutronix.de, kernel@pengutronix.de
Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-mtd@lists.infradead.org,
	festevam@gmail.com, linux-imx@nxp.com,
	linux-arm-kernel@lists.infradead.org, haibo.chen@nxp.com,
	zhengxunli@mxic.com.tw
Subject: [PATCH 09/11] mtd: spi-nor: macronix: add mx25uw51345g OPI mode support
Date: Tue,  5 Jul 2022 17:11:41 +0800	[thread overview]
Message-ID: <1657012303-6464-9-git-send-email-haibo.chen@nxp.com> (raw)
In-Reply-To: <1657012303-6464-1-git-send-email-haibo.chen@nxp.com>

From: Haibo Chen <haibo.chen@nxp.com>

mx25uw51345g has a special OPI DTR read command id, so add this
special fixup.
For RDID under OPI DTR mode, the dummy need to enlarge to 20 cycles,
otherwise can't get correct ID value.

Acked-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 drivers/mtd/spi-nor/macronix.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index b4f4d8185cce..99140fc9305b 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -13,6 +13,7 @@
 #define SPINOR_REG_MXIC_CR2_MODE	0x00000000	/* For setting octal DTR mode */
 #define SPINOR_REG_MXIC_OPI_DTR_EN	0x2		/* Enable Octal DTR */
 #define SPINOR_REG_MXIC_SPI_EN		0x0		/* Enable SPI */
+#define SPINOR_OP_OPI_DTR_RD		0xEE		/* OPI DTR first read opcode */
 
 static int
 mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
@@ -117,6 +118,19 @@ static struct spi_nor_fixups octaflash_fixups = {
 	.default_init = octaflash_default_init,
 };
 
+static void mx25uw51345g_post_sfdp_fixup(struct spi_nor *nor)
+{
+	nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
+	spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR],
+				  0, 20, SPINOR_OP_OPI_DTR_RD,
+				  SNOR_PROTO_8_8_8_DTR);
+}
+
+static struct spi_nor_fixups mx25uw51345g_fixups = {
+	.default_init = octaflash_default_init,
+	.post_sfdp = mx25uw51345g_post_sfdp_fixup,
+};
+
 static const struct flash_info macronix_nor_parts[] = {
 	/* Macronix */
 	{ "mx25l512e",   INFO(0xc22010, 0, 64 * 1024,   1)
@@ -264,7 +278,7 @@ static const struct flash_info macronix_nor_parts[] = {
 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
 			      SPI_NOR_OCTAL_DTR_PP)
 		FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
-		.fixups = &octaflash_fixups },
+		.fixups = &mx25uw51345g_fixups },
 	{ "mx25um25645g", INFO(0xc28039, 0, 8 * 1024, 4096)
 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
 			      SPI_NOR_OCTAL_DTR_PP)
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2022-07-05  9:27 UTC|newest]

Thread overview: 99+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-05  9:11 [PATCH 01/11] spi: spi-nxp-fspi: enable runtime pm for fspi haibo.chen
2022-07-05  9:11 ` haibo.chen
2022-07-05  9:11 ` haibo.chen
2022-07-05  9:11 ` [PATCH 02/11] spi: spi-nxp-fspi: change the default lut index haibo.chen
2022-07-05  9:11   ` haibo.chen
2022-07-05  9:11   ` haibo.chen
2022-07-05  9:11 ` [PATCH 03/11] spi: spi-nxp-fspi: add DTR mode support haibo.chen
2022-07-05  9:11   ` haibo.chen
2022-07-05  9:11   ` haibo.chen
2022-07-05  9:11 ` [PATCH 04/11] spi: spi-nxp-fspi: add function to select sample clock source for flash reading haibo.chen
2022-07-05  9:11   ` haibo.chen
2022-07-05  9:11   ` haibo.chen
2022-07-06 21:02   ` Michael Walle
2022-07-06 21:02     ` Michael Walle
2022-07-06 21:02     ` Michael Walle
2022-07-05  9:11 ` [PATCH 05/11] spi: spi-nxp-fspi: Add quirk to disable DTR support haibo.chen
2022-07-05  9:11   ` haibo.chen
2022-07-05  9:11   ` haibo.chen
2022-07-05 13:50   ` Michael Walle
2022-07-05 13:50     ` Michael Walle
2022-07-05 13:50     ` Michael Walle
2022-07-05  9:11 ` [PATCH 06/11] spi: spi-nxp-fspi: enable octal ddr for iMX8QM/QXP/DXL haibo.chen
2022-07-05  9:11   ` haibo.chen
2022-07-05  9:11   ` haibo.chen
2022-07-05  9:11 ` [PATCH 07/11] dt-bindings: spi: spi-nxp-fspi: add a new property nxp,fspi-dll-slvdly haibo.chen
2022-07-05  9:11   ` haibo.chen
2022-07-05  9:11   ` haibo.chen
2022-07-05  9:48   ` Krzysztof Kozlowski
2022-07-05  9:48     ` Krzysztof Kozlowski
2022-07-05  9:48     ` Krzysztof Kozlowski
2022-07-05 10:28     ` Bough Chen
2022-07-05 10:28       ` Bough Chen
2022-07-05 10:28       ` Bough Chen
2022-07-05 10:36       ` Krzysztof Kozlowski
2022-07-05 10:36         ` Krzysztof Kozlowski
2022-07-05 10:36         ` Krzysztof Kozlowski
2022-07-05 13:19         ` Han Xu
2022-07-05 13:19           ` Han Xu
2022-07-05 13:19           ` Han Xu
2022-07-05 13:29           ` Krzysztof Kozlowski
2022-07-05 13:29             ` Krzysztof Kozlowski
2022-07-05 13:29             ` Krzysztof Kozlowski
2022-07-05 14:00             ` Han Xu
2022-07-05 14:00               ` Han Xu
2022-07-05 14:00               ` Han Xu
2022-07-05 14:03               ` Krzysztof Kozlowski
2022-07-05 14:03                 ` Krzysztof Kozlowski
2022-07-05 14:03                 ` Krzysztof Kozlowski
2022-07-05 14:31                 ` Han Xu
2022-07-05 14:31                   ` Han Xu
2022-07-05 14:31                   ` Han Xu
2022-07-05 14:06               ` Michael Walle
2022-07-05 14:06                 ` Michael Walle
2022-07-05 14:06                 ` Michael Walle
2022-07-05 14:12                 ` Krzysztof Kozlowski
2022-07-05 14:12                   ` Krzysztof Kozlowski
2022-07-05 14:12                   ` Krzysztof Kozlowski
2022-07-05 14:52                   ` Han Xu
2022-07-05 14:52                     ` Han Xu
2022-07-05 14:52                     ` Han Xu
2022-07-05 14:58                     ` Michael Walle
2022-07-05 14:58                       ` Michael Walle
2022-07-05 14:58                       ` Michael Walle
2022-07-05 15:07                       ` Mark Brown
2022-07-05 15:07                         ` Mark Brown
2022-07-05 15:07                         ` Mark Brown
2022-07-05 15:38                     ` Krzysztof Kozlowski
2022-07-05 15:38                       ` Krzysztof Kozlowski
2022-07-05 15:38                       ` Krzysztof Kozlowski
2022-07-05 15:50                       ` Han Xu
2022-07-05 15:50                         ` Han Xu
2022-07-05 15:50                         ` Han Xu
2022-07-06 16:11                         ` Rob Herring
2022-07-06 16:11                           ` Rob Herring
2022-07-06 16:11                           ` Rob Herring
2022-07-06 20:59                           ` Michael Walle
2022-07-06 20:59                             ` Michael Walle
2022-07-06 20:59                             ` Michael Walle
2022-07-05  9:11 ` [PATCH 08/11] mtd: spi-nor: macronix: add support for Macronix octaflash haibo.chen
2022-07-05  9:11   ` haibo.chen
2022-07-05  9:11   ` haibo.chen
2022-07-05  9:11 ` haibo.chen [this message]
2022-07-05  9:11   ` [PATCH 09/11] mtd: spi-nor: macronix: add mx25uw51345g OPI mode support haibo.chen
2022-07-05  9:11   ` haibo.chen
2022-07-18  6:57   ` Michael Walle
2022-07-18  6:57     ` Michael Walle
2022-07-18  6:57     ` Michael Walle
2022-07-05  9:11 ` [PATCH 10/11] arm64: dts: imx8ulp: add flexspi support haibo.chen
2022-07-05  9:11   ` haibo.chen
2022-07-05  9:11   ` haibo.chen
2022-07-05  9:11 ` [PATCH 11/11] arm64: dts: imx8qm/imx8qxp: " haibo.chen
2022-07-05  9:11   ` haibo.chen
2022-07-05  9:11   ` haibo.chen
2022-07-05 14:01 ` [PATCH 01/11] spi: spi-nxp-fspi: enable runtime pm for fspi Michael Walle
2022-07-05 14:01   ` Michael Walle
2022-07-05 14:01   ` Michael Walle
2022-07-05 23:06   ` Han Xu
2022-07-05 23:06     ` Han Xu
2022-07-05 23:06     ` Han Xu

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