From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu <andy.chiu@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Heiko Stuebner <heiko.stuebner@vrull.eu>, Guo Ren <guoren@kernel.org>, Conor Dooley <conor.dooley@microchip.com>, Al Viro <viro@zeniv.linux.org.uk>, Mathis Salmen <mathis.salmen@matsal.de>, Vincent Chen <vincent.chen@sifive.com>, Andrew Bresticker <abrestic@rivosinc.com> Subject: [PATCH -next v19 13/24] riscv: signal: check fp-reserved words unconditionally Date: Tue, 9 May 2023 10:30:22 +0000 [thread overview] Message-ID: <20230509103033.11285-14-andy.chiu@sifive.com> (raw) In-Reply-To: <20230509103033.11285-1-andy.chiu@sifive.com> In order to let kernel/user locate and identify an extension context on the existing sigframe, we are going to utilize reserved space of fp and encode the information there. And since the sigcontext has already preserved a space for fp context w or w/o CONFIG_FPU, we move those reserved words checking/setting routine back into generic code. This commit also undone an additional logical change carried by the refactor commit 007f5c3589578 ("Refactor FPU code in signal setup/return procedures"). Originally we did not restore fp context if restoring of gpr have failed. And it was fine on the other side. In such way the kernel could keep the regfiles intact, and potentially react at the failing point of restore. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu> --- arch/riscv/kernel/signal.c | 55 +++++++++++++++++++------------------- 1 file changed, 28 insertions(+), 27 deletions(-) diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 9aff9d720590..6b4a5c90bd87 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -40,26 +40,13 @@ static long restore_fp_state(struct pt_regs *regs, { long err; struct __riscv_d_ext_state __user *state = &sc_fpregs->d; - size_t i; err = __copy_from_user(¤t->thread.fstate, state, sizeof(*state)); if (unlikely(err)) return err; fstate_restore(current, regs); - - /* We support no other extension state at this time. */ - for (i = 0; i < ARRAY_SIZE(sc_fpregs->q.reserved); i++) { - u32 value; - - err = __get_user(value, &sc_fpregs->q.reserved[i]); - if (unlikely(err)) - break; - if (value != 0) - return -EINVAL; - } - - return err; + return 0; } static long save_fp_state(struct pt_regs *regs, @@ -67,20 +54,9 @@ static long save_fp_state(struct pt_regs *regs, { long err; struct __riscv_d_ext_state __user *state = &sc_fpregs->d; - size_t i; fstate_save(current, regs); err = __copy_to_user(state, ¤t->thread.fstate, sizeof(*state)); - if (unlikely(err)) - return err; - - /* We support no other extension state at this time. */ - for (i = 0; i < ARRAY_SIZE(sc_fpregs->q.reserved); i++) { - err = __put_user(0, &sc_fpregs->q.reserved[i]); - if (unlikely(err)) - break; - } - return err; } #else @@ -92,11 +68,30 @@ static long restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) { long err; + size_t i; + /* sc_regs is structured the same as the start of pt_regs */ err = __copy_from_user(regs, &sc->sc_regs, sizeof(sc->sc_regs)); + if (unlikely(err)) + return err; + /* Restore the floating-point state. */ - if (has_fpu()) - err |= restore_fp_state(regs, &sc->sc_fpregs); + if (has_fpu()) { + err = restore_fp_state(regs, &sc->sc_fpregs); + if (unlikely(err)) + return err; + } + + /* We support no other extension state at this time. */ + for (i = 0; i < ARRAY_SIZE(sc->sc_fpregs.q.reserved); i++) { + u32 value; + + err = __get_user(value, &sc->sc_fpregs.q.reserved[i]); + if (unlikely(err)) + break; + if (value != 0) + return -EINVAL; + } return err; } @@ -147,11 +142,17 @@ static long setup_sigcontext(struct rt_sigframe __user *frame, { struct sigcontext __user *sc = &frame->uc.uc_mcontext; long err; + size_t i; + /* sc_regs is structured the same as the start of pt_regs */ err = __copy_to_user(&sc->sc_regs, regs, sizeof(sc->sc_regs)); /* Save the floating-point state. */ if (has_fpu()) err |= save_fp_state(regs, &sc->sc_fpregs); + /* We support no other extension state at this time. */ + for (i = 0; i < ARRAY_SIZE(sc->sc_fpregs.q.reserved); i++) + err |= __put_user(0, &sc->sc_fpregs.q.reserved[i]); + return err; } -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu <andy.chiu@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Heiko Stuebner <heiko.stuebner@vrull.eu>, Guo Ren <guoren@kernel.org>, Conor Dooley <conor.dooley@microchip.com>, Al Viro <viro@zeniv.linux.org.uk>, Mathis Salmen <mathis.salmen@matsal.de>, Vincent Chen <vincent.chen@sifive.com>, Andrew Bresticker <abrestic@rivosinc.com> Subject: [PATCH -next v19 13/24] riscv: signal: check fp-reserved words unconditionally Date: Tue, 9 May 2023 10:30:22 +0000 [thread overview] Message-ID: <20230509103033.11285-14-andy.chiu@sifive.com> (raw) In-Reply-To: <20230509103033.11285-1-andy.chiu@sifive.com> In order to let kernel/user locate and identify an extension context on the existing sigframe, we are going to utilize reserved space of fp and encode the information there. And since the sigcontext has already preserved a space for fp context w or w/o CONFIG_FPU, we move those reserved words checking/setting routine back into generic code. This commit also undone an additional logical change carried by the refactor commit 007f5c3589578 ("Refactor FPU code in signal setup/return procedures"). Originally we did not restore fp context if restoring of gpr have failed. And it was fine on the other side. In such way the kernel could keep the regfiles intact, and potentially react at the failing point of restore. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu> --- arch/riscv/kernel/signal.c | 55 +++++++++++++++++++------------------- 1 file changed, 28 insertions(+), 27 deletions(-) diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 9aff9d720590..6b4a5c90bd87 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -40,26 +40,13 @@ static long restore_fp_state(struct pt_regs *regs, { long err; struct __riscv_d_ext_state __user *state = &sc_fpregs->d; - size_t i; err = __copy_from_user(¤t->thread.fstate, state, sizeof(*state)); if (unlikely(err)) return err; fstate_restore(current, regs); - - /* We support no other extension state at this time. */ - for (i = 0; i < ARRAY_SIZE(sc_fpregs->q.reserved); i++) { - u32 value; - - err = __get_user(value, &sc_fpregs->q.reserved[i]); - if (unlikely(err)) - break; - if (value != 0) - return -EINVAL; - } - - return err; + return 0; } static long save_fp_state(struct pt_regs *regs, @@ -67,20 +54,9 @@ static long save_fp_state(struct pt_regs *regs, { long err; struct __riscv_d_ext_state __user *state = &sc_fpregs->d; - size_t i; fstate_save(current, regs); err = __copy_to_user(state, ¤t->thread.fstate, sizeof(*state)); - if (unlikely(err)) - return err; - - /* We support no other extension state at this time. */ - for (i = 0; i < ARRAY_SIZE(sc_fpregs->q.reserved); i++) { - err = __put_user(0, &sc_fpregs->q.reserved[i]); - if (unlikely(err)) - break; - } - return err; } #else @@ -92,11 +68,30 @@ static long restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) { long err; + size_t i; + /* sc_regs is structured the same as the start of pt_regs */ err = __copy_from_user(regs, &sc->sc_regs, sizeof(sc->sc_regs)); + if (unlikely(err)) + return err; + /* Restore the floating-point state. */ - if (has_fpu()) - err |= restore_fp_state(regs, &sc->sc_fpregs); + if (has_fpu()) { + err = restore_fp_state(regs, &sc->sc_fpregs); + if (unlikely(err)) + return err; + } + + /* We support no other extension state at this time. */ + for (i = 0; i < ARRAY_SIZE(sc->sc_fpregs.q.reserved); i++) { + u32 value; + + err = __get_user(value, &sc->sc_fpregs.q.reserved[i]); + if (unlikely(err)) + break; + if (value != 0) + return -EINVAL; + } return err; } @@ -147,11 +142,17 @@ static long setup_sigcontext(struct rt_sigframe __user *frame, { struct sigcontext __user *sc = &frame->uc.uc_mcontext; long err; + size_t i; + /* sc_regs is structured the same as the start of pt_regs */ err = __copy_to_user(&sc->sc_regs, regs, sizeof(sc->sc_regs)); /* Save the floating-point state. */ if (has_fpu()) err |= save_fp_state(regs, &sc->sc_fpregs); + /* We support no other extension state at this time. */ + for (i = 0; i < ARRAY_SIZE(sc->sc_fpregs.q.reserved); i++) + err |= __put_user(0, &sc->sc_fpregs.q.reserved[i]); + return err; } -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-05-09 10:32 UTC|newest] Thread overview: 110+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-05-09 10:30 [PATCH -next v19 00/24] riscv: Add vector ISA support Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 01/24] riscv: Rename __switch_to_aux() -> fpu Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-16 2:47 ` Andy Chiu 2023-05-16 2:47 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 02/24] riscv: Extending cpufeature.c to detect V-extension Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-09 10:30 ` [PATCH -next v19 03/24] riscv: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_V Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 11:05 ` Heiko Stübner 2023-05-09 11:05 ` Heiko Stübner 2023-05-09 16:41 ` Andy Chiu 2023-05-09 16:41 ` Andy Chiu 2023-05-09 17:32 ` Evan Green 2023-05-09 17:32 ` Evan Green 2023-05-09 17:59 ` Palmer Dabbelt 2023-05-09 17:59 ` Palmer Dabbelt 2023-05-09 18:29 ` Evan Green 2023-05-09 18:29 ` Evan Green 2023-05-11 22:36 ` Palmer Dabbelt 2023-05-11 22:36 ` Palmer Dabbelt 2023-05-09 10:30 ` [PATCH -next v19 04/24] riscv: Add new csr defines related to vector extension Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-16 3:15 ` Andy Chiu 2023-05-16 3:15 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 05/24] riscv: Clear vector regfile on bootup Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-09 10:30 ` [PATCH -next v19 06/24] riscv: Disable Vector Instructions for kernel itself Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-09 10:30 ` [PATCH -next v19 07/24] riscv: Introduce Vector enable/disable helpers Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-09 10:30 ` [PATCH -next v19 08/24] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-09 10:30 ` [PATCH -next v19 09/24] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 10/24] riscv: Add task switch support for vector Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 11/24] riscv: Allocate user's vector context in the first-use trap Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 12/24] riscv: Add ptrace vector support Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` Andy Chiu [this message] 2023-05-09 10:30 ` [PATCH -next v19 13/24] riscv: signal: check fp-reserved words unconditionally Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 14/24] riscv: signal: Add sigcontext save/restore for vector Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 15/24] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 16/24] riscv: signal: validate altstack to reflect Vector Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 17/24] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 18/24] riscv: kvm: Add V extension to KVM ISA Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 19/24] riscv: KVM: Add vector lazy save/restore support Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 20/24] riscv: Add prctl controls for userspace vector management Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 11:14 ` Heiko Stübner 2023-05-09 11:14 ` Heiko Stübner 2023-05-09 16:11 ` Andy Chiu 2023-05-09 16:11 ` Andy Chiu 2023-05-09 17:58 ` Palmer Dabbelt 2023-05-09 17:58 ` Palmer Dabbelt 2023-05-15 11:38 ` Björn Töpel 2023-05-15 11:38 ` Björn Töpel 2023-05-16 7:13 ` Andy Chiu 2023-05-16 7:13 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 21/24] riscv: Add sysctl to set the default vector rule for new processes Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-15 11:42 ` Björn Töpel 2023-05-15 11:42 ` Björn Töpel 2023-05-09 10:30 ` [PATCH -next v19 22/24] riscv: detect assembler support for .option arch Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 23/24] riscv: Enable Vector code to be built Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 12:34 ` Conor Dooley 2023-05-09 12:34 ` Conor Dooley 2023-05-09 16:04 ` Andy Chiu 2023-05-09 16:04 ` Andy Chiu 2023-05-09 16:53 ` Conor Dooley 2023-05-09 16:53 ` Conor Dooley 2023-05-09 20:59 ` Palmer Dabbelt 2023-05-09 20:59 ` Palmer Dabbelt 2023-05-09 21:06 ` Conor Dooley 2023-05-09 21:06 ` Conor Dooley 2023-05-15 12:04 ` Conor Dooley 2023-05-15 12:04 ` Conor Dooley 2023-05-09 22:14 ` kernel test robot 2023-05-09 22:14 ` kernel test robot 2023-05-09 10:30 ` [PATCH -next v19 24/24] riscv: Add documentation for Vector Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-15 11:41 ` Björn Töpel 2023-05-15 11:41 ` Björn Töpel 2023-05-09 20:59 ` [PATCH -next v19 00/24] riscv: Add vector ISA support Palmer Dabbelt 2023-05-09 20:59 ` Palmer Dabbelt
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