From: "Heiko Stübner" <heiko@sntech.de> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, Andy Chiu <andy.chiu@sifive.com> Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu <andy.chiu@sifive.com>, Jonathan Corbet <corbet@lwn.net>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Evan Green <evan@rivosinc.com>, Conor Dooley <conor.dooley@microchip.com>, Andrew Jones <ajones@ventanamicro.com>, Celeste Liu <coelacanthus@outlook.com>, Andrew Bresticker <abrestic@rivosinc.com> Subject: Re: [PATCH -next v19 03/24] riscv: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_V Date: Tue, 09 May 2023 13:05:36 +0200 [thread overview] Message-ID: <2172277.NgBsaNRSFp@diego> (raw) In-Reply-To: <20230509103033.11285-4-andy.chiu@sifive.com> Am Dienstag, 9. Mai 2023, 12:30:12 CEST schrieb Andy Chiu: > Probing kernel support for Vector extension is available now. > > Signed-off-by: Andy Chiu <andy.chiu@sifive.com> > --- > Documentation/riscv/hwprobe.rst | 10 ++++++++++ > arch/riscv/include/asm/hwprobe.h | 2 +- > arch/riscv/include/uapi/asm/hwprobe.h | 3 +++ > arch/riscv/kernel/sys_riscv.c | 9 +++++++++ > 4 files changed, 23 insertions(+), 1 deletion(-) > > diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst > index 9f0dd62dcb5d..b8755e180fbf 100644 > --- a/Documentation/riscv/hwprobe.rst > +++ b/Documentation/riscv/hwprobe.rst > @@ -53,6 +53,9 @@ The following keys are defined: > programs (it may still be executed in userspace via a > kernel-controlled mechanism such as the vDSO). > > + * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_V`: Support for Vector extension, as > + defined by verion 1.0 of the RISC-V Vector extension. ^^ version [missing the S] > + > * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions > that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: > base system behavior. > @@ -64,6 +67,13 @@ The following keys are defined: > * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined > by version 2.2 of the RISC-V ISA manual. > > +* :c:macro:`RISCV_HWPROBE_KEY_V_EXT_0`: A bitmask containing the extensions > + that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_V`: base > + system behavior. > + > + * :c:macro:`RISCV_HWPROBE_V`: The V extension is supported, as defined by > + version 1.0 of the RISC-V Vector extension manual. > + this seems to be doubling the RISCV_HWPROBE_BASE_BEHAVIOR_V state without adding additional information? Both essentially tell the system that V extension "defined by verion 1.0 of the RISC-V Vector extension" is supported. I don't question that we'll probably need a key for deeper vector- specifics but I guess I'd the commit message should definitly explain why there is a duplication here. > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance > information about the selected set of processors. > > diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h > index 78936f4ff513..39df8604fea1 100644 > --- a/arch/riscv/include/asm/hwprobe.h > +++ b/arch/riscv/include/asm/hwprobe.h > @@ -8,6 +8,6 @@ > > #include <uapi/asm/hwprobe.h> > > -#define RISCV_HWPROBE_MAX_KEY 5 > +#define RISCV_HWPROBE_MAX_KEY 6 > > #endif > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > index 8d745a4ad8a2..93a7fd3fd341 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -22,6 +22,7 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_KEY_MIMPID 2 > #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 > #define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) > +#define RISCV_HWPROBE_BASE_BEHAVIOR_V (1 << 1) > #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 > #define RISCV_HWPROBE_IMA_FD (1 << 0) > #define RISCV_HWPROBE_IMA_C (1 << 1) > @@ -32,6 +33,8 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) > #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) > #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) > +#define RISCV_HWPROBE_KEY_V_EXT_0 6 > +#define RISCV_HWPROBE_V (1 << 0) > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ > > #endif > diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c > index 5db29683ebee..6280a7f778b3 100644 > --- a/arch/riscv/kernel/sys_riscv.c > +++ b/arch/riscv/kernel/sys_riscv.c > @@ -10,6 +10,7 @@ > #include <asm/cpufeature.h> > #include <asm/hwprobe.h> > #include <asm/sbi.h> > +#include <asm/vector.h> > #include <asm/switch_to.h> > #include <asm/uaccess.h> > #include <asm/unistd.h> > @@ -161,6 +162,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, > */ > case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: > pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA; > + pair->value |= RISCV_HWPROBE_BASE_BEHAVIOR_V; Doesn't this also need a if (has_vector()) Heiko > break; > > case RISCV_HWPROBE_KEY_IMA_EXT_0: > @@ -173,6 +175,13 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, > > break; > > + case RISCV_HWPROBE_KEY_V_EXT_0: > + pair->value = 0; > + if (has_vector()) > + pair->value |= RISCV_HWPROBE_V; > + > + break; > + > case RISCV_HWPROBE_KEY_CPUPERF_0: > pair->value = hwprobe_misaligned(cpus); > break; >
WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko@sntech.de> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, Andy Chiu <andy.chiu@sifive.com> Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu <andy.chiu@sifive.com>, Jonathan Corbet <corbet@lwn.net>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Evan Green <evan@rivosinc.com>, Conor Dooley <conor.dooley@microchip.com>, Andrew Jones <ajones@ventanamicro.com>, Celeste Liu <coelacanthus@outlook.com>, Andrew Bresticker <abrestic@rivosinc.com> Subject: Re: [PATCH -next v19 03/24] riscv: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_V Date: Tue, 09 May 2023 13:05:36 +0200 [thread overview] Message-ID: <2172277.NgBsaNRSFp@diego> (raw) In-Reply-To: <20230509103033.11285-4-andy.chiu@sifive.com> Am Dienstag, 9. Mai 2023, 12:30:12 CEST schrieb Andy Chiu: > Probing kernel support for Vector extension is available now. > > Signed-off-by: Andy Chiu <andy.chiu@sifive.com> > --- > Documentation/riscv/hwprobe.rst | 10 ++++++++++ > arch/riscv/include/asm/hwprobe.h | 2 +- > arch/riscv/include/uapi/asm/hwprobe.h | 3 +++ > arch/riscv/kernel/sys_riscv.c | 9 +++++++++ > 4 files changed, 23 insertions(+), 1 deletion(-) > > diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst > index 9f0dd62dcb5d..b8755e180fbf 100644 > --- a/Documentation/riscv/hwprobe.rst > +++ b/Documentation/riscv/hwprobe.rst > @@ -53,6 +53,9 @@ The following keys are defined: > programs (it may still be executed in userspace via a > kernel-controlled mechanism such as the vDSO). > > + * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_V`: Support for Vector extension, as > + defined by verion 1.0 of the RISC-V Vector extension. ^^ version [missing the S] > + > * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions > that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: > base system behavior. > @@ -64,6 +67,13 @@ The following keys are defined: > * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined > by version 2.2 of the RISC-V ISA manual. > > +* :c:macro:`RISCV_HWPROBE_KEY_V_EXT_0`: A bitmask containing the extensions > + that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_V`: base > + system behavior. > + > + * :c:macro:`RISCV_HWPROBE_V`: The V extension is supported, as defined by > + version 1.0 of the RISC-V Vector extension manual. > + this seems to be doubling the RISCV_HWPROBE_BASE_BEHAVIOR_V state without adding additional information? Both essentially tell the system that V extension "defined by verion 1.0 of the RISC-V Vector extension" is supported. I don't question that we'll probably need a key for deeper vector- specifics but I guess I'd the commit message should definitly explain why there is a duplication here. > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance > information about the selected set of processors. > > diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h > index 78936f4ff513..39df8604fea1 100644 > --- a/arch/riscv/include/asm/hwprobe.h > +++ b/arch/riscv/include/asm/hwprobe.h > @@ -8,6 +8,6 @@ > > #include <uapi/asm/hwprobe.h> > > -#define RISCV_HWPROBE_MAX_KEY 5 > +#define RISCV_HWPROBE_MAX_KEY 6 > > #endif > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > index 8d745a4ad8a2..93a7fd3fd341 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -22,6 +22,7 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_KEY_MIMPID 2 > #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 > #define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) > +#define RISCV_HWPROBE_BASE_BEHAVIOR_V (1 << 1) > #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 > #define RISCV_HWPROBE_IMA_FD (1 << 0) > #define RISCV_HWPROBE_IMA_C (1 << 1) > @@ -32,6 +33,8 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) > #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) > #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) > +#define RISCV_HWPROBE_KEY_V_EXT_0 6 > +#define RISCV_HWPROBE_V (1 << 0) > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ > > #endif > diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c > index 5db29683ebee..6280a7f778b3 100644 > --- a/arch/riscv/kernel/sys_riscv.c > +++ b/arch/riscv/kernel/sys_riscv.c > @@ -10,6 +10,7 @@ > #include <asm/cpufeature.h> > #include <asm/hwprobe.h> > #include <asm/sbi.h> > +#include <asm/vector.h> > #include <asm/switch_to.h> > #include <asm/uaccess.h> > #include <asm/unistd.h> > @@ -161,6 +162,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, > */ > case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: > pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA; > + pair->value |= RISCV_HWPROBE_BASE_BEHAVIOR_V; Doesn't this also need a if (has_vector()) Heiko > break; > > case RISCV_HWPROBE_KEY_IMA_EXT_0: > @@ -173,6 +175,13 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, > > break; > > + case RISCV_HWPROBE_KEY_V_EXT_0: > + pair->value = 0; > + if (has_vector()) > + pair->value |= RISCV_HWPROBE_V; > + > + break; > + > case RISCV_HWPROBE_KEY_CPUPERF_0: > pair->value = hwprobe_misaligned(cpus); > break; > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-05-09 11:05 UTC|newest] Thread overview: 110+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-05-09 10:30 [PATCH -next v19 00/24] riscv: Add vector ISA support Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 01/24] riscv: Rename __switch_to_aux() -> fpu Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-16 2:47 ` Andy Chiu 2023-05-16 2:47 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 02/24] riscv: Extending cpufeature.c to detect V-extension Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-09 10:30 ` [PATCH -next v19 03/24] riscv: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_V Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 11:05 ` Heiko Stübner [this message] 2023-05-09 11:05 ` Heiko Stübner 2023-05-09 16:41 ` Andy Chiu 2023-05-09 16:41 ` Andy Chiu 2023-05-09 17:32 ` Evan Green 2023-05-09 17:32 ` Evan Green 2023-05-09 17:59 ` Palmer Dabbelt 2023-05-09 17:59 ` Palmer Dabbelt 2023-05-09 18:29 ` Evan Green 2023-05-09 18:29 ` Evan Green 2023-05-11 22:36 ` Palmer Dabbelt 2023-05-11 22:36 ` Palmer Dabbelt 2023-05-09 10:30 ` [PATCH -next v19 04/24] riscv: Add new csr defines related to vector extension Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-16 3:15 ` Andy Chiu 2023-05-16 3:15 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 05/24] riscv: Clear vector regfile on bootup Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-09 10:30 ` [PATCH -next v19 06/24] riscv: Disable Vector Instructions for kernel itself Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-09 10:30 ` [PATCH -next v19 07/24] riscv: Introduce Vector enable/disable helpers Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-09 10:30 ` [PATCH -next v19 08/24] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-09 10:30 ` [PATCH -next v19 09/24] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 10/24] riscv: Add task switch support for vector Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 11/24] riscv: Allocate user's vector context in the first-use trap Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 12/24] riscv: Add ptrace vector support Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 13/24] riscv: signal: check fp-reserved words unconditionally Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 14/24] riscv: signal: Add sigcontext save/restore for vector Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 15/24] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 16/24] riscv: signal: validate altstack to reflect Vector Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 17/24] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 18/24] riscv: kvm: Add V extension to KVM ISA Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 19/24] riscv: KVM: Add vector lazy save/restore support Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 20/24] riscv: Add prctl controls for userspace vector management Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 11:14 ` Heiko Stübner 2023-05-09 11:14 ` Heiko Stübner 2023-05-09 16:11 ` Andy Chiu 2023-05-09 16:11 ` Andy Chiu 2023-05-09 17:58 ` Palmer Dabbelt 2023-05-09 17:58 ` Palmer Dabbelt 2023-05-15 11:38 ` Björn Töpel 2023-05-15 11:38 ` Björn Töpel 2023-05-16 7:13 ` Andy Chiu 2023-05-16 7:13 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 21/24] riscv: Add sysctl to set the default vector rule for new processes Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-15 11:42 ` Björn Töpel 2023-05-15 11:42 ` Björn Töpel 2023-05-09 10:30 ` [PATCH -next v19 22/24] riscv: detect assembler support for .option arch Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 23/24] riscv: Enable Vector code to be built Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 12:34 ` Conor Dooley 2023-05-09 12:34 ` Conor Dooley 2023-05-09 16:04 ` Andy Chiu 2023-05-09 16:04 ` Andy Chiu 2023-05-09 16:53 ` Conor Dooley 2023-05-09 16:53 ` Conor Dooley 2023-05-09 20:59 ` Palmer Dabbelt 2023-05-09 20:59 ` Palmer Dabbelt 2023-05-09 21:06 ` Conor Dooley 2023-05-09 21:06 ` Conor Dooley 2023-05-15 12:04 ` Conor Dooley 2023-05-15 12:04 ` Conor Dooley 2023-05-09 22:14 ` kernel test robot 2023-05-09 22:14 ` kernel test robot 2023-05-09 10:30 ` [PATCH -next v19 24/24] riscv: Add documentation for Vector Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-15 11:41 ` Björn Töpel 2023-05-15 11:41 ` Björn Töpel 2023-05-09 20:59 ` [PATCH -next v19 00/24] riscv: Add vector ISA support Palmer Dabbelt 2023-05-09 20:59 ` Palmer Dabbelt
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