From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, "Vincent Chen" <vincent.chen@sifive.com>, "Andy Chiu" <andy.chiu@sifive.com>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Heiko Stuebner" <heiko.stuebner@vrull.eu>, "Guo Ren" <guoren@kernel.org>, "Conor Dooley" <conor.dooley@microchip.com>, "Björn Töpel" <bjorn@rivosinc.com>, "Jisheng Zhang" <jszhang@kernel.org>, "Alexandre Ghiti" <alexghiti@rivosinc.com>, "Li Zhengyu" <lizhengyu3@huawei.com>, "Masahiro Yamada" <masahiroy@kernel.org>, "Andrew Jones" <ajones@ventanamicro.com>, "Atish Patra" <atishp@rivosinc.com>, "Anup Patel" <apatel@ventanamicro.com>, "Ley Foon Tan" <leyfoon.tan@starfivetech.com>, "Sunil V L" <sunilvl@ventanamicro.com> Subject: [PATCH -next v19 08/24] riscv: Introduce riscv_v_vsize to record size of Vector context Date: Tue, 9 May 2023 10:30:17 +0000 [thread overview] Message-ID: <20230509103033.11285-9-andy.chiu@sifive.com> (raw) In-Reply-To: <20230509103033.11285-1-andy.chiu@sifive.com> From: Greentime Hu <greentime.hu@sifive.com> This patch is used to detect the size of CPU vector registers and use riscv_v_vsize to save the size of all the vector registers. It assumes all harts has the same capabilities in a SMP system. If a core detects VLENB that is different from the boot core, then it warns and turns off V support for user space. Co-developed-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu> --- Changelog V19: - Fix grammar in WARN() (Conor) Changelog V18: - Detect inconsistent VLEN setup on an SMP system (Heiko). arch/riscv/include/asm/vector.h | 8 ++++++++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/cpufeature.c | 2 ++ arch/riscv/kernel/smpboot.c | 7 +++++++ arch/riscv/kernel/vector.c | 36 +++++++++++++++++++++++++++++++++ 5 files changed, 54 insertions(+) create mode 100644 arch/riscv/kernel/vector.c diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index dfe5a321b2b4..68c9fe831a41 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -7,12 +7,16 @@ #define __ASM_RISCV_VECTOR_H #include <linux/types.h> +#include <uapi/asm-generic/errno.h> #ifdef CONFIG_RISCV_ISA_V #include <asm/hwcap.h> #include <asm/csr.h> +extern unsigned long riscv_v_vsize; +int riscv_v_setup_vsize(void); + static __always_inline bool has_vector(void) { return riscv_has_extension_likely(RISCV_ISA_EXT_v); @@ -30,7 +34,11 @@ static __always_inline void riscv_v_disable(void) #else /* ! CONFIG_RISCV_ISA_V */ +struct pt_regs; + +static inline int riscv_v_setup_vsize(void) { return -EOPNOTSUPP; } static __always_inline bool has_vector(void) { return false; } +#define riscv_v_vsize (0) #endif /* CONFIG_RISCV_ISA_V */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index fbdccc21418a..c51f34c2756a 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_MMU) += vdso.o vdso/ obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o obj-$(CONFIG_FPU) += fpu.o +obj-$(CONFIG_RISCV_ISA_V) += vector.o obj-$(CONFIG_SMP) += smpboot.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP) += cpu_ops.o diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 7aaf92fff64e..28032b083463 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -18,6 +18,7 @@ #include <asm/hwcap.h> #include <asm/patch.h> #include <asm/processor.h> +#include <asm/vector.h> #define NUM_ALPHA_EXTS ('z' - 'a' + 1) @@ -269,6 +270,7 @@ void __init riscv_fill_hwcap(void) } if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + riscv_v_setup_vsize(); /* * ISA string in device tree might have 'v' flag, but * CONFIG_RISCV_ISA_V is disabled in kernel. diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 445a4efee267..66011bf2b36e 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -31,6 +31,8 @@ #include <asm/tlbflush.h> #include <asm/sections.h> #include <asm/smp.h> +#include <uapi/asm/hwcap.h> +#include <asm/vector.h> #include "head.h" @@ -169,6 +171,11 @@ asmlinkage __visible void smp_callin(void) set_cpu_online(curr_cpuid, 1); probe_vendor_features(curr_cpuid); + if (has_vector()) { + if (riscv_v_setup_vsize()) + elf_hwcap &= ~COMPAT_HWCAP_ISA_V; + } + /* * Remote TLB flushes are ignored while the CPU is offline, so emit * a local TLB flush right now just in case. diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c new file mode 100644 index 000000000000..120f1ce9abf9 --- /dev/null +++ b/arch/riscv/kernel/vector.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2023 SiFive + * Author: Andy Chiu <andy.chiu@sifive.com> + */ +#include <linux/export.h> + +#include <asm/vector.h> +#include <asm/csr.h> +#include <asm/elf.h> +#include <asm/bug.h> + +unsigned long riscv_v_vsize __read_mostly; +EXPORT_SYMBOL_GPL(riscv_v_vsize); + +int riscv_v_setup_vsize(void) +{ + unsigned long this_vsize; + + /* There are 32 vector registers with vlenb length. */ + riscv_v_enable(); + this_vsize = csr_read(CSR_VLENB) * 32; + riscv_v_disable(); + + if (!riscv_v_vsize) { + riscv_v_vsize = this_vsize; + return 0; + } + + if (riscv_v_vsize != this_vsize) { + WARN(1, "RISCV_ISA_V only supports one vlenb on SMP systems"); + return -EOPNOTSUPP; + } + + return 0; +} -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: "Anup Patel" <apatel@ventanamicro.com>, guoren@linux.alibaba.com, "Jisheng Zhang" <jszhang@kernel.org>, "Ley Foon Tan" <leyfoon.tan@starfivetech.com>, "Atish Patra" <atishp@rivosinc.com>, "Masahiro Yamada" <masahiroy@kernel.org>, vineetg@rivosinc.com, "Björn Töpel" <bjorn@rivosinc.com>, "Vincent Chen" <vincent.chen@sifive.com>, "Conor Dooley" <conor.dooley@microchip.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Guo Ren" <guoren@kernel.org>, "Andy Chiu" <andy.chiu@sifive.com>, "Paul Walmsley" <paul.walmsley@sifive.com>, greentime.hu@sifive.com, "Andrew Jones" <ajones@ventanamicro.com>, "Heiko Stuebner" <heiko.stuebner@vrull.eu>, "Li Zhengyu" <lizhengyu3@huawei.com>, "Alexandre Ghiti" <alexghiti@rivosinc.com> Subject: [PATCH -next v19 08/24] riscv: Introduce riscv_v_vsize to record size of Vector context Date: Tue, 9 May 2023 10:30:17 +0000 [thread overview] Message-ID: <20230509103033.11285-9-andy.chiu@sifive.com> (raw) In-Reply-To: <20230509103033.11285-1-andy.chiu@sifive.com> From: Greentime Hu <greentime.hu@sifive.com> This patch is used to detect the size of CPU vector registers and use riscv_v_vsize to save the size of all the vector registers. It assumes all harts has the same capabilities in a SMP system. If a core detects VLENB that is different from the boot core, then it warns and turns off V support for user space. Co-developed-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu> --- Changelog V19: - Fix grammar in WARN() (Conor) Changelog V18: - Detect inconsistent VLEN setup on an SMP system (Heiko). arch/riscv/include/asm/vector.h | 8 ++++++++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/cpufeature.c | 2 ++ arch/riscv/kernel/smpboot.c | 7 +++++++ arch/riscv/kernel/vector.c | 36 +++++++++++++++++++++++++++++++++ 5 files changed, 54 insertions(+) create mode 100644 arch/riscv/kernel/vector.c diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index dfe5a321b2b4..68c9fe831a41 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -7,12 +7,16 @@ #define __ASM_RISCV_VECTOR_H #include <linux/types.h> +#include <uapi/asm-generic/errno.h> #ifdef CONFIG_RISCV_ISA_V #include <asm/hwcap.h> #include <asm/csr.h> +extern unsigned long riscv_v_vsize; +int riscv_v_setup_vsize(void); + static __always_inline bool has_vector(void) { return riscv_has_extension_likely(RISCV_ISA_EXT_v); @@ -30,7 +34,11 @@ static __always_inline void riscv_v_disable(void) #else /* ! CONFIG_RISCV_ISA_V */ +struct pt_regs; + +static inline int riscv_v_setup_vsize(void) { return -EOPNOTSUPP; } static __always_inline bool has_vector(void) { return false; } +#define riscv_v_vsize (0) #endif /* CONFIG_RISCV_ISA_V */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index fbdccc21418a..c51f34c2756a 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_MMU) += vdso.o vdso/ obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o obj-$(CONFIG_FPU) += fpu.o +obj-$(CONFIG_RISCV_ISA_V) += vector.o obj-$(CONFIG_SMP) += smpboot.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP) += cpu_ops.o diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 7aaf92fff64e..28032b083463 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -18,6 +18,7 @@ #include <asm/hwcap.h> #include <asm/patch.h> #include <asm/processor.h> +#include <asm/vector.h> #define NUM_ALPHA_EXTS ('z' - 'a' + 1) @@ -269,6 +270,7 @@ void __init riscv_fill_hwcap(void) } if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + riscv_v_setup_vsize(); /* * ISA string in device tree might have 'v' flag, but * CONFIG_RISCV_ISA_V is disabled in kernel. diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 445a4efee267..66011bf2b36e 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -31,6 +31,8 @@ #include <asm/tlbflush.h> #include <asm/sections.h> #include <asm/smp.h> +#include <uapi/asm/hwcap.h> +#include <asm/vector.h> #include "head.h" @@ -169,6 +171,11 @@ asmlinkage __visible void smp_callin(void) set_cpu_online(curr_cpuid, 1); probe_vendor_features(curr_cpuid); + if (has_vector()) { + if (riscv_v_setup_vsize()) + elf_hwcap &= ~COMPAT_HWCAP_ISA_V; + } + /* * Remote TLB flushes are ignored while the CPU is offline, so emit * a local TLB flush right now just in case. diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c new file mode 100644 index 000000000000..120f1ce9abf9 --- /dev/null +++ b/arch/riscv/kernel/vector.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2023 SiFive + * Author: Andy Chiu <andy.chiu@sifive.com> + */ +#include <linux/export.h> + +#include <asm/vector.h> +#include <asm/csr.h> +#include <asm/elf.h> +#include <asm/bug.h> + +unsigned long riscv_v_vsize __read_mostly; +EXPORT_SYMBOL_GPL(riscv_v_vsize); + +int riscv_v_setup_vsize(void) +{ + unsigned long this_vsize; + + /* There are 32 vector registers with vlenb length. */ + riscv_v_enable(); + this_vsize = csr_read(CSR_VLENB) * 32; + riscv_v_disable(); + + if (!riscv_v_vsize) { + riscv_v_vsize = this_vsize; + return 0; + } + + if (riscv_v_vsize != this_vsize) { + WARN(1, "RISCV_ISA_V only supports one vlenb on SMP systems"); + return -EOPNOTSUPP; + } + + return 0; +} -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-05-09 10:32 UTC|newest] Thread overview: 110+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-05-09 10:30 [PATCH -next v19 00/24] riscv: Add vector ISA support Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 01/24] riscv: Rename __switch_to_aux() -> fpu Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-16 2:47 ` Andy Chiu 2023-05-16 2:47 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 02/24] riscv: Extending cpufeature.c to detect V-extension Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-09 10:30 ` [PATCH -next v19 03/24] riscv: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_V Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 11:05 ` Heiko Stübner 2023-05-09 11:05 ` Heiko Stübner 2023-05-09 16:41 ` Andy Chiu 2023-05-09 16:41 ` Andy Chiu 2023-05-09 17:32 ` Evan Green 2023-05-09 17:32 ` Evan Green 2023-05-09 17:59 ` Palmer Dabbelt 2023-05-09 17:59 ` Palmer Dabbelt 2023-05-09 18:29 ` Evan Green 2023-05-09 18:29 ` Evan Green 2023-05-11 22:36 ` Palmer Dabbelt 2023-05-11 22:36 ` Palmer Dabbelt 2023-05-09 10:30 ` [PATCH -next v19 04/24] riscv: Add new csr defines related to vector extension Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-16 3:15 ` Andy Chiu 2023-05-16 3:15 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 05/24] riscv: Clear vector regfile on bootup Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-09 10:30 ` [PATCH -next v19 06/24] riscv: Disable Vector Instructions for kernel itself Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-09 10:30 ` [PATCH -next v19 07/24] riscv: Introduce Vector enable/disable helpers Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-09 10:30 ` Andy Chiu [this message] 2023-05-09 10:30 ` [PATCH -next v19 08/24] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-11 22:56 ` Palmer Dabbelt 2023-05-09 10:30 ` [PATCH -next v19 09/24] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 10/24] riscv: Add task switch support for vector Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 11/24] riscv: Allocate user's vector context in the first-use trap Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 12/24] riscv: Add ptrace vector support Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 13/24] riscv: signal: check fp-reserved words unconditionally Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 14/24] riscv: signal: Add sigcontext save/restore for vector Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 15/24] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 16/24] riscv: signal: validate altstack to reflect Vector Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 17/24] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 18/24] riscv: kvm: Add V extension to KVM ISA Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 19/24] riscv: KVM: Add vector lazy save/restore support Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 20/24] riscv: Add prctl controls for userspace vector management Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 11:14 ` Heiko Stübner 2023-05-09 11:14 ` Heiko Stübner 2023-05-09 16:11 ` Andy Chiu 2023-05-09 16:11 ` Andy Chiu 2023-05-09 17:58 ` Palmer Dabbelt 2023-05-09 17:58 ` Palmer Dabbelt 2023-05-15 11:38 ` Björn Töpel 2023-05-15 11:38 ` Björn Töpel 2023-05-16 7:13 ` Andy Chiu 2023-05-16 7:13 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 21/24] riscv: Add sysctl to set the default vector rule for new processes Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-15 11:42 ` Björn Töpel 2023-05-15 11:42 ` Björn Töpel 2023-05-09 10:30 ` [PATCH -next v19 22/24] riscv: detect assembler support for .option arch Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 10:30 ` [PATCH -next v19 23/24] riscv: Enable Vector code to be built Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-09 12:34 ` Conor Dooley 2023-05-09 12:34 ` Conor Dooley 2023-05-09 16:04 ` Andy Chiu 2023-05-09 16:04 ` Andy Chiu 2023-05-09 16:53 ` Conor Dooley 2023-05-09 16:53 ` Conor Dooley 2023-05-09 20:59 ` Palmer Dabbelt 2023-05-09 20:59 ` Palmer Dabbelt 2023-05-09 21:06 ` Conor Dooley 2023-05-09 21:06 ` Conor Dooley 2023-05-15 12:04 ` Conor Dooley 2023-05-15 12:04 ` Conor Dooley 2023-05-09 22:14 ` kernel test robot 2023-05-09 22:14 ` kernel test robot 2023-05-09 10:30 ` [PATCH -next v19 24/24] riscv: Add documentation for Vector Andy Chiu 2023-05-09 10:30 ` Andy Chiu 2023-05-15 11:41 ` Björn Töpel 2023-05-15 11:41 ` Björn Töpel 2023-05-09 20:59 ` [PATCH -next v19 00/24] riscv: Add vector ISA support Palmer Dabbelt 2023-05-09 20:59 ` Palmer Dabbelt
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20230509103033.11285-9-andy.chiu@sifive.com \ --to=andy.chiu@sifive.com \ --cc=ajones@ventanamicro.com \ --cc=alexghiti@rivosinc.com \ --cc=anup@brainfault.org \ --cc=aou@eecs.berkeley.edu \ --cc=apatel@ventanamicro.com \ --cc=atishp@atishpatra.org \ --cc=atishp@rivosinc.com \ --cc=bjorn@rivosinc.com \ --cc=conor.dooley@microchip.com \ --cc=greentime.hu@sifive.com \ --cc=guoren@kernel.org \ --cc=guoren@linux.alibaba.com \ --cc=heiko.stuebner@vrull.eu \ --cc=jszhang@kernel.org \ --cc=kvm-riscv@lists.infradead.org \ --cc=kvm@vger.kernel.org \ --cc=leyfoon.tan@starfivetech.com \ --cc=linux-riscv@lists.infradead.org \ --cc=lizhengyu3@huawei.com \ --cc=masahiroy@kernel.org \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=sunilvl@ventanamicro.com \ --cc=vincent.chen@sifive.com \ --cc=vineetg@rivosinc.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.