From: Palmer Dabbelt <palmer@dabbelt.com>
To: andy.chiu@sifive.com
Cc: linux-riscv@lists.infradead.org, anup@brainfault.org,
atishp@atishpatra.org, kvm-riscv@lists.infradead.org,
kvm@vger.kernel.org, Vineet Gupta <vineetg@rivosinc.com>,
greentime.hu@sifive.com, guoren@linux.alibaba.com,
andy.chiu@sifive.com, Paul Walmsley <paul.walmsley@sifive.com>,
aou@eecs.berkeley.edu, heiko.stuebner@vrull.eu,
vincent.chen@sifive.com,
Conor Dooley <conor.dooley@microchip.com>,
guoren@kernel.org, alex@ghiti.fr, masahiroy@kernel.org
Subject: Re: [PATCH -next v19 05/24] riscv: Clear vector regfile on bootup
Date: Thu, 11 May 2023 15:56:38 -0700 (PDT) [thread overview]
Message-ID: <mhng-6740b2a0-90ed-49c7-8908-87d55dbda354@palmer-ri-x1c9a> (raw)
In-Reply-To: <20230509103033.11285-6-andy.chiu@sifive.com>
On Tue, 09 May 2023 03:30:14 PDT (-0700), andy.chiu@sifive.com wrote:
> From: Greentime Hu <greentime.hu@sifive.com>
>
> clear vector registers on boot if kernel supports V.
>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> ---
> arch/riscv/kernel/head.S | 27 +++++++++++++++++++++++++--
> 1 file changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index 4bf6c449d78b..3fd6a4bd9c3e 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -392,7 +392,7 @@ ENTRY(reset_regs)
> #ifdef CONFIG_FPU
> csrr t0, CSR_MISA
> andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
> - beqz t0, .Lreset_regs_done
> + beqz t0, .Lreset_regs_done_fpu
>
> li t1, SR_FS
> csrs CSR_STATUS, t1
> @@ -430,8 +430,31 @@ ENTRY(reset_regs)
> fmv.s.x f31, zero
> csrw fcsr, 0
> /* note that the caller must clear SR_FS */
> +.Lreset_regs_done_fpu:
> #endif /* CONFIG_FPU */
> -.Lreset_regs_done:
> +
> +#ifdef CONFIG_RISCV_ISA_V
> + csrr t0, CSR_MISA
> + li t1, COMPAT_HWCAP_ISA_V
> + and t0, t0, t1
> + beqz t0, .Lreset_regs_done_vector
> +
> + /*
> + * Clear vector registers and reset vcsr
> + * VLMAX has a defined value, VLEN is a constant,
> + * and this form of vsetvli is defined to set vl to VLMAX.
> + */
> + li t1, SR_VS
> + csrs CSR_STATUS, t1
> + csrs CSR_VCSR, x0
> + vsetvli t1, x0, e8, m8, ta, ma
> + vmv.v.i v0, 0
> + vmv.v.i v8, 0
> + vmv.v.i v16, 0
> + vmv.v.i v24, 0
> + /* note that the caller must clear SR_VS */
> +.Lreset_regs_done_vector:
> +#endif /* CONFIG_RISCV_ISA_V */
> ret
> END(reset_regs)
> #endif /* CONFIG_RISCV_M_MODE */
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
WARNING: multiple messages have this Message-ID (diff)
From: Palmer Dabbelt <palmer@dabbelt.com>
To: andy.chiu@sifive.com
Cc: linux-riscv@lists.infradead.org, anup@brainfault.org,
atishp@atishpatra.org, kvm-riscv@lists.infradead.org,
kvm@vger.kernel.org, Vineet Gupta <vineetg@rivosinc.com>,
greentime.hu@sifive.com, guoren@linux.alibaba.com,
andy.chiu@sifive.com, Paul Walmsley <paul.walmsley@sifive.com>,
aou@eecs.berkeley.edu, heiko.stuebner@vrull.eu,
vincent.chen@sifive.com,
Conor Dooley <conor.dooley@microchip.com>,
guoren@kernel.org, alex@ghiti.fr, masahiroy@kernel.org
Subject: Re: [PATCH -next v19 05/24] riscv: Clear vector regfile on bootup
Date: Thu, 11 May 2023 15:56:38 -0700 (PDT) [thread overview]
Message-ID: <mhng-6740b2a0-90ed-49c7-8908-87d55dbda354@palmer-ri-x1c9a> (raw)
In-Reply-To: <20230509103033.11285-6-andy.chiu@sifive.com>
On Tue, 09 May 2023 03:30:14 PDT (-0700), andy.chiu@sifive.com wrote:
> From: Greentime Hu <greentime.hu@sifive.com>
>
> clear vector registers on boot if kernel supports V.
>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> ---
> arch/riscv/kernel/head.S | 27 +++++++++++++++++++++++++--
> 1 file changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index 4bf6c449d78b..3fd6a4bd9c3e 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -392,7 +392,7 @@ ENTRY(reset_regs)
> #ifdef CONFIG_FPU
> csrr t0, CSR_MISA
> andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
> - beqz t0, .Lreset_regs_done
> + beqz t0, .Lreset_regs_done_fpu
>
> li t1, SR_FS
> csrs CSR_STATUS, t1
> @@ -430,8 +430,31 @@ ENTRY(reset_regs)
> fmv.s.x f31, zero
> csrw fcsr, 0
> /* note that the caller must clear SR_FS */
> +.Lreset_regs_done_fpu:
> #endif /* CONFIG_FPU */
> -.Lreset_regs_done:
> +
> +#ifdef CONFIG_RISCV_ISA_V
> + csrr t0, CSR_MISA
> + li t1, COMPAT_HWCAP_ISA_V
> + and t0, t0, t1
> + beqz t0, .Lreset_regs_done_vector
> +
> + /*
> + * Clear vector registers and reset vcsr
> + * VLMAX has a defined value, VLEN is a constant,
> + * and this form of vsetvli is defined to set vl to VLMAX.
> + */
> + li t1, SR_VS
> + csrs CSR_STATUS, t1
> + csrs CSR_VCSR, x0
> + vsetvli t1, x0, e8, m8, ta, ma
> + vmv.v.i v0, 0
> + vmv.v.i v8, 0
> + vmv.v.i v16, 0
> + vmv.v.i v24, 0
> + /* note that the caller must clear SR_VS */
> +.Lreset_regs_done_vector:
> +#endif /* CONFIG_RISCV_ISA_V */
> ret
> END(reset_regs)
> #endif /* CONFIG_RISCV_M_MODE */
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
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next prev parent reply other threads:[~2023-05-11 22:56 UTC|newest]
Thread overview: 110+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-09 10:30 [PATCH -next v19 00/24] riscv: Add vector ISA support Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 01/24] riscv: Rename __switch_to_aux() -> fpu Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-11 22:56 ` Palmer Dabbelt
2023-05-11 22:56 ` Palmer Dabbelt
2023-05-16 2:47 ` Andy Chiu
2023-05-16 2:47 ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 02/24] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-11 22:56 ` Palmer Dabbelt
2023-05-11 22:56 ` Palmer Dabbelt
2023-05-09 10:30 ` [PATCH -next v19 03/24] riscv: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_V Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-09 11:05 ` Heiko Stübner
2023-05-09 11:05 ` Heiko Stübner
2023-05-09 16:41 ` Andy Chiu
2023-05-09 16:41 ` Andy Chiu
2023-05-09 17:32 ` Evan Green
2023-05-09 17:32 ` Evan Green
2023-05-09 17:59 ` Palmer Dabbelt
2023-05-09 17:59 ` Palmer Dabbelt
2023-05-09 18:29 ` Evan Green
2023-05-09 18:29 ` Evan Green
2023-05-11 22:36 ` Palmer Dabbelt
2023-05-11 22:36 ` Palmer Dabbelt
2023-05-09 10:30 ` [PATCH -next v19 04/24] riscv: Add new csr defines related to vector extension Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-11 22:56 ` Palmer Dabbelt
2023-05-11 22:56 ` Palmer Dabbelt
2023-05-16 3:15 ` Andy Chiu
2023-05-16 3:15 ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 05/24] riscv: Clear vector regfile on bootup Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-11 22:56 ` Palmer Dabbelt [this message]
2023-05-11 22:56 ` Palmer Dabbelt
2023-05-09 10:30 ` [PATCH -next v19 06/24] riscv: Disable Vector Instructions for kernel itself Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-11 22:56 ` Palmer Dabbelt
2023-05-11 22:56 ` Palmer Dabbelt
2023-05-09 10:30 ` [PATCH -next v19 07/24] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-11 22:56 ` Palmer Dabbelt
2023-05-11 22:56 ` Palmer Dabbelt
2023-05-09 10:30 ` [PATCH -next v19 08/24] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-11 22:56 ` Palmer Dabbelt
2023-05-11 22:56 ` Palmer Dabbelt
2023-05-09 10:30 ` [PATCH -next v19 09/24] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 10/24] riscv: Add task switch support for vector Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 11/24] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 12/24] riscv: Add ptrace vector support Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 13/24] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 14/24] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 15/24] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 16/24] riscv: signal: validate altstack to reflect Vector Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 17/24] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 18/24] riscv: kvm: Add V extension to KVM ISA Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 19/24] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 20/24] riscv: Add prctl controls for userspace vector management Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-09 11:14 ` Heiko Stübner
2023-05-09 11:14 ` Heiko Stübner
2023-05-09 16:11 ` Andy Chiu
2023-05-09 16:11 ` Andy Chiu
2023-05-09 17:58 ` Palmer Dabbelt
2023-05-09 17:58 ` Palmer Dabbelt
2023-05-15 11:38 ` Björn Töpel
2023-05-15 11:38 ` Björn Töpel
2023-05-16 7:13 ` Andy Chiu
2023-05-16 7:13 ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 21/24] riscv: Add sysctl to set the default vector rule for new processes Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-15 11:42 ` Björn Töpel
2023-05-15 11:42 ` Björn Töpel
2023-05-09 10:30 ` [PATCH -next v19 22/24] riscv: detect assembler support for .option arch Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-09 10:30 ` [PATCH -next v19 23/24] riscv: Enable Vector code to be built Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-09 12:34 ` Conor Dooley
2023-05-09 12:34 ` Conor Dooley
2023-05-09 16:04 ` Andy Chiu
2023-05-09 16:04 ` Andy Chiu
2023-05-09 16:53 ` Conor Dooley
2023-05-09 16:53 ` Conor Dooley
2023-05-09 20:59 ` Palmer Dabbelt
2023-05-09 20:59 ` Palmer Dabbelt
2023-05-09 21:06 ` Conor Dooley
2023-05-09 21:06 ` Conor Dooley
2023-05-15 12:04 ` Conor Dooley
2023-05-15 12:04 ` Conor Dooley
2023-05-09 22:14 ` kernel test robot
2023-05-09 22:14 ` kernel test robot
2023-05-09 10:30 ` [PATCH -next v19 24/24] riscv: Add documentation for Vector Andy Chiu
2023-05-09 10:30 ` Andy Chiu
2023-05-15 11:41 ` Björn Töpel
2023-05-15 11:41 ` Björn Töpel
2023-05-09 20:59 ` [PATCH -next v19 00/24] riscv: Add vector ISA support Palmer Dabbelt
2023-05-09 20:59 ` Palmer Dabbelt
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