From: Richard Zhu <hongxing.zhu@nxp.com> To: l.stach@pengutronix.de, bhelgaas@google.com, lorenzo.pieralisi@arm.com, jingoohan1@gmail.com Cc: linux-pci@vger.kernel.org, linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, Richard Zhu <hongxing.zhu@nxp.com> Subject: [PATCH v3 7/7] PCI: imx6: Add the compliance tests mode support Date: Fri, 22 Oct 2021 15:12:30 +0800 [thread overview] Message-ID: <1634886750-13861-8-git-send-email-hongxing.zhu@nxp.com> (raw) In-Reply-To: <1634886750-13861-1-git-send-email-hongxing.zhu@nxp.com> Refer to the system board signal Quality of PCIe archiecture PHY test specification. Signal quality tests(for example: jitters, differential eye opening and so on ) can be executed with devices in the polling.compliance state. To let the device support polling.compliance stat, the clocks and powers shouldn't be turned off when the probe of device driver is failed. Based on CLB(Compliance Load Board) Test Fixture and so on test equipments, the PHY link would be down during the compliance tests. Refer to this scenario, add the i.MX PCIe compliance tests mode enable support, and keep the clocks and powers on, and finish the driver probe without error return. Use the "pci_imx6.compliance=1" in kernel command line to enable the compliance tests mode. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- drivers/pci/controller/dwc/pci-imx6.c | 34 ++++++++++++++++++++------- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index c723df053574..0eb84fae817d 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -143,6 +143,10 @@ struct imx6_pcie { #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) +static bool imx6_pcie_cmp_mode; +module_param_named(compliance, imx6_pcie_cmp_mode, bool, 0644); +MODULE_PARM_DESC(compliance, "i.MX PCIe compliance test mode (1=compliance test mode enabled)"); + static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) { struct dw_pcie *pci = imx6_pcie->pci; @@ -812,10 +816,12 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) * started in Gen2 mode, there is a possibility the devices on the * bus will not be detected at all. This happens with PCIe switches. */ - tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); - tmp &= ~PCI_EXP_LNKCAP_SLS; - tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); + if (!imx6_pcie_cmp_mode) { + tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); + tmp &= ~PCI_EXP_LNKCAP_SLS; + tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); + } /* Start LTSSM. */ imx6_pcie_ltssm_enable(dev); @@ -903,10 +909,13 @@ static void imx6_pcie_host_exit(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); - imx6_pcie_reset_phy(imx6_pcie); - imx6_pcie_clk_disable(imx6_pcie); - if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) - regulator_disable(imx6_pcie->vpcie); + if (!imx6_pcie_cmp_mode) { + imx6_pcie_reset_phy(imx6_pcie); + imx6_pcie_clk_disable(imx6_pcie); + if (imx6_pcie->vpcie + && regulator_is_enabled(imx6_pcie->vpcie) > 0) + regulator_disable(imx6_pcie->vpcie); + } } static const struct dw_pcie_host_ops imx6_pcie_host_ops = { @@ -1191,8 +1200,15 @@ static int imx6_pcie_probe(struct platform_device *pdev) return ret; ret = dw_pcie_host_init(&pci->pp); - if (ret < 0) + if (ret < 0) { + if (imx6_pcie_cmp_mode) { + dev_info(dev, "Driver loaded with compliance test mode enabled.\n"); + ret = 0; + } else { + dev_err(dev, "Unable to add pcie port.\n"); + } return ret; + } if (pci_msi_enabled()) { u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Richard Zhu <hongxing.zhu@nxp.com> To: l.stach@pengutronix.de, bhelgaas@google.com, lorenzo.pieralisi@arm.com, jingoohan1@gmail.com Cc: linux-pci@vger.kernel.org, linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, Richard Zhu <hongxing.zhu@nxp.com> Subject: [PATCH v3 7/7] PCI: imx6: Add the compliance tests mode support Date: Fri, 22 Oct 2021 15:12:30 +0800 [thread overview] Message-ID: <1634886750-13861-8-git-send-email-hongxing.zhu@nxp.com> (raw) In-Reply-To: <1634886750-13861-1-git-send-email-hongxing.zhu@nxp.com> Refer to the system board signal Quality of PCIe archiecture PHY test specification. Signal quality tests(for example: jitters, differential eye opening and so on ) can be executed with devices in the polling.compliance state. To let the device support polling.compliance stat, the clocks and powers shouldn't be turned off when the probe of device driver is failed. Based on CLB(Compliance Load Board) Test Fixture and so on test equipments, the PHY link would be down during the compliance tests. Refer to this scenario, add the i.MX PCIe compliance tests mode enable support, and keep the clocks and powers on, and finish the driver probe without error return. Use the "pci_imx6.compliance=1" in kernel command line to enable the compliance tests mode. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- drivers/pci/controller/dwc/pci-imx6.c | 34 ++++++++++++++++++++------- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index c723df053574..0eb84fae817d 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -143,6 +143,10 @@ struct imx6_pcie { #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) +static bool imx6_pcie_cmp_mode; +module_param_named(compliance, imx6_pcie_cmp_mode, bool, 0644); +MODULE_PARM_DESC(compliance, "i.MX PCIe compliance test mode (1=compliance test mode enabled)"); + static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) { struct dw_pcie *pci = imx6_pcie->pci; @@ -812,10 +816,12 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) * started in Gen2 mode, there is a possibility the devices on the * bus will not be detected at all. This happens with PCIe switches. */ - tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); - tmp &= ~PCI_EXP_LNKCAP_SLS; - tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); + if (!imx6_pcie_cmp_mode) { + tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); + tmp &= ~PCI_EXP_LNKCAP_SLS; + tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); + } /* Start LTSSM. */ imx6_pcie_ltssm_enable(dev); @@ -903,10 +909,13 @@ static void imx6_pcie_host_exit(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); - imx6_pcie_reset_phy(imx6_pcie); - imx6_pcie_clk_disable(imx6_pcie); - if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) - regulator_disable(imx6_pcie->vpcie); + if (!imx6_pcie_cmp_mode) { + imx6_pcie_reset_phy(imx6_pcie); + imx6_pcie_clk_disable(imx6_pcie); + if (imx6_pcie->vpcie + && regulator_is_enabled(imx6_pcie->vpcie) > 0) + regulator_disable(imx6_pcie->vpcie); + } } static const struct dw_pcie_host_ops imx6_pcie_host_ops = { @@ -1191,8 +1200,15 @@ static int imx6_pcie_probe(struct platform_device *pdev) return ret; ret = dw_pcie_host_init(&pci->pp); - if (ret < 0) + if (ret < 0) { + if (imx6_pcie_cmp_mode) { + dev_info(dev, "Driver loaded with compliance test mode enabled.\n"); + ret = 0; + } else { + dev_err(dev, "Unable to add pcie port.\n"); + } return ret; + } if (pci_msi_enabled()) { u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-10-22 7:38 UTC|newest] Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-22 7:12 [PATCH v3 0/7] PCI: imx6: refine codes and add compliance tests mode support Richard Zhu 2021-10-22 7:12 ` Richard Zhu 2021-10-22 7:12 ` [PATCH v3 1/7] PCI: imx6: Encapsulate the clock enable into one standalone function Richard Zhu 2021-10-22 7:12 ` Richard Zhu 2021-10-22 7:12 ` [PATCH v3 2/7] PCI: imx6: Add the error propagation from host_init Richard Zhu 2021-10-22 7:12 ` Richard Zhu 2021-10-22 7:12 ` [PATCH v3 3/7] PCI: imx6: Fix the regulator dump when link never came up Richard Zhu 2021-10-22 7:12 ` Richard Zhu 2021-10-25 11:13 ` Francesco Dolcini 2021-10-25 11:13 ` Francesco Dolcini 2021-10-25 11:23 ` Mark Brown 2021-10-25 11:23 ` Mark Brown 2021-10-26 2:18 ` Richard Zhu 2021-10-26 2:18 ` Richard Zhu 2021-10-26 8:52 ` Francesco Dolcini 2021-10-26 8:52 ` Francesco Dolcini 2021-10-26 9:06 ` Richard Zhu 2021-10-26 9:06 ` Richard Zhu 2021-10-26 9:11 ` Francesco Dolcini 2021-10-26 9:11 ` Francesco Dolcini 2021-10-26 9:18 ` Richard Zhu 2021-10-26 9:18 ` Richard Zhu 2021-10-26 9:48 ` Francesco Dolcini 2021-10-26 9:48 ` Francesco Dolcini 2021-10-28 6:48 ` Richard Zhu 2021-10-28 6:48 ` Richard Zhu 2021-10-26 10:58 ` Mark Brown 2021-10-26 10:58 ` Mark Brown 2021-10-28 6:50 ` Richard Zhu 2021-10-28 6:50 ` Richard Zhu 2021-10-28 11:50 ` Mark Brown 2021-10-28 11:50 ` Mark Brown 2021-10-29 3:58 ` Richard Zhu 2021-10-29 3:58 ` Richard Zhu 2021-10-29 11:46 ` Mark Brown 2021-10-29 11:46 ` Mark Brown 2021-11-01 1:46 ` Richard Zhu 2021-11-01 1:46 ` Richard Zhu 2021-10-26 1:57 ` Richard Zhu 2021-10-26 1:57 ` Richard Zhu 2021-10-22 7:12 ` [PATCH v3 4/7] PCI: imx6: move the clock disable function to a proper place Richard Zhu 2021-10-22 7:12 ` Richard Zhu 2021-10-22 7:12 ` [PATCH v3 5/7] PCI: dwc: add a new callback host exit function into host ops Richard Zhu 2021-10-22 7:12 ` Richard Zhu 2021-10-22 7:12 ` [PATCH v3 6/7] PCI: imx6: Fix the reference handling unbalance when link never came up Richard Zhu 2021-10-22 7:12 ` Richard Zhu 2021-10-22 7:12 ` Richard Zhu [this message] 2021-10-22 7:12 ` [PATCH v3 7/7] PCI: imx6: Add the compliance tests mode support Richard Zhu
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1634886750-13861-8-git-send-email-hongxing.zhu@nxp.com \ --to=hongxing.zhu@nxp.com \ --cc=bhelgaas@google.com \ --cc=jingoohan1@gmail.com \ --cc=kernel@pengutronix.de \ --cc=l.stach@pengutronix.de \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-imx@nxp.com \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-pci@vger.kernel.org \ --cc=lorenzo.pieralisi@arm.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.