From: mark.rutland@arm.com (Mark Rutland) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 4/7] arm64: Disable TTBR0_EL1 during normal kernel execution Date: Tue, 6 Sep 2016 18:31:39 +0100 [thread overview] Message-ID: <20160906173139.GA13934@leverpostej> (raw) In-Reply-To: <1472828533-28197-5-git-send-email-catalin.marinas@arm.com> Hi Catalin, This generally looks fine, and my comments below are mostly nits. :) On Fri, Sep 02, 2016 at 04:02:10PM +0100, Catalin Marinas wrote: > static inline void > -switch_mm(struct mm_struct *prev, struct mm_struct *next, > - struct task_struct *tsk) > +__switch_mm(struct mm_struct *prev, struct mm_struct *next, > + struct task_struct *tsk) It looks like the comment above this function is now out-of-date, and has been somewhat misleading for a while. While we're making changes here, can we remove it entirely? [...] > @@ -109,6 +111,34 @@ > mrs x22, elr_el1 > mrs x23, spsr_el1 > stp lr, x21, [sp, #S_LR] > + > +#ifdef CONFIG_ARM64_TTBR0_PAN > + /* > + * Set the TTBR0 PAN in SPSR. When the exception is taken from EL0, > + * there is no need to check the state of TTBR0_EL1 since accesses are > + * always enabled. Nit: missing 'bit' from the first sentence? [...] > diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c > index 536dce22fe76..4a4aaa47f869 100644 > --- a/arch/arm64/kernel/setup.c > +++ b/arch/arm64/kernel/setup.c > @@ -228,6 +228,14 @@ void __init setup_arch(char **cmdline_p) > { > pr_info("Boot CPU: AArch64 Processor [%08x]\n", read_cpuid_id()); > > +#ifdef CONFIG_ARM64_TTBR0_PAN > + /* > + * uaccess_enable() may be called on the init thread, so make sure > + * the saved TTBR0_EL1 always generates translation faults. > + */ > + init_thread_info.ttbr0 = virt_to_phys(empty_zero_page); > +#endif Just to check, does this need to happen so early? e.g. do we need this to report exceptions safely? Otherwise, it would be nice if we could group this with the uninstall of the idmap a little later in setup_arch. Thanks, Mark.
WARNING: multiple messages have this Message-ID (diff)
From: Mark Rutland <mark.rutland@arm.com> To: Catalin Marinas <catalin.marinas@arm.com> Cc: linux-arm-kernel@lists.infradead.org, AKASHI Takahiro <takahiro.akashi@linaro.org>, Will Deacon <will.deacon@arm.com>, James Morse <james.morse@arm.com>, Kees Cook <keescook@chromium.org>, kernel-hardening@lists.openwall.com Subject: [kernel-hardening] Re: [PATCH v2 4/7] arm64: Disable TTBR0_EL1 during normal kernel execution Date: Tue, 6 Sep 2016 18:31:39 +0100 [thread overview] Message-ID: <20160906173139.GA13934@leverpostej> (raw) In-Reply-To: <1472828533-28197-5-git-send-email-catalin.marinas@arm.com> Hi Catalin, This generally looks fine, and my comments below are mostly nits. :) On Fri, Sep 02, 2016 at 04:02:10PM +0100, Catalin Marinas wrote: > static inline void > -switch_mm(struct mm_struct *prev, struct mm_struct *next, > - struct task_struct *tsk) > +__switch_mm(struct mm_struct *prev, struct mm_struct *next, > + struct task_struct *tsk) It looks like the comment above this function is now out-of-date, and has been somewhat misleading for a while. While we're making changes here, can we remove it entirely? [...] > @@ -109,6 +111,34 @@ > mrs x22, elr_el1 > mrs x23, spsr_el1 > stp lr, x21, [sp, #S_LR] > + > +#ifdef CONFIG_ARM64_TTBR0_PAN > + /* > + * Set the TTBR0 PAN in SPSR. When the exception is taken from EL0, > + * there is no need to check the state of TTBR0_EL1 since accesses are > + * always enabled. Nit: missing 'bit' from the first sentence? [...] > diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c > index 536dce22fe76..4a4aaa47f869 100644 > --- a/arch/arm64/kernel/setup.c > +++ b/arch/arm64/kernel/setup.c > @@ -228,6 +228,14 @@ void __init setup_arch(char **cmdline_p) > { > pr_info("Boot CPU: AArch64 Processor [%08x]\n", read_cpuid_id()); > > +#ifdef CONFIG_ARM64_TTBR0_PAN > + /* > + * uaccess_enable() may be called on the init thread, so make sure > + * the saved TTBR0_EL1 always generates translation faults. > + */ > + init_thread_info.ttbr0 = virt_to_phys(empty_zero_page); > +#endif Just to check, does this need to happen so early? e.g. do we need this to report exceptions safely? Otherwise, it would be nice if we could group this with the uninstall of the idmap a little later in setup_arch. Thanks, Mark.
next prev parent reply other threads:[~2016-09-06 17:31 UTC|newest] Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-09-02 15:02 [PATCH v2 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching Catalin Marinas 2016-09-02 15:02 ` [kernel-hardening] " Catalin Marinas 2016-09-02 15:02 ` [PATCH v2 1/7] arm64: Factor out PAN enabling/disabling into separate uaccess_* macros Catalin Marinas 2016-09-02 15:02 ` [kernel-hardening] " Catalin Marinas 2016-09-05 15:38 ` Mark Rutland 2016-09-05 15:38 ` [kernel-hardening] " Mark Rutland 2016-09-12 14:52 ` Catalin Marinas 2016-09-12 14:52 ` [kernel-hardening] " Catalin Marinas 2016-09-12 15:09 ` Mark Rutland 2016-09-12 15:09 ` [kernel-hardening] " Mark Rutland 2016-09-12 16:26 ` Catalin Marinas 2016-09-12 16:26 ` [kernel-hardening] " Catalin Marinas 2016-09-02 15:02 ` [PATCH v2 2/7] arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro Catalin Marinas 2016-09-02 15:02 ` [kernel-hardening] " Catalin Marinas 2016-09-05 16:11 ` Mark Rutland 2016-09-05 16:11 ` [kernel-hardening] " Mark Rutland 2016-09-02 15:02 ` [PATCH v2 3/7] arm64: Introduce uaccess_{disable, enable} functionality based on TTBR0_EL1 Catalin Marinas 2016-09-02 15:02 ` [kernel-hardening] [PATCH v2 3/7] arm64: Introduce uaccess_{disable,enable} " Catalin Marinas 2016-09-05 17:20 ` [PATCH v2 3/7] arm64: Introduce uaccess_{disable, enable} " Mark Rutland 2016-09-05 17:20 ` [kernel-hardening] " Mark Rutland 2016-09-06 10:27 ` Catalin Marinas 2016-09-06 10:27 ` [kernel-hardening] " Catalin Marinas 2016-09-06 10:45 ` Mark Rutland 2016-09-06 10:45 ` [kernel-hardening] " Mark Rutland 2016-09-11 13:55 ` Ard Biesheuvel 2016-09-11 13:55 ` Ard Biesheuvel 2016-09-12 9:32 ` Catalin Marinas 2016-09-12 9:32 ` Catalin Marinas 2016-09-09 17:15 ` Catalin Marinas 2016-09-09 17:15 ` [kernel-hardening] " Catalin Marinas 2016-09-02 15:02 ` [PATCH v2 4/7] arm64: Disable TTBR0_EL1 during normal kernel execution Catalin Marinas 2016-09-02 15:02 ` [kernel-hardening] " Catalin Marinas 2016-09-06 17:31 ` Mark Rutland [this message] 2016-09-06 17:31 ` [kernel-hardening] " Mark Rutland 2016-09-02 15:02 ` [PATCH v2 5/7] arm64: Handle faults caused by inadvertent user access with PAN enabled Catalin Marinas 2016-09-02 15:02 ` [kernel-hardening] " Catalin Marinas 2016-09-02 15:02 ` [PATCH v2 6/7] arm64: xen: Enable user access before a privcmd hvc call Catalin Marinas 2016-09-02 15:02 ` [kernel-hardening] " Catalin Marinas 2016-09-02 15:02 ` [PATCH v2 7/7] arm64: Enable CONFIG_ARM64_TTBR0_PAN Catalin Marinas 2016-09-02 15:02 ` [kernel-hardening] " Catalin Marinas 2016-09-02 15:47 ` Mark Rutland 2016-09-02 15:47 ` [kernel-hardening] " Mark Rutland 2016-09-07 23:20 ` [PATCH v2 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching Kees Cook 2016-09-07 23:20 ` [kernel-hardening] " Kees Cook 2016-09-08 12:51 ` Catalin Marinas 2016-09-08 12:51 ` [kernel-hardening] " Catalin Marinas 2016-09-08 15:50 ` Kees Cook 2016-09-08 15:50 ` [kernel-hardening] " Kees Cook 2016-09-09 16:31 ` Mark Rutland 2016-09-09 16:31 ` [kernel-hardening] " Mark Rutland 2016-09-09 18:24 ` Kees Cook 2016-09-09 18:24 ` [kernel-hardening] " Kees Cook 2016-09-09 23:40 ` [kernel-hardening] " David Brown 2016-09-09 23:40 ` David Brown 2016-09-10 9:51 ` Catalin Marinas 2016-09-10 9:51 ` [kernel-hardening] " Catalin Marinas 2016-09-10 10:56 ` Ard Biesheuvel 2016-09-10 10:56 ` [kernel-hardening] " Ard Biesheuvel 2016-09-11 12:16 ` Catalin Marinas 2016-09-11 12:16 ` [kernel-hardening] " Catalin Marinas
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