From: keescook@chromium.org (Kees Cook)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching
Date: Fri, 9 Sep 2016 11:24:30 -0700 [thread overview]
Message-ID: <CAGXu5jJMdym7jWv5P7YHdqu4eU7a3dzQqgXHppzOwRCYQ6O1Cg@mail.gmail.com> (raw)
In-Reply-To: <20160909163116.GA10792@leverpostej>
On Fri, Sep 9, 2016 at 9:31 AM, Mark Rutland <mark.rutland@arm.com> wrote:
> On Thu, Sep 08, 2016 at 01:51:24PM +0100, Catalin Marinas wrote:
>> On Wed, Sep 07, 2016 at 04:20:55PM -0700, Kees Cook wrote:
>> > On Fri, Sep 2, 2016 at 8:02 AM, Catalin Marinas <catalin.marinas@arm.com> wrote:
>> > > This is the second version of the arm64 PAN emulation by disabling
>> > > TTBR0_EL1 accesses. The major change from v1 is the use of a thread_info
>> > > member to store the real TTBR0_EL1 value. The advantage is slightly
>> > > simpler assembler macros for uaccess_enable with the downside that
>> > > switch_mm() must always update the saved ttbr0 even if there is no mm
>> > > switch.
>> >
>> > Is arm64 thread_info attached to the kernel stack? (i.e. is this
>> > introducing a valuable target for stack-based attacks?)
>>
>> Currently yes, thread_info is on the kernel stack. At some point we'll
>> decouple it in a similar way to what x86 are doing/planning.
>
> FWIW, I'm currently working on this (atop of Andy's x86 patches). The
> IRQ stack work largely removed out dependence on the stack pointer to
> find thread_info, and I have a plan for the remaining places.
>
> There's a fair amount of ground work to do first (e.g. reworking headers
> to avoid circular dependencies), but hopefully I'll have something that
> I can share soon.
Fantastic! Thanks for the heads-up. :)
-Kees
--
Kees Cook
Nexus Security
WARNING: multiple messages have this Message-ID (diff)
From: Kees Cook <keescook@chromium.org>
To: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
"kernel-hardening@lists.openwall.com"
<kernel-hardening@lists.openwall.com>,
Will Deacon <will.deacon@arm.com>,
AKASHI Takahiro <takahiro.akashi@linaro.org>,
Julien Grall <julien.grall@arm.com>,
James Morse <james.morse@arm.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: [kernel-hardening] Re: [PATCH v2 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching
Date: Fri, 9 Sep 2016 11:24:30 -0700 [thread overview]
Message-ID: <CAGXu5jJMdym7jWv5P7YHdqu4eU7a3dzQqgXHppzOwRCYQ6O1Cg@mail.gmail.com> (raw)
In-Reply-To: <20160909163116.GA10792@leverpostej>
On Fri, Sep 9, 2016 at 9:31 AM, Mark Rutland <mark.rutland@arm.com> wrote:
> On Thu, Sep 08, 2016 at 01:51:24PM +0100, Catalin Marinas wrote:
>> On Wed, Sep 07, 2016 at 04:20:55PM -0700, Kees Cook wrote:
>> > On Fri, Sep 2, 2016 at 8:02 AM, Catalin Marinas <catalin.marinas@arm.com> wrote:
>> > > This is the second version of the arm64 PAN emulation by disabling
>> > > TTBR0_EL1 accesses. The major change from v1 is the use of a thread_info
>> > > member to store the real TTBR0_EL1 value. The advantage is slightly
>> > > simpler assembler macros for uaccess_enable with the downside that
>> > > switch_mm() must always update the saved ttbr0 even if there is no mm
>> > > switch.
>> >
>> > Is arm64 thread_info attached to the kernel stack? (i.e. is this
>> > introducing a valuable target for stack-based attacks?)
>>
>> Currently yes, thread_info is on the kernel stack. At some point we'll
>> decouple it in a similar way to what x86 are doing/planning.
>
> FWIW, I'm currently working on this (atop of Andy's x86 patches). The
> IRQ stack work largely removed out dependence on the stack pointer to
> find thread_info, and I have a plan for the remaining places.
>
> There's a fair amount of ground work to do first (e.g. reworking headers
> to avoid circular dependencies), but hopefully I'll have something that
> I can share soon.
Fantastic! Thanks for the heads-up. :)
-Kees
--
Kees Cook
Nexus Security
next prev parent reply other threads:[~2016-09-09 18:24 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-02 15:02 [PATCH v2 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching Catalin Marinas
2016-09-02 15:02 ` [kernel-hardening] " Catalin Marinas
2016-09-02 15:02 ` [PATCH v2 1/7] arm64: Factor out PAN enabling/disabling into separate uaccess_* macros Catalin Marinas
2016-09-02 15:02 ` [kernel-hardening] " Catalin Marinas
2016-09-05 15:38 ` Mark Rutland
2016-09-05 15:38 ` [kernel-hardening] " Mark Rutland
2016-09-12 14:52 ` Catalin Marinas
2016-09-12 14:52 ` [kernel-hardening] " Catalin Marinas
2016-09-12 15:09 ` Mark Rutland
2016-09-12 15:09 ` [kernel-hardening] " Mark Rutland
2016-09-12 16:26 ` Catalin Marinas
2016-09-12 16:26 ` [kernel-hardening] " Catalin Marinas
2016-09-02 15:02 ` [PATCH v2 2/7] arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro Catalin Marinas
2016-09-02 15:02 ` [kernel-hardening] " Catalin Marinas
2016-09-05 16:11 ` Mark Rutland
2016-09-05 16:11 ` [kernel-hardening] " Mark Rutland
2016-09-02 15:02 ` [PATCH v2 3/7] arm64: Introduce uaccess_{disable, enable} functionality based on TTBR0_EL1 Catalin Marinas
2016-09-02 15:02 ` [kernel-hardening] [PATCH v2 3/7] arm64: Introduce uaccess_{disable,enable} " Catalin Marinas
2016-09-05 17:20 ` [PATCH v2 3/7] arm64: Introduce uaccess_{disable, enable} " Mark Rutland
2016-09-05 17:20 ` [kernel-hardening] " Mark Rutland
2016-09-06 10:27 ` Catalin Marinas
2016-09-06 10:27 ` [kernel-hardening] " Catalin Marinas
2016-09-06 10:45 ` Mark Rutland
2016-09-06 10:45 ` [kernel-hardening] " Mark Rutland
2016-09-11 13:55 ` Ard Biesheuvel
2016-09-11 13:55 ` Ard Biesheuvel
2016-09-12 9:32 ` Catalin Marinas
2016-09-12 9:32 ` Catalin Marinas
2016-09-09 17:15 ` Catalin Marinas
2016-09-09 17:15 ` [kernel-hardening] " Catalin Marinas
2016-09-02 15:02 ` [PATCH v2 4/7] arm64: Disable TTBR0_EL1 during normal kernel execution Catalin Marinas
2016-09-02 15:02 ` [kernel-hardening] " Catalin Marinas
2016-09-06 17:31 ` Mark Rutland
2016-09-06 17:31 ` [kernel-hardening] " Mark Rutland
2016-09-02 15:02 ` [PATCH v2 5/7] arm64: Handle faults caused by inadvertent user access with PAN enabled Catalin Marinas
2016-09-02 15:02 ` [kernel-hardening] " Catalin Marinas
2016-09-02 15:02 ` [PATCH v2 6/7] arm64: xen: Enable user access before a privcmd hvc call Catalin Marinas
2016-09-02 15:02 ` [kernel-hardening] " Catalin Marinas
2016-09-02 15:02 ` [PATCH v2 7/7] arm64: Enable CONFIG_ARM64_TTBR0_PAN Catalin Marinas
2016-09-02 15:02 ` [kernel-hardening] " Catalin Marinas
2016-09-02 15:47 ` Mark Rutland
2016-09-02 15:47 ` [kernel-hardening] " Mark Rutland
2016-09-07 23:20 ` [PATCH v2 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching Kees Cook
2016-09-07 23:20 ` [kernel-hardening] " Kees Cook
2016-09-08 12:51 ` Catalin Marinas
2016-09-08 12:51 ` [kernel-hardening] " Catalin Marinas
2016-09-08 15:50 ` Kees Cook
2016-09-08 15:50 ` [kernel-hardening] " Kees Cook
2016-09-09 16:31 ` Mark Rutland
2016-09-09 16:31 ` [kernel-hardening] " Mark Rutland
2016-09-09 18:24 ` Kees Cook [this message]
2016-09-09 18:24 ` Kees Cook
2016-09-09 23:40 ` [kernel-hardening] " David Brown
2016-09-09 23:40 ` David Brown
2016-09-10 9:51 ` Catalin Marinas
2016-09-10 9:51 ` [kernel-hardening] " Catalin Marinas
2016-09-10 10:56 ` Ard Biesheuvel
2016-09-10 10:56 ` [kernel-hardening] " Ard Biesheuvel
2016-09-11 12:16 ` Catalin Marinas
2016-09-11 12:16 ` [kernel-hardening] " Catalin Marinas
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