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From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [kernel-hardening] Re: [PATCH v2 3/7] arm64: Introduce uaccess_{disable, enable} functionality based on TTBR0_EL1
Date: Mon, 12 Sep 2016 10:32:49 +0100	[thread overview]
Message-ID: <20160912093249.GA2492@e104818-lin.cambridge.arm.com> (raw)
In-Reply-To: <CAKv+Gu8GMU=Lgh4awFLda-7K=orpg03D18kPDVVQEP6KzB5++g@mail.gmail.com>

On Sun, Sep 11, 2016 at 02:55:12PM +0100, Ard Biesheuvel wrote:
> On 6 September 2016 at 11:45, Mark Rutland <mark.rutland@arm.com> wrote:
> > On Tue, Sep 06, 2016 at 11:27:42AM +0100, Catalin Marinas wrote:
> >> On Mon, Sep 05, 2016 at 06:20:38PM +0100, Mark Rutland wrote:
> >> > On Fri, Sep 02, 2016 at 04:02:09PM +0100, Catalin Marinas wrote:
> >> > >    * tables again to remove any speculatively loaded cache lines.
> >> > >    */
> >> > >   mov     x0, x25
> >> > > - add     x1, x26, #SWAPPER_DIR_SIZE
> >> > > + add     x1, x26, #SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE
> >> > >   dmb     sy
> >> > >   bl      __inval_cache_range
> >> > >
> >> > > diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
> >> > > index 659963d40bb4..fe393ccf9352 100644
> >> > > --- a/arch/arm64/kernel/vmlinux.lds.S
> >> > > +++ b/arch/arm64/kernel/vmlinux.lds.S
> >> > > @@ -196,6 +196,11 @@ SECTIONS
> >> > >   swapper_pg_dir = .;
> >> > >   . += SWAPPER_DIR_SIZE;
> >> > >
> >> > > +#ifdef CONFIG_ARM64_TTBR0_PAN
> >> > > + reserved_ttbr0 = .;
> >> > > + . += PAGE_SIZE;
> >> > > +#endif
> >> >
> >> > Surely RESERVED_TTBR0_SIZE, as elsewhere?
> >>
> >> I'll try to move it somewhere where it can be included in vmlinux.lds.S
> >> (I can probably include cpufeature.h directly).
> 
> Do we really need another zero page? The ordinary zero page is already
> statically allocated these days, so we could simply move it between
> idmap_pg_dir[] and swapper_pg_dir[], and get all the changes in the
> early boot code for free (given that it covers the range between the
> start of idmap_pg_dir[] and the end of swapper_pg_dir[])
> 
> That way, we could refer to __pa(empty_zero_page) anywhere by reading
> ttbr1_el1 and subtracting PAGE_SIZE

That's fine by me. I'll cherry-pick your patch and rebase this series on
top.

-- 
Catalin

WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: kernel-hardening@lists.openwall.com,
	Kees Cook <keescook@chromium.org>,
	Will Deacon <will.deacon@arm.com>,
	AKASHI Takahiro <takahiro.akashi@linaro.org>,
	James Morse <james.morse@arm.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [kernel-hardening] Re: [PATCH v2 3/7] arm64: Introduce uaccess_{disable, enable} functionality based on TTBR0_EL1
Date: Mon, 12 Sep 2016 10:32:49 +0100	[thread overview]
Message-ID: <20160912093249.GA2492@e104818-lin.cambridge.arm.com> (raw)
In-Reply-To: <CAKv+Gu8GMU=Lgh4awFLda-7K=orpg03D18kPDVVQEP6KzB5++g@mail.gmail.com>

On Sun, Sep 11, 2016 at 02:55:12PM +0100, Ard Biesheuvel wrote:
> On 6 September 2016 at 11:45, Mark Rutland <mark.rutland@arm.com> wrote:
> > On Tue, Sep 06, 2016 at 11:27:42AM +0100, Catalin Marinas wrote:
> >> On Mon, Sep 05, 2016 at 06:20:38PM +0100, Mark Rutland wrote:
> >> > On Fri, Sep 02, 2016 at 04:02:09PM +0100, Catalin Marinas wrote:
> >> > >    * tables again to remove any speculatively loaded cache lines.
> >> > >    */
> >> > >   mov     x0, x25
> >> > > - add     x1, x26, #SWAPPER_DIR_SIZE
> >> > > + add     x1, x26, #SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE
> >> > >   dmb     sy
> >> > >   bl      __inval_cache_range
> >> > >
> >> > > diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
> >> > > index 659963d40bb4..fe393ccf9352 100644
> >> > > --- a/arch/arm64/kernel/vmlinux.lds.S
> >> > > +++ b/arch/arm64/kernel/vmlinux.lds.S
> >> > > @@ -196,6 +196,11 @@ SECTIONS
> >> > >   swapper_pg_dir = .;
> >> > >   . += SWAPPER_DIR_SIZE;
> >> > >
> >> > > +#ifdef CONFIG_ARM64_TTBR0_PAN
> >> > > + reserved_ttbr0 = .;
> >> > > + . += PAGE_SIZE;
> >> > > +#endif
> >> >
> >> > Surely RESERVED_TTBR0_SIZE, as elsewhere?
> >>
> >> I'll try to move it somewhere where it can be included in vmlinux.lds.S
> >> (I can probably include cpufeature.h directly).
> 
> Do we really need another zero page? The ordinary zero page is already
> statically allocated these days, so we could simply move it between
> idmap_pg_dir[] and swapper_pg_dir[], and get all the changes in the
> early boot code for free (given that it covers the range between the
> start of idmap_pg_dir[] and the end of swapper_pg_dir[])
> 
> That way, we could refer to __pa(empty_zero_page) anywhere by reading
> ttbr1_el1 and subtracting PAGE_SIZE

That's fine by me. I'll cherry-pick your patch and rebase this series on
top.

-- 
Catalin

  reply	other threads:[~2016-09-12  9:32 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-02 15:02 [PATCH v2 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching Catalin Marinas
2016-09-02 15:02 ` [kernel-hardening] " Catalin Marinas
2016-09-02 15:02 ` [PATCH v2 1/7] arm64: Factor out PAN enabling/disabling into separate uaccess_* macros Catalin Marinas
2016-09-02 15:02   ` [kernel-hardening] " Catalin Marinas
2016-09-05 15:38   ` Mark Rutland
2016-09-05 15:38     ` [kernel-hardening] " Mark Rutland
2016-09-12 14:52     ` Catalin Marinas
2016-09-12 14:52       ` [kernel-hardening] " Catalin Marinas
2016-09-12 15:09       ` Mark Rutland
2016-09-12 15:09         ` [kernel-hardening] " Mark Rutland
2016-09-12 16:26         ` Catalin Marinas
2016-09-12 16:26           ` [kernel-hardening] " Catalin Marinas
2016-09-02 15:02 ` [PATCH v2 2/7] arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro Catalin Marinas
2016-09-02 15:02   ` [kernel-hardening] " Catalin Marinas
2016-09-05 16:11   ` Mark Rutland
2016-09-05 16:11     ` [kernel-hardening] " Mark Rutland
2016-09-02 15:02 ` [PATCH v2 3/7] arm64: Introduce uaccess_{disable, enable} functionality based on TTBR0_EL1 Catalin Marinas
2016-09-02 15:02   ` [kernel-hardening] [PATCH v2 3/7] arm64: Introduce uaccess_{disable,enable} " Catalin Marinas
2016-09-05 17:20   ` [PATCH v2 3/7] arm64: Introduce uaccess_{disable, enable} " Mark Rutland
2016-09-05 17:20     ` [kernel-hardening] " Mark Rutland
2016-09-06 10:27     ` Catalin Marinas
2016-09-06 10:27       ` [kernel-hardening] " Catalin Marinas
2016-09-06 10:45       ` Mark Rutland
2016-09-06 10:45         ` [kernel-hardening] " Mark Rutland
2016-09-11 13:55         ` Ard Biesheuvel
2016-09-11 13:55           ` Ard Biesheuvel
2016-09-12  9:32           ` Catalin Marinas [this message]
2016-09-12  9:32             ` Catalin Marinas
2016-09-09 17:15   ` Catalin Marinas
2016-09-09 17:15     ` [kernel-hardening] " Catalin Marinas
2016-09-02 15:02 ` [PATCH v2 4/7] arm64: Disable TTBR0_EL1 during normal kernel execution Catalin Marinas
2016-09-02 15:02   ` [kernel-hardening] " Catalin Marinas
2016-09-06 17:31   ` Mark Rutland
2016-09-06 17:31     ` [kernel-hardening] " Mark Rutland
2016-09-02 15:02 ` [PATCH v2 5/7] arm64: Handle faults caused by inadvertent user access with PAN enabled Catalin Marinas
2016-09-02 15:02   ` [kernel-hardening] " Catalin Marinas
2016-09-02 15:02 ` [PATCH v2 6/7] arm64: xen: Enable user access before a privcmd hvc call Catalin Marinas
2016-09-02 15:02   ` [kernel-hardening] " Catalin Marinas
2016-09-02 15:02 ` [PATCH v2 7/7] arm64: Enable CONFIG_ARM64_TTBR0_PAN Catalin Marinas
2016-09-02 15:02   ` [kernel-hardening] " Catalin Marinas
2016-09-02 15:47   ` Mark Rutland
2016-09-02 15:47     ` [kernel-hardening] " Mark Rutland
2016-09-07 23:20 ` [PATCH v2 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching Kees Cook
2016-09-07 23:20   ` [kernel-hardening] " Kees Cook
2016-09-08 12:51   ` Catalin Marinas
2016-09-08 12:51     ` [kernel-hardening] " Catalin Marinas
2016-09-08 15:50     ` Kees Cook
2016-09-08 15:50       ` [kernel-hardening] " Kees Cook
2016-09-09 16:31     ` Mark Rutland
2016-09-09 16:31       ` [kernel-hardening] " Mark Rutland
2016-09-09 18:24       ` Kees Cook
2016-09-09 18:24         ` [kernel-hardening] " Kees Cook
2016-09-09 23:40 ` [kernel-hardening] " David Brown
2016-09-09 23:40   ` David Brown
2016-09-10  9:51 ` Catalin Marinas
2016-09-10  9:51   ` [kernel-hardening] " Catalin Marinas
2016-09-10 10:56   ` Ard Biesheuvel
2016-09-10 10:56     ` [kernel-hardening] " Ard Biesheuvel
2016-09-11 12:16     ` Catalin Marinas
2016-09-11 12:16       ` [kernel-hardening] " Catalin Marinas

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