From: "Pali Rohár" <pali@kernel.org> To: "Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>, "Bjorn Helgaas" <bhelgaas@google.com>, "Rob Herring" <robh+dt@kernel.org>, "Thomas Petazzoni" <thomas.petazzoni@bootlin.com>, "Krzysztof Wilczyński" <kw@linux.com>, "Marek Behún" <kabel@kernel.org>, "Russell King" <rmk+kernel@armlinux.org.uk> Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 05/11] PCI: mvebu: Correctly configure x1/x4 mode Date: Wed, 5 Jan 2022 16:02:33 +0100 [thread overview] Message-ID: <20220105150239.9628-6-pali@kernel.org> (raw) In-Reply-To: <20220105150239.9628-1-pali@kernel.org> If x1/x4 mode is not set correctly then link with endpoint card is not established. Use DTS property 'num-lanes' to deteriminate x1/x4 mode. Signed-off-by: Pali Rohár <pali@kernel.org> --- drivers/pci/controller/pci-mvebu.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index a075ba26cff1..0f2ec0a17874 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -93,6 +93,7 @@ struct mvebu_pcie_port { void __iomem *base; u32 port; u32 lane; + bool is_x4; int devfn; unsigned int mem_target; unsigned int mem_attr; @@ -233,13 +234,25 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) { - u32 ctrl, cmd, dev_rev, mask; + u32 ctrl, lnkcap, cmd, dev_rev, mask; /* Setup PCIe controller to Root Complex mode. */ ctrl = mvebu_readl(port, PCIE_CTRL_OFF); ctrl |= PCIE_CTRL_RC_MODE; mvebu_writel(port, ctrl, PCIE_CTRL_OFF); + /* + * Set Maximum Link Width to X1 or X4 in Root Port's PCIe Link + * Capability register. This register is defined by PCIe specification + * as read-only but this mvebu controller has it as read-write and must + * be set to number of SerDes PCIe lanes (1 or 4). If this register is + * not set correctly then link with endpoint card is not established. + */ + lnkcap = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP); + lnkcap &= ~PCI_EXP_LNKCAP_MLW; + lnkcap |= (port->is_x4 ? 4 : 1) << 4; + mvebu_writel(port, lnkcap, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP); + /* Disable Root Bridge I/O space, memory space and bus mastering. */ cmd = mvebu_readl(port, PCIE_CMD_OFF); cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); @@ -986,6 +999,7 @@ static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie, struct device *dev = &pcie->pdev->dev; enum of_gpio_flags flags; int reset_gpio, ret; + u32 num_lanes; port->pcie = pcie; @@ -998,6 +1012,9 @@ static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie, if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane)) port->lane = 0; + if (!of_property_read_u32(child, "num-lanes", &num_lanes) && num_lanes == 4) + port->is_x4 = true; + port->name = devm_kasprintf(dev, GFP_KERNEL, "pcie%d.%d", port->port, port->lane); if (!port->name) { -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: "Pali Rohár" <pali@kernel.org> To: "Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>, "Bjorn Helgaas" <bhelgaas@google.com>, "Rob Herring" <robh+dt@kernel.org>, "Thomas Petazzoni" <thomas.petazzoni@bootlin.com>, "Krzysztof Wilczyński" <kw@linux.com>, "Marek Behún" <kabel@kernel.org>, "Russell King" <rmk+kernel@armlinux.org.uk> Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 05/11] PCI: mvebu: Correctly configure x1/x4 mode Date: Wed, 5 Jan 2022 16:02:33 +0100 [thread overview] Message-ID: <20220105150239.9628-6-pali@kernel.org> (raw) In-Reply-To: <20220105150239.9628-1-pali@kernel.org> If x1/x4 mode is not set correctly then link with endpoint card is not established. Use DTS property 'num-lanes' to deteriminate x1/x4 mode. Signed-off-by: Pali Rohár <pali@kernel.org> --- drivers/pci/controller/pci-mvebu.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index a075ba26cff1..0f2ec0a17874 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -93,6 +93,7 @@ struct mvebu_pcie_port { void __iomem *base; u32 port; u32 lane; + bool is_x4; int devfn; unsigned int mem_target; unsigned int mem_attr; @@ -233,13 +234,25 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) { - u32 ctrl, cmd, dev_rev, mask; + u32 ctrl, lnkcap, cmd, dev_rev, mask; /* Setup PCIe controller to Root Complex mode. */ ctrl = mvebu_readl(port, PCIE_CTRL_OFF); ctrl |= PCIE_CTRL_RC_MODE; mvebu_writel(port, ctrl, PCIE_CTRL_OFF); + /* + * Set Maximum Link Width to X1 or X4 in Root Port's PCIe Link + * Capability register. This register is defined by PCIe specification + * as read-only but this mvebu controller has it as read-write and must + * be set to number of SerDes PCIe lanes (1 or 4). If this register is + * not set correctly then link with endpoint card is not established. + */ + lnkcap = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP); + lnkcap &= ~PCI_EXP_LNKCAP_MLW; + lnkcap |= (port->is_x4 ? 4 : 1) << 4; + mvebu_writel(port, lnkcap, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP); + /* Disable Root Bridge I/O space, memory space and bus mastering. */ cmd = mvebu_readl(port, PCIE_CMD_OFF); cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); @@ -986,6 +999,7 @@ static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie, struct device *dev = &pcie->pdev->dev; enum of_gpio_flags flags; int reset_gpio, ret; + u32 num_lanes; port->pcie = pcie; @@ -998,6 +1012,9 @@ static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie, if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane)) port->lane = 0; + if (!of_property_read_u32(child, "num-lanes", &num_lanes) && num_lanes == 4) + port->is_x4 = true; + port->name = devm_kasprintf(dev, GFP_KERNEL, "pcie%d.%d", port->port, port->lane); if (!port->name) { -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-01-05 15:04 UTC|newest] Thread overview: 130+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-05 15:02 [PATCH 00/11] PCI: mvebu: subsystem ids, AER and INTx Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-05 15:02 ` [PATCH 01/11] PCI: pci-bridge-emul: Re-arrange register tests Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-05 15:02 ` [PATCH 02/11] PCI: pci-bridge-emul: Add support for PCIe extended capabilities Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-05 15:02 ` [PATCH 03/11] PCI: pci-bridge-emul: Add support for PCI Bridge Subsystem Vendor ID capability Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-05 15:02 ` [PATCH 04/11] dt-bindings: PCI: mvebu: Add num-lanes property Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-12 1:29 ` Rob Herring 2022-01-12 1:29 ` Rob Herring 2022-01-05 15:02 ` Pali Rohár [this message] 2022-01-05 15:02 ` [PATCH 05/11] PCI: mvebu: Correctly configure x1/x4 mode Pali Rohár 2022-01-05 15:02 ` [PATCH 06/11] PCI: mvebu: Add support for PCI Bridge Subsystem Vendor ID on emulated bridge Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-05 15:02 ` [PATCH 07/11] PCI: mvebu: Add support for Advanced Error Reporting registers " Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-05 15:02 ` [PATCH 08/11] PCI: mvebu: Use child_ops API Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-05 15:41 ` Rob Herring 2022-01-05 15:41 ` Rob Herring 2022-01-05 15:49 ` Pali Rohár 2022-01-05 15:49 ` Pali Rohár 2022-01-12 1:43 ` Pali Rohár 2022-01-12 1:43 ` Pali Rohár 2022-01-12 14:53 ` Rob Herring 2022-01-12 14:53 ` Rob Herring 2022-01-05 15:02 ` [PATCH 09/11] dt-bindings: PCI: mvebu: Update information about intx interrupts Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-12 1:30 ` Rob Herring 2022-01-12 1:30 ` Rob Herring 2022-01-05 15:02 ` [PATCH 10/11] PCI: mvebu: Implement support for legacy INTx interrupts Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-06 15:28 ` Marc Zyngier 2022-01-06 15:28 ` Marc Zyngier 2022-01-06 15:44 ` Pali Rohár 2022-01-06 15:44 ` Pali Rohár 2022-01-06 15:55 ` Marc Zyngier 2022-01-06 15:55 ` Marc Zyngier 2022-01-06 16:20 ` Pali Rohár 2022-01-06 16:20 ` Pali Rohár 2022-01-06 16:27 ` Marc Zyngier 2022-01-06 16:27 ` Marc Zyngier 2022-01-06 17:20 ` Marek Behún 2022-01-06 17:20 ` Marek Behún 2022-01-06 17:31 ` Marc Zyngier 2022-01-06 17:31 ` Marc Zyngier 2022-01-07 11:50 ` Pali Rohár 2022-01-07 11:50 ` Pali Rohár 2022-01-07 18:53 ` Marc Zyngier 2022-01-07 18:53 ` Marc Zyngier 2022-01-05 15:02 ` [PATCH 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe " Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-12 15:18 ` [PATCH v2 00/11] PCI: mvebu: subsystem ids, AER and INTx Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-01-12 15:18 ` [PATCH v2 01/11] PCI: pci-bridge-emul: Re-arrange register tests Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-01-12 15:18 ` [PATCH v2 02/11] PCI: pci-bridge-emul: Add support for PCIe extended capabilities Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-01-12 15:18 ` [PATCH v2 03/11] PCI: pci-bridge-emul: Add support for PCI Bridge Subsystem Vendor ID capability Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-01-12 15:18 ` [PATCH v2 04/11] dt-bindings: PCI: mvebu: Add num-lanes property Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-01-12 15:18 ` [PATCH v2 05/11] PCI: mvebu: Correctly configure x1/x4 mode Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-01-20 17:09 ` Rob Herring 2022-01-20 17:09 ` Rob Herring 2022-01-20 17:19 ` Pali Rohár 2022-01-20 17:19 ` Pali Rohár 2022-01-12 15:18 ` [PATCH v2 06/11] PCI: mvebu: Add support for PCI Bridge Subsystem Vendor ID on emulated bridge Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-01-12 15:18 ` [PATCH v2 07/11] PCI: mvebu: Add support for Advanced Error Reporting registers " Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-01-12 15:18 ` [PATCH v2 08/11] PCI: mvebu: Use child_ops API Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-01-20 16:49 ` Rob Herring 2022-01-20 16:49 ` Rob Herring 2022-01-20 16:55 ` Pali Rohár 2022-01-20 16:55 ` Pali Rohár 2022-01-20 18:40 ` Rob Herring 2022-01-20 18:40 ` Rob Herring 2022-01-12 15:18 ` [PATCH v2 09/11] dt-bindings: PCI: mvebu: Update information about intx interrupts Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-01-12 15:36 ` Marek Behún 2022-01-12 15:36 ` Marek Behún 2022-01-12 15:18 ` [PATCH v2 10/11] PCI: mvebu: Implement support for legacy INTx interrupts Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-02-11 17:19 ` Lorenzo Pieralisi 2022-02-11 17:19 ` Lorenzo Pieralisi 2022-02-11 17:52 ` Pali Rohár 2022-02-11 17:52 ` Pali Rohár 2022-02-11 18:21 ` Lorenzo Pieralisi 2022-02-11 18:21 ` Lorenzo Pieralisi 2022-02-12 10:59 ` Marc Zyngier 2022-02-12 10:59 ` Marc Zyngier 2022-02-16 23:40 ` Pali Rohár 2022-02-16 23:40 ` Pali Rohár 2022-02-22 10:21 ` Lorenzo Pieralisi 2022-02-22 10:21 ` Lorenzo Pieralisi 2022-02-22 10:51 ` Pali Rohár 2022-02-22 10:51 ` Pali Rohár 2022-02-22 15:24 ` Lorenzo Pieralisi 2022-02-22 15:24 ` Lorenzo Pieralisi 2022-02-22 15:42 ` Pali Rohár 2022-02-22 15:42 ` Pali Rohár 2022-02-22 15:45 ` Lorenzo Pieralisi 2022-02-22 15:45 ` Lorenzo Pieralisi 2022-02-22 15:55 ` Pali Rohár 2022-02-22 15:55 ` Pali Rohár 2022-01-12 15:18 ` [PATCH v2 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe " Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-02-14 15:07 ` Gregory CLEMENT 2022-02-14 15:07 ` Gregory CLEMENT 2022-02-14 15:09 ` Pali Rohár 2022-02-14 15:09 ` Pali Rohár 2022-02-14 15:26 ` Gregory CLEMENT 2022-02-14 15:26 ` Gregory CLEMENT [not found] ` <CAEzXK1qYKVk7QiSY_DwqkZ7WV6WU06WBtiqZx0JJCc+mOP-7Kg@mail.gmail.com> 2022-02-15 10:48 ` Luís Mendes 2022-02-15 10:48 ` Luís Mendes 2022-02-15 10:52 ` Pali Rohár 2022-02-15 10:52 ` Pali Rohár 2022-02-18 21:53 ` Luís Mendes 2022-02-18 21:53 ` Luís Mendes 2022-02-19 13:36 ` Pali Rohár 2022-02-19 13:36 ` Pali Rohár 2022-02-11 17:50 ` [PATCH 00/11] PCI: mvebu: subsystem ids, AER and INTx Lorenzo Pieralisi 2022-02-11 17:50 ` Lorenzo Pieralisi 2022-02-11 18:01 ` Pali Rohár 2022-02-11 18:01 ` Pali Rohár
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