From: "Pali Rohár" <pali@kernel.org> To: "Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>, "Bjorn Helgaas" <bhelgaas@google.com>, "Rob Herring" <robh+dt@kernel.org>, "Thomas Petazzoni" <thomas.petazzoni@bootlin.com>, "Krzysztof Wilczyński" <kw@linux.com>, "Marek Behún" <kabel@kernel.org>, "Russell King" <rmk+kernel@armlinux.org.uk> Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 04/11] dt-bindings: PCI: mvebu: Add num-lanes property Date: Wed, 12 Jan 2022 16:18:07 +0100 [thread overview] Message-ID: <20220112151814.24361-5-pali@kernel.org> (raw) In-Reply-To: <20220112151814.24361-1-pali@kernel.org> Controller driver needs to correctly configure PCIe link if it contains 1 or 4 SerDes PCIe lanes. Therefore add a new 'num-lanes' DT property for mvebu PCIe controller. Property 'num-lanes' seems to be de-facto standard way how number of lanes is specified in other PCIe controllers. Signed-off-by: Pali Rohár <pali@kernel.org> Acked-by: Rob Herring <robh@kernel.org> --- Documentation/devicetree/bindings/pci/mvebu-pci.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt index 6173af6885f8..24225852bce0 100644 --- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt +++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt @@ -77,6 +77,7 @@ and the following optional properties: - marvell,pcie-lane: the physical PCIe lane number, for ports having multiple lanes. If this property is not found, we assume that the value is 0. +- num-lanes: number of SerDes PCIe lanes for this link (1 or 4) - reset-gpios: optional GPIO to PERST# - reset-delay-us: delay in us to wait after reset de-assertion, if not specified will default to 100ms, as required by the PCIe specification. @@ -141,6 +142,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; + num-lanes = <1>; /* low-active PERST# reset on GPIO 25 */ reset-gpios = <&gpio0 25 1>; /* wait 20ms for device settle after reset deassertion */ @@ -161,6 +163,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 59>; marvell,pcie-port = <0>; marvell,pcie-lane = <1>; + num-lanes = <1>; clocks = <&gateclk 6>; }; @@ -177,6 +180,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 60>; marvell,pcie-port = <0>; marvell,pcie-lane = <2>; + num-lanes = <1>; clocks = <&gateclk 7>; }; @@ -193,6 +197,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 61>; marvell,pcie-port = <0>; marvell,pcie-lane = <3>; + num-lanes = <1>; clocks = <&gateclk 8>; }; @@ -209,6 +214,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 62>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; + num-lanes = <1>; clocks = <&gateclk 9>; }; @@ -225,6 +231,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 63>; marvell,pcie-port = <1>; marvell,pcie-lane = <1>; + num-lanes = <1>; clocks = <&gateclk 10>; }; @@ -241,6 +248,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 64>; marvell,pcie-port = <1>; marvell,pcie-lane = <2>; + num-lanes = <1>; clocks = <&gateclk 11>; }; @@ -257,6 +265,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 65>; marvell,pcie-port = <1>; marvell,pcie-lane = <3>; + num-lanes = <1>; clocks = <&gateclk 12>; }; @@ -273,6 +282,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 99>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; + num-lanes = <1>; clocks = <&gateclk 26>; }; @@ -289,6 +299,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 103>; marvell,pcie-port = <3>; marvell,pcie-lane = <0>; + num-lanes = <1>; clocks = <&gateclk 27>; }; }; -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: "Pali Rohár" <pali@kernel.org> To: "Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>, "Bjorn Helgaas" <bhelgaas@google.com>, "Rob Herring" <robh+dt@kernel.org>, "Thomas Petazzoni" <thomas.petazzoni@bootlin.com>, "Krzysztof Wilczyński" <kw@linux.com>, "Marek Behún" <kabel@kernel.org>, "Russell King" <rmk+kernel@armlinux.org.uk> Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 04/11] dt-bindings: PCI: mvebu: Add num-lanes property Date: Wed, 12 Jan 2022 16:18:07 +0100 [thread overview] Message-ID: <20220112151814.24361-5-pali@kernel.org> (raw) In-Reply-To: <20220112151814.24361-1-pali@kernel.org> Controller driver needs to correctly configure PCIe link if it contains 1 or 4 SerDes PCIe lanes. Therefore add a new 'num-lanes' DT property for mvebu PCIe controller. Property 'num-lanes' seems to be de-facto standard way how number of lanes is specified in other PCIe controllers. Signed-off-by: Pali Rohár <pali@kernel.org> Acked-by: Rob Herring <robh@kernel.org> --- Documentation/devicetree/bindings/pci/mvebu-pci.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt index 6173af6885f8..24225852bce0 100644 --- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt +++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt @@ -77,6 +77,7 @@ and the following optional properties: - marvell,pcie-lane: the physical PCIe lane number, for ports having multiple lanes. If this property is not found, we assume that the value is 0. +- num-lanes: number of SerDes PCIe lanes for this link (1 or 4) - reset-gpios: optional GPIO to PERST# - reset-delay-us: delay in us to wait after reset de-assertion, if not specified will default to 100ms, as required by the PCIe specification. @@ -141,6 +142,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; + num-lanes = <1>; /* low-active PERST# reset on GPIO 25 */ reset-gpios = <&gpio0 25 1>; /* wait 20ms for device settle after reset deassertion */ @@ -161,6 +163,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 59>; marvell,pcie-port = <0>; marvell,pcie-lane = <1>; + num-lanes = <1>; clocks = <&gateclk 6>; }; @@ -177,6 +180,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 60>; marvell,pcie-port = <0>; marvell,pcie-lane = <2>; + num-lanes = <1>; clocks = <&gateclk 7>; }; @@ -193,6 +197,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 61>; marvell,pcie-port = <0>; marvell,pcie-lane = <3>; + num-lanes = <1>; clocks = <&gateclk 8>; }; @@ -209,6 +214,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 62>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; + num-lanes = <1>; clocks = <&gateclk 9>; }; @@ -225,6 +231,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 63>; marvell,pcie-port = <1>; marvell,pcie-lane = <1>; + num-lanes = <1>; clocks = <&gateclk 10>; }; @@ -241,6 +248,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 64>; marvell,pcie-port = <1>; marvell,pcie-lane = <2>; + num-lanes = <1>; clocks = <&gateclk 11>; }; @@ -257,6 +265,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 65>; marvell,pcie-port = <1>; marvell,pcie-lane = <3>; + num-lanes = <1>; clocks = <&gateclk 12>; }; @@ -273,6 +282,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 99>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; + num-lanes = <1>; clocks = <&gateclk 26>; }; @@ -289,6 +299,7 @@ pcie-controller { interrupt-map = <0 0 0 0 &mpic 103>; marvell,pcie-port = <3>; marvell,pcie-lane = <0>; + num-lanes = <1>; clocks = <&gateclk 27>; }; }; -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-01-12 15:18 UTC|newest] Thread overview: 130+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-05 15:02 [PATCH 00/11] PCI: mvebu: subsystem ids, AER and INTx Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-05 15:02 ` [PATCH 01/11] PCI: pci-bridge-emul: Re-arrange register tests Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-05 15:02 ` [PATCH 02/11] PCI: pci-bridge-emul: Add support for PCIe extended capabilities Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-05 15:02 ` [PATCH 03/11] PCI: pci-bridge-emul: Add support for PCI Bridge Subsystem Vendor ID capability Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-05 15:02 ` [PATCH 04/11] dt-bindings: PCI: mvebu: Add num-lanes property Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-12 1:29 ` Rob Herring 2022-01-12 1:29 ` Rob Herring 2022-01-05 15:02 ` [PATCH 05/11] PCI: mvebu: Correctly configure x1/x4 mode Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-05 15:02 ` [PATCH 06/11] PCI: mvebu: Add support for PCI Bridge Subsystem Vendor ID on emulated bridge Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-05 15:02 ` [PATCH 07/11] PCI: mvebu: Add support for Advanced Error Reporting registers " Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-05 15:02 ` [PATCH 08/11] PCI: mvebu: Use child_ops API Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-05 15:41 ` Rob Herring 2022-01-05 15:41 ` Rob Herring 2022-01-05 15:49 ` Pali Rohár 2022-01-05 15:49 ` Pali Rohár 2022-01-12 1:43 ` Pali Rohár 2022-01-12 1:43 ` Pali Rohár 2022-01-12 14:53 ` Rob Herring 2022-01-12 14:53 ` Rob Herring 2022-01-05 15:02 ` [PATCH 09/11] dt-bindings: PCI: mvebu: Update information about intx interrupts Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-12 1:30 ` Rob Herring 2022-01-12 1:30 ` Rob Herring 2022-01-05 15:02 ` [PATCH 10/11] PCI: mvebu: Implement support for legacy INTx interrupts Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-06 15:28 ` Marc Zyngier 2022-01-06 15:28 ` Marc Zyngier 2022-01-06 15:44 ` Pali Rohár 2022-01-06 15:44 ` Pali Rohár 2022-01-06 15:55 ` Marc Zyngier 2022-01-06 15:55 ` Marc Zyngier 2022-01-06 16:20 ` Pali Rohár 2022-01-06 16:20 ` Pali Rohár 2022-01-06 16:27 ` Marc Zyngier 2022-01-06 16:27 ` Marc Zyngier 2022-01-06 17:20 ` Marek Behún 2022-01-06 17:20 ` Marek Behún 2022-01-06 17:31 ` Marc Zyngier 2022-01-06 17:31 ` Marc Zyngier 2022-01-07 11:50 ` Pali Rohár 2022-01-07 11:50 ` Pali Rohár 2022-01-07 18:53 ` Marc Zyngier 2022-01-07 18:53 ` Marc Zyngier 2022-01-05 15:02 ` [PATCH 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe " Pali Rohár 2022-01-05 15:02 ` Pali Rohár 2022-01-12 15:18 ` [PATCH v2 00/11] PCI: mvebu: subsystem ids, AER and INTx Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-01-12 15:18 ` [PATCH v2 01/11] PCI: pci-bridge-emul: Re-arrange register tests Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-01-12 15:18 ` [PATCH v2 02/11] PCI: pci-bridge-emul: Add support for PCIe extended capabilities Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-01-12 15:18 ` [PATCH v2 03/11] PCI: pci-bridge-emul: Add support for PCI Bridge Subsystem Vendor ID capability Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-01-12 15:18 ` Pali Rohár [this message] 2022-01-12 15:18 ` [PATCH v2 04/11] dt-bindings: PCI: mvebu: Add num-lanes property Pali Rohár 2022-01-12 15:18 ` [PATCH v2 05/11] PCI: mvebu: Correctly configure x1/x4 mode Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-01-20 17:09 ` Rob Herring 2022-01-20 17:09 ` Rob Herring 2022-01-20 17:19 ` Pali Rohár 2022-01-20 17:19 ` Pali Rohár 2022-01-12 15:18 ` [PATCH v2 06/11] PCI: mvebu: Add support for PCI Bridge Subsystem Vendor ID on emulated bridge Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-01-12 15:18 ` [PATCH v2 07/11] PCI: mvebu: Add support for Advanced Error Reporting registers " Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-01-12 15:18 ` [PATCH v2 08/11] PCI: mvebu: Use child_ops API Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-01-20 16:49 ` Rob Herring 2022-01-20 16:49 ` Rob Herring 2022-01-20 16:55 ` Pali Rohár 2022-01-20 16:55 ` Pali Rohár 2022-01-20 18:40 ` Rob Herring 2022-01-20 18:40 ` Rob Herring 2022-01-12 15:18 ` [PATCH v2 09/11] dt-bindings: PCI: mvebu: Update information about intx interrupts Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-01-12 15:36 ` Marek Behún 2022-01-12 15:36 ` Marek Behún 2022-01-12 15:18 ` [PATCH v2 10/11] PCI: mvebu: Implement support for legacy INTx interrupts Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-02-11 17:19 ` Lorenzo Pieralisi 2022-02-11 17:19 ` Lorenzo Pieralisi 2022-02-11 17:52 ` Pali Rohár 2022-02-11 17:52 ` Pali Rohár 2022-02-11 18:21 ` Lorenzo Pieralisi 2022-02-11 18:21 ` Lorenzo Pieralisi 2022-02-12 10:59 ` Marc Zyngier 2022-02-12 10:59 ` Marc Zyngier 2022-02-16 23:40 ` Pali Rohár 2022-02-16 23:40 ` Pali Rohár 2022-02-22 10:21 ` Lorenzo Pieralisi 2022-02-22 10:21 ` Lorenzo Pieralisi 2022-02-22 10:51 ` Pali Rohár 2022-02-22 10:51 ` Pali Rohár 2022-02-22 15:24 ` Lorenzo Pieralisi 2022-02-22 15:24 ` Lorenzo Pieralisi 2022-02-22 15:42 ` Pali Rohár 2022-02-22 15:42 ` Pali Rohár 2022-02-22 15:45 ` Lorenzo Pieralisi 2022-02-22 15:45 ` Lorenzo Pieralisi 2022-02-22 15:55 ` Pali Rohár 2022-02-22 15:55 ` Pali Rohár 2022-01-12 15:18 ` [PATCH v2 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe " Pali Rohár 2022-01-12 15:18 ` Pali Rohár 2022-02-14 15:07 ` Gregory CLEMENT 2022-02-14 15:07 ` Gregory CLEMENT 2022-02-14 15:09 ` Pali Rohár 2022-02-14 15:09 ` Pali Rohár 2022-02-14 15:26 ` Gregory CLEMENT 2022-02-14 15:26 ` Gregory CLEMENT [not found] ` <CAEzXK1qYKVk7QiSY_DwqkZ7WV6WU06WBtiqZx0JJCc+mOP-7Kg@mail.gmail.com> 2022-02-15 10:48 ` Luís Mendes 2022-02-15 10:48 ` Luís Mendes 2022-02-15 10:52 ` Pali Rohár 2022-02-15 10:52 ` Pali Rohár 2022-02-18 21:53 ` Luís Mendes 2022-02-18 21:53 ` Luís Mendes 2022-02-19 13:36 ` Pali Rohár 2022-02-19 13:36 ` Pali Rohár 2022-02-11 17:50 ` [PATCH 00/11] PCI: mvebu: subsystem ids, AER and INTx Lorenzo Pieralisi 2022-02-11 17:50 ` Lorenzo Pieralisi 2022-02-11 18:01 ` Pali Rohár 2022-02-11 18:01 ` Pali Rohár
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20220112151814.24361-5-pali@kernel.org \ --to=pali@kernel.org \ --cc=bhelgaas@google.com \ --cc=kabel@kernel.org \ --cc=kw@linux.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-pci@vger.kernel.org \ --cc=lorenzo.pieralisi@arm.com \ --cc=rmk+kernel@armlinux.org.uk \ --cc=robh+dt@kernel.org \ --cc=thomas.petazzoni@bootlin.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.