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From: "Luís Mendes" <luis.p.mendes@gmail.com>
To: "Pali Rohár" <pali@kernel.org>
Cc: "Gregory CLEMENT" <gregory.clement@bootlin.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Marek Behún" <kabel@kernel.org>,
	"Russell King" <rmk+kernel@armlinux.org.uk>,
	"Andrew Lunn" <andrew@lunn.ch>,
	"Linux PCI" <linux-pci@vger.kernel.org>,
	"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v2 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe legacy INTx interrupts
Date: Fri, 18 Feb 2022 21:53:43 +0000	[thread overview]
Message-ID: <CAEzXK1qbv+cuRqoNh9_JQK=ViDtO9a+2S9sRMr-o4dUvRnn4Uw@mail.gmail.com> (raw)
In-Reply-To: <20220215105214.f5biuptsruoredqi@pali>

Successfully tested on my custom A388 system with two PCI express slots.

If you wish you can add a:
Tested-by: Luis Mendes <luis.p.mendes@gmail.com>

On Tue, Feb 15, 2022 at 10:52 AM Pali Rohár <pali@kernel.org> wrote:
>
> Hello! armada-388.dtsi file has #include "armada-385.dtsi" line and
> therefore is already covered by this my patch.
>
> Gregory's question was about A380.
>
> But if you want, you can test this patch series (which already covers
> A388) on your A388 HW. It is still better to do tests on more HW.
>
> On Tuesday 15 February 2022 10:48:17 Luís Mendes wrote:
> > Hello,
> >
> > Sorry for jumping in the conversation, but I read this thread and I
> > have an Armada A388 HW so I can test it, if desired.
> >
> > Luís
> >
> >
> > On Tue, Feb 15, 2022 at 10:47 AM Luís Mendes <luis.p.mendes@gmail.com> wrote:
> > >
> > > Hello,
> > >
> > > Sorry for jumping in the conversation, but I read this thread and I have an Armada A388 HW so I can test it, if desired.
> > >
> > > Luís
> > >
> > > On Mon, Feb 14, 2022 at 7:57 PM Gregory CLEMENT <gregory.clement@bootlin.com> wrote:
> > >>
> > >> Hello,
> > >>
> > >> > On Monday 14 February 2022 16:07:13 Gregory CLEMENT wrote:
> > >> >> Hello Pali,
> > >> >>
> > >> >> > With this change legacy INTA, INTB, INTC and INTD interrupts are reported
> > >> >> > separately and not mixed into one Linux virq source anymore.
> > >> >> >
> > >> >> > Signed-off-by: Pali Rohár <pali@kernel.org>
> > >> >> > ---
> > >> >> >  arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++-----
> > >> >>
> > >> >> Is there any reason for not doing the same change in armada-380.dtsi ?
> > >> >
> > >> > I do not have A380 HW, so I did this change only for A385 which I have
> > >> > tested.
> > >>
> > >> OK fair enough.
> > >>
> > >> So you can add my
> > >> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> > >>
> > >> Moreover to keep biscetability  this patch should be merged after the
> > >> support in the driver. So the easier is to let merge it through the PCI
> > >> subsystem with the other patches from this series. I do not think there
> > >> will be any other changes in this file so there won't be any merge
> > >> conflicts.
> > >>
> > >> Thanks,
> > >>
> > >> Grégory
> > >>
> > >>
> > >> >
> > >> >> Grégory
> > >> >>
> > >> >> >  1 file changed, 44 insertions(+), 8 deletions(-)
> > >> >> >
> > >> >> > diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
> > >> >> > index f0022d10c715..83392b92dae2 100644
> > >> >> > --- a/arch/arm/boot/dts/armada-385.dtsi
> > >> >> > +++ b/arch/arm/boot/dts/armada-385.dtsi
> > >> >> > @@ -69,16 +69,25 @@
> > >> >> >                            reg = <0x0800 0 0 0 0>;
> > >> >> >                            #address-cells = <3>;
> > >> >> >                            #size-cells = <2>;
> > >> >> > +                          interrupt-names = "intx";
> > >> >> > +                          interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> > >> >> >                            #interrupt-cells = <1>;
> > >> >> >                            ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
> > >> >> >                                      0x81000000 0 0 0x81000000 0x1 0 1 0>;
> > >> >> >                            bus-range = <0x00 0xff>;
> > >> >> > -                          interrupt-map-mask = <0 0 0 0>;
> > >> >> > -                          interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> > >> >> > +                          interrupt-map-mask = <0 0 0 7>;
> > >> >> > +                          interrupt-map = <0 0 0 1 &pcie1_intc 0>,
> > >> >> > +                                          <0 0 0 2 &pcie1_intc 1>,
> > >> >> > +                                          <0 0 0 3 &pcie1_intc 2>,
> > >> >> > +                                          <0 0 0 4 &pcie1_intc 3>;
> > >> >> >                            marvell,pcie-port = <0>;
> > >> >> >                            marvell,pcie-lane = <0>;
> > >> >> >                            clocks = <&gateclk 8>;
> > >> >> >                            status = "disabled";
> > >> >> > +                          pcie1_intc: interrupt-controller {
> > >> >> > +                                  interrupt-controller;
> > >> >> > +                                  #interrupt-cells = <1>;
> > >> >> > +                          };
> > >> >> >                    };
> > >> >> >
> > >> >> >                    /* x1 port */
> > >> >> > @@ -88,16 +97,25 @@
> > >> >> >                            reg = <0x1000 0 0 0 0>;
> > >> >> >                            #address-cells = <3>;
> > >> >> >                            #size-cells = <2>;
> > >> >> > +                          interrupt-names = "intx";
> > >> >> > +                          interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> > >> >> >                            #interrupt-cells = <1>;
> > >> >> >                            ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
> > >> >> >                                      0x81000000 0 0 0x81000000 0x2 0 1 0>;
> > >> >> >                            bus-range = <0x00 0xff>;
> > >> >> > -                          interrupt-map-mask = <0 0 0 0>;
> > >> >> > -                          interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> > >> >> > +                          interrupt-map-mask = <0 0 0 7>;
> > >> >> > +                          interrupt-map = <0 0 0 1 &pcie2_intc 0>,
> > >> >> > +                                          <0 0 0 2 &pcie2_intc 1>,
> > >> >> > +                                          <0 0 0 3 &pcie2_intc 2>,
> > >> >> > +                                          <0 0 0 4 &pcie2_intc 3>;
> > >> >> >                            marvell,pcie-port = <1>;
> > >> >> >                            marvell,pcie-lane = <0>;
> > >> >> >                            clocks = <&gateclk 5>;
> > >> >> >                            status = "disabled";
> > >> >> > +                          pcie2_intc: interrupt-controller {
> > >> >> > +                                  interrupt-controller;
> > >> >> > +                                  #interrupt-cells = <1>;
> > >> >> > +                          };
> > >> >> >                    };
> > >> >> >
> > >> >> >                    /* x1 port */
> > >> >> > @@ -107,16 +125,25 @@
> > >> >> >                            reg = <0x1800 0 0 0 0>;
> > >> >> >                            #address-cells = <3>;
> > >> >> >                            #size-cells = <2>;
> > >> >> > +                          interrupt-names = "intx";
> > >> >> > +                          interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> > >> >> >                            #interrupt-cells = <1>;
> > >> >> >                            ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
> > >> >> >                                      0x81000000 0 0 0x81000000 0x3 0 1 0>;
> > >> >> >                            bus-range = <0x00 0xff>;
> > >> >> > -                          interrupt-map-mask = <0 0 0 0>;
> > >> >> > -                          interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> > >> >> > +                          interrupt-map-mask = <0 0 0 7>;
> > >> >> > +                          interrupt-map = <0 0 0 1 &pcie3_intc 0>,
> > >> >> > +                                          <0 0 0 2 &pcie3_intc 1>,
> > >> >> > +                                          <0 0 0 3 &pcie3_intc 2>,
> > >> >> > +                                          <0 0 0 4 &pcie3_intc 3>;
> > >> >> >                            marvell,pcie-port = <2>;
> > >> >> >                            marvell,pcie-lane = <0>;
> > >> >> >                            clocks = <&gateclk 6>;
> > >> >> >                            status = "disabled";
> > >> >> > +                          pcie3_intc: interrupt-controller {
> > >> >> > +                                  interrupt-controller;
> > >> >> > +                                  #interrupt-cells = <1>;
> > >> >> > +                          };
> > >> >> >                    };
> > >> >> >
> > >> >> >                    /*
> > >> >> > @@ -129,16 +156,25 @@
> > >> >> >                            reg = <0x2000 0 0 0 0>;
> > >> >> >                            #address-cells = <3>;
> > >> >> >                            #size-cells = <2>;
> > >> >> > +                          interrupt-names = "intx";
> > >> >> > +                          interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> > >> >> >                            #interrupt-cells = <1>;
> > >> >> >                            ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
> > >> >> >                                      0x81000000 0 0 0x81000000 0x4 0 1 0>;
> > >> >> >                            bus-range = <0x00 0xff>;
> > >> >> > -                          interrupt-map-mask = <0 0 0 0>;
> > >> >> > -                          interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> > >> >> > +                          interrupt-map-mask = <0 0 0 7>;
> > >> >> > +                          interrupt-map = <0 0 0 1 &pcie4_intc 0>,
> > >> >> > +                                          <0 0 0 2 &pcie4_intc 1>,
> > >> >> > +                                          <0 0 0 3 &pcie4_intc 2>,
> > >> >> > +                                          <0 0 0 4 &pcie4_intc 3>;
> > >> >> >                            marvell,pcie-port = <3>;
> > >> >> >                            marvell,pcie-lane = <0>;
> > >> >> >                            clocks = <&gateclk 7>;
> > >> >> >                            status = "disabled";
> > >> >> > +                          pcie4_intc: interrupt-controller {
> > >> >> > +                                  interrupt-controller;
> > >> >> > +                                  #interrupt-cells = <1>;
> > >> >> > +                          };
> > >> >> >                    };
> > >> >> >            };
> > >> >> >    };
> > >> >> > --
> > >> >> > 2.20.1
> > >> >> >
> > >> >>
> > >> >> --
> > >> >> Gregory Clement, Bootlin
> > >> >> Embedded Linux and Kernel engineering
> > >> >> http://bootlin.com
> > >>
> > >> --
> > >> Gregory Clement, Bootlin
> > >> Embedded Linux and Kernel engineering
> > >> http://bootlin.com

WARNING: multiple messages have this Message-ID (diff)
From: "Luís Mendes" <luis.p.mendes@gmail.com>
To: "Pali Rohár" <pali@kernel.org>
Cc: "Gregory CLEMENT" <gregory.clement@bootlin.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Marek Behún" <kabel@kernel.org>,
	"Russell King" <rmk+kernel@armlinux.org.uk>,
	"Andrew Lunn" <andrew@lunn.ch>,
	"Linux PCI" <linux-pci@vger.kernel.org>,
	"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v2 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe legacy INTx interrupts
Date: Fri, 18 Feb 2022 21:53:43 +0000	[thread overview]
Message-ID: <CAEzXK1qbv+cuRqoNh9_JQK=ViDtO9a+2S9sRMr-o4dUvRnn4Uw@mail.gmail.com> (raw)
In-Reply-To: <20220215105214.f5biuptsruoredqi@pali>

Successfully tested on my custom A388 system with two PCI express slots.

If you wish you can add a:
Tested-by: Luis Mendes <luis.p.mendes@gmail.com>

On Tue, Feb 15, 2022 at 10:52 AM Pali Rohár <pali@kernel.org> wrote:
>
> Hello! armada-388.dtsi file has #include "armada-385.dtsi" line and
> therefore is already covered by this my patch.
>
> Gregory's question was about A380.
>
> But if you want, you can test this patch series (which already covers
> A388) on your A388 HW. It is still better to do tests on more HW.
>
> On Tuesday 15 February 2022 10:48:17 Luís Mendes wrote:
> > Hello,
> >
> > Sorry for jumping in the conversation, but I read this thread and I
> > have an Armada A388 HW so I can test it, if desired.
> >
> > Luís
> >
> >
> > On Tue, Feb 15, 2022 at 10:47 AM Luís Mendes <luis.p.mendes@gmail.com> wrote:
> > >
> > > Hello,
> > >
> > > Sorry for jumping in the conversation, but I read this thread and I have an Armada A388 HW so I can test it, if desired.
> > >
> > > Luís
> > >
> > > On Mon, Feb 14, 2022 at 7:57 PM Gregory CLEMENT <gregory.clement@bootlin.com> wrote:
> > >>
> > >> Hello,
> > >>
> > >> > On Monday 14 February 2022 16:07:13 Gregory CLEMENT wrote:
> > >> >> Hello Pali,
> > >> >>
> > >> >> > With this change legacy INTA, INTB, INTC and INTD interrupts are reported
> > >> >> > separately and not mixed into one Linux virq source anymore.
> > >> >> >
> > >> >> > Signed-off-by: Pali Rohár <pali@kernel.org>
> > >> >> > ---
> > >> >> >  arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++-----
> > >> >>
> > >> >> Is there any reason for not doing the same change in armada-380.dtsi ?
> > >> >
> > >> > I do not have A380 HW, so I did this change only for A385 which I have
> > >> > tested.
> > >>
> > >> OK fair enough.
> > >>
> > >> So you can add my
> > >> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> > >>
> > >> Moreover to keep biscetability  this patch should be merged after the
> > >> support in the driver. So the easier is to let merge it through the PCI
> > >> subsystem with the other patches from this series. I do not think there
> > >> will be any other changes in this file so there won't be any merge
> > >> conflicts.
> > >>
> > >> Thanks,
> > >>
> > >> Grégory
> > >>
> > >>
> > >> >
> > >> >> Grégory
> > >> >>
> > >> >> >  1 file changed, 44 insertions(+), 8 deletions(-)
> > >> >> >
> > >> >> > diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
> > >> >> > index f0022d10c715..83392b92dae2 100644
> > >> >> > --- a/arch/arm/boot/dts/armada-385.dtsi
> > >> >> > +++ b/arch/arm/boot/dts/armada-385.dtsi
> > >> >> > @@ -69,16 +69,25 @@
> > >> >> >                            reg = <0x0800 0 0 0 0>;
> > >> >> >                            #address-cells = <3>;
> > >> >> >                            #size-cells = <2>;
> > >> >> > +                          interrupt-names = "intx";
> > >> >> > +                          interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> > >> >> >                            #interrupt-cells = <1>;
> > >> >> >                            ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
> > >> >> >                                      0x81000000 0 0 0x81000000 0x1 0 1 0>;
> > >> >> >                            bus-range = <0x00 0xff>;
> > >> >> > -                          interrupt-map-mask = <0 0 0 0>;
> > >> >> > -                          interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> > >> >> > +                          interrupt-map-mask = <0 0 0 7>;
> > >> >> > +                          interrupt-map = <0 0 0 1 &pcie1_intc 0>,
> > >> >> > +                                          <0 0 0 2 &pcie1_intc 1>,
> > >> >> > +                                          <0 0 0 3 &pcie1_intc 2>,
> > >> >> > +                                          <0 0 0 4 &pcie1_intc 3>;
> > >> >> >                            marvell,pcie-port = <0>;
> > >> >> >                            marvell,pcie-lane = <0>;
> > >> >> >                            clocks = <&gateclk 8>;
> > >> >> >                            status = "disabled";
> > >> >> > +                          pcie1_intc: interrupt-controller {
> > >> >> > +                                  interrupt-controller;
> > >> >> > +                                  #interrupt-cells = <1>;
> > >> >> > +                          };
> > >> >> >                    };
> > >> >> >
> > >> >> >                    /* x1 port */
> > >> >> > @@ -88,16 +97,25 @@
> > >> >> >                            reg = <0x1000 0 0 0 0>;
> > >> >> >                            #address-cells = <3>;
> > >> >> >                            #size-cells = <2>;
> > >> >> > +                          interrupt-names = "intx";
> > >> >> > +                          interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> > >> >> >                            #interrupt-cells = <1>;
> > >> >> >                            ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
> > >> >> >                                      0x81000000 0 0 0x81000000 0x2 0 1 0>;
> > >> >> >                            bus-range = <0x00 0xff>;
> > >> >> > -                          interrupt-map-mask = <0 0 0 0>;
> > >> >> > -                          interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> > >> >> > +                          interrupt-map-mask = <0 0 0 7>;
> > >> >> > +                          interrupt-map = <0 0 0 1 &pcie2_intc 0>,
> > >> >> > +                                          <0 0 0 2 &pcie2_intc 1>,
> > >> >> > +                                          <0 0 0 3 &pcie2_intc 2>,
> > >> >> > +                                          <0 0 0 4 &pcie2_intc 3>;
> > >> >> >                            marvell,pcie-port = <1>;
> > >> >> >                            marvell,pcie-lane = <0>;
> > >> >> >                            clocks = <&gateclk 5>;
> > >> >> >                            status = "disabled";
> > >> >> > +                          pcie2_intc: interrupt-controller {
> > >> >> > +                                  interrupt-controller;
> > >> >> > +                                  #interrupt-cells = <1>;
> > >> >> > +                          };
> > >> >> >                    };
> > >> >> >
> > >> >> >                    /* x1 port */
> > >> >> > @@ -107,16 +125,25 @@
> > >> >> >                            reg = <0x1800 0 0 0 0>;
> > >> >> >                            #address-cells = <3>;
> > >> >> >                            #size-cells = <2>;
> > >> >> > +                          interrupt-names = "intx";
> > >> >> > +                          interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> > >> >> >                            #interrupt-cells = <1>;
> > >> >> >                            ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
> > >> >> >                                      0x81000000 0 0 0x81000000 0x3 0 1 0>;
> > >> >> >                            bus-range = <0x00 0xff>;
> > >> >> > -                          interrupt-map-mask = <0 0 0 0>;
> > >> >> > -                          interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> > >> >> > +                          interrupt-map-mask = <0 0 0 7>;
> > >> >> > +                          interrupt-map = <0 0 0 1 &pcie3_intc 0>,
> > >> >> > +                                          <0 0 0 2 &pcie3_intc 1>,
> > >> >> > +                                          <0 0 0 3 &pcie3_intc 2>,
> > >> >> > +                                          <0 0 0 4 &pcie3_intc 3>;
> > >> >> >                            marvell,pcie-port = <2>;
> > >> >> >                            marvell,pcie-lane = <0>;
> > >> >> >                            clocks = <&gateclk 6>;
> > >> >> >                            status = "disabled";
> > >> >> > +                          pcie3_intc: interrupt-controller {
> > >> >> > +                                  interrupt-controller;
> > >> >> > +                                  #interrupt-cells = <1>;
> > >> >> > +                          };
> > >> >> >                    };
> > >> >> >
> > >> >> >                    /*
> > >> >> > @@ -129,16 +156,25 @@
> > >> >> >                            reg = <0x2000 0 0 0 0>;
> > >> >> >                            #address-cells = <3>;
> > >> >> >                            #size-cells = <2>;
> > >> >> > +                          interrupt-names = "intx";
> > >> >> > +                          interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> > >> >> >                            #interrupt-cells = <1>;
> > >> >> >                            ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
> > >> >> >                                      0x81000000 0 0 0x81000000 0x4 0 1 0>;
> > >> >> >                            bus-range = <0x00 0xff>;
> > >> >> > -                          interrupt-map-mask = <0 0 0 0>;
> > >> >> > -                          interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> > >> >> > +                          interrupt-map-mask = <0 0 0 7>;
> > >> >> > +                          interrupt-map = <0 0 0 1 &pcie4_intc 0>,
> > >> >> > +                                          <0 0 0 2 &pcie4_intc 1>,
> > >> >> > +                                          <0 0 0 3 &pcie4_intc 2>,
> > >> >> > +                                          <0 0 0 4 &pcie4_intc 3>;
> > >> >> >                            marvell,pcie-port = <3>;
> > >> >> >                            marvell,pcie-lane = <0>;
> > >> >> >                            clocks = <&gateclk 7>;
> > >> >> >                            status = "disabled";
> > >> >> > +                          pcie4_intc: interrupt-controller {
> > >> >> > +                                  interrupt-controller;
> > >> >> > +                                  #interrupt-cells = <1>;
> > >> >> > +                          };
> > >> >> >                    };
> > >> >> >            };
> > >> >> >    };
> > >> >> > --
> > >> >> > 2.20.1
> > >> >> >
> > >> >>
> > >> >> --
> > >> >> Gregory Clement, Bootlin
> > >> >> Embedded Linux and Kernel engineering
> > >> >> http://bootlin.com
> > >>
> > >> --
> > >> Gregory Clement, Bootlin
> > >> Embedded Linux and Kernel engineering
> > >> http://bootlin.com

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  reply	other threads:[~2022-02-18 21:54 UTC|newest]

Thread overview: 130+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-05 15:02 [PATCH 00/11] PCI: mvebu: subsystem ids, AER and INTx Pali Rohár
2022-01-05 15:02 ` Pali Rohár
2022-01-05 15:02 ` [PATCH 01/11] PCI: pci-bridge-emul: Re-arrange register tests Pali Rohár
2022-01-05 15:02   ` Pali Rohár
2022-01-05 15:02 ` [PATCH 02/11] PCI: pci-bridge-emul: Add support for PCIe extended capabilities Pali Rohár
2022-01-05 15:02   ` Pali Rohár
2022-01-05 15:02 ` [PATCH 03/11] PCI: pci-bridge-emul: Add support for PCI Bridge Subsystem Vendor ID capability Pali Rohár
2022-01-05 15:02   ` Pali Rohár
2022-01-05 15:02 ` [PATCH 04/11] dt-bindings: PCI: mvebu: Add num-lanes property Pali Rohár
2022-01-05 15:02   ` Pali Rohár
2022-01-12  1:29   ` Rob Herring
2022-01-12  1:29     ` Rob Herring
2022-01-05 15:02 ` [PATCH 05/11] PCI: mvebu: Correctly configure x1/x4 mode Pali Rohár
2022-01-05 15:02   ` Pali Rohár
2022-01-05 15:02 ` [PATCH 06/11] PCI: mvebu: Add support for PCI Bridge Subsystem Vendor ID on emulated bridge Pali Rohár
2022-01-05 15:02   ` Pali Rohár
2022-01-05 15:02 ` [PATCH 07/11] PCI: mvebu: Add support for Advanced Error Reporting registers " Pali Rohár
2022-01-05 15:02   ` Pali Rohár
2022-01-05 15:02 ` [PATCH 08/11] PCI: mvebu: Use child_ops API Pali Rohár
2022-01-05 15:02   ` Pali Rohár
2022-01-05 15:41   ` Rob Herring
2022-01-05 15:41     ` Rob Herring
2022-01-05 15:49     ` Pali Rohár
2022-01-05 15:49       ` Pali Rohár
2022-01-12  1:43     ` Pali Rohár
2022-01-12  1:43       ` Pali Rohár
2022-01-12 14:53       ` Rob Herring
2022-01-12 14:53         ` Rob Herring
2022-01-05 15:02 ` [PATCH 09/11] dt-bindings: PCI: mvebu: Update information about intx interrupts Pali Rohár
2022-01-05 15:02   ` Pali Rohár
2022-01-12  1:30   ` Rob Herring
2022-01-12  1:30     ` Rob Herring
2022-01-05 15:02 ` [PATCH 10/11] PCI: mvebu: Implement support for legacy INTx interrupts Pali Rohár
2022-01-05 15:02   ` Pali Rohár
2022-01-06 15:28   ` Marc Zyngier
2022-01-06 15:28     ` Marc Zyngier
2022-01-06 15:44     ` Pali Rohár
2022-01-06 15:44       ` Pali Rohár
2022-01-06 15:55       ` Marc Zyngier
2022-01-06 15:55         ` Marc Zyngier
2022-01-06 16:20         ` Pali Rohár
2022-01-06 16:20           ` Pali Rohár
2022-01-06 16:27           ` Marc Zyngier
2022-01-06 16:27             ` Marc Zyngier
2022-01-06 17:20             ` Marek Behún
2022-01-06 17:20               ` Marek Behún
2022-01-06 17:31               ` Marc Zyngier
2022-01-06 17:31                 ` Marc Zyngier
2022-01-07 11:50                 ` Pali Rohár
2022-01-07 11:50                   ` Pali Rohár
2022-01-07 18:53                   ` Marc Zyngier
2022-01-07 18:53                     ` Marc Zyngier
2022-01-05 15:02 ` [PATCH 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe " Pali Rohár
2022-01-05 15:02   ` Pali Rohár
2022-01-12 15:18 ` [PATCH v2 00/11] PCI: mvebu: subsystem ids, AER and INTx Pali Rohár
2022-01-12 15:18   ` Pali Rohár
2022-01-12 15:18   ` [PATCH v2 01/11] PCI: pci-bridge-emul: Re-arrange register tests Pali Rohár
2022-01-12 15:18     ` Pali Rohár
2022-01-12 15:18   ` [PATCH v2 02/11] PCI: pci-bridge-emul: Add support for PCIe extended capabilities Pali Rohár
2022-01-12 15:18     ` Pali Rohár
2022-01-12 15:18   ` [PATCH v2 03/11] PCI: pci-bridge-emul: Add support for PCI Bridge Subsystem Vendor ID capability Pali Rohár
2022-01-12 15:18     ` Pali Rohár
2022-01-12 15:18   ` [PATCH v2 04/11] dt-bindings: PCI: mvebu: Add num-lanes property Pali Rohár
2022-01-12 15:18     ` Pali Rohár
2022-01-12 15:18   ` [PATCH v2 05/11] PCI: mvebu: Correctly configure x1/x4 mode Pali Rohár
2022-01-12 15:18     ` Pali Rohár
2022-01-20 17:09     ` Rob Herring
2022-01-20 17:09       ` Rob Herring
2022-01-20 17:19       ` Pali Rohár
2022-01-20 17:19         ` Pali Rohár
2022-01-12 15:18   ` [PATCH v2 06/11] PCI: mvebu: Add support for PCI Bridge Subsystem Vendor ID on emulated bridge Pali Rohár
2022-01-12 15:18     ` Pali Rohár
2022-01-12 15:18   ` [PATCH v2 07/11] PCI: mvebu: Add support for Advanced Error Reporting registers " Pali Rohár
2022-01-12 15:18     ` Pali Rohár
2022-01-12 15:18   ` [PATCH v2 08/11] PCI: mvebu: Use child_ops API Pali Rohár
2022-01-12 15:18     ` Pali Rohár
2022-01-20 16:49     ` Rob Herring
2022-01-20 16:49       ` Rob Herring
2022-01-20 16:55       ` Pali Rohár
2022-01-20 16:55         ` Pali Rohár
2022-01-20 18:40         ` Rob Herring
2022-01-20 18:40           ` Rob Herring
2022-01-12 15:18   ` [PATCH v2 09/11] dt-bindings: PCI: mvebu: Update information about intx interrupts Pali Rohár
2022-01-12 15:18     ` Pali Rohár
2022-01-12 15:36     ` Marek Behún
2022-01-12 15:36       ` Marek Behún
2022-01-12 15:18   ` [PATCH v2 10/11] PCI: mvebu: Implement support for legacy INTx interrupts Pali Rohár
2022-01-12 15:18     ` Pali Rohár
2022-02-11 17:19     ` Lorenzo Pieralisi
2022-02-11 17:19       ` Lorenzo Pieralisi
2022-02-11 17:52       ` Pali Rohár
2022-02-11 17:52         ` Pali Rohár
2022-02-11 18:21         ` Lorenzo Pieralisi
2022-02-11 18:21           ` Lorenzo Pieralisi
2022-02-12 10:59           ` Marc Zyngier
2022-02-12 10:59             ` Marc Zyngier
2022-02-16 23:40         ` Pali Rohár
2022-02-16 23:40           ` Pali Rohár
2022-02-22 10:21           ` Lorenzo Pieralisi
2022-02-22 10:21             ` Lorenzo Pieralisi
2022-02-22 10:51             ` Pali Rohár
2022-02-22 10:51               ` Pali Rohár
2022-02-22 15:24               ` Lorenzo Pieralisi
2022-02-22 15:24                 ` Lorenzo Pieralisi
2022-02-22 15:42                 ` Pali Rohár
2022-02-22 15:42                   ` Pali Rohár
2022-02-22 15:45                   ` Lorenzo Pieralisi
2022-02-22 15:45                     ` Lorenzo Pieralisi
2022-02-22 15:55                     ` Pali Rohár
2022-02-22 15:55                       ` Pali Rohár
2022-01-12 15:18   ` [PATCH v2 11/11] ARM: dts: armada-385.dtsi: Add definitions for PCIe " Pali Rohár
2022-01-12 15:18     ` Pali Rohár
2022-02-14 15:07     ` Gregory CLEMENT
2022-02-14 15:07       ` Gregory CLEMENT
2022-02-14 15:09       ` Pali Rohár
2022-02-14 15:09         ` Pali Rohár
2022-02-14 15:26         ` Gregory CLEMENT
2022-02-14 15:26           ` Gregory CLEMENT
     [not found]           ` <CAEzXK1qYKVk7QiSY_DwqkZ7WV6WU06WBtiqZx0JJCc+mOP-7Kg@mail.gmail.com>
2022-02-15 10:48             ` Luís Mendes
2022-02-15 10:48               ` Luís Mendes
2022-02-15 10:52               ` Pali Rohár
2022-02-15 10:52                 ` Pali Rohár
2022-02-18 21:53                 ` Luís Mendes [this message]
2022-02-18 21:53                   ` Luís Mendes
2022-02-19 13:36                   ` Pali Rohár
2022-02-19 13:36                     ` Pali Rohár
2022-02-11 17:50 ` [PATCH 00/11] PCI: mvebu: subsystem ids, AER and INTx Lorenzo Pieralisi
2022-02-11 17:50   ` Lorenzo Pieralisi
2022-02-11 18:01   ` Pali Rohár
2022-02-11 18:01     ` Pali Rohár

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