* [PATCH v2 00/23] Update cache properties for arm64 DTS
@ 2022-11-07 15:56 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:56 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Peng Fan, Shenwei Wang, Ming Qian,
Lucas Stach, Adam Ford, Tim Harvey, Richard Zhu, Li Jun,
Joakim Zhang, Markus Niebel, Marco Felsch, Marek Vasut,
Laurent Pinchart, Alexander Stein, Paul Elder, Martin Kepplinger,
David Heidelberg, Oliver Graute, Liu Ying, Shijie Qin, Jacky Bai,
Clark Wang, Chris Packham, Vadym Kochan, Sameer Pujar, Akhil R,
Prathamesh Shete, Sumit Gupta, Diogo Ivo, Mikko Perttunen,
Vidya Sagar, Ashish Mhetre, Johan Jonker, Christopher Obbard,
Ezequiel Garcia, Aswani Reddy, Shashank Prashar, Arjun K V,
devicetree, linux-rpi-kernel, linux-arm-kernel, linux-amlogic,
linux-samsung-soc, linux-mediatek, openbmc, linux-tegra,
linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
v2:
- Update/Add patches for missed cache properties requiring to be
updated for the following platforns: bcm, amazon, arm, exynos,
freescale, marvell, mediatek, nvidia, socinext, tesla, ti.
Missed cache properties were detected using Rob Herring's branch:
https://github.com/robherring/dt-schema/tree/cache-rework
- v1 of exynos, tesla were merged.
- Updated wrong reference in commit message.
- Added received Rb/Acked-by.
Align arm64 DTS to the DeviceTree specification v0.3 regarding
cache properties. The patch-set mainly adds 'cache-level' or
'cache' compatibility properties.
For one qcom DTS, level 1 cache nodes are removed as they should
be in the cpu nodes.
On another node, it seems that the 'cache-unified' is under-used.
cache-unified:
If present, specifies the cache has a unified or-
ganization. If not present, specifies that the
cache has a Harvard architecture with separate
caches for instructions and data.
Only a few l2 cache nodes have this property, and in the absence
of [|d|i]-cache-size properties (or other), the cache is assumed to be
split.
The l2 cache of the Rockchip RK3308 platform is thus assumed to be
split:
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
};
when the platform datasheet advertises a unified cache.
No modification/check was made to correct that due to the lack of
cache information for most platforms.
Pierre Gondois (23):
arm64: dts: Update cache properties for amazon
arm64: dts: Update cache properties for amd
arm64: dts: Update cache properties for amlogic
arm64: dts: Update cache properties for apm
arm64: dts: Update cache properties for arm
arm64: dts: Update cache properties for broadcom
arm64: dts: Update cache properties for exynos
arm64: dts: Update cache properties for freescale
arm64: dts: Update cache properties for hisilicon
arm64: dts: Update cache properties for lg
arm64: dts: Update cache properties for marvell
arm64: dts: Update cache properties for mediatek
arm64: dts: Update cache properties for microchip
arm64: dts: Update cache properties for nuvoton
arm64: dts: Update cache properties for nvidia
arm64: dts: Update cache properties for qcom
arm64: dts: Update cache properties for realtek
arm64: dts: Update cache properties for renesas
arm64: dts: Update cache properties for rockchip
arm64: dts: Update cache properties for socionext
arm64: dts: Update cache properties for synaptics
arm64: dts: Update cache properties for tesla
arm64: dts: Update cache properties for ti
arch/arm/boot/dts/bcm2711.dtsi | 1 +
arch/arm/boot/dts/bcm2837.dtsi | 1 +
arch/arm64/boot/dts/amazon/alpine-v3.dtsi | 4 ++
arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi | 9 +++
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 1 +
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 4 ++
arch/arm64/boot/dts/apm/apm-storm.dtsi | 4 ++
arch/arm64/boot/dts/arm/corstone1000.dtsi | 1 +
arch/arm64/boot/dts/arm/foundation-v8.dtsi | 1 +
arch/arm64/boot/dts/arm/juno-r1.dts | 2 +
arch/arm64/boot/dts/arm/juno-r2.dts | 2 +
arch/arm64/boot/dts/arm/juno.dts | 2 +
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 1 +
.../boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 1 +
.../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 1 +
.../boot/dts/broadcom/bcmbca/bcm4912.dtsi | 1 +
.../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 1 +
.../boot/dts/broadcom/bcmbca/bcm63158.dtsi | 1 +
.../boot/dts/broadcom/bcmbca/bcm6813.dtsi | 1 +
.../boot/dts/broadcom/bcmbca/bcm6856.dtsi | 1 +
.../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 1 +
.../boot/dts/broadcom/northstar2/ns2.dtsi | 1 +
.../boot/dts/broadcom/stingray/stingray.dtsi | 4 ++
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 4 ++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 +
.../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 +
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 +
.../arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++
.../arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 +++
arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 2 +
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 1 +
arch/arm64/boot/dts/freescale/s32g2.dtsi | 2 +
arch/arm64/boot/dts/freescale/s32v234.dtsi | 2 +
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 +
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 +
arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 ++
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 16 ++++++
arch/arm64/boot/dts/lg/lg1312.dtsi | 1 +
arch/arm64/boot/dts/lg/lg1313.dtsi | 1 +
arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 +
.../boot/dts/marvell/armada-ap806-dual.dtsi | 2 +
.../boot/dts/marvell/armada-ap806-quad.dtsi | 4 ++
.../boot/dts/marvell/armada-ap807-quad.dtsi | 4 ++
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 3 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 3 +
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 +
arch/arm64/boot/dts/microchip/sparx5.dtsi | 1 +
.../boot/dts/nuvoton/nuvoton-npcm845.dtsi | 1 +
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 15 +++++
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 +
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 33 +++++++++++
arch/arm64/boot/dts/qcom/msm8953.dtsi | 56 -------------------
arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 +++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 9 +++
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++
arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +
arch/arm64/boot/dts/qcom/sm6350.dtsi | 9 +++
arch/arm64/boot/dts/qcom/sm8150.dtsi | 9 +++
arch/arm64/boot/dts/qcom/sm8250.dtsi | 9 +++
arch/arm64/boot/dts/qcom/sm8350.dtsi | 9 +++
arch/arm64/boot/dts/qcom/sm8450.dtsi | 9 +++
arch/arm64/boot/dts/realtek/rtd1293.dtsi | 1 +
arch/arm64/boot/dts/realtek/rtd1295.dtsi | 1 +
arch/arm64/boot/dts/realtek/rtd1296.dtsi | 1 +
arch/arm64/boot/dts/realtek/rtd1395.dtsi | 1 +
arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 2 +
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 1 +
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 1 +
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 1 +
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 1 +
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1 +
.../boot/dts/socionext/uniphier-ld11.dtsi | 1 +
.../boot/dts/socionext/uniphier-ld20.dtsi | 2 +
.../boot/dts/socionext/uniphier-pxs3.dtsi | 1 +
arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 1 +
arch/arm64/boot/dts/tesla/fsd.dtsi | 2 +
arch/arm64/boot/dts/ti/k3-am625.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am642.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am654.dtsi | 2 +
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 1 +
98 files changed, 299 insertions(+), 56 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 107+ messages in thread
* [PATCH v2 00/23] Update cache properties for arm64 DTS
@ 2022-11-07 15:56 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:56 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Peng Fan, Shenwei Wang, Ming Qian,
Lucas Stach, Adam Ford, Tim Harvey, Richard Zhu, Li Jun,
Joakim Zhang, Markus Niebel, Marco Felsch, Marek Vasut,
Laurent Pinchart, Alexander Stein, Paul Elder, Martin Kepplinger,
David Heidelberg, Oliver Graute, Liu Ying, Shijie Qin, Jacky Bai,
Clark Wang, Chris Packham, Vadym Kochan, Sameer Pujar, Akhil R,
Prathamesh Shete, Sumit Gupta, Diogo Ivo, Mikko Perttunen,
Vidya Sagar, Ashish Mhetre, Johan Jonker, Christopher Obbard,
Ezequiel Garcia, Aswani Reddy, Shashank Prashar, Arjun K V,
devicetree, linux-rpi-kernel, linux-arm-kernel, linux-amlogic,
linux-samsung-soc, linux-mediatek, openbmc, linux-tegra,
linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
v2:
- Update/Add patches for missed cache properties requiring to be
updated for the following platforns: bcm, amazon, arm, exynos,
freescale, marvell, mediatek, nvidia, socinext, tesla, ti.
Missed cache properties were detected using Rob Herring's branch:
https://github.com/robherring/dt-schema/tree/cache-rework
- v1 of exynos, tesla were merged.
- Updated wrong reference in commit message.
- Added received Rb/Acked-by.
Align arm64 DTS to the DeviceTree specification v0.3 regarding
cache properties. The patch-set mainly adds 'cache-level' or
'cache' compatibility properties.
For one qcom DTS, level 1 cache nodes are removed as they should
be in the cpu nodes.
On another node, it seems that the 'cache-unified' is under-used.
cache-unified:
If present, specifies the cache has a unified or-
ganization. If not present, specifies that the
cache has a Harvard architecture with separate
caches for instructions and data.
Only a few l2 cache nodes have this property, and in the absence
of [|d|i]-cache-size properties (or other), the cache is assumed to be
split.
The l2 cache of the Rockchip RK3308 platform is thus assumed to be
split:
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
};
when the platform datasheet advertises a unified cache.
No modification/check was made to correct that due to the lack of
cache information for most platforms.
Pierre Gondois (23):
arm64: dts: Update cache properties for amazon
arm64: dts: Update cache properties for amd
arm64: dts: Update cache properties for amlogic
arm64: dts: Update cache properties for apm
arm64: dts: Update cache properties for arm
arm64: dts: Update cache properties for broadcom
arm64: dts: Update cache properties for exynos
arm64: dts: Update cache properties for freescale
arm64: dts: Update cache properties for hisilicon
arm64: dts: Update cache properties for lg
arm64: dts: Update cache properties for marvell
arm64: dts: Update cache properties for mediatek
arm64: dts: Update cache properties for microchip
arm64: dts: Update cache properties for nuvoton
arm64: dts: Update cache properties for nvidia
arm64: dts: Update cache properties for qcom
arm64: dts: Update cache properties for realtek
arm64: dts: Update cache properties for renesas
arm64: dts: Update cache properties for rockchip
arm64: dts: Update cache properties for socionext
arm64: dts: Update cache properties for synaptics
arm64: dts: Update cache properties for tesla
arm64: dts: Update cache properties for ti
arch/arm/boot/dts/bcm2711.dtsi | 1 +
arch/arm/boot/dts/bcm2837.dtsi | 1 +
arch/arm64/boot/dts/amazon/alpine-v3.dtsi | 4 ++
arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi | 9 +++
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 1 +
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 4 ++
arch/arm64/boot/dts/apm/apm-storm.dtsi | 4 ++
arch/arm64/boot/dts/arm/corstone1000.dtsi | 1 +
arch/arm64/boot/dts/arm/foundation-v8.dtsi | 1 +
arch/arm64/boot/dts/arm/juno-r1.dts | 2 +
arch/arm64/boot/dts/arm/juno-r2.dts | 2 +
arch/arm64/boot/dts/arm/juno.dts | 2 +
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 1 +
.../boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 1 +
.../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 1 +
.../boot/dts/broadcom/bcmbca/bcm4912.dtsi | 1 +
.../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 1 +
.../boot/dts/broadcom/bcmbca/bcm63158.dtsi | 1 +
.../boot/dts/broadcom/bcmbca/bcm6813.dtsi | 1 +
.../boot/dts/broadcom/bcmbca/bcm6856.dtsi | 1 +
.../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 1 +
.../boot/dts/broadcom/northstar2/ns2.dtsi | 1 +
.../boot/dts/broadcom/stingray/stingray.dtsi | 4 ++
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 4 ++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 +
.../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 +
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 +
.../arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++
.../arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 +++
arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 2 +
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 1 +
arch/arm64/boot/dts/freescale/s32g2.dtsi | 2 +
arch/arm64/boot/dts/freescale/s32v234.dtsi | 2 +
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 +
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 +
arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 ++
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 16 ++++++
arch/arm64/boot/dts/lg/lg1312.dtsi | 1 +
arch/arm64/boot/dts/lg/lg1313.dtsi | 1 +
arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 +
.../boot/dts/marvell/armada-ap806-dual.dtsi | 2 +
.../boot/dts/marvell/armada-ap806-quad.dtsi | 4 ++
.../boot/dts/marvell/armada-ap807-quad.dtsi | 4 ++
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 3 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 3 +
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 +
arch/arm64/boot/dts/microchip/sparx5.dtsi | 1 +
.../boot/dts/nuvoton/nuvoton-npcm845.dtsi | 1 +
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 15 +++++
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 +
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 33 +++++++++++
arch/arm64/boot/dts/qcom/msm8953.dtsi | 56 -------------------
arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 +++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 9 +++
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++
arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +
arch/arm64/boot/dts/qcom/sm6350.dtsi | 9 +++
arch/arm64/boot/dts/qcom/sm8150.dtsi | 9 +++
arch/arm64/boot/dts/qcom/sm8250.dtsi | 9 +++
arch/arm64/boot/dts/qcom/sm8350.dtsi | 9 +++
arch/arm64/boot/dts/qcom/sm8450.dtsi | 9 +++
arch/arm64/boot/dts/realtek/rtd1293.dtsi | 1 +
arch/arm64/boot/dts/realtek/rtd1295.dtsi | 1 +
arch/arm64/boot/dts/realtek/rtd1296.dtsi | 1 +
arch/arm64/boot/dts/realtek/rtd1395.dtsi | 1 +
arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 2 +
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 1 +
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 1 +
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 1 +
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 1 +
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1 +
.../boot/dts/socionext/uniphier-ld11.dtsi | 1 +
.../boot/dts/socionext/uniphier-ld20.dtsi | 2 +
.../boot/dts/socionext/uniphier-pxs3.dtsi | 1 +
arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 1 +
arch/arm64/boot/dts/tesla/fsd.dtsi | 2 +
arch/arm64/boot/dts/ti/k3-am625.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am642.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am654.dtsi | 2 +
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 1 +
98 files changed, 299 insertions(+), 56 deletions(-)
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 107+ messages in thread
* [PATCH v2 01/23] arm64: dts: Update cache properties for amazon
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:56 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:56 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Peng Fan, Ming Qian, Shenwei Wang,
Adam Ford, Tim Harvey, Lucas Stach, Richard Zhu, Li Jun,
Markus Niebel, Marco Felsch, Joakim Zhang, Marek Vasut,
Laurent Pinchart, Alexander Stein, Paul Elder, Martin Kepplinger,
David Heidelberg, Liu Ying, Oliver Graute, Dong Aisheng,
Clark Wang, Jacky Bai, Chris Packham, Vadym Kochan, Sameer Pujar,
Mikko Perttunen, Akhil R, Sumit Gupta, Prathamesh Shete,
Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Arnd Bergmann, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/amazon/alpine-v3.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi
index 73a352ea8fd5..ba7e56dc85db 100644
--- a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi
+++ b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi
@@ -246,6 +246,7 @@ cpu@303 {
cluster0_l2: cache@0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -254,6 +255,7 @@ cluster0_l2: cache@0 {
cluster1_l2: cache@100 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -262,6 +264,7 @@ cluster1_l2: cache@100 {
cluster2_l2: cache@200 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -270,6 +273,7 @@ cluster2_l2: cache@200 {
cluster3_l2: cache@300 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 01/23] arm64: dts: Update cache properties for amazon
@ 2022-11-07 15:56 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:56 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Peng Fan, Ming Qian, Shenwei Wang,
Adam Ford, Tim Harvey, Lucas Stach, Richard Zhu, Li Jun,
Markus Niebel, Marco Felsch, Joakim Zhang, Marek Vasut,
Laurent Pinchart, Alexander Stein, Paul Elder, Martin Kepplinger,
David Heidelberg, Liu Ying, Oliver Graute, Dong Aisheng,
Clark Wang, Jacky Bai, Chris Packham, Vadym Kochan, Sameer Pujar,
Mikko Perttunen, Akhil R, Sumit Gupta, Prathamesh Shete,
Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Arnd Bergmann, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/amazon/alpine-v3.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi
index 73a352ea8fd5..ba7e56dc85db 100644
--- a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi
+++ b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi
@@ -246,6 +246,7 @@ cpu@303 {
cluster0_l2: cache@0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -254,6 +255,7 @@ cluster0_l2: cache@0 {
cluster1_l2: cache@100 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -262,6 +264,7 @@ cluster1_l2: cache@100 {
cluster2_l2: cache@200 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -270,6 +273,7 @@ cluster2_l2: cache@200 {
cluster3_l2: cache@300 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 02/23] arm64: dts: Update cache properties for amd
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:56 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:56 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Zhou Peng, Shenwei Wang, Ming Qian,
Peng Fan, Tim Harvey, Adam Ford, Lucas Stach, Richard Zhu,
Li Jun, Markus Niebel, Joakim Zhang, Marek Vasut,
Laurent Pinchart, Paul Elder, Alexander Stein, Martin Kepplinger,
David Heidelberg, Liu Ying, Oliver Graute, Dong Aisheng,
Wei Fang, Clark Wang, Jacky Bai, Chris Packham, Vadym Kochan,
Sameer Pujar, Prathamesh Shete, Mikko Perttunen, Akhil R,
Sumit Gupta, Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, devicetree, linux-rpi-kernel, linux-arm-kernel,
linux-amlogic, linux-samsung-soc, linux-mediatek, openbmc,
linux-tegra, linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
index 93688a0b6820..9f2d983e082d 100644
--- a/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
+++ b/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
@@ -163,38 +163,47 @@ CPU7: cpu@301 {
};
L2_0: l2-cache0 {
+ compatible = "cache";
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&L3>;
};
L2_1: l2-cache1 {
+ compatible = "cache";
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&L3>;
};
L2_2: l2-cache2 {
+ compatible = "cache";
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&L3>;
};
L2_3: l2-cache3 {
+ compatible = "cache";
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&L3>;
};
L3: l3-cache {
+ compatible = "cache";
cache-level = <3>;
cache-size = <0x800000>;
cache-line-size = <64>;
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 02/23] arm64: dts: Update cache properties for amd
@ 2022-11-07 15:56 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:56 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Zhou Peng, Shenwei Wang, Ming Qian,
Peng Fan, Tim Harvey, Adam Ford, Lucas Stach, Richard Zhu,
Li Jun, Markus Niebel, Joakim Zhang, Marek Vasut,
Laurent Pinchart, Paul Elder, Alexander Stein, Martin Kepplinger,
David Heidelberg, Liu Ying, Oliver Graute, Dong Aisheng,
Wei Fang, Clark Wang, Jacky Bai, Chris Packham, Vadym Kochan,
Sameer Pujar, Prathamesh Shete, Mikko Perttunen, Akhil R,
Sumit Gupta, Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, devicetree, linux-rpi-kernel, linux-arm-kernel,
linux-amlogic, linux-samsung-soc, linux-mediatek, openbmc,
linux-tegra, linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
index 93688a0b6820..9f2d983e082d 100644
--- a/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
+++ b/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
@@ -163,38 +163,47 @@ CPU7: cpu@301 {
};
L2_0: l2-cache0 {
+ compatible = "cache";
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&L3>;
};
L2_1: l2-cache1 {
+ compatible = "cache";
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&L3>;
};
L2_2: l2-cache2 {
+ compatible = "cache";
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&L3>;
};
L2_3: l2-cache3 {
+ compatible = "cache";
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&L3>;
};
L3: l3-cache {
+ compatible = "cache";
cache-level = <3>;
cache-size = <0x800000>;
cache-line-size = <64>;
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 03/23] arm64: dts: Update cache properties for amlogic
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:56 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:56 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Martin Blumenstingl, Rob Herring,
Krzysztof Kozlowski, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Khuong Dinh, Liviu Dudau,
Sudeep Holla, Lorenzo Pieralisi, William Zhang, Anand Gore,
Kursad Oney, Rafał Miłecki, Alim Akhtar, Shawn Guo,
Li Yang, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shenwei Wang, Ming Qian, Peng Fan,
Tim Harvey, Lucas Stach, Adam Ford, Richard Zhu, Li Jun,
Joakim Zhang, Markus Niebel, Marek Vasut, Laurent Pinchart,
Alexander Stein, Paul Elder, Martin Kepplinger, David Heidelberg,
Liu Ying, Oliver Graute, Zhou Peng, Wei Fang, Jacky Bai,
Clark Wang, Chris Packham, Vadym Kochan, Sameer Pujar,
Prathamesh Shete, Akhil R, Mikko Perttunen, Sumit Gupta,
Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Arjun K V, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 1 +
6 files changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index b4000cf65a9a..d2f7cb4e5375 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -36,6 +36,7 @@ cpu1: cpu@1 {
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 04f797b5a012..1648e67afbb6 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -105,6 +105,7 @@ cpu3: cpu@3 {
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index fb0ab27d1f64..af23d7968181 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -50,6 +50,7 @@ cpu3: cpu@3 {
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
index ee8fcae9f9f0..9978e619accc 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
@@ -105,6 +105,7 @@ cpu103: cpu@103 {
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 023a52005494..e3c12e0be99d 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -132,6 +132,7 @@ cpu3: cpu@3 {
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
index 80737731af3f..d845eb19d93d 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
@@ -88,6 +88,7 @@ cpu3: cpu@3 {
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 03/23] arm64: dts: Update cache properties for amlogic
@ 2022-11-07 15:56 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:56 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Martin Blumenstingl, Rob Herring,
Krzysztof Kozlowski, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Khuong Dinh, Liviu Dudau,
Sudeep Holla, Lorenzo Pieralisi, William Zhang, Anand Gore,
Kursad Oney, Rafał Miłecki, Alim Akhtar, Shawn Guo,
Li Yang, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shenwei Wang, Ming Qian, Peng Fan,
Tim Harvey, Lucas Stach, Adam Ford, Richard Zhu, Li Jun,
Joakim Zhang, Markus Niebel, Marek Vasut, Laurent Pinchart,
Alexander Stein, Paul Elder, Martin Kepplinger, David Heidelberg,
Liu Ying, Oliver Graute, Zhou Peng, Wei Fang, Jacky Bai,
Clark Wang, Chris Packham, Vadym Kochan, Sameer Pujar,
Prathamesh Shete, Akhil R, Mikko Perttunen, Sumit Gupta,
Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Arjun K V, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 +
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 1 +
6 files changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index b4000cf65a9a..d2f7cb4e5375 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -36,6 +36,7 @@ cpu1: cpu@1 {
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 04f797b5a012..1648e67afbb6 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -105,6 +105,7 @@ cpu3: cpu@3 {
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index fb0ab27d1f64..af23d7968181 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -50,6 +50,7 @@ cpu3: cpu@3 {
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
index ee8fcae9f9f0..9978e619accc 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
@@ -105,6 +105,7 @@ cpu103: cpu@103 {
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 023a52005494..e3c12e0be99d 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -132,6 +132,7 @@ cpu3: cpu@3 {
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
index 80737731af3f..d845eb19d93d 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
@@ -88,6 +88,7 @@ cpu3: cpu@3 {
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 04/23] arm64: dts: Update cache properties for apm
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:56 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:56 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shenwei Wang, Ming Qian, Peng Fan,
Lucas Stach, Adam Ford, Tim Harvey, Li Jun, Richard Zhu,
Marek Vasut, Markus Niebel, Laurent Pinchart, Joakim Zhang,
Paul Elder, Alexander Stein, Martin Kepplinger, David Heidelberg,
Liu Ying, Oliver Graute, Shijie Qin, Clark Wang, Jacky Bai,
Wei Fang, Chris Packham, Vadym Kochan, Sameer Pujar,
Mikko Perttunen, Prathamesh Shete, Akhil R, Sumit Gupta,
Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Ajay Kumar, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 4 ++++
arch/arm64/boot/dts/apm/apm-storm.dtsi | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
index a8526f8157ec..68ba865fcd58 100644
--- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
@@ -97,15 +97,19 @@ cpu@301 {
};
xgene_L2_0: l2-cache-0 {
compatible = "cache";
+ cache-level = <2>;
};
xgene_L2_1: l2-cache-1 {
compatible = "cache";
+ cache-level = <2>;
};
xgene_L2_2: l2-cache-2 {
compatible = "cache";
+ cache-level = <2>;
};
xgene_L2_3: l2-cache-3 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index f56d687f772d..9ac7417f65eb 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -81,15 +81,19 @@ cpu@301 {
};
xgene_L2_0: l2-cache-0 {
compatible = "cache";
+ cache-level = <2>;
};
xgene_L2_1: l2-cache-1 {
compatible = "cache";
+ cache-level = <2>;
};
xgene_L2_2: l2-cache-2 {
compatible = "cache";
+ cache-level = <2>;
};
xgene_L2_3: l2-cache-3 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 04/23] arm64: dts: Update cache properties for apm
@ 2022-11-07 15:56 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:56 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shenwei Wang, Ming Qian, Peng Fan,
Lucas Stach, Adam Ford, Tim Harvey, Li Jun, Richard Zhu,
Marek Vasut, Markus Niebel, Laurent Pinchart, Joakim Zhang,
Paul Elder, Alexander Stein, Martin Kepplinger, David Heidelberg,
Liu Ying, Oliver Graute, Shijie Qin, Clark Wang, Jacky Bai,
Wei Fang, Chris Packham, Vadym Kochan, Sameer Pujar,
Mikko Perttunen, Prathamesh Shete, Akhil R, Sumit Gupta,
Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Ajay Kumar, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 4 ++++
arch/arm64/boot/dts/apm/apm-storm.dtsi | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
index a8526f8157ec..68ba865fcd58 100644
--- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
@@ -97,15 +97,19 @@ cpu@301 {
};
xgene_L2_0: l2-cache-0 {
compatible = "cache";
+ cache-level = <2>;
};
xgene_L2_1: l2-cache-1 {
compatible = "cache";
+ cache-level = <2>;
};
xgene_L2_2: l2-cache-2 {
compatible = "cache";
+ cache-level = <2>;
};
xgene_L2_3: l2-cache-3 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index f56d687f772d..9ac7417f65eb 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -81,15 +81,19 @@ cpu@301 {
};
xgene_L2_0: l2-cache-0 {
compatible = "cache";
+ cache-level = <2>;
};
xgene_L2_1: l2-cache-1 {
compatible = "cache";
+ cache-level = <2>;
};
xgene_L2_2: l2-cache-2 {
compatible = "cache";
+ cache-level = <2>;
};
xgene_L2_3: l2-cache-3 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 05/23] arm64: dts: Update cache properties for arm
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:56 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:56 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Zhou Peng, Shijie Qin, Ming Qian,
Peng Fan, Shenwei Wang, Adam Ford, Lucas Stach, Tim Harvey,
Li Jun, Richard Zhu, Markus Niebel, Marco Felsch, Marek Vasut,
Laurent Pinchart, Alexander Stein, Joakim Zhang, Paul Elder,
Martin Kepplinger, David Heidelberg, Liu Ying, Oliver Graute,
Ahmad Fatoum, Clark Wang, Jacky Bai, Chris Packham, Vadym Kochan,
Sameer Pujar, Prathamesh Shete, Akhil R, Mikko Perttunen,
Sumit Gupta, Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Arnd Bergmann, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/arm/corstone1000.dtsi | 1 +
arch/arm64/boot/dts/arm/foundation-v8.dtsi | 1 +
arch/arm64/boot/dts/arm/juno-r1.dts | 2 ++
arch/arm64/boot/dts/arm/juno-r2.dts | 2 ++
arch/arm64/boot/dts/arm/juno.dts | 2 ++
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 1 +
arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 1 +
7 files changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi
index 4e46826f883a..21f1f952e985 100644
--- a/arch/arm64/boot/dts/arm/corstone1000.dtsi
+++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi
@@ -53,6 +53,7 @@ gic: interrupt-controller@1c000000 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-level = <2>;
cache-size = <0x80000>;
cache-line-size = <64>;
diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
index 83e3e7e3984f..c8bd23b1a7ba 100644
--- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi
+++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
@@ -58,6 +58,7 @@ cpu3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
index 6451c62146fd..1d90eeebb37d 100644
--- a/arch/arm64/boot/dts/arm/juno-r1.dts
+++ b/arch/arm64/boot/dts/arm/juno-r1.dts
@@ -189,6 +189,7 @@ A53_3: cpu@103 {
A57_L2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -197,6 +198,7 @@ A57_L2: l2-cache0 {
A53_L2: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
index 438cd1ff4bd0..d2ada69b0a43 100644
--- a/arch/arm64/boot/dts/arm/juno-r2.dts
+++ b/arch/arm64/boot/dts/arm/juno-r2.dts
@@ -195,6 +195,7 @@ A53_3: cpu@103 {
A72_L2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -203,6 +204,7 @@ A72_L2: l2-cache0 {
A53_L2: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index cf4a58211399..5e48a01a5b9f 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -194,6 +194,7 @@ A53_3: cpu@103 {
A57_L2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -202,6 +203,7 @@ A57_L2: l2-cache0 {
A53_L2: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
index 258991ad7cc0..ef68f5aae7dd 100644
--- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
@@ -71,6 +71,7 @@ cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
index 5b6d9d8e934d..796cd7d02eb5 100644
--- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
+++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
@@ -57,6 +57,7 @@ cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 05/23] arm64: dts: Update cache properties for arm
@ 2022-11-07 15:56 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:56 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Zhou Peng, Shijie Qin, Ming Qian,
Peng Fan, Shenwei Wang, Adam Ford, Lucas Stach, Tim Harvey,
Li Jun, Richard Zhu, Markus Niebel, Marco Felsch, Marek Vasut,
Laurent Pinchart, Alexander Stein, Joakim Zhang, Paul Elder,
Martin Kepplinger, David Heidelberg, Liu Ying, Oliver Graute,
Ahmad Fatoum, Clark Wang, Jacky Bai, Chris Packham, Vadym Kochan,
Sameer Pujar, Prathamesh Shete, Akhil R, Mikko Perttunen,
Sumit Gupta, Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Arnd Bergmann, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/arm/corstone1000.dtsi | 1 +
arch/arm64/boot/dts/arm/foundation-v8.dtsi | 1 +
arch/arm64/boot/dts/arm/juno-r1.dts | 2 ++
arch/arm64/boot/dts/arm/juno-r2.dts | 2 ++
arch/arm64/boot/dts/arm/juno.dts | 2 ++
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 1 +
arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 1 +
7 files changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi
index 4e46826f883a..21f1f952e985 100644
--- a/arch/arm64/boot/dts/arm/corstone1000.dtsi
+++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi
@@ -53,6 +53,7 @@ gic: interrupt-controller@1c000000 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-level = <2>;
cache-size = <0x80000>;
cache-line-size = <64>;
diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
index 83e3e7e3984f..c8bd23b1a7ba 100644
--- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi
+++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
@@ -58,6 +58,7 @@ cpu3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
index 6451c62146fd..1d90eeebb37d 100644
--- a/arch/arm64/boot/dts/arm/juno-r1.dts
+++ b/arch/arm64/boot/dts/arm/juno-r1.dts
@@ -189,6 +189,7 @@ A53_3: cpu@103 {
A57_L2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -197,6 +198,7 @@ A57_L2: l2-cache0 {
A53_L2: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
index 438cd1ff4bd0..d2ada69b0a43 100644
--- a/arch/arm64/boot/dts/arm/juno-r2.dts
+++ b/arch/arm64/boot/dts/arm/juno-r2.dts
@@ -195,6 +195,7 @@ A53_3: cpu@103 {
A72_L2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -203,6 +204,7 @@ A72_L2: l2-cache0 {
A53_L2: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index cf4a58211399..5e48a01a5b9f 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -194,6 +194,7 @@ A53_3: cpu@103 {
A57_L2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -202,6 +203,7 @@ A57_L2: l2-cache0 {
A53_L2: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
index 258991ad7cc0..ef68f5aae7dd 100644
--- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
@@ -71,6 +71,7 @@ cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
index 5b6d9d8e934d..796cd7d02eb5 100644
--- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
+++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
@@ -57,6 +57,7 @@ cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 06/23] arm64: dts: Update cache properties for broadcom
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:56 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:56 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, William Zhang, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Anand Gore,
Kursad Oney, Rafał Miłecki, Alim Akhtar, Shawn Guo,
Li Yang, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Peng Fan, Shenwei Wang, Ming Qian,
Tim Harvey, Adam Ford, Lucas Stach, Li Jun, Richard Zhu,
Markus Niebel, Marek Vasut, Laurent Pinchart, Joakim Zhang,
Alexander Stein, Paul Elder, Martin Kepplinger, David Heidelberg,
Liu Ying, Oliver Graute, Wei Fang, Jacky Bai, Clark Wang,
Chris Packham, Vadym Kochan, Sameer Pujar, Mikko Perttunen,
Akhil R, Prathamesh Shete, Sumit Gupta, Diogo Ivo, Vidya Sagar,
Ashish Mhetre, Johan Jonker, Christopher Obbard, Ezequiel Garcia,
Aswani Reddy, Shashank Prashar, Andi Shyti, devicetree,
linux-rpi-kernel, linux-arm-kernel, linux-amlogic,
linux-samsung-soc, linux-mediatek, openbmc, linux-tegra,
linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Acked-by: William Zhang <william.zhang@broadcom.com>
---
arch/arm/boot/dts/bcm2711.dtsi | 1 +
arch/arm/boot/dts/bcm2837.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi | 1 +
arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 1 +
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 4 ++++
11 files changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
index 941c4d16791b..c6104149f959 100644
--- a/arch/arm/boot/dts/bcm2711.dtsi
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -536,6 +536,7 @@ cpu3: cpu@3 {
*/
l2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi
index 5dbdebc46259..b352ac784af6 100644
--- a/arch/arm/boot/dts/bcm2837.dtsi
+++ b/arch/arm/boot/dts/bcm2837.dtsi
@@ -115,6 +115,7 @@ cpu3: cpu@3 {
*/
l2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
index dac9d3b4e91d..996412ed52a0 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
@@ -63,6 +63,7 @@ cpu3: cpu@3 {
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
index 3d016c2ce675..d5bc31980f03 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
@@ -51,6 +51,7 @@ B53_3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
index 04de96bd0a03..6f805266d3c9 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
@@ -35,6 +35,7 @@ B53_1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
index 13629702f70b..b982249b80a2 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
@@ -51,6 +51,7 @@ B53_3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
index c3e6197be808..a996d436e977 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
@@ -51,6 +51,7 @@ B53_3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
index 0bce6497219f..62c530d4b103 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
@@ -35,6 +35,7 @@ B53_1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
index 29a880c6c858..ba3d5a98ccbc 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
@@ -50,6 +50,7 @@ B53_3: cpu@3 {
};
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
index fda97c47f4e9..18cdbc20f03f 100644
--- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
@@ -79,6 +79,7 @@ A57_3: cpu@3 {
CLUSTER0_L2: l2-cache@0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
index 8f8c25e51194..e05901abe957 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
@@ -108,18 +108,22 @@ cpu@301 {
CLUSTER0_L2: l2-cache@0 {
compatible = "cache";
+ cache-level = <2>;
};
CLUSTER1_L2: l2-cache@100 {
compatible = "cache";
+ cache-level = <2>;
};
CLUSTER2_L2: l2-cache@200 {
compatible = "cache";
+ cache-level = <2>;
};
CLUSTER3_L2: l2-cache@300 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 06/23] arm64: dts: Update cache properties for broadcom
@ 2022-11-07 15:56 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:56 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, William Zhang, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Anand Gore,
Kursad Oney, Rafał Miłecki, Alim Akhtar, Shawn Guo,
Li Yang, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Peng Fan, Shenwei Wang, Ming Qian,
Tim Harvey, Adam Ford, Lucas Stach, Li Jun, Richard Zhu,
Markus Niebel, Marek Vasut, Laurent Pinchart, Joakim Zhang,
Alexander Stein, Paul Elder, Martin Kepplinger, David Heidelberg,
Liu Ying, Oliver Graute, Wei Fang, Jacky Bai, Clark Wang,
Chris Packham, Vadym Kochan, Sameer Pujar, Mikko Perttunen,
Akhil R, Prathamesh Shete, Sumit Gupta, Diogo Ivo, Vidya Sagar,
Ashish Mhetre, Johan Jonker, Christopher Obbard, Ezequiel Garcia,
Aswani Reddy, Shashank Prashar, Andi Shyti, devicetree,
linux-rpi-kernel, linux-arm-kernel, linux-amlogic,
linux-samsung-soc, linux-mediatek, openbmc, linux-tegra,
linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Acked-by: William Zhang <william.zhang@broadcom.com>
---
arch/arm/boot/dts/bcm2711.dtsi | 1 +
arch/arm/boot/dts/bcm2837.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi | 1 +
arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 1 +
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 4 ++++
11 files changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
index 941c4d16791b..c6104149f959 100644
--- a/arch/arm/boot/dts/bcm2711.dtsi
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -536,6 +536,7 @@ cpu3: cpu@3 {
*/
l2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi
index 5dbdebc46259..b352ac784af6 100644
--- a/arch/arm/boot/dts/bcm2837.dtsi
+++ b/arch/arm/boot/dts/bcm2837.dtsi
@@ -115,6 +115,7 @@ cpu3: cpu@3 {
*/
l2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
index dac9d3b4e91d..996412ed52a0 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
@@ -63,6 +63,7 @@ cpu3: cpu@3 {
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
index 3d016c2ce675..d5bc31980f03 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
@@ -51,6 +51,7 @@ B53_3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
index 04de96bd0a03..6f805266d3c9 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
@@ -35,6 +35,7 @@ B53_1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
index 13629702f70b..b982249b80a2 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
@@ -51,6 +51,7 @@ B53_3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
index c3e6197be808..a996d436e977 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
@@ -51,6 +51,7 @@ B53_3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
index 0bce6497219f..62c530d4b103 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
@@ -35,6 +35,7 @@ B53_1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
index 29a880c6c858..ba3d5a98ccbc 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
@@ -50,6 +50,7 @@ B53_3: cpu@3 {
};
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
index fda97c47f4e9..18cdbc20f03f 100644
--- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
@@ -79,6 +79,7 @@ A57_3: cpu@3 {
CLUSTER0_L2: l2-cache@0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
index 8f8c25e51194..e05901abe957 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
@@ -108,18 +108,22 @@ cpu@301 {
CLUSTER0_L2: l2-cache@0 {
compatible = "cache";
+ cache-level = <2>;
};
CLUSTER1_L2: l2-cache@100 {
compatible = "cache";
+ cache-level = <2>;
};
CLUSTER2_L2: l2-cache@200 {
compatible = "cache";
+ cache-level = <2>;
};
CLUSTER3_L2: l2-cache@300 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 07/23] arm64: dts: Update cache properties for exynos
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:57 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shijie Qin, Peng Fan, Ming Qian,
Shenwei Wang, Adam Ford, Tim Harvey, Lucas Stach, Li Jun,
Richard Zhu, Markus Niebel, Marek Vasut, Marco Felsch,
Laurent Pinchart, Alexander Stein, Paul Elder, Martin Kepplinger,
David Heidelberg, Oliver Graute, Liu Ying, Zhou Peng, Haibo Chen,
Clark Wang, Jacky Bai, Wei Fang, Chris Packham, Vadym Kochan,
Sameer Pujar, Mikko Perttunen, Prathamesh Shete, Akhil R,
Sumit Gupta, Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Sriranjani P, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 4 ++++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 ++
2 files changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index bd6a354b9cb5..8619920da4b6 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -226,6 +226,8 @@ cpu7: cpu@3 {
cluster_a57_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -233,6 +235,8 @@ cluster_a57_l2: l2-cache0 {
cluster_a53_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
cache-size = <0x40000>;
cache-line-size = <64>;
cache-sets = <256>;
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 1cd771c90b47..f378d8629d88 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -107,6 +107,8 @@ cpu_atlas3: cpu@3 {
atlas_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 07/23] arm64: dts: Update cache properties for exynos
@ 2022-11-07 15:57 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shijie Qin, Peng Fan, Ming Qian,
Shenwei Wang, Adam Ford, Tim Harvey, Lucas Stach, Li Jun,
Richard Zhu, Markus Niebel, Marek Vasut, Marco Felsch,
Laurent Pinchart, Alexander Stein, Paul Elder, Martin Kepplinger,
David Heidelberg, Oliver Graute, Liu Ying, Zhou Peng, Haibo Chen,
Clark Wang, Jacky Bai, Wei Fang, Chris Packham, Vadym Kochan,
Sameer Pujar, Mikko Perttunen, Prathamesh Shete, Akhil R,
Sumit Gupta, Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Sriranjani P, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 4 ++++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 ++
2 files changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index bd6a354b9cb5..8619920da4b6 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -226,6 +226,8 @@ cpu7: cpu@3 {
cluster_a57_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -233,6 +235,8 @@ cluster_a57_l2: l2-cache0 {
cluster_a53_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
cache-size = <0x40000>;
cache-line-size = <64>;
cache-sets = <256>;
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 1cd771c90b47..f378d8629d88 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -107,6 +107,8 @@ cpu_atlas3: cpu@3 {
atlas_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 08/23] arm64: dts: Update cache properties for freescale
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:57 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shenwei Wang, Shijie Qin, Ming Qian,
Peng Fan, Adam Ford, Lucas Stach, Tim Harvey, Li Jun,
Richard Zhu, Joakim Zhang, Markus Niebel, Marek Vasut,
Laurent Pinchart, Paul Elder, Alexander Stein, Martin Kepplinger,
David Heidelberg, Liu Ying, Oliver Graute, Zhou Peng, Haibo Chen,
Ahmad Fatoum, Clark Wang, Jacky Bai, Chris Packham, Vadym Kochan,
Sameer Pujar, Prathamesh Shete, Mikko Perttunen, Akhil R,
Sumit Gupta, Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Ajay Kumar, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++++
arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 ++++++++
arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 2 ++
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 1 +
arch/arm64/boot/dts/freescale/s32g2.dtsi | 2 ++
arch/arm64/boot/dts/freescale/s32v234.dtsi | 2 ++
16 files changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index ac1c3a7e5f7a..1b33cabb4e14 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -46,6 +46,7 @@ cpu1: cpu@1 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 704f72caddd3..b9fd24cdc919 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -84,6 +84,7 @@ cpu3: cpu@3 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 3d9e29824bb2..a01e3cfec77f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -79,6 +79,7 @@ cpu3: cpu@3 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index a2cadf757148..1e5d76c4d83d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -95,18 +95,22 @@ cpu7: cpu@301 {
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-level = <2>;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-level = <2>;
};
CPU_PW20: cpu-pw20 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
index c3dc38188c17..c12c86915ec8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
@@ -95,18 +95,22 @@ cpu7: cpu@301 {
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-level = <2>;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-level = <2>;
};
CPU_PW20: cpu-pw20 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 8c76d86cb756..50c19e8405d5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -300,6 +300,7 @@ cpu701: cpu@701 {
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -308,6 +309,7 @@ cluster0_l2: l2-cache0 {
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -316,6 +318,7 @@ cluster1_l2: l2-cache1 {
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -324,6 +327,7 @@ cluster2_l2: l2-cache2 {
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -332,6 +336,7 @@ cluster3_l2: l2-cache3 {
cluster4_l2: l2-cache4 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -340,6 +345,7 @@ cluster4_l2: l2-cache4 {
cluster5_l2: l2-cache5 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -348,6 +354,7 @@ cluster5_l2: l2-cache5 {
cluster6_l2: l2-cache6 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -356,6 +363,7 @@ cluster6_l2: l2-cache6 {
cluster7_l2: l2-cache7 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
index 5ddbda0b4def..9a7965a694a2 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
@@ -59,6 +59,7 @@ A35_1: cpu@1 {
A35_L2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index dabd94dc30c4..149b7af5349d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -139,6 +139,7 @@ A53_3: cpu@3 {
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index ad0b99adf691..12cc1a6c50c2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -139,6 +139,7 @@ A53_3: cpu@3 {
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index bb916a0948a8..e2a9ddbe4d40 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -123,6 +123,7 @@ A53_3: cpu@3 {
A53_L2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-level = <2>;
cache-size = <0x80000>;
cache-line-size = <64>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 19eaa523564d..1b7e7ac2750a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -179,6 +179,7 @@ A53_3: cpu@3 {
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index c9c2b6536233..41ce8336f29e 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -136,6 +136,7 @@ A72_1: cpu@101 {
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -144,6 +145,7 @@ A53_L2: l2-cache0 {
A72_L2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index f4ea18bb95ab..85c0b1d2bac5 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -127,6 +127,7 @@ A35_3: cpu@3 {
A35_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 06ce5f19aa8a..32193a43ff49 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -51,6 +51,7 @@ A35_1: cpu@1 {
A35_L2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 824d401e7a2c..d8c82da88ca0 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -52,10 +52,12 @@ cpu3: cpu@101 {
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi
index ba0b5305d481..3e306218d533 100644
--- a/arch/arm64/boot/dts/freescale/s32v234.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi
@@ -61,10 +61,12 @@ cpu3: cpu@101 {
cluster0_l2_cache: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2_cache: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 08/23] arm64: dts: Update cache properties for freescale
@ 2022-11-07 15:57 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shenwei Wang, Shijie Qin, Ming Qian,
Peng Fan, Adam Ford, Lucas Stach, Tim Harvey, Li Jun,
Richard Zhu, Joakim Zhang, Markus Niebel, Marek Vasut,
Laurent Pinchart, Paul Elder, Alexander Stein, Martin Kepplinger,
David Heidelberg, Liu Ying, Oliver Graute, Zhou Peng, Haibo Chen,
Ahmad Fatoum, Clark Wang, Jacky Bai, Chris Packham, Vadym Kochan,
Sameer Pujar, Prathamesh Shete, Mikko Perttunen, Akhil R,
Sumit Gupta, Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Ajay Kumar, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++++
arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 ++++++++
arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 2 ++
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 1 +
arch/arm64/boot/dts/freescale/s32g2.dtsi | 2 ++
arch/arm64/boot/dts/freescale/s32v234.dtsi | 2 ++
16 files changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index ac1c3a7e5f7a..1b33cabb4e14 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -46,6 +46,7 @@ cpu1: cpu@1 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 704f72caddd3..b9fd24cdc919 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -84,6 +84,7 @@ cpu3: cpu@3 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 3d9e29824bb2..a01e3cfec77f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -79,6 +79,7 @@ cpu3: cpu@3 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index a2cadf757148..1e5d76c4d83d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -95,18 +95,22 @@ cpu7: cpu@301 {
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-level = <2>;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-level = <2>;
};
CPU_PW20: cpu-pw20 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
index c3dc38188c17..c12c86915ec8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
@@ -95,18 +95,22 @@ cpu7: cpu@301 {
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-level = <2>;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-level = <2>;
};
CPU_PW20: cpu-pw20 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 8c76d86cb756..50c19e8405d5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -300,6 +300,7 @@ cpu701: cpu@701 {
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -308,6 +309,7 @@ cluster0_l2: l2-cache0 {
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -316,6 +318,7 @@ cluster1_l2: l2-cache1 {
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -324,6 +327,7 @@ cluster2_l2: l2-cache2 {
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -332,6 +336,7 @@ cluster3_l2: l2-cache3 {
cluster4_l2: l2-cache4 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -340,6 +345,7 @@ cluster4_l2: l2-cache4 {
cluster5_l2: l2-cache5 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -348,6 +354,7 @@ cluster5_l2: l2-cache5 {
cluster6_l2: l2-cache6 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -356,6 +363,7 @@ cluster6_l2: l2-cache6 {
cluster7_l2: l2-cache7 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
index 5ddbda0b4def..9a7965a694a2 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
@@ -59,6 +59,7 @@ A35_1: cpu@1 {
A35_L2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index dabd94dc30c4..149b7af5349d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -139,6 +139,7 @@ A53_3: cpu@3 {
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index ad0b99adf691..12cc1a6c50c2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -139,6 +139,7 @@ A53_3: cpu@3 {
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index bb916a0948a8..e2a9ddbe4d40 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -123,6 +123,7 @@ A53_3: cpu@3 {
A53_L2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-level = <2>;
cache-size = <0x80000>;
cache-line-size = <64>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 19eaa523564d..1b7e7ac2750a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -179,6 +179,7 @@ A53_3: cpu@3 {
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index c9c2b6536233..41ce8336f29e 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -136,6 +136,7 @@ A72_1: cpu@101 {
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -144,6 +145,7 @@ A53_L2: l2-cache0 {
A72_L2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index f4ea18bb95ab..85c0b1d2bac5 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -127,6 +127,7 @@ A35_3: cpu@3 {
A35_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 06ce5f19aa8a..32193a43ff49 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -51,6 +51,7 @@ A35_1: cpu@1 {
A35_L2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 824d401e7a2c..d8c82da88ca0 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -52,10 +52,12 @@ cpu3: cpu@101 {
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi
index ba0b5305d481..3e306218d533 100644
--- a/arch/arm64/boot/dts/freescale/s32v234.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi
@@ -61,10 +61,12 @@ cpu3: cpu@101 {
cluster0_l2_cache: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2_cache: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 09/23] arm64: dts: Update cache properties for hisilicon
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:57 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Ming Qian, Shijie Qin, Peng Fan,
Shenwei Wang, Tim Harvey, Lucas Stach, Adam Ford, Richard Zhu,
Li Jun, Markus Niebel, Joakim Zhang, Marek Vasut,
Laurent Pinchart, Alexander Stein, Paul Elder, Martin Kepplinger,
David Heidelberg, Oliver Graute, Liu Ying, Jacky Bai, Clark Wang,
Wei Fang, Chris Packham, Vadym Kochan, Sameer Pujar, Akhil R,
Mikko Perttunen, Prathamesh Shete, Sumit Gupta, Diogo Ivo,
Vidya Sagar, Ashish Mhetre, Johan Jonker, Christopher Obbard,
Ezequiel Garcia, Aswani Reddy, Shashank Prashar, Andi Shyti,
devicetree, linux-rpi-kernel, linux-arm-kernel, linux-amlogic,
linux-samsung-soc, linux-mediatek, openbmc, linux-tegra,
linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 ++
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 ++
arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++++
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 ++++
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 16 ++++++++++++++++
5 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 8343d0cedde3..a57f35eb5ef6 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -203,10 +203,12 @@ CLUSTER_SLEEP_1: cluster-sleep-1 {
A53_L2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
A73_L2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index ae0a7cfeeb47..f6d3202b0d1a 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -186,10 +186,12 @@ cpu7: cpu@103 {
CLUSTER0_L2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
CLUSTER1_L2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index 7b2abd10d3d6..5b2b1bfd0d2a 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -211,18 +211,22 @@ cpu15: cpu@20303 {
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-level = <2>;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 2f8b03b0d365..291c2ee38288 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -211,18 +211,22 @@ cpu15: cpu@10303 {
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-level = <2>;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index 1a16662f8867..b8746fb959b5 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -842,66 +842,82 @@ cpu63: cpu@70303 {
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-level = <2>;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-level = <2>;
};
cluster4_l2: l2-cache4 {
compatible = "cache";
+ cache-level = <2>;
};
cluster5_l2: l2-cache5 {
compatible = "cache";
+ cache-level = <2>;
};
cluster6_l2: l2-cache6 {
compatible = "cache";
+ cache-level = <2>;
};
cluster7_l2: l2-cache7 {
compatible = "cache";
+ cache-level = <2>;
};
cluster8_l2: l2-cache8 {
compatible = "cache";
+ cache-level = <2>;
};
cluster9_l2: l2-cache9 {
compatible = "cache";
+ cache-level = <2>;
};
cluster10_l2: l2-cache10 {
compatible = "cache";
+ cache-level = <2>;
};
cluster11_l2: l2-cache11 {
compatible = "cache";
+ cache-level = <2>;
};
cluster12_l2: l2-cache12 {
compatible = "cache";
+ cache-level = <2>;
};
cluster13_l2: l2-cache13 {
compatible = "cache";
+ cache-level = <2>;
};
cluster14_l2: l2-cache14 {
compatible = "cache";
+ cache-level = <2>;
};
cluster15_l2: l2-cache15 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 09/23] arm64: dts: Update cache properties for hisilicon
@ 2022-11-07 15:57 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Ming Qian, Shijie Qin, Peng Fan,
Shenwei Wang, Tim Harvey, Lucas Stach, Adam Ford, Richard Zhu,
Li Jun, Markus Niebel, Joakim Zhang, Marek Vasut,
Laurent Pinchart, Alexander Stein, Paul Elder, Martin Kepplinger,
David Heidelberg, Oliver Graute, Liu Ying, Jacky Bai, Clark Wang,
Wei Fang, Chris Packham, Vadym Kochan, Sameer Pujar, Akhil R,
Mikko Perttunen, Prathamesh Shete, Sumit Gupta, Diogo Ivo,
Vidya Sagar, Ashish Mhetre, Johan Jonker, Christopher Obbard,
Ezequiel Garcia, Aswani Reddy, Shashank Prashar, Andi Shyti,
devicetree, linux-rpi-kernel, linux-arm-kernel, linux-amlogic,
linux-samsung-soc, linux-mediatek, openbmc, linux-tegra,
linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 ++
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 ++
arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++++
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 ++++
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 16 ++++++++++++++++
5 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 8343d0cedde3..a57f35eb5ef6 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -203,10 +203,12 @@ CLUSTER_SLEEP_1: cluster-sleep-1 {
A53_L2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
A73_L2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index ae0a7cfeeb47..f6d3202b0d1a 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -186,10 +186,12 @@ cpu7: cpu@103 {
CLUSTER0_L2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
CLUSTER1_L2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index 7b2abd10d3d6..5b2b1bfd0d2a 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -211,18 +211,22 @@ cpu15: cpu@20303 {
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-level = <2>;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 2f8b03b0d365..291c2ee38288 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -211,18 +211,22 @@ cpu15: cpu@10303 {
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-level = <2>;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index 1a16662f8867..b8746fb959b5 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -842,66 +842,82 @@ cpu63: cpu@70303 {
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-level = <2>;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-level = <2>;
};
cluster4_l2: l2-cache4 {
compatible = "cache";
+ cache-level = <2>;
};
cluster5_l2: l2-cache5 {
compatible = "cache";
+ cache-level = <2>;
};
cluster6_l2: l2-cache6 {
compatible = "cache";
+ cache-level = <2>;
};
cluster7_l2: l2-cache7 {
compatible = "cache";
+ cache-level = <2>;
};
cluster8_l2: l2-cache8 {
compatible = "cache";
+ cache-level = <2>;
};
cluster9_l2: l2-cache9 {
compatible = "cache";
+ cache-level = <2>;
};
cluster10_l2: l2-cache10 {
compatible = "cache";
+ cache-level = <2>;
};
cluster11_l2: l2-cache11 {
compatible = "cache";
+ cache-level = <2>;
};
cluster12_l2: l2-cache12 {
compatible = "cache";
+ cache-level = <2>;
};
cluster13_l2: l2-cache13 {
compatible = "cache";
+ cache-level = <2>;
};
cluster14_l2: l2-cache14 {
compatible = "cache";
+ cache-level = <2>;
};
cluster15_l2: l2-cache15 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 10/23] arm64: dts: Update cache properties for lg
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:57 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shijie Qin, Zhou Peng, Peng Fan,
Ming Qian, Shenwei Wang, Adam Ford, Tim Harvey, Lucas Stach,
Richard Zhu, Li Jun, Markus Niebel, Marco Felsch, Marek Vasut,
Laurent Pinchart, Alexander Stein, Paul Elder, Martin Kepplinger,
Joakim Zhang, Joy Zou, David Heidelberg, Liu Ying, Oliver Graute,
Dong Aisheng, Jacky Bai, Wei Fang, Clark Wang, Chris Packham,
Vadym Kochan, Sameer Pujar, Akhil R, Mikko Perttunen,
Sumit Gupta, Prathamesh Shete, Diogo Ivo, Vidya Sagar,
Ashish Mhetre, Johan Jonker, Christopher Obbard, Ezequiel Garcia,
Aswani Reddy, Shashank Prashar, Bharat Uppal, devicetree,
linux-rpi-kernel, linux-arm-kernel, linux-amlogic,
linux-samsung-soc, linux-mediatek, openbmc, linux-tegra,
linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/lg/lg1312.dtsi | 1 +
arch/arm64/boot/dts/lg/lg1313.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi
index 78ae73d0cf36..25ed9aeee2dc 100644
--- a/arch/arm64/boot/dts/lg/lg1312.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
@@ -48,6 +48,7 @@ cpu3: cpu@3 {
};
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi
index 2173316573be..db82fd4cc759 100644
--- a/arch/arm64/boot/dts/lg/lg1313.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
@@ -48,6 +48,7 @@ cpu3: cpu@3 {
};
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 10/23] arm64: dts: Update cache properties for lg
@ 2022-11-07 15:57 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shijie Qin, Zhou Peng, Peng Fan,
Ming Qian, Shenwei Wang, Adam Ford, Tim Harvey, Lucas Stach,
Richard Zhu, Li Jun, Markus Niebel, Marco Felsch, Marek Vasut,
Laurent Pinchart, Alexander Stein, Paul Elder, Martin Kepplinger,
Joakim Zhang, Joy Zou, David Heidelberg, Liu Ying, Oliver Graute,
Dong Aisheng, Jacky Bai, Wei Fang, Clark Wang, Chris Packham,
Vadym Kochan, Sameer Pujar, Akhil R, Mikko Perttunen,
Sumit Gupta, Prathamesh Shete, Diogo Ivo, Vidya Sagar,
Ashish Mhetre, Johan Jonker, Christopher Obbard, Ezequiel Garcia,
Aswani Reddy, Shashank Prashar, Bharat Uppal, devicetree,
linux-rpi-kernel, linux-arm-kernel, linux-amlogic,
linux-samsung-soc, linux-mediatek, openbmc, linux-tegra,
linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/lg/lg1312.dtsi | 1 +
arch/arm64/boot/dts/lg/lg1313.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi
index 78ae73d0cf36..25ed9aeee2dc 100644
--- a/arch/arm64/boot/dts/lg/lg1312.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
@@ -48,6 +48,7 @@ cpu3: cpu@3 {
};
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi
index 2173316573be..db82fd4cc759 100644
--- a/arch/arm64/boot/dts/lg/lg1313.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
@@ -48,6 +48,7 @@ cpu3: cpu@3 {
};
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 11/23] arm64: dts: Update cache properties for marvell
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:57 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Chris Packham, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Peng Fan, Shenwei Wang, Ming Qian,
Lucas Stach, Adam Ford, Tim Harvey, Richard Zhu, Li Jun,
Markus Niebel, Joakim Zhang, Marek Vasut, Laurent Pinchart,
Alexander Stein, Paul Elder, Martin Kepplinger, David Heidelberg,
Liu Ying, Oliver Graute, Shijie Qin, Zhou Peng, Wei Fang,
Jacky Bai, Clark Wang, Vadym Kochan, Sameer Pujar,
Prathamesh Shete, Akhil R, Mikko Perttunen, Sumit Gupta,
Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Bharat Uppal, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
For ac5-98dx25xx.dtsi:
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 +
arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 2 ++
arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 4 ++++
arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 4 ++++
4 files changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
index 44ed6f963b75..7308f7b6b22c 100644
--- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
@@ -49,6 +49,7 @@ cpu1: cpu@1 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
index fcab5173fe67..6713b2ee50c9 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
@@ -48,9 +48,11 @@ cpu1: cpu@1 {
l2: l2-cache {
compatible = "cache";
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
index 3db427122f9e..695c8f070dbc 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
@@ -78,16 +78,20 @@ cpu3: cpu@101 {
l2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
l2_1: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
index 68782f161f12..878d82bb1052 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
@@ -78,16 +78,20 @@ cpu3: cpu@101 {
l2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
l2_1: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 11/23] arm64: dts: Update cache properties for marvell
@ 2022-11-07 15:57 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Chris Packham, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Peng Fan, Shenwei Wang, Ming Qian,
Lucas Stach, Adam Ford, Tim Harvey, Richard Zhu, Li Jun,
Markus Niebel, Joakim Zhang, Marek Vasut, Laurent Pinchart,
Alexander Stein, Paul Elder, Martin Kepplinger, David Heidelberg,
Liu Ying, Oliver Graute, Shijie Qin, Zhou Peng, Wei Fang,
Jacky Bai, Clark Wang, Vadym Kochan, Sameer Pujar,
Prathamesh Shete, Akhil R, Mikko Perttunen, Sumit Gupta,
Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Bharat Uppal, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
For ac5-98dx25xx.dtsi:
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 +
arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 2 ++
arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 4 ++++
arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 4 ++++
4 files changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
index 44ed6f963b75..7308f7b6b22c 100644
--- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
@@ -49,6 +49,7 @@ cpu1: cpu@1 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
index fcab5173fe67..6713b2ee50c9 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
@@ -48,9 +48,11 @@ cpu1: cpu@1 {
l2: l2-cache {
compatible = "cache";
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
index 3db427122f9e..695c8f070dbc 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
@@ -78,16 +78,20 @@ cpu3: cpu@101 {
l2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
l2_1: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
index 68782f161f12..878d82bb1052 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
@@ -78,16 +78,20 @@ cpu3: cpu@101 {
l2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
l2_1: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
};
};
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 12/23] arm64: dts: Update cache properties for mediatek
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:57 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shenwei Wang, Ming Qian, Peng Fan,
Adam Ford, Lucas Stach, Tim Harvey, Li Jun, Richard Zhu,
Markus Niebel, Joakim Zhang, Marek Vasut, Laurent Pinchart,
Alexander Stein, Paul Elder, Martin Kepplinger, David Heidelberg,
Liu Ying, Oliver Graute, Zhou Peng, Wei Fang, Clark Wang,
Jacky Bai, Chris Packham, Vadym Kochan, Sameer Pujar,
Prathamesh Shete, Akhil R, Mikko Perttunen, Sumit Gupta,
Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Bharat Uppal, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 3 +++
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 3 +++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 +++
3 files changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 64693c17af9e..c326aeb33a10 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -198,16 +198,19 @@ cluster_off_b: cluster-off-b {
l2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 6b20376191a7..424fc89cc6f7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -169,16 +169,19 @@ core3 {
l2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
idle-states {
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 905d1a90b406..cb74905cfbb8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -213,16 +213,19 @@ cluster_off_b: cluster-off-b {
l2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 12/23] arm64: dts: Update cache properties for mediatek
@ 2022-11-07 15:57 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shenwei Wang, Ming Qian, Peng Fan,
Adam Ford, Lucas Stach, Tim Harvey, Li Jun, Richard Zhu,
Markus Niebel, Joakim Zhang, Marek Vasut, Laurent Pinchart,
Alexander Stein, Paul Elder, Martin Kepplinger, David Heidelberg,
Liu Ying, Oliver Graute, Zhou Peng, Wei Fang, Clark Wang,
Jacky Bai, Chris Packham, Vadym Kochan, Sameer Pujar,
Prathamesh Shete, Akhil R, Mikko Perttunen, Sumit Gupta,
Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Bharat Uppal, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 3 +++
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 3 +++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 +++
3 files changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 64693c17af9e..c326aeb33a10 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -198,16 +198,19 @@ cluster_off_b: cluster-off-b {
l2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 6b20376191a7..424fc89cc6f7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -169,16 +169,19 @@ core3 {
l2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
idle-states {
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 905d1a90b406..cb74905cfbb8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -213,16 +213,19 @@ cluster_off_b: cluster-off-b {
l2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 13/23] arm64: dts: Update cache properties for microchip
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:57 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Peng Fan, Ming Qian, Shenwei Wang,
Adam Ford, Tim Harvey, Lucas Stach, Richard Zhu, Li Jun,
Markus Niebel, Joakim Zhang, Marek Vasut, Laurent Pinchart,
Alexander Stein, Paul Elder, Martin Kepplinger, David Heidelberg,
Joy Zou, Oliver Graute, Liu Ying, Zhou Peng, Shijie Qin,
Wei Fang, Jacky Bai, Clark Wang, Chris Packham, Vadym Kochan,
Sameer Pujar, Akhil R, Mikko Perttunen, Prathamesh Shete,
Sumit Gupta, Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Arnd Bergmann, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 2dd5e38820b1..c4bca23b96b9 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -52,6 +52,7 @@ cpu1: cpu@1 {
};
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 13/23] arm64: dts: Update cache properties for microchip
@ 2022-11-07 15:57 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Peng Fan, Ming Qian, Shenwei Wang,
Adam Ford, Tim Harvey, Lucas Stach, Richard Zhu, Li Jun,
Markus Niebel, Joakim Zhang, Marek Vasut, Laurent Pinchart,
Alexander Stein, Paul Elder, Martin Kepplinger, David Heidelberg,
Joy Zou, Oliver Graute, Liu Ying, Zhou Peng, Shijie Qin,
Wei Fang, Jacky Bai, Clark Wang, Chris Packham, Vadym Kochan,
Sameer Pujar, Akhil R, Mikko Perttunen, Prathamesh Shete,
Sumit Gupta, Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Arnd Bergmann, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 2dd5e38820b1..c4bca23b96b9 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -52,6 +52,7 @@ cpu1: cpu@1 {
};
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 14/23] arm64: dts: Update cache properties for nuvoton
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:57 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shijie Qin, Zhou Peng, Shenwei Wang,
Peng Fan, Ming Qian, Lucas Stach, Adam Ford, Tim Harvey,
Richard Zhu, Li Jun, Markus Niebel, Joakim Zhang, Marek Vasut,
Laurent Pinchart, Paul Elder, Alexander Stein, Martin Kepplinger,
David Heidelberg, Oliver Graute, Liu Ying, Jacky Bai, Clark Wang,
Chris Packham, Vadym Kochan, Sameer Pujar, Mikko Perttunen,
Prathamesh Shete, Akhil R, Sumit Gupta, Diogo Ivo, Vidya Sagar,
Ashish Mhetre, Johan Jonker, Christopher Obbard, Ezequiel Garcia,
Aswani Reddy, Shashank Prashar, Bharat Uppal, devicetree,
linux-rpi-kernel, linux-arm-kernel, linux-amlogic,
linux-samsung-soc, linux-mediatek, openbmc, linux-tegra,
linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
index 12118b75c0e6..4c196140634b 100644
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
@@ -49,6 +49,7 @@ cpu3: cpu@3 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 14/23] arm64: dts: Update cache properties for nuvoton
@ 2022-11-07 15:57 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shijie Qin, Zhou Peng, Shenwei Wang,
Peng Fan, Ming Qian, Lucas Stach, Adam Ford, Tim Harvey,
Richard Zhu, Li Jun, Markus Niebel, Joakim Zhang, Marek Vasut,
Laurent Pinchart, Paul Elder, Alexander Stein, Martin Kepplinger,
David Heidelberg, Oliver Graute, Liu Ying, Jacky Bai, Clark Wang,
Chris Packham, Vadym Kochan, Sameer Pujar, Mikko Perttunen,
Prathamesh Shete, Akhil R, Sumit Gupta, Diogo Ivo, Vidya Sagar,
Ashish Mhetre, Johan Jonker, Christopher Obbard, Ezequiel Garcia,
Aswani Reddy, Shashank Prashar, Bharat Uppal, devicetree,
linux-rpi-kernel, linux-arm-kernel, linux-amlogic,
linux-samsung-soc, linux-mediatek, openbmc, linux-tegra,
linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
index 12118b75c0e6..4c196140634b 100644
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
@@ -49,6 +49,7 @@ cpu3: cpu@3 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 15/23] arm64: dts: Update cache properties for nvidia
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:57 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shenwei Wang, Shijie Qin, Ming Qian,
Peng Fan, Tim Harvey, Adam Ford, Lucas Stach, Li Jun,
Richard Zhu, Markus Niebel, Joakim Zhang, Marek Vasut,
Laurent Pinchart, Alexander Stein, Paul Elder, Martin Kepplinger,
Joy Zou, David Heidelberg, Oliver Graute, Liu Ying, Ahmad Fatoum,
Wei Fang, Clark Wang, Jacky Bai, Chris Packham, Vadym Kochan,
Sameer Pujar, Prathamesh Shete, Akhil R, Mikko Perttunen,
Sumit Gupta, Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Bharat Uppal, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 15 +++++++++++
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 +
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 33 ++++++++++++++++++++++++
3 files changed, 49 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 41f3a7e188d0..ed2a534dcfd6 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -3029,36 +3029,51 @@ core1 {
};
l2c_0: l2-cache0 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <2>;
next-level-cache = <&l3c>;
};
l2c_1: l2-cache1 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <2>;
next-level-cache = <&l3c>;
};
l2c_2: l2-cache2 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <2>;
next-level-cache = <&l3c>;
};
l2c_3: l2-cache3 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <2>;
next-level-cache = <&l3c>;
};
l3c: l3-cache {
+ compatible = "cache";
+ cache-unified;
cache-size = <4194304>;
cache-line-size = <64>;
+ cache-level = <3>;
cache-sets = <4096>;
};
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 724e87450605..9474b0da0a3e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -2005,6 +2005,7 @@ CPU_SLEEP: cpu-sleep {
L2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 0170bfa8a467..583c12444124 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -2905,117 +2905,150 @@ core3 {
};
l2c0_0: l2-cache00 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c0>;
};
l2c0_1: l2-cache01 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c0>;
};
l2c0_2: l2-cache02 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c0>;
};
l2c0_3: l2-cache03 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c0>;
};
l2c1_0: l2-cache10 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c1>;
};
l2c1_1: l2-cache11 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c1>;
};
l2c1_2: l2-cache12 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c1>;
};
l2c1_3: l2-cache13 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c1>;
};
l2c2_0: l2-cache20 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c2>;
};
l2c2_1: l2-cache21 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c2>;
};
l2c2_2: l2-cache22 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c2>;
};
l2c2_3: l2-cache23 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c2>;
};
l3c0: l3-cache0 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <3>;
};
l3c1: l3-cache1 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <3>;
};
l3c2: l3-cache2 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <3>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 15/23] arm64: dts: Update cache properties for nvidia
@ 2022-11-07 15:57 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shenwei Wang, Shijie Qin, Ming Qian,
Peng Fan, Tim Harvey, Adam Ford, Lucas Stach, Li Jun,
Richard Zhu, Markus Niebel, Joakim Zhang, Marek Vasut,
Laurent Pinchart, Alexander Stein, Paul Elder, Martin Kepplinger,
Joy Zou, David Heidelberg, Oliver Graute, Liu Ying, Ahmad Fatoum,
Wei Fang, Clark Wang, Jacky Bai, Chris Packham, Vadym Kochan,
Sameer Pujar, Prathamesh Shete, Akhil R, Mikko Perttunen,
Sumit Gupta, Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Bharat Uppal, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 15 +++++++++++
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 +
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 33 ++++++++++++++++++++++++
3 files changed, 49 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 41f3a7e188d0..ed2a534dcfd6 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -3029,36 +3029,51 @@ core1 {
};
l2c_0: l2-cache0 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <2>;
next-level-cache = <&l3c>;
};
l2c_1: l2-cache1 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <2>;
next-level-cache = <&l3c>;
};
l2c_2: l2-cache2 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <2>;
next-level-cache = <&l3c>;
};
l2c_3: l2-cache3 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <2>;
next-level-cache = <&l3c>;
};
l3c: l3-cache {
+ compatible = "cache";
+ cache-unified;
cache-size = <4194304>;
cache-line-size = <64>;
+ cache-level = <3>;
cache-sets = <4096>;
};
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 724e87450605..9474b0da0a3e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -2005,6 +2005,7 @@ CPU_SLEEP: cpu-sleep {
L2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 0170bfa8a467..583c12444124 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -2905,117 +2905,150 @@ core3 {
};
l2c0_0: l2-cache00 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c0>;
};
l2c0_1: l2-cache01 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c0>;
};
l2c0_2: l2-cache02 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c0>;
};
l2c0_3: l2-cache03 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c0>;
};
l2c1_0: l2-cache10 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c1>;
};
l2c1_1: l2-cache11 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c1>;
};
l2c1_2: l2-cache12 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c1>;
};
l2c1_3: l2-cache13 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c1>;
};
l2c2_0: l2-cache20 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c2>;
};
l2c2_1: l2-cache21 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c2>;
};
l2c2_2: l2-cache22 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c2>;
};
l2c2_3: l2-cache23 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c2>;
};
l3c0: l3-cache0 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <3>;
};
l3c1: l3-cache1 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <3>;
};
l3c2: l3-cache2 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <3>;
};
};
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 16/23] arm64: dts: Update cache properties for qcom
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:57 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Zhou Peng, Shenwei Wang, Ming Qian,
Peng Fan, Adam Ford, Tim Harvey, Lucas Stach, Richard Zhu,
Li Jun, Markus Niebel, Marco Felsch, Marek Vasut,
Laurent Pinchart, Joakim Zhang, Paul Elder, Alexander Stein,
Martin Kepplinger, David Heidelberg, Liu Ying, Oliver Graute,
Shijie Qin, Clark Wang, Wei Fang, Jacky Bai, Chris Packham,
Vadym Kochan, Sameer Pujar, Akhil R, Prathamesh Shete,
Sumit Gupta, Diogo Ivo, Mikko Perttunen, Vidya Sagar,
Ashish Mhetre, Johan Jonker, Christopher Obbard, Ezequiel Garcia,
Aswani Reddy, Shashank Prashar, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
About msm8953.dtsi:
According to the Devicetree Specification v0.3,
s3.7.3 'Internal (L1) Cache Properties',
cache-unified:
If present, specifies the cache has a unified or-
ganization. If not present, specifies that the
cache has a Harvard architecture with separate
caches for instructions and data.
Plus, the 'cache-level' property seems to be reserved to higher
cache levels (cf s3.8).
To describe a l1 data/instruction cache couple, no cache
information should be described. Remove the l1 cache nodes.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/qcom/msm8953.dtsi | 56 --------------------------
arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 +++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 9 +++++
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++++
arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +
arch/arm64/boot/dts/qcom/sm6350.dtsi | 9 +++++
arch/arm64/boot/dts/qcom/sm8150.dtsi | 9 +++++
arch/arm64/boot/dts/qcom/sm8250.dtsi | 9 +++++
arch/arm64/boot/dts/qcom/sm8350.dtsi | 9 +++++
arch/arm64/boot/dts/qcom/sm8450.dtsi | 9 +++++
11 files changed, 83 insertions(+), 56 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index 6b992a6d56c1..a07b7a45b9e5 100644
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -42,13 +42,6 @@ CPU0: cpu@0 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
-
- l1-icache {
- compatible = "cache";
- };
- l1-dcache {
- compatible = "cache";
- };
};
CPU1: cpu@1 {
@@ -59,13 +52,6 @@ CPU1: cpu@1 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
-
- l1-icache {
- compatible = "cache";
- };
- l1-dcache {
- compatible = "cache";
- };
};
CPU2: cpu@2 {
@@ -76,13 +62,6 @@ CPU2: cpu@2 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
-
- l1-icache {
- compatible = "cache";
- };
- l1-dcache {
- compatible = "cache";
- };
};
CPU3: cpu@3 {
@@ -93,13 +72,6 @@ CPU3: cpu@3 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
-
- l1-icache {
- compatible = "cache";
- };
- l1-dcache {
- compatible = "cache";
- };
};
CPU4: cpu@100 {
@@ -110,13 +82,6 @@ CPU4: cpu@100 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
-
- l1-icache {
- compatible = "cache";
- };
- l1-dcache {
- compatible = "cache";
- };
};
CPU5: cpu@101 {
@@ -127,13 +92,6 @@ CPU5: cpu@101 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
-
- l1-icache {
- compatible = "cache";
- };
- l1-dcache {
- compatible = "cache";
- };
};
CPU6: cpu@102 {
@@ -144,13 +102,6 @@ CPU6: cpu@102 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
-
- l1-icache {
- compatible = "cache";
- };
- l1-dcache {
- compatible = "cache";
- };
};
CPU7: cpu@103 {
@@ -161,13 +112,6 @@ CPU7: cpu@103 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
-
- l1-icache {
- compatible = "cache";
- };
- l1-dcache {
- compatible = "cache";
- };
};
cpu-map {
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 58976a1ba06b..ecda96d19861 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -146,9 +146,11 @@ &LITTLE_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 0>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
};
@@ -171,6 +173,7 @@ &LITTLE_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 0>;
L2_100: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -193,6 +196,7 @@ &LITTLE_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 0>;
L2_200: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -215,6 +219,7 @@ &LITTLE_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 0>;
L2_300: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -237,6 +242,7 @@ &LITTLE_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 0>;
L2_400: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -259,6 +265,7 @@ &LITTLE_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 0>;
L2_500: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -281,6 +288,7 @@ &BIG_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 1>;
L2_600: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -303,6 +311,7 @@ &BIG_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 1>;
L2_700: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 212580316d3e..2476e494a5a9 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -180,9 +180,11 @@ &LITTLE_CPU_SLEEP_1
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
};
@@ -203,6 +205,7 @@ &LITTLE_CPU_SLEEP_1
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -223,6 +226,7 @@ &LITTLE_CPU_SLEEP_1
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -243,6 +247,7 @@ &LITTLE_CPU_SLEEP_1
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -263,6 +268,7 @@ &BIG_CPU_SLEEP_1
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -283,6 +289,7 @@ &BIG_CPU_SLEEP_1
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -303,6 +310,7 @@ &BIG_CPU_SLEEP_1
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -323,6 +331,7 @@ &BIG_CPU_SLEEP_1
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index c32bcded2aef..8acb037d77a2 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -188,9 +188,11 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
};
@@ -209,6 +211,7 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -227,6 +230,7 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -245,6 +249,7 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -263,6 +268,7 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -281,6 +287,7 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -299,6 +306,7 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -317,6 +325,7 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index d761da47220d..52bccd705bee 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -209,9 +209,11 @@ CPU0: cpu@0 {
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
};
@@ -233,6 +235,7 @@ CPU1: cpu@100 {
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -254,6 +257,7 @@ CPU2: cpu@200 {
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -275,6 +279,7 @@ CPU3: cpu@300 {
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -296,6 +301,7 @@ CPU4: cpu@400 {
next-level-cache = <&L2_400>;
L2_400: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -317,6 +323,7 @@ CPU5: cpu@500 {
next-level-cache = <&L2_500>;
L2_500: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -338,6 +345,7 @@ CPU6: cpu@600 {
next-level-cache = <&L2_600>;
L2_600: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -359,6 +367,7 @@ CPU7: cpu@700 {
next-level-cache = <&L2_700>;
L2_700: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 1fe3fa3ad877..7768db00e698 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -45,6 +45,7 @@ CPU0: cpu@0 {
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
@@ -84,6 +85,7 @@ CPU4: cpu@100 {
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index c39de7d3ace0..b9e5de93bbda 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -50,9 +50,11 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
};
@@ -69,6 +71,7 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -85,6 +88,7 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -101,6 +105,7 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -117,6 +122,7 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -133,6 +139,7 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -150,6 +157,7 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -166,6 +174,7 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index cef8c4f4f0ff..03168a47d007 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -60,9 +60,11 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
};
@@ -84,6 +86,7 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -106,6 +109,7 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -127,6 +131,7 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -148,6 +153,7 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -169,6 +175,7 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -190,6 +197,7 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -211,6 +219,7 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index a5b62cadb129..1cf3a569989d 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -110,9 +110,11 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
};
@@ -134,6 +136,7 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -155,6 +158,7 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -176,6 +180,7 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -197,6 +202,7 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -218,6 +224,7 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -240,6 +247,7 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -261,6 +269,7 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index a86d9ea93b9d..545bc1774f74 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -73,9 +73,11 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
};
@@ -92,6 +94,7 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -108,6 +111,7 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -124,6 +128,7 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -140,6 +145,7 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -156,6 +162,7 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -173,6 +180,7 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -189,6 +197,7 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index d32f08df743d..3292f5fbf44d 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -53,9 +53,11 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
};
@@ -72,6 +74,7 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -88,6 +91,7 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -104,6 +108,7 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -120,6 +125,7 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -136,6 +142,7 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -153,6 +160,7 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -169,6 +177,7 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 16/23] arm64: dts: Update cache properties for qcom
@ 2022-11-07 15:57 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Zhou Peng, Shenwei Wang, Ming Qian,
Peng Fan, Adam Ford, Tim Harvey, Lucas Stach, Richard Zhu,
Li Jun, Markus Niebel, Marco Felsch, Marek Vasut,
Laurent Pinchart, Joakim Zhang, Paul Elder, Alexander Stein,
Martin Kepplinger, David Heidelberg, Liu Ying, Oliver Graute,
Shijie Qin, Clark Wang, Wei Fang, Jacky Bai, Chris Packham,
Vadym Kochan, Sameer Pujar, Akhil R, Prathamesh Shete,
Sumit Gupta, Diogo Ivo, Mikko Perttunen, Vidya Sagar,
Ashish Mhetre, Johan Jonker, Christopher Obbard, Ezequiel Garcia,
Aswani Reddy, Shashank Prashar, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
About msm8953.dtsi:
According to the Devicetree Specification v0.3,
s3.7.3 'Internal (L1) Cache Properties',
cache-unified:
If present, specifies the cache has a unified or-
ganization. If not present, specifies that the
cache has a Harvard architecture with separate
caches for instructions and data.
Plus, the 'cache-level' property seems to be reserved to higher
cache levels (cf s3.8).
To describe a l1 data/instruction cache couple, no cache
information should be described. Remove the l1 cache nodes.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/qcom/msm8953.dtsi | 56 --------------------------
arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 +++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 9 +++++
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++++
arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +
arch/arm64/boot/dts/qcom/sm6350.dtsi | 9 +++++
arch/arm64/boot/dts/qcom/sm8150.dtsi | 9 +++++
arch/arm64/boot/dts/qcom/sm8250.dtsi | 9 +++++
arch/arm64/boot/dts/qcom/sm8350.dtsi | 9 +++++
arch/arm64/boot/dts/qcom/sm8450.dtsi | 9 +++++
11 files changed, 83 insertions(+), 56 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index 6b992a6d56c1..a07b7a45b9e5 100644
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -42,13 +42,6 @@ CPU0: cpu@0 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
-
- l1-icache {
- compatible = "cache";
- };
- l1-dcache {
- compatible = "cache";
- };
};
CPU1: cpu@1 {
@@ -59,13 +52,6 @@ CPU1: cpu@1 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
-
- l1-icache {
- compatible = "cache";
- };
- l1-dcache {
- compatible = "cache";
- };
};
CPU2: cpu@2 {
@@ -76,13 +62,6 @@ CPU2: cpu@2 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
-
- l1-icache {
- compatible = "cache";
- };
- l1-dcache {
- compatible = "cache";
- };
};
CPU3: cpu@3 {
@@ -93,13 +72,6 @@ CPU3: cpu@3 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
-
- l1-icache {
- compatible = "cache";
- };
- l1-dcache {
- compatible = "cache";
- };
};
CPU4: cpu@100 {
@@ -110,13 +82,6 @@ CPU4: cpu@100 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
-
- l1-icache {
- compatible = "cache";
- };
- l1-dcache {
- compatible = "cache";
- };
};
CPU5: cpu@101 {
@@ -127,13 +92,6 @@ CPU5: cpu@101 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
-
- l1-icache {
- compatible = "cache";
- };
- l1-dcache {
- compatible = "cache";
- };
};
CPU6: cpu@102 {
@@ -144,13 +102,6 @@ CPU6: cpu@102 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
-
- l1-icache {
- compatible = "cache";
- };
- l1-dcache {
- compatible = "cache";
- };
};
CPU7: cpu@103 {
@@ -161,13 +112,6 @@ CPU7: cpu@103 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
-
- l1-icache {
- compatible = "cache";
- };
- l1-dcache {
- compatible = "cache";
- };
};
cpu-map {
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 58976a1ba06b..ecda96d19861 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -146,9 +146,11 @@ &LITTLE_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 0>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
};
@@ -171,6 +173,7 @@ &LITTLE_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 0>;
L2_100: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -193,6 +196,7 @@ &LITTLE_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 0>;
L2_200: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -215,6 +219,7 @@ &LITTLE_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 0>;
L2_300: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -237,6 +242,7 @@ &LITTLE_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 0>;
L2_400: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -259,6 +265,7 @@ &LITTLE_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 0>;
L2_500: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -281,6 +288,7 @@ &BIG_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 1>;
L2_600: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -303,6 +311,7 @@ &BIG_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 1>;
L2_700: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 212580316d3e..2476e494a5a9 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -180,9 +180,11 @@ &LITTLE_CPU_SLEEP_1
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
};
@@ -203,6 +205,7 @@ &LITTLE_CPU_SLEEP_1
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -223,6 +226,7 @@ &LITTLE_CPU_SLEEP_1
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -243,6 +247,7 @@ &LITTLE_CPU_SLEEP_1
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -263,6 +268,7 @@ &BIG_CPU_SLEEP_1
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -283,6 +289,7 @@ &BIG_CPU_SLEEP_1
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -303,6 +310,7 @@ &BIG_CPU_SLEEP_1
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -323,6 +331,7 @@ &BIG_CPU_SLEEP_1
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index c32bcded2aef..8acb037d77a2 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -188,9 +188,11 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
};
@@ -209,6 +211,7 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -227,6 +230,7 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -245,6 +249,7 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -263,6 +268,7 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -281,6 +287,7 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -299,6 +306,7 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -317,6 +325,7 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index d761da47220d..52bccd705bee 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -209,9 +209,11 @@ CPU0: cpu@0 {
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
};
@@ -233,6 +235,7 @@ CPU1: cpu@100 {
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -254,6 +257,7 @@ CPU2: cpu@200 {
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -275,6 +279,7 @@ CPU3: cpu@300 {
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -296,6 +301,7 @@ CPU4: cpu@400 {
next-level-cache = <&L2_400>;
L2_400: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -317,6 +323,7 @@ CPU5: cpu@500 {
next-level-cache = <&L2_500>;
L2_500: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -338,6 +345,7 @@ CPU6: cpu@600 {
next-level-cache = <&L2_600>;
L2_600: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -359,6 +367,7 @@ CPU7: cpu@700 {
next-level-cache = <&L2_700>;
L2_700: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 1fe3fa3ad877..7768db00e698 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -45,6 +45,7 @@ CPU0: cpu@0 {
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
@@ -84,6 +85,7 @@ CPU4: cpu@100 {
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index c39de7d3ace0..b9e5de93bbda 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -50,9 +50,11 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
};
@@ -69,6 +71,7 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -85,6 +88,7 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -101,6 +105,7 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -117,6 +122,7 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -133,6 +139,7 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -150,6 +157,7 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -166,6 +174,7 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index cef8c4f4f0ff..03168a47d007 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -60,9 +60,11 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
};
@@ -84,6 +86,7 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -106,6 +109,7 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -127,6 +131,7 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -148,6 +153,7 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -169,6 +175,7 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -190,6 +197,7 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -211,6 +219,7 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index a5b62cadb129..1cf3a569989d 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -110,9 +110,11 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
};
@@ -134,6 +136,7 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -155,6 +158,7 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -176,6 +180,7 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -197,6 +202,7 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -218,6 +224,7 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -240,6 +247,7 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -261,6 +269,7 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index a86d9ea93b9d..545bc1774f74 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -73,9 +73,11 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
};
@@ -92,6 +94,7 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -108,6 +111,7 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -124,6 +128,7 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -140,6 +145,7 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -156,6 +162,7 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -173,6 +180,7 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -189,6 +197,7 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index d32f08df743d..3292f5fbf44d 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -53,9 +53,11 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
};
@@ -72,6 +74,7 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -88,6 +91,7 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -104,6 +108,7 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -120,6 +125,7 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -136,6 +142,7 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -153,6 +160,7 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -169,6 +177,7 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 17/23] arm64: dts: Update cache properties for realtek
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:57 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shenwei Wang, Peng Fan, Ming Qian,
Lucas Stach, Tim Harvey, Adam Ford, Li Jun, Richard Zhu,
Marek Vasut, Markus Niebel, Joakim Zhang, Laurent Pinchart,
Paul Elder, Alexander Stein, Martin Kepplinger, David Heidelberg,
Liu Ying, Oliver Graute, Shijie Qin, Clark Wang, Haibo Chen,
Wei Fang, Jacky Bai, Chris Packham, Vadym Kochan, Sameer Pujar,
Mikko Perttunen, Akhil R, Prathamesh Shete, Sumit Gupta,
Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Arjun K V, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/realtek/rtd1293.dtsi | 1 +
arch/arm64/boot/dts/realtek/rtd1295.dtsi | 1 +
arch/arm64/boot/dts/realtek/rtd1296.dtsi | 1 +
arch/arm64/boot/dts/realtek/rtd1395.dtsi | 1 +
arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 2 ++
5 files changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/realtek/rtd1293.dtsi b/arch/arm64/boot/dts/realtek/rtd1293.dtsi
index 2d92b56ac94d..0696b99fc40d 100644
--- a/arch/arm64/boot/dts/realtek/rtd1293.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd1293.dtsi
@@ -30,6 +30,7 @@ cpu1: cpu@1 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
index 1402abe80ea1..4ca322e420e6 100644
--- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
@@ -44,6 +44,7 @@ cpu3: cpu@3 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/realtek/rtd1296.dtsi b/arch/arm64/boot/dts/realtek/rtd1296.dtsi
index fb864a139c97..03fccd48f0c0 100644
--- a/arch/arm64/boot/dts/realtek/rtd1296.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd1296.dtsi
@@ -44,6 +44,7 @@ cpu3: cpu@3 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/realtek/rtd1395.dtsi b/arch/arm64/boot/dts/realtek/rtd1395.dtsi
index 05c9216a87ee..94c0a8cf4953 100644
--- a/arch/arm64/boot/dts/realtek/rtd1395.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd1395.dtsi
@@ -44,6 +44,7 @@ cpu3: cpu@3 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
index afba5f04c8ec..2ee9ba1ecdc1 100644
--- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
@@ -87,12 +87,14 @@ cpu5: cpu@500 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&l3>;
};
l3: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 17/23] arm64: dts: Update cache properties for realtek
@ 2022-11-07 15:57 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shenwei Wang, Peng Fan, Ming Qian,
Lucas Stach, Tim Harvey, Adam Ford, Li Jun, Richard Zhu,
Marek Vasut, Markus Niebel, Joakim Zhang, Laurent Pinchart,
Paul Elder, Alexander Stein, Martin Kepplinger, David Heidelberg,
Liu Ying, Oliver Graute, Shijie Qin, Clark Wang, Haibo Chen,
Wei Fang, Jacky Bai, Chris Packham, Vadym Kochan, Sameer Pujar,
Mikko Perttunen, Akhil R, Prathamesh Shete, Sumit Gupta,
Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Arjun K V, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/realtek/rtd1293.dtsi | 1 +
arch/arm64/boot/dts/realtek/rtd1295.dtsi | 1 +
arch/arm64/boot/dts/realtek/rtd1296.dtsi | 1 +
arch/arm64/boot/dts/realtek/rtd1395.dtsi | 1 +
arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 2 ++
5 files changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/realtek/rtd1293.dtsi b/arch/arm64/boot/dts/realtek/rtd1293.dtsi
index 2d92b56ac94d..0696b99fc40d 100644
--- a/arch/arm64/boot/dts/realtek/rtd1293.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd1293.dtsi
@@ -30,6 +30,7 @@ cpu1: cpu@1 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
index 1402abe80ea1..4ca322e420e6 100644
--- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
@@ -44,6 +44,7 @@ cpu3: cpu@3 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/realtek/rtd1296.dtsi b/arch/arm64/boot/dts/realtek/rtd1296.dtsi
index fb864a139c97..03fccd48f0c0 100644
--- a/arch/arm64/boot/dts/realtek/rtd1296.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd1296.dtsi
@@ -44,6 +44,7 @@ cpu3: cpu@3 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/realtek/rtd1395.dtsi b/arch/arm64/boot/dts/realtek/rtd1395.dtsi
index 05c9216a87ee..94c0a8cf4953 100644
--- a/arch/arm64/boot/dts/realtek/rtd1395.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd1395.dtsi
@@ -44,6 +44,7 @@ cpu3: cpu@3 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
index afba5f04c8ec..2ee9ba1ecdc1 100644
--- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
@@ -87,12 +87,14 @@ cpu5: cpu@500 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&l3>;
};
l3: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 18/23] arm64: dts: Update cache properties for renesas
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:57 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shenwei Wang, Peng Fan, Ming Qian,
Adam Ford, Lucas Stach, Tim Harvey, Richard Zhu, Li Jun,
Marek Vasut, Markus Niebel, Joakim Zhang, Laurent Pinchart,
Alexander Stein, Paul Elder, Martin Kepplinger, Joy Zou,
David Heidelberg, Liu Ying, Oliver Graute, Shijie Qin, Jacky Bai,
Wei Fang, Clark Wang, Chris Packham, Vadym Kochan, Sameer Pujar,
Prathamesh Shete, Akhil R, Mikko Perttunen, Sumit Gupta,
Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, devicetree, linux-rpi-kernel, linux-arm-kernel,
linux-amlogic, linux-samsung-soc, linux-mediatek, openbmc,
linux-tegra, linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 1 +
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 1 +
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 1 +
3 files changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 689aa4ba416b..18c69a187ecb 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -88,6 +88,7 @@ L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x40000>;
+ cache-level = <3>;
};
};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 2283d4fb8736..86866d9dc7c4 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -109,6 +109,7 @@ L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x40000>;
+ cache-level = <3>;
};
};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 358d4c34465f..b36dd5291e5a 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -109,6 +109,7 @@ L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x40000>;
+ cache-level = <3>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 18/23] arm64: dts: Update cache properties for renesas
@ 2022-11-07 15:57 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shenwei Wang, Peng Fan, Ming Qian,
Adam Ford, Lucas Stach, Tim Harvey, Richard Zhu, Li Jun,
Marek Vasut, Markus Niebel, Joakim Zhang, Laurent Pinchart,
Alexander Stein, Paul Elder, Martin Kepplinger, Joy Zou,
David Heidelberg, Liu Ying, Oliver Graute, Shijie Qin, Jacky Bai,
Wei Fang, Clark Wang, Chris Packham, Vadym Kochan, Sameer Pujar,
Prathamesh Shete, Akhil R, Mikko Perttunen, Sumit Gupta,
Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, devicetree, linux-rpi-kernel, linux-arm-kernel,
linux-amlogic, linux-samsung-soc, linux-mediatek, openbmc,
linux-tegra, linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 1 +
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 1 +
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 1 +
3 files changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 689aa4ba416b..18c69a187ecb 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -88,6 +88,7 @@ L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x40000>;
+ cache-level = <3>;
};
};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 2283d4fb8736..86866d9dc7c4 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -109,6 +109,7 @@ L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x40000>;
+ cache-level = <3>;
};
};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 358d4c34465f..b36dd5291e5a 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -109,6 +109,7 @@ L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x40000>;
+ cache-level = <3>;
};
};
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 19/23] arm64: dts: Update cache properties for rockchip
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:57 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shijie Qin, Ming Qian, Peng Fan,
Shenwei Wang, Adam Ford, Lucas Stach, Tim Harvey, Li Jun,
Richard Zhu, Joakim Zhang, Markus Niebel, Marek Vasut,
Laurent Pinchart, Paul Elder, Alexander Stein, Martin Kepplinger,
David Heidelberg, Oliver Graute, Liu Ying, Dong Aisheng,
Ahmad Fatoum, Clark Wang, Wei Fang, Jacky Bai, Chris Packham,
Vadym Kochan, Sameer Pujar, Prathamesh Shete, Akhil R,
Sumit Gupta, Diogo Ivo, Mikko Perttunen, Vidya Sagar,
Ashish Mhetre, Johan Jonker, Christopher Obbard, Ezequiel Garcia,
Aswani Reddy, Shashank Prashar, Chandrasekar R, devicetree,
linux-rpi-kernel, linux-arm-kernel, linux-amlogic,
linux-samsung-soc, linux-mediatek, openbmc, linux-tegra,
linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 1 +
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
index 2dfa67f1cd67..dd228a256a32 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -96,6 +96,7 @@ CPU_SLEEP: cpu-sleep {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 49ae15708a0b..8741914cea44 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -102,6 +102,7 @@ CPU_SLEEP: cpu-sleep {
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 19/23] arm64: dts: Update cache properties for rockchip
@ 2022-11-07 15:57 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shijie Qin, Ming Qian, Peng Fan,
Shenwei Wang, Adam Ford, Lucas Stach, Tim Harvey, Li Jun,
Richard Zhu, Joakim Zhang, Markus Niebel, Marek Vasut,
Laurent Pinchart, Paul Elder, Alexander Stein, Martin Kepplinger,
David Heidelberg, Oliver Graute, Liu Ying, Dong Aisheng,
Ahmad Fatoum, Clark Wang, Wei Fang, Jacky Bai, Chris Packham,
Vadym Kochan, Sameer Pujar, Prathamesh Shete, Akhil R,
Sumit Gupta, Diogo Ivo, Mikko Perttunen, Vidya Sagar,
Ashish Mhetre, Johan Jonker, Christopher Obbard, Ezequiel Garcia,
Aswani Reddy, Shashank Prashar, Chandrasekar R, devicetree,
linux-rpi-kernel, linux-arm-kernel, linux-amlogic,
linux-samsung-soc, linux-mediatek, openbmc, linux-tegra,
linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 1 +
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
index 2dfa67f1cd67..dd228a256a32 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -96,6 +96,7 @@ CPU_SLEEP: cpu-sleep {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 49ae15708a0b..8741914cea44 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -102,6 +102,7 @@ CPU_SLEEP: cpu-sleep {
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 20/23] arm64: dts: Update cache properties for socionext
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:57 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shenwei Wang, Shijie Qin, Ming Qian,
Peng Fan, Lucas Stach, Adam Ford, Tim Harvey, Li Jun,
Richard Zhu, Markus Niebel, Marek Vasut, Laurent Pinchart,
Alexander Stein, Paul Elder, Martin Kepplinger, Joakim Zhang,
David Heidelberg, Oliver Graute, Liu Ying, Zhou Peng, Wei Fang,
Clark Wang, Jacky Bai, Chris Packham, Vadym Kochan, Sameer Pujar,
Prathamesh Shete, Akhil R, Mikko Perttunen, Sumit Gupta,
Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Chandrasekar R, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 1 +
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 1 +
3 files changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index 1c76b4375b2e..6e1e00939214 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -52,6 +52,7 @@ cpu1: cpu@1 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 9308458f9611..db7d20a1a301 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -86,10 +86,12 @@ cpu3: cpu@101 {
a72_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
a53_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index b0c29510a7da..9ce544c9ea0a 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -83,6 +83,7 @@ cpu3: cpu@3 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 20/23] arm64: dts: Update cache properties for socionext
@ 2022-11-07 15:57 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shenwei Wang, Shijie Qin, Ming Qian,
Peng Fan, Lucas Stach, Adam Ford, Tim Harvey, Li Jun,
Richard Zhu, Markus Niebel, Marek Vasut, Laurent Pinchart,
Alexander Stein, Paul Elder, Martin Kepplinger, Joakim Zhang,
David Heidelberg, Oliver Graute, Liu Ying, Zhou Peng, Wei Fang,
Clark Wang, Jacky Bai, Chris Packham, Vadym Kochan, Sameer Pujar,
Prathamesh Shete, Akhil R, Mikko Perttunen, Sumit Gupta,
Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Chandrasekar R, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 1 +
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 1 +
3 files changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index 1c76b4375b2e..6e1e00939214 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -52,6 +52,7 @@ cpu1: cpu@1 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 9308458f9611..db7d20a1a301 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -86,10 +86,12 @@ cpu3: cpu@101 {
a72_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
a53_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index b0c29510a7da..9ce544c9ea0a 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -83,6 +83,7 @@ cpu3: cpu@3 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 21/23] arm64: dts: Update cache properties for synaptics
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:57 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Jisheng Zhang, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Viorel Suman,
Abel Vesa, Peng Fan, Shenwei Wang, Ming Qian, Tim Harvey,
Lucas Stach, Adam Ford, Li Jun, Richard Zhu, Markus Niebel,
Marco Felsch, Marek Vasut, Laurent Pinchart, Joakim Zhang,
Paul Elder, Alexander Stein, Martin Kepplinger, Joy Zou,
David Heidelberg, Liu Ying, Oliver Graute, Zhou Peng, Shijie Qin,
Haibo Chen, Jacky Bai, Wei Fang, Clark Wang, Chris Packham,
Vadym Kochan, Sameer Pujar, Mikko Perttunen, Akhil R,
Sumit Gupta, Prathamesh Shete, Diogo Ivo, Vidya Sagar,
Ashish Mhetre, Johan Jonker, Christopher Obbard, Ezequiel Garcia,
Aswani Reddy, Shashank Prashar, Andi Shyti, devicetree,
linux-rpi-kernel, linux-arm-kernel, linux-amlogic,
linux-samsung-soc, linux-mediatek, openbmc, linux-tegra,
linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
index 0949acee4728..926da7e1a6ba 100644
--- a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
+++ b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
@@ -64,6 +64,7 @@ cpu3: cpu@3 {
l2: cache {
compatible = "cache";
+ cache-level = <2>;
};
idle-states {
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 21/23] arm64: dts: Update cache properties for synaptics
@ 2022-11-07 15:57 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Jisheng Zhang, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Viorel Suman,
Abel Vesa, Peng Fan, Shenwei Wang, Ming Qian, Tim Harvey,
Lucas Stach, Adam Ford, Li Jun, Richard Zhu, Markus Niebel,
Marco Felsch, Marek Vasut, Laurent Pinchart, Joakim Zhang,
Paul Elder, Alexander Stein, Martin Kepplinger, Joy Zou,
David Heidelberg, Liu Ying, Oliver Graute, Zhou Peng, Shijie Qin,
Haibo Chen, Jacky Bai, Wei Fang, Clark Wang, Chris Packham,
Vadym Kochan, Sameer Pujar, Mikko Perttunen, Akhil R,
Sumit Gupta, Prathamesh Shete, Diogo Ivo, Vidya Sagar,
Ashish Mhetre, Johan Jonker, Christopher Obbard, Ezequiel Garcia,
Aswani Reddy, Shashank Prashar, Andi Shyti, devicetree,
linux-rpi-kernel, linux-arm-kernel, linux-amlogic,
linux-samsung-soc, linux-mediatek, openbmc, linux-tegra,
linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
index 0949acee4728..926da7e1a6ba 100644
--- a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
+++ b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
@@ -64,6 +64,7 @@ cpu3: cpu@3 {
l2: cache {
compatible = "cache";
+ cache-level = <2>;
};
idle-states {
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 22/23] arm64: dts: Update cache properties for tesla
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:57 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Peng Fan, Zhou Peng, Shenwei Wang,
Ming Qian, Adam Ford, Tim Harvey, Lucas Stach, Li Jun,
Richard Zhu, Markus Niebel, Marek Vasut, Laurent Pinchart,
Joakim Zhang, Alexander Stein, Paul Elder, Martin Kepplinger,
David Heidelberg, Oliver Graute, Liu Ying, Shijie Qin,
Dong Aisheng, Clark Wang, Jacky Bai, Chris Packham, Vadym Kochan,
Sameer Pujar, Mikko Perttunen, Prathamesh Shete, Akhil R,
Sumit Gupta, Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, devicetree, linux-rpi-kernel, linux-arm-kernel,
linux-amlogic, linux-samsung-soc, linux-mediatek, openbmc,
linux-tegra, linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/tesla/fsd.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index f35bc5a288c2..d58d47618c95 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -281,6 +281,8 @@ cpucl2_3: cpu@203 {
cpucl_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
cache-size = <0x400000>;
cache-line-size = <64>;
cache-sets = <4096>;
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 22/23] arm64: dts: Update cache properties for tesla
@ 2022-11-07 15:57 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Peng Fan, Zhou Peng, Shenwei Wang,
Ming Qian, Adam Ford, Tim Harvey, Lucas Stach, Li Jun,
Richard Zhu, Markus Niebel, Marek Vasut, Laurent Pinchart,
Joakim Zhang, Alexander Stein, Paul Elder, Martin Kepplinger,
David Heidelberg, Oliver Graute, Liu Ying, Shijie Qin,
Dong Aisheng, Clark Wang, Jacky Bai, Chris Packham, Vadym Kochan,
Sameer Pujar, Mikko Perttunen, Prathamesh Shete, Akhil R,
Sumit Gupta, Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, devicetree, linux-rpi-kernel, linux-arm-kernel,
linux-amlogic, linux-samsung-soc, linux-mediatek, openbmc,
linux-tegra, linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/tesla/fsd.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index f35bc5a288c2..d58d47618c95 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -281,6 +281,8 @@ cpucl2_3: cpu@203 {
cpucl_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
cache-size = <0x400000>;
cache-line-size = <64>;
cache-sets = <4096>;
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 23/23] arm64: dts: Update cache properties for ti
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 15:57 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Zhou Peng, Shenwei Wang, Peng Fan,
Ming Qian, Tim Harvey, Adam Ford, Lucas Stach, Li Jun,
Richard Zhu, Markus Niebel, Joakim Zhang, Marek Vasut,
Laurent Pinchart, Alexander Stein, Paul Elder, Martin Kepplinger,
David Heidelberg, Oliver Graute, Liu Ying, Wei Fang, Clark Wang,
Jacky Bai, Chris Packham, Vadym Kochan, Sameer Pujar,
Mikko Perttunen, Prathamesh Shete, Akhil R, Sumit Gupta,
Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Arjun K V, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/ti/k3-am625.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am642.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am654.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 1 +
7 files changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi
index 887f31c23fef..7d7e5a1673a2 100644
--- a/arch/arm64/boot/dts/ti/k3-am625.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi
@@ -95,6 +95,7 @@ cpu3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-level = <2>;
cache-size = <0x40000>;
cache-line-size = <64>;
diff --git a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi
index 331d89fda29d..9734549851c0 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi
@@ -95,6 +95,7 @@ cpu3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-level = <2>;
cache-size = <0x40000>;
cache-line-size = <64>;
diff --git a/arch/arm64/boot/dts/ti/k3-am642.dtsi b/arch/arm64/boot/dts/ti/k3-am642.dtsi
index 8a76f4821b11..7a6eedea3aae 100644
--- a/arch/arm64/boot/dts/ti/k3-am642.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am642.dtsi
@@ -58,6 +58,7 @@ cpu1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x40000>;
cache-line-size = <64>;
cache-sets = <256>;
diff --git a/arch/arm64/boot/dts/ti/k3-am654.dtsi b/arch/arm64/boot/dts/ti/k3-am654.dtsi
index a89257900047..4cc329b271ac 100644
--- a/arch/arm64/boot/dts/ti/k3-am654.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am654.dtsi
@@ -93,6 +93,7 @@ cpu3: cpu@101 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
@@ -102,6 +103,7 @@ L2_0: l2-cache0 {
L2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
index b6da0454cc5b..d74f86b0f622 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
@@ -84,6 +84,7 @@ cpu1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index 0e23886c9fd1..6975cae644d9 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -86,6 +86,7 @@ cpu1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
index 7b930a85a29d..78295ee0fee5 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
@@ -69,6 +69,7 @@ cpu1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-level = <2>;
cache-size = <0x100000>;
cache-line-size = <64>;
--
2.25.1
^ permalink raw reply related [flat|nested] 107+ messages in thread
* [PATCH v2 23/23] arm64: dts: Update cache properties for ti
@ 2022-11-07 15:57 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 15:57 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Zhou Peng, Shenwei Wang, Peng Fan,
Ming Qian, Tim Harvey, Adam Ford, Lucas Stach, Li Jun,
Richard Zhu, Markus Niebel, Joakim Zhang, Marek Vasut,
Laurent Pinchart, Alexander Stein, Paul Elder, Martin Kepplinger,
David Heidelberg, Oliver Graute, Liu Ying, Wei Fang, Clark Wang,
Jacky Bai, Chris Packham, Vadym Kochan, Sameer Pujar,
Mikko Perttunen, Prathamesh Shete, Akhil R, Sumit Gupta,
Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Arjun K V, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/ti/k3-am625.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am642.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am654.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 1 +
7 files changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi
index 887f31c23fef..7d7e5a1673a2 100644
--- a/arch/arm64/boot/dts/ti/k3-am625.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi
@@ -95,6 +95,7 @@ cpu3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-level = <2>;
cache-size = <0x40000>;
cache-line-size = <64>;
diff --git a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi
index 331d89fda29d..9734549851c0 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi
@@ -95,6 +95,7 @@ cpu3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-level = <2>;
cache-size = <0x40000>;
cache-line-size = <64>;
diff --git a/arch/arm64/boot/dts/ti/k3-am642.dtsi b/arch/arm64/boot/dts/ti/k3-am642.dtsi
index 8a76f4821b11..7a6eedea3aae 100644
--- a/arch/arm64/boot/dts/ti/k3-am642.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am642.dtsi
@@ -58,6 +58,7 @@ cpu1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x40000>;
cache-line-size = <64>;
cache-sets = <256>;
diff --git a/arch/arm64/boot/dts/ti/k3-am654.dtsi b/arch/arm64/boot/dts/ti/k3-am654.dtsi
index a89257900047..4cc329b271ac 100644
--- a/arch/arm64/boot/dts/ti/k3-am654.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am654.dtsi
@@ -93,6 +93,7 @@ cpu3: cpu@101 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
@@ -102,6 +103,7 @@ L2_0: l2-cache0 {
L2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
index b6da0454cc5b..d74f86b0f622 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
@@ -84,6 +84,7 @@ cpu1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index 0e23886c9fd1..6975cae644d9 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -86,6 +86,7 @@ cpu1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
index 7b930a85a29d..78295ee0fee5 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
@@ -69,6 +69,7 @@ cpu1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-level = <2>;
cache-size = <0x100000>;
cache-line-size = <64>;
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 107+ messages in thread
* Re: (subset) [PATCH v2 00/23] Update cache properties for arm64 DTS
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 17:23 ` Neil Armstrong
-1 siblings, 0 replies; 107+ messages in thread
From: Neil Armstrong @ 2022-11-07 17:23 UTC (permalink / raw)
To: linux-kernel, Pierre Gondois
Cc: Florian Fainelli, Sumit Gupta, Kursad Oney, Clark Wang,
Avi Fishman, Steen Hegelund, Scott Branden, UNGLinuxDriver,
Arjun K V, linux-tegra, William Zhang, Paul Elder,
Andreas Färber, Pengutronix Kernel Team, Ming Qian,
Chris Packham, Sameer Pujar, Nancy Yuen, Diogo Ivo, Joakim Zhang,
Wei Xu, David Heidelberg, Martin Blumenstingl, Liu Ying,
Liviu Dudau, Oliver Graute, Lucas Stach, Vadym Kochan,
Matthias Brugger, openbmc, Lars Povlsen, Thierry Reding, Akhil R,
Viorel Suman, Shenwei Wang, Shawn Guo, Krzysztof Kozlowski,
Alim Akhtar, NXP Linux Team, Li Jun, linux-rpi-kernel,
linux-arm-msm, Vignesh Raghavendra, Sascha Hauer, Tom Lendacky,
Shashank Prashar, Suravee Suthikulpanit, linux-renesas-soc,
Tali Perry, linux-amlogic, Geert Uytterhoeven, Shijie Qin,
Richard Zhu, Lorenzo Pieralisi, Jonathan Hunter, Chester Lin,
Kunihiko Hayashi, Konrad Dybcio, Peng Fan, linux-rockchip,
Rob Herring, Aswani Reddy, Jerome Brunet, Li Yang, Johan Jonker,
linux-mediatek, Masami Hiramatsu, Mikko Perttunen, Kevin Hilman,
Jacky Bai, Ashish Mhetre, Sudeep Holla, Patrick Venture,
Markus Niebel, Tsahee Zidenberg, Bjorn Andersson, Jisheng Zhang,
Ezequiel Garcia, Anand Gore, Khuong Dinh, Brijesh Singh,
Sebastian Hesselbarth, Tim Harvey, Magnus Damm, Vidya Sagar,
linux-arm-kernel, Marco Felsch, Fabio Estevam, Prathamesh Shete,
devicetree, Adam Ford, Tero Kristo, Rafał Miłecki,
Broadcom internal kernel review list, Nishanth Menon,
Martin Kepplinger, Chanho Min, linux-samsung-soc, Marek Vasut,
Andy Gross, Heiko Stuebner, Christopher Obbard, Laurent Pinchart,
Alexander Stein, Abel Vesa, Andrew Lunn, linux-realtek-soc,
Daniel Machon, Benjamin Fair, NXP S32 Linux Team,
Gregory Clement, Tomer Maimon, Antoine Tenart, Ray Jui
Hi,
On Mon, 7 Nov 2022 16:56:53 +0100, Pierre Gondois wrote:
> v2:
> - Update/Add patches for missed cache properties requiring to be
> updated for the following platforns: bcm, amazon, arm, exynos,
> freescale, marvell, mediatek, nvidia, socinext, tesla, ti.
> Missed cache properties were detected using Rob Herring's branch:
> https://github.com/robherring/dt-schema/tree/cache-rework
> - v1 of exynos, tesla were merged.
> - Updated wrong reference in commit message.
> - Added received Rb/Acked-by.
>
> [...]
Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v6.2/arm64-dt)
[03/23] arm64: dts: Update cache properties for amlogic
https://git.kernel.org/amlogic/c/49f65e2eaaf96de1282bb82039386c2d2d04ee53
These changes has been applied on the intermediate git tree [1].
The v6.2/arm64-dt branch will then be sent via a formal Pull Request to the Linux SoC maintainers
for inclusion in their intermediate git branches in order to be sent to Linus during
the next merge window, or sooner if it's a set of fixes.
In the cases of fixes, those will be merged in the current release candidate
kernel and as soon they appear on the Linux master branch they will be
backported to the previous Stable and Long-Stable kernels [2].
The intermediate git branches are merged daily in the linux-next tree [3],
people are encouraged testing these pre-release kernels and report issues on the
relevant mailing-lists.
If problems are discovered on those changes, please submit a signed-off-by revert
patch followed by a corrective changeset.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
[3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
--
Neil
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: (subset) [PATCH v2 00/23] Update cache properties for arm64 DTS
@ 2022-11-07 17:23 ` Neil Armstrong
0 siblings, 0 replies; 107+ messages in thread
From: Neil Armstrong @ 2022-11-07 17:23 UTC (permalink / raw)
To: linux-kernel, Pierre Gondois
Cc: Florian Fainelli, Sumit Gupta, Kursad Oney, Clark Wang,
Avi Fishman, Steen Hegelund, Scott Branden, UNGLinuxDriver,
Arjun K V, linux-tegra, William Zhang, Paul Elder,
Andreas Färber, Pengutronix Kernel Team, Ming Qian,
Chris Packham, Sameer Pujar, Nancy Yuen, Diogo Ivo, Joakim Zhang,
Wei Xu, David Heidelberg, Martin Blumenstingl, Liu Ying,
Liviu Dudau, Oliver Graute, Lucas Stach, Vadym Kochan,
Matthias Brugger, openbmc, Lars Povlsen, Thierry Reding, Akhil R,
Viorel Suman, Shenwei Wang, Shawn Guo, Krzysztof Kozlowski,
Alim Akhtar, NXP Linux Team, Li Jun, linux-rpi-kernel,
linux-arm-msm, Vignesh Raghavendra, Sascha Hauer, Tom Lendacky,
Shashank Prashar, Suravee Suthikulpanit, linux-renesas-soc,
Tali Perry, linux-amlogic, Geert Uytterhoeven, Shijie Qin,
Richard Zhu, Lorenzo Pieralisi, Jonathan Hunter, Chester Lin,
Kunihiko Hayashi, Konrad Dybcio, Peng Fan, linux-rockchip,
Rob Herring, Aswani Reddy, Jerome Brunet, Li Yang, Johan Jonker,
linux-mediatek, Masami Hiramatsu, Mikko Perttunen, Kevin Hilman,
Jacky Bai, Ashish Mhetre, Sudeep Holla, Patrick Venture,
Markus Niebel, Tsahee Zidenberg, Bjorn Andersson, Jisheng Zhang,
Ezequiel Garcia, Anand Gore, Khuong Dinh, Brijesh Singh,
Sebastian Hesselbarth, Tim Harvey, Magnus Damm, Vidya Sagar,
linux-arm-kernel, Marco Felsch, Fabio Estevam, Prathamesh Shete,
devicetree, Adam Ford, Tero Kristo, Rafał Miłecki,
Broadcom internal kernel review list, Nishanth Menon,
Martin Kepplinger, Chanho Min, linux-samsung-soc, Marek Vasut,
Andy Gross, Heiko Stuebner, Christopher Obbard, Laurent Pinchart,
Alexander Stein, Abel Vesa, Andrew Lunn, linux-realtek-soc,
Daniel Machon, Benjamin Fair, NXP S32 Linux Team,
Gregory Clement, Tomer Maimon, Antoine Tenart, Ray Jui
Hi,
On Mon, 7 Nov 2022 16:56:53 +0100, Pierre Gondois wrote:
> v2:
> - Update/Add patches for missed cache properties requiring to be
> updated for the following platforns: bcm, amazon, arm, exynos,
> freescale, marvell, mediatek, nvidia, socinext, tesla, ti.
> Missed cache properties were detected using Rob Herring's branch:
> https://github.com/robherring/dt-schema/tree/cache-rework
> - v1 of exynos, tesla were merged.
> - Updated wrong reference in commit message.
> - Added received Rb/Acked-by.
>
> [...]
Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v6.2/arm64-dt)
[03/23] arm64: dts: Update cache properties for amlogic
https://git.kernel.org/amlogic/c/49f65e2eaaf96de1282bb82039386c2d2d04ee53
These changes has been applied on the intermediate git tree [1].
The v6.2/arm64-dt branch will then be sent via a formal Pull Request to the Linux SoC maintainers
for inclusion in their intermediate git branches in order to be sent to Linus during
the next merge window, or sooner if it's a set of fixes.
In the cases of fixes, those will be merged in the current release candidate
kernel and as soon they appear on the Linux master branch they will be
backported to the previous Stable and Long-Stable kernels [2].
The intermediate git branches are merged daily in the linux-next tree [3],
people are encouraged testing these pre-release kernels and report issues on the
relevant mailing-lists.
If problems are discovered on those changes, please submit a signed-off-by revert
patch followed by a corrective changeset.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
[3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
--
Neil
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 06/23] arm64: dts: Update cache properties for broadcom
2022-11-07 15:56 ` Pierre Gondois
(?)
@ 2022-11-07 17:31 ` Florian Fainelli
2022-11-07 17:58 ` Pierre Gondois
-1 siblings, 1 reply; 107+ messages in thread
From: Florian Fainelli @ 2022-11-07 17:31 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel,
Broadcom internal kernel review list, William Zhang, Rob Herring,
Krzysztof Kozlowski
(way too many recipients, gmail's SMTP server would not allow me to
respond unless I moved most people to BCC now done).
On 11/7/22 07:56, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> Acked-by: William Zhang <william.zhang@broadcom.com>
This looks fine, but incomplete, you seem to have missed:
- adding 'cache-unified' to all of the cache nodes modified in this
patch set that did not have one already
- bcm63148.dtsi, bcm63178.dtsi, bcm6756.dtsi, bcm6846.dtsi,
bcm6855.dtsi, bcm6878.dtsi, bcm47622.dtsi
Thanks
--
Florian
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 07/23] arm64: dts: Update cache properties for exynos
2022-11-07 15:57 ` Pierre Gondois
@ 2022-11-07 17:55 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 107+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-07 17:55 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Nishanth Menon, Tero Kristo, 73, Martin Kepplinger, Liu Ying,
Haibo Chen, Clark Wang, Chris Packham, Vadym Kochan,
Sameer Pujar, Akhil R, Ashish Mhetre, Ezequiel Garcia,
Shashank Prashar, Sriranjani P, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
On 07/11/2022 16:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
Why do you send it again? This was applied.
What is more - you have way too many recipients. Mail servers reject it.
It's impossible even to reply to it...
> cache-sets = <2048>;
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 07/23] arm64: dts: Update cache properties for exynos
@ 2022-11-07 17:55 ` Krzysztof Kozlowski
0 siblings, 0 replies; 107+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-07 17:55 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Nishanth Menon, Tero Kristo, 73, Martin Kepplinger, Liu Ying,
Haibo Chen, Clark Wang, Chris Packham, Vadym Kochan,
Sameer Pujar, Akhil R, Ashish Mhetre, Ezequiel Garcia,
Shashank Prashar, Sriranjani P, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
On 07/11/2022 16:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
Why do you send it again? This was applied.
What is more - you have way too many recipients. Mail servers reject it.
It's impossible even to reply to it...
> cache-sets = <2048>;
Best regards,
Krzysztof
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 22/23] arm64: dts: Update cache properties for tesla
2022-11-07 15:57 ` Pierre Gondois
(?)
@ 2022-11-07 17:56 ` Krzysztof Kozlowski
2022-11-07 18:23 ` Pierre Gondois
-1 siblings, 1 reply; 107+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-07 17:56 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chanho Min, Andrew Lunn,
Sebastian Hesselbarth, Lars Povlsen, Steen Hegelund,
Daniel Machon, UNGLinuxDriver, Avi Fishman, Tomer Maimon,
Tali Perry, Patrick Venture, Nancy Yuen, Benjamin Fair,
Thierry Reding, Jonathan Hunter, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Geert Uytterhoeven, Magnus Damm, Heiko Stuebner,
Kunihiko Hayashi, Masami Hiramatsu, Jisheng Zhang,
Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Viorel Suman,
Abel Vesa, Peng Fan, Zhou Peng, Shenwei Wang, Ming Qian,
Adam Ford, Tim Harvey, Lucas Stach, Li Jun, Richard Zhu,
Markus Niebel
On 07/11/2022 16:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
No. This was applied and subject has wrong prefix.
Trim your CC list because it's impossible to reply (without manually
removing people).
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 06/23] arm64: dts: Update cache properties for broadcom
2022-11-07 17:31 ` Florian Fainelli
@ 2022-11-07 17:58 ` Pierre Gondois
2022-11-16 18:22 ` Florian Fainelli
0 siblings, 1 reply; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 17:58 UTC (permalink / raw)
To: Florian Fainelli, linux-kernel,
Broadcom internal kernel review list, William Zhang, Rob Herring,
Krzysztof Kozlowski
On 11/7/22 18:31, Florian Fainelli wrote:
> (way too many recipients, gmail's SMTP server would not allow me to
> respond unless I moved most people to BCC now done).
>
> On 11/7/22 07:56, Pierre Gondois wrote:
>> The DeviceTree Specification v0.3 specifies that the cache node
>> 'compatible' and 'cache-level' properties are 'required'. Cf.
>> s3.8 Multi-level and Shared Cache Nodes
>> The 'cache-unified' property should be present if one of the
>> properties for unified cache is present ('cache-size', ...).
>>
>> Update the Device Trees accordingly.
>>
>> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
>> Acked-by: William Zhang <william.zhang@broadcom.com>
>
> This looks fine, but incomplete, you seem to have missed:
>
> - adding 'cache-unified' to all of the cache nodes modified in this
> patch set that did not have one already
>
> - bcm63148.dtsi, bcm63178.dtsi, bcm6756.dtsi, bcm6846.dtsi,
> bcm6855.dtsi, bcm6878.dtsi, bcm47622.dtsi
>
> Thanks
I indeed forgot to update some platforms in the broadcom folder.
The other folders should be complete.
Regards,
Pierre
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 00/23] Update cache properties for arm64 DTS
2022-11-07 15:56 ` Pierre Gondois
@ 2022-11-07 18:03 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 107+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-07 18:03 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Peng Fan, Shenwei Wang, Ming Qian,
Lucas Stach, Adam Ford, Tim Harvey, Richard Zhu, Li Jun,
Joakim Zhang, Markus Niebel, Marco Felsch, Marek Vasut,
Laurent Pinchart, Arjun K V, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
On 07/11/2022 16:56, Pierre Gondois wrote:
> v2:
> - Update/Add patches for missed cache properties requiring to be
> updated for the following platforns: bcm, amazon, arm, exynos,
> freescale, marvell, mediatek, nvidia, socinext, tesla, ti.
> Missed cache properties were detected using Rob Herring's branch:
> https://github.com/robherring/dt-schema/tree/cache-rework
> - v1 of exynos, tesla were merged.
So you now duplicated the properties... You need to explicitly ask for a
patch to be dropped.
This cannot be sent like this because it is unmanageable.
1. Split the patchset per sub arch:
"Sending of the message failed.
An error occurred while sending mail. The mail server responded:
Your message has too many recipients. For more information regarding
Google's sending limits, please visit:
https://support.google.com/mail/?p=TooManyRecipientsError
w8-20020ac24428000000b00492ea54beeasm1344368lfl.306 - gsmtp.
Please check the message recipient "chris.obbard@collabora.com" and try
again."
2. Ask explicitly for dropping already merged patches (I assume they are
incorrect if you send v2 of them).
3. Use subject prefixes matching the subsystem (git log --oneline -- ...).
4. Send such patches only to interested parties, not as part of everything.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 00/23] Update cache properties for arm64 DTS
@ 2022-11-07 18:03 ` Krzysztof Kozlowski
0 siblings, 0 replies; 107+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-07 18:03 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Peng Fan, Shenwei Wang, Ming Qian,
Lucas Stach, Adam Ford, Tim Harvey, Richard Zhu, Li Jun,
Joakim Zhang, Markus Niebel, Marco Felsch, Marek Vasut,
Laurent Pinchart, Arjun K V, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
On 07/11/2022 16:56, Pierre Gondois wrote:
> v2:
> - Update/Add patches for missed cache properties requiring to be
> updated for the following platforns: bcm, amazon, arm, exynos,
> freescale, marvell, mediatek, nvidia, socinext, tesla, ti.
> Missed cache properties were detected using Rob Herring's branch:
> https://github.com/robherring/dt-schema/tree/cache-rework
> - v1 of exynos, tesla were merged.
So you now duplicated the properties... You need to explicitly ask for a
patch to be dropped.
This cannot be sent like this because it is unmanageable.
1. Split the patchset per sub arch:
"Sending of the message failed.
An error occurred while sending mail. The mail server responded:
Your message has too many recipients. For more information regarding
Google's sending limits, please visit:
https://support.google.com/mail/?p=TooManyRecipientsError
w8-20020ac24428000000b00492ea54beeasm1344368lfl.306 - gsmtp.
Please check the message recipient "chris.obbard@collabora.com" and try
again."
2. Ask explicitly for dropping already merged patches (I assume they are
incorrect if you send v2 of them).
3. Use subject prefixes matching the subsystem (git log --oneline -- ...).
4. Send such patches only to interested parties, not as part of everything.
Best regards,
Krzysztof
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 22/23] arm64: dts: Update cache properties for tesla
2022-11-07 17:56 ` Krzysztof Kozlowski
@ 2022-11-07 18:23 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 18:23 UTC (permalink / raw)
To: Krzysztof Kozlowski, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Alim Akhtar, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel
On 11/7/22 18:56, Krzysztof Kozlowski wrote:
> On 07/11/2022 16:57, Pierre Gondois wrote:
>> The DeviceTree Specification v0.3 specifies that the cache node
>> 'compatible' and 'cache-level' properties are 'required'. Cf.
>> s3.8 Multi-level and Shared Cache Nodes
>> The 'cache-unified' property should be present if one of the
>> properties for unified cache is present ('cache-size', ...).
>
> No. This was applied and subject has wrong prefix.
>
> Trim your CC list because it's impossible to reply (without manually
> removing people).
>
> Best regards,
> Krzysztof
>
Yes, this patch must be dropped.
I will do as you suggested in the cover letter,
Sorry for the trouble,
Regards,
Pierre
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 22/23] arm64: dts: Update cache properties for tesla
@ 2022-11-07 18:23 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 18:23 UTC (permalink / raw)
To: Krzysztof Kozlowski, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Alim Akhtar, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel
On 11/7/22 18:56, Krzysztof Kozlowski wrote:
> On 07/11/2022 16:57, Pierre Gondois wrote:
>> The DeviceTree Specification v0.3 specifies that the cache node
>> 'compatible' and 'cache-level' properties are 'required'. Cf.
>> s3.8 Multi-level and Shared Cache Nodes
>> The 'cache-unified' property should be present if one of the
>> properties for unified cache is present ('cache-size', ...).
>
> No. This was applied and subject has wrong prefix.
>
> Trim your CC list because it's impossible to reply (without manually
> removing people).
>
> Best regards,
> Krzysztof
>
Yes, this patch must be dropped.
I will do as you suggested in the cover letter,
Sorry for the trouble,
Regards,
Pierre
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 07/23] arm64: dts: Update cache properties for exynos
2022-11-07 17:55 ` Krzysztof Kozlowski
@ 2022-11-07 18:24 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 18:24 UTC (permalink / raw)
To: Krzysztof Kozlowski, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Alim Akhtar, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel
On 11/7/22 18:55, Krzysztof Kozlowski wrote:
> On 07/11/2022 16:57, Pierre Gondois wrote:
>> The DeviceTree Specification v0.3 specifies that the cache node
>> 'compatible' and 'cache-level' properties are 'required'. Cf.
>> s3.8 Multi-level and Shared Cache Nodes
>> The 'cache-unified' property should be present if one of the
>> properties for unified cache is present ('cache-size', ...).
>>
>> Update the Device Trees accordingly.
>
> Why do you send it again? This was applied.
>
> What is more - you have way too many recipients. Mail servers reject it.
> It's impossible even to reply to it...
>
>> cache-sets = <2048>;
>
> Best regards,
> Krzysztof
>
Yes, this patch must be dropped.
Sorry for the trouble,
Regards,
Pierre
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 07/23] arm64: dts: Update cache properties for exynos
@ 2022-11-07 18:24 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-07 18:24 UTC (permalink / raw)
To: Krzysztof Kozlowski, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Alim Akhtar, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel
On 11/7/22 18:55, Krzysztof Kozlowski wrote:
> On 07/11/2022 16:57, Pierre Gondois wrote:
>> The DeviceTree Specification v0.3 specifies that the cache node
>> 'compatible' and 'cache-level' properties are 'required'. Cf.
>> s3.8 Multi-level and Shared Cache Nodes
>> The 'cache-unified' property should be present if one of the
>> properties for unified cache is present ('cache-size', ...).
>>
>> Update the Device Trees accordingly.
>
> Why do you send it again? This was applied.
>
> What is more - you have way too many recipients. Mail servers reject it.
> It's impossible even to reply to it...
>
>> cache-sets = <2048>;
>
> Best regards,
> Krzysztof
>
Yes, this patch must be dropped.
Sorry for the trouble,
Regards,
Pierre
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 00/23] Update cache properties for arm64 DTS
2022-11-07 15:56 ` Pierre Gondois
` (25 preceding siblings ...)
(?)
@ 2022-11-07 23:11 ` Rob Herring
-1 siblings, 0 replies; 107+ messages in thread
From: Rob Herring @ 2022-11-07 23:11 UTC (permalink / raw)
To: Pierre Gondois
Cc: linux-kernel, Krzysztof Kozlowski, Florian Fainelli,
Scott Branden, Tsahee Zidenberg, Antoine Tenart, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Sudeep Holla,
Lorenzo Pieralisi, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Sascha Hauer, Andreas Färber, Matthias Brugger,
Wei Xu, Chanho Min, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Lars Povlsen, Steen Hegelund,
Daniel Machon, Avi Fishman, Tomer Maimon, Tali Perry,
Patrick Venture, Nancy Yuen, Benjamin Fair, Thierry Reding,
Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven, Magnus Damm,
Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Peng Fan, Lucas Stach, Adam Ford, Tim Harvey, Richard Zhu,
Joakim Zhang, Markus Niebel, Marek Vasut, Laurent Pinchart,
Alexander Stein, Paul Elder, David Heidelberg, Oliver Graute,
Liu Ying, Jacky Bai, Chris Packham, Vidya Sagar, Johan Jonker,
Ezequiel Garcia, devicetree, linux-arm-kernel
On Mon, Nov 07, 2022 at 04:56:53PM +0100, Pierre Gondois wrote:
> v2:
> - Update/Add patches for missed cache properties requiring to be
> updated for the following platforns: bcm, amazon, arm, exynos,
> freescale, marvell, mediatek, nvidia, socinext, tesla, ti.
> Missed cache properties were detected using Rob Herring's branch:
> https://github.com/robherring/dt-schema/tree/cache-rework
> - v1 of exynos, tesla were merged.
> - Updated wrong reference in commit message.
> - Added received Rb/Acked-by.
>
> Align arm64 DTS to the DeviceTree specification v0.3 regarding
> cache properties. The patch-set mainly adds 'cache-level' or
> 'cache' compatibility properties.
> For one qcom DTS, level 1 cache nodes are removed as they should
> be in the cpu nodes.
>
> On another node, it seems that the 'cache-unified' is under-used.
> cache-unified:
> If present, specifies the cache has a unified or-
> ganization. If not present, specifies that the
> cache has a Harvard architecture with separate
> caches for instructions and data.
> Only a few l2 cache nodes have this property, and in the absence
> of [|d|i]-cache-size properties (or other), the cache is assumed to be
> split.
>
> The l2 cache of the Rockchip RK3308 platform is thus assumed to be
> split:
> l2: l2-cache {
> compatible = "cache";
> cache-level = <2>;
> };
> when the platform datasheet advertises a unified cache.
>
> No modification/check was made to correct that due to the lack of
> cache information for most platforms.
I suppose in theory a split L2 is possible, but I think in practice that
doesn't exist. The Arm ARM allows for such a thing, but this[1] says L2
caches are unified. IMO, we should just define level 2+ is unified in
the schema and we can relax that if ever needed. I've updated the cache
schema branch[2] with that requirement.
Rob
[1] https://developer.arm.com/documentation/den0024/a/Caches/Cache-terminology
[2] https://github.com/robherring/dt-schema/tree/cache-rework
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 18/23] arm64: dts: Update cache properties for renesas
2022-11-07 15:57 ` Pierre Gondois
(?)
@ 2022-11-08 8:34 ` Geert Uytterhoeven
-1 siblings, 0 replies; 107+ messages in thread
From: Geert Uytterhoeven @ 2022-11-08 8:34 UTC (permalink / raw)
To: Pierre Gondois
Cc: linux-kernel, Rob Herring, Krzysztof Kozlowski, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shenwei Wang, Peng Fan, Ming Qian,
Adam Ford, Lucas Stach, Tim Harvey, Richard Zhu, Li Jun,
Marek Vasut, Markus Niebel, Joakim Zhang, Laurent Pinchart,
Alexander Stein, Paul Elder, Martin Kepplinger, Joy Zou,
David Heidelberg, Liu Ying, Oliver Graute, Shijie Qin, Jacky Bai,
Wei Fang, Clark Wang, Chris Packham, Vadym Kochan, Sameer Pujar,
Prathamesh Shete, Akhil R, Mikko Perttunen, Sumit Gupta,
Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, devicetree, linux-rpi-kernel, linux-arm-kernel,
linux-amlogic, linux-samsung-soc, linux-mediatek, openbmc,
linux-tegra, linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
Hi Pierre,
Thanks for your patch!
On Mon, Nov 7, 2022 at 5:33 PM Pierre Gondois <pierre.gondois@arm.com> wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
"compatible" is present?
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
Present, too?
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> @@ -88,6 +88,7 @@ L3_CA55: cache-controller-0 {
> compatible = "cache";
> cache-unified;
> cache-size = <0x40000>;
> + cache-level = <3>;
> };
> };
'
This hunk now applies to arch/arm64/boot/dts/renesas/r9a07g043u.dtsi.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.2, with the patch description
and the file names updated to match the real world.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 12/23] arm64: dts: Update cache properties for mediatek
2022-11-07 15:57 ` Pierre Gondois
@ 2022-11-08 11:42 ` Matthias Brugger
-1 siblings, 0 replies; 107+ messages in thread
From: Matthias Brugger @ 2022-11-08 11:42 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Kevin Hilman, devicetree,
linux-arm-kernel, linux-mediatek
On 07/11/2022 16:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Applied, thanks,
Matthias
> ---
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 3 +++
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 3 +++
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 +++
> 3 files changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index 64693c17af9e..c326aeb33a10 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -198,16 +198,19 @@ cluster_off_b: cluster-off-b {
>
> l2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> next-level-cache = <&l3_0>;
> };
>
> l2_1: l2-cache1 {
> compatible = "cache";
> + cache-level = <2>;
> next-level-cache = <&l3_0>;
> };
>
> l3_0: l3-cache {
> compatible = "cache";
> + cache-level = <3>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 6b20376191a7..424fc89cc6f7 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -169,16 +169,19 @@ core3 {
>
> l2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> next-level-cache = <&l3_0>;
> };
>
> l2_1: l2-cache1 {
> compatible = "cache";
> + cache-level = <2>;
> next-level-cache = <&l3_0>;
> };
>
> l3_0: l3-cache {
> compatible = "cache";
> + cache-level = <3>;
> };
>
> idle-states {
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 905d1a90b406..cb74905cfbb8 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -213,16 +213,19 @@ cluster_off_b: cluster-off-b {
>
> l2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> next-level-cache = <&l3_0>;
> };
>
> l2_1: l2-cache1 {
> compatible = "cache";
> + cache-level = <2>;
> next-level-cache = <&l3_0>;
> };
>
> l3_0: l3-cache {
> compatible = "cache";
> + cache-level = <3>;
> };
> };
>
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 12/23] arm64: dts: Update cache properties for mediatek
@ 2022-11-08 11:42 ` Matthias Brugger
0 siblings, 0 replies; 107+ messages in thread
From: Matthias Brugger @ 2022-11-08 11:42 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Kevin Hilman, devicetree,
linux-arm-kernel, linux-mediatek
On 07/11/2022 16:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Applied, thanks,
Matthias
> ---
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 3 +++
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 3 +++
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 +++
> 3 files changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index 64693c17af9e..c326aeb33a10 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -198,16 +198,19 @@ cluster_off_b: cluster-off-b {
>
> l2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> next-level-cache = <&l3_0>;
> };
>
> l2_1: l2-cache1 {
> compatible = "cache";
> + cache-level = <2>;
> next-level-cache = <&l3_0>;
> };
>
> l3_0: l3-cache {
> compatible = "cache";
> + cache-level = <3>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 6b20376191a7..424fc89cc6f7 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -169,16 +169,19 @@ core3 {
>
> l2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> next-level-cache = <&l3_0>;
> };
>
> l2_1: l2-cache1 {
> compatible = "cache";
> + cache-level = <2>;
> next-level-cache = <&l3_0>;
> };
>
> l3_0: l3-cache {
> compatible = "cache";
> + cache-level = <3>;
> };
>
> idle-states {
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 905d1a90b406..cb74905cfbb8 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -213,16 +213,19 @@ cluster_off_b: cluster-off-b {
>
> l2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> next-level-cache = <&l3_0>;
> };
>
> l2_1: l2-cache1 {
> compatible = "cache";
> + cache-level = <2>;
> next-level-cache = <&l3_0>;
> };
>
> l3_0: l3-cache {
> compatible = "cache";
> + cache-level = <3>;
> };
> };
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 05/23] arm64: dts: Update cache properties for arm
2022-11-07 15:56 ` Pierre Gondois
(?)
@ 2022-11-11 15:56 ` Sudeep Holla
-1 siblings, 0 replies; 107+ messages in thread
From: Sudeep Holla @ 2022-11-11 15:56 UTC (permalink / raw)
To: linux-kernel, Pierre Gondois
Cc: Sudeep Holla, Liviu Dudau, devicetree, robh+dt
On Mon, 7 Nov 2022 16:56:53 +0100, Pierre Gondois wrote:
> v2:
> - Update/Add patches for missed cache properties requiring to be
> updated for the following platforns: bcm, amazon, arm, exynos,
> freescale, marvell, mediatek, nvidia, socinext, tesla, ti.
> Missed cache properties were detected using Rob Herring's branch:
> https://github.com/robherring/dt-schema/tree/cache-rework
> - v1 of exynos, tesla were merged.
> - Updated wrong reference in commit message.
> - Added received Rb/Acked-by.
>
> [...]
Applied to sudeep.holla/linux (for-next/juno), thanks!
[05/23] arm64: dts: Update cache properties for arm
https://git.kernel.org/sudeep.holla/c/59fb813f9742
--
Regards,
Sudeep
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 08/23] arm64: dts: Update cache properties for freescale
2022-11-07 15:57 ` Pierre Gondois
(?)
@ 2022-11-14 11:41 ` Shawn Guo
-1 siblings, 0 replies; 107+ messages in thread
From: Shawn Guo @ 2022-11-14 11:41 UTC (permalink / raw)
To: Pierre Gondois
Cc: linux-kernel, Rob Herring, Krzysztof Kozlowski, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Li Yang, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Shenwei Wang, Shijie Qin, Ming Qian,
Peng Fan, Adam Ford, Lucas Stach, Tim Harvey, Li Jun,
Richard Zhu, Joakim Zhang, Markus Niebel, Marek Vasut,
Laurent Pinchart, Paul Elder, Alexander Stein, Martin Kepplinger,
David Heidelberg, Liu Ying, Oliver Graute, Zhou Peng, Haibo Chen,
Ahmad Fatoum, Clark Wang, Jacky Bai, Chris Packham, Vadym Kochan,
Sameer Pujar, Prathamesh Shete, Mikko Perttunen, Akhil R,
Sumit Gupta, Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Ajay Kumar, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
On Mon, Nov 07, 2022 at 04:57:01PM +0100, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Applied, thanks!
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 09/23] arm64: dts: Update cache properties for hisilicon
2022-11-07 15:57 ` Pierre Gondois
(?)
@ 2022-11-16 2:17 ` Wei Xu
-1 siblings, 0 replies; 107+ messages in thread
From: Wei Xu @ 2022-11-16 2:17 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Chanho Min, Andrew Lunn,
Gregory Clement, Sebastian Hesselbarth, Lars Povlsen,
Steen Hegelund, Daniel Machon, UNGLinuxDriver, Avi Fishman,
Tomer Maimon, Tali Perry, Patrick Venture, Nancy Yuen,
Benjamin Fair, Thierry Reding, Jonathan Hunter, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven, Magnus Damm,
Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Ming Qian, Shijie Qin, Peng Fan,
Shenwei Wang, Tim Harvey, Lucas Stach, Adam Ford, Richard Zhu,
Li Jun, Markus Niebel, Joakim Zhang, Marek Vasut,
Laurent Pinchart, Alexander Stein, Paul Elder, Martin Kepplinger,
David Heidelberg, Oliver Graute, Liu Ying, Jacky Bai, Clark Wang,
Wei Fang, Chris Packham, Vadym Kochan, Sameer Pujar, Akhil R,
Mikko Perttunen, Prathamesh Shete, Sumit Gupta, Diogo Ivo,
Vidya Sagar, Ashish Mhetre, Johan Jonker, Christopher Obbard,
Ezequiel Garcia, Aswani Reddy, Shashank Prashar, Andi Shyti,
devicetree, linux-rpi-kernel, linux-arm-kernel, linux-amlogic,
linux-samsung-soc, linux-mediatek, openbmc, linux-tegra,
linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
Hi Pierre,
On 2022/11/7 23:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Applied to the HiSilicon arm64 dt tree.
Thanks!
Best Regards,
Wei
> ---
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 ++
> arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 ++
> arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++++
> arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 ++++
> arch/arm64/boot/dts/hisilicon/hip07.dtsi | 16 ++++++++++++++++
> 5 files changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> index 8343d0cedde3..a57f35eb5ef6 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -203,10 +203,12 @@ CLUSTER_SLEEP_1: cluster-sleep-1 {
>
> A53_L2: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> A73_L2: l2-cache1 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> index ae0a7cfeeb47..f6d3202b0d1a 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> @@ -186,10 +186,12 @@ cpu7: cpu@103 {
>
> CLUSTER0_L2: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> CLUSTER1_L2: l2-cache1 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
> index 7b2abd10d3d6..5b2b1bfd0d2a 100644
> --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
> @@ -211,18 +211,22 @@ cpu15: cpu@20303 {
>
> cluster0_l2: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster1_l2: l2-cache1 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster2_l2: l2-cache2 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster3_l2: l2-cache3 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
> index 2f8b03b0d365..291c2ee38288 100644
> --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
> @@ -211,18 +211,22 @@ cpu15: cpu@10303 {
>
> cluster0_l2: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster1_l2: l2-cache1 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster2_l2: l2-cache2 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster3_l2: l2-cache3 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
> index 1a16662f8867..b8746fb959b5 100644
> --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
> @@ -842,66 +842,82 @@ cpu63: cpu@70303 {
>
> cluster0_l2: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster1_l2: l2-cache1 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster2_l2: l2-cache2 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster3_l2: l2-cache3 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster4_l2: l2-cache4 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster5_l2: l2-cache5 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster6_l2: l2-cache6 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster7_l2: l2-cache7 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster8_l2: l2-cache8 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster9_l2: l2-cache9 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster10_l2: l2-cache10 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster11_l2: l2-cache11 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster12_l2: l2-cache12 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster13_l2: l2-cache13 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster14_l2: l2-cache14 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> cluster15_l2: l2-cache15 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
>
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 06/23] arm64: dts: Update cache properties for broadcom
2022-11-07 17:58 ` Pierre Gondois
@ 2022-11-16 18:22 ` Florian Fainelli
2022-11-17 9:39 ` Pierre Gondois
0 siblings, 1 reply; 107+ messages in thread
From: Florian Fainelli @ 2022-11-16 18:22 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel,
Broadcom internal kernel review list, William Zhang, Rob Herring,
Krzysztof Kozlowski
On 11/7/2022 9:58 AM, Pierre Gondois wrote:
>
>
> On 11/7/22 18:31, Florian Fainelli wrote:
>> (way too many recipients, gmail's SMTP server would not allow me to
>> respond unless I moved most people to BCC now done).
>>
>> On 11/7/22 07:56, Pierre Gondois wrote:
>>> The DeviceTree Specification v0.3 specifies that the cache node
>>> 'compatible' and 'cache-level' properties are 'required'. Cf.
>>> s3.8 Multi-level and Shared Cache Nodes
>>> The 'cache-unified' property should be present if one of the
>>> properties for unified cache is present ('cache-size', ...).
>>>
>>> Update the Device Trees accordingly.
>>>
>>> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
>>> Acked-by: William Zhang <william.zhang@broadcom.com>
>>
>> This looks fine, but incomplete, you seem to have missed:
>>
>> - adding 'cache-unified' to all of the cache nodes modified in this
>> patch set that did not have one already
>>
>> - bcm63148.dtsi, bcm63178.dtsi, bcm6756.dtsi, bcm6846.dtsi,
>> bcm6855.dtsi, bcm6878.dtsi, bcm47622.dtsi
>>
>> Thanks
>
> I indeed forgot to update some platforms in the broadcom folder.
> The other folders should be complete.
Can I expect a resend in the next few days so we have a chance of
getting that included in 6.2? Thanks
--
Florian
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 06/23] arm64: dts: Update cache properties for broadcom
2022-11-16 18:22 ` Florian Fainelli
@ 2022-11-17 9:39 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2022-11-17 9:39 UTC (permalink / raw)
To: Florian Fainelli, linux-kernel,
Broadcom internal kernel review list, William Zhang, Rob Herring,
Krzysztof Kozlowski
On 11/16/22 19:22, Florian Fainelli wrote:
>
>
> On 11/7/2022 9:58 AM, Pierre Gondois wrote:
>>
>>
>> On 11/7/22 18:31, Florian Fainelli wrote:
>>> (way too many recipients, gmail's SMTP server would not allow me to
>>> respond unless I moved most people to BCC now done).
>>>
>>> On 11/7/22 07:56, Pierre Gondois wrote:
>>>> The DeviceTree Specification v0.3 specifies that the cache node
>>>> 'compatible' and 'cache-level' properties are 'required'. Cf.
>>>> s3.8 Multi-level and Shared Cache Nodes
>>>> The 'cache-unified' property should be present if one of the
>>>> properties for unified cache is present ('cache-size', ...).
>>>>
>>>> Update the Device Trees accordingly.
>>>>
>>>> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
>>>> Acked-by: William Zhang <william.zhang@broadcom.com>
>>>
>>> This looks fine, but incomplete, you seem to have missed:
>>>
>>> - adding 'cache-unified' to all of the cache nodes modified in this
>>> patch set that did not have one already
>>>
>>> - bcm63148.dtsi, bcm63178.dtsi, bcm6756.dtsi, bcm6846.dtsi,
>>> bcm6855.dtsi, bcm6878.dtsi, bcm47622.dtsi
>>>
>>> Thanks
>>
>> I indeed forgot to update some platforms in the broadcom folder.
>> The other folders should be complete.
>
> Can I expect a resend in the next few days so we have a chance of
> getting that included in 6.2? Thanks
Yes sure. Just to check, the 'cache-unified' property is only required
by the DT spec when there is one of these properties in the cache node:
'cache-[size|line-size|block-size|sets|level]'
So the below doesn't require it. Do you still want to have it added ?
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: (subset) [PATCH v2 00/23] Update cache properties for arm64 DTS
2022-11-07 15:56 ` Pierre Gondois
(?)
@ 2022-11-22 22:34 ` Heiko Stuebner
-1 siblings, 0 replies; 107+ messages in thread
From: Heiko Stuebner @ 2022-11-22 22:34 UTC (permalink / raw)
To: linux-kernel, Pierre Gondois
Cc: Heiko Stuebner, linux-arm-kernel, Rob Herring, devicetree,
Krzysztof Kozlowski, linux-rockchip
On Mon, 7 Nov 2022 16:56:53 +0100, Pierre Gondois wrote:
> v2:
> - Update/Add patches for missed cache properties requiring to be
> updated for the following platforns: bcm, amazon, arm, exynos,
> freescale, marvell, mediatek, nvidia, socinext, tesla, ti.
> Missed cache properties were detected using Rob Herring's branch:
> https://github.com/robherring/dt-schema/tree/cache-rework
> - v1 of exynos, tesla were merged.
> - Updated wrong reference in commit message.
> - Added received Rb/Acked-by.
>
> [...]
Applied, thanks!
[19/23] arm64: dts: Update cache properties for rockchip
commit: 848343c0b4d64821aec19b2cff47b58f77362d38
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: (subset) [PATCH v2 00/23] Update cache properties for arm64 DTS
@ 2022-11-22 22:34 ` Heiko Stuebner
0 siblings, 0 replies; 107+ messages in thread
From: Heiko Stuebner @ 2022-11-22 22:34 UTC (permalink / raw)
To: linux-kernel, Pierre Gondois
Cc: Heiko Stuebner, linux-arm-kernel, Rob Herring, devicetree,
Krzysztof Kozlowski, linux-rockchip
On Mon, 7 Nov 2022 16:56:53 +0100, Pierre Gondois wrote:
> v2:
> - Update/Add patches for missed cache properties requiring to be
> updated for the following platforns: bcm, amazon, arm, exynos,
> freescale, marvell, mediatek, nvidia, socinext, tesla, ti.
> Missed cache properties were detected using Rob Herring's branch:
> https://github.com/robherring/dt-schema/tree/cache-rework
> - v1 of exynos, tesla were merged.
> - Updated wrong reference in commit message.
> - Added received Rb/Acked-by.
>
> [...]
Applied, thanks!
[19/23] arm64: dts: Update cache properties for rockchip
commit: 848343c0b4d64821aec19b2cff47b58f77362d38
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: (subset) [PATCH v2 00/23] Update cache properties for arm64 DTS
@ 2022-11-22 22:34 ` Heiko Stuebner
0 siblings, 0 replies; 107+ messages in thread
From: Heiko Stuebner @ 2022-11-22 22:34 UTC (permalink / raw)
To: linux-kernel, Pierre Gondois
Cc: Heiko Stuebner, linux-arm-kernel, Rob Herring, devicetree,
Krzysztof Kozlowski, linux-rockchip
On Mon, 7 Nov 2022 16:56:53 +0100, Pierre Gondois wrote:
> v2:
> - Update/Add patches for missed cache properties requiring to be
> updated for the following platforns: bcm, amazon, arm, exynos,
> freescale, marvell, mediatek, nvidia, socinext, tesla, ti.
> Missed cache properties were detected using Rob Herring's branch:
> https://github.com/robherring/dt-schema/tree/cache-rework
> - v1 of exynos, tesla were merged.
> - Updated wrong reference in commit message.
> - Added received Rb/Acked-by.
>
> [...]
Applied, thanks!
[19/23] arm64: dts: Update cache properties for rockchip
commit: 848343c0b4d64821aec19b2cff47b58f77362d38
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 16/23] arm64: dts: Update cache properties for qcom
2022-11-07 15:57 ` Pierre Gondois
@ 2022-12-29 12:47 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 107+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-29 12:47 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, linux-rpi-kernel, linux-arm-kernel,
linux-amlogic, linux-samsung-soc, linux-mediatek, openbmc,
linux-tegra, linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
On 07/11/2022 16:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
Any progress on this? Pierre, are you going to resend to target specific
maintainers or SoC?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 16/23] arm64: dts: Update cache properties for qcom
@ 2022-12-29 12:47 ` Krzysztof Kozlowski
0 siblings, 0 replies; 107+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-29 12:47 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, linux-rpi-kernel, linux-arm-kernel,
linux-amlogic, linux-samsung-soc, linux-mediatek, openbmc,
linux-tegra, linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
On 07/11/2022 16:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
Any progress on this? Pierre, are you going to resend to target specific
maintainers or SoC?
Best regards,
Krzysztof
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: (subset) [PATCH v2 16/23] arm64: dts: Update cache properties for qcom
2022-11-07 15:57 ` Pierre Gondois
@ 2022-12-29 17:23 ` Bjorn Andersson
-1 siblings, 0 replies; 107+ messages in thread
From: Bjorn Andersson @ 2022-12-29 17:23 UTC (permalink / raw)
To: linux-kernel, pierre.gondois
Cc: linux-realtek-soc, alim.akhtar, clin, krzysztof.kozlowski+dt,
tmaimon77, chris.obbard, ming.qian, william.zhang,
linux-arm-kernel, Markus.Niebel, m.felsch, jszhang, viorel.suman,
liviu.dudau, openbmc, agross, Sascha Hauer, xiaoning.wang,
mbrugger, hayashi.kunihiko, aswani.reddy, linux-arm-msm, s32,
mhiramat, marex, Steen.Hegelund, anand.gore, thomas.lendacky,
pshete, benjaminfair, diogo.ivo, jbx6244, heiko, tharvey,
vigneshr, linux-rpi-kernel, afaerber, jun.li, victor.liu,
linux-mediatek, mperttunen, peng.fan, abelvesa, chris.packham,
lpieralisi, laurent.pinchart, ezequiel, rafal, jonathanh,
konrad.dybcio, UNGLinuxDriver, martin.blumenstingl,
linux-rockchip, kernel, qiangqing.zhang, amhetre, linux-tegra,
andrew, kristo, nm, spujar, leoyang.li, vadym.kochan,
daniel.machon, paul.elder, khilman, avifishman70, tali.perry1,
linux-samsung-soc, robh+dt, alexander.stein, festevam,
brijeshkumar.singh, oliver.graute, martink, shenwei.wang,
f.fainelli, sumitg, devicetree, eagle.zhou,
sebastian.hesselbarth, atenart, l.stach, xuwei5, tsahee,
ping.bai, shawnguo, linux-amlogic, jbrunet,
bcm-kernel-feedback-list, neil.armstrong, suravee.suthikulpanit,
thierry.reding, rjui, lars.povlsen, magnus.damm, geert+renesas,
wei.fang, linux-imx, gregory.clement, yuenn, vidyas, chanho.min,
david, aford173, s.prashar, khuong, sudeep.holla, sbranden,
shijie.qin, venture, kursad.oney, linux-renesas-soc,
hongxing.zhu, akhilrajeev
On Mon, 7 Nov 2022 16:57:09 +0100, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> [...]
Applied, thanks!
[16/23] arm64: dts: Update cache properties for qcom
commit: 9435294c6517dc70bb608505b79097a58ea7c6a3
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: (subset) [PATCH v2 16/23] arm64: dts: Update cache properties for qcom
@ 2022-12-29 17:23 ` Bjorn Andersson
0 siblings, 0 replies; 107+ messages in thread
From: Bjorn Andersson @ 2022-12-29 17:23 UTC (permalink / raw)
To: linux-kernel, pierre.gondois
Cc: linux-realtek-soc, alim.akhtar, clin, krzysztof.kozlowski+dt,
tmaimon77, chris.obbard, ming.qian, william.zhang,
linux-arm-kernel, Markus.Niebel, m.felsch, jszhang, viorel.suman,
liviu.dudau, openbmc, agross, Sascha Hauer, xiaoning.wang,
mbrugger, hayashi.kunihiko, aswani.reddy, linux-arm-msm, s32,
mhiramat, marex, Steen.Hegelund, anand.gore, thomas.lendacky,
pshete, benjaminfair, diogo.ivo, jbx6244, heiko, tharvey,
vigneshr, linux-rpi-kernel, afaerber, jun.li, victor.liu,
linux-mediatek, mperttunen, peng.fan, abelvesa, chris.packham,
lpieralisi, laurent.pinchart, ezequiel, rafal, jonathanh,
konrad.dybcio, UNGLinuxDriver, martin.blumenstingl,
linux-rockchip, kernel, qiangqing.zhang, amhetre, linux-tegra,
andrew, kristo, nm, spujar, leoyang.li, vadym.kochan,
daniel.machon, paul.elder, khilman, avifishman70, tali.perry1,
linux-samsung-soc, robh+dt, alexander.stein, festevam,
brijeshkumar.singh, oliver.graute, martink, shenwei.wang,
f.fainelli, sumitg, devicetree, eagle.zhou,
sebastian.hesselbarth, atenart, l.stach, xuwei5, tsahee,
ping.bai, shawnguo, linux-amlogic, jbrunet,
bcm-kernel-feedback-list, neil.armstrong, suravee.suthikulpanit,
thierry.reding, rjui, lars.povlsen, magnus.damm, geert+renesas,
wei.fang, linux-imx, gregory.clement, yuenn, vidyas, chanho.min,
david, aford173, s.prashar, khuong, sudeep.holla, sbranden,
shijie.qin, venture, kursad.oney, linux-renesas-soc,
hongxing.zhu, akhilrajeev
On Mon, 7 Nov 2022 16:57:09 +0100, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> [...]
Applied, thanks!
[16/23] arm64: dts: Update cache properties for qcom
commit: 9435294c6517dc70bb608505b79097a58ea7c6a3
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 21/23] arm64: dts: Update cache properties for synaptics
2022-11-07 15:57 ` Pierre Gondois
@ 2023-01-12 8:32 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2023-01-12 8:32 UTC (permalink / raw)
To: LKML
Cc: Jisheng Zhang, Sebastian Hesselbarth, Rob Herring,
Krzysztof Kozlowski, linux-arm-kernel, devicetree
(subset for cc list)
Hello,
Just a reminder in case the patch was forgotten,
Regards,
Pierre
On 11/7/22 16:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
> index 0949acee4728..926da7e1a6ba 100644
> --- a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
> +++ b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
> @@ -64,6 +64,7 @@ cpu3: cpu@3 {
>
> l2: cache {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> idle-states {
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 21/23] arm64: dts: Update cache properties for synaptics
@ 2023-01-12 8:32 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2023-01-12 8:32 UTC (permalink / raw)
To: LKML
Cc: Jisheng Zhang, Sebastian Hesselbarth, Rob Herring,
Krzysztof Kozlowski, linux-arm-kernel, devicetree
(subset for cc list)
Hello,
Just a reminder in case the patch was forgotten,
Regards,
Pierre
On 11/7/22 16:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
> index 0949acee4728..926da7e1a6ba 100644
> --- a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
> +++ b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
> @@ -64,6 +64,7 @@ cpu3: cpu@3 {
>
> l2: cache {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> idle-states {
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 20/23] arm64: dts: Update cache properties for socionext
2022-11-07 15:57 ` Pierre Gondois
@ 2023-01-12 8:33 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2023-01-12 8:33 UTC (permalink / raw)
To: LKML
Cc: Rob Herring, Krzysztof Kozlowski, Kunihiko Hayashi,
Masami Hiramatsu, devicetree, linux-arm-kernel
(subset for cc list)
Hello,
Just a reminder in case the patch was forgotten,
Regards,
Pierre
On 11/7/22 16:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
> arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 1 +
> arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++
> arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 1 +
> 3 files changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
> index 1c76b4375b2e..6e1e00939214 100644
> --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
> +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
> @@ -52,6 +52,7 @@ cpu1: cpu@1 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
> index 9308458f9611..db7d20a1a301 100644
> --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
> +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
> @@ -86,10 +86,12 @@ cpu3: cpu@101 {
>
> a72_l2: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> a53_l2: l2-cache1 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
> index b0c29510a7da..9ce544c9ea0a 100644
> --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
> +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
> @@ -83,6 +83,7 @@ cpu3: cpu@3 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 20/23] arm64: dts: Update cache properties for socionext
@ 2023-01-12 8:33 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2023-01-12 8:33 UTC (permalink / raw)
To: LKML
Cc: Rob Herring, Krzysztof Kozlowski, Kunihiko Hayashi,
Masami Hiramatsu, devicetree, linux-arm-kernel
(subset for cc list)
Hello,
Just a reminder in case the patch was forgotten,
Regards,
Pierre
On 11/7/22 16:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
> arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 1 +
> arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++
> arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 1 +
> 3 files changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
> index 1c76b4375b2e..6e1e00939214 100644
> --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
> +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
> @@ -52,6 +52,7 @@ cpu1: cpu@1 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
> index 9308458f9611..db7d20a1a301 100644
> --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
> +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
> @@ -86,10 +86,12 @@ cpu3: cpu@101 {
>
> a72_l2: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
>
> a53_l2: l2-cache1 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
> index b0c29510a7da..9ce544c9ea0a 100644
> --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
> +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
> @@ -83,6 +83,7 @@ cpu3: cpu@3 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 17/23] arm64: dts: Update cache properties for realtek
2022-11-07 15:57 ` Pierre Gondois
@ 2023-01-12 8:33 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2023-01-12 8:33 UTC (permalink / raw)
To: LKML
Cc: Andreas Färber, Rob Herring, Krzysztof Kozlowski,
linux-arm-kernel, linux-realtek-soc, devicetree
(subset for cc list)
Hello,
Just a reminder in case the patch was forgotten,
Regards,
Pierre
On 11/7/22 16:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
> arch/arm64/boot/dts/realtek/rtd1293.dtsi | 1 +
> arch/arm64/boot/dts/realtek/rtd1295.dtsi | 1 +
> arch/arm64/boot/dts/realtek/rtd1296.dtsi | 1 +
> arch/arm64/boot/dts/realtek/rtd1395.dtsi | 1 +
> arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 2 ++
> 5 files changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/realtek/rtd1293.dtsi b/arch/arm64/boot/dts/realtek/rtd1293.dtsi
> index 2d92b56ac94d..0696b99fc40d 100644
> --- a/arch/arm64/boot/dts/realtek/rtd1293.dtsi
> +++ b/arch/arm64/boot/dts/realtek/rtd1293.dtsi
> @@ -30,6 +30,7 @@ cpu1: cpu@1 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
> index 1402abe80ea1..4ca322e420e6 100644
> --- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi
> +++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
> @@ -44,6 +44,7 @@ cpu3: cpu@3 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/realtek/rtd1296.dtsi b/arch/arm64/boot/dts/realtek/rtd1296.dtsi
> index fb864a139c97..03fccd48f0c0 100644
> --- a/arch/arm64/boot/dts/realtek/rtd1296.dtsi
> +++ b/arch/arm64/boot/dts/realtek/rtd1296.dtsi
> @@ -44,6 +44,7 @@ cpu3: cpu@3 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/realtek/rtd1395.dtsi b/arch/arm64/boot/dts/realtek/rtd1395.dtsi
> index 05c9216a87ee..94c0a8cf4953 100644
> --- a/arch/arm64/boot/dts/realtek/rtd1395.dtsi
> +++ b/arch/arm64/boot/dts/realtek/rtd1395.dtsi
> @@ -44,6 +44,7 @@ cpu3: cpu@3 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
> index afba5f04c8ec..2ee9ba1ecdc1 100644
> --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
> +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
> @@ -87,12 +87,14 @@ cpu5: cpu@500 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> next-level-cache = <&l3>;
>
> };
>
> l3: l3-cache {
> compatible = "cache";
> + cache-level = <3>;
> };
> };
>
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 17/23] arm64: dts: Update cache properties for realtek
@ 2023-01-12 8:33 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2023-01-12 8:33 UTC (permalink / raw)
To: LKML
Cc: Andreas Färber, Rob Herring, Krzysztof Kozlowski,
linux-arm-kernel, linux-realtek-soc, devicetree
(subset for cc list)
Hello,
Just a reminder in case the patch was forgotten,
Regards,
Pierre
On 11/7/22 16:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
> arch/arm64/boot/dts/realtek/rtd1293.dtsi | 1 +
> arch/arm64/boot/dts/realtek/rtd1295.dtsi | 1 +
> arch/arm64/boot/dts/realtek/rtd1296.dtsi | 1 +
> arch/arm64/boot/dts/realtek/rtd1395.dtsi | 1 +
> arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 2 ++
> 5 files changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/realtek/rtd1293.dtsi b/arch/arm64/boot/dts/realtek/rtd1293.dtsi
> index 2d92b56ac94d..0696b99fc40d 100644
> --- a/arch/arm64/boot/dts/realtek/rtd1293.dtsi
> +++ b/arch/arm64/boot/dts/realtek/rtd1293.dtsi
> @@ -30,6 +30,7 @@ cpu1: cpu@1 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
> index 1402abe80ea1..4ca322e420e6 100644
> --- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi
> +++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
> @@ -44,6 +44,7 @@ cpu3: cpu@3 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/realtek/rtd1296.dtsi b/arch/arm64/boot/dts/realtek/rtd1296.dtsi
> index fb864a139c97..03fccd48f0c0 100644
> --- a/arch/arm64/boot/dts/realtek/rtd1296.dtsi
> +++ b/arch/arm64/boot/dts/realtek/rtd1296.dtsi
> @@ -44,6 +44,7 @@ cpu3: cpu@3 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/realtek/rtd1395.dtsi b/arch/arm64/boot/dts/realtek/rtd1395.dtsi
> index 05c9216a87ee..94c0a8cf4953 100644
> --- a/arch/arm64/boot/dts/realtek/rtd1395.dtsi
> +++ b/arch/arm64/boot/dts/realtek/rtd1395.dtsi
> @@ -44,6 +44,7 @@ cpu3: cpu@3 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
> index afba5f04c8ec..2ee9ba1ecdc1 100644
> --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
> +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
> @@ -87,12 +87,14 @@ cpu5: cpu@500 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> next-level-cache = <&l3>;
>
> };
>
> l3: l3-cache {
> compatible = "cache";
> + cache-level = <3>;
> };
> };
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 00/23] Update cache properties for arm64 DTS
2022-11-07 15:56 ` Pierre Gondois
@ 2023-01-12 8:33 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2023-01-12 8:33 UTC (permalink / raw)
To: LKML
Cc: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, linux-arm-kernel, devicetree
(subset of the cc list for the Texas Instruments patch)
Hello,
Just a reminder in case the following patch was forgotten:
arm64: dts: Update cache properties for ti
Regards,
Pierre
On 11/7/22 16:56, Pierre Gondois wrote:
> v2:
> - Update/Add patches for missed cache properties requiring to be
> updated for the following platforns: bcm, amazon, arm, exynos,
> freescale, marvell, mediatek, nvidia, socinext, tesla, ti.
> Missed cache properties were detected using Rob Herring's branch:
> https://github.com/robherring/dt-schema/tree/cache-rework
> - v1 of exynos, tesla were merged.
> - Updated wrong reference in commit message.
> - Added received Rb/Acked-by.
>
> Align arm64 DTS to the DeviceTree specification v0.3 regarding
> cache properties. The patch-set mainly adds 'cache-level' or
> 'cache' compatibility properties.
> For one qcom DTS, level 1 cache nodes are removed as they should
> be in the cpu nodes.
>
> On another node, it seems that the 'cache-unified' is under-used.
> cache-unified:
> If present, specifies the cache has a unified or-
> ganization. If not present, specifies that the
> cache has a Harvard architecture with separate
> caches for instructions and data.
> Only a few l2 cache nodes have this property, and in the absence
> of [|d|i]-cache-size properties (or other), the cache is assumed to be
> split.
>
> The l2 cache of the Rockchip RK3308 platform is thus assumed to be
> split:
> l2: l2-cache {
> compatible = "cache";
> cache-level = <2>;
> };
> when the platform datasheet advertises a unified cache.
>
> No modification/check was made to correct that due to the lack of
> cache information for most platforms.
>
> Pierre Gondois (23):
> arm64: dts: Update cache properties for amazon
> arm64: dts: Update cache properties for amd
> arm64: dts: Update cache properties for amlogic
> arm64: dts: Update cache properties for apm
> arm64: dts: Update cache properties for arm
> arm64: dts: Update cache properties for broadcom
> arm64: dts: Update cache properties for exynos
> arm64: dts: Update cache properties for freescale
> arm64: dts: Update cache properties for hisilicon
> arm64: dts: Update cache properties for lg
> arm64: dts: Update cache properties for marvell
> arm64: dts: Update cache properties for mediatek
> arm64: dts: Update cache properties for microchip
> arm64: dts: Update cache properties for nuvoton
> arm64: dts: Update cache properties for nvidia
> arm64: dts: Update cache properties for qcom
> arm64: dts: Update cache properties for realtek
> arm64: dts: Update cache properties for renesas
> arm64: dts: Update cache properties for rockchip
> arm64: dts: Update cache properties for socionext
> arm64: dts: Update cache properties for synaptics
> arm64: dts: Update cache properties for tesla
> arm64: dts: Update cache properties for ti
>
> arch/arm/boot/dts/bcm2711.dtsi | 1 +
> arch/arm/boot/dts/bcm2837.dtsi | 1 +
> arch/arm64/boot/dts/amazon/alpine-v3.dtsi | 4 ++
> arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi | 9 +++
> arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 1 +
> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 1 +
> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 1 +
> arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 1 +
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 +
> arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 1 +
> arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 4 ++
> arch/arm64/boot/dts/apm/apm-storm.dtsi | 4 ++
> arch/arm64/boot/dts/arm/corstone1000.dtsi | 1 +
> arch/arm64/boot/dts/arm/foundation-v8.dtsi | 1 +
> arch/arm64/boot/dts/arm/juno-r1.dts | 2 +
> arch/arm64/boot/dts/arm/juno-r2.dts | 2 +
> arch/arm64/boot/dts/arm/juno.dts | 2 +
> arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 1 +
> .../boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 1 +
> .../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 1 +
> .../boot/dts/broadcom/bcmbca/bcm4912.dtsi | 1 +
> .../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 1 +
> .../boot/dts/broadcom/bcmbca/bcm63158.dtsi | 1 +
> .../boot/dts/broadcom/bcmbca/bcm6813.dtsi | 1 +
> .../boot/dts/broadcom/bcmbca/bcm6856.dtsi | 1 +
> .../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 1 +
> .../boot/dts/broadcom/northstar2/ns2.dtsi | 1 +
> .../boot/dts/broadcom/stingray/stingray.dtsi | 4 ++
> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 4 ++
> arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +
> .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 +
> .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 +
> .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 +
> .../arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++
> .../arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++
> .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 +++
> arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 1 +
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 +
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 +
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 +
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 +
> arch/arm64/boot/dts/freescale/imx8qm.dtsi | 2 +
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
> arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 1 +
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 2 +
> arch/arm64/boot/dts/freescale/s32v234.dtsi | 2 +
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 +
> arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 +
> arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++
> arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 ++
> arch/arm64/boot/dts/hisilicon/hip07.dtsi | 16 ++++++
> arch/arm64/boot/dts/lg/lg1312.dtsi | 1 +
> arch/arm64/boot/dts/lg/lg1313.dtsi | 1 +
> arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 +
> .../boot/dts/marvell/armada-ap806-dual.dtsi | 2 +
> .../boot/dts/marvell/armada-ap806-quad.dtsi | 4 ++
> .../boot/dts/marvell/armada-ap807-quad.dtsi | 4 ++
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 3 +
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 3 +
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 +
> arch/arm64/boot/dts/microchip/sparx5.dtsi | 1 +
> .../boot/dts/nuvoton/nuvoton-npcm845.dtsi | 1 +
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 15 +++++
> arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 +
> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 33 +++++++++++
> arch/arm64/boot/dts/qcom/msm8953.dtsi | 56 -------------------
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 +++
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 9 +++
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++
> arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +
> arch/arm64/boot/dts/qcom/sm6350.dtsi | 9 +++
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 9 +++
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 9 +++
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 9 +++
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 9 +++
> arch/arm64/boot/dts/realtek/rtd1293.dtsi | 1 +
> arch/arm64/boot/dts/realtek/rtd1295.dtsi | 1 +
> arch/arm64/boot/dts/realtek/rtd1296.dtsi | 1 +
> arch/arm64/boot/dts/realtek/rtd1395.dtsi | 1 +
> arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 2 +
> arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 1 +
> arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 1 +
> arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 1 +
> arch/arm64/boot/dts/rockchip/rk3308.dtsi | 1 +
> arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1 +
> .../boot/dts/socionext/uniphier-ld11.dtsi | 1 +
> .../boot/dts/socionext/uniphier-ld20.dtsi | 2 +
> .../boot/dts/socionext/uniphier-pxs3.dtsi | 1 +
> arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 1 +
> arch/arm64/boot/dts/tesla/fsd.dtsi | 2 +
> arch/arm64/boot/dts/ti/k3-am625.dtsi | 1 +
> arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 1 +
> arch/arm64/boot/dts/ti/k3-am642.dtsi | 1 +
> arch/arm64/boot/dts/ti/k3-am654.dtsi | 2 +
> arch/arm64/boot/dts/ti/k3-j7200.dtsi | 1 +
> arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 +
> arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 1 +
> 98 files changed, 299 insertions(+), 56 deletions(-)
>
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 00/23] Update cache properties for arm64 DTS
@ 2023-01-12 8:33 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2023-01-12 8:33 UTC (permalink / raw)
To: LKML
Cc: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, linux-arm-kernel, devicetree
(subset of the cc list for the Texas Instruments patch)
Hello,
Just a reminder in case the following patch was forgotten:
arm64: dts: Update cache properties for ti
Regards,
Pierre
On 11/7/22 16:56, Pierre Gondois wrote:
> v2:
> - Update/Add patches for missed cache properties requiring to be
> updated for the following platforns: bcm, amazon, arm, exynos,
> freescale, marvell, mediatek, nvidia, socinext, tesla, ti.
> Missed cache properties were detected using Rob Herring's branch:
> https://github.com/robherring/dt-schema/tree/cache-rework
> - v1 of exynos, tesla were merged.
> - Updated wrong reference in commit message.
> - Added received Rb/Acked-by.
>
> Align arm64 DTS to the DeviceTree specification v0.3 regarding
> cache properties. The patch-set mainly adds 'cache-level' or
> 'cache' compatibility properties.
> For one qcom DTS, level 1 cache nodes are removed as they should
> be in the cpu nodes.
>
> On another node, it seems that the 'cache-unified' is under-used.
> cache-unified:
> If present, specifies the cache has a unified or-
> ganization. If not present, specifies that the
> cache has a Harvard architecture with separate
> caches for instructions and data.
> Only a few l2 cache nodes have this property, and in the absence
> of [|d|i]-cache-size properties (or other), the cache is assumed to be
> split.
>
> The l2 cache of the Rockchip RK3308 platform is thus assumed to be
> split:
> l2: l2-cache {
> compatible = "cache";
> cache-level = <2>;
> };
> when the platform datasheet advertises a unified cache.
>
> No modification/check was made to correct that due to the lack of
> cache information for most platforms.
>
> Pierre Gondois (23):
> arm64: dts: Update cache properties for amazon
> arm64: dts: Update cache properties for amd
> arm64: dts: Update cache properties for amlogic
> arm64: dts: Update cache properties for apm
> arm64: dts: Update cache properties for arm
> arm64: dts: Update cache properties for broadcom
> arm64: dts: Update cache properties for exynos
> arm64: dts: Update cache properties for freescale
> arm64: dts: Update cache properties for hisilicon
> arm64: dts: Update cache properties for lg
> arm64: dts: Update cache properties for marvell
> arm64: dts: Update cache properties for mediatek
> arm64: dts: Update cache properties for microchip
> arm64: dts: Update cache properties for nuvoton
> arm64: dts: Update cache properties for nvidia
> arm64: dts: Update cache properties for qcom
> arm64: dts: Update cache properties for realtek
> arm64: dts: Update cache properties for renesas
> arm64: dts: Update cache properties for rockchip
> arm64: dts: Update cache properties for socionext
> arm64: dts: Update cache properties for synaptics
> arm64: dts: Update cache properties for tesla
> arm64: dts: Update cache properties for ti
>
> arch/arm/boot/dts/bcm2711.dtsi | 1 +
> arch/arm/boot/dts/bcm2837.dtsi | 1 +
> arch/arm64/boot/dts/amazon/alpine-v3.dtsi | 4 ++
> arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi | 9 +++
> arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 1 +
> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 1 +
> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 1 +
> arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 1 +
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 +
> arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 1 +
> arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 4 ++
> arch/arm64/boot/dts/apm/apm-storm.dtsi | 4 ++
> arch/arm64/boot/dts/arm/corstone1000.dtsi | 1 +
> arch/arm64/boot/dts/arm/foundation-v8.dtsi | 1 +
> arch/arm64/boot/dts/arm/juno-r1.dts | 2 +
> arch/arm64/boot/dts/arm/juno-r2.dts | 2 +
> arch/arm64/boot/dts/arm/juno.dts | 2 +
> arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 1 +
> .../boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 1 +
> .../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 1 +
> .../boot/dts/broadcom/bcmbca/bcm4912.dtsi | 1 +
> .../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 1 +
> .../boot/dts/broadcom/bcmbca/bcm63158.dtsi | 1 +
> .../boot/dts/broadcom/bcmbca/bcm6813.dtsi | 1 +
> .../boot/dts/broadcom/bcmbca/bcm6856.dtsi | 1 +
> .../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 1 +
> .../boot/dts/broadcom/northstar2/ns2.dtsi | 1 +
> .../boot/dts/broadcom/stingray/stingray.dtsi | 4 ++
> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 4 ++
> arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +
> .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 +
> .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 +
> .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 +
> .../arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++
> .../arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++
> .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 +++
> arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 1 +
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 +
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 +
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 +
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 +
> arch/arm64/boot/dts/freescale/imx8qm.dtsi | 2 +
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
> arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 1 +
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 2 +
> arch/arm64/boot/dts/freescale/s32v234.dtsi | 2 +
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 +
> arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 +
> arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++
> arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 ++
> arch/arm64/boot/dts/hisilicon/hip07.dtsi | 16 ++++++
> arch/arm64/boot/dts/lg/lg1312.dtsi | 1 +
> arch/arm64/boot/dts/lg/lg1313.dtsi | 1 +
> arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 +
> .../boot/dts/marvell/armada-ap806-dual.dtsi | 2 +
> .../boot/dts/marvell/armada-ap806-quad.dtsi | 4 ++
> .../boot/dts/marvell/armada-ap807-quad.dtsi | 4 ++
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 3 +
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 3 +
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 +
> arch/arm64/boot/dts/microchip/sparx5.dtsi | 1 +
> .../boot/dts/nuvoton/nuvoton-npcm845.dtsi | 1 +
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 15 +++++
> arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 +
> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 33 +++++++++++
> arch/arm64/boot/dts/qcom/msm8953.dtsi | 56 -------------------
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 +++
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 9 +++
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++
> arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +
> arch/arm64/boot/dts/qcom/sm6350.dtsi | 9 +++
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 9 +++
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 9 +++
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 9 +++
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 9 +++
> arch/arm64/boot/dts/realtek/rtd1293.dtsi | 1 +
> arch/arm64/boot/dts/realtek/rtd1295.dtsi | 1 +
> arch/arm64/boot/dts/realtek/rtd1296.dtsi | 1 +
> arch/arm64/boot/dts/realtek/rtd1395.dtsi | 1 +
> arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 2 +
> arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 1 +
> arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 1 +
> arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 1 +
> arch/arm64/boot/dts/rockchip/rk3308.dtsi | 1 +
> arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1 +
> .../boot/dts/socionext/uniphier-ld11.dtsi | 1 +
> .../boot/dts/socionext/uniphier-ld20.dtsi | 2 +
> .../boot/dts/socionext/uniphier-pxs3.dtsi | 1 +
> arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 1 +
> arch/arm64/boot/dts/tesla/fsd.dtsi | 2 +
> arch/arm64/boot/dts/ti/k3-am625.dtsi | 1 +
> arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 1 +
> arch/arm64/boot/dts/ti/k3-am642.dtsi | 1 +
> arch/arm64/boot/dts/ti/k3-am654.dtsi | 2 +
> arch/arm64/boot/dts/ti/k3-j7200.dtsi | 1 +
> arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 +
> arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 1 +
> 98 files changed, 299 insertions(+), 56 deletions(-)
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 13/23] arm64: dts: Update cache properties for microchip
2022-11-07 15:57 ` Pierre Gondois
@ 2023-01-12 8:33 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2023-01-12 8:33 UTC (permalink / raw)
To: LKML
Cc: Rob Herring, Krzysztof Kozlowski, Lars Povlsen, Steen Hegelund,
Daniel Machon, UNGLinuxDriver, devicetree, linux-arm-kernel
(subset for cc list)
Hello,
Just a reminder in case the patch was forgotten,
Regards,
Pierre
On 11/7/22 16:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
> arch/arm64/boot/dts/microchip/sparx5.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> index 2dd5e38820b1..c4bca23b96b9 100644
> --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> @@ -52,6 +52,7 @@ cpu1: cpu@1 {
> };
> L2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 13/23] arm64: dts: Update cache properties for microchip
@ 2023-01-12 8:33 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2023-01-12 8:33 UTC (permalink / raw)
To: LKML
Cc: Rob Herring, Krzysztof Kozlowski, Lars Povlsen, Steen Hegelund,
Daniel Machon, UNGLinuxDriver, devicetree, linux-arm-kernel
(subset for cc list)
Hello,
Just a reminder in case the patch was forgotten,
Regards,
Pierre
On 11/7/22 16:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
> arch/arm64/boot/dts/microchip/sparx5.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> index 2dd5e38820b1..c4bca23b96b9 100644
> --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> @@ -52,6 +52,7 @@ cpu1: cpu@1 {
> };
> L2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 04/23] arm64: dts: Update cache properties for apm
2022-11-07 15:56 ` Pierre Gondois
(?)
@ 2023-01-12 8:33 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2023-01-12 8:33 UTC (permalink / raw)
To: LKML; +Cc: Khuong Dinh, Rob Herring, Krzysztof Kozlowski, devicetree
(subset for cc list)
Hello,
Just a reminder in case the patch was forgotten,
Regards,
Pierre
On 11/7/22 16:56, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
> arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 4 ++++
> arch/arm64/boot/dts/apm/apm-storm.dtsi | 4 ++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
> index a8526f8157ec..68ba865fcd58 100644
> --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
> +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
> @@ -97,15 +97,19 @@ cpu@301 {
> };
> xgene_L2_0: l2-cache-0 {
> compatible = "cache";
> + cache-level = <2>;
> };
> xgene_L2_1: l2-cache-1 {
> compatible = "cache";
> + cache-level = <2>;
> };
> xgene_L2_2: l2-cache-2 {
> compatible = "cache";
> + cache-level = <2>;
> };
> xgene_L2_3: l2-cache-3 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
> index f56d687f772d..9ac7417f65eb 100644
> --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
> +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
> @@ -81,15 +81,19 @@ cpu@301 {
> };
> xgene_L2_0: l2-cache-0 {
> compatible = "cache";
> + cache-level = <2>;
> };
> xgene_L2_1: l2-cache-1 {
> compatible = "cache";
> + cache-level = <2>;
> };
> xgene_L2_2: l2-cache-2 {
> compatible = "cache";
> + cache-level = <2>;
> };
> xgene_L2_3: l2-cache-3 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 02/23] arm64: dts: Update cache properties for amd
2022-11-07 15:56 ` Pierre Gondois
(?)
@ 2023-01-12 8:34 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2023-01-12 8:34 UTC (permalink / raw)
To: LKML
Cc: Brijesh Singh, Suravee Suthikulpanit, Tom Lendacky, Rob Herring,
Krzysztof Kozlowski, devicetree
(subset for cc list)
Hello,
Just a reminder in case the patch was forgotten,
Regards,
Pierre
On 11/7/22 16:56, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
> arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
> index 93688a0b6820..9f2d983e082d 100644
> --- a/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
> +++ b/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
> @@ -163,38 +163,47 @@ CPU7: cpu@301 {
> };
>
> L2_0: l2-cache0 {
> + compatible = "cache";
> cache-size = <0x100000>;
> cache-line-size = <64>;
> cache-sets = <1024>;
> cache-unified;
> + cache-level = <2>;
> next-level-cache = <&L3>;
> };
>
> L2_1: l2-cache1 {
> + compatible = "cache";
> cache-size = <0x100000>;
> cache-line-size = <64>;
> cache-sets = <1024>;
> cache-unified;
> + cache-level = <2>;
> next-level-cache = <&L3>;
> };
>
> L2_2: l2-cache2 {
> + compatible = "cache";
> cache-size = <0x100000>;
> cache-line-size = <64>;
> cache-sets = <1024>;
> cache-unified;
> + cache-level = <2>;
> next-level-cache = <&L3>;
> };
>
> L2_3: l2-cache3 {
> + compatible = "cache";
> cache-size = <0x100000>;
> cache-line-size = <64>;
> cache-sets = <1024>;
> cache-unified;
> + cache-level = <2>;
> next-level-cache = <&L3>;
> };
>
> L3: l3-cache {
> + compatible = "cache";
> cache-level = <3>;
> cache-size = <0x800000>;
> cache-line-size = <64>;
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 14/23] arm64: dts: Update cache properties for nuvoton
2022-11-07 15:57 ` Pierre Gondois
@ 2023-01-12 8:34 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2023-01-12 8:34 UTC (permalink / raw)
To: LKML
Cc: Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Rob Herring, Krzysztof Kozlowski,
openbmc, devicetree
(subset for cc list)
Hello,
Just a reminder in case the patch was forgotten,
Regards,
Pierre
On 11/7/22 16:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
> arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
> index 12118b75c0e6..4c196140634b 100644
> --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
> +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
> @@ -49,6 +49,7 @@ cpu3: cpu@3 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 14/23] arm64: dts: Update cache properties for nuvoton
@ 2023-01-12 8:34 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2023-01-12 8:34 UTC (permalink / raw)
To: LKML
Cc: devicetree, Benjamin Fair, Avi Fishman, Patrick Venture, openbmc,
Tali Perry, Rob Herring, Krzysztof Kozlowski, Tomer Maimon
(subset for cc list)
Hello,
Just a reminder in case the patch was forgotten,
Regards,
Pierre
On 11/7/22 16:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
> arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
> index 12118b75c0e6..4c196140634b 100644
> --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
> +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
> @@ -49,6 +49,7 @@ cpu3: cpu@3 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 10/23] arm64: dts: Update cache properties for lg
2022-11-07 15:57 ` Pierre Gondois
@ 2023-01-12 8:34 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2023-01-12 8:34 UTC (permalink / raw)
To: LKML
Cc: Chanho Min, Rob Herring, Krzysztof Kozlowski, linux-arm-kernel,
devicetree
(subset for cc list)
Hello,
Just a reminder in case the patch was forgotten,
Regards,
Pierre
On 11/7/22 16:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
> arch/arm64/boot/dts/lg/lg1312.dtsi | 1 +
> arch/arm64/boot/dts/lg/lg1313.dtsi | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi
> index 78ae73d0cf36..25ed9aeee2dc 100644
> --- a/arch/arm64/boot/dts/lg/lg1312.dtsi
> +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
> @@ -48,6 +48,7 @@ cpu3: cpu@3 {
> };
> L2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi
> index 2173316573be..db82fd4cc759 100644
> --- a/arch/arm64/boot/dts/lg/lg1313.dtsi
> +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
> @@ -48,6 +48,7 @@ cpu3: cpu@3 {
> };
> L2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 10/23] arm64: dts: Update cache properties for lg
@ 2023-01-12 8:34 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2023-01-12 8:34 UTC (permalink / raw)
To: LKML
Cc: Chanho Min, Rob Herring, Krzysztof Kozlowski, linux-arm-kernel,
devicetree
(subset for cc list)
Hello,
Just a reminder in case the patch was forgotten,
Regards,
Pierre
On 11/7/22 16:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
> arch/arm64/boot/dts/lg/lg1312.dtsi | 1 +
> arch/arm64/boot/dts/lg/lg1313.dtsi | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi
> index 78ae73d0cf36..25ed9aeee2dc 100644
> --- a/arch/arm64/boot/dts/lg/lg1312.dtsi
> +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
> @@ -48,6 +48,7 @@ cpu3: cpu@3 {
> };
> L2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi
> index 2173316573be..db82fd4cc759 100644
> --- a/arch/arm64/boot/dts/lg/lg1313.dtsi
> +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
> @@ -48,6 +48,7 @@ cpu3: cpu@3 {
> };
> L2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 01/23] arm64: dts: Update cache properties for amazon
2022-11-07 15:56 ` Pierre Gondois
@ 2023-01-12 8:34 ` Pierre Gondois
-1 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2023-01-12 8:34 UTC (permalink / raw)
To: LKML
Cc: Tsahee Zidenberg, Antoine Tenart, Rob Herring,
Krzysztof Kozlowski, linux-arm-kernel, devicetree
(subset for cc list)
Hello,
Just a reminder in case the patch was forgotten,
Regards,
Pierre
On 11/7/22 16:56, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
> arch/arm64/boot/dts/amazon/alpine-v3.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi
> index 73a352ea8fd5..ba7e56dc85db 100644
> --- a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi
> +++ b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi
> @@ -246,6 +246,7 @@ cpu@303 {
>
> cluster0_l2: cache@0 {
> compatible = "cache";
> + cache-unified;
> cache-size = <0x200000>;
> cache-line-size = <64>;
> cache-sets = <2048>;
> @@ -254,6 +255,7 @@ cluster0_l2: cache@0 {
>
> cluster1_l2: cache@100 {
> compatible = "cache";
> + cache-unified;
> cache-size = <0x200000>;
> cache-line-size = <64>;
> cache-sets = <2048>;
> @@ -262,6 +264,7 @@ cluster1_l2: cache@100 {
>
> cluster2_l2: cache@200 {
> compatible = "cache";
> + cache-unified;
> cache-size = <0x200000>;
> cache-line-size = <64>;
> cache-sets = <2048>;
> @@ -270,6 +273,7 @@ cluster2_l2: cache@200 {
>
> cluster3_l2: cache@300 {
> compatible = "cache";
> + cache-unified;
> cache-size = <0x200000>;
> cache-line-size = <64>;
> cache-sets = <2048>;
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 01/23] arm64: dts: Update cache properties for amazon
@ 2023-01-12 8:34 ` Pierre Gondois
0 siblings, 0 replies; 107+ messages in thread
From: Pierre Gondois @ 2023-01-12 8:34 UTC (permalink / raw)
To: LKML
Cc: Tsahee Zidenberg, Antoine Tenart, Rob Herring,
Krzysztof Kozlowski, linux-arm-kernel, devicetree
(subset for cc list)
Hello,
Just a reminder in case the patch was forgotten,
Regards,
Pierre
On 11/7/22 16:56, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
> arch/arm64/boot/dts/amazon/alpine-v3.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi
> index 73a352ea8fd5..ba7e56dc85db 100644
> --- a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi
> +++ b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi
> @@ -246,6 +246,7 @@ cpu@303 {
>
> cluster0_l2: cache@0 {
> compatible = "cache";
> + cache-unified;
> cache-size = <0x200000>;
> cache-line-size = <64>;
> cache-sets = <2048>;
> @@ -254,6 +255,7 @@ cluster0_l2: cache@0 {
>
> cluster1_l2: cache@100 {
> compatible = "cache";
> + cache-unified;
> cache-size = <0x200000>;
> cache-line-size = <64>;
> cache-sets = <2048>;
> @@ -262,6 +264,7 @@ cluster1_l2: cache@100 {
>
> cluster2_l2: cache@200 {
> compatible = "cache";
> + cache-unified;
> cache-size = <0x200000>;
> cache-line-size = <64>;
> cache-sets = <2048>;
> @@ -270,6 +273,7 @@ cluster2_l2: cache@200 {
>
> cluster3_l2: cache@300 {
> compatible = "cache";
> + cache-unified;
> cache-size = <0x200000>;
> cache-line-size = <64>;
> cache-sets = <2048>;
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 17/23] arm64: dts: Update cache properties for realtek
2023-01-12 8:33 ` Pierre Gondois
@ 2023-01-12 8:51 ` Andreas Färber
-1 siblings, 0 replies; 107+ messages in thread
From: Andreas Färber @ 2023-01-12 8:51 UTC (permalink / raw)
To: Pierre Gondois, LKML
Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-kernel,
linux-realtek-soc, devicetree
Hello,
On 12.01.23 09:33, Pierre Gondois wrote:
> Just a reminder in case the patch was forgotten,
[...]
> On 11/7/22 16:57, Pierre Gondois wrote:
>> The DeviceTree Specification v0.3 specifies that the cache node
>> 'compatible' and 'cache-level' properties are 'required'. Cf.
>> s3.8 Multi-level and Shared Cache Nodes
>> The 'cache-unified' property should be present if one of the
>> properties for unified cache is present ('cache-size', ...).
>>
>> Update the Device Trees accordingly.
>>
>> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
>> ---
>> arch/arm64/boot/dts/realtek/rtd1293.dtsi | 1 +
>> arch/arm64/boot/dts/realtek/rtd1295.dtsi | 1 +
>> arch/arm64/boot/dts/realtek/rtd1296.dtsi | 1 +
>> arch/arm64/boot/dts/realtek/rtd1395.dtsi | 1 +
>> arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 2 ++
>> 5 files changed, 6 insertions(+)
Short-term I can offer an
Acked-by: Andreas Färber <afaerber@suse.de>
Regards,
Andreas
>>
>> diff --git a/arch/arm64/boot/dts/realtek/rtd1293.dtsi
>> b/arch/arm64/boot/dts/realtek/rtd1293.dtsi
>> index 2d92b56ac94d..0696b99fc40d 100644
>> --- a/arch/arm64/boot/dts/realtek/rtd1293.dtsi
>> +++ b/arch/arm64/boot/dts/realtek/rtd1293.dtsi
>> @@ -30,6 +30,7 @@ cpu1: cpu@1 {
>> l2: l2-cache {
>> compatible = "cache";
>> + cache-level = <2>;
>> };
>> };
>> diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi
>> b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
>> index 1402abe80ea1..4ca322e420e6 100644
>> --- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi
>> +++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
>> @@ -44,6 +44,7 @@ cpu3: cpu@3 {
>> l2: l2-cache {
>> compatible = "cache";
>> + cache-level = <2>;
>> };
>> };
>> diff --git a/arch/arm64/boot/dts/realtek/rtd1296.dtsi
>> b/arch/arm64/boot/dts/realtek/rtd1296.dtsi
>> index fb864a139c97..03fccd48f0c0 100644
>> --- a/arch/arm64/boot/dts/realtek/rtd1296.dtsi
>> +++ b/arch/arm64/boot/dts/realtek/rtd1296.dtsi
>> @@ -44,6 +44,7 @@ cpu3: cpu@3 {
>> l2: l2-cache {
>> compatible = "cache";
>> + cache-level = <2>;
>> };
>> };
>> diff --git a/arch/arm64/boot/dts/realtek/rtd1395.dtsi
>> b/arch/arm64/boot/dts/realtek/rtd1395.dtsi
>> index 05c9216a87ee..94c0a8cf4953 100644
>> --- a/arch/arm64/boot/dts/realtek/rtd1395.dtsi
>> +++ b/arch/arm64/boot/dts/realtek/rtd1395.dtsi
>> @@ -44,6 +44,7 @@ cpu3: cpu@3 {
>> l2: l2-cache {
>> compatible = "cache";
>> + cache-level = <2>;
>> };
>> };
>> diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
>> b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
>> index afba5f04c8ec..2ee9ba1ecdc1 100644
>> --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
>> +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
>> @@ -87,12 +87,14 @@ cpu5: cpu@500 {
>> l2: l2-cache {
>> compatible = "cache";
>> + cache-level = <2>;
>> next-level-cache = <&l3>;
>> };
>> l3: l3-cache {
>> compatible = "cache";
>> + cache-level = <3>;
>> };
>> };
--
SUSE Software Solutions Germany GmbH
Frankenstr. 146, 90461 Nürnberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nürnberg)
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 17/23] arm64: dts: Update cache properties for realtek
@ 2023-01-12 8:51 ` Andreas Färber
0 siblings, 0 replies; 107+ messages in thread
From: Andreas Färber @ 2023-01-12 8:51 UTC (permalink / raw)
To: Pierre Gondois, LKML
Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-kernel,
linux-realtek-soc, devicetree
Hello,
On 12.01.23 09:33, Pierre Gondois wrote:
> Just a reminder in case the patch was forgotten,
[...]
> On 11/7/22 16:57, Pierre Gondois wrote:
>> The DeviceTree Specification v0.3 specifies that the cache node
>> 'compatible' and 'cache-level' properties are 'required'. Cf.
>> s3.8 Multi-level and Shared Cache Nodes
>> The 'cache-unified' property should be present if one of the
>> properties for unified cache is present ('cache-size', ...).
>>
>> Update the Device Trees accordingly.
>>
>> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
>> ---
>> arch/arm64/boot/dts/realtek/rtd1293.dtsi | 1 +
>> arch/arm64/boot/dts/realtek/rtd1295.dtsi | 1 +
>> arch/arm64/boot/dts/realtek/rtd1296.dtsi | 1 +
>> arch/arm64/boot/dts/realtek/rtd1395.dtsi | 1 +
>> arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 2 ++
>> 5 files changed, 6 insertions(+)
Short-term I can offer an
Acked-by: Andreas Färber <afaerber@suse.de>
Regards,
Andreas
>>
>> diff --git a/arch/arm64/boot/dts/realtek/rtd1293.dtsi
>> b/arch/arm64/boot/dts/realtek/rtd1293.dtsi
>> index 2d92b56ac94d..0696b99fc40d 100644
>> --- a/arch/arm64/boot/dts/realtek/rtd1293.dtsi
>> +++ b/arch/arm64/boot/dts/realtek/rtd1293.dtsi
>> @@ -30,6 +30,7 @@ cpu1: cpu@1 {
>> l2: l2-cache {
>> compatible = "cache";
>> + cache-level = <2>;
>> };
>> };
>> diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi
>> b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
>> index 1402abe80ea1..4ca322e420e6 100644
>> --- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi
>> +++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
>> @@ -44,6 +44,7 @@ cpu3: cpu@3 {
>> l2: l2-cache {
>> compatible = "cache";
>> + cache-level = <2>;
>> };
>> };
>> diff --git a/arch/arm64/boot/dts/realtek/rtd1296.dtsi
>> b/arch/arm64/boot/dts/realtek/rtd1296.dtsi
>> index fb864a139c97..03fccd48f0c0 100644
>> --- a/arch/arm64/boot/dts/realtek/rtd1296.dtsi
>> +++ b/arch/arm64/boot/dts/realtek/rtd1296.dtsi
>> @@ -44,6 +44,7 @@ cpu3: cpu@3 {
>> l2: l2-cache {
>> compatible = "cache";
>> + cache-level = <2>;
>> };
>> };
>> diff --git a/arch/arm64/boot/dts/realtek/rtd1395.dtsi
>> b/arch/arm64/boot/dts/realtek/rtd1395.dtsi
>> index 05c9216a87ee..94c0a8cf4953 100644
>> --- a/arch/arm64/boot/dts/realtek/rtd1395.dtsi
>> +++ b/arch/arm64/boot/dts/realtek/rtd1395.dtsi
>> @@ -44,6 +44,7 @@ cpu3: cpu@3 {
>> l2: l2-cache {
>> compatible = "cache";
>> + cache-level = <2>;
>> };
>> };
>> diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
>> b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
>> index afba5f04c8ec..2ee9ba1ecdc1 100644
>> --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
>> +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
>> @@ -87,12 +87,14 @@ cpu5: cpu@500 {
>> l2: l2-cache {
>> compatible = "cache";
>> + cache-level = <2>;
>> next-level-cache = <&l3>;
>> };
>> l3: l3-cache {
>> compatible = "cache";
>> + cache-level = <3>;
>> };
>> };
--
SUSE Software Solutions Germany GmbH
Frankenstr. 146, 90461 Nürnberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nürnberg)
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 20/23] arm64: dts: Update cache properties for socionext
2023-01-12 8:33 ` Pierre Gondois
@ 2023-01-12 10:27 ` Kunihiko Hayashi
-1 siblings, 0 replies; 107+ messages in thread
From: Kunihiko Hayashi @ 2023-01-12 10:27 UTC (permalink / raw)
To: Pierre Gondois
Cc: Rob Herring, Krzysztof Kozlowski, Masami Hiramatsu, devicetree,
linux-arm-kernel, LKML
Hi Pierre,
On 2023/01/12 17:33, Pierre Gondois wrote:
> (subset for cc list)
> Hello,
> Just a reminder in case the patch was forgotten,
> Regards,
> Pierre
>
> On 11/7/22 16:57, Pierre Gondois wrote:
>> The DeviceTree Specification v0.3 specifies that the cache node
>> 'compatible' and 'cache-level' properties are 'required'. Cf.
>> s3.8 Multi-level and Shared Cache Nodes
>> The 'cache-unified' property should be present if one of the
>> properties for unified cache is present ('cache-size', ...).
>>
>> Update the Device Trees accordingly.
>>
>> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
>> ---
>> arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 1 +
>> arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++
>> arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 1 +
>> 3 files changed, 4 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
>> b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
>> index 1c76b4375b2e..6e1e00939214 100644
>> --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
>> +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
>> @@ -52,6 +52,7 @@ cpu1: cpu@1 {
>>
>> l2: l2-cache {
>> compatible = "cache";
>> + cache-level = <2>;
>> };
>> };
>>
>> diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
>> b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
>> index 9308458f9611..db7d20a1a301 100644
>> --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
>> +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
>> @@ -86,10 +86,12 @@ cpu3: cpu@101 {
>>
>> a72_l2: l2-cache0 {
>> compatible = "cache";
>> + cache-level = <2>;
>> };
>>
>> a53_l2: l2-cache1 {
>> compatible = "cache";
>> + cache-level = <2>;
>> };
>> };
>>
>> diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
>> b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
>> index b0c29510a7da..9ce544c9ea0a 100644
>> --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
>> +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
>> @@ -83,6 +83,7 @@ cpu3: cpu@3 {
>>
>> l2: l2-cache {
>> compatible = "cache";
>> + cache-level = <2>;
>> };
>> };
>>
Looks good to me. "cache-unified" will be added with other cache-related
(size etc.) properties if needed.
Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Thank you,
---
Best Regards
Kunihiko Hayashi
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 20/23] arm64: dts: Update cache properties for socionext
@ 2023-01-12 10:27 ` Kunihiko Hayashi
0 siblings, 0 replies; 107+ messages in thread
From: Kunihiko Hayashi @ 2023-01-12 10:27 UTC (permalink / raw)
To: Pierre Gondois
Cc: Rob Herring, Krzysztof Kozlowski, Masami Hiramatsu, devicetree,
linux-arm-kernel, LKML
Hi Pierre,
On 2023/01/12 17:33, Pierre Gondois wrote:
> (subset for cc list)
> Hello,
> Just a reminder in case the patch was forgotten,
> Regards,
> Pierre
>
> On 11/7/22 16:57, Pierre Gondois wrote:
>> The DeviceTree Specification v0.3 specifies that the cache node
>> 'compatible' and 'cache-level' properties are 'required'. Cf.
>> s3.8 Multi-level and Shared Cache Nodes
>> The 'cache-unified' property should be present if one of the
>> properties for unified cache is present ('cache-size', ...).
>>
>> Update the Device Trees accordingly.
>>
>> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
>> ---
>> arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 1 +
>> arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++
>> arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 1 +
>> 3 files changed, 4 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
>> b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
>> index 1c76b4375b2e..6e1e00939214 100644
>> --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
>> +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
>> @@ -52,6 +52,7 @@ cpu1: cpu@1 {
>>
>> l2: l2-cache {
>> compatible = "cache";
>> + cache-level = <2>;
>> };
>> };
>>
>> diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
>> b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
>> index 9308458f9611..db7d20a1a301 100644
>> --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
>> +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
>> @@ -86,10 +86,12 @@ cpu3: cpu@101 {
>>
>> a72_l2: l2-cache0 {
>> compatible = "cache";
>> + cache-level = <2>;
>> };
>>
>> a53_l2: l2-cache1 {
>> compatible = "cache";
>> + cache-level = <2>;
>> };
>> };
>>
>> diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
>> b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
>> index b0c29510a7da..9ce544c9ea0a 100644
>> --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
>> +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
>> @@ -83,6 +83,7 @@ cpu3: cpu@3 {
>>
>> l2: l2-cache {
>> compatible = "cache";
>> + cache-level = <2>;
>> };
>> };
>>
Looks good to me. "cache-unified" will be added with other cache-related
(size etc.) properties if needed.
Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Thank you,
---
Best Regards
Kunihiko Hayashi
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 02/23] arm64: dts: Update cache properties for amd
2022-11-07 15:56 ` Pierre Gondois
@ 2023-01-12 15:31 ` Tom Lendacky
-1 siblings, 0 replies; 107+ messages in thread
From: Tom Lendacky @ 2023-01-12 15:31 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Neil Armstrong, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl, Khuong Dinh, Liviu Dudau,
Sudeep Holla, Lorenzo Pieralisi, William Zhang, Anand Gore,
Kursad Oney, Rafał Miłecki, Alim Akhtar, Shawn Guo,
Li Yang, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Zhou Peng, Shenwei Wang, Ming Qian,
Peng Fan, Tim Harvey, Adam Ford, Lucas Stach, Richard Zhu,
Li Jun, Markus Niebel, Joakim Zhang, Marek Vasut,
Laurent Pinchart, Paul Elder, Alexander Stein, Martin Kepplinger,
David Heidelberg, Liu Ying, Oliver Graute, Dong Aisheng,
Wei Fang, Clark Wang, Jacky Bai, Chris Packham, Vadym Kochan,
Sameer Pujar, Prathamesh Shete, Mikko Perttunen, Akhil R,
Sumit Gupta, Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, devicetree, linux-rpi-kernel, linux-arm-kernel,
linux-amlogic, linux-samsung-soc, linux-mediatek, openbmc,
linux-tegra, linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
On 11/7/22 09:56, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
> ---
> arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
> index 93688a0b6820..9f2d983e082d 100644
> --- a/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
> +++ b/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
> @@ -163,38 +163,47 @@ CPU7: cpu@301 {
> };
>
> L2_0: l2-cache0 {
> + compatible = "cache";
> cache-size = <0x100000>;
> cache-line-size = <64>;
> cache-sets = <1024>;
> cache-unified;
> + cache-level = <2>;
> next-level-cache = <&L3>;
> };
>
> L2_1: l2-cache1 {
> + compatible = "cache";
> cache-size = <0x100000>;
> cache-line-size = <64>;
> cache-sets = <1024>;
> cache-unified;
> + cache-level = <2>;
> next-level-cache = <&L3>;
> };
>
> L2_2: l2-cache2 {
> + compatible = "cache";
> cache-size = <0x100000>;
> cache-line-size = <64>;
> cache-sets = <1024>;
> cache-unified;
> + cache-level = <2>;
> next-level-cache = <&L3>;
> };
>
> L2_3: l2-cache3 {
> + compatible = "cache";
> cache-size = <0x100000>;
> cache-line-size = <64>;
> cache-sets = <1024>;
> cache-unified;
> + cache-level = <2>;
> next-level-cache = <&L3>;
> };
>
> L3: l3-cache {
> + compatible = "cache";
> cache-level = <3>;
> cache-size = <0x800000>;
> cache-line-size = <64>;
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 02/23] arm64: dts: Update cache properties for amd
@ 2023-01-12 15:31 ` Tom Lendacky
0 siblings, 0 replies; 107+ messages in thread
From: Tom Lendacky @ 2023-01-12 15:31 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Neil Armstrong, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl, Khuong Dinh, Liviu Dudau,
Sudeep Holla, Lorenzo Pieralisi, William Zhang, Anand Gore,
Kursad Oney, Rafał Miłecki, Alim Akhtar, Shawn Guo,
Li Yang, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Zhou Peng, Shenwei Wang, Ming Qian,
Peng Fan, Tim Harvey, Adam Ford, Lucas Stach, Richard Zhu,
Li Jun, Markus Niebel, Joakim Zhang, Marek Vasut,
Laurent Pinchart, Paul Elder, Alexander Stein, Martin Kepplinger,
David Heidelberg, Liu Ying, Oliver Graute, Dong Aisheng,
Wei Fang, Clark Wang, Jacky Bai, Chris Packham, Vadym Kochan,
Sameer Pujar, Prathamesh Shete, Mikko Perttunen, Akhil R,
Sumit Gupta, Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, devicetree, linux-rpi-kernel, linux-arm-kernel,
linux-amlogic, linux-samsung-soc, linux-mediatek, openbmc,
linux-tegra, linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
On 11/7/22 09:56, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
> ---
> arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
> index 93688a0b6820..9f2d983e082d 100644
> --- a/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
> +++ b/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
> @@ -163,38 +163,47 @@ CPU7: cpu@301 {
> };
>
> L2_0: l2-cache0 {
> + compatible = "cache";
> cache-size = <0x100000>;
> cache-line-size = <64>;
> cache-sets = <1024>;
> cache-unified;
> + cache-level = <2>;
> next-level-cache = <&L3>;
> };
>
> L2_1: l2-cache1 {
> + compatible = "cache";
> cache-size = <0x100000>;
> cache-line-size = <64>;
> cache-sets = <1024>;
> cache-unified;
> + cache-level = <2>;
> next-level-cache = <&L3>;
> };
>
> L2_2: l2-cache2 {
> + compatible = "cache";
> cache-size = <0x100000>;
> cache-line-size = <64>;
> cache-sets = <1024>;
> cache-unified;
> + cache-level = <2>;
> next-level-cache = <&L3>;
> };
>
> L2_3: l2-cache3 {
> + compatible = "cache";
> cache-size = <0x100000>;
> cache-line-size = <64>;
> cache-sets = <1024>;
> cache-unified;
> + cache-level = <2>;
> next-level-cache = <&L3>;
> };
>
> L3: l3-cache {
> + compatible = "cache";
> cache-level = <3>;
> cache-size = <0x800000>;
> cache-line-size = <64>;
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: Re: [PATCH v2 10/23] arm64: dts: Update cache properties for lg
2023-01-12 8:34 ` Pierre Gondois
@ 2023-01-13 1:12 ` Chanho Min
-1 siblings, 0 replies; 107+ messages in thread
From: Chanho Min @ 2023-01-13 1:12 UTC (permalink / raw)
To: Pierre Gondois, LKML
Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-kernel, devicetree,
Lee Gunho
23. 1. 12. 오후 5:34에 Pierre Gondois 이(가) 쓴 글:
> (subset for cc list)
> Hello,
> Just a reminder in case the patch was forgotten,
> Regards,
> Pierre
>
> On 11/7/22 16:57, Pierre Gondois wrote:
>> The DeviceTree Specification v0.3 specifies that the cache node
>> 'compatible' and 'cache-level' properties are 'required'. Cf.
>> s3.8 Multi-level and Shared Cache Nodes
>> The 'cache-unified' property should be present if one of the
>> properties for unified cache is present ('cache-size', ...).
>>
>> Update the Device Trees accordingly.
>>
>> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Acked-by: Chanho Min <chanho.min@lge.com>
>> ---
>> arch/arm64/boot/dts/lg/lg1312.dtsi | 1 +
>> arch/arm64/boot/dts/lg/lg1313.dtsi | 1 +
>> 2 files changed, 2 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi
>> b/arch/arm64/boot/dts/lg/lg1312.dtsi
>> index 78ae73d0cf36..25ed9aeee2dc 100644
>> --- a/arch/arm64/boot/dts/lg/lg1312.dtsi
>> +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
>> @@ -48,6 +48,7 @@ cpu3: cpu@3 {
>> };
>> L2_0: l2-cache0 {
>> compatible = "cache";
>> + cache-level = <2>;
>> };
>> };
>> diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi
>> b/arch/arm64/boot/dts/lg/lg1313.dtsi
>> index 2173316573be..db82fd4cc759 100644
>> --- a/arch/arm64/boot/dts/lg/lg1313.dtsi
>> +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
>> @@ -48,6 +48,7 @@ cpu3: cpu@3 {
>> };
>> L2_0: l2-cache0 {Re: Re: [PATCH v2 10/23] arm64: dts: Update cache properties for lg
>> compatible = "cache";
>> + cache-leveRe: Re: [PATCH v2 10/23] arm64: dts: Update cache properties for lgl = <2>;
>> };
>> };
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: Re: [PATCH v2 10/23] arm64: dts: Update cache properties for lg
@ 2023-01-13 1:12 ` Chanho Min
0 siblings, 0 replies; 107+ messages in thread
From: Chanho Min @ 2023-01-13 1:12 UTC (permalink / raw)
To: Pierre Gondois, LKML
Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-kernel, devicetree,
Lee Gunho
23. 1. 12. 오후 5:34에 Pierre Gondois 이(가) 쓴 글:
> (subset for cc list)
> Hello,
> Just a reminder in case the patch was forgotten,
> Regards,
> Pierre
>
> On 11/7/22 16:57, Pierre Gondois wrote:
>> The DeviceTree Specification v0.3 specifies that the cache node
>> 'compatible' and 'cache-level' properties are 'required'. Cf.
>> s3.8 Multi-level and Shared Cache Nodes
>> The 'cache-unified' property should be present if one of the
>> properties for unified cache is present ('cache-size', ...).
>>
>> Update the Device Trees accordingly.
>>
>> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Acked-by: Chanho Min <chanho.min@lge.com>
>> ---
>> arch/arm64/boot/dts/lg/lg1312.dtsi | 1 +
>> arch/arm64/boot/dts/lg/lg1313.dtsi | 1 +
>> 2 files changed, 2 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi
>> b/arch/arm64/boot/dts/lg/lg1312.dtsi
>> index 78ae73d0cf36..25ed9aeee2dc 100644
>> --- a/arch/arm64/boot/dts/lg/lg1312.dtsi
>> +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
>> @@ -48,6 +48,7 @@ cpu3: cpu@3 {
>> };
>> L2_0: l2-cache0 {
>> compatible = "cache";
>> + cache-level = <2>;
>> };
>> };
>> diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi
>> b/arch/arm64/boot/dts/lg/lg1313.dtsi
>> index 2173316573be..db82fd4cc759 100644
>> --- a/arch/arm64/boot/dts/lg/lg1313.dtsi
>> +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
>> @@ -48,6 +48,7 @@ cpu3: cpu@3 {
>> };
>> L2_0: l2-cache0 {Re: Re: [PATCH v2 10/23] arm64: dts: Update cache properties for lg
>> compatible = "cache";
>> + cache-leveRe: Re: [PATCH v2 10/23] arm64: dts: Update cache properties for lgl = <2>;
>> };
>> };
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: (subset) [PATCH v2 23/23] arm64: dts: Update cache properties for ti
2022-11-07 15:57 ` Pierre Gondois
@ 2023-01-17 13:41 ` Raghavendra, Vignesh
-1 siblings, 0 replies; 107+ messages in thread
From: Raghavendra, Vignesh @ 2023-01-17 13:41 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Tero Kristo, Viorel Suman,
Abel Vesa, Zhou Peng, Shenwei Wang, Peng Fan, Ming Qian,
Tim Harvey, Adam Ford, Lucas Stach, Li Jun, Richard Zhu,
Markus Niebel, Joakim Zhang, Marek Vasut, Laurent Pinchart,
Alexander Stein, Paul Elder, Martin Kepplinger, David Heidelberg,
Oliver Graute, Liu Ying, Wei Fang, Clark Wang, Jacky Bai,
Chris Packham, Vadym Kochan, Sameer Pujar, Mikko Perttunen,
Prathamesh Shete, Akhil R, Sumit Gupta, Diogo Ivo, Vidya Sagar,
Ashish Mhetre, Johan Jonker, Christopher Obbard, Ezequiel Garcia,
Aswani Reddy, Shashank Prashar, Arjun K V, devicetree,
linux-rpi-kernel, linux-arm-kernel, linux-amlogic,
linux-samsung-soc, linux-mediatek, openbmc, linux-tegra,
linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
Hi Pierre Gondois,
On 11/7/2022 9:27 PM, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
[...]
[23/23] arm64: dts: Update cache properties for ti
commit: 880932e657ffc677c1b053a947afa87ffed1b29d
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain
during the next merge window (or sooner if it is a relevant bug fix),
however if problems are discovered then the patch may be dropped or
reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh
[...]
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: (subset) [PATCH v2 23/23] arm64: dts: Update cache properties for ti
@ 2023-01-17 13:41 ` Raghavendra, Vignesh
0 siblings, 0 replies; 107+ messages in thread
From: Raghavendra, Vignesh @ 2023-01-17 13:41 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Steen Hegelund, Daniel Machon, UNGLinuxDriver,
Avi Fishman, Tomer Maimon, Tali Perry, Patrick Venture,
Nancy Yuen, Benjamin Fair, Thierry Reding, Jonathan Hunter,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven,
Magnus Damm, Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Tero Kristo, Viorel Suman,
Abel Vesa, Zhou Peng, Shenwei Wang, Peng Fan, Ming Qian,
Tim Harvey, Adam Ford, Lucas Stach, Li Jun, Richard Zhu,
Markus Niebel, Joakim Zhang, Marek Vasut, Laurent Pinchart,
Alexander Stein, Paul Elder, Martin Kepplinger, David Heidelberg,
Oliver Graute, Liu Ying, Wei Fang, Clark Wang, Jacky Bai,
Chris Packham, Vadym Kochan, Sameer Pujar, Mikko Perttunen,
Prathamesh Shete, Akhil R, Sumit Gupta, Diogo Ivo, Vidya Sagar,
Ashish Mhetre, Johan Jonker, Christopher Obbard, Ezequiel Garcia,
Aswani Reddy, Shashank Prashar, Arjun K V, devicetree,
linux-rpi-kernel, linux-arm-kernel, linux-amlogic,
linux-samsung-soc, linux-mediatek, openbmc, linux-tegra,
linux-arm-msm, linux-realtek-soc, linux-renesas-soc,
linux-rockchip
Hi Pierre Gondois,
On 11/7/2022 9:27 PM, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
[...]
[23/23] arm64: dts: Update cache properties for ti
commit: 880932e657ffc677c1b053a947afa87ffed1b29d
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain
during the next merge window (or sooner if it is a relevant bug fix),
however if problems are discovered then the patch may be dropped or
reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh
[...]
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 13/23] arm64: dts: Update cache properties for microchip
2022-11-07 15:57 ` Pierre Gondois
@ 2023-01-18 8:21 ` Steen Hegelund
-1 siblings, 0 replies; 107+ messages in thread
From: Steen Hegelund @ 2023-01-18 8:21 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Daniel Machon, UNGLinuxDriver, Avi Fishman,
Tomer Maimon, Tali Perry, Patrick Venture, Nancy Yuen,
Benjamin Fair, Thierry Reding, Jonathan Hunter, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven, Magnus Damm,
Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Peng Fan, Ming Qian, Shenwei Wang,
Adam Ford, Tim Harvey, Lucas Stach, Richard Zhu, Li Jun,
Markus Niebel, Joakim Zhang, Marek Vasut, Laurent Pinchart,
Alexander Stein, Paul Elder, Martin Kepplinger, David Heidelberg,
Joy Zou, Oliver Graute, Liu Ying, Zhou Peng, Shijie Qin,
Wei Fang, Jacky Bai, Clark Wang, Chris Packham, Vadym Kochan,
Sameer Pujar, Akhil R, Mikko Perttunen, Prathamesh Shete,
Sumit Gupta, Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Arnd Bergmann, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
Hi Pierre,
This looks good to me.
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
BR
Steen
On Mon, 2022-11-07 at 16:57 +0100, Pierre Gondois wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
> arch/arm64/boot/dts/microchip/sparx5.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> index 2dd5e38820b1..c4bca23b96b9 100644
> --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> @@ -52,6 +52,7 @@ cpu1: cpu@1 {
> };
> L2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 107+ messages in thread
* Re: [PATCH v2 13/23] arm64: dts: Update cache properties for microchip
@ 2023-01-18 8:21 ` Steen Hegelund
0 siblings, 0 replies; 107+ messages in thread
From: Steen Hegelund @ 2023-01-18 8:21 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
Tsahee Zidenberg, Antoine Tenart, Brijesh Singh,
Suravee Suthikulpanit, Tom Lendacky, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Khuong Dinh,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, William Zhang,
Anand Gore, Kursad Oney, Rafał Miłecki, Alim Akhtar,
Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Chester Lin, Andreas Färber,
Matthias Brugger, NXP S32 Linux Team, Wei Xu, Chanho Min,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Lars Povlsen, Daniel Machon, UNGLinuxDriver, Avi Fishman,
Tomer Maimon, Tali Perry, Patrick Venture, Nancy Yuen,
Benjamin Fair, Thierry Reding, Jonathan Hunter, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Geert Uytterhoeven, Magnus Damm,
Heiko Stuebner, Kunihiko Hayashi, Masami Hiramatsu,
Jisheng Zhang, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Viorel Suman, Abel Vesa, Peng Fan, Ming Qian, Shenwei Wang,
Adam Ford, Tim Harvey, Lucas Stach, Richard Zhu, Li Jun,
Markus Niebel, Joakim Zhang, Marek Vasut, Laurent Pinchart,
Alexander Stein, Paul Elder, Martin Kepplinger, David Heidelberg,
Joy Zou, Oliver Graute, Liu Ying, Zhou Peng, Shijie Qin,
Wei Fang, Jacky Bai, Clark Wang, Chris Packham, Vadym Kochan,
Sameer Pujar, Akhil R, Mikko Perttunen, Prathamesh Shete,
Sumit Gupta, Diogo Ivo, Vidya Sagar, Ashish Mhetre, Johan Jonker,
Christopher Obbard, Ezequiel Garcia, Aswani Reddy,
Shashank Prashar, Arnd Bergmann, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-amlogic, linux-samsung-soc,
linux-mediatek, openbmc, linux-tegra, linux-arm-msm,
linux-realtek-soc, linux-renesas-soc, linux-rockchip
Hi Pierre,
This looks good to me.
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
BR
Steen
On Mon, 2022-11-07 at 16:57 +0100, Pierre Gondois wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
> arch/arm64/boot/dts/microchip/sparx5.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> index 2dd5e38820b1..c4bca23b96b9 100644
> --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> @@ -52,6 +52,7 @@ cpu1: cpu@1 {
> };
> L2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> --
> 2.25.1
>
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 107+ messages in thread
end of thread, other threads:[~2023-02-01 16:04 UTC | newest]
Thread overview: 107+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-11-07 15:56 [PATCH v2 00/23] Update cache properties for arm64 DTS Pierre Gondois
2022-11-07 15:56 ` Pierre Gondois
2022-11-07 15:56 ` [PATCH v2 01/23] arm64: dts: Update cache properties for amazon Pierre Gondois
2022-11-07 15:56 ` Pierre Gondois
2023-01-12 8:34 ` Pierre Gondois
2023-01-12 8:34 ` Pierre Gondois
2022-11-07 15:56 ` [PATCH v2 02/23] arm64: dts: Update cache properties for amd Pierre Gondois
2022-11-07 15:56 ` Pierre Gondois
2023-01-12 8:34 ` Pierre Gondois
2023-01-12 15:31 ` Tom Lendacky
2023-01-12 15:31 ` Tom Lendacky
2022-11-07 15:56 ` [PATCH v2 03/23] arm64: dts: Update cache properties for amlogic Pierre Gondois
2022-11-07 15:56 ` Pierre Gondois
2022-11-07 15:56 ` [PATCH v2 04/23] arm64: dts: Update cache properties for apm Pierre Gondois
2022-11-07 15:56 ` Pierre Gondois
2023-01-12 8:33 ` Pierre Gondois
2022-11-07 15:56 ` [PATCH v2 05/23] arm64: dts: Update cache properties for arm Pierre Gondois
2022-11-07 15:56 ` Pierre Gondois
2022-11-11 15:56 ` Sudeep Holla
2022-11-07 15:56 ` [PATCH v2 06/23] arm64: dts: Update cache properties for broadcom Pierre Gondois
2022-11-07 15:56 ` Pierre Gondois
2022-11-07 17:31 ` Florian Fainelli
2022-11-07 17:58 ` Pierre Gondois
2022-11-16 18:22 ` Florian Fainelli
2022-11-17 9:39 ` Pierre Gondois
2022-11-07 15:57 ` [PATCH v2 07/23] arm64: dts: Update cache properties for exynos Pierre Gondois
2022-11-07 15:57 ` Pierre Gondois
2022-11-07 17:55 ` Krzysztof Kozlowski
2022-11-07 17:55 ` Krzysztof Kozlowski
2022-11-07 18:24 ` Pierre Gondois
2022-11-07 18:24 ` Pierre Gondois
2022-11-07 15:57 ` [PATCH v2 08/23] arm64: dts: Update cache properties for freescale Pierre Gondois
2022-11-07 15:57 ` Pierre Gondois
2022-11-14 11:41 ` Shawn Guo
2022-11-07 15:57 ` [PATCH v2 09/23] arm64: dts: Update cache properties for hisilicon Pierre Gondois
2022-11-07 15:57 ` Pierre Gondois
2022-11-16 2:17 ` Wei Xu
2022-11-07 15:57 ` [PATCH v2 10/23] arm64: dts: Update cache properties for lg Pierre Gondois
2022-11-07 15:57 ` Pierre Gondois
2023-01-12 8:34 ` Pierre Gondois
2023-01-12 8:34 ` Pierre Gondois
2023-01-13 1:12 ` Chanho Min
2023-01-13 1:12 ` Chanho Min
2022-11-07 15:57 ` [PATCH v2 11/23] arm64: dts: Update cache properties for marvell Pierre Gondois
2022-11-07 15:57 ` Pierre Gondois
2022-11-07 15:57 ` [PATCH v2 12/23] arm64: dts: Update cache properties for mediatek Pierre Gondois
2022-11-07 15:57 ` Pierre Gondois
2022-11-08 11:42 ` Matthias Brugger
2022-11-08 11:42 ` Matthias Brugger
2022-11-07 15:57 ` [PATCH v2 13/23] arm64: dts: Update cache properties for microchip Pierre Gondois
2022-11-07 15:57 ` Pierre Gondois
2023-01-12 8:33 ` Pierre Gondois
2023-01-12 8:33 ` Pierre Gondois
2023-01-18 8:21 ` Steen Hegelund
2023-01-18 8:21 ` Steen Hegelund
2022-11-07 15:57 ` [PATCH v2 14/23] arm64: dts: Update cache properties for nuvoton Pierre Gondois
2022-11-07 15:57 ` Pierre Gondois
2023-01-12 8:34 ` Pierre Gondois
2023-01-12 8:34 ` Pierre Gondois
2022-11-07 15:57 ` [PATCH v2 15/23] arm64: dts: Update cache properties for nvidia Pierre Gondois
2022-11-07 15:57 ` Pierre Gondois
2022-11-07 15:57 ` [PATCH v2 16/23] arm64: dts: Update cache properties for qcom Pierre Gondois
2022-11-07 15:57 ` Pierre Gondois
2022-12-29 12:47 ` Krzysztof Kozlowski
2022-12-29 12:47 ` Krzysztof Kozlowski
2022-12-29 17:23 ` (subset) " Bjorn Andersson
2022-12-29 17:23 ` Bjorn Andersson
2022-11-07 15:57 ` [PATCH v2 17/23] arm64: dts: Update cache properties for realtek Pierre Gondois
2022-11-07 15:57 ` Pierre Gondois
2023-01-12 8:33 ` Pierre Gondois
2023-01-12 8:33 ` Pierre Gondois
2023-01-12 8:51 ` Andreas Färber
2023-01-12 8:51 ` Andreas Färber
2022-11-07 15:57 ` [PATCH v2 18/23] arm64: dts: Update cache properties for renesas Pierre Gondois
2022-11-07 15:57 ` Pierre Gondois
2022-11-08 8:34 ` Geert Uytterhoeven
2022-11-07 15:57 ` [PATCH v2 19/23] arm64: dts: Update cache properties for rockchip Pierre Gondois
2022-11-07 15:57 ` Pierre Gondois
2022-11-07 15:57 ` [PATCH v2 20/23] arm64: dts: Update cache properties for socionext Pierre Gondois
2022-11-07 15:57 ` Pierre Gondois
2023-01-12 8:33 ` Pierre Gondois
2023-01-12 8:33 ` Pierre Gondois
2023-01-12 10:27 ` Kunihiko Hayashi
2023-01-12 10:27 ` Kunihiko Hayashi
2022-11-07 15:57 ` [PATCH v2 21/23] arm64: dts: Update cache properties for synaptics Pierre Gondois
2022-11-07 15:57 ` Pierre Gondois
2023-01-12 8:32 ` Pierre Gondois
2023-01-12 8:32 ` Pierre Gondois
2022-11-07 15:57 ` [PATCH v2 22/23] arm64: dts: Update cache properties for tesla Pierre Gondois
2022-11-07 15:57 ` Pierre Gondois
2022-11-07 17:56 ` Krzysztof Kozlowski
2022-11-07 18:23 ` Pierre Gondois
2022-11-07 18:23 ` Pierre Gondois
2022-11-07 15:57 ` [PATCH v2 23/23] arm64: dts: Update cache properties for ti Pierre Gondois
2022-11-07 15:57 ` Pierre Gondois
2023-01-17 13:41 ` (subset) " Raghavendra, Vignesh
2023-01-17 13:41 ` Raghavendra, Vignesh
2022-11-07 17:23 ` (subset) [PATCH v2 00/23] Update cache properties for arm64 DTS Neil Armstrong
2022-11-07 17:23 ` Neil Armstrong
2022-11-07 18:03 ` Krzysztof Kozlowski
2022-11-07 18:03 ` Krzysztof Kozlowski
2022-11-07 23:11 ` Rob Herring
2022-11-22 22:34 ` (subset) " Heiko Stuebner
2022-11-22 22:34 ` Heiko Stuebner
2022-11-22 22:34 ` Heiko Stuebner
2023-01-12 8:33 ` Pierre Gondois
2023-01-12 8:33 ` Pierre Gondois
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