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From: Ross Philipson <ross.philipson@oracle.com>
To: linux-kernel@vger.kernel.org, x86@kernel.org,
	linux-integrity@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-crypto@vger.kernel.org, iommu@lists.linux-foundation.org,
	kexec@lists.infradead.org, linux-efi@vger.kernel.org
Cc: ross.philipson@oracle.com, dpsmith@apertussolutions.com,
	tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
	hpa@zytor.com, ardb@kernel.org, mjg59@srcf.ucam.org,
	James.Bottomley@hansenpartnership.com, luto@amacapital.net,
	nivedita@alum.mit.edu, kanth.ghatraju@oracle.com,
	trenchboot-devel@googlegroups.com
Subject: [PATCH v6 04/14] x86: Secure Launch Resource Table header file
Date: Thu,  4 May 2023 14:50:13 +0000	[thread overview]
Message-ID: <20230504145023.835096-5-ross.philipson@oracle.com> (raw)
In-Reply-To: <20230504145023.835096-1-ross.philipson@oracle.com>

Introduce the Secure Launch Resource Table which forms the formal
interface between the pre and post launch code.

Signed-off-by: Ross Philipson <ross.philipson@oracle.com>
---
 include/linux/slr_table.h | 270 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 270 insertions(+)
 create mode 100644 include/linux/slr_table.h

diff --git a/include/linux/slr_table.h b/include/linux/slr_table.h
new file mode 100644
index 0000000..d4b76e5
--- /dev/null
+++ b/include/linux/slr_table.h
@@ -0,0 +1,270 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Secure Launch Resource Table
+ *
+ * Copyright (c) 2023, Oracle and/or its affiliates.
+ */
+
+#ifndef _LINUX_SLR_TABLE_H
+#define _LINUX_SLR_TABLE_H
+
+/* Put this in efi.h if it becomes a standard */
+#define SLR_TABLE_GUID				EFI_GUID(0x877a9b2a, 0x0385, 0x45d1, 0xa0, 0x34, 0x9d, 0xac, 0x9c, 0x9e, 0x56, 0x5f)
+
+/* SLR table header values */
+#define SLR_TABLE_MAGIC		0x4452544d
+#define SLR_TABLE_REVISION	1
+
+/* Current revisions for the policy and UEFI config */
+#define SLR_POLICY_REVISION		1
+#define SLR_UEFI_CONFIG_REVISION	1
+
+/* SLR defined architectures */
+#define SLR_INTEL_TXT		1
+#define SLR_AMD_SKINIT		2
+
+/* SLR defined bootloaders */
+#define SLR_BOOTLOADER_INVALID	0
+#define SLR_BOOTLOADER_GRUB	1
+
+/* Log formats */
+#define SLR_DRTM_TPM12_LOG	1
+#define SLR_DRTM_TPM20_LOG	2
+
+/* DRTM Policy Entry Flags */
+#define SLR_POLICY_FLAG_MEASURED	0x1
+#define SLR_POLICY_IMPLICIT_SIZE	0x2
+
+/* Array Lengths */
+#define TPM_EVENT_INFO_LENGTH		32
+#define TXT_VARIABLE_MTRRS_LENGTH	32
+
+/* Tags */
+#define SLR_ENTRY_INVALID	0x0000
+#define SLR_ENTRY_DL_INFO	0x0001
+#define SLR_ENTRY_LOG_INFO	0x0002
+#define SLR_ENTRY_ENTRY_POLICY	0x0003
+#define SLR_ENTRY_INTEL_INFO	0x0004
+#define SLR_ENTRY_AMD_INFO	0x0005
+#define SLR_ENTRY_ARM_INFO	0x0006
+#define SLR_ENTRY_UEFI_INFO	0x0007
+#define SLR_ENTRY_UEFI_CONFIG	0x0008
+#define SLR_ENTRY_END		0xffff
+
+/* Entity Types */
+#define SLR_ET_UNSPECIFIED	0x0000
+#define SLR_ET_SLRT		0x0001
+#define SLR_ET_BOOT_PARAMS	0x0002
+#define SLR_ET_SETUP_DATA	0x0003
+#define SLR_ET_CMDLINE		0x0004
+#define SLR_ET_UEFI_MEMMAP	0x0005
+#define SLR_ET_RAMDISK		0x0006
+#define SLR_ET_TXT_OS2MLE	0x0010
+#define SLR_ET_UNUSED		0xffff
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Primary SLR Table Header
+ */
+struct slr_table {
+	u32 magic;
+	u16 revision;
+	u16 architecture;
+	u32 size;
+	u32 max_size;
+	/* entries[] */
+} __packed;
+
+/*
+ * Common SLRT Table Header
+ */
+struct slr_entry_hdr {
+	u16 tag;
+	u16 size;
+} __packed;
+
+/*
+ * Boot loader context
+ */
+struct slr_bl_context {
+	u16 bootloader;
+	u16 reserved;
+	u64 context;
+} __packed;
+
+/*
+ * DRTM Dynamic Launch Configuration
+ */
+struct slr_entry_dl_info {
+	struct slr_entry_hdr hdr;
+	struct slr_bl_context bl_context;
+	u64 dl_handler;
+	u64 dce_base;
+	u32 dce_size;
+	u64 dlme_entry;
+} __packed;
+
+/*
+ * TPM Log Information
+ */
+struct slr_entry_log_info {
+	struct slr_entry_hdr hdr;
+	u16 format;
+	u16 reserved;
+	u64 addr;
+	u32 size;
+} __packed;
+
+/*
+ * DRTM Measurement Policy
+ */
+struct slr_entry_policy {
+	struct slr_entry_hdr hdr;
+	u16 revision;
+	u16 nr_entries;
+	/* policy_entries[] */
+} __packed;
+
+/*
+ * DRTM Measurement Entry
+ */
+struct slr_policy_entry {
+	u16 pcr;
+	u16 entity_type;
+	u16 flags;
+	u16 reserved;
+	u64 entity;
+	u64 size;
+	char evt_info[TPM_EVENT_INFO_LENGTH];
+} __packed;
+
+/*
+ * Secure Launch defined MTRR saving structures
+ */
+struct slr_txt_mtrr_pair {
+	u64 mtrr_physbase;
+	u64 mtrr_physmask;
+} __packed;
+
+struct slr_txt_mtrr_state {
+	u64 default_mem_type;
+	u64 mtrr_vcnt;
+	struct slr_txt_mtrr_pair mtrr_pair[TXT_VARIABLE_MTRRS_LENGTH];
+} __packed;
+
+/*
+ * Intel TXT Info table
+ */
+struct slr_entry_intel_info {
+	struct slr_entry_hdr hdr;
+	u64 saved_misc_enable_msr;
+	struct slr_txt_mtrr_state saved_bsp_mtrrs;
+} __packed;
+
+/*
+ * AMD SKINIT Info table
+ */
+struct slr_entry_amd_info {
+	struct slr_entry_hdr hdr;
+} __packed;
+
+/*
+ * ARM DRTM Info table
+ */
+struct slr_entry_arm_info {
+	struct slr_entry_hdr hdr;
+} __packed;
+
+struct slr_entry_uefi_config {
+	struct slr_entry_hdr hdr;
+	u16 revision;
+	u16 nr_entries;
+	/* uefi_cfg_entries[] */
+} __packed;
+
+struct slr_uefi_cfg_entry {
+	u16 pcr;
+	u16 reserved;
+	u64 cfg; /* address or value */
+	u32 size;
+	char evt_info[TPM_EVENT_INFO_LENGTH];
+} __packed;
+
+static inline void *slr_end_of_entrys(struct slr_table *table)
+{
+	return (((void *)table) + table->size);
+}
+
+static inline struct slr_entry_hdr *
+slr_next_entry(struct slr_table *table,
+		struct slr_entry_hdr *curr)
+{
+	struct slr_entry_hdr *next = (struct slr_entry_hdr *)
+				((u8 *)curr + curr->size);
+
+	if ((void *)next >= slr_end_of_entrys(table))
+		return NULL;
+	if (next->tag == SLR_ENTRY_END)
+		return NULL;
+
+	return next;
+}
+
+static inline struct slr_entry_hdr *
+slr_next_entry_by_tag(struct slr_table *table,
+		      struct slr_entry_hdr *entry,
+		      u16 tag)
+{
+	if (!entry) /* Start from the beginning */
+		entry = (struct slr_entry_hdr *)(((u8 *)table) + sizeof(*table));
+
+	for ( ; ; ) {
+		if (entry->tag == tag)
+			return entry;
+
+		entry = slr_next_entry(table, entry);
+		if (!entry)
+			return NULL;
+	}
+
+	return NULL;
+}
+
+static inline int
+slr_add_entry(struct slr_table *table,
+	      struct slr_entry_hdr *entry)
+{
+	struct slr_entry_hdr *end;
+
+	if ((table->size + entry->size) > table->max_size)
+		return -1;
+
+	memcpy((u8 *)table + table->size - sizeof(*end), entry, entry->size);
+	table->size += entry->size;
+
+	end  = (struct slr_entry_hdr *)((u8 *)table + table->size - sizeof(*end));
+	end->tag = SLR_ENTRY_END;
+	end->size = sizeof(*end);
+
+	return 0;
+}
+
+static inline void
+slr_init_table(struct slr_table *slrt, u16 architecture, u32 max_size)
+{
+	struct slr_entry_hdr *end;
+
+	slrt->magic = SLR_TABLE_MAGIC;
+	slrt->revision = SLR_TABLE_REVISION;
+	slrt->architecture = architecture;
+	slrt->size = sizeof(*slrt) + sizeof(*end);
+	slrt->max_size = max_size;
+	end = (struct slr_entry_hdr *)((u8 *)slrt + sizeof(*slrt));
+	end->tag = SLR_ENTRY_END;
+	end->size = sizeof(*end);
+}
+
+#endif /* !__ASSEMBLY */
+
+#endif /* _LINUX_SLR_TABLE_H */
-- 
1.8.3.1


WARNING: multiple messages have this Message-ID (diff)
From: Ross Philipson <ross.philipson@oracle.com>
To: linux-kernel@vger.kernel.org, x86@kernel.org,
	linux-integrity@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-crypto@vger.kernel.org, iommu@lists.linux-foundation.org,
	kexec@lists.infradead.org, linux-efi@vger.kernel.org
Cc: ross.philipson@oracle.com, dpsmith@apertussolutions.com,
	tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
	hpa@zytor.com, ardb@kernel.org, mjg59@srcf.ucam.org,
	James.Bottomley@hansenpartnership.com, luto@amacapital.net,
	nivedita@alum.mit.edu, kanth.ghatraju@oracle.com,
	trenchboot-devel@googlegroups.com
Subject: [PATCH v6 04/14] x86: Secure Launch Resource Table header file
Date: Thu,  4 May 2023 14:50:13 +0000	[thread overview]
Message-ID: <20230504145023.835096-5-ross.philipson@oracle.com> (raw)
In-Reply-To: <20230504145023.835096-1-ross.philipson@oracle.com>

Introduce the Secure Launch Resource Table which forms the formal
interface between the pre and post launch code.

Signed-off-by: Ross Philipson <ross.philipson@oracle.com>
---
 include/linux/slr_table.h | 270 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 270 insertions(+)
 create mode 100644 include/linux/slr_table.h

diff --git a/include/linux/slr_table.h b/include/linux/slr_table.h
new file mode 100644
index 0000000..d4b76e5
--- /dev/null
+++ b/include/linux/slr_table.h
@@ -0,0 +1,270 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Secure Launch Resource Table
+ *
+ * Copyright (c) 2023, Oracle and/or its affiliates.
+ */
+
+#ifndef _LINUX_SLR_TABLE_H
+#define _LINUX_SLR_TABLE_H
+
+/* Put this in efi.h if it becomes a standard */
+#define SLR_TABLE_GUID				EFI_GUID(0x877a9b2a, 0x0385, 0x45d1, 0xa0, 0x34, 0x9d, 0xac, 0x9c, 0x9e, 0x56, 0x5f)
+
+/* SLR table header values */
+#define SLR_TABLE_MAGIC		0x4452544d
+#define SLR_TABLE_REVISION	1
+
+/* Current revisions for the policy and UEFI config */
+#define SLR_POLICY_REVISION		1
+#define SLR_UEFI_CONFIG_REVISION	1
+
+/* SLR defined architectures */
+#define SLR_INTEL_TXT		1
+#define SLR_AMD_SKINIT		2
+
+/* SLR defined bootloaders */
+#define SLR_BOOTLOADER_INVALID	0
+#define SLR_BOOTLOADER_GRUB	1
+
+/* Log formats */
+#define SLR_DRTM_TPM12_LOG	1
+#define SLR_DRTM_TPM20_LOG	2
+
+/* DRTM Policy Entry Flags */
+#define SLR_POLICY_FLAG_MEASURED	0x1
+#define SLR_POLICY_IMPLICIT_SIZE	0x2
+
+/* Array Lengths */
+#define TPM_EVENT_INFO_LENGTH		32
+#define TXT_VARIABLE_MTRRS_LENGTH	32
+
+/* Tags */
+#define SLR_ENTRY_INVALID	0x0000
+#define SLR_ENTRY_DL_INFO	0x0001
+#define SLR_ENTRY_LOG_INFO	0x0002
+#define SLR_ENTRY_ENTRY_POLICY	0x0003
+#define SLR_ENTRY_INTEL_INFO	0x0004
+#define SLR_ENTRY_AMD_INFO	0x0005
+#define SLR_ENTRY_ARM_INFO	0x0006
+#define SLR_ENTRY_UEFI_INFO	0x0007
+#define SLR_ENTRY_UEFI_CONFIG	0x0008
+#define SLR_ENTRY_END		0xffff
+
+/* Entity Types */
+#define SLR_ET_UNSPECIFIED	0x0000
+#define SLR_ET_SLRT		0x0001
+#define SLR_ET_BOOT_PARAMS	0x0002
+#define SLR_ET_SETUP_DATA	0x0003
+#define SLR_ET_CMDLINE		0x0004
+#define SLR_ET_UEFI_MEMMAP	0x0005
+#define SLR_ET_RAMDISK		0x0006
+#define SLR_ET_TXT_OS2MLE	0x0010
+#define SLR_ET_UNUSED		0xffff
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Primary SLR Table Header
+ */
+struct slr_table {
+	u32 magic;
+	u16 revision;
+	u16 architecture;
+	u32 size;
+	u32 max_size;
+	/* entries[] */
+} __packed;
+
+/*
+ * Common SLRT Table Header
+ */
+struct slr_entry_hdr {
+	u16 tag;
+	u16 size;
+} __packed;
+
+/*
+ * Boot loader context
+ */
+struct slr_bl_context {
+	u16 bootloader;
+	u16 reserved;
+	u64 context;
+} __packed;
+
+/*
+ * DRTM Dynamic Launch Configuration
+ */
+struct slr_entry_dl_info {
+	struct slr_entry_hdr hdr;
+	struct slr_bl_context bl_context;
+	u64 dl_handler;
+	u64 dce_base;
+	u32 dce_size;
+	u64 dlme_entry;
+} __packed;
+
+/*
+ * TPM Log Information
+ */
+struct slr_entry_log_info {
+	struct slr_entry_hdr hdr;
+	u16 format;
+	u16 reserved;
+	u64 addr;
+	u32 size;
+} __packed;
+
+/*
+ * DRTM Measurement Policy
+ */
+struct slr_entry_policy {
+	struct slr_entry_hdr hdr;
+	u16 revision;
+	u16 nr_entries;
+	/* policy_entries[] */
+} __packed;
+
+/*
+ * DRTM Measurement Entry
+ */
+struct slr_policy_entry {
+	u16 pcr;
+	u16 entity_type;
+	u16 flags;
+	u16 reserved;
+	u64 entity;
+	u64 size;
+	char evt_info[TPM_EVENT_INFO_LENGTH];
+} __packed;
+
+/*
+ * Secure Launch defined MTRR saving structures
+ */
+struct slr_txt_mtrr_pair {
+	u64 mtrr_physbase;
+	u64 mtrr_physmask;
+} __packed;
+
+struct slr_txt_mtrr_state {
+	u64 default_mem_type;
+	u64 mtrr_vcnt;
+	struct slr_txt_mtrr_pair mtrr_pair[TXT_VARIABLE_MTRRS_LENGTH];
+} __packed;
+
+/*
+ * Intel TXT Info table
+ */
+struct slr_entry_intel_info {
+	struct slr_entry_hdr hdr;
+	u64 saved_misc_enable_msr;
+	struct slr_txt_mtrr_state saved_bsp_mtrrs;
+} __packed;
+
+/*
+ * AMD SKINIT Info table
+ */
+struct slr_entry_amd_info {
+	struct slr_entry_hdr hdr;
+} __packed;
+
+/*
+ * ARM DRTM Info table
+ */
+struct slr_entry_arm_info {
+	struct slr_entry_hdr hdr;
+} __packed;
+
+struct slr_entry_uefi_config {
+	struct slr_entry_hdr hdr;
+	u16 revision;
+	u16 nr_entries;
+	/* uefi_cfg_entries[] */
+} __packed;
+
+struct slr_uefi_cfg_entry {
+	u16 pcr;
+	u16 reserved;
+	u64 cfg; /* address or value */
+	u32 size;
+	char evt_info[TPM_EVENT_INFO_LENGTH];
+} __packed;
+
+static inline void *slr_end_of_entrys(struct slr_table *table)
+{
+	return (((void *)table) + table->size);
+}
+
+static inline struct slr_entry_hdr *
+slr_next_entry(struct slr_table *table,
+		struct slr_entry_hdr *curr)
+{
+	struct slr_entry_hdr *next = (struct slr_entry_hdr *)
+				((u8 *)curr + curr->size);
+
+	if ((void *)next >= slr_end_of_entrys(table))
+		return NULL;
+	if (next->tag == SLR_ENTRY_END)
+		return NULL;
+
+	return next;
+}
+
+static inline struct slr_entry_hdr *
+slr_next_entry_by_tag(struct slr_table *table,
+		      struct slr_entry_hdr *entry,
+		      u16 tag)
+{
+	if (!entry) /* Start from the beginning */
+		entry = (struct slr_entry_hdr *)(((u8 *)table) + sizeof(*table));
+
+	for ( ; ; ) {
+		if (entry->tag == tag)
+			return entry;
+
+		entry = slr_next_entry(table, entry);
+		if (!entry)
+			return NULL;
+	}
+
+	return NULL;
+}
+
+static inline int
+slr_add_entry(struct slr_table *table,
+	      struct slr_entry_hdr *entry)
+{
+	struct slr_entry_hdr *end;
+
+	if ((table->size + entry->size) > table->max_size)
+		return -1;
+
+	memcpy((u8 *)table + table->size - sizeof(*end), entry, entry->size);
+	table->size += entry->size;
+
+	end  = (struct slr_entry_hdr *)((u8 *)table + table->size - sizeof(*end));
+	end->tag = SLR_ENTRY_END;
+	end->size = sizeof(*end);
+
+	return 0;
+}
+
+static inline void
+slr_init_table(struct slr_table *slrt, u16 architecture, u32 max_size)
+{
+	struct slr_entry_hdr *end;
+
+	slrt->magic = SLR_TABLE_MAGIC;
+	slrt->revision = SLR_TABLE_REVISION;
+	slrt->architecture = architecture;
+	slrt->size = sizeof(*slrt) + sizeof(*end);
+	slrt->max_size = max_size;
+	end = (struct slr_entry_hdr *)((u8 *)slrt + sizeof(*slrt));
+	end->tag = SLR_ENTRY_END;
+	end->size = sizeof(*end);
+}
+
+#endif /* !__ASSEMBLY */
+
+#endif /* _LINUX_SLR_TABLE_H */
-- 
1.8.3.1


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  parent reply	other threads:[~2023-05-04 14:51 UTC|newest]

Thread overview: 200+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-04 14:50 [PATCH v6 00/14] x86: Trenchboot secure dynamic launch Linux kernel support Ross Philipson
2023-05-04 14:50 ` Ross Philipson
2023-05-04 14:50 ` [PATCH v6 01/14] x86/boot: Place kernel_info at a fixed offset Ross Philipson
2023-05-04 14:50   ` Ross Philipson
2023-05-04 14:50 ` [PATCH v6 02/14] Documentation/x86: Secure Launch kernel documentation Ross Philipson
2023-05-04 14:50   ` Ross Philipson
2023-05-05 16:19   ` Simon Horman
2023-05-05 16:19     ` Simon Horman
2023-05-05 17:32     ` Ross Philipson
2023-05-05 17:32       ` Ross Philipson
2023-05-06  8:48   ` Bagas Sanjaya
2023-05-06  8:48     ` Bagas Sanjaya
2023-05-10 15:41     ` Ross Philipson
2023-05-10 15:41       ` Ross Philipson
2023-05-12 10:47   ` Matthew Garrett
2023-05-12 10:47     ` Matthew Garrett
2023-06-16 16:44     ` Daniel P. Smith
2023-06-16 16:44       ` Daniel P. Smith
2023-06-16 16:54       ` Matthew Garrett
2023-06-16 16:54         ` Matthew Garrett
2023-06-16 18:21         ` Daniel P. Smith
2023-06-16 18:21           ` Daniel P. Smith
2023-05-12 13:19   ` Thomas Gleixner
2023-05-12 13:19     ` Thomas Gleixner
2023-05-04 14:50 ` [PATCH v6 03/14] x86: Secure Launch Kconfig Ross Philipson
2023-05-04 14:50   ` Ross Philipson
2023-05-04 14:50 ` Ross Philipson [this message]
2023-05-04 14:50   ` [PATCH v6 04/14] x86: Secure Launch Resource Table header file Ross Philipson
2023-05-05 16:22   ` Simon Horman
2023-05-05 16:22     ` Simon Horman
2023-05-05 17:34     ` Ross Philipson
2023-05-05 17:34       ` Ross Philipson
2023-05-10 23:04   ` Jarkko Sakkinen
2023-05-10 23:04     ` Jarkko Sakkinen
2023-05-15 20:58     ` Daniel P. Smith
2023-05-15 20:58       ` Daniel P. Smith
2023-05-12 10:55   ` Matthew Garrett
2023-05-12 10:55     ` Matthew Garrett
2023-05-15 21:15     ` Daniel P. Smith
2023-05-15 21:15       ` Daniel P. Smith
2023-05-15 21:22       ` Matthew Garrett
2023-05-15 21:22         ` Matthew Garrett
2023-05-16  0:41         ` Daniel P. Smith
2023-05-16  0:41           ` Daniel P. Smith
2023-05-16  1:43           ` Matthew Garrett
2023-05-16  1:43             ` Matthew Garrett
2023-06-16 20:01             ` Daniel P. Smith
2023-06-16 20:01               ` Daniel P. Smith
2023-06-16 20:15               ` Matthew Garrett
2023-06-16 20:15                 ` Matthew Garrett
2023-07-07 19:31                 ` Daniel P. Smith
2023-07-07 19:31                   ` Daniel P. Smith
2023-05-04 14:50 ` [PATCH v6 05/14] x86: Secure Launch main " Ross Philipson
2023-05-04 14:50   ` Ross Philipson
2023-05-05 16:25   ` Simon Horman
2023-05-05 16:25     ` Simon Horman
2023-05-05 17:37     ` Ross Philipson
2023-05-05 17:37       ` Ross Philipson
2023-05-12 11:00   ` Matthew Garrett
2023-05-12 11:00     ` Matthew Garrett
2023-05-12 16:10     ` Ross Philipson
2023-05-12 16:10       ` Ross Philipson
2023-10-31 21:37       ` ross.philipson
2023-10-31 21:37         ` ross.philipson
2023-05-04 14:50 ` [PATCH v6 06/14] x86: Add early SHA support for Secure Launch early measurements Ross Philipson
2023-05-04 14:50   ` Ross Philipson
2023-05-05 16:34   ` Simon Horman
2023-05-05 16:34     ` Simon Horman
2023-05-09 16:09     ` Daniel P. Smith
2023-05-09 16:09       ` Daniel P. Smith
2023-05-10  1:21   ` Eric Biggers
2023-05-10  1:21     ` Eric Biggers
2023-05-10 22:28     ` Jarkko Sakkinen
2023-05-10 22:28       ` Jarkko Sakkinen
2023-05-12 11:04     ` Matthew Garrett
2023-05-12 11:04       ` Matthew Garrett
2023-05-12 11:18       ` Ard Biesheuvel
2023-05-12 11:18         ` Ard Biesheuvel
2023-05-12 11:28         ` Matthew Garrett
2023-05-12 11:28           ` Matthew Garrett
2023-05-12 11:58           ` Ard Biesheuvel
2023-05-12 11:58             ` Ard Biesheuvel
2023-05-12 12:24             ` Andrew Cooper
2023-05-12 12:24               ` Andrew Cooper
2023-05-14 18:18               ` Eric Biggers
2023-05-14 18:18                 ` Eric Biggers
2023-05-14 19:11                 ` Matthew Garrett
2023-05-14 19:11                   ` Matthew Garrett
2023-05-12 13:24           ` Thomas Gleixner
2023-05-12 13:24             ` Thomas Gleixner
2023-05-12 16:13             ` Matthew Garrett
2023-05-12 16:13               ` Matthew Garrett
2023-05-12 18:17               ` Thomas Gleixner
2023-05-12 18:17                 ` Thomas Gleixner
2023-05-12 19:12                 ` Matthew Garrett
2023-05-12 19:12                   ` Matthew Garrett
2023-05-12 19:42                   ` Andrew Cooper
2023-05-12 19:42                     ` Andrew Cooper
2023-05-15 21:23     ` Daniel P. Smith
2023-05-15 21:23       ` Daniel P. Smith
2023-05-11  3:33   ` Herbert Xu
2023-05-11  3:33     ` Herbert Xu
2023-05-16  0:50     ` Daniel P. Smith
2023-05-16  0:50       ` Daniel P. Smith
2023-05-04 14:50 ` [PATCH v6 07/14] x86: Secure Launch kernel early boot stub Ross Philipson
2023-05-04 14:50   ` Ross Philipson
2023-05-05 17:47   ` Simon Horman
2023-05-05 17:47     ` Simon Horman
2023-05-05 18:58     ` Ross Philipson
2023-05-05 18:58       ` Ross Philipson
2023-05-05 19:46       ` Simon Horman
2023-05-05 19:46         ` Simon Horman
2023-05-12 11:26   ` Matthew Garrett
2023-05-12 11:26     ` Matthew Garrett
2023-05-12 16:17     ` Ross Philipson
2023-05-12 16:17       ` Ross Philipson
2023-05-12 16:27       ` Matthew Garrett
2023-05-12 16:27         ` Matthew Garrett
2023-05-16  1:11       ` Daniel P. Smith
2023-05-16  1:11         ` Daniel P. Smith
2023-05-16  1:45         ` Matthew Garrett
2023-05-16  1:45           ` Matthew Garrett
2023-06-15 18:00           ` Ross Philipson
2023-06-15 18:00             ` Ross Philipson
2023-05-12 18:04   ` Thomas Gleixner
2023-05-12 18:04     ` Thomas Gleixner
2023-05-15 20:13     ` Ross Philipson
2023-05-15 20:13       ` Ross Philipson
2023-09-20 21:40     ` ross.philipson
2023-09-20 21:40       ` ross.philipson
2023-05-04 14:50 ` [PATCH v6 08/14] x86: Secure Launch kernel late " Ross Philipson
2023-05-04 14:50   ` Ross Philipson
2023-05-05 17:52   ` Simon Horman
2023-05-05 17:52     ` Simon Horman
2023-05-05 18:59     ` Ross Philipson
2023-05-05 18:59       ` Ross Philipson
2023-05-10 23:02   ` Jarkko Sakkinen
2023-05-10 23:02     ` Jarkko Sakkinen
2023-05-12 15:58     ` Ross Philipson
2023-05-12 15:58       ` Ross Philipson
2023-05-24  2:55       ` Jarkko Sakkinen
2023-05-24  2:55         ` Jarkko Sakkinen
2023-05-12 15:44   ` Thomas Gleixner
2023-05-12 15:44     ` Thomas Gleixner
2023-05-15 20:06     ` Ross Philipson
2023-05-15 20:06       ` Ross Philipson
2023-05-04 14:50 ` [PATCH v6 09/14] x86: Secure Launch SMP bringup support Ross Philipson
2023-05-04 14:50   ` Ross Philipson
2023-05-05 17:54   ` Simon Horman
2023-05-05 17:54     ` Simon Horman
2023-05-05 18:59     ` Ross Philipson
2023-05-05 18:59       ` Ross Philipson
2023-05-10 22:55   ` Jarkko Sakkinen
2023-05-10 22:55     ` Jarkko Sakkinen
2023-05-11 16:21     ` Ross Philipson
2023-05-11 16:21       ` Ross Philipson
2023-05-12 18:02   ` Thomas Gleixner
2023-05-12 18:02     ` Thomas Gleixner
2023-05-15 20:19     ` Ross Philipson
2023-05-15 20:19       ` Ross Philipson
2023-05-04 14:50 ` [PATCH v6 10/14] kexec: Secure Launch kexec SEXIT support Ross Philipson
2023-05-04 14:50   ` Ross Philipson
2023-05-04 14:50 ` [PATCH v6 11/14] reboot: Secure Launch SEXIT support on reboot paths Ross Philipson
2023-05-04 14:50   ` Ross Philipson
2023-05-12 11:40   ` Matthew Garrett
2023-05-12 11:40     ` Matthew Garrett
2023-05-15 18:16     ` Ross Philipson
2023-05-15 18:16       ` Ross Philipson
2023-05-16  1:23       ` Daniel P. Smith
2023-05-16  1:23         ` Daniel P. Smith
2023-05-04 14:50 ` [PATCH v6 12/14] x86: Secure Launch late initcall platform module Ross Philipson
2023-05-04 14:50   ` Ross Philipson
2023-05-05 19:42   ` Simon Horman
2023-05-05 19:42     ` Simon Horman
2023-05-08 15:07     ` Ross Philipson
2023-05-08 15:07       ` Ross Philipson
2023-05-10 22:39   ` Jarkko Sakkinen
2023-05-10 22:39     ` Jarkko Sakkinen
2023-05-12 15:53     ` Ross Philipson
2023-05-12 15:53       ` Ross Philipson
2023-05-10 22:40   ` Jarkko Sakkinen
2023-05-10 22:40     ` Jarkko Sakkinen
2023-05-12 15:54     ` Ross Philipson
2023-05-12 15:54       ` Ross Philipson
2023-05-04 14:50 ` [PATCH v6 13/14] tpm: Allow locality 2 to be set when initializing the TPM for Secure Launch Ross Philipson
2023-05-04 14:50   ` Ross Philipson
2023-05-12 11:43   ` Matthew Garrett
2023-05-12 11:43     ` Matthew Garrett
2023-05-12 16:22     ` Ross Philipson
2023-05-12 16:22       ` Ross Philipson
2023-05-16  1:37       ` Daniel P. Smith
2023-05-16  1:37         ` Daniel P. Smith
2023-05-04 14:50 ` [PATCH v6 14/14] x86: EFI stub DRTM launch support " Ross Philipson
2023-05-04 14:50   ` Ross Philipson
2023-05-05  8:39 ` [PATCH v6 00/14] x86: Trenchboot secure dynamic launch Linux kernel support Bagas Sanjaya
2023-05-05  8:39   ` Bagas Sanjaya
2023-05-05 15:45   ` Ross Philipson
2023-05-05 15:45     ` Ross Philipson
2023-05-06  7:56     ` Bagas Sanjaya
2023-05-06  7:56       ` Bagas Sanjaya

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