[U-Boot] [PATCH 1/3] Revert "ARM: imx6: Disable DDR DRAM calibration DHCOM i.MX6 PDK"

[U-Boot] [PATCH 1/3] Revert "ARM: imx6: Disable DDR DRAM calibration DHCOM i.MX6 PDK"

[lzenz at dh-electronics.de]

From: Ludwig Zenz <lzenz@dh-electronics.de>

This reverts commit a637fe6f27fd4c19ef9f43a5f871c244581422ac.

The DDR DRAM calibration was enhanced by write leveling correction code.
It can be used with T-topology now.

Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
---
 board/dhelectronics/dh_imx6/dh_imx6_spl.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
index dffe4eb..beda389 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
@@ -384,6 +384,10 @@ void board_init_f(ulong dummy)
 				  &dhcom6sdl_grp_ioregs);
 	mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr);
 
+	/* Perform DDR DRAM calibration */
+	udelay(100);
+	mmdc_do_dqs_calibration(&dhcom_ddr_info);
+
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
-- 
2.7.4

[U-Boot] [PATCH 2/3] ARM: imx6: configure ddrcode pins in spl DHCOM i.MX6 PDK

[lzenz at dh-electronics.de]

From: Ludwig Zenz <lzenz@dh-electronics.de>

Preperation for conditional DDR3 initialization based on GPIO codes.

Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
---
 board/dhelectronics/dh_imx6/dh_imx6_spl.c | 40 +++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
index beda389..eafb86d 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
@@ -208,6 +208,45 @@ static void setup_iomux_boardid(void)
 	SETUP_IOMUX_PADS(hwcode_pads);
 }
 
+/* DDR Code */
+static iomux_v3_cfg_t const ddrcode_pads[] = {
+	IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+};
+
+static void setup_iomux_ddrcode(void)
+{
+	/* ddr code pins */
+	SETUP_IOMUX_PADS(ddrcode_pads);
+}
+
+enum dhcom_ddr3_code {
+	DH_DDR3_SIZE_256MIB = 0x00,
+	DH_DDR3_SIZE_512MIB = 0x01,
+	DH_DDR3_SIZE_1GIB   = 0x02,
+	DH_DDR3_SIZE_2GIB   = 0x03
+};
+
+#define DDR3_CODE_BIT_0   IMX_GPIO_NR(2, 22)
+#define DDR3_CODE_BIT_1   IMX_GPIO_NR(2, 21)
+
+enum dhcom_ddr3_code dhcom_get_ddr3_code(void)
+{
+	enum dhcom_ddr3_code ddr3_code;
+
+	gpio_request(DDR3_CODE_BIT_0, "DDR3_CODE_BIT_0");
+	gpio_request(DDR3_CODE_BIT_1, "DDR3_CODE_BIT_1");
+
+	gpio_direction_input(DDR3_CODE_BIT_0);
+	gpio_direction_input(DDR3_CODE_BIT_1);
+
+	/* 256MB = 0b00; 512MB = 0b01; 1GB = 0b10; 2GB = 0b11 */
+	ddr3_code = (!!gpio_get_value(DDR3_CODE_BIT_1) << 1)
+	     | (!!gpio_get_value(DDR3_CODE_BIT_0));
+
+	return ddr3_code;
+}
+
 /* GPIO */
 static iomux_v3_cfg_t const gpio_pads[] = {
 	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
@@ -365,6 +404,7 @@ void board_init_f(ulong dummy)
 	timer_init();
 
 	setup_iomux_boardid();
+	setup_iomux_ddrcode();
 	setup_iomux_gpio();
 	setup_iomux_enet();
 	setup_iomux_sd();
-- 
2.7.4

[U-Boot] [PATCH 2/3] ARM: imx6: configure ddrcode pins in spl DHCOM i.MX6 PDK

[Stefano Babic]

On 05/07/2018 09:23, lzenz at dh-electronics.de wrote:
> From: Ludwig Zenz <lzenz@dh-electronics.de>
> 
> Preperation for conditional DDR3 initialization based on GPIO codes.
> 
> Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
> ---
>  board/dhelectronics/dh_imx6/dh_imx6_spl.c | 40 +++++++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
> 
> diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> index beda389..eafb86d 100644
> --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> @@ -208,6 +208,45 @@ static void setup_iomux_boardid(void)
>  	SETUP_IOMUX_PADS(hwcode_pads);
>  }
>  
> +/* DDR Code */
> +static iomux_v3_cfg_t const ddrcode_pads[] = {
> +	IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> +	IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> +};
> +
> +static void setup_iomux_ddrcode(void)
> +{
> +	/* ddr code pins */
> +	SETUP_IOMUX_PADS(ddrcode_pads);
> +}
> +
> +enum dhcom_ddr3_code {
> +	DH_DDR3_SIZE_256MIB = 0x00,
> +	DH_DDR3_SIZE_512MIB = 0x01,
> +	DH_DDR3_SIZE_1GIB   = 0x02,
> +	DH_DDR3_SIZE_2GIB   = 0x03
> +};
> +
> +#define DDR3_CODE_BIT_0   IMX_GPIO_NR(2, 22)
> +#define DDR3_CODE_BIT_1   IMX_GPIO_NR(2, 21)
> +
> +enum dhcom_ddr3_code dhcom_get_ddr3_code(void)
> +{
> +	enum dhcom_ddr3_code ddr3_code;
> +
> +	gpio_request(DDR3_CODE_BIT_0, "DDR3_CODE_BIT_0");
> +	gpio_request(DDR3_CODE_BIT_1, "DDR3_CODE_BIT_1");
> +
> +	gpio_direction_input(DDR3_CODE_BIT_0);
> +	gpio_direction_input(DDR3_CODE_BIT_1);
> +
> +	/* 256MB = 0b00; 512MB = 0b01; 1GB = 0b10; 2GB = 0b11 */
> +	ddr3_code = (!!gpio_get_value(DDR3_CODE_BIT_1) << 1)
> +	     | (!!gpio_get_value(DDR3_CODE_BIT_0));
> +
> +	return ddr3_code;
> +}
> +
>  /* GPIO */
>  static iomux_v3_cfg_t const gpio_pads[] = {
>  	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> @@ -365,6 +404,7 @@ void board_init_f(ulong dummy)
>  	timer_init();
>  
>  	setup_iomux_boardid();
> +	setup_iomux_ddrcode();
>  	setup_iomux_gpio();
>  	setup_iomux_enet();
>  	setup_iomux_sd();
> 
Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
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Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 3/3] ARM: imx6: DHCOM i.MX6 PDK: ddr init for 32bit bus and 4GBit chips

[lzenz at dh-electronics.de]

From: Ludwig Zenz <lzenz@dh-electronics.de>

Support 1GIB + 2GIB DDR3 with 64bit bus width and 512MIB + 1GIB with 32bit bus width

Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
---
 board/dhelectronics/dh_imx6/dh_imx6_spl.c | 191 +++++++++++++++++++++++++++---
 1 file changed, 173 insertions(+), 18 deletions(-)

diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
index eafb86d..04e9eab 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
@@ -136,7 +136,31 @@ static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = {
 	.grp_b7ds	= 0x00000030,
 };
 
-static const struct mx6_mmdc_calibration dhcom_mmdc_calib = {
+static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x4g_1066 = {
+	.p0_mpwldectrl0	= 0x00150019,
+	.p0_mpwldectrl1	= 0x001C000B,
+	.p1_mpwldectrl0	= 0x00020018,
+	.p1_mpwldectrl1	= 0x0002000C,
+	.p0_mpdgctrl0	= 0x43140320,
+	.p0_mpdgctrl1	= 0x03080304,
+	.p1_mpdgctrl0	= 0x43180320,
+	.p1_mpdgctrl1	= 0x03100254,
+	.p0_mprddlctl	= 0x4830383C,
+	.p1_mprddlctl	= 0x3836323E,
+	.p0_mpwrdlctl	= 0x3E444642,
+	.p1_mpwrdlctl	= 0x42344442,
+};
+
+static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = {
+	.p0_mpwldectrl0	= 0x0040003C,
+	.p0_mpwldectrl1	= 0x0032003E,
+	.p0_mpdgctrl0	= 0x42350231,
+	.p0_mpdgctrl1	= 0x021A0218,
+	.p0_mprddlctl	= 0x4B4B4E49,
+	.p0_mpwrdlctl	= 0x3F3F3035,
+};
+
+static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = {
 	.p0_mpwldectrl0	= 0x0011000E,
 	.p0_mpwldectrl1	= 0x000E001B,
 	.p1_mpwldectrl0	= 0x00190015,
@@ -151,23 +175,89 @@ static const struct mx6_mmdc_calibration dhcom_mmdc_calib = {
 	.p1_mpwrdlctl	= 0x473E4A3B,
 };
 
-static const struct mx6_ddr3_cfg dhcom_mem_ddr = {
+static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = {
+	.p0_mpwldectrl0	= 0x003A003A,
+	.p0_mpwldectrl1	= 0x0030002F,
+	.p1_mpwldectrl0	= 0x002F0038,
+	.p1_mpwldectrl1	= 0x00270039,
+	.p0_mpdgctrl0	= 0x420F020F,
+	.p0_mpdgctrl1	= 0x01760175,
+	.p1_mpdgctrl0	= 0x41640171,
+	.p1_mpdgctrl1	= 0x015E0160,
+	.p0_mprddlctl	= 0x45464B4A,
+	.p1_mprddlctl	= 0x49484A46,
+	.p0_mpwrdlctl	= 0x40402E32,
+	.p1_mpwrdlctl	= 0x3A3A3231,
+};
+
+static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x2g_800 = {
+	.p0_mpwldectrl0	= 0x0040003C,
+	.p0_mpwldectrl1	= 0x0032003E,
+	.p0_mpdgctrl0	= 0x42350231,
+	.p0_mpdgctrl1	= 0x021A0218,
+	.p0_mprddlctl	= 0x4B4B4E49,
+	.p0_mpwrdlctl	= 0x3F3F3035,
+};
+
+/*
+ * 2 Gbit DDR3 memory
+ *   - NANYA #NT5CC128M16IP-DII
+ *   - NANYA #NT5CB128M16FP-DII
+ */
+static const struct mx6_ddr3_cfg dhcom_mem_ddr_2g = {
 	.mem_speed	= 1600,
 	.density	= 2,
-	.width		= 64,
+	.width		= 16,
 	.banks		= 8,
 	.rowaddr	= 14,
 	.coladdr	= 10,
 	.pagesz		= 2,
-	.trcd		= 1312,
+	.trcd		= 1375,
 	.trcmin		= 5863,
 	.trasmin	= 3750,
 };
 
-static const struct mx6_ddr_sysinfo dhcom_ddr_info = {
+/*
+ * 4 Gbit DDR3 memory
+ *   - Intelligent Memory #IM4G16D3EABG-125I
+ */
+static const struct mx6_ddr3_cfg dhcom_mem_ddr_4g = {
+	.mem_speed	= 1600,
+	.density	= 4,
+	.width		= 16,
+	.banks		= 8,
+	.rowaddr	= 15,
+	.coladdr	= 10,
+	.pagesz		= 2,
+	.trcd		= 1375,
+	.trcmin		= 4875,
+	.trasmin	= 3500,
+};
+
+/* DDR3 64bit */
+static const struct mx6_ddr_sysinfo dhcom_ddr_64bit = {
 	/* width of data bus:0=16,1=32,2=64 */
 	.dsize		= 2,
-	.cs_density	= 16,
+	.cs_density	= 32,
+	.ncs		= 1,	/* single chip select */
+	.cs1_mirror	= 1,
+	.rtt_wr		= 1,	/* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
+	.rtt_nom	= 1,	/* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
+	.walat		= 1,	/* Write additional latency */
+	.ralat		= 5,	/* Read additional latency */
+	.mif3_mode	= 3,	/* Command prediction working mode */
+	.bi_on		= 1,	/* Bank interleaving enabled */
+	.sde_to_rst	= 0x10,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke	= 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.refsel		= 1,	/* Refresh cycles at 32KHz */
+	.refr		= 3,	/* 4 refresh commands per refresh cycle */
+};
+
+/* DDR3 32bit */
+static const struct mx6_ddr_sysinfo dhcom_ddr_32bit = {
+	/* width of data bus:0=16,1=32,2=64 */
+	.dsize		= 1,
+	.cs_density	= 32,
 	.ncs		= 1,	/* single chip select */
 	.cs1_mirror	= 1,
 	.rtt_wr		= 1,	/* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
@@ -392,6 +482,81 @@ static void setup_iomux_usb(void)
 	SETUP_IOMUX_PADS(usb_pads);
 }
 
+
+/* DRAM */
+static void dhcom_spl_dram_init(void)
+{
+	enum dhcom_ddr3_code ddr3_code = dhcom_get_ddr3_code();
+
+	if (is_mx6dq()) {
+		mx6dq_dram_iocfg(64, &dhcom6dq_ddr_ioregs,
+					&dhcom6dq_grp_ioregs);
+		switch (ddr3_code) {
+		default:
+			printf("imx6qd: unsupported ddr3 code %d\n", ddr3_code);
+			printf("        choosing 1024 MB\n");
+			/* fall through */
+		case DH_DDR3_SIZE_1GIB:
+			mx6_dram_cfg(&dhcom_ddr_64bit,
+				     &dhcom_mmdc_calib_4x2g_1066,
+				     &dhcom_mem_ddr_2g);
+			break;
+		case DH_DDR3_SIZE_2GIB:
+			mx6_dram_cfg(&dhcom_ddr_64bit,
+				     &dhcom_mmdc_calib_4x4g_1066,
+				     &dhcom_mem_ddr_4g);
+			break;
+		}
+
+		/* Perform DDR DRAM calibration */
+		udelay(100);
+		mmdc_do_dqs_calibration(&dhcom_ddr_64bit);
+
+	} else if (is_cpu_type(MXC_CPU_MX6DL)) {
+		mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs,
+					  &dhcom6sdl_grp_ioregs);
+		switch (ddr3_code) {
+		default:
+			printf("imx6dl: unsupported ddr3 code %d\n", ddr3_code);
+			printf("        choosing 1024 MB\n");
+			/* fall through */
+		case DH_DDR3_SIZE_1GIB:
+			mx6_dram_cfg(&dhcom_ddr_64bit,
+				     &dhcom_mmdc_calib_4x2g_800,
+				     &dhcom_mem_ddr_2g);
+			break;
+		}
+
+		/* Perform DDR DRAM calibration */
+		udelay(100);
+		mmdc_do_dqs_calibration(&dhcom_ddr_64bit);
+
+	} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
+		mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs,
+					  &dhcom6sdl_grp_ioregs);
+		switch (ddr3_code) {
+		default:
+			printf("imx6s: unsupported ddr3 code %d\n", ddr3_code);
+			printf("       choosing 512 MB\n");
+			/* fall through */
+		case DH_DDR3_SIZE_512MIB:
+			mx6_dram_cfg(&dhcom_ddr_32bit,
+				     &dhcom_mmdc_calib_2x2g_800,
+				     &dhcom_mem_ddr_2g);
+			break;
+		case DH_DDR3_SIZE_1GIB:
+			mx6_dram_cfg(&dhcom_ddr_32bit,
+				     &dhcom_mmdc_calib_2x4g_800,
+				     &dhcom_mem_ddr_4g);
+			break;
+		}
+
+		/* Perform DDR DRAM calibration */
+		udelay(100);
+		mmdc_do_dqs_calibration(&dhcom_ddr_32bit);
+	}
+}
+
 void board_init_f(ulong dummy)
 {
 	/* setup AIPS and disable watchdog */
@@ -415,18 +580,8 @@ void board_init_f(ulong dummy)
 	/* UART clocks enabled and gd valid - init serial console */
 	preloader_console_init();
 
-	/* Start the DDR DRAM */
-	if (is_mx6dq())
-		mx6dq_dram_iocfg(dhcom_mem_ddr.width, &dhcom6dq_ddr_ioregs,
-				 &dhcom6dq_grp_ioregs);
-	else
-		mx6sdl_dram_iocfg(dhcom_mem_ddr.width, &dhcom6sdl_ddr_ioregs,
-				  &dhcom6sdl_grp_ioregs);
-	mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr);
-
-	/* Perform DDR DRAM calibration */
-	udelay(100);
-	mmdc_do_dqs_calibration(&dhcom_ddr_info);
+	/* DDR3 initialization */
+	dhcom_spl_dram_init();
 
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
-- 
2.7.4

[U-Boot] [PATCH 3/3] ARM: imx6: DHCOM i.MX6 PDK: ddr init for 32bit bus and 4GBit chips

[Stefano Babic]

On 05/07/2018 09:23, lzenz at dh-electronics.de wrote:
> From: Ludwig Zenz <lzenz@dh-electronics.de>
> 
> Support 1GIB + 2GIB DDR3 with 64bit bus width and 512MIB + 1GIB with 32bit bus width
> 
> Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
> ---
>  board/dhelectronics/dh_imx6/dh_imx6_spl.c | 191 +++++++++++++++++++++++++++---
>  1 file changed, 173 insertions(+), 18 deletions(-)
> 
> diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> index eafb86d..04e9eab 100644
> --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> @@ -136,7 +136,31 @@ static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = {
>  	.grp_b7ds	= 0x00000030,
>  };
>  
> -static const struct mx6_mmdc_calibration dhcom_mmdc_calib = {
> +static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x4g_1066 = {
> +	.p0_mpwldectrl0	= 0x00150019,
> +	.p0_mpwldectrl1	= 0x001C000B,
> +	.p1_mpwldectrl0	= 0x00020018,
> +	.p1_mpwldectrl1	= 0x0002000C,
> +	.p0_mpdgctrl0	= 0x43140320,
> +	.p0_mpdgctrl1	= 0x03080304,
> +	.p1_mpdgctrl0	= 0x43180320,
> +	.p1_mpdgctrl1	= 0x03100254,
> +	.p0_mprddlctl	= 0x4830383C,
> +	.p1_mprddlctl	= 0x3836323E,
> +	.p0_mpwrdlctl	= 0x3E444642,
> +	.p1_mpwrdlctl	= 0x42344442,
> +};
> +
> +static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = {
> +	.p0_mpwldectrl0	= 0x0040003C,
> +	.p0_mpwldectrl1	= 0x0032003E,
> +	.p0_mpdgctrl0	= 0x42350231,
> +	.p0_mpdgctrl1	= 0x021A0218,
> +	.p0_mprddlctl	= 0x4B4B4E49,
> +	.p0_mpwrdlctl	= 0x3F3F3035,
> +};
> +
> +static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = {
>  	.p0_mpwldectrl0	= 0x0011000E,
>  	.p0_mpwldectrl1	= 0x000E001B,
>  	.p1_mpwldectrl0	= 0x00190015,
> @@ -151,23 +175,89 @@ static const struct mx6_mmdc_calibration dhcom_mmdc_calib = {
>  	.p1_mpwrdlctl	= 0x473E4A3B,
>  };
>  
> -static const struct mx6_ddr3_cfg dhcom_mem_ddr = {
> +static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = {
> +	.p0_mpwldectrl0	= 0x003A003A,
> +	.p0_mpwldectrl1	= 0x0030002F,
> +	.p1_mpwldectrl0	= 0x002F0038,
> +	.p1_mpwldectrl1	= 0x00270039,
> +	.p0_mpdgctrl0	= 0x420F020F,
> +	.p0_mpdgctrl1	= 0x01760175,
> +	.p1_mpdgctrl0	= 0x41640171,
> +	.p1_mpdgctrl1	= 0x015E0160,
> +	.p0_mprddlctl	= 0x45464B4A,
> +	.p1_mprddlctl	= 0x49484A46,
> +	.p0_mpwrdlctl	= 0x40402E32,
> +	.p1_mpwrdlctl	= 0x3A3A3231,
> +};
> +
> +static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x2g_800 = {
> +	.p0_mpwldectrl0	= 0x0040003C,
> +	.p0_mpwldectrl1	= 0x0032003E,
> +	.p0_mpdgctrl0	= 0x42350231,
> +	.p0_mpdgctrl1	= 0x021A0218,
> +	.p0_mprddlctl	= 0x4B4B4E49,
> +	.p0_mpwrdlctl	= 0x3F3F3035,
> +};
> +
> +/*
> + * 2 Gbit DDR3 memory
> + *   - NANYA #NT5CC128M16IP-DII
> + *   - NANYA #NT5CB128M16FP-DII
> + */
> +static const struct mx6_ddr3_cfg dhcom_mem_ddr_2g = {
>  	.mem_speed	= 1600,
>  	.density	= 2,
> -	.width		= 64,
> +	.width		= 16,
>  	.banks		= 8,
>  	.rowaddr	= 14,
>  	.coladdr	= 10,
>  	.pagesz		= 2,
> -	.trcd		= 1312,
> +	.trcd		= 1375,
>  	.trcmin		= 5863,
>  	.trasmin	= 3750,
>  };
>  
> -static const struct mx6_ddr_sysinfo dhcom_ddr_info = {
> +/*
> + * 4 Gbit DDR3 memory
> + *   - Intelligent Memory #IM4G16D3EABG-125I
> + */
> +static const struct mx6_ddr3_cfg dhcom_mem_ddr_4g = {
> +	.mem_speed	= 1600,
> +	.density	= 4,
> +	.width		= 16,
> +	.banks		= 8,
> +	.rowaddr	= 15,
> +	.coladdr	= 10,
> +	.pagesz		= 2,
> +	.trcd		= 1375,
> +	.trcmin		= 4875,
> +	.trasmin	= 3500,
> +};
> +
> +/* DDR3 64bit */
> +static const struct mx6_ddr_sysinfo dhcom_ddr_64bit = {
>  	/* width of data bus:0=16,1=32,2=64 */
>  	.dsize		= 2,
> -	.cs_density	= 16,
> +	.cs_density	= 32,
> +	.ncs		= 1,	/* single chip select */
> +	.cs1_mirror	= 1,
> +	.rtt_wr		= 1,	/* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
> +	.rtt_nom	= 1,	/* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
> +	.walat		= 1,	/* Write additional latency */
> +	.ralat		= 5,	/* Read additional latency */
> +	.mif3_mode	= 3,	/* Command prediction working mode */
> +	.bi_on		= 1,	/* Bank interleaving enabled */
> +	.sde_to_rst	= 0x10,	/* 14 cycles, 200us (JEDEC default) */
> +	.rst_to_cke	= 0x23,	/* 33 cycles, 500us (JEDEC default) */
> +	.refsel		= 1,	/* Refresh cycles at 32KHz */
> +	.refr		= 3,	/* 4 refresh commands per refresh cycle */
> +};
> +
> +/* DDR3 32bit */
> +static const struct mx6_ddr_sysinfo dhcom_ddr_32bit = {
> +	/* width of data bus:0=16,1=32,2=64 */
> +	.dsize		= 1,
> +	.cs_density	= 32,
>  	.ncs		= 1,	/* single chip select */
>  	.cs1_mirror	= 1,
>  	.rtt_wr		= 1,	/* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
> @@ -392,6 +482,81 @@ static void setup_iomux_usb(void)
>  	SETUP_IOMUX_PADS(usb_pads);
>  }
>  
> +
> +/* DRAM */
> +static void dhcom_spl_dram_init(void)
> +{
> +	enum dhcom_ddr3_code ddr3_code = dhcom_get_ddr3_code();
> +
> +	if (is_mx6dq()) {
> +		mx6dq_dram_iocfg(64, &dhcom6dq_ddr_ioregs,
> +					&dhcom6dq_grp_ioregs);
> +		switch (ddr3_code) {
> +		default:
> +			printf("imx6qd: unsupported ddr3 code %d\n", ddr3_code);
> +			printf("        choosing 1024 MB\n");
> +			/* fall through */
> +		case DH_DDR3_SIZE_1GIB:
> +			mx6_dram_cfg(&dhcom_ddr_64bit,
> +				     &dhcom_mmdc_calib_4x2g_1066,
> +				     &dhcom_mem_ddr_2g);
> +			break;
> +		case DH_DDR3_SIZE_2GIB:
> +			mx6_dram_cfg(&dhcom_ddr_64bit,
> +				     &dhcom_mmdc_calib_4x4g_1066,
> +				     &dhcom_mem_ddr_4g);
> +			break;
> +		}
> +
> +		/* Perform DDR DRAM calibration */
> +		udelay(100);
> +		mmdc_do_dqs_calibration(&dhcom_ddr_64bit);
> +
> +	} else if (is_cpu_type(MXC_CPU_MX6DL)) {
> +		mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs,
> +					  &dhcom6sdl_grp_ioregs);
> +		switch (ddr3_code) {
> +		default:
> +			printf("imx6dl: unsupported ddr3 code %d\n", ddr3_code);
> +			printf("        choosing 1024 MB\n");
> +			/* fall through */
> +		case DH_DDR3_SIZE_1GIB:
> +			mx6_dram_cfg(&dhcom_ddr_64bit,
> +				     &dhcom_mmdc_calib_4x2g_800,
> +				     &dhcom_mem_ddr_2g);
> +			break;
> +		}
> +
> +		/* Perform DDR DRAM calibration */
> +		udelay(100);
> +		mmdc_do_dqs_calibration(&dhcom_ddr_64bit);
> +
> +	} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
> +		mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs,
> +					  &dhcom6sdl_grp_ioregs);
> +		switch (ddr3_code) {
> +		default:
> +			printf("imx6s: unsupported ddr3 code %d\n", ddr3_code);
> +			printf("       choosing 512 MB\n");
> +			/* fall through */
> +		case DH_DDR3_SIZE_512MIB:
> +			mx6_dram_cfg(&dhcom_ddr_32bit,
> +				     &dhcom_mmdc_calib_2x2g_800,
> +				     &dhcom_mem_ddr_2g);
> +			break;
> +		case DH_DDR3_SIZE_1GIB:
> +			mx6_dram_cfg(&dhcom_ddr_32bit,
> +				     &dhcom_mmdc_calib_2x4g_800,
> +				     &dhcom_mem_ddr_4g);
> +			break;
> +		}
> +
> +		/* Perform DDR DRAM calibration */
> +		udelay(100);
> +		mmdc_do_dqs_calibration(&dhcom_ddr_32bit);
> +	}
> +}
> +
>  void board_init_f(ulong dummy)
>  {
>  	/* setup AIPS and disable watchdog */
> @@ -415,18 +580,8 @@ void board_init_f(ulong dummy)
>  	/* UART clocks enabled and gd valid - init serial console */
>  	preloader_console_init();
>  
> -	/* Start the DDR DRAM */
> -	if (is_mx6dq())
> -		mx6dq_dram_iocfg(dhcom_mem_ddr.width, &dhcom6dq_ddr_ioregs,
> -				 &dhcom6dq_grp_ioregs);
> -	else
> -		mx6sdl_dram_iocfg(dhcom_mem_ddr.width, &dhcom6sdl_ddr_ioregs,
> -				  &dhcom6sdl_grp_ioregs);
> -	mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr);
> -
> -	/* Perform DDR DRAM calibration */
> -	udelay(100);
> -	mmdc_do_dqs_calibration(&dhcom_ddr_info);
> +	/* DDR3 initialization */
> +	dhcom_spl_dram_init();
>  
>  	/* Clear the BSS. */
>  	memset(__bss_start, 0, __bss_end - __bss_start);
> 

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 3/3] ARM: imx6: DHCOM i.MX6 PDK: ddr init for 32bit bus and 4GBit chips

[Marek Vasut]

On 07/05/2018 09:23 AM, lzenz at dh-electronics.de wrote:
> From: Ludwig Zenz <lzenz@dh-electronics.de>
> 
> Support 1GIB + 2GIB DDR3 with 64bit bus width and 512MIB + 1GIB with 32bit bus width
> 
> Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
> ---
>  board/dhelectronics/dh_imx6/dh_imx6_spl.c | 191 +++++++++++++++++++++++++++---
>  1 file changed, 173 insertions(+), 18 deletions(-)
> 
> diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
[...]

This patch causes memory instability on 1GiB MX6Q part.

Can you check that and fix it ? Thanks.

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH 3/3] ARM: imx6: DHCOM i.MX6 PDK: ddr init for 32bit bus and 4GBit chips

[Ludwig Zenz]

Hello Marek,

>> From: Ludwig Zenz <lzenz@dh-electronics.de>
>> 
>> Support 1GIB + 2GIB DDR3 with 64bit bus width and 512MIB + 1GIB with 32bit bus width
>> 
>> Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
>> ---
>>  board/dhelectronics/dh_imx6/dh_imx6_spl.c | 191 +++++++++++++++++++++++++++---
>>  1 file changed, 173 insertions(+), 18 deletions(-)
>> 
>> diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> [...]
> 
> This patch causes memory instability on 1GiB MX6Q part.
> 
> Can you check that and fix it ? Thanks.

Can you tell me more about the error? How do you test this? Did you run a git bisect?

We did tests in a climate chamber with this configuration (with the MX6Q and all others).

I think there is only one change that could make a difference:

static const struct mx6_ddr3_cfg dhcom_mem_ddr_2g = {
...
-       .trcd           = 1312,
+       .trcd           = 1375,
....

Best Regards,
Ludwig Zenz

[U-Boot] [PATCH 3/3] ARM: imx6: DHCOM i.MX6 PDK: ddr init for 32bit bus and 4GBit chips

[Marek Vasut]

On 10/11/2018 09:09 AM, Ludwig Zenz wrote:
> Hello Marek,

Hello Ludwig,

>>> From: Ludwig Zenz <lzenz@dh-electronics.de>
>>>
>>> Support 1GIB + 2GIB DDR3 with 64bit bus width and 512MIB + 1GIB with 32bit bus width
>>>
>>> Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
>>> ---
>>>  board/dhelectronics/dh_imx6/dh_imx6_spl.c | 191 +++++++++++++++++++++++++++---
>>>  1 file changed, 173 insertions(+), 18 deletions(-)
>>>
>>> diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
>> [...]
>>
>> This patch causes memory instability on 1GiB MX6Q part.
>>
>> Can you check that and fix it ? Thanks.
> 
> Can you tell me more about the error? How do you test this? Did you run a git bisect?
> 
> We did tests in a climate chamber with this configuration (with the MX6Q and all others).
> 
> I think there is only one change that could make a difference:
> 
> static const struct mx6_ddr3_cfg dhcom_mem_ddr_2g = {
> ...
> -       .trcd           = 1312,
> +       .trcd           = 1375,
> ....

In this particular case, the board exhibited random instability. Try
running memtester in linux for a few days, maybe some board that you
have will start exhibiting this too.

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH 1/3] Revert "ARM: imx6: Disable DDR DRAM calibration DHCOM i.MX6 PDK"

[Stefano Babic]

On 05/07/2018 09:23, lzenz at dh-electronics.de wrote:
> From: Ludwig Zenz <lzenz@dh-electronics.de>
> 
> This reverts commit a637fe6f27fd4c19ef9f43a5f871c244581422ac.
> 
> The DDR DRAM calibration was enhanced by write leveling correction code.
> It can be used with T-topology now.
> 
> Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
> ---
>  board/dhelectronics/dh_imx6/dh_imx6_spl.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> index dffe4eb..beda389 100644
> --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> @@ -384,6 +384,10 @@ void board_init_f(ulong dummy)
>  				  &dhcom6sdl_grp_ioregs);
>  	mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr);
>  
> +	/* Perform DDR DRAM calibration */
> +	udelay(100);
> +	mmdc_do_dqs_calibration(&dhcom_ddr_info);
> +
>  	/* Clear the BSS. */
>  	memset(__bss_start, 0, __bss_end - __bss_start);
>  
> 

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================