* [Qemu-devel] [PULL 01/28] target-ppc: Use sensible POWER8/POWER8E versions
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 19:14 ` Alexander Graf
2016-01-25 1:15 ` [Qemu-devel] [PULL 02/28] target-ppc: use cpu_write_xer() helper in cpu_post_load David Gibson
` (27 subsequent siblings)
28 siblings, 1 reply; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
We never released anything older than POWER8 DD2.0 and POWER8E DD2.1,
so let's use these versions, without that some firmware or Linux code
might fail to use some HW features that were non functional in earlier
internal only spins of the chip.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/cpu-models.c | 12 ++++++------
target-ppc/cpu-models.h | 4 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
index 4d5ab4b..349783e 100644
--- a/target-ppc/cpu-models.c
+++ b/target-ppc/cpu-models.c
@@ -1138,10 +1138,10 @@
"POWER7 v2.3")
POWERPC_DEF("POWER7+_v2.1", CPU_POWERPC_POWER7P_v21, POWER7,
"POWER7+ v2.1")
- POWERPC_DEF("POWER8E_v1.0", CPU_POWERPC_POWER8E_v10, POWER8,
- "POWER8E v1.0")
- POWERPC_DEF("POWER8_v1.0", CPU_POWERPC_POWER8_v10, POWER8,
- "POWER8 v1.0")
+ POWERPC_DEF("POWER8E_v2.1", CPU_POWERPC_POWER8E_v21, POWER8,
+ "POWER8E v2.1")
+ POWERPC_DEF("POWER8_v2.0", CPU_POWERPC_POWER8_v20, POWER8,
+ "POWER8 v2.0")
POWERPC_DEF("970_v2.2", CPU_POWERPC_970_v22, 970,
"PowerPC 970 v2.2")
POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970,
@@ -1389,8 +1389,8 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "POWER5gs", "POWER5+_v2.1" },
{ "POWER7", "POWER7_v2.3" },
{ "POWER7+", "POWER7+_v2.1" },
- { "POWER8E", "POWER8E_v1.0" },
- { "POWER8", "POWER8_v1.0" },
+ { "POWER8E", "POWER8E_v2.1" },
+ { "POWER8", "POWER8_v2.0" },
{ "970", "970_v2.2" },
{ "970fx", "970fx_v3.1" },
{ "970mp", "970mp_v1.1" },
diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h
index 9d80e72..2992427 100644
--- a/target-ppc/cpu-models.h
+++ b/target-ppc/cpu-models.h
@@ -557,9 +557,9 @@ enum {
CPU_POWERPC_POWER7P_BASE = 0x004A0000,
CPU_POWERPC_POWER7P_v21 = 0x004A0201,
CPU_POWERPC_POWER8E_BASE = 0x004B0000,
- CPU_POWERPC_POWER8E_v10 = 0x004B0100,
+ CPU_POWERPC_POWER8E_v21 = 0x004B0201,
CPU_POWERPC_POWER8_BASE = 0x004D0000,
- CPU_POWERPC_POWER8_v10 = 0x004D0100,
+ CPU_POWERPC_POWER8_v20 = 0x004D0200,
CPU_POWERPC_970_v22 = 0x00390202,
CPU_POWERPC_970FX_v10 = 0x00391100,
CPU_POWERPC_970FX_v20 = 0x003C0200,
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [Qemu-devel] [PULL 01/28] target-ppc: Use sensible POWER8/POWER8E versions
2016-01-25 1:15 ` [Qemu-devel] [PULL 01/28] target-ppc: Use sensible POWER8/POWER8E versions David Gibson
@ 2016-01-25 19:14 ` Alexander Graf
2016-01-25 19:26 ` Thomas Huth
0 siblings, 1 reply; 46+ messages in thread
From: Alexander Graf @ 2016-01-25 19:14 UTC (permalink / raw)
To: David Gibson, peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, qemu-devel, qemu-ppc, bharata, gkurz
On 01/25/2016 02:15 AM, David Gibson wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> We never released anything older than POWER8 DD2.0 and POWER8E DD2.1,
> so let's use these versions, without that some firmware or Linux code
> might fail to use some HW features that were non functional in earlier
> internal only spins of the chip.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target-ppc/cpu-models.c | 12 ++++++------
> target-ppc/cpu-models.h | 4 ++--
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
> index 4d5ab4b..349783e 100644
> --- a/target-ppc/cpu-models.c
> +++ b/target-ppc/cpu-models.c
> @@ -1138,10 +1138,10 @@
> "POWER7 v2.3")
> POWERPC_DEF("POWER7+_v2.1", CPU_POWERPC_POWER7P_v21, POWER7,
> "POWER7+ v2.1")
> - POWERPC_DEF("POWER8E_v1.0", CPU_POWERPC_POWER8E_v10, POWER8,
> - "POWER8E v1.0")
> - POWERPC_DEF("POWER8_v1.0", CPU_POWERPC_POWER8_v10, POWER8,
> - "POWER8 v1.0")
Removing those breaks -cpu host on 1.0 machines, no?
Alex
> + POWERPC_DEF("POWER8E_v2.1", CPU_POWERPC_POWER8E_v21, POWER8,
> + "POWER8E v2.1")
> + POWERPC_DEF("POWER8_v2.0", CPU_POWERPC_POWER8_v20, POWER8,
> + "POWER8 v2.0")
> POWERPC_DEF("970_v2.2", CPU_POWERPC_970_v22, 970,
> "PowerPC 970 v2.2")
> POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970,
> @@ -1389,8 +1389,8 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
> { "POWER5gs", "POWER5+_v2.1" },
> { "POWER7", "POWER7_v2.3" },
> { "POWER7+", "POWER7+_v2.1" },
> - { "POWER8E", "POWER8E_v1.0" },
> - { "POWER8", "POWER8_v1.0" },
> + { "POWER8E", "POWER8E_v2.1" },
> + { "POWER8", "POWER8_v2.0" },
> { "970", "970_v2.2" },
> { "970fx", "970fx_v3.1" },
> { "970mp", "970mp_v1.1" },
> diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h
> index 9d80e72..2992427 100644
> --- a/target-ppc/cpu-models.h
> +++ b/target-ppc/cpu-models.h
> @@ -557,9 +557,9 @@ enum {
> CPU_POWERPC_POWER7P_BASE = 0x004A0000,
> CPU_POWERPC_POWER7P_v21 = 0x004A0201,
> CPU_POWERPC_POWER8E_BASE = 0x004B0000,
> - CPU_POWERPC_POWER8E_v10 = 0x004B0100,
> + CPU_POWERPC_POWER8E_v21 = 0x004B0201,
> CPU_POWERPC_POWER8_BASE = 0x004D0000,
> - CPU_POWERPC_POWER8_v10 = 0x004D0100,
> + CPU_POWERPC_POWER8_v20 = 0x004D0200,
> CPU_POWERPC_970_v22 = 0x00390202,
> CPU_POWERPC_970FX_v10 = 0x00391100,
> CPU_POWERPC_970FX_v20 = 0x003C0200,
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [Qemu-devel] [PULL 01/28] target-ppc: Use sensible POWER8/POWER8E versions
2016-01-25 19:14 ` Alexander Graf
@ 2016-01-25 19:26 ` Thomas Huth
2016-01-25 20:20 ` Alexander Graf
2016-01-29 6:15 ` [Qemu-devel] [Qemu-ppc] " Stewart Smith
0 siblings, 2 replies; 46+ messages in thread
From: Thomas Huth @ 2016-01-25 19:26 UTC (permalink / raw)
To: Alexander Graf, David Gibson, peter.maydell
Cc: lvivier, mark.cave-ayland, qemu-devel, qemu-ppc, bharata, gkurz
On 25.01.2016 20:14, Alexander Graf wrote:
>
>
> On 01/25/2016 02:15 AM, David Gibson wrote:
>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>
>> We never released anything older than POWER8 DD2.0 and POWER8E DD2.1,
>> so let's use these versions, without that some firmware or Linux code
>> might fail to use some HW features that were non functional in earlier
>> internal only spins of the chip.
>>
>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
>> ---
>> target-ppc/cpu-models.c | 12 ++++++------
>> target-ppc/cpu-models.h | 4 ++--
>> 2 files changed, 8 insertions(+), 8 deletions(-)
>>
>> diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
>> index 4d5ab4b..349783e 100644
>> --- a/target-ppc/cpu-models.c
>> +++ b/target-ppc/cpu-models.c
>> @@ -1138,10 +1138,10 @@
>> "POWER7 v2.3")
>> POWERPC_DEF("POWER7+_v2.1", CPU_POWERPC_POWER7P_v21,
>> POWER7,
>> "POWER7+ v2.1")
>> - POWERPC_DEF("POWER8E_v1.0", CPU_POWERPC_POWER8E_v10,
>> POWER8,
>> - "POWER8E v1.0")
>> - POWERPC_DEF("POWER8_v1.0", CPU_POWERPC_POWER8_v10,
>> POWER8,
>> - "POWER8 v1.0")
>
> Removing those breaks -cpu host on 1.0 machines, no?
I don't think so. The code in kvm_ppc_register_host_cpu_type()
explicitly registers a "host" CPU type with the PVR of the current host.
Apart from that, as mentioned in the patch description, v1.0 chips
apparently have never been released into the wild - and I guess the
unreleased v1.0 chips have all already scrapped nowadays ... so the
patch should be fine, I think.
Thomas
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [Qemu-devel] [PULL 01/28] target-ppc: Use sensible POWER8/POWER8E versions
2016-01-25 19:26 ` Thomas Huth
@ 2016-01-25 20:20 ` Alexander Graf
2016-01-29 6:15 ` [Qemu-devel] [Qemu-ppc] " Stewart Smith
1 sibling, 0 replies; 46+ messages in thread
From: Alexander Graf @ 2016-01-25 20:20 UTC (permalink / raw)
To: Thomas Huth, David Gibson, peter.maydell
Cc: lvivier, mark.cave-ayland, qemu-devel, qemu-ppc, bharata, gkurz
On 01/25/2016 08:26 PM, Thomas Huth wrote:
> On 25.01.2016 20:14, Alexander Graf wrote:
>>
>> On 01/25/2016 02:15 AM, David Gibson wrote:
>>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>>
>>> We never released anything older than POWER8 DD2.0 and POWER8E DD2.1,
>>> so let's use these versions, without that some firmware or Linux code
>>> might fail to use some HW features that were non functional in earlier
>>> internal only spins of the chip.
>>>
>>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
>>> ---
>>> target-ppc/cpu-models.c | 12 ++++++------
>>> target-ppc/cpu-models.h | 4 ++--
>>> 2 files changed, 8 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
>>> index 4d5ab4b..349783e 100644
>>> --- a/target-ppc/cpu-models.c
>>> +++ b/target-ppc/cpu-models.c
>>> @@ -1138,10 +1138,10 @@
>>> "POWER7 v2.3")
>>> POWERPC_DEF("POWER7+_v2.1", CPU_POWERPC_POWER7P_v21,
>>> POWER7,
>>> "POWER7+ v2.1")
>>> - POWERPC_DEF("POWER8E_v1.0", CPU_POWERPC_POWER8E_v10,
>>> POWER8,
>>> - "POWER8E v1.0")
>>> - POWERPC_DEF("POWER8_v1.0", CPU_POWERPC_POWER8_v10,
>>> POWER8,
>>> - "POWER8 v1.0")
>> Removing those breaks -cpu host on 1.0 machines, no?
> I don't think so. The code in kvm_ppc_register_host_cpu_type()
> explicitly registers a "host" CPU type with the PVR of the current host.
Ah, right, it used to only search for a fitting one, but I think we
changed it to account for cpu families. So all is safe :).
Alex
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [Qemu-devel] [Qemu-ppc] [PULL 01/28] target-ppc: Use sensible POWER8/POWER8E versions
2016-01-25 19:26 ` Thomas Huth
2016-01-25 20:20 ` Alexander Graf
@ 2016-01-29 6:15 ` Stewart Smith
1 sibling, 0 replies; 46+ messages in thread
From: Stewart Smith @ 2016-01-29 6:15 UTC (permalink / raw)
To: Thomas Huth, Alexander Graf, David Gibson, peter.maydell
Cc: lvivier, gkurz, qemu-ppc, qemu-devel, bharata
Thomas Huth <thuth@redhat.com> writes:
> Apart from that, as mentioned in the patch description, v1.0 chips
> apparently have never been released into the wild - and I guess the
> unreleased v1.0 chips have all already scrapped nowadays ... so the
> patch should be fine, I think.
Not only not in the wild, but I'm pretty sure there's < 1.0 of them left
inside IBM. Literally 0 users who expect *anything* to work.
--
Stewart Smith
OPAL Architect, IBM.
^ permalink raw reply [flat|nested] 46+ messages in thread
* [Qemu-devel] [PULL 02/28] target-ppc: use cpu_write_xer() helper in cpu_post_load
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 01/28] target-ppc: Use sensible POWER8/POWER8E versions David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 03/28] macio: use the existing IDEDMA aiocb to hold the active DMA aiocb David Gibson
` (26 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Otherwise some internal xer variables fail to get set post-migration.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/machine.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/machine.c b/target-ppc/machine.c
index f4ac761..b61c060 100644
--- a/target-ppc/machine.c
+++ b/target-ppc/machine.c
@@ -168,7 +168,7 @@ static int cpu_post_load(void *opaque, int version_id)
env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
env->lr = env->spr[SPR_LR];
env->ctr = env->spr[SPR_CTR];
- env->xer = env->spr[SPR_XER];
+ cpu_write_xer(env, env->spr[SPR_XER]);
#if defined(TARGET_PPC64)
env->cfar = env->spr[SPR_CFAR];
#endif
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 03/28] macio: use the existing IDEDMA aiocb to hold the active DMA aiocb
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 01/28] target-ppc: Use sensible POWER8/POWER8E versions David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 02/28] target-ppc: use cpu_write_xer() helper in cpu_post_load David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 04/28] macio: add dma_active to VMStateDescription David Gibson
` (25 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Currently the aiocb is held within MACIOIDEState, however the IDE core code
assumes that the current actvie DMA aiocb is held in aiocb in a few places,
e.g. ide_bus_reset() and ide_reset().
Switch over to using IDEDMA aiocb to store the aiocb for the current active
DMA request so that bus resets and restarts are handled correctly. As a
consequence we can now use ide_set_inactive() rather than handling its
functionality ourselves.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: John Snow <jsnow@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ide/macio.c | 20 +-
hw/ide/macio.c.orig | 634 ++++++++++++++++++++++++++++++++++++++++++++++++++++
hw/ppc/mac.h | 1 -
3 files changed, 646 insertions(+), 9 deletions(-)
create mode 100644 hw/ide/macio.c.orig
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index d4031b6..110af46 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -119,8 +119,8 @@ static void pmac_dma_read(BlockBackend *blk,
MACIO_DPRINTF("--- Block read transfer - sector_num: %" PRIx64 " "
"nsector: %x\n", (offset >> 9), (bytes >> 9));
- m->aiocb = blk_aio_readv(blk, (offset >> 9), &io->iov, (bytes >> 9),
- cb, io);
+ s->bus->dma->aiocb = blk_aio_readv(blk, (offset >> 9), &io->iov,
+ (bytes >> 9), cb, io);
}
static void pmac_dma_write(BlockBackend *blk,
@@ -204,8 +204,8 @@ static void pmac_dma_write(BlockBackend *blk,
MACIO_DPRINTF("--- Block write transfer - sector_num: %" PRIx64 " "
"nsector: %x\n", (offset >> 9), (bytes >> 9));
- m->aiocb = blk_aio_writev(blk, (offset >> 9), &io->iov, (bytes >> 9),
- cb, io);
+ s->bus->dma->aiocb = blk_aio_writev(blk, (offset >> 9), &io->iov,
+ (bytes >> 9), cb, io);
}
static void pmac_dma_trim(BlockBackend *blk,
@@ -231,8 +231,8 @@ static void pmac_dma_trim(BlockBackend *blk,
s->io_buffer_index += io->len;
io->len = 0;
- m->aiocb = ide_issue_trim(blk, (offset >> 9), &io->iov, (bytes >> 9),
- cb, io);
+ s->bus->dma->aiocb = ide_issue_trim(blk, (offset >> 9), &io->iov,
+ (bytes >> 9), cb, io);
}
static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
@@ -291,6 +291,8 @@ done:
} else {
block_acct_done(blk_get_stats(s->blk), &s->acct);
}
+
+ ide_set_inactive(s, false);
io->dma_end(opaque);
}
@@ -305,7 +307,6 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
if (ret < 0) {
MACIO_DPRINTF("DMA error: %d\n", ret);
- m->aiocb = NULL;
ide_dma_error(s);
goto done;
}
@@ -356,6 +357,8 @@ done:
block_acct_done(blk_get_stats(s->blk), &s->acct);
}
}
+
+ ide_set_inactive(s, false);
io->dma_end(opaque);
}
@@ -393,8 +396,9 @@ static void pmac_ide_transfer(DBDMA_io *io)
static void pmac_ide_flush(DBDMA_io *io)
{
MACIOIDEState *m = io->opaque;
+ IDEState *s = idebus_active_if(&m->bus);
- if (m->aiocb) {
+ if (s->bus->dma->aiocb) {
blk_drain_all();
}
}
diff --git a/hw/ide/macio.c.orig b/hw/ide/macio.c.orig
new file mode 100644
index 0000000..d4031b6
--- /dev/null
+++ b/hw/ide/macio.c.orig
@@ -0,0 +1,634 @@
+/*
+ * QEMU IDE Emulation: MacIO support.
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ * Copyright (c) 2006 Openedhand Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw/hw.h"
+#include "hw/ppc/mac.h"
+#include "hw/ppc/mac_dbdma.h"
+#include "sysemu/block-backend.h"
+#include "sysemu/dma.h"
+
+#include <hw/ide/internal.h>
+
+/* debug MACIO */
+// #define DEBUG_MACIO
+
+#ifdef DEBUG_MACIO
+static const int debug_macio = 1;
+#else
+static const int debug_macio = 0;
+#endif
+
+#define MACIO_DPRINTF(fmt, ...) do { \
+ if (debug_macio) { \
+ printf(fmt , ## __VA_ARGS__); \
+ } \
+ } while (0)
+
+
+/***********************************************************/
+/* MacIO based PowerPC IDE */
+
+#define MACIO_PAGE_SIZE 4096
+
+/*
+ * Unaligned DMA read/write access functions required for OS X/Darwin which
+ * don't perform DMA transactions on sector boundaries. These functions are
+ * modelled on bdrv_co_do_preadv()/bdrv_co_do_pwritev() and so should be
+ * easy to remove if the unaligned block APIs are ever exposed.
+ */
+
+static void pmac_dma_read(BlockBackend *blk,
+ int64_t offset, unsigned int bytes,
+ void (*cb)(void *opaque, int ret), void *opaque)
+{
+ DBDMA_io *io = opaque;
+ MACIOIDEState *m = io->opaque;
+ IDEState *s = idebus_active_if(&m->bus);
+ dma_addr_t dma_addr, dma_len;
+ void *mem;
+ int64_t sector_num;
+ int nsector;
+ uint64_t align = BDRV_SECTOR_SIZE;
+ size_t head_bytes, tail_bytes;
+
+ qemu_iovec_destroy(&io->iov);
+ qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
+
+ sector_num = (offset >> 9);
+ nsector = (io->len >> 9);
+
+ MACIO_DPRINTF("--- DMA read transfer (0x%" HWADDR_PRIx ",0x%x): "
+ "sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
+ sector_num, nsector);
+
+ dma_addr = io->addr;
+ dma_len = io->len;
+ mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
+ DMA_DIRECTION_FROM_DEVICE);
+
+ if (offset & (align - 1)) {
+ head_bytes = offset & (align - 1);
+
+ MACIO_DPRINTF("--- DMA unaligned head: sector %" PRId64 ", "
+ "discarding %zu bytes\n", sector_num, head_bytes);
+
+ qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
+
+ bytes += offset & (align - 1);
+ offset = offset & ~(align - 1);
+ }
+
+ qemu_iovec_add(&io->iov, mem, io->len);
+
+ if ((offset + bytes) & (align - 1)) {
+ tail_bytes = (offset + bytes) & (align - 1);
+
+ MACIO_DPRINTF("--- DMA unaligned tail: sector %" PRId64 ", "
+ "discarding bytes %zu\n", sector_num, tail_bytes);
+
+ qemu_iovec_add(&io->iov, &io->tail_remainder, align - tail_bytes);
+ bytes = ROUND_UP(bytes, align);
+ }
+
+ s->io_buffer_size -= io->len;
+ s->io_buffer_index += io->len;
+
+ io->len = 0;
+
+ MACIO_DPRINTF("--- Block read transfer - sector_num: %" PRIx64 " "
+ "nsector: %x\n", (offset >> 9), (bytes >> 9));
+
+ m->aiocb = blk_aio_readv(blk, (offset >> 9), &io->iov, (bytes >> 9),
+ cb, io);
+}
+
+static void pmac_dma_write(BlockBackend *blk,
+ int64_t offset, int bytes,
+ void (*cb)(void *opaque, int ret), void *opaque)
+{
+ DBDMA_io *io = opaque;
+ MACIOIDEState *m = io->opaque;
+ IDEState *s = idebus_active_if(&m->bus);
+ dma_addr_t dma_addr, dma_len;
+ void *mem;
+ int64_t sector_num;
+ int nsector;
+ uint64_t align = BDRV_SECTOR_SIZE;
+ size_t head_bytes, tail_bytes;
+ bool unaligned_head = false, unaligned_tail = false;
+
+ qemu_iovec_destroy(&io->iov);
+ qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
+
+ sector_num = (offset >> 9);
+ nsector = (io->len >> 9);
+
+ MACIO_DPRINTF("--- DMA write transfer (0x%" HWADDR_PRIx ",0x%x): "
+ "sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
+ sector_num, nsector);
+
+ dma_addr = io->addr;
+ dma_len = io->len;
+ mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
+ DMA_DIRECTION_TO_DEVICE);
+
+ if (offset & (align - 1)) {
+ head_bytes = offset & (align - 1);
+ sector_num = ((offset & ~(align - 1)) >> 9);
+
+ MACIO_DPRINTF("--- DMA unaligned head: pre-reading head sector %"
+ PRId64 "\n", sector_num);
+
+ blk_pread(s->blk, (sector_num << 9), &io->head_remainder, align);
+
+ qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
+ qemu_iovec_add(&io->iov, mem, io->len);
+
+ bytes += offset & (align - 1);
+ offset = offset & ~(align - 1);
+
+ unaligned_head = true;
+ }
+
+ if ((offset + bytes) & (align - 1)) {
+ tail_bytes = (offset + bytes) & (align - 1);
+ sector_num = (((offset + bytes) & ~(align - 1)) >> 9);
+
+ MACIO_DPRINTF("--- DMA unaligned tail: pre-reading tail sector %"
+ PRId64 "\n", sector_num);
+
+ blk_pread(s->blk, (sector_num << 9), &io->tail_remainder, align);
+
+ if (!unaligned_head) {
+ qemu_iovec_add(&io->iov, mem, io->len);
+ }
+
+ qemu_iovec_add(&io->iov, &io->tail_remainder + tail_bytes,
+ align - tail_bytes);
+
+ bytes = ROUND_UP(bytes, align);
+
+ unaligned_tail = true;
+ }
+
+ if (!unaligned_head && !unaligned_tail) {
+ qemu_iovec_add(&io->iov, mem, io->len);
+ }
+
+ s->io_buffer_size -= io->len;
+ s->io_buffer_index += io->len;
+
+ io->len = 0;
+
+ MACIO_DPRINTF("--- Block write transfer - sector_num: %" PRIx64 " "
+ "nsector: %x\n", (offset >> 9), (bytes >> 9));
+
+ m->aiocb = blk_aio_writev(blk, (offset >> 9), &io->iov, (bytes >> 9),
+ cb, io);
+}
+
+static void pmac_dma_trim(BlockBackend *blk,
+ int64_t offset, int bytes,
+ void (*cb)(void *opaque, int ret), void *opaque)
+{
+ DBDMA_io *io = opaque;
+ MACIOIDEState *m = io->opaque;
+ IDEState *s = idebus_active_if(&m->bus);
+ dma_addr_t dma_addr, dma_len;
+ void *mem;
+
+ qemu_iovec_destroy(&io->iov);
+ qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
+
+ dma_addr = io->addr;
+ dma_len = io->len;
+ mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
+ DMA_DIRECTION_TO_DEVICE);
+
+ qemu_iovec_add(&io->iov, mem, io->len);
+ s->io_buffer_size -= io->len;
+ s->io_buffer_index += io->len;
+ io->len = 0;
+
+ m->aiocb = ide_issue_trim(blk, (offset >> 9), &io->iov, (bytes >> 9),
+ cb, io);
+}
+
+static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
+{
+ DBDMA_io *io = opaque;
+ MACIOIDEState *m = io->opaque;
+ IDEState *s = idebus_active_if(&m->bus);
+ int64_t offset;
+
+ MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
+
+ if (ret < 0) {
+ MACIO_DPRINTF("DMA error: %d\n", ret);
+ ide_atapi_io_error(s, ret);
+ goto done;
+ }
+
+ if (!m->dma_active) {
+ MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
+ s->nsector, io->len, s->status);
+ /* data not ready yet, wait for the channel to get restarted */
+ io->processing = false;
+ return;
+ }
+
+ if (s->io_buffer_size <= 0) {
+ MACIO_DPRINTF("End of IDE transfer\n");
+ ide_atapi_cmd_ok(s);
+ m->dma_active = false;
+ goto done;
+ }
+
+ if (io->len == 0) {
+ MACIO_DPRINTF("End of DMA transfer\n");
+ goto done;
+ }
+
+ if (s->lba == -1) {
+ /* Non-block ATAPI transfer - just copy to RAM */
+ s->io_buffer_size = MIN(s->io_buffer_size, io->len);
+ cpu_physical_memory_write(io->addr, s->io_buffer, s->io_buffer_size);
+ ide_atapi_cmd_ok(s);
+ m->dma_active = false;
+ goto done;
+ }
+
+ /* Calculate current offset */
+ offset = ((int64_t)s->lba << 11) + s->io_buffer_index;
+
+ pmac_dma_read(s->blk, offset, io->len, pmac_ide_atapi_transfer_cb, io);
+ return;
+
+done:
+ if (ret < 0) {
+ block_acct_failed(blk_get_stats(s->blk), &s->acct);
+ } else {
+ block_acct_done(blk_get_stats(s->blk), &s->acct);
+ }
+ io->dma_end(opaque);
+}
+
+static void pmac_ide_transfer_cb(void *opaque, int ret)
+{
+ DBDMA_io *io = opaque;
+ MACIOIDEState *m = io->opaque;
+ IDEState *s = idebus_active_if(&m->bus);
+ int64_t offset;
+
+ MACIO_DPRINTF("pmac_ide_transfer_cb\n");
+
+ if (ret < 0) {
+ MACIO_DPRINTF("DMA error: %d\n", ret);
+ m->aiocb = NULL;
+ ide_dma_error(s);
+ goto done;
+ }
+
+ if (!m->dma_active) {
+ MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
+ s->nsector, io->len, s->status);
+ /* data not ready yet, wait for the channel to get restarted */
+ io->processing = false;
+ return;
+ }
+
+ if (s->io_buffer_size <= 0) {
+ MACIO_DPRINTF("End of IDE transfer\n");
+ s->status = READY_STAT | SEEK_STAT;
+ ide_set_irq(s->bus);
+ m->dma_active = false;
+ goto done;
+ }
+
+ if (io->len == 0) {
+ MACIO_DPRINTF("End of DMA transfer\n");
+ goto done;
+ }
+
+ /* Calculate number of sectors */
+ offset = (ide_get_sector(s) << 9) + s->io_buffer_index;
+
+ switch (s->dma_cmd) {
+ case IDE_DMA_READ:
+ pmac_dma_read(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
+ break;
+ case IDE_DMA_WRITE:
+ pmac_dma_write(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
+ break;
+ case IDE_DMA_TRIM:
+ pmac_dma_trim(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
+ break;
+ }
+
+ return;
+
+done:
+ if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
+ if (ret < 0) {
+ block_acct_failed(blk_get_stats(s->blk), &s->acct);
+ } else {
+ block_acct_done(blk_get_stats(s->blk), &s->acct);
+ }
+ }
+ io->dma_end(opaque);
+}
+
+static void pmac_ide_transfer(DBDMA_io *io)
+{
+ MACIOIDEState *m = io->opaque;
+ IDEState *s = idebus_active_if(&m->bus);
+
+ MACIO_DPRINTF("\n");
+
+ if (s->drive_kind == IDE_CD) {
+ block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
+ BLOCK_ACCT_READ);
+
+ pmac_ide_atapi_transfer_cb(io, 0);
+ return;
+ }
+
+ switch (s->dma_cmd) {
+ case IDE_DMA_READ:
+ block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
+ BLOCK_ACCT_READ);
+ break;
+ case IDE_DMA_WRITE:
+ block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
+ BLOCK_ACCT_WRITE);
+ break;
+ default:
+ break;
+ }
+
+ pmac_ide_transfer_cb(io, 0);
+}
+
+static void pmac_ide_flush(DBDMA_io *io)
+{
+ MACIOIDEState *m = io->opaque;
+
+ if (m->aiocb) {
+ blk_drain_all();
+ }
+}
+
+/* PowerMac IDE memory IO */
+static void pmac_ide_writeb (void *opaque,
+ hwaddr addr, uint32_t val)
+{
+ MACIOIDEState *d = opaque;
+
+ addr = (addr & 0xFFF) >> 4;
+ switch (addr) {
+ case 1 ... 7:
+ ide_ioport_write(&d->bus, addr, val);
+ break;
+ case 8:
+ case 22:
+ ide_cmd_write(&d->bus, 0, val);
+ break;
+ default:
+ break;
+ }
+}
+
+static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
+{
+ uint8_t retval;
+ MACIOIDEState *d = opaque;
+
+ addr = (addr & 0xFFF) >> 4;
+ switch (addr) {
+ case 1 ... 7:
+ retval = ide_ioport_read(&d->bus, addr);
+ break;
+ case 8:
+ case 22:
+ retval = ide_status_read(&d->bus, 0);
+ break;
+ default:
+ retval = 0xFF;
+ break;
+ }
+ return retval;
+}
+
+static void pmac_ide_writew (void *opaque,
+ hwaddr addr, uint32_t val)
+{
+ MACIOIDEState *d = opaque;
+
+ addr = (addr & 0xFFF) >> 4;
+ val = bswap16(val);
+ if (addr == 0) {
+ ide_data_writew(&d->bus, 0, val);
+ }
+}
+
+static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
+{
+ uint16_t retval;
+ MACIOIDEState *d = opaque;
+
+ addr = (addr & 0xFFF) >> 4;
+ if (addr == 0) {
+ retval = ide_data_readw(&d->bus, 0);
+ } else {
+ retval = 0xFFFF;
+ }
+ retval = bswap16(retval);
+ return retval;
+}
+
+static void pmac_ide_writel (void *opaque,
+ hwaddr addr, uint32_t val)
+{
+ MACIOIDEState *d = opaque;
+
+ addr = (addr & 0xFFF) >> 4;
+ val = bswap32(val);
+ if (addr == 0) {
+ ide_data_writel(&d->bus, 0, val);
+ }
+}
+
+static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
+{
+ uint32_t retval;
+ MACIOIDEState *d = opaque;
+
+ addr = (addr & 0xFFF) >> 4;
+ if (addr == 0) {
+ retval = ide_data_readl(&d->bus, 0);
+ } else {
+ retval = 0xFFFFFFFF;
+ }
+ retval = bswap32(retval);
+ return retval;
+}
+
+static const MemoryRegionOps pmac_ide_ops = {
+ .old_mmio = {
+ .write = {
+ pmac_ide_writeb,
+ pmac_ide_writew,
+ pmac_ide_writel,
+ },
+ .read = {
+ pmac_ide_readb,
+ pmac_ide_readw,
+ pmac_ide_readl,
+ },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription vmstate_pmac = {
+ .name = "ide",
+ .version_id = 3,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_IDE_BUS(bus, MACIOIDEState),
+ VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void macio_ide_reset(DeviceState *dev)
+{
+ MACIOIDEState *d = MACIO_IDE(dev);
+
+ ide_bus_reset(&d->bus);
+}
+
+static int ide_nop_int(IDEDMA *dma, int x)
+{
+ return 0;
+}
+
+static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
+{
+ return 0;
+}
+
+static void ide_dbdma_start(IDEDMA *dma, IDEState *s,
+ BlockCompletionFunc *cb)
+{
+ MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
+
+ s->io_buffer_index = 0;
+ if (s->drive_kind == IDE_CD) {
+ s->io_buffer_size = s->packet_transfer_size;
+ } else {
+ s->io_buffer_size = s->nsector * BDRV_SECTOR_SIZE;
+ }
+
+ MACIO_DPRINTF("\n\n------------ IDE transfer\n");
+ MACIO_DPRINTF("buffer_size: %x buffer_index: %x\n",
+ s->io_buffer_size, s->io_buffer_index);
+ MACIO_DPRINTF("lba: %x size: %x\n", s->lba, s->io_buffer_size);
+ MACIO_DPRINTF("-------------------------\n");
+
+ m->dma_active = true;
+ DBDMA_kick(m->dbdma);
+}
+
+static const IDEDMAOps dbdma_ops = {
+ .start_dma = ide_dbdma_start,
+ .prepare_buf = ide_nop_int32,
+ .rw_buf = ide_nop_int,
+};
+
+static void macio_ide_realizefn(DeviceState *dev, Error **errp)
+{
+ MACIOIDEState *s = MACIO_IDE(dev);
+
+ ide_init2(&s->bus, s->irq);
+
+ /* Register DMA callbacks */
+ s->dma.ops = &dbdma_ops;
+ s->bus.dma = &s->dma;
+}
+
+static void macio_ide_initfn(Object *obj)
+{
+ SysBusDevice *d = SYS_BUS_DEVICE(obj);
+ MACIOIDEState *s = MACIO_IDE(obj);
+
+ ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
+ memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
+ sysbus_init_mmio(d, &s->mem);
+ sysbus_init_irq(d, &s->irq);
+ sysbus_init_irq(d, &s->dma_irq);
+}
+
+static void macio_ide_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = macio_ide_realizefn;
+ dc->reset = macio_ide_reset;
+ dc->vmsd = &vmstate_pmac;
+ set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
+}
+
+static const TypeInfo macio_ide_type_info = {
+ .name = TYPE_MACIO_IDE,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MACIOIDEState),
+ .instance_init = macio_ide_initfn,
+ .class_init = macio_ide_class_init,
+};
+
+static void macio_ide_register_types(void)
+{
+ type_register_static(&macio_ide_type_info);
+}
+
+/* hd_table must contain 2 block drivers */
+void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
+{
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ if (hd_table[i]) {
+ ide_create_drive(&s->bus, i, hd_table[i]);
+ }
+ }
+}
+
+void macio_ide_register_dma(MACIOIDEState *s, void *dbdma, int channel)
+{
+ s->dbdma = dbdma;
+ DBDMA_register_channel(dbdma, channel, s->dma_irq,
+ pmac_ide_transfer, pmac_ide_flush, s);
+}
+
+type_init(macio_ide_register_types)
diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h
index e375ed2..ecf7792 100644
--- a/hw/ppc/mac.h
+++ b/hw/ppc/mac.h
@@ -134,7 +134,6 @@ typedef struct MACIOIDEState {
MemoryRegion mem;
IDEBus bus;
- BlockAIOCB *aiocb;
IDEDMA dma;
void *dbdma;
bool dma_active;
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 04/28] macio: add dma_active to VMStateDescription
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (2 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 03/28] macio: use the existing IDEDMA aiocb to hold the active DMA aiocb David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 05/28] mac_dbdma: add DBDMA controller state " David Gibson
` (24 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Make sure that we include the value of dma_active in the migration stream.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: John Snow <jsnow@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ide/macio.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index 110af46..a39bdc0 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -516,11 +516,12 @@ static const MemoryRegionOps pmac_ide_ops = {
static const VMStateDescription vmstate_pmac = {
.name = "ide",
- .version_id = 3,
+ .version_id = 4,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_IDE_BUS(bus, MACIOIDEState),
VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
+ VMSTATE_BOOL(dma_active, MACIOIDEState),
VMSTATE_END_OF_LIST()
}
};
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 05/28] mac_dbdma: add DBDMA controller state to VMStateDescription
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (3 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 04/28] macio: add dma_active to VMStateDescription David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 06/28] cuda: add missing fields " David Gibson
` (23 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Make sure that we include the DBDMA controller state in the migration
stream.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/misc/macio/mac_dbdma.c | 40 ++++++++++++++++++++++++++++++++++++----
1 file changed, 36 insertions(+), 4 deletions(-)
diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c
index 5ee8f02..161f49e 100644
--- a/hw/misc/macio/mac_dbdma.c
+++ b/hw/misc/macio/mac_dbdma.c
@@ -712,20 +712,52 @@ static const MemoryRegionOps dbdma_ops = {
},
};
-static const VMStateDescription vmstate_dbdma_channel = {
- .name = "dbdma_channel",
+static const VMStateDescription vmstate_dbdma_io = {
+ .name = "dbdma_io",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(addr, struct DBDMA_io),
+ VMSTATE_INT32(len, struct DBDMA_io),
+ VMSTATE_INT32(is_last, struct DBDMA_io),
+ VMSTATE_INT32(is_dma_out, struct DBDMA_io),
+ VMSTATE_BOOL(processing, struct DBDMA_io),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_dbdma_cmd = {
+ .name = "dbdma_cmd",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
+ VMSTATE_UINT16(req_count, dbdma_cmd),
+ VMSTATE_UINT16(command, dbdma_cmd),
+ VMSTATE_UINT32(phy_addr, dbdma_cmd),
+ VMSTATE_UINT32(cmd_dep, dbdma_cmd),
+ VMSTATE_UINT16(res_count, dbdma_cmd),
+ VMSTATE_UINT16(xfer_status, dbdma_cmd),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_dbdma_channel = {
+ .name = "dbdma_channel",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, struct DBDMA_channel, DBDMA_REGS),
+ VMSTATE_STRUCT(io, struct DBDMA_channel, 0, vmstate_dbdma_io, DBDMA_io),
+ VMSTATE_STRUCT(current, struct DBDMA_channel, 0, vmstate_dbdma_cmd,
+ dbdma_cmd),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_dbdma = {
.name = "dbdma",
- .version_id = 2,
- .minimum_version_id = 2,
+ .version_id = 3,
+ .minimum_version_id = 3,
.fields = (VMStateField[]) {
VMSTATE_STRUCT_ARRAY(channels, DBDMAState, DBDMA_CHANNELS, 1,
vmstate_dbdma_channel, DBDMA_channel),
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 06/28] cuda: add missing fields to VMStateDescription
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (4 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 05/28] mac_dbdma: add DBDMA controller state " David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 07/28] spapr: Small fixes to rtas_ibm_get_system_parameter, remove rtas_st_buffer David Gibson
` (22 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Include some fields missed from the previous VMState conversion to the
migration stream, as well as the new SR_INT delay timer.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/misc/macio/cuda.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c
index 9db4c64..3556852 100644
--- a/hw/misc/macio/cuda.c
+++ b/hw/misc/macio/cuda.c
@@ -704,15 +704,17 @@ static const VMStateDescription vmstate_cuda_timer = {
static const VMStateDescription vmstate_cuda = {
.name = "cuda",
- .version_id = 2,
- .minimum_version_id = 2,
+ .version_id = 3,
+ .minimum_version_id = 3,
.fields = (VMStateField[]) {
VMSTATE_UINT8(a, CUDAState),
VMSTATE_UINT8(b, CUDAState),
+ VMSTATE_UINT8(last_b, CUDAState),
VMSTATE_UINT8(dira, CUDAState),
VMSTATE_UINT8(dirb, CUDAState),
VMSTATE_UINT8(sr, CUDAState),
VMSTATE_UINT8(acr, CUDAState),
+ VMSTATE_UINT8(last_acr, CUDAState),
VMSTATE_UINT8(pcr, CUDAState),
VMSTATE_UINT8(ifr, CUDAState),
VMSTATE_UINT8(ier, CUDAState),
@@ -727,6 +729,7 @@ static const VMStateDescription vmstate_cuda = {
VMSTATE_STRUCT_ARRAY(timers, CUDAState, 2, 1,
vmstate_cuda_timer, CUDATimer),
VMSTATE_TIMER_PTR(adb_poll_timer, CUDAState),
+ VMSTATE_TIMER_PTR(sr_delay_timer, CUDAState),
VMSTATE_END_OF_LIST()
}
};
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 07/28] spapr: Small fixes to rtas_ibm_get_system_parameter, remove rtas_st_buffer
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (5 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 06/28] cuda: add missing fields " David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 08/28] spapr: Remove rtas_st_buffer_direct() David Gibson
` (21 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
rtas_st_buffer() appears in spapr.h as though it were a widely used helper,
but in fact it is only used for saving data in a format used by
rtas_ibm_get_system_parameter(). This changes it to a local helper more
specifically for that function.
While we're there fix a couple of small defects in
rtas_ibm_get_system_parameter:
- For the string value SPLPAR_CHARACTERISTICS, it wasn't including the
terminating \0 in the length which it should according to LoPAPR
7.3.16.1
- It now checks that the supplied buffer has at least enough space for
the length of the returned data, and returns an error if it does not.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
hw/ppc/spapr_rtas.c | 21 +++++++++++++++++----
include/hw/ppc/spapr.h | 28 +++++++++-------------------
2 files changed, 26 insertions(+), 23 deletions(-)
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index 34b12a3..8b702b5 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -228,6 +228,19 @@ static void rtas_stop_self(PowerPCCPU *cpu, sPAPRMachineState *spapr,
env->msr = 0;
}
+static inline int sysparm_st(target_ulong addr, target_ulong len,
+ const void *val, uint16_t vallen)
+{
+ hwaddr phys = ppc64_phys_to_real(addr);
+
+ if (len < 2) {
+ return RTAS_OUT_SYSPARM_PARAM_ERROR;
+ }
+ stw_be_phys(&address_space_memory, phys, vallen);
+ cpu_physical_memory_write(phys + 2, val, MIN(len - 2, vallen));
+ return RTAS_OUT_SUCCESS;
+}
+
static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu,
sPAPRMachineState *spapr,
uint32_t token, uint32_t nargs,
@@ -237,7 +250,7 @@ static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu,
target_ulong parameter = rtas_ld(args, 0);
target_ulong buffer = rtas_ld(args, 1);
target_ulong length = rtas_ld(args, 2);
- target_ulong ret = RTAS_OUT_SUCCESS;
+ target_ulong ret;
switch (parameter) {
case RTAS_SYSPARM_SPLPAR_CHARACTERISTICS: {
@@ -249,18 +262,18 @@ static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu,
current_machine->ram_size / M_BYTE,
smp_cpus,
max_cpus);
- rtas_st_buffer(buffer, length, (uint8_t *)param_val, strlen(param_val));
+ ret = sysparm_st(buffer, length, param_val, strlen(param_val) + 1);
g_free(param_val);
break;
}
case RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE: {
uint8_t param_val = DIAGNOSTICS_RUN_MODE_DISABLED;
- rtas_st_buffer(buffer, length, ¶m_val, sizeof(param_val));
+ ret = sysparm_st(buffer, length, ¶m_val, sizeof(param_val));
break;
}
case RTAS_SYSPARM_UUID:
- rtas_st_buffer(buffer, length, qemu_uuid, (qemu_uuid_set ? 16 : 0));
+ ret = sysparm_st(buffer, length, qemu_uuid, (qemu_uuid_set ? 16 : 0));
break;
default:
ret = RTAS_OUT_NOT_SUPPORTED;
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 53af76a..1e10fc9 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -408,14 +408,15 @@ int spapr_allocate_irq_block(int num, bool lsi, bool msi);
#define RTAS_SLOT_PERM_ERR_LOG 2
/* RTAS return codes */
-#define RTAS_OUT_SUCCESS 0
-#define RTAS_OUT_NO_ERRORS_FOUND 1
-#define RTAS_OUT_HW_ERROR -1
-#define RTAS_OUT_BUSY -2
-#define RTAS_OUT_PARAM_ERROR -3
-#define RTAS_OUT_NOT_SUPPORTED -3
-#define RTAS_OUT_NO_SUCH_INDICATOR -3
-#define RTAS_OUT_NOT_AUTHORIZED -9002
+#define RTAS_OUT_SUCCESS 0
+#define RTAS_OUT_NO_ERRORS_FOUND 1
+#define RTAS_OUT_HW_ERROR -1
+#define RTAS_OUT_BUSY -2
+#define RTAS_OUT_PARAM_ERROR -3
+#define RTAS_OUT_NOT_SUPPORTED -3
+#define RTAS_OUT_NO_SUCH_INDICATOR -3
+#define RTAS_OUT_NOT_AUTHORIZED -9002
+#define RTAS_OUT_SYSPARM_PARAM_ERROR -9999
/* RTAS tokens */
#define RTAS_TOKEN_BASE 0x2000
@@ -513,17 +514,6 @@ static inline void rtas_st_buffer_direct(target_ulong phys,
MIN(buffer_len, phys_len));
}
-static inline void rtas_st_buffer(target_ulong phys, target_ulong phys_len,
- uint8_t *buffer, uint16_t buffer_len)
-{
- if (phys_len < 2) {
- return;
- }
- stw_be_phys(&address_space_memory,
- ppc64_phys_to_real(phys), buffer_len);
- rtas_st_buffer_direct(phys + 2, phys_len - 2, buffer, buffer_len);
-}
-
typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
uint32_t token,
uint32_t nargs, target_ulong args,
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 08/28] spapr: Remove rtas_st_buffer_direct()
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (6 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 07/28] spapr: Small fixes to rtas_ibm_get_system_parameter, remove rtas_st_buffer David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 09/28] spapr: Remove abuse of rtas_ld() in h_client_architecture_support David Gibson
` (20 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
rtas_st_buffer_direct() is a not particularly useful wrapper around
cpu_physical_memory_write(). All the callers are in
rtas_ibm_configure_connector, where it's better handled by local helper.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
hw/ppc/spapr_rtas.c | 17 ++++++++++-------
include/hw/ppc/spapr.h | 8 --------
2 files changed, 10 insertions(+), 15 deletions(-)
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index 8b702b5..eac1556 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -505,6 +505,13 @@ out:
#define CC_VAL_DATA_OFFSET ((CC_IDX_PROP_DATA_OFFSET + 1) * 4)
#define CC_WA_LEN 4096
+static void configure_connector_st(target_ulong addr, target_ulong offset,
+ const void *buf, size_t len)
+{
+ cpu_physical_memory_write(ppc64_phys_to_real(addr + offset),
+ buf, MIN(len, CC_WA_LEN - offset));
+}
+
static void rtas_ibm_configure_connector(PowerPCCPU *cpu,
sPAPRMachineState *spapr,
uint32_t token, uint32_t nargs,
@@ -570,8 +577,7 @@ static void rtas_ibm_configure_connector(PowerPCCPU *cpu,
/* provide the name of the next OF node */
wa_offset = CC_VAL_DATA_OFFSET;
rtas_st(wa_addr, CC_IDX_NODE_NAME_OFFSET, wa_offset);
- rtas_st_buffer_direct(wa_addr + wa_offset, CC_WA_LEN - wa_offset,
- (uint8_t *)name, strlen(name) + 1);
+ configure_connector_st(wa_addr, wa_offset, name, strlen(name) + 1);
resp = SPAPR_DR_CC_RESPONSE_NEXT_CHILD;
break;
case FDT_END_NODE:
@@ -596,8 +602,7 @@ static void rtas_ibm_configure_connector(PowerPCCPU *cpu,
/* provide the name of the next OF property */
wa_offset = CC_VAL_DATA_OFFSET;
rtas_st(wa_addr, CC_IDX_PROP_NAME_OFFSET, wa_offset);
- rtas_st_buffer_direct(wa_addr + wa_offset, CC_WA_LEN - wa_offset,
- (uint8_t *)name, strlen(name) + 1);
+ configure_connector_st(wa_addr, wa_offset, name, strlen(name) + 1);
/* provide the length and value of the OF property. data gets
* placed immediately after NULL terminator of the OF property's
@@ -606,9 +611,7 @@ static void rtas_ibm_configure_connector(PowerPCCPU *cpu,
wa_offset += strlen(name) + 1,
rtas_st(wa_addr, CC_IDX_PROP_LEN, prop_len);
rtas_st(wa_addr, CC_IDX_PROP_DATA_OFFSET, wa_offset);
- rtas_st_buffer_direct(wa_addr + wa_offset, CC_WA_LEN - wa_offset,
- (uint8_t *)((struct fdt_property *)prop)->data,
- prop_len);
+ configure_connector_st(wa_addr, wa_offset, prop->data, prop_len);
resp = SPAPR_DR_CC_RESPONSE_NEXT_PROPERTY;
break;
case FDT_END:
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 1e10fc9..1f9e722 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -506,14 +506,6 @@ static inline void rtas_st(target_ulong phys, int n, uint32_t val)
stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
}
-static inline void rtas_st_buffer_direct(target_ulong phys,
- target_ulong phys_len,
- uint8_t *buffer, uint16_t buffer_len)
-{
- cpu_physical_memory_write(ppc64_phys_to_real(phys), buffer,
- MIN(buffer_len, phys_len));
-}
-
typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
uint32_t token,
uint32_t nargs, target_ulong args,
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 09/28] spapr: Remove abuse of rtas_ld() in h_client_architecture_support
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (7 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 08/28] spapr: Remove rtas_st_buffer_direct() David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 10/28] spapr: Don't create ibm, dynamic-reconfiguration-memory w/o DR LMBs David Gibson
` (19 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
h_client_architecture_support() uses rtas_ld() for general purpose memory
access, despite the fact that it's not an RTAS routine at all and rtas_ld
makes things more awkward.
Clean this up by replacing rtas_ld() calls with appropriate ldXX_phys()
calls.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
hw/ppc/spapr_hcall.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index cebceea..9dbdba9 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -861,7 +861,8 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu_,
target_ulong opcode,
target_ulong *args)
{
- target_ulong list = args[0], ov_table;
+ target_ulong list = ppc64_phys_to_real(args[0]);
+ target_ulong ov_table, ov5;
PowerPCCPUClass *pcc_ = POWERPC_CPU_GET_CLASS(cpu_);
CPUState *cs;
bool cpu_match = false, cpu_update = true, memory_update = false;
@@ -875,9 +876,9 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu_,
for (counter = 0; counter < 512; ++counter) {
uint32_t pvr, pvr_mask;
- pvr_mask = rtas_ld(list, 0);
+ pvr_mask = ldl_be_phys(&address_space_memory, list);
list += 4;
- pvr = rtas_ld(list, 0);
+ pvr = ldl_be_phys(&address_space_memory, list);
list += 4;
trace_spapr_cas_pvr_try(pvr);
@@ -948,14 +949,13 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu_,
/* For the future use: here @ov_table points to the first option vector */
ov_table = list;
- list = cas_get_option_vector(5, ov_table);
- if (!list) {
+ ov5 = cas_get_option_vector(5, ov_table);
+ if (!ov5) {
return H_SUCCESS;
}
/* @list now points to OV 5 */
- list += 2;
- ov5_byte2 = rtas_ld(list, 0) >> 24;
+ ov5_byte2 = ldub_phys(&address_space_memory, ov5 + 2);
if (ov5_byte2 & OV5_DRCONF_MEMORY) {
memory_update = true;
}
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 10/28] spapr: Don't create ibm, dynamic-reconfiguration-memory w/o DR LMBs
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (8 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 09/28] spapr: Remove abuse of rtas_ld() in h_client_architecture_support David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 11/28] ppc: Clean up error handling in ppc_set_compat() David Gibson
` (18 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
If guest doesn't have any dynamically reconfigurable (DR) logical memory
blocks (LMB), then we shouldn't create ibm,dynamic-reconfiguration-memory
device tree node.
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 50e5a26..86e5023 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -763,6 +763,13 @@ static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
/*
+ * Don't create the node if there are no DR LMBs.
+ */
+ if (!nr_lmbs) {
+ return 0;
+ }
+
+ /*
* Allocate enough buffer size to fit in ibm,dynamic-memory
* or ibm,associativity-lookup-arrays
*/
@@ -868,7 +875,7 @@ int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
_FDT((spapr_fixup_cpu_dt(fdt, spapr)));
}
- /* Generate memory nodes or ibm,dynamic-reconfiguration-memory node */
+ /* Generate ibm,dynamic-reconfiguration-memory node if required */
if (memory_update && smc->dr_lmb_enabled) {
_FDT((spapr_populate_drconf_memory(spapr, fdt)));
}
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 11/28] ppc: Clean up error handling in ppc_set_compat()
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (9 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 10/28] spapr: Don't create ibm, dynamic-reconfiguration-memory w/o DR LMBs David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 12/28] pseries: Clean up error handling of spapr_cpu_init() David Gibson
` (17 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
Current ppc_set_compat() returns -1 for errors, and also (unconditionally)
reports an error message. The caller in h_client_architecture_support()
may then report it again using an outdated fprintf().
Clean this up by using the modern error reporting mechanisms. Also add
strerror(errno) to the error message.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
---
hw/ppc/spapr.c | 4 +---
hw/ppc/spapr_hcall.c | 10 +++++-----
target-ppc/cpu.h | 2 +-
target-ppc/translate_init.c | 13 +++++++------
4 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 86e5023..672815f 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1642,9 +1642,7 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu)
}
if (cpu->max_compat) {
- if (ppc_set_compat(cpu, cpu->max_compat) < 0) {
- exit(1);
- }
+ ppc_set_compat(cpu, cpu->max_compat, &error_fatal);
}
xics_cpu_setup(spapr->icp, cpu);
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 9dbdba9..e9c057d 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -837,7 +837,7 @@ static target_ulong cas_get_option_vector(int vector, target_ulong table)
typedef struct {
PowerPCCPU *cpu;
uint32_t cpu_version;
- int ret;
+ Error *err;
} SetCompatState;
static void do_set_compat(void *arg)
@@ -845,7 +845,7 @@ static void do_set_compat(void *arg)
SetCompatState *s = arg;
cpu_synchronize_state(CPU(s->cpu));
- s->ret = ppc_set_compat(s->cpu, s->cpu_version);
+ ppc_set_compat(s->cpu, s->cpu_version, &s->err);
}
#define get_compat_level(cpuver) ( \
@@ -930,13 +930,13 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu_,
SetCompatState s = {
.cpu = POWERPC_CPU(cs),
.cpu_version = cpu_version,
- .ret = 0
+ .err = NULL,
};
run_on_cpu(cs, do_set_compat, &s);
- if (s.ret < 0) {
- fprintf(stderr, "Unable to set compatibility mode\n");
+ if (s.err) {
+ error_report_err(s.err);
return H_HARDWARE;
}
}
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 9706000..b3b89e6 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1210,7 +1210,7 @@ void ppc_store_msr (CPUPPCState *env, target_ulong value);
void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
int ppc_get_compat_smt_threads(PowerPCCPU *cpu);
-int ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version);
+void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp);
/* Time-base and decrementer management */
#ifndef NO_CPU_IO_DEFS
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 4ab2d92..678957a 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -9186,7 +9186,7 @@ int ppc_get_compat_smt_threads(PowerPCCPU *cpu)
return ret;
}
-int ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version)
+void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp)
{
int ret = 0;
CPUPPCState *env = &cpu->env;
@@ -9208,12 +9208,13 @@ int ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version)
break;
}
- if (kvm_enabled() && kvmppc_set_compat(cpu, cpu->cpu_version) < 0) {
- error_report("Unable to set compatibility mode in KVM");
- ret = -1;
+ if (kvm_enabled()) {
+ ret = kvmppc_set_compat(cpu, cpu->cpu_version);
+ if (ret < 0) {
+ error_setg_errno(errp, -ret,
+ "Unable to set CPU compatibility mode in KVM");
+ }
}
-
- return ret;
}
static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 12/28] pseries: Clean up error handling of spapr_cpu_init()
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (10 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 11/28] ppc: Clean up error handling in ppc_set_compat() David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 13/28] pseries: Clean up error handling in spapr_validate_node_memory() David Gibson
` (16 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
Currently spapr_cpu_init() is hardcoded to handle any errors as fatal.
That works for now, since it's only called from initial setup where an
error here means we really can't proceed.
However, we'll want to handle this more flexibly for cpu hotplug in future
so generalize this using the error reporting infrastructure. While we're
at it make a small cleanup in a related part of ppc_spapr_init() to use
error_report() instead of an old-style explicit fprintf().
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
---
hw/ppc/spapr.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 672815f..447fa5d 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1624,7 +1624,8 @@ static void spapr_boot_set(void *opaque, const char *boot_device,
machine->boot_order = g_strdup(boot_device);
}
-static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu)
+static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
+ Error **errp)
{
CPUPPCState *env = &cpu->env;
@@ -1642,7 +1643,13 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu)
}
if (cpu->max_compat) {
- ppc_set_compat(cpu, cpu->max_compat, &error_fatal);
+ Error *local_err = NULL;
+
+ ppc_set_compat(cpu, cpu->max_compat, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
}
xics_cpu_setup(spapr->icp, cpu);
@@ -1811,10 +1818,10 @@ static void ppc_spapr_init(MachineState *machine)
for (i = 0; i < smp_cpus; i++) {
cpu = cpu_ppc_init(machine->cpu_model);
if (cpu == NULL) {
- fprintf(stderr, "Unable to find PowerPC CPU definition\n");
+ error_report("Unable to find PowerPC CPU definition");
exit(1);
}
- spapr_cpu_init(spapr, cpu);
+ spapr_cpu_init(spapr, cpu, &error_fatal);
}
if (kvm_enabled()) {
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 13/28] pseries: Clean up error handling in spapr_validate_node_memory()
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (11 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 12/28] pseries: Clean up error handling of spapr_cpu_init() David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 14/28] pseries: Clean up error handling in spapr_vga_init() David Gibson
` (15 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
Use error_setg() and return an error, rather than using an explicit exit().
Also improve messages, and be more explicit about which constraint failed.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
---
hw/ppc/spapr.c | 37 ++++++++++++++++++++++---------------
1 file changed, 22 insertions(+), 15 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 447fa5d..5793205 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1698,27 +1698,34 @@ static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
* to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
* since we can't support such unaligned sizes with DRCONF_MEMORY.
*/
-static void spapr_validate_node_memory(MachineState *machine)
+static void spapr_validate_node_memory(MachineState *machine, Error **errp)
{
int i;
- if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE ||
- machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
- error_report("Can't support memory configuration where RAM size "
- "0x" RAM_ADDR_FMT " or maxmem size "
- "0x" RAM_ADDR_FMT " isn't aligned to %llu MB",
- machine->ram_size, machine->maxram_size,
- SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
- exit(EXIT_FAILURE);
+ if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
+ error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
+ " is not aligned to %llu MiB",
+ machine->ram_size,
+ SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
+ return;
+ }
+
+ if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
+ error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
+ " is not aligned to %llu MiB",
+ machine->ram_size,
+ SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
+ return;
}
for (i = 0; i < nb_numa_nodes; i++) {
if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
- error_report("Can't support memory configuration where memory size"
- " %" PRIx64 " of node %d isn't aligned to %llu MB",
- numa_info[i].node_mem, i,
- SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
- exit(EXIT_FAILURE);
+ error_setg(errp,
+ "Node %d memory size 0x" RAM_ADDR_FMT
+ " is not aligned to %llu MiB",
+ i, numa_info[i].node_mem,
+ SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
+ return;
}
}
}
@@ -1808,7 +1815,7 @@ static void ppc_spapr_init(MachineState *machine)
XICS_IRQS);
if (smc->dr_lmb_enabled) {
- spapr_validate_node_memory(machine);
+ spapr_validate_node_memory(machine, &error_fatal);
}
/* init CPUs */
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 14/28] pseries: Clean up error handling in spapr_vga_init()
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (12 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 13/28] pseries: Clean up error handling in spapr_validate_node_memory() David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 15/28] pseries: Clean up error handling in spapr_rtas_register() David Gibson
` (14 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
Use error_setg() to return an error rather than an explicit exit().
Previously it was an exit(0) instead of a non-zero exit code, which was
simply a bug. Also improve the error message.
While we're at it change the type of spapr_vga_init() to bool since that's
how we're using it anyway.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
---
hw/ppc/spapr.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 5793205..c04666d 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1245,7 +1245,7 @@ static void spapr_rtc_create(sPAPRMachineState *spapr)
}
/* Returns whether we want to use VGA or not */
-static int spapr_vga_init(PCIBus *pci_bus)
+static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
{
switch (vga_interface_type) {
case VGA_NONE:
@@ -1256,9 +1256,9 @@ static int spapr_vga_init(PCIBus *pci_bus)
case VGA_VIRTIO:
return pci_vga_init(pci_bus) != NULL;
default:
- fprintf(stderr, "This vga model is not supported,"
- "currently it only supports -vga std\n");
- exit(0);
+ error_setg(errp,
+ "Unsupported VGA mode, only -vga std or -vga virtio is supported");
+ return false;
}
}
@@ -1933,7 +1933,7 @@ static void ppc_spapr_init(MachineState *machine)
}
/* Graphics */
- if (spapr_vga_init(phb->bus)) {
+ if (spapr_vga_init(phb->bus, &error_fatal)) {
spapr->has_graphics = true;
machine->usb |= defaults_enabled() && !machine->usb_disabled;
}
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 15/28] pseries: Clean up error handling in spapr_rtas_register()
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (13 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 14/28] pseries: Clean up error handling in spapr_vga_init() David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 16/28] pseries: Clean up error handling in xics_system_init() David Gibson
` (13 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
The errors detected in this function necessarily indicate bugs in the rest
of the qemu code, rather than an external or configuration problem.
So, a simple assert() is more appropriate than any more complex error
reporting.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
---
hw/ppc/spapr_rtas.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index eac1556..130c917 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -664,17 +664,11 @@ target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *spapr,
void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn)
{
- if (!((token >= RTAS_TOKEN_BASE) && (token < RTAS_TOKEN_MAX))) {
- fprintf(stderr, "RTAS invalid token 0x%x\n", token);
- exit(1);
- }
+ assert((token >= RTAS_TOKEN_BASE) && (token < RTAS_TOKEN_MAX));
token -= RTAS_TOKEN_BASE;
- if (rtas_table[token].name) {
- fprintf(stderr, "RTAS call \"%s\" is registered already as 0x%x\n",
- rtas_table[token].name, token);
- exit(1);
- }
+
+ assert(!rtas_table[token].name);
rtas_table[token].name = name;
rtas_table[token].fn = fn;
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 16/28] pseries: Clean up error handling in xics_system_init()
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (14 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 15/28] pseries: Clean up error handling in spapr_rtas_register() David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 17/28] pseries: Clean up error reporting in ppc_spapr_init() David Gibson
` (12 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
Use the error handling infrastructure to pass an error out from
try_create_xics() instead of assuming &error_abort - the caller is in a
better position to decide on error handling policy.
Also change the error handling from an &error_abort to &error_fatal, since
this occurs during the initial machine construction and could be triggered
by bad configuration rather than a program error.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
---
hw/ppc/spapr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index c04666d..b93dc10 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -111,7 +111,7 @@ static XICSState *try_create_xics(const char *type, int nr_servers,
}
static XICSState *xics_system_init(MachineState *machine,
- int nr_servers, int nr_irqs)
+ int nr_servers, int nr_irqs, Error **errp)
{
XICSState *icp = NULL;
@@ -130,7 +130,7 @@ static XICSState *xics_system_init(MachineState *machine,
}
if (!icp) {
- icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, &error_abort);
+ icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, errp);
}
return icp;
@@ -1812,7 +1812,7 @@ static void ppc_spapr_init(MachineState *machine)
spapr->icp = xics_system_init(machine,
DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(),
smp_threads),
- XICS_IRQS);
+ XICS_IRQS, &error_fatal);
if (smc->dr_lmb_enabled) {
spapr_validate_node_memory(machine, &error_fatal);
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 17/28] pseries: Clean up error reporting in ppc_spapr_init()
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (15 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 16/28] pseries: Clean up error handling in xics_system_init() David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 18/28] pseries: Clean up error reporting in htab migration functions David Gibson
` (11 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
This function includes a number of explicit fprintf()s for errors.
Change these to use error_report() instead.
Also replace the single exit(EXIT_FAILURE) with an explicit exit(1), since
the latter is the more usual idiom in qemu by a large margin.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
---
hw/ppc/spapr.c | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index b93dc10..4d88a29 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1788,8 +1788,8 @@ static void ppc_spapr_init(MachineState *machine)
}
if (spapr->rma_size > node0_size) {
- fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n",
- spapr->rma_size);
+ error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
+ spapr->rma_size);
exit(1);
}
@@ -1855,10 +1855,10 @@ static void ppc_spapr_init(MachineState *machine)
ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
if (machine->ram_slots > SPAPR_MAX_RAM_SLOTS) {
- error_report("Specified number of memory slots %" PRIu64
- " exceeds max supported %d",
+ error_report("Specified number of memory slots %"
+ PRIu64" exceeds max supported %d",
machine->ram_slots, SPAPR_MAX_RAM_SLOTS);
- exit(EXIT_FAILURE);
+ exit(1);
}
spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
@@ -1954,8 +1954,9 @@ static void ppc_spapr_init(MachineState *machine)
}
if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
- fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
- "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF);
+ error_report(
+ "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
+ MIN_RMA_SLOF);
exit(1);
}
@@ -1971,8 +1972,8 @@ static void ppc_spapr_init(MachineState *machine)
kernel_le = kernel_size > 0;
}
if (kernel_size < 0) {
- fprintf(stderr, "qemu: error loading %s: %s\n",
- kernel_filename, load_elf_strerror(kernel_size));
+ error_report("error loading %s: %s",
+ kernel_filename, load_elf_strerror(kernel_size));
exit(1);
}
@@ -1985,8 +1986,8 @@ static void ppc_spapr_init(MachineState *machine)
initrd_size = load_image_targphys(initrd_filename, initrd_base,
load_limit - initrd_base);
if (initrd_size < 0) {
- fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
- initrd_filename);
+ error_report("could not load initial ram disk '%s'",
+ initrd_filename);
exit(1);
}
} else {
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 18/28] pseries: Clean up error reporting in htab migration functions
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (16 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 17/28] pseries: Clean up error reporting in ppc_spapr_init() David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 19/28] target-ppc: kvm: fix floating point registers sync on little-endian hosts David Gibson
` (10 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
The functions for migrating the hash page table on pseries machine type
(htab_save_setup() and htab_load()) can report some errors with an
explicit fprintf() before returning an appropriate error code. Change some
of these to use error_report() instead. htab_save_setup() is omitted for
now to avoid conflicts with some other in-progress work.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
---
hw/ppc/spapr.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 4d88a29..5df9274 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1533,7 +1533,7 @@ static int htab_load(QEMUFile *f, void *opaque, int version_id)
int fd = -1;
if (version_id < 1 || version_id > 1) {
- fprintf(stderr, "htab_load() bad version\n");
+ error_report("htab_load() bad version");
return -EINVAL;
}
@@ -1554,8 +1554,8 @@ static int htab_load(QEMUFile *f, void *opaque, int version_id)
fd = kvmppc_get_htab_fd(true);
if (fd < 0) {
- fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n",
- strerror(errno));
+ error_report("Unable to open fd to restore KVM hash table: %s",
+ strerror(errno));
}
}
@@ -1575,9 +1575,9 @@ static int htab_load(QEMUFile *f, void *opaque, int version_id)
if ((index + n_valid + n_invalid) >
(HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
/* Bad index in stream */
- fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) "
- "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid,
- spapr->htab_shift);
+ error_report(
+ "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
+ index, n_valid, n_invalid, spapr->htab_shift);
return -EINVAL;
}
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 19/28] target-ppc: kvm: fix floating point registers sync on little-endian hosts
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (17 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 18/28] pseries: Clean up error reporting in htab migration functions David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 20/28] target-ppc: rename and export maybe_bswap_register() David Gibson
` (9 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
From: Greg Kurz <gkurz@linux.vnet.ibm.com>
On VSX capable CPUs, the 32 FP registers are mapped to the high-bits
of the 32 first VSX registers. So if you have:
VSR31 = (uint128) 0x0102030405060708090a0b0c0d0e0f00
then
FPR31 = (uint64) 0x0102030405060708
The kernel stores the VSX registers in the fp_state struct following the
host endian element ordering.
On big-endian:
fp_state.fpr[31][0] = 0x0102030405060708
fp_state.fpr[31][1] = 0x090a0b0c0d0e0f00
On little-endian:
fp_state.fpr[31][0] = 0x090a0b0c0d0e0f00
fp_state.fpr[31][1] = 0x0102030405060708
The KVM_GET_ONE_REG and KVM_SET_ONE_REG ioctls preserve this ordering, but
QEMU considers it as big-endian and always copies element [0] to the
fpr[] array and element [1] to the vsr[] array. This does not work with
little-endian hosts, and you will get:
(qemu) p $f31
0x90a0b0c0d0e0f00
instead of:
(qemu) p $f31
0x102030405060708
This patch fixes the element ordering for little-endian hosts.
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/kvm.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 9940a90..4524999 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -650,8 +650,13 @@ static int kvm_put_fp(CPUState *cs)
for (i = 0; i < 32; i++) {
uint64_t vsr[2];
+#ifdef HOST_WORDS_BIGENDIAN
vsr[0] = float64_val(env->fpr[i]);
vsr[1] = env->vsr[i];
+#else
+ vsr[0] = env->vsr[i];
+ vsr[1] = float64_val(env->fpr[i]);
+#endif
reg.addr = (uintptr_t) &vsr;
reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
@@ -721,10 +726,17 @@ static int kvm_get_fp(CPUState *cs)
vsx ? "VSR" : "FPR", i, strerror(errno));
return ret;
} else {
+#ifdef HOST_WORDS_BIGENDIAN
env->fpr[i] = vsr[0];
if (vsx) {
env->vsr[i] = vsr[1];
}
+#else
+ env->fpr[i] = vsr[1];
+ if (vsx) {
+ env->vsr[i] = vsr[0];
+ }
+#endif
}
}
}
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 20/28] target-ppc: rename and export maybe_bswap_register()
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (18 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 19/28] target-ppc: kvm: fix floating point registers sync on little-endian hosts David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 21/28] target-ppc: gdbstub: fix float registers for little-endian guests David Gibson
` (8 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
From: Greg Kurz <gkurz@linux.vnet.ibm.com>
This helper will be used to support FP, Altivec and VSX registers when
the guest is little-endian.
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/cpu.h | 1 +
target-ppc/gdbstub.c | 10 +++++-----
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index b3b89e6..2bc96b4 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -2355,4 +2355,5 @@ int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
*/
PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
+void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
#endif /* !defined (__CPU_PPC_H__) */
diff --git a/target-ppc/gdbstub.c b/target-ppc/gdbstub.c
index 14675f4..b20bb0c 100644
--- a/target-ppc/gdbstub.c
+++ b/target-ppc/gdbstub.c
@@ -88,7 +88,7 @@ static int ppc_gdb_register_len(int n)
the proper ordering for the binary, and cannot be changed.
For system mode, TARGET_WORDS_BIGENDIAN is always set, and we must check
the current mode of the chip to see if we're running in little-endian. */
-static void maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len)
+void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len)
{
#ifndef CONFIG_USER_ONLY
if (!msr_le) {
@@ -158,7 +158,7 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
break;
}
}
- maybe_bswap_register(env, mem_buf, r);
+ ppc_maybe_bswap_register(env, mem_buf, r);
return r;
}
@@ -214,7 +214,7 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
break;
}
}
- maybe_bswap_register(env, mem_buf, r);
+ ppc_maybe_bswap_register(env, mem_buf, r);
return r;
}
@@ -227,7 +227,7 @@ int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
if (!r) {
return r;
}
- maybe_bswap_register(env, mem_buf, r);
+ ppc_maybe_bswap_register(env, mem_buf, r);
if (n < 32) {
/* gprs */
env->gpr[n] = ldtul_p(mem_buf);
@@ -277,7 +277,7 @@ int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
if (!r) {
return r;
}
- maybe_bswap_register(env, mem_buf, r);
+ ppc_maybe_bswap_register(env, mem_buf, r);
if (n < 32) {
/* gprs */
env->gpr[n] = ldq_p(mem_buf);
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 21/28] target-ppc: gdbstub: fix float registers for little-endian guests
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (19 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 20/28] target-ppc: rename and export maybe_bswap_register() David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 22/28] target-ppc: gdbstub: introduce avr_need_swap() David Gibson
` (7 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
From: Greg Kurz <gkurz@linux.vnet.ibm.com>
Let's reuse the ppc_maybe_bswap_register() helper, like we already do
with the general registers.
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/translate_init.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 678957a..aabf754 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8755,10 +8755,12 @@ static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
stfq_p(mem_buf, env->fpr[n]);
+ ppc_maybe_bswap_register(env, mem_buf, 8);
return 8;
}
if (n == 32) {
stl_p(mem_buf, env->fpscr);
+ ppc_maybe_bswap_register(env, mem_buf, 4);
return 4;
}
return 0;
@@ -8767,10 +8769,12 @@ static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
+ ppc_maybe_bswap_register(env, mem_buf, 8);
env->fpr[n] = ldfq_p(mem_buf);
return 8;
}
if (n == 32) {
+ ppc_maybe_bswap_register(env, mem_buf, 4);
helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
return 4;
}
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 22/28] target-ppc: gdbstub: introduce avr_need_swap()
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (20 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 21/28] target-ppc: gdbstub: fix float registers for little-endian guests David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 23/28] target-ppc: gdbstub: fix altivec registers for little-endian guests David Gibson
` (6 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
From: Greg Kurz <gkurz@linux.vnet.ibm.com>
This helper will be used to support Altivec registers in little-endian guests.
This patch does not change functionnality.
Note: I had to put the helper some lines away from the gdb_*_avr_reg()
routines to get a more readable patch.
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/translate_init.c | 37 +++++++++++++++++++++++--------------
1 file changed, 23 insertions(+), 14 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index aabf754..54720ca 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8751,6 +8751,15 @@ static void dump_ppc_insns (CPUPPCState *env)
}
#endif
+static bool avr_need_swap(CPUPPCState *env)
+{
+#ifdef HOST_WORDS_BIGENDIAN
+ return false;
+#else
+ return true;
+#endif
+}
+
static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
@@ -8784,13 +8793,13 @@ static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
-#ifdef HOST_WORDS_BIGENDIAN
- stq_p(mem_buf, env->avr[n].u64[0]);
- stq_p(mem_buf+8, env->avr[n].u64[1]);
-#else
- stq_p(mem_buf, env->avr[n].u64[1]);
- stq_p(mem_buf+8, env->avr[n].u64[0]);
-#endif
+ if (!avr_need_swap(env)) {
+ stq_p(mem_buf, env->avr[n].u64[0]);
+ stq_p(mem_buf+8, env->avr[n].u64[1]);
+ } else {
+ stq_p(mem_buf, env->avr[n].u64[1]);
+ stq_p(mem_buf+8, env->avr[n].u64[0]);
+ }
return 16;
}
if (n == 32) {
@@ -8807,13 +8816,13 @@ static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
-#ifdef HOST_WORDS_BIGENDIAN
- env->avr[n].u64[0] = ldq_p(mem_buf);
- env->avr[n].u64[1] = ldq_p(mem_buf+8);
-#else
- env->avr[n].u64[1] = ldq_p(mem_buf);
- env->avr[n].u64[0] = ldq_p(mem_buf+8);
-#endif
+ if (!avr_need_swap(env)) {
+ env->avr[n].u64[0] = ldq_p(mem_buf);
+ env->avr[n].u64[1] = ldq_p(mem_buf+8);
+ } else {
+ env->avr[n].u64[1] = ldq_p(mem_buf);
+ env->avr[n].u64[0] = ldq_p(mem_buf+8);
+ }
return 16;
}
if (n == 32) {
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 23/28] target-ppc: gdbstub: fix altivec registers for little-endian guests
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (21 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 22/28] target-ppc: gdbstub: introduce avr_need_swap() David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 24/28] target-ppc: gdbstub: fix spe " David Gibson
` (5 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
From: Greg Kurz <gkurz@linux.vnet.ibm.com>
Altivec registers are 128-bit wide. They are stored in memory as two
64-bit values that must be byteswapped when the guest is little-endian.
Let's reuse the ppc_maybe_bswap_register() helper for this.
We also need to fix the ordering of the 64-bit elements according to
the target endianness, for both system and user mode.
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/translate_init.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 54720ca..4c29912 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8754,9 +8754,9 @@ static void dump_ppc_insns (CPUPPCState *env)
static bool avr_need_swap(CPUPPCState *env)
{
#ifdef HOST_WORDS_BIGENDIAN
- return false;
+ return msr_le;
#else
- return true;
+ return !msr_le;
#endif
}
@@ -8800,14 +8800,18 @@ static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
stq_p(mem_buf, env->avr[n].u64[1]);
stq_p(mem_buf+8, env->avr[n].u64[0]);
}
+ ppc_maybe_bswap_register(env, mem_buf, 8);
+ ppc_maybe_bswap_register(env, mem_buf + 8, 8);
return 16;
}
if (n == 32) {
stl_p(mem_buf, env->vscr);
+ ppc_maybe_bswap_register(env, mem_buf, 4);
return 4;
}
if (n == 33) {
stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
+ ppc_maybe_bswap_register(env, mem_buf, 4);
return 4;
}
return 0;
@@ -8816,6 +8820,8 @@ static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
+ ppc_maybe_bswap_register(env, mem_buf, 8);
+ ppc_maybe_bswap_register(env, mem_buf + 8, 8);
if (!avr_need_swap(env)) {
env->avr[n].u64[0] = ldq_p(mem_buf);
env->avr[n].u64[1] = ldq_p(mem_buf+8);
@@ -8826,10 +8832,12 @@ static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
return 16;
}
if (n == 32) {
+ ppc_maybe_bswap_register(env, mem_buf, 4);
env->vscr = ldl_p(mem_buf);
return 4;
}
if (n == 33) {
+ ppc_maybe_bswap_register(env, mem_buf, 4);
env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
return 4;
}
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 24/28] target-ppc: gdbstub: fix spe registers for little-endian guests
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (22 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 23/28] target-ppc: gdbstub: fix altivec registers for little-endian guests David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 25/28] target-ppc: gdbstub: Add VSX support David Gibson
` (4 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
From: Greg Kurz <gkurz@linux.vnet.ibm.com>
Let's reuse the ppc_maybe_bswap_register() helper, like we already do
with the general registers.
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/translate_init.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 4c29912..6625bb5 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8849,6 +8849,7 @@ static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
if (n < 32) {
#if defined(TARGET_PPC64)
stl_p(mem_buf, env->gpr[n] >> 32);
+ ppc_maybe_bswap_register(env, mem_buf, 4);
#else
stl_p(mem_buf, env->gprh[n]);
#endif
@@ -8856,10 +8857,12 @@ static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
}
if (n == 32) {
stq_p(mem_buf, env->spe_acc);
+ ppc_maybe_bswap_register(env, mem_buf, 8);
return 8;
}
if (n == 33) {
stl_p(mem_buf, env->spe_fscr);
+ ppc_maybe_bswap_register(env, mem_buf, 4);
return 4;
}
return 0;
@@ -8870,7 +8873,11 @@ static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
if (n < 32) {
#if defined(TARGET_PPC64)
target_ulong lo = (uint32_t)env->gpr[n];
- target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
+ target_ulong hi;
+
+ ppc_maybe_bswap_register(env, mem_buf, 4);
+
+ hi = (target_ulong)ldl_p(mem_buf) << 32;
env->gpr[n] = lo | hi;
#else
env->gprh[n] = ldl_p(mem_buf);
@@ -8878,10 +8885,12 @@ static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
return 4;
}
if (n == 32) {
+ ppc_maybe_bswap_register(env, mem_buf, 8);
env->spe_acc = ldq_p(mem_buf);
return 8;
}
if (n == 33) {
+ ppc_maybe_bswap_register(env, mem_buf, 4);
env->spe_fscr = ldl_p(mem_buf);
return 4;
}
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 25/28] target-ppc: gdbstub: Add VSX support
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (23 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 24/28] target-ppc: gdbstub: fix spe " David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 26/28] pseries: Allow TCG h_enter to work with hotplugged memory David Gibson
` (3 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
Anton Blanchard, bharata, David Gibson, gkurz
From: Anton Blanchard <anton@samba.org>
Add the XML and functions to get and set VSX registers.
Signed-off-by: Anton Blanchard <anton@samba.org>
(fixed little-endian guests)
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
configure | 6 +++---
gdb-xml/power-vsx.xml | 44 ++++++++++++++++++++++++++++++++++++++++++++
target-ppc/translate_init.c | 24 ++++++++++++++++++++++++
3 files changed, 71 insertions(+), 3 deletions(-)
create mode 100644 gdb-xml/power-vsx.xml
diff --git a/configure b/configure
index 44ac9ab..d96d646 100755
--- a/configure
+++ b/configure
@@ -5632,20 +5632,20 @@ case "$target_name" in
ppc64)
TARGET_BASE_ARCH=ppc
TARGET_ABI_DIR=ppc
- gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml"
+ gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml"
;;
ppc64le)
TARGET_ARCH=ppc64
TARGET_BASE_ARCH=ppc
TARGET_ABI_DIR=ppc
- gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml"
+ gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml"
;;
ppc64abi32)
TARGET_ARCH=ppc64
TARGET_BASE_ARCH=ppc
TARGET_ABI_DIR=ppc
echo "TARGET_ABI32=y" >> $config_target_mak
- gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml"
+ gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml"
;;
sh4|sh4eb)
TARGET_ARCH=sh4
diff --git a/gdb-xml/power-vsx.xml b/gdb-xml/power-vsx.xml
new file mode 100644
index 0000000..fd290e9
--- /dev/null
+++ b/gdb-xml/power-vsx.xml
@@ -0,0 +1,44 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2008-2015 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- POWER7 VSX registers that do not overlap existing FP and VMX
+ registers. -->
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.power.vsx">
+ <reg name="vs0h" bitsize="64" type="uint64"/>
+ <reg name="vs1h" bitsize="64" type="uint64"/>
+ <reg name="vs2h" bitsize="64" type="uint64"/>
+ <reg name="vs3h" bitsize="64" type="uint64"/>
+ <reg name="vs4h" bitsize="64" type="uint64"/>
+ <reg name="vs5h" bitsize="64" type="uint64"/>
+ <reg name="vs6h" bitsize="64" type="uint64"/>
+ <reg name="vs7h" bitsize="64" type="uint64"/>
+ <reg name="vs8h" bitsize="64" type="uint64"/>
+ <reg name="vs9h" bitsize="64" type="uint64"/>
+ <reg name="vs10h" bitsize="64" type="uint64"/>
+ <reg name="vs11h" bitsize="64" type="uint64"/>
+ <reg name="vs12h" bitsize="64" type="uint64"/>
+ <reg name="vs13h" bitsize="64" type="uint64"/>
+ <reg name="vs14h" bitsize="64" type="uint64"/>
+ <reg name="vs15h" bitsize="64" type="uint64"/>
+ <reg name="vs16h" bitsize="64" type="uint64"/>
+ <reg name="vs17h" bitsize="64" type="uint64"/>
+ <reg name="vs18h" bitsize="64" type="uint64"/>
+ <reg name="vs19h" bitsize="64" type="uint64"/>
+ <reg name="vs20h" bitsize="64" type="uint64"/>
+ <reg name="vs21h" bitsize="64" type="uint64"/>
+ <reg name="vs22h" bitsize="64" type="uint64"/>
+ <reg name="vs23h" bitsize="64" type="uint64"/>
+ <reg name="vs24h" bitsize="64" type="uint64"/>
+ <reg name="vs25h" bitsize="64" type="uint64"/>
+ <reg name="vs26h" bitsize="64" type="uint64"/>
+ <reg name="vs27h" bitsize="64" type="uint64"/>
+ <reg name="vs28h" bitsize="64" type="uint64"/>
+ <reg name="vs29h" bitsize="64" type="uint64"/>
+ <reg name="vs30h" bitsize="64" type="uint64"/>
+ <reg name="vs31h" bitsize="64" type="uint64"/>
+</feature>
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 6625bb5..f6babd2 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8897,6 +8897,26 @@ static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
return 0;
}
+static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ stq_p(mem_buf, env->vsr[n]);
+ ppc_maybe_bswap_register(env, mem_buf, 8);
+ return 8;
+ }
+ return 0;
+}
+
+static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ ppc_maybe_bswap_register(env, mem_buf, 8);
+ env->vsr[n] = ldq_p(mem_buf);
+ return 8;
+ }
+ return 0;
+}
+
static int ppc_fixup_cpu(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
@@ -9002,6 +9022,10 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
34, "power-spe.xml", 0);
}
+ if (pcc->insns_flags2 & PPC2_VSX) {
+ gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
+ 32, "power-vsx.xml", 0);
+ }
qemu_init_vcpu(cs);
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 26/28] pseries: Allow TCG h_enter to work with hotplugged memory
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (24 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 25/28] target-ppc: gdbstub: Add VSX support David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 27/28] cuda.c: return error for unknown commands David Gibson
` (2 subsequent siblings)
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel, qemu-ppc,
bharata, David Gibson, gkurz
The implementation of the H_ENTER hypercall for PAPR guests needs to
enforce correct access attributes on the inserted HPTE. This means
determining if the HPTE's real address is a regular RAM address (which
requires attributes for coherent access) or an IO address (which requires
attributes for cache-inhibited access).
At the moment this check is implemented with (raddr < machine->ram_size),
but that only handles addresses in the base RAM area, not any hotplugged
RAM.
This patch corrects the problem with a new helper.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
hw/ppc/spapr_hcall.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index e9c057d..c4ae255 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -84,10 +84,25 @@ static inline bool valid_pte_index(CPUPPCState *env, target_ulong pte_index)
return true;
}
+static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr)
+{
+ MachineState *machine = MACHINE(spapr);
+ MemoryHotplugState *hpms = &spapr->hotplug_memory;
+
+ if (addr < machine->ram_size) {
+ return true;
+ }
+ if ((addr >= hpms->base)
+ && ((addr - hpms->base) < memory_region_size(&hpms->mr))) {
+ return true;
+ }
+
+ return false;
+}
+
static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
- MachineState *machine = MACHINE(spapr);
CPUPPCState *env = &cpu->env;
target_ulong flags = args[0];
target_ulong pte_index = args[1];
@@ -119,7 +134,7 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr,
raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << page_shift) - 1);
- if (raddr < machine->ram_size) {
+ if (is_ram_address(spapr, raddr)) {
/* Regular RAM - should have WIMG=0010 */
if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) {
return H_PARAMETER;
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 27/28] cuda.c: return error for unknown commands
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (25 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 26/28] pseries: Allow TCG h_enter to work with hotplugged memory David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 1:15 ` [Qemu-devel] [PULL 28/28] uninorth.c: add support for UniNorth kMacRISCPCIAddressSelect (0x48) register David Gibson
2016-01-25 10:42 ` [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 Peter Maydell
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel,
Alyssa Milburn, qemu-ppc, bharata, David Gibson, gkurz
From: Alyssa Milburn <fuzzie@fuzzie.org>
This avoids MacsBug hanging at startup in the absence of ADB mouse
input, by replying with an error (which is also what MOL does) when
it sends an unknown command (0x1c).
Signed-off-by: Alyssa Milburn <fuzzie@fuzzie.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/misc/macio/cuda.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c
index 3556852..5e4d5d5 100644
--- a/hw/misc/macio/cuda.c
+++ b/hw/misc/macio/cuda.c
@@ -605,6 +605,11 @@ static void cuda_receive_packet(CUDAState *s,
}
break;
default:
+ obuf[0] = ERROR_PACKET;
+ obuf[1] = 0x2;
+ obuf[2] = CUDA_PACKET;
+ obuf[3] = data[0];
+ cuda_send_packet_to_host(s, obuf, 4);
break;
}
}
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Qemu-devel] [PULL 28/28] uninorth.c: add support for UniNorth kMacRISCPCIAddressSelect (0x48) register
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (26 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 27/28] cuda.c: return error for unknown commands David Gibson
@ 2016-01-25 1:15 ` David Gibson
2016-01-25 10:42 ` [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 Peter Maydell
28 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-25 1:15 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, thuth, mark.cave-ayland, agraf, qemu-devel,
Programmingkid, qemu-ppc, bharata, David Gibson, gkurz
From: Programmingkid <programmingkidx@gmail.com>
Darwin/OS X use the undocumented kMacRISCPCIAddressSelect (0x48) to
configure PCI memory space size for mac99 machines. Without this
register, warnings similar to below are emitted to the console during boot:
AppleMacRiscPCI: bad range 2(80000000:01000000)
AppleMacRiscPCI: bad range 2(81000000:00001000)
AppleMacRiscPCI: bad range 2(81080000:00080000)
Based upon the algorithm in Darwin's AppleMacRiscPCI.cpp driver, set the
kMacRISCPCIAddressSelect register so that Darwin considers the PCI
memory space to be at 0x80000000 (size 0x10000000) which matches that
currently used by QEMU and OpenBIOS.
Signed-off-by: John Arbuckle <programmingkidx@gmail.com>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
[commit message and comment revised as suggested by Mark Cave-Ayland]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/uninorth.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
index 215b64f..d4aff84 100644
--- a/hw/pci-host/uninorth.c
+++ b/hw/pci-host/uninorth.c
@@ -330,6 +330,15 @@ static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
d->config[0x0C] = 0x08; // cache_line_size
d->config[0x0D] = 0x10; // latency_timer
// d->config[0x34] = 0x80; // capabilities_pointer
+ /*
+ * Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI
+ * memory space with base 0x80000000, size 0x10000000 for Apple's
+ * AppleMacRiscPCI driver
+ */
+ d->config[0x48] = 0x0;
+ d->config[0x49] = 0x0;
+ d->config[0x4a] = 0x0;
+ d->config[0x4b] = 0x1;
}
static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp)
--
2.5.0
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125
2016-01-25 1:14 [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 David Gibson
` (27 preceding siblings ...)
2016-01-25 1:15 ` [Qemu-devel] [PULL 28/28] uninorth.c: add support for UniNorth kMacRISCPCIAddressSelect (0x48) register David Gibson
@ 2016-01-25 10:42 ` Peter Maydell
2016-01-25 11:19 ` David Gibson
28 siblings, 1 reply; 46+ messages in thread
From: Peter Maydell @ 2016-01-25 10:42 UTC (permalink / raw)
To: David Gibson
Cc: Laurent Vivier, Thomas Huth, Mark Cave-Ayland, Alexander Graf,
QEMU Developers, qemu-ppc, bharata, Greg Kurz
On 25 January 2016 at 01:14, David Gibson <david@gibson.dropbear.id.au> wrote:
> The following changes since commit 047e363b05679724d6b784c6ec6310697fe48ba0:
>
> Merge remote-tracking branch 'remotes/pmaydell/tags/pull-softfloat-20160122' into staging (2016-01-22 15:19:21 +0000)
>
> are available in the git repository at:
>
> git://github.com/dgibson/qemu.git tags/ppc-for-2.6-20160125
>
> for you to fetch changes up to ce3b7990c1ddf70b29f00eb878bb693471f9bc36:
>
> uninorth.c: add support for UniNorth kMacRISCPCIAddressSelect (0x48) register (2016-01-25 10:35:50 +1100)
>
> ----------------------------------------------------------------
> ppc patch queue for 2016-01-25
>
> Currently accumulated patches for target-ppc, pseries machine type and
> related devices.
> * Cleanup of error handling code in spapr
> * A number of fixes for Macintosh devices for the benefit of MacOS 9 and X
> * Remove some abuses of the RTAS memory access functions in spapr
> * Fixes for the gdbstub (and monitor debug) for VMX and VSX extensions.
> * Fix pseries machine hotplug memory under TCG
Fails to build on 32-bit I'm afraid:
/home/petmay01/qemu/hw/ppc/spapr.c: In function 'spapr_validate_node_memory':
/home/petmay01/qemu/hw/ppc/spapr.c:1723:13: error: format '%x' expects
argument of type 'unsigned int', but argument 7 has type 'uint64_t'
[-Werror=format]
error_setg(errp,
^
Same thing from OSX clang, which gets the location of the error a bit
more precise:
/Users/pm215/src/qemu-for-merges/hw/ppc/spapr.c:1726:27: warning:
format specifies type 'unsigned long' but the argument has type
'uint64_t' (aka 'unsigned long long') [-Wformat]
i, numa_info[i].node_mem,
^~~~~~~~~~~~~~~~~~~~~
/Users/pm215/src/qemu-for-merges/include/qapi/error.h:168:35: note:
expanded from macro 'error_setg'
(fmt), ## __VA_ARGS__)
^
thanks
-- PMM
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125
2016-01-25 10:42 ` [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125 Peter Maydell
@ 2016-01-25 11:19 ` David Gibson
2016-01-25 11:59 ` Peter Maydell
0 siblings, 1 reply; 46+ messages in thread
From: David Gibson @ 2016-01-25 11:19 UTC (permalink / raw)
To: Peter Maydell
Cc: Laurent Vivier, Thomas Huth, Mark Cave-Ayland, Alexander Graf,
QEMU Developers, qemu-ppc, bharata, Greg Kurz
[-- Attachment #1: Type: text/plain, Size: 2482 bytes --]
On Mon, Jan 25, 2016 at 10:42:40AM +0000, Peter Maydell wrote:
> On 25 January 2016 at 01:14, David Gibson <david@gibson.dropbear.id.au> wrote:
> > The following changes since commit 047e363b05679724d6b784c6ec6310697fe48ba0:
> >
> > Merge remote-tracking branch 'remotes/pmaydell/tags/pull-softfloat-20160122' into staging (2016-01-22 15:19:21 +0000)
> >
> > are available in the git repository at:
> >
> > git://github.com/dgibson/qemu.git tags/ppc-for-2.6-20160125
> >
> > for you to fetch changes up to ce3b7990c1ddf70b29f00eb878bb693471f9bc36:
> >
> > uninorth.c: add support for UniNorth kMacRISCPCIAddressSelect (0x48) register (2016-01-25 10:35:50 +1100)
> >
> > ----------------------------------------------------------------
> > ppc patch queue for 2016-01-25
> >
> > Currently accumulated patches for target-ppc, pseries machine type and
> > related devices.
> > * Cleanup of error handling code in spapr
> > * A number of fixes for Macintosh devices for the benefit of MacOS 9 and X
> > * Remove some abuses of the RTAS memory access functions in spapr
> > * Fixes for the gdbstub (and monitor debug) for VMX and VSX extensions.
> > * Fix pseries machine hotplug memory under TCG
>
> Fails to build on 32-bit I'm afraid:
>
> /home/petmay01/qemu/hw/ppc/spapr.c: In function 'spapr_validate_node_memory':
> /home/petmay01/qemu/hw/ppc/spapr.c:1723:13: error: format '%x' expects
> argument of type 'unsigned int', but argument 7 has type 'uint64_t'
> [-Werror=format]
> error_setg(errp,
> ^
>
> Same thing from OSX clang, which gets the location of the error a bit
> more precise:
>
> /Users/pm215/src/qemu-for-merges/hw/ppc/spapr.c:1726:27: warning:
> format specifies type 'unsigned long' but the argument has type
> 'uint64_t' (aka 'unsigned long long') [-Wformat]
> i, numa_info[i].node_mem,
> ^~~~~~~~~~~~~~~~~~~~~
> /Users/pm215/src/qemu-for-merges/include/qapi/error.h:168:35: note:
> expanded from macro 'error_setg'
> (fmt), ## __VA_ARGS__)
Ah, sorry, thanks for the info.
I think I've fixed it, but it's a bit hard to tell since for me
origin/master also fails to compile on 32-bit :(.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125
2016-01-25 11:19 ` David Gibson
@ 2016-01-25 11:59 ` Peter Maydell
2016-01-25 14:00 ` David Gibson
0 siblings, 1 reply; 46+ messages in thread
From: Peter Maydell @ 2016-01-25 11:59 UTC (permalink / raw)
To: David Gibson
Cc: Laurent Vivier, Thomas Huth, Mark Cave-Ayland, Alexander Graf,
QEMU Developers, qemu-ppc, bharata, Greg Kurz
On 25 January 2016 at 11:19, David Gibson <david@gibson.dropbear.id.au> wrote:
> I think I've fixed it, but it's a bit hard to tell since for me
> origin/master also fails to compile on 32-bit :(.
Oops -- what's the failure there?
(I do know of a vixl compile failure with older gcc you might be running
into; if that's it try configuring with --cxx=none. I should send a patch
to fix that.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125
2016-01-25 11:59 ` Peter Maydell
@ 2016-01-25 14:00 ` David Gibson
2016-01-25 14:38 ` Peter Maydell
0 siblings, 1 reply; 46+ messages in thread
From: David Gibson @ 2016-01-25 14:00 UTC (permalink / raw)
To: Peter Maydell
Cc: Laurent Vivier, Thomas Huth, Mark Cave-Ayland, Alexander Graf,
QEMU Developers, qemu-ppc, bharata, Greg Kurz
[-- Attachment #1: Type: text/plain, Size: 5267 bytes --]
On Mon, Jan 25, 2016 at 11:59:22AM +0000, Peter Maydell wrote:
> On 25 January 2016 at 11:19, David Gibson <david@gibson.dropbear.id.au> wrote:
> > I think I've fixed it, but it's a bit hard to tell since for me
> > origin/master also fails to compile on 32-bit :(.
>
> Oops -- what's the failure there?
>
> (I do know of a vixl compile failure with older gcc you might be running
> into; if that's it try configuring with --cxx=none. I should send a patch
> to fix that.)
Doesn't look like it. Might be something to do with a specific glib
version though:
$ make -k
CC qga/commands-posix.o
qga/commands-posix.c: In function ‘qmp_guest_file_write’:
qga/commands-posix.c:529:39: error: passing argument 3 of ‘qbase64_decode’ from incompatible pointer type [-Werror=incompatible-pointer-types]
buf = qbase64_decode(buf_b64, -1, &buf_len, errp);
^
In file included from qga/commands-posix.c:32:0:
/home/dwg/src/qemu/include/qemu/base64.h:52:10: note: expected ‘size_t * {aka unsigned int *}’ but argument is of type ‘gsize * {aka long unsigned int *}’
uint8_t *qbase64_decode(const char *input,
^
cc1: all warnings being treated as errors
/home/dwg/src/qemu/rules.mak:57: recipe for target 'qga/commands-posix.o' failed
make: *** [qga/commands-posix.o] Error 1
CC util/base64.o
util/base64.c: In function ‘qbase64_decode’:
util/base64.c:59:35: error: passing argument 2 of ‘g_base64_decode’ from incompatible pointer type [-Werror=incompatible-pointer-types]
return g_base64_decode(input, out_len);
^
In file included from /usr/include/glib-2.0/glib.h:35:0,
from /home/dwg/src/qemu/include/glib-compat.h:19,
from /home/dwg/src/qemu/include/qemu/osdep.h:72,
from /home/dwg/src/qemu/include/qemu-common.h:15,
from /home/dwg/src/qemu/include/qemu/base64.h:24,
from util/base64.c:23:
/usr/include/glib-2.0/glib/gbase64.h:52:9: note: expected ‘gsize * {aka long unsigned int *}’ but argument is of type ‘size_t * {aka unsigned int *}’
guchar *g_base64_decode (const gchar *text,
^
cc1: all warnings being treated as errors
/home/dwg/src/qemu/rules.mak:57: recipe for target 'util/base64.o' failed
make: *** [util/base64.o] Error 1
CC crypto/secret.o
crypto/secret.c: In function ‘qcrypto_secret_load_data’:
crypto/secret.c:47:55: error: passing argument 3 of ‘g_file_get_contents’ from incompatible pointer type [-Werror=incompatible-pointer-types]
if (!g_file_get_contents(secret->file, &data, &length, &gerr)) {
^
In file included from /usr/include/glib-2.0/glib.h:48:0,
from /home/dwg/src/qemu/include/glib-compat.h:19,
from /home/dwg/src/qemu/include/qemu/osdep.h:72,
from /home/dwg/src/qemu/include/qemu-common.h:15,
from /home/dwg/src/qemu/include/crypto/secret.h:24,
from crypto/secret.c:21:
/usr/include/glib-2.0/glib/gfileutils.h:85:10: note: expected ‘gsize * {aka long unsigned int *}’ but argument is of type ‘size_t * {aka unsigned int *}’
gboolean g_file_get_contents (const gchar *filename,
^
cc1: all warnings being treated as errors
/home/dwg/src/qemu/rules.mak:57: recipe for target 'crypto/secret.o' failed
make: *** [crypto/secret.o] Error 1
CC qemu-char.o
qemu-char.c: In function ‘qmp_ringbuf_write’:
qemu-char.c:3317:37: error: passing argument 3 of ‘qbase64_decode’ from incompatible pointer type [-Werror=incompatible-pointer-types]
&write_count,
^
In file included from qemu-char.c:35:0:
/home/dwg/src/qemu/include/qemu/base64.h:52:10: note: expected ‘size_t * {aka unsigned int *}’ but argument is of type ‘gsize * {aka long unsigned int *}’
uint8_t *qbase64_decode(const char *input,
^
cc1: all warnings being treated as errors
/home/dwg/src/qemu/rules.mak:57: recipe for target 'qemu-char.o' failed
make: *** [qemu-char.o] Error 1
CC vl.o
vl.c: In function ‘parse_fw_cfg’:
vl.c:2317:46: error: passing argument 3 of ‘g_file_get_contents’ from incompatible pointer type [-Werror=incompatible-pointer-types]
if (!g_file_get_contents(file, &buf, &size, NULL)) {
^
In file included from /usr/include/glib-2.0/glib.h:48:0,
from vl.c:59:
/usr/include/glib-2.0/glib/gfileutils.h:85:10: note: expected ‘gsize * {aka long unsigned int *}’ but argument is of type ‘size_t * {aka unsigned int *}’
gboolean g_file_get_contents (const gchar *filename,
^
cc1: all warnings being treated as errors
/home/dwg/src/qemu/rules.mak:57: recipe for target 'vl.o' failed
make: *** [vl.o] Error 1
make: Target 'all' not remade because of errors.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125
2016-01-25 14:00 ` David Gibson
@ 2016-01-25 14:38 ` Peter Maydell
2016-01-26 5:37 ` David Gibson
0 siblings, 1 reply; 46+ messages in thread
From: Peter Maydell @ 2016-01-25 14:38 UTC (permalink / raw)
To: David Gibson
Cc: Laurent Vivier, Thomas Huth, Mark Cave-Ayland, Alexander Graf,
QEMU Developers, qemu-ppc, bharata, Greg Kurz
On 25 January 2016 at 14:00, David Gibson <david@gibson.dropbear.id.au> wrote:
> On Mon, Jan 25, 2016 at 11:59:22AM +0000, Peter Maydell wrote:
>> On 25 January 2016 at 11:19, David Gibson <david@gibson.dropbear.id.au> wrote:
>> > I think I've fixed it, but it's a bit hard to tell since for me
>> > origin/master also fails to compile on 32-bit :(.
>>
>> Oops -- what's the failure there?
>>
>> (I do know of a vixl compile failure with older gcc you might be running
>> into; if that's it try configuring with --cxx=none. I should send a patch
>> to fix that.)
>
> Doesn't look like it. Might be something to do with a specific glib
> version though:
>
> $ make -k
> CC qga/commands-posix.o
> qga/commands-posix.c: In function ‘qmp_guest_file_write’:
> qga/commands-posix.c:529:39: error: passing argument 3 of ‘qbase64_decode’ from incompatible pointer type [-Werror=incompatible-pointer-types]
> buf = qbase64_decode(buf_b64, -1, &buf_len, errp);
> ^
> In file included from qga/commands-posix.c:32:0:
> /home/dwg/src/qemu/include/qemu/base64.h:52:10: note: expected ‘size_t * {aka unsigned int *}’ but argument is of type ‘gsize * {aka long unsigned int *}’
> uint8_t *qbase64_decode(const char *input,
> ^
> cc1: all warnings being treated as errors
> /home/dwg/src/qemu/rules.mak:57: recipe for target 'qga/commands-posix.o' failed
> make: *** [qga/commands-posix.o] Error 1
> CC util/base64.o
Ah, that's your compile environment being wrong -- you're trying to
build QEMU 32-bit but using the 64-bit glib headers.
Daniel sent a patch which diagnoses this at the configure stage
http://patchwork.ozlabs.org/patch/544254/
but it looks like it didn't get applied...
Try setting PKG_CONFIG_LIBDIR and perhaps other things.
thanks
-- PMM
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125
2016-01-25 14:38 ` Peter Maydell
@ 2016-01-26 5:37 ` David Gibson
2016-01-26 7:08 ` Alexander Graf
2016-01-26 9:13 ` Peter Maydell
0 siblings, 2 replies; 46+ messages in thread
From: David Gibson @ 2016-01-26 5:37 UTC (permalink / raw)
To: Peter Maydell
Cc: Laurent Vivier, Thomas Huth, Mark Cave-Ayland, Alexander Graf,
QEMU Developers, qemu-ppc, bharata, Greg Kurz
[-- Attachment #1: Type: text/plain, Size: 2322 bytes --]
On Mon, Jan 25, 2016 at 02:38:15PM +0000, Peter Maydell wrote:
> On 25 January 2016 at 14:00, David Gibson <david@gibson.dropbear.id.au> wrote:
> > On Mon, Jan 25, 2016 at 11:59:22AM +0000, Peter Maydell wrote:
> >> On 25 January 2016 at 11:19, David Gibson <david@gibson.dropbear.id.au> wrote:
> >> > I think I've fixed it, but it's a bit hard to tell since for me
> >> > origin/master also fails to compile on 32-bit :(.
> >>
> >> Oops -- what's the failure there?
> >>
> >> (I do know of a vixl compile failure with older gcc you might be running
> >> into; if that's it try configuring with --cxx=none. I should send a patch
> >> to fix that.)
> >
> > Doesn't look like it. Might be something to do with a specific glib
> > version though:
> >
> > $ make -k
> > CC qga/commands-posix.o
> > qga/commands-posix.c: In function ‘qmp_guest_file_write’:
> > qga/commands-posix.c:529:39: error: passing argument 3 of ‘qbase64_decode’ from incompatible pointer type [-Werror=incompatible-pointer-types]
> > buf = qbase64_decode(buf_b64, -1, &buf_len, errp);
> > ^
> > In file included from qga/commands-posix.c:32:0:
> > /home/dwg/src/qemu/include/qemu/base64.h:52:10: note: expected ‘size_t * {aka unsigned int *}’ but argument is of type ‘gsize * {aka long unsigned int *}’
> > uint8_t *qbase64_decode(const char *input,
> > ^
> > cc1: all warnings being treated as errors
> > /home/dwg/src/qemu/rules.mak:57: recipe for target 'qga/commands-posix.o' failed
> > make: *** [qga/commands-posix.o] Error 1
> > CC util/base64.o
>
> Ah, that's your compile environment being wrong -- you're trying to
> build QEMU 32-bit but using the 64-bit glib headers.
There are different versions of the *headers*!? Wtf?
> Daniel sent a patch which diagnoses this at the configure stage
> http://patchwork.ozlabs.org/patch/544254/
> but it looks like it didn't get applied...
>
> Try setting PKG_CONFIG_LIBDIR and perhaps other things.
Good grief. And this would be why I don't generally test 32-bit
builds...
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125
2016-01-26 5:37 ` David Gibson
@ 2016-01-26 7:08 ` Alexander Graf
2016-01-26 10:56 ` Gerd Hoffmann
2016-01-26 9:13 ` Peter Maydell
1 sibling, 1 reply; 46+ messages in thread
From: Alexander Graf @ 2016-01-26 7:08 UTC (permalink / raw)
To: David Gibson
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Mark Cave-Ayland,
QEMU Developers, qemu-ppc, bharata, Greg Kurz
> Am 26.01.2016 um 06:37 schrieb David Gibson <david@gibson.dropbear.id.au>:
>
>> On Mon, Jan 25, 2016 at 02:38:15PM +0000, Peter Maydell wrote:
>>> On 25 January 2016 at 14:00, David Gibson <david@gibson.dropbear.id.au> wrote:
>>>> On Mon, Jan 25, 2016 at 11:59:22AM +0000, Peter Maydell wrote:
>>>>> On 25 January 2016 at 11:19, David Gibson <david@gibson.dropbear.id.au> wrote:
>>>>> I think I've fixed it, but it's a bit hard to tell since for me
>>>>> origin/master also fails to compile on 32-bit :(.
>>>>
>>>> Oops -- what's the failure there?
>>>>
>>>> (I do know of a vixl compile failure with older gcc you might be running
>>>> into; if that's it try configuring with --cxx=none. I should send a patch
>>>> to fix that.)
>>>
>>> Doesn't look like it. Might be something to do with a specific glib
>>> version though:
>>>
>>> $ make -k
>>> CC qga/commands-posix.o
>>> qga/commands-posix.c: In function ‘qmp_guest_file_write’:
>>> qga/commands-posix.c:529:39: error: passing argument 3 of ‘qbase64_decode’ from incompatible pointer type [-Werror=incompatible-pointer-types]
>>> buf = qbase64_decode(buf_b64, -1, &buf_len, errp);
>>> ^
>>> In file included from qga/commands-posix.c:32:0:
>>> /home/dwg/src/qemu/include/qemu/base64.h:52:10: note: expected ‘size_t * {aka unsigned int *}’ but argument is of type ‘gsize * {aka long unsigned int *}’
>>> uint8_t *qbase64_decode(const char *input,
>>> ^
>>> cc1: all warnings being treated as errors
>>> /home/dwg/src/qemu/rules.mak:57: recipe for target 'qga/commands-posix.o' failed
>>> make: *** [qga/commands-posix.o] Error 1
>>> CC util/base64.o
>>
>> Ah, that's your compile environment being wrong -- you're trying to
>> build QEMU 32-bit but using the 64-bit glib headers.
>
> There are different versions of the *headers*!? Wtf?
>
>> Daniel sent a patch which diagnoses this at the configure stage
>> http://patchwork.ozlabs.org/patch/544254/
>> but it looks like it didn't get applied...
>>
>> Try setting PKG_CONFIG_LIBDIR and perhaps other things.
>
> Good grief. And this would be why I don't generally test 32-bit
> builds...
Just set up a 32bit vm and maybe configure it to automatically test your git branch? ;)
Alex
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125
2016-01-26 7:08 ` Alexander Graf
@ 2016-01-26 10:56 ` Gerd Hoffmann
2016-01-27 3:01 ` David Gibson
0 siblings, 1 reply; 46+ messages in thread
From: Gerd Hoffmann @ 2016-01-26 10:56 UTC (permalink / raw)
To: Alexander Graf
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Mark Cave-Ayland,
QEMU Developers, qemu-ppc, bharata, Greg Kurz, David Gibson
Hi,
> Just set up a 32bit vm and maybe configure it to automatically test your git branch? ;)
Container works even better as you can kick the build right from the
(host) command line, without boot vm, login, ...
sudo systemd-nspawn \
--directory /path/to/32bit-distro-root \
--bind /home \
--share-system \
--user $USER \
make -C $HOME/projects/qemu/build-32bit
configure is a bit more complicated because systemd-nspaws lacks a
--workdir switch, you need either some wrapper scripting or have to boot
the container, login, cd $builddir and run configure manually.
HTH,
Gerd
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125
2016-01-26 10:56 ` Gerd Hoffmann
@ 2016-01-27 3:01 ` David Gibson
2016-01-27 13:36 ` Gerd Hoffmann
0 siblings, 1 reply; 46+ messages in thread
From: David Gibson @ 2016-01-27 3:01 UTC (permalink / raw)
To: Gerd Hoffmann
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Mark Cave-Ayland,
Alexander Graf, QEMU Developers, qemu-ppc, bharata, Greg Kurz
[-- Attachment #1: Type: text/plain, Size: 1043 bytes --]
On Tue, Jan 26, 2016 at 11:56:15AM +0100, Gerd Hoffmann wrote:
> Hi,
>
> > Just set up a 32bit vm and maybe configure it to automatically test your git branch? ;)
>
> Container works even better as you can kick the build right from the
> (host) command line, without boot vm, login, ...
>
> sudo systemd-nspawn \
> --directory /path/to/32bit-distro-root \
> --bind /home \
> --share-system \
> --user $USER \
> make -C $HOME/projects/qemu/build-32bit
>
> configure is a bit more complicated because systemd-nspaws lacks a
> --workdir switch, you need either some wrapper scripting or have to boot
> the container, login, cd $builddir and run configure manually.
Hmm. Is there a HOWTO for setting up a 32-bit container? Containers
aren't something I've had the time to become familiar with so far.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125
2016-01-27 3:01 ` David Gibson
@ 2016-01-27 13:36 ` Gerd Hoffmann
2016-01-27 13:49 ` Laurent Vivier
0 siblings, 1 reply; 46+ messages in thread
From: Gerd Hoffmann @ 2016-01-27 13:36 UTC (permalink / raw)
To: David Gibson
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Mark Cave-Ayland,
Alexander Graf, QEMU Developers, qemu-ppc, bharata, Greg Kurz
Hi,
> Hmm. Is there a HOWTO for setting up a 32-bit container? Containers
> aren't something I've had the time to become familiar with so far.
systemd-nspawn manpage has a few examples in the examples section (and
is worth reading anyway).
For fedora it boils down to "yum/dnf --installroot=/dest/dir
groupinstall core", possibly with --config $cfgfile where you list your
repos in $cfgfile, especially when installing fedora on rhel so you
don't want the host repos.
Use "systemd-nspawn -D /dest/dir passwd" to set the root password,
otherwise you can't login. Boot with "systemd-nspawn -bD /dest/dir".
With --bind you can make host directories visible within the container.
For debian there is debootstrap which you can use (is packaged for
fedora and epel too).
Alternatively you can fetch a cloud image and run that.
HTH,
Gerd
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125
2016-01-27 13:36 ` Gerd Hoffmann
@ 2016-01-27 13:49 ` Laurent Vivier
0 siblings, 0 replies; 46+ messages in thread
From: Laurent Vivier @ 2016-01-27 13:49 UTC (permalink / raw)
To: Gerd Hoffmann, David Gibson
Cc: Peter Maydell, Thomas Huth, Mark Cave-Ayland, Alexander Graf,
QEMU Developers, qemu-ppc, bharata, Greg Kurz
On 27/01/2016 14:36, Gerd Hoffmann wrote:
> Hi,
>
>> Hmm. Is there a HOWTO for setting up a 32-bit container? Containers
>> aren't something I've had the time to become familiar with so far.
>
> systemd-nspawn manpage has a few examples in the examples section (and
> is worth reading anyway).
>
> For fedora it boils down to "yum/dnf --installroot=/dest/dir
> groupinstall core", possibly with --config $cfgfile where you list your
> repos in $cfgfile, especially when installing fedora on rhel so you
> don't want the host repos.
>
> Use "systemd-nspawn -D /dest/dir passwd" to set the root password,
> otherwise you can't login. Boot with "systemd-nspawn -bD /dest/dir".
> With --bind you can make host directories visible within the container.
>
> For debian there is debootstrap which you can use (is packaged for
> fedora and epel too).
With lxc, you can just do:
sudo lxc-create -n my_container -t debian -- --arch i686
and then
sudo lxc-start -n my_container -F
you need the lxc-templates package.
The fedora template (-t fedora) seems broken.
> Alternatively you can fetch a cloud image and run that.
>
> HTH,
> Gerd
>
Laurent
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125
2016-01-26 5:37 ` David Gibson
2016-01-26 7:08 ` Alexander Graf
@ 2016-01-26 9:13 ` Peter Maydell
2016-01-29 3:31 ` David Gibson
1 sibling, 1 reply; 46+ messages in thread
From: Peter Maydell @ 2016-01-26 9:13 UTC (permalink / raw)
To: David Gibson
Cc: Laurent Vivier, Thomas Huth, Mark Cave-Ayland, Alexander Graf,
QEMU Developers, qemu-ppc, bharata, Greg Kurz
On 26 January 2016 at 05:37, David Gibson <david@gibson.dropbear.id.au> wrote:
> Good grief. And this would be why I don't generally test 32-bit
> builds...
32-bit on 64-bit host is a special case of a cross-compile,
and cross-compiling is always pain... (My test 32-bit builds
are just done on a natively 32-bit machine.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [Qemu-devel] [PULL 00/28] ppc-for-2.6 queue 20160125
2016-01-26 9:13 ` Peter Maydell
@ 2016-01-29 3:31 ` David Gibson
0 siblings, 0 replies; 46+ messages in thread
From: David Gibson @ 2016-01-29 3:31 UTC (permalink / raw)
To: Peter Maydell
Cc: Laurent Vivier, Thomas Huth, Mark Cave-Ayland, Alexander Graf,
QEMU Developers, qemu-ppc, bharata, Greg Kurz
[-- Attachment #1: Type: text/plain, Size: 740 bytes --]
On Tue, Jan 26, 2016 at 09:13:34AM +0000, Peter Maydell wrote:
> On 26 January 2016 at 05:37, David Gibson <david@gibson.dropbear.id.au> wrote:
> > Good grief. And this would be why I don't generally test 32-bit
> > builds...
>
> 32-bit on 64-bit host is a special case of a cross-compile,
> and cross-compiling is always pain... (My test 32-bit builds
> are just done on a natively 32-bit machine.)
Well, sort of. With modern distro biarch / multiarch support it's
supposed to be a much easier case. And is with most packages.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 46+ messages in thread