[PATCH v4 0/5] arm: mvebu: Support for 98DX25xx/98DX35xx (AlleyCat5)

[PATCH v4 0/5] arm: mvebu: Support for 98DX25xx/98DX35xx (AlleyCat5)

[Chris Packham]

These patches are based on Marvell's bootloader for the AlleyCat5/5X
which was based on u-boot 2018.03. I've split that code into consumable
chunks and dropped as much unnecessary stuff as I can. I've also tried
to sync the device trees as much as possible with the support that will
land in Linux 6.0 although there are still some differences

Changes in v4:
- Collect r-by from Stefan
- Remove unused mvebu_get_nand_clock() (will return in a later series)
- Remove unnecessary #ifdefs
- Misc style cleanups
- Replace CONFIG_MVEBU_SAR with simpler code implemented directly in
  soc.c based around get_sar_freq which the 32-bit platforms already
  use.
- Move CONFIG_DISPLAY_BOARDINFO_LATE and CONFIG_ENV_OVERWRITE to
  the defconfig.
- Remove CONFIG_BAUDRATE as this is already set in the default config
- Remove CONFIG_USB_MAX_CONTROLLER_COUNT as this is not needed with
  DM_USB
- Remove CONFIG_PREBOOT as we don't have anything to run
- Remove commented out CONFIG_BOARD_EARLY_INIT_R
- Remove DEBUG_UART configuration
- Remove unnecessary console environment variable
- Remove CONFIG_MVEBU_SAR

Changes in v3:
- Remove unnecessary changes to RX descriptor handling
- Use dev_get_dma_range() to parse dma-ranges property from parent
  device.
- Remove unnecessary dma-ranges property from ethernet nodes (mvneta now
  correctly parses the property from the parent node).
- Keep soc_print_clock_info and soc_print_device_info local to
  alleycat5.
- Remove MMC and UBIFS distroboot options (MMC driver is not currently
  functional, NAND is not populated on the RD-AC5X board)
- Remove unnecessary Ethernet configuration
- Remove unnecessary NAND configuration
- Remove memory node from dts so the value passed by the DDR FW will be
  used

Changes in v2:
- Use distro boot by default
- remove unnecessary SPI-NOR partitions

Chris Packham (5):
  net: mvneta: Add support for AlleyCat5
  usb: ehci: ehci-marvell: Support for marvell,ac5-ehci
  pinctrl: mvebu: Add AlleyCat5 support
  arm: mvebu: Support for 98DX25xx/98DX35xx SoC
  arm: mvebu: Add RD-AC5X board

 arch/arm/dts/Makefile                      |   3 +-
 arch/arm/dts/ac5-98dx25xx.dtsi             | 277 +++++++++++++++++++
 arch/arm/dts/ac5-98dx35xx-rd.dts           | 129 +++++++++
 arch/arm/dts/ac5-98dx35xx.dtsi             |  17 ++
 arch/arm/mach-mvebu/Kconfig                |  13 +-
 arch/arm/mach-mvebu/Makefile               |   1 +
 arch/arm/mach-mvebu/alleycat5/Makefile     |   8 +
 arch/arm/mach-mvebu/alleycat5/cpu.c        | 124 +++++++++
 arch/arm/mach-mvebu/alleycat5/soc.c        | 298 +++++++++++++++++++++
 arch/arm/mach-mvebu/alleycat5/soc.h        |   7 +
 arch/arm/mach-mvebu/arm64-common.c         |   5 +
 arch/arm/mach-mvebu/include/mach/cpu.h     |   4 +
 board/Marvell/mvebu_alleycat-5/MAINTAINERS |   6 +
 board/Marvell/mvebu_alleycat-5/Makefile    |   3 +
 board/Marvell/mvebu_alleycat-5/board.c     |  28 ++
 configs/mvebu_ac5_rd_defconfig             |  84 ++++++
 drivers/net/Kconfig                        |   2 +-
 drivers/net/mvneta.c                       |  43 ++-
 drivers/pinctrl/mvebu/Kconfig              |   2 +-
 drivers/usb/host/Kconfig                   |   1 +
 drivers/usb/host/ehci-marvell.c            |  57 +++-
 include/configs/mvebu_alleycat-5.h         |  42 +++
 22 files changed, 1139 insertions(+), 15 deletions(-)
 create mode 100644 arch/arm/dts/ac5-98dx25xx.dtsi
 create mode 100644 arch/arm/dts/ac5-98dx35xx-rd.dts
 create mode 100644 arch/arm/dts/ac5-98dx35xx.dtsi
 create mode 100644 arch/arm/mach-mvebu/alleycat5/Makefile
 create mode 100644 arch/arm/mach-mvebu/alleycat5/cpu.c
 create mode 100644 arch/arm/mach-mvebu/alleycat5/soc.c
 create mode 100644 arch/arm/mach-mvebu/alleycat5/soc.h
 create mode 100644 board/Marvell/mvebu_alleycat-5/MAINTAINERS
 create mode 100644 board/Marvell/mvebu_alleycat-5/Makefile
 create mode 100644 board/Marvell/mvebu_alleycat-5/board.c
 create mode 100644 configs/mvebu_ac5_rd_defconfig
 create mode 100644 include/configs/mvebu_alleycat-5.h

-- 
2.37.3

[PATCH v4 1/5] net: mvneta: Add support for AlleyCat5

[Chris Packham]

Add support for the AlleyCat5 SoC. This lacks the mbus from the other
users of the mvneta.c driver so a new compatible string is needed to
allow for a different window configuration.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
---

(no changes since v3)

Changes in v3:
- Remove unnecessary changes to RX descriptor handling
- Use dev_get_dma_range() to parse dma-ranges property from parent
  device.

 drivers/net/Kconfig  |  2 +-
 drivers/net/mvneta.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 43 insertions(+), 2 deletions(-)

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 6bbbadc5ee..8df3dce6df 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -448,7 +448,7 @@ config MVGBE
 
 config MVNETA
 	bool "Marvell Armada XP/385/3700 network interface support"
-	depends on ARMADA_XP || ARMADA_38X || ARMADA_3700
+	depends on ARMADA_XP || ARMADA_38X || ARMADA_3700 || ALLEYCAT_5
 	select PHYLIB
 	select DM_MDIO
 	help
diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
index d2c42c4396..0fbfad11d4 100644
--- a/drivers/net/mvneta.c
+++ b/drivers/net/mvneta.c
@@ -91,6 +91,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MVNETA_WIN_SIZE_MASK			(0xffff0000)
 #define MVNETA_BASE_ADDR_ENABLE                 0x2290
 #define      MVNETA_BASE_ADDR_ENABLE_BIT	0x1
+#define      MVNETA_AC5_CNM_DDR_TARGET		0x2
+#define      MVNETA_AC5_CNM_DDR_ATTR		0xb
 #define MVNETA_PORT_ACCESS_PROTECT              0x2294
 #define      MVNETA_PORT_ACCESS_PROTECT_WIN0_RW	0x3
 #define MVNETA_PORT_CONFIG                      0x2400
@@ -282,6 +284,8 @@ struct mvneta_port {
 	struct gpio_desc phy_reset_gpio;
 	struct gpio_desc sfp_tx_disable_gpio;
 #endif
+
+	uintptr_t dma_base;     /* base address for DMA address decoding */
 };
 
 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
@@ -1343,6 +1347,29 @@ static void mvneta_conf_mbus_windows(struct mvneta_port *pp)
 	mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
 }
 
+static void mvneta_conf_ac5_cnm_xbar_windows(struct mvneta_port *pp)
+{
+	int i;
+
+	/* Clear all windows */
+	for (i = 0; i < 6; i++) {
+		mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
+		mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
+
+		if (i < 4)
+			mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
+	}
+
+	/*
+	 * Setup window #0 base 0x0 to target XBAR port 2 (AMB2), attribute 0xb, size 4GB
+	 * AMB2 address decoder remaps 0x0 to DDR 64 bit base address
+	 */
+	mvreg_write(pp, MVNETA_WIN_BASE(0),
+		    (MVNETA_AC5_CNM_DDR_ATTR << 8) | MVNETA_AC5_CNM_DDR_TARGET);
+	mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000);
+	mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, 0x3e);
+}
+
 /* Power up the port */
 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
 {
@@ -1525,7 +1552,7 @@ static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp)
 		 * No cache invalidation needed here, since the rx_buffer's are
 		 * located in a uncached memory region
 		 */
-		*packetp = data;
+		*packetp = data + pp->dma_base;
 
 		/*
 		 * Only mark one descriptor as free
@@ -1544,6 +1571,10 @@ static int mvneta_probe(struct udevice *dev)
 	struct ofnode_phandle_args sfp_args;
 #endif
 	void *bd_space;
+	phys_addr_t cpu;
+	dma_addr_t bus;
+	u64 size;
+	int ret;
 
 	/*
 	 * Allocate buffer area for descs and rx_buffers. This is only
@@ -1577,9 +1608,18 @@ static int mvneta_probe(struct udevice *dev)
 	/* Configure MBUS address windows */
 	if (device_is_compatible(dev, "marvell,armada-3700-neta"))
 		mvneta_bypass_mbus_windows(pp);
+	else if (device_is_compatible(dev, "marvell,armada-ac5-neta"))
+		mvneta_conf_ac5_cnm_xbar_windows(pp);
 	else
 		mvneta_conf_mbus_windows(pp);
 
+	/* fetch dma ranges property */
+	ret = dev_get_dma_range(dev, &cpu, &bus, &size);
+	if (!ret)
+		pp->dma_base = cpu;
+	else
+		pp->dma_base = 0;
+
 #if CONFIG_IS_ENABLED(DM_GPIO)
 	if (!dev_read_phandle_with_args(dev, "sfp", NULL, 0, 0, &sfp_args) &&
 	    ofnode_is_enabled(sfp_args.node))
@@ -1620,6 +1660,7 @@ static const struct eth_ops mvneta_ops = {
 
 static const struct udevice_id mvneta_ids[] = {
 	{ .compatible = "marvell,armada-370-neta" },
+	{ .compatible = "marvell,armada-ac5-neta" },
 	{ .compatible = "marvell,armada-xp-neta" },
 	{ .compatible = "marvell,armada-3700-neta" },
 	{ }
-- 
2.37.3

[PATCH v4 2/5] usb: ehci: ehci-marvell: Support for marvell,ac5-ehci

[Chris Packham]

Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
the fact that the ac5 does not have the mbus infrastructure the 32-bit
SoCs have and ensure USB_EHCI_IS_TDI is selected.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
---

(no changes since v1)

 drivers/usb/host/Kconfig        |  1 +
 drivers/usb/host/ehci-marvell.c | 57 +++++++++++++++++++++++++++------
 2 files changed, 48 insertions(+), 10 deletions(-)

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index a0f48f09a7..628078f495 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -178,6 +178,7 @@ config USB_EHCI_MARVELL
 	depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X
 	default y
 	select USB_EHCI_IS_TDI if !ARM64
+	select USB_EHCI_IS_TDI if ALLEYCAT_5
 	---help---
 	  Enables support for the on-chip EHCI controller on MVEBU SoCs.
 
diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
index b7e60c690a..7d859b9cce 100644
--- a/drivers/usb/host/ehci-marvell.c
+++ b/drivers/usb/host/ehci-marvell.c
@@ -48,12 +48,17 @@ struct ehci_mvebu_priv {
 	fdt_addr_t hcd_base;
 };
 
+#define USB_TO_DRAM_TARGET_ID 0x2
+#define USB_TO_DRAM_ATTR_ID 0x0
+#define USB_DRAM_BASE 0x00000000
+#define USB_DRAM_SIZE 0xfff	/* don't overrun u-boot source (was 0xffff) */
+
 /*
  * Once all the older Marvell SoC's (Orion, Kirkwood) are converted
  * to the common mvebu archticture including the mbus setup, this
  * will be the only function needed to configure the access windows
  */
-static void usb_brg_adrdec_setup(void *base)
+static void usb_brg_adrdec_setup(struct udevice *dev, void *base)
 {
 	const struct mbus_dram_target_info *dram;
 	int i;
@@ -65,16 +70,34 @@ static void usb_brg_adrdec_setup(void *base)
 		writel(0, base + USB_WINDOW_BASE(i));
 	}
 
-	for (i = 0; i < dram->num_cs; i++) {
-		const struct mbus_dram_window *cs = dram->cs + i;
+	if (device_is_compatible(dev, "marvell,ac5-ehci")) {
+		/*
+		 * use decoding window to map dram address seen by usb to 0x0
+		 */
 
 		/* Write size, attributes and target id to control register */
-		writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
-		       (dram->mbus_dram_target_id << 4) | 1,
-		       base + USB_WINDOW_CTRL(i));
+		writel((USB_DRAM_SIZE << 16) | (USB_TO_DRAM_ATTR_ID << 8) |
+			   (USB_TO_DRAM_TARGET_ID << 4) | 1,
+			   base + USB_WINDOW_CTRL(0));
 
 		/* Write base address to base register */
-		writel(cs->base, base + USB_WINDOW_BASE(i));
+		writel(USB_DRAM_BASE, base + USB_WINDOW_BASE(0));
+
+		debug("## AC5 decoding windows, ctrl[%p]=0x%x, base[%p]=0x%x\n",
+		      base + USB_WINDOW_CTRL(0), readl(base + USB_WINDOW_CTRL(0)),
+		      base + USB_WINDOW_BASE(0), readl(base + USB_WINDOW_BASE(0)));
+	} else {
+		for (i = 0; i < dram->num_cs; i++) {
+			const struct mbus_dram_window *cs = dram->cs + i;
+
+			/* Write size, attributes and target id to control register */
+			writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
+				   (dram->mbus_dram_target_id << 4) | 1,
+				   base + USB_WINDOW_CTRL(i));
+
+			/* Write base address to base register */
+			writel(cs->base, base + USB_WINDOW_BASE(i));
+		}
 	}
 }
 
@@ -126,15 +149,28 @@ static int ehci_mvebu_probe(struct udevice *dev)
 	if (device_is_compatible(dev, "marvell,armada-3700-ehci"))
 		marvell_ehci_ops.powerup_fixup = marvell_ehci_powerup_fixup;
 	else
-		usb_brg_adrdec_setup((void *)priv->hcd_base);
+		usb_brg_adrdec_setup(dev, (void *)priv->hcd_base);
 
 	hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100);
 	hcor = (struct ehci_hcor *)
 		((uintptr_t)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
 
 	debug("ehci-marvell: init hccr %lx and hcor %lx hc_length %ld\n",
-	      (uintptr_t)hccr, (uintptr_t)hcor,
-	      (uintptr_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+		  (uintptr_t)hccr, (uintptr_t)hcor,
+		  (uintptr_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+#define PHY_CALIB_OFFSET 0x808
+	/*
+	 * Trigger calibration during each usb start/reset:
+	 * BIT 13 to 0, and then to 1
+	 */
+	if (device_is_compatible(dev, "marvell,ac5-ehci")) {
+		void *phy_calib_reg = (void *)(priv->hcd_base + PHY_CALIB_OFFSET);
+		u32 val = readl(phy_calib_reg) & (~BIT(13));
+
+		writel(val, phy_calib_reg);
+		writel(val | BIT(13), phy_calib_reg);
+	}
 
 	return ehci_register(dev, hccr, hcor, &marvell_ehci_ops, 0,
 			     USB_INIT_HOST);
@@ -143,6 +179,7 @@ static int ehci_mvebu_probe(struct udevice *dev)
 static const struct udevice_id ehci_usb_ids[] = {
 	{ .compatible = "marvell,orion-ehci", },
 	{ .compatible = "marvell,armada-3700-ehci", },
+	{ .compatible = "marvell,ac5-ehci", },
 	{ }
 };
 
-- 
2.37.3

Re: [PATCH v4 2/5] usb: ehci: ehci-marvell: Support for marvell,ac5-ehci

[Stefan Roese]

On 22.09.22 05:31, Chris Packham wrote:
> Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
> block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
> the fact that the ac5 does not have the mbus infrastructure the 32-bit
> SoCs have and ensure USB_EHCI_IS_TDI is selected.
> 
> Signed-off-by: Chris Packham <judge.packham@gmail.com>
> ---
> 
> (no changes since v1)
> 
>   drivers/usb/host/Kconfig        |  1 +
>   drivers/usb/host/ehci-marvell.c | 57 +++++++++++++++++++++++++++------
>   2 files changed, 48 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index a0f48f09a7..628078f495 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -178,6 +178,7 @@ config USB_EHCI_MARVELL
>   	depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X
>   	default y
>   	select USB_EHCI_IS_TDI if !ARM64
> +	select USB_EHCI_IS_TDI if ALLEYCAT_5
>   	---help---
>   	  Enables support for the on-chip EHCI controller on MVEBU SoCs.
>   
> diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
> index b7e60c690a..7d859b9cce 100644
> --- a/drivers/usb/host/ehci-marvell.c
> +++ b/drivers/usb/host/ehci-marvell.c
> @@ -48,12 +48,17 @@ struct ehci_mvebu_priv {
>   	fdt_addr_t hcd_base;
>   };
>   
> +#define USB_TO_DRAM_TARGET_ID 0x2
> +#define USB_TO_DRAM_ATTR_ID 0x0
> +#define USB_DRAM_BASE 0x00000000
> +#define USB_DRAM_SIZE 0xfff	/* don't overrun u-boot source (was 0xffff) */
> +
>   /*
>    * Once all the older Marvell SoC's (Orion, Kirkwood) are converted
>    * to the common mvebu archticture including the mbus setup, this
>    * will be the only function needed to configure the access windows
>    */
> -static void usb_brg_adrdec_setup(void *base)
> +static void usb_brg_adrdec_setup(struct udevice *dev, void *base)
>   {
>   	const struct mbus_dram_target_info *dram;
>   	int i;
> @@ -65,16 +70,34 @@ static void usb_brg_adrdec_setup(void *base)
>   		writel(0, base + USB_WINDOW_BASE(i));
>   	}
>   
> -	for (i = 0; i < dram->num_cs; i++) {
> -		const struct mbus_dram_window *cs = dram->cs + i;
> +	if (device_is_compatible(dev, "marvell,ac5-ehci")) {
> +		/*
> +		 * use decoding window to map dram address seen by usb to 0x0
> +		 */
>   
>   		/* Write size, attributes and target id to control register */
> -		writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
> -		       (dram->mbus_dram_target_id << 4) | 1,
> -		       base + USB_WINDOW_CTRL(i));
> +		writel((USB_DRAM_SIZE << 16) | (USB_TO_DRAM_ATTR_ID << 8) |
> +			   (USB_TO_DRAM_TARGET_ID << 4) | 1,
> +			   base + USB_WINDOW_CTRL(0));

Nitpicking / coding-style comment: Not aligned with the '(' in the
line above. I assume that checkpatch.pl will complain here.

>   
>   		/* Write base address to base register */
> -		writel(cs->base, base + USB_WINDOW_BASE(i));
> +		writel(USB_DRAM_BASE, base + USB_WINDOW_BASE(0));
> +
> +		debug("## AC5 decoding windows, ctrl[%p]=0x%x, base[%p]=0x%x\n",
> +		      base + USB_WINDOW_CTRL(0), readl(base + USB_WINDOW_CTRL(0)),
> +		      base + USB_WINDOW_BASE(0), readl(base + USB_WINDOW_BASE(0)));
> +	} else {
> +		for (i = 0; i < dram->num_cs; i++) {
> +			const struct mbus_dram_window *cs = dram->cs + i;
> +
> +			/* Write size, attributes and target id to control register */
> +			writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
> +				   (dram->mbus_dram_target_id << 4) | 1,
> +				   base + USB_WINDOW_CTRL(i));
> +
> +			/* Write base address to base register */
> +			writel(cs->base, base + USB_WINDOW_BASE(i));
> +		}
>   	}
>   }
>   
> @@ -126,15 +149,28 @@ static int ehci_mvebu_probe(struct udevice *dev)
>   	if (device_is_compatible(dev, "marvell,armada-3700-ehci"))
>   		marvell_ehci_ops.powerup_fixup = marvell_ehci_powerup_fixup;
>   	else
> -		usb_brg_adrdec_setup((void *)priv->hcd_base);
> +		usb_brg_adrdec_setup(dev, (void *)priv->hcd_base);
>   
>   	hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100);
>   	hcor = (struct ehci_hcor *)
>   		((uintptr_t)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
>   
>   	debug("ehci-marvell: init hccr %lx and hcor %lx hc_length %ld\n",
> -	      (uintptr_t)hccr, (uintptr_t)hcor,
> -	      (uintptr_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
> +		  (uintptr_t)hccr, (uintptr_t)hcor,
> +		  (uintptr_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));

Unrelated change of indentation (see above).

> +
> +#define PHY_CALIB_OFFSET 0x808
> +	/*
> +	 * Trigger calibration during each usb start/reset:
> +	 * BIT 13 to 0, and then to 1
> +	 */
> +	if (device_is_compatible(dev, "marvell,ac5-ehci")) {
> +		void *phy_calib_reg = (void *)(priv->hcd_base + PHY_CALIB_OFFSET);
> +		u32 val = readl(phy_calib_reg) & (~BIT(13));
> +
> +		writel(val, phy_calib_reg);
> +		writel(val | BIT(13), phy_calib_reg);
> +	}
>   
>   	return ehci_register(dev, hccr, hcor, &marvell_ehci_ops, 0,
>   			     USB_INIT_HOST);
> @@ -143,6 +179,7 @@ static int ehci_mvebu_probe(struct udevice *dev)
>   static const struct udevice_id ehci_usb_ids[] = {
>   	{ .compatible = "marvell,orion-ehci", },
>   	{ .compatible = "marvell,armada-3700-ehci", },
> +	{ .compatible = "marvell,ac5-ehci", },
>   	{ }
>   };
>   

Other than this:

Reviewed-by: Stefan Roese <sr@denx.de>

Thanks,
Stefan

Re: [PATCH v4 2/5] usb: ehci: ehci-marvell: Support for marvell, ac5-ehci

[Chris Packham]

On Thu, Sep 22, 2022 at 5:18 PM Stefan Roese <sr@denx.de> wrote:
>
> On 22.09.22 05:31, Chris Packham wrote:
> > Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
> > block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
> > the fact that the ac5 does not have the mbus infrastructure the 32-bit
> > SoCs have and ensure USB_EHCI_IS_TDI is selected.
> >
> > Signed-off-by: Chris Packham <judge.packham@gmail.com>
> > ---
> >
> > (no changes since v1)
> >
> >   drivers/usb/host/Kconfig        |  1 +
> >   drivers/usb/host/ehci-marvell.c | 57 +++++++++++++++++++++++++++------
> >   2 files changed, 48 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> > index a0f48f09a7..628078f495 100644
> > --- a/drivers/usb/host/Kconfig
> > +++ b/drivers/usb/host/Kconfig
> > @@ -178,6 +178,7 @@ config USB_EHCI_MARVELL
> >       depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X
> >       default y
> >       select USB_EHCI_IS_TDI if !ARM64
> > +     select USB_EHCI_IS_TDI if ALLEYCAT_5
> >       ---help---
> >         Enables support for the on-chip EHCI controller on MVEBU SoCs.
> >
> > diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
> > index b7e60c690a..7d859b9cce 100644
> > --- a/drivers/usb/host/ehci-marvell.c
> > +++ b/drivers/usb/host/ehci-marvell.c
> > @@ -48,12 +48,17 @@ struct ehci_mvebu_priv {
> >       fdt_addr_t hcd_base;
> >   };
> >
> > +#define USB_TO_DRAM_TARGET_ID 0x2
> > +#define USB_TO_DRAM_ATTR_ID 0x0
> > +#define USB_DRAM_BASE 0x00000000
> > +#define USB_DRAM_SIZE 0xfff  /* don't overrun u-boot source (was 0xffff) */
> > +
> >   /*
> >    * Once all the older Marvell SoC's (Orion, Kirkwood) are converted
> >    * to the common mvebu archticture including the mbus setup, this
> >    * will be the only function needed to configure the access windows
> >    */
> > -static void usb_brg_adrdec_setup(void *base)
> > +static void usb_brg_adrdec_setup(struct udevice *dev, void *base)
> >   {
> >       const struct mbus_dram_target_info *dram;
> >       int i;
> > @@ -65,16 +70,34 @@ static void usb_brg_adrdec_setup(void *base)
> >               writel(0, base + USB_WINDOW_BASE(i));
> >       }
> >
> > -     for (i = 0; i < dram->num_cs; i++) {
> > -             const struct mbus_dram_window *cs = dram->cs + i;
> > +     if (device_is_compatible(dev, "marvell,ac5-ehci")) {
> > +             /*
> > +              * use decoding window to map dram address seen by usb to 0x0
> > +              */
> >
> >               /* Write size, attributes and target id to control register */
> > -             writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
> > -                    (dram->mbus_dram_target_id << 4) | 1,
> > -                    base + USB_WINDOW_CTRL(i));
> > +             writel((USB_DRAM_SIZE << 16) | (USB_TO_DRAM_ATTR_ID << 8) |
> > +                        (USB_TO_DRAM_TARGET_ID << 4) | 1,
> > +                        base + USB_WINDOW_CTRL(0));
>
> Nitpicking / coding-style comment: Not aligned with the '(' in the
> line above. I assume that checkpatch.pl will complain here.
>

Doesn't seem to complain about this (ran manually and via patman).
I'll fix it regardless.

> >
> >               /* Write base address to base register */
> > -             writel(cs->base, base + USB_WINDOW_BASE(i));
> > +             writel(USB_DRAM_BASE, base + USB_WINDOW_BASE(0));
> > +
> > +             debug("## AC5 decoding windows, ctrl[%p]=0x%x, base[%p]=0x%x\n",
> > +                   base + USB_WINDOW_CTRL(0), readl(base + USB_WINDOW_CTRL(0)),
> > +                   base + USB_WINDOW_BASE(0), readl(base + USB_WINDOW_BASE(0)));
> > +     } else {
> > +             for (i = 0; i < dram->num_cs; i++) {
> > +                     const struct mbus_dram_window *cs = dram->cs + i;
> > +
> > +                     /* Write size, attributes and target id to control register */
> > +                     writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
> > +                                (dram->mbus_dram_target_id << 4) | 1,
> > +                                base + USB_WINDOW_CTRL(i));
> > +
> > +                     /* Write base address to base register */
> > +                     writel(cs->base, base + USB_WINDOW_BASE(i));
> > +             }
> >       }
> >   }
> >
> > @@ -126,15 +149,28 @@ static int ehci_mvebu_probe(struct udevice *dev)
> >       if (device_is_compatible(dev, "marvell,armada-3700-ehci"))
> >               marvell_ehci_ops.powerup_fixup = marvell_ehci_powerup_fixup;
> >       else
> > -             usb_brg_adrdec_setup((void *)priv->hcd_base);
> > +             usb_brg_adrdec_setup(dev, (void *)priv->hcd_base);
> >
> >       hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100);
> >       hcor = (struct ehci_hcor *)
> >               ((uintptr_t)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
> >
> >       debug("ehci-marvell: init hccr %lx and hcor %lx hc_length %ld\n",
> > -           (uintptr_t)hccr, (uintptr_t)hcor,
> > -           (uintptr_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
> > +               (uintptr_t)hccr, (uintptr_t)hcor,
> > +               (uintptr_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
>
> Unrelated change of indentation (see above).
>

Yep will remove

> > +
> > +#define PHY_CALIB_OFFSET 0x808
> > +     /*
> > +      * Trigger calibration during each usb start/reset:
> > +      * BIT 13 to 0, and then to 1
> > +      */
> > +     if (device_is_compatible(dev, "marvell,ac5-ehci")) {
> > +             void *phy_calib_reg = (void *)(priv->hcd_base + PHY_CALIB_OFFSET);
> > +             u32 val = readl(phy_calib_reg) & (~BIT(13));
> > +
> > +             writel(val, phy_calib_reg);
> > +             writel(val | BIT(13), phy_calib_reg);
> > +     }
> >
> >       return ehci_register(dev, hccr, hcor, &marvell_ehci_ops, 0,
> >                            USB_INIT_HOST);
> > @@ -143,6 +179,7 @@ static int ehci_mvebu_probe(struct udevice *dev)
> >   static const struct udevice_id ehci_usb_ids[] = {
> >       { .compatible = "marvell,orion-ehci", },
> >       { .compatible = "marvell,armada-3700-ehci", },
> > +     { .compatible = "marvell,ac5-ehci", },
> >       { }
> >   };
> >
>
> Other than this:
>
> Reviewed-by: Stefan Roese <sr@denx.de>
>
> Thanks,
> Stefan

[PATCH v4 3/5] pinctrl: mvebu: Add AlleyCat5 support

[Chris Packham]

This uses the same IP block as the Armada-8K SoCs.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
---

Changes in v4:
- Collect r-by from Stefan

 drivers/pinctrl/mvebu/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index 574fb4dfb0..7c51d138c8 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -15,7 +15,7 @@ config PINCTRL_ARMADA_37XX
 	   Marvell's Armada-37xx SoC.
 
 config PINCTRL_ARMADA_8K
-	depends on ARMADA_8K && PINCTRL_FULL
+	depends on (ARMADA_8K || ALLEYCAT_5) && PINCTRL_FULL
 	bool "Armada 7k/8k pin control driver"
 	help
 	   Support pin multiplexing and pin configuration control on
-- 
2.37.3

[PATCH v4 4/5] arm: mvebu: Support for 98DX25xx/98DX35xx SoC

[Chris Packham]

Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with
an integrated CPU (referred to as the CnM block in Marvell's
documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support
has been ported from Marvell's SDK which is based on a much older
version of U-Boot.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
---

Changes in v4:
- Remove unused mvebu_get_nand_clock() (will return in a later series)
- Remove unnecessary #ifdefs
- Misc style cleanups
- Replace CONFIG_MVEBU_SAR with simpler code implemented directly in
  soc.c based around get_sar_freq which the 32-bit platforms already
  use.

Changes in v3:
- Remove unnecessary dma-ranges property from ethernet nodes (mvneta now
  correctly parses the property from the parent node).
- Keep soc_print_clock_info and soc_print_device_info local to
  alleycat5.

 arch/arm/dts/ac5-98dx25xx.dtsi         | 277 +++++++++++++++++++++++
 arch/arm/dts/ac5-98dx35xx.dtsi         |  17 ++
 arch/arm/mach-mvebu/Kconfig            |   4 +
 arch/arm/mach-mvebu/Makefile           |   1 +
 arch/arm/mach-mvebu/alleycat5/Makefile |   8 +
 arch/arm/mach-mvebu/alleycat5/cpu.c    | 124 ++++++++++
 arch/arm/mach-mvebu/alleycat5/soc.c    | 298 +++++++++++++++++++++++++
 arch/arm/mach-mvebu/alleycat5/soc.h    |   7 +
 arch/arm/mach-mvebu/arm64-common.c     |   5 +
 arch/arm/mach-mvebu/include/mach/cpu.h |   4 +
 10 files changed, 745 insertions(+)
 create mode 100644 arch/arm/dts/ac5-98dx25xx.dtsi
 create mode 100644 arch/arm/dts/ac5-98dx35xx.dtsi
 create mode 100644 arch/arm/mach-mvebu/alleycat5/Makefile
 create mode 100644 arch/arm/mach-mvebu/alleycat5/cpu.c
 create mode 100644 arch/arm/mach-mvebu/alleycat5/soc.c
 create mode 100644 arch/arm/mach-mvebu/alleycat5/soc.h

diff --git a/arch/arm/dts/ac5-98dx25xx.dtsi b/arch/arm/dts/ac5-98dx25xx.dtsi
new file mode 100644
index 0000000000..3c68355f32
--- /dev/null
+++ b/arch/arm/dts/ac5-98dx25xx.dtsi
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree For AC5.
+ *
+ * Copyright (C) 2021 Marvell
+ * Copyright (C) 2022 Allied Telesis Labs
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	model = "Marvell AC5 SoC";
+	compatible = "marvell,ac5";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache {
+			compatible = "cache";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		dma-ranges;
+
+		internal-regs@7f000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			/* 16M internal register @ 0x7f00_0000 */
+			ranges = <0x0 0x0 0x7f000000 0x1000000>;
+			dma-coherent;
+
+			uart0: serial@12000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x12000 0x100>;
+				reg-shift = <2>;
+				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+				reg-io-width = <1>;
+				clocks = <&cnm_clock>;
+				status = "okay";
+			};
+
+			uart1: serial@12100 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x12100 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				clocks = <&cnm_clock>;
+				status = "disabled";
+			};
+
+			uart2: serial@12200 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x12200 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				clocks = <&cnm_clock>;
+				status = "disabled";
+			};
+
+			uart3: serial@12300 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x12300 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				clocks = <&cnm_clock>;
+				status = "disabled";
+			};
+
+			mdio: mdio@22004 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "marvell,orion-mdio";
+				reg = <0x22004 0x4>;
+				clocks = <&cnm_clock>;
+			};
+
+			i2c0: i2c@11000 {
+				compatible = "marvell,mv78230-i2c";
+				reg = <0x11000 0x20>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				clocks = <&cnm_clock>;
+				clock-names = "core";
+				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+				clock-frequency=<100000>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@11100 {
+				compatible = "marvell,mv78230-i2c";
+				reg = <0x11100 0x20>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				clocks = <&cnm_clock>;
+				clock-names = "core";
+				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+				clock-frequency=<100000>;
+				status = "disabled";
+			};
+
+			gpio0: gpio@18100 {
+				compatible = "marvell,orion-gpio";
+				reg = <0x18100 0x40>;
+				ngpios = <32>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				status = "okay";
+			};
+
+			gpio1: gpio@18140 {
+				reg = <0x18140 0x40>;
+				compatible = "marvell,orion-gpio";
+				ngpios = <14>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				status = "okay";
+			};
+		};
+
+		/*
+		 * Dedicated section for devices behind 32bit controllers so we
+		 * can configure specific DMA mapping for them
+		 */
+		behind-32bit-controller@7f000000 {
+			compatible = "simple-bus";
+			#address-cells = <0x2>;
+			#size-cells = <0x2>;
+			ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
+			/* Host phy ram starts at 0x200M */
+			dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
+			dma-coherent;
+
+			eth0: ethernet@20000 {
+				compatible = "marvell,armada-ac5-neta";
+				reg = <0x0 0x20000 0x0 0x4000>;
+				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cnm_clock>;
+				phy-mode = "sgmii";
+				status = "disabled";
+			};
+
+			eth1: ethernet@24000 {
+				compatible = "marvell,armada-ac5-neta";
+				reg = <0x0 0x24000 0x0 0x4000>;
+				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cnm_clock>;
+				phy-mode = "sgmii";
+				status = "disabled";
+			};
+
+			usb0: usb@80000 {
+				compatible = "marvell,ac5-ehci";
+				reg = <0x0 0x80000 0x0 0x500>;
+				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			usb1: usb@a0000 {
+				compatible = "marvell,ac5-ehci";
+				reg = <0x0 0xa0000 0x0 0x500>;
+				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+
+		pinctrl0: pinctrl@80020100 {
+			compatible = "marvell,mvebu-pinctrl";
+			reg = <0 0x80020100 0 0x20>;
+			pin-count = <46>;
+			max-func = <0xf>;
+			status = "okay";
+		};
+
+		spi0: spi@805a0000 {
+			compatible = "marvell,armada-3700-spi";
+			reg = <0x0 0x805a0000 0x0 0x50>;
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			clocks = <&spi_clock>;
+			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+			num-cs = <1>;
+			status = "disabled";
+		};
+
+		spi1: spi@805a8000 {
+			compatible = "marvell,armada-3700-spi";
+			reg = <0x0 0x805a8000 0x0 0x50>;
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			clocks = <&spi_clock>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			num-cs = <1>;
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@80600000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
+			      <0x0 0x80660000 0x0 0x40000>; /* GICR */
+			interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+
+	clocks {
+		cnm_clock: cnm-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <328000000>;
+		};
+
+		spi_clock: spi-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+		};
+	};
+};
diff --git a/arch/arm/dts/ac5-98dx35xx.dtsi b/arch/arm/dts/ac5-98dx35xx.dtsi
new file mode 100644
index 0000000000..2ab72f854b
--- /dev/null
+++ b/arch/arm/dts/ac5-98dx35xx.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree For AC5X.
+ *
+ * Copyright (C) 2022 Allied Telesis Labs
+ */
+
+#include "ac5-98dx25xx.dtsi"
+
+/ {
+	model = "Marvell AC5X SoC";
+	compatible = "marvell,ac5x", "marvell,ac5";
+};
+
+&cnm_clock {
+	clock-frequency = <325000000>;
+};
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index a81b8e2b0d..45efa24194 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -49,6 +49,10 @@ config ARMADA_8K
 	bool
 	select ARM64
 
+config ALLEYCAT_5
+	bool
+	select ARM64
+
 # Armada PLL frequency (used for NAND clock generation)
 config SYS_MVEBU_PLL_CLOCK
 	int
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 103e64cf20..f7d7f5f8ef 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -6,6 +6,7 @@ ifdef CONFIG_ARM64
 
 obj-$(CONFIG_ARMADA_3700) += armada3700/
 obj-$(CONFIG_ARMADA_8K) += armada8k/
+obj-$(CONFIG_ALLEYCAT_5) += alleycat5/
 obj-y += arm64-common.o
 
 else # CONFIG_ARM64
diff --git a/arch/arm/mach-mvebu/alleycat5/Makefile b/arch/arm/mach-mvebu/alleycat5/Makefile
new file mode 100644
index 0000000000..b897ad089a
--- /dev/null
+++ b/arch/arm/mach-mvebu/alleycat5/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2016 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y = cpu.o
+obj-y += soc.o
diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c
new file mode 100644
index 0000000000..cc7f9794c5
--- /dev/null
+++ b/arch/arm/mach-mvebu/alleycat5/cpu.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <linux/libfdt.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/arch/cpu.h>
+#include <linux/sizes.h>
+#include <asm/armv8/mmu.h>
+#include "soc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define RAM_SIZE	SZ_1G
+
+static struct mm_region ac5_mem_map[] = {
+	{
+		/* RAM */
+		.phys = CONFIG_SYS_SDRAM_BASE,
+		.virt = CONFIG_SYS_SDRAM_BASE,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	},
+	{
+		/* MMIO regions */
+		.phys = 0x00000000,
+		.virt = 0xa0000000,
+		.size = 0x100000,
+
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	{
+		/* MMIO regions */
+		.phys = 0x100000,
+		.virt = 0x100000,
+		.size = 0x3ff00000,
+
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	{
+		/* MMIO regions */
+		.phys = 0x7F000000,
+		.virt = 0x7F000000,
+		.size = 0x21000000,
+
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	{
+		0,
+	}
+};
+
+struct mm_region *mem_map = ac5_mem_map;
+
+void reset_cpu(void)
+{
+}
+
+int print_cpuinfo(void)
+{
+	soc_print_device_info();
+	soc_print_clock_info();
+
+	return 0;
+}
+
+int alleycat5_dram_init(void)
+{
+#define SCRATCH_PAD_REG		0x80010018
+	int ret;
+
+	/* override DDR_FW size if DTS is set with size */
+	ret = fdtdec_setup_mem_size_base();
+	if (ret == -EINVAL)
+		gd->ram_size = readl(SCRATCH_PAD_REG) * 4ULL;
+
+	/* if DRAM size == 0, print error message */
+	if (gd->ram_size == 0) {
+		pr_err("DRAM size not initialized - check DRAM configuration\n");
+		printf("\n Using temporary DRAM size of 512MB.\n\n");
+		gd->ram_size = SZ_512M;
+	}
+
+	ac5_mem_map[0].size = gd->ram_size;
+
+	return 0;
+}
+
+int alleycat5_dram_init_banksize(void)
+{
+	/*
+	 * Config single DRAM bank
+	 */
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
+}
+
+int timer_init(void)
+{
+	return 0;
+}
+
+/*
+ * get_ref_clk
+ *
+ * return: reference clock in MHz
+ */
+u32 get_ref_clk(void)
+{
+	return 25;
+}
diff --git a/arch/arm/mach-mvebu/alleycat5/soc.c b/arch/arm/mach-mvebu/alleycat5/soc.c
new file mode 100644
index 0000000000..b84e4ac145
--- /dev/null
+++ b/arch/arm/mach-mvebu/alleycat5/soc.c
@@ -0,0 +1,298 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ */
+
+#include <common.h>
+#include <asm/arch-armada8k/cache_llc.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <dm/device.h>
+
+#define DEVICE_ID_REG			0x7F90004C
+#define DEVICE_ID_MASK			0xffff0
+#define REV_ID_MASK			0xf
+#define DEVICE_ID_OFFSET		4
+#define REV_ID_OFFSET			0
+
+#define DEVICE_SAR_REG			0x944F8204
+
+#define DEVICE_ID_SUB_REV		(MVEBU_REGISTER(0x2400230))
+#define DEVICE_ID_SUB_REV_OFFSET	7
+#define DEVICE_ID_SUB_REV_MASK		(0xffff << DEVICE_ID_SUB_REV_OFFSET)
+
+#define AC5X_DEV_ID			0x9800
+
+struct soc_info {
+	u32 dev_id;
+	u32 rev_id;
+	char *soc_name;
+};
+
+static struct soc_info soc_info_table[] = {
+	/* Two reserved entries for unidentified devices - don't change */
+	{ 0xB4FF, 0x0, "Unidentified Alleycat5"},
+	{ 0x98FF, 0x0, "Unidentified Alleycat5x"},
+
+	{ 0xB400, 0x2, "Alleycat5-plus  98DX2538-A2"},
+	{ 0xB401, 0x2, "Alleycat5-plus  98DX2535-A2"},
+	{ 0xB402, 0x2, "Alleycat5-plus  98DX2532-A2"},
+	{ 0xB403, 0x2, "Alleycat5-plus  98DX2531-A2"},
+	{ 0xB408, 0x2, "Alleycat5  98DX2528-A2"},
+	{ 0xB409, 0x2, "Alleycat5  98DX2525-A2"},
+	{ 0xB40A, 0x2, "Alleycat5  98DX2522-A2"},
+	{ 0xB40B, 0x2, "Alleycat5  98DX2521-A2"},
+	{ 0xB410, 0x2, "Alleycat5-lite  98DX2518-A2"},
+	{ 0xB411, 0x2, "Alleycat5-lite  98DX2515-A2"},
+	{ 0xB412, 0x2, "Alleycat5-lite  98DX2512-A2"},
+	{ 0xB413, 0x2, "Alleycat5-lite  98DX2511-A2"},
+
+	{ 0xB400, 0x1, "Alleycat5-plus  98DX2538-A1"},
+	{ 0xB401, 0x1, "Alleycat5-plus  98DX2535-A1"},
+	{ 0xB402, 0x1, "Alleycat5-plus  98DX2532-A1"},
+	{ 0xB403, 0x1, "Alleycat5-plus  98DX2531-A1"},
+	{ 0xB408, 0x1, "Alleycat5  98DX2528-A1"},
+	{ 0xB409, 0x1, "Alleycat5  98DX2525-A1"},
+	{ 0xB40A, 0x1, "Alleycat5  98DX2522-A1"},
+	{ 0xB40B, 0x1, "Alleycat5  98DX2521-A1"},
+	{ 0xB410, 0x1, "Alleycat5-lite  98DX2518-A1"},
+	{ 0xB411, 0x1, "Alleycat5-lite  98DX2515-A1"},
+	{ 0xB412, 0x1, "Alleycat5-lite  98DX2512-A1"},
+	{ 0xB413, 0x1, "Alleycat5-lite  98DX2511-A1"},
+	{ 0x9800, 0x1, "Alleycat5X 98DX3500M-A1"},
+	{ 0x9806, 0x1, "Alleycat5X 98DX3501M-A1"},
+	{ 0x9801, 0x1, "Alleycat5X 98DX3510M-A1"},
+	{ 0x9802, 0x1, "Alleycat5X 98DX3520M-A1"},
+	{ 0x9803, 0x1, "Alleycat5X 98DX3530M-A1"},
+	{ 0x9804, 0x1, "Alleycat5X 98DX3540M-A1"},
+	{ 0x9805, 0x1, "Alleycat5X 98DX3550M-A1"},
+	{ 0x9820, 0x1, "Alleycat5X 98DX3500-A1"},
+	{ 0x9826, 0x1, "Alleycat5X 98DX3501-A1"},
+	{ 0x9821, 0x1, "Alleycat5X 98DX3510-A1"},
+	{ 0x9861, 0x1, "Alleycat5X 98DX3510H-A1"},
+	{ 0x9841, 0x1, "Alleycat5X 98DX3510MH-A1"},
+	{ 0x9822, 0x1, "Alleycat5X 98DX3520-A1"},
+	{ 0x9823, 0x1, "Alleycat5X 98DX3530-A1"},
+	{ 0x9863, 0x1, "Alleycat5X 98DX3530H-A1"},
+	{ 0x9824, 0x1, "Alleycat5X 98DX3540-A1"},
+	{ 0x9825, 0x1, "Alleycat5X 98DX3550-A1"},
+
+	{ 0xB400, 0x0, "Alleycat5-plus  98DX2538-A0"},
+	{ 0xB401, 0x0, "Alleycat5-plus  98DX2535-A0"},
+	{ 0xB402, 0x0, "Alleycat5-plus  98DX2532-A0"},
+	{ 0xB403, 0x0, "Alleycat5-plus  98DX2531-A0"},
+	{ 0xB408, 0x0, "Alleycat5  98DX2528-A0"},
+	{ 0xB409, 0x0, "Alleycat5  98DX2525-A0"},
+	{ 0xB40A, 0x0, "Alleycat5  98DX2522-A0"},
+	{ 0xB40B, 0x0, "Alleycat5  98DX2521-A0"},
+	{ 0xB410, 0x0, "Alleycat5-lite  98DX2518-A0"},
+	{ 0xB411, 0x0, "Alleycat5-lite  98DX2515-A0"},
+	{ 0xB412, 0x0, "Alleycat5-lite  98DX2512-A0"},
+	{ 0xB413, 0x0, "Alleycat5-lite  98DX2511-A0"},
+	{ 0x9800, 0x0, "Alleycat5X 98DX3500M-A0"},
+	{ 0x9806, 0x0, "Alleycat5X 98DX3501M-A0"},
+	{ 0x9801, 0x0, "Alleycat5X 98DX3510M-A0"},
+	{ 0x9802, 0x0, "Alleycat5X 98DX3520M-A0"},
+	{ 0x9803, 0x0, "Alleycat5X 98DX3530M-A0"},
+	{ 0x9804, 0x0, "Alleycat5X 98DX3540M-A0"},
+	{ 0x9805, 0x0, "Alleycat5X 98DX3550M-A0"},
+	{ 0x9820, 0x0, "Alleycat5X 98DX3500-A0"},
+	{ 0x9826, 0x0, "Alleycat5X 98DX3501-A0"},
+	{ 0x9821, 0x0, "Alleycat5X 98DX3510-A0"},
+	{ 0x9861, 0x0, "Alleycat5X 98DX3510H-A0"},
+	{ 0x9841, 0x0, "Alleycat5X 98DX3510MH-A0"},
+	{ 0x9822, 0x0, "Alleycat5X 98DX3520-A0"},
+	{ 0x9823, 0x0, "Alleycat5X 98DX3530-A0"},
+	{ 0x9863, 0x0, "Alleycat5X 98DX3530H-A0"},
+	{ 0x9824, 0x0, "Alleycat5X 98DX3540-A0"},
+	{ 0x9825, 0x0, "Alleycat5X 98DX3550-A0"},
+};
+
+#define BIT_VAL(b)          ((1ULL << ((b) + 1)) - 1)
+#define BIT_RANGE(bl, bh)   (BIT_VAL(bh) - BIT_VAL((bl) - 1))
+
+#define PLL_MAX_CHOICE	4
+
+#define CPU_TYPE_AC5    0
+#define CPU_TYPE_AC5x   1
+#define CPU_TYPE_LAST   2
+
+enum mvebu_sar_opts {
+	SAR_CPU_FREQ = 0,
+	SAR_DDR_FREQ,
+	SAR_AP_FABRIC_FREQ,
+	SAR_CP_FABRIC_FREQ,
+	SAR_CP0_PCIE0_CLK,
+	SAR_CP0_PCIE1_CLK,
+	SAR_CP1_PCIE0_CLK,
+	SAR_CP1_PCIE1_CLK,
+	SAR_BOOT_SRC,
+	SAR_MAX_IDX
+};
+
+static const u32 pll_freq_tbl[CPU_TYPE_LAST][SAR_AP_FABRIC_FREQ + 1][PLL_MAX_CHOICE] = {
+	[CPU_TYPE_AC5] = {
+		[SAR_CPU_FREQ] = {
+			800, 1200, 1400, 1000
+		},
+		[SAR_DDR_FREQ] = {
+			1200, 800, 0, 0
+		},
+		[SAR_AP_FABRIC_FREQ] = {
+			396, 290, 197, 0
+		},
+	},
+	[CPU_TYPE_AC5x] = {
+		[SAR_CPU_FREQ] = {
+			800, 1200, 1500, 1600
+		},
+		[SAR_DDR_FREQ] = {
+			1200, 800, 0, 0
+		},
+		[SAR_AP_FABRIC_FREQ] = {
+			0, 0, 0, 0
+		}
+	}
+};
+
+static const u32 soc_sar_masks_tbl[CPU_TYPE_LAST][SAR_AP_FABRIC_FREQ + 1] = {
+	[CPU_TYPE_AC5] = {
+		[SAR_CPU_FREQ] = BIT_RANGE(18, 20),
+		[SAR_DDR_FREQ] = BIT_RANGE(16, 17),
+		[SAR_AP_FABRIC_FREQ] = BIT_RANGE(22, 23),
+	},
+	[CPU_TYPE_AC5x] = {
+		[SAR_CPU_FREQ] = BIT_RANGE(8, 10),
+		[SAR_DDR_FREQ] = BIT_RANGE(6, 7),
+		[SAR_AP_FABRIC_FREQ] = 1,
+	},
+};
+
+static int get_soc_type_rev(u32 *type, u32 *rev)
+{
+	*type = (readl(DEVICE_ID_REG) & DEVICE_ID_MASK) >> DEVICE_ID_OFFSET;
+	*rev =  (readl(DEVICE_ID_REG) & REV_ID_MASK)    >> REV_ID_OFFSET;
+
+	return 0;
+}
+
+static void get_one_sar_freq(int cpu_type, u32 sar_reg_val, enum mvebu_sar_opts sar_opt, u32 *freq)
+{
+	u32 mask;
+	unsigned char choice;
+
+	mask = soc_sar_masks_tbl[cpu_type][sar_opt];
+	choice = (sar_reg_val & mask) >> (__builtin_ffs(mask) - 1);
+	*freq = pll_freq_tbl[cpu_type][sar_opt][choice];
+}
+
+void get_sar_freq(struct sar_freq_modes *sar_freq)
+{
+	int cpu_type;
+	u32 soc_type, rev;
+	u32 sar_reg_val = readl(DEVICE_SAR_REG);
+
+	get_soc_type_rev(&soc_type, &rev);
+	cpu_type = (soc_type & 0xFF00) == AC5X_DEV_ID ? CPU_TYPE_AC5x : CPU_TYPE_AC5;
+
+	get_one_sar_freq(cpu_type, sar_reg_val, SAR_CPU_FREQ, &sar_freq->p_clk);
+	get_one_sar_freq(cpu_type, sar_reg_val, SAR_AP_FABRIC_FREQ, &sar_freq->nb_clk);
+	get_one_sar_freq(cpu_type, sar_reg_val, SAR_DDR_FREQ, &sar_freq->d_clk);
+}
+
+static int get_soc_table_index(u32 *index)
+{
+	u32 soc_type;
+	u32 rev, i, ret = 1;
+
+	*index = 0;
+	get_soc_type_rev(&soc_type, &rev);
+
+	for (i = 0; i < ARRAY_SIZE(soc_info_table) && ret != 0; i++) {
+		if (soc_type != soc_info_table[i].dev_id ||
+		    rev != soc_info_table[i].rev_id)
+			continue;
+
+		*index = i;
+		ret = 0;
+	}
+
+	if (ret && ((soc_type & 0xFF00) == AC5X_DEV_ID))
+		*index = 1;
+
+	return ret;
+}
+
+static int get_soc_name(char **soc_name)
+{
+	u32 index;
+
+	get_soc_table_index(&index);
+	*soc_name = soc_info_table[index].soc_name;
+
+	return 0;
+}
+
+/* Print device's SoC name and AP & CP information */
+void soc_print_device_info(void)
+{
+	char *soc_name = NULL;
+
+	get_soc_name(&soc_name);
+
+	printf("SoC: %s\n", soc_name);
+}
+
+void soc_print_clock_info(void)
+{
+	struct sar_freq_modes sar_freq;
+
+	get_sar_freq(&sar_freq);
+	printf("Clock:  CPU     %4d MHz\n", sar_freq.p_clk);
+	printf("\tDDR     %4d MHz\n", sar_freq.d_clk);
+	printf("\tFABRIC  %4d MHz\n", sar_freq.nb_clk);
+	printf("\tMSS     %4d MHz\n", 200);
+}
+
+/*
+ * Override of __weak int mach_cpu_init(void) :
+ * SoC/machine dependent CPU setup
+ */
+int mach_cpu_init(void)
+{
+	u32 phy_i;
+	u64 new_val, phy_base = 0x7F080800;
+
+	/* Init USB PHY */
+#define USB_STEPPING	0x20000
+#define WRITE_MASK(addr, mask, val)		\
+	{ new_val = (readl(addr) & (~(mask))) | val;\
+	writel(new_val, addr); }
+
+	for (phy_i = 0; phy_i < 2; phy_i++, phy_base += USB_STEPPING) {
+		WRITE_MASK(phy_base + 0x4,     0x3,	   0x2);
+		WRITE_MASK(phy_base + 0xC,     0x3000000,   0x2000000);
+		WRITE_MASK(phy_base + 0x1C,    0x3,         0x2);
+		WRITE_MASK(phy_base + 0x0,     0x1FF007F,   0x600005);
+		WRITE_MASK(phy_base + 0xC,     0x000F000,   0x0002000);
+		/* Calibration Threshold Setting = 4*/
+		WRITE_MASK(phy_base + 0x8,     0x700,	   0x400)
+		WRITE_MASK(phy_base + 0x14,    0x000000F,   0x000000a);
+		/* Change AMP to 4*/
+		WRITE_MASK(phy_base + 0xC,     0x3700000,   0x3400000);
+		WRITE_MASK(phy_base + 0x4,     0x3,	   0x3);
+		/* Impedance calibration triggering is performed by USB probe */
+	}
+
+	return 0;
+}
+
+int arch_misc_init(void)
+{
+	u32 type, rev;
+
+	get_soc_type_rev(&type, &rev);
+
+	return 0;
+}
diff --git a/arch/arm/mach-mvebu/alleycat5/soc.h b/arch/arm/mach-mvebu/alleycat5/soc.h
new file mode 100644
index 0000000000..97663d2c01
--- /dev/null
+++ b/arch/arm/mach-mvebu/alleycat5/soc.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _ALLEYCAT5_SOC_H
+#define _ALLEYCAT5_SOC_H
+void soc_print_device_info(void);
+void soc_print_clock_info(void);
+#endif /* _ALLEYCAT5_SOC_H */
diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c
index 238edbe6ba..7b8f7641b4 100644
--- a/arch/arm/mach-mvebu/arm64-common.c
+++ b/arch/arm/mach-mvebu/arm64-common.c
@@ -53,6 +53,8 @@ __weak int dram_init_banksize(void)
 		return a8k_dram_init_banksize();
 	else if (CONFIG_IS_ENABLED(ARMADA_3700))
 		return a3700_dram_init_banksize();
+	else if (CONFIG_IS_ENABLED(ALLEYCAT_5))
+		return alleycat5_dram_init_banksize();
 	else
 		return fdtdec_setup_memory_banksize();
 }
@@ -68,6 +70,9 @@ __weak int dram_init(void)
 	if (CONFIG_IS_ENABLED(ARMADA_3700))
 		return a3700_dram_init();
 
+	if (CONFIG_IS_ENABLED(ALLEYCAT_5))
+		return alleycat5_dram_init();
+
 	if (fdtdec_setup_mem_size_base() != 0)
 		return -EINVAL;
 
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h
index b127fce865..c17c2440f1 100644
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -174,6 +174,10 @@ int a3700_dram_init_banksize(void);
 /* A3700 PCIe regions fixer for device tree */
 int a3700_fdt_fix_pcie_regions(void *blob);
 
+/* Alleycat5 dram functions */
+int alleycat5_dram_init(void);
+int alleycat5_dram_init_banksize(void);
+
 /*
  * get_ref_clk
  *
-- 
2.37.3

[PATCH v4 5/5] arm: mvebu: Add RD-AC5X board

[Chris Packham]

The RD-AC5X-32G16HVG6HLG-A0 development board main components and
features include:
* Main 12V/54V power supply
* 270 Gbps throughput packet processor on the main board
* DDR4:
  * SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
  * SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
  * PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
* 16GB eMMC (Samsung KLMAG1JETD-B041006)
* 16MB SPI NOR(GD25Q127C)
* 32 x 1000 Base-T interfaces
* 16 x 2500 Base-T interfaces
  * SR1: 88E2540*4
  * SR2: 88E2580*1+88E2540*2
* Six (6) x 25G Base-R SFP28 interfaces
* One (1) x RJ-45 console connector, interfacing to the on board UART
* One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
* One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
* One (1) x RJ-45 1G Base-T Management port, interfacing to the host
  port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy
* One (1) x Oculink port, interfacing to the PCIe port for external CPU
  connection
* POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~
  Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881
  solution)
* POE total power budget 780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)

Signed-off-by: Chris Packham <judge.packham@gmail.com>
---

Changes in v4:
- Move CONFIG_DISPLAY_BOARDINFO_LATE and CONFIG_ENV_OVERWRITE to
  the defconfig.
- Remove CONFIG_BAUDRATE as this is already set in the default config
- Remove CONFIG_USB_MAX_CONTROLLER_COUNT as this is not needed with
  DM_USB
- Remove CONFIG_PREBOOT as we don't have anything to run
- Remove commented out CONFIG_BOARD_EARLY_INIT_R
- Remove DEBUG_UART configuration
- Remove unnecessary console environment variable
- Remove CONFIG_MVEBU_SAR

Changes in v3:
- Remove MMC and UBIFS distroboot options (MMC driver is not currently
  functional, NAND is not populated on the RD-AC5X board)
- Remove unnecessary Ethernet configuration
- Remove unnecessary NAND configuration
- Remove memory node from dts so the value passed by the DDR FW will be
  used

Changes in v2:
- Use distro boot by default
- remove unnecessary SPI-NOR partitions

 arch/arm/dts/Makefile                      |   3 +-
 arch/arm/dts/ac5-98dx35xx-rd.dts           | 129 +++++++++++++++++++++
 arch/arm/mach-mvebu/Kconfig                |   9 +-
 board/Marvell/mvebu_alleycat-5/MAINTAINERS |   6 +
 board/Marvell/mvebu_alleycat-5/Makefile    |   3 +
 board/Marvell/mvebu_alleycat-5/board.c     |  28 +++++
 configs/mvebu_ac5_rd_defconfig             |  84 ++++++++++++++
 include/configs/mvebu_alleycat-5.h         |  42 +++++++
 8 files changed, 302 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/ac5-98dx35xx-rd.dts
 create mode 100644 board/Marvell/mvebu_alleycat-5/MAINTAINERS
 create mode 100644 board/Marvell/mvebu_alleycat-5/Makefile
 create mode 100644 board/Marvell/mvebu_alleycat-5/board.c
 create mode 100644 configs/mvebu_ac5_rd_defconfig
 create mode 100644 include/configs/mvebu_alleycat-5.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 965895bc2a..57a5272884 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -274,7 +274,8 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	cn9132-db-A.dtb				\
 	cn9132-db-B.dtb				\
 	cn9130-crb-A.dtb			\
-	cn9130-crb-B.dtb
+	cn9130-crb-B.dtb			\
+	ac5-98dx35xx-rd.dtb
 endif
 
 dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
diff --git a/arch/arm/dts/ac5-98dx35xx-rd.dts b/arch/arm/dts/ac5-98dx35xx-rd.dts
new file mode 100644
index 0000000000..d9f217cd4a
--- /dev/null
+++ b/arch/arm/dts/ac5-98dx35xx-rd.dts
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree For RD-AC5X.
+ *
+ * Copyright (C) 2021 Marvell
+ * Copyright (C) 2022 Allied Telesis Labs
+ */
+/*
+ * Device Tree file for Marvell Alleycat 5X development board
+ * This board file supports the B configuration of the board
+ */
+
+/dts-v1/;
+
+#include "ac5-98dx35xx.dtsi"
+
+/ {
+	model = "Marvell RD-AC5X Board";
+	compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5";
+
+	aliases {
+		serial0 = &uart0;
+		spiflash0 = &spiflash0;
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		ethernet0 = &eth0;
+		ethernet1 = &eth1;
+		spi0 = &spi0;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		usb0 = &usb0;
+		usb1 = &usb1;
+		pinctrl0 = &pinctrl0;
+		sar-reg0 = "/config-space/sar-reg";
+	};
+
+	usb1phy: usb-phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&mdio {
+	phy0: ethernet-phy@0 {
+	      reg = <0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&eth0 {
+	status = "okay";
+	phy-handle = <&phy0>;
+};
+
+/* USB0 is a host USB */
+&usb0 {
+	status = "okay";
+};
+
+/* USB1 is a peripheral USB */
+&usb1 {
+	status = "okay";
+	phys = <&usb1phy>;
+	phy-names = "usb-phy";
+	dr_mode = "peripheral";
+};
+
+&spi0 {
+	status = "okay";
+
+	spiflash0: flash@0 {
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <50000000>;
+		spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
+		spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
+		reg = <0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
+
+&pinctrl0 {
+	/*
+	 * MPP Bus:     MPP#     mode#
+	 * eMMC          [0-11]   0x1
+	 * SPI[0]        [12-17]  0x1
+	 * TSEN_INT      [18]     0x1
+	 * DEV_INIT      [19]     0x1
+	 * SPI[1]        [20-23]  0x3
+	 * UART[1]       [24-25]  0x3
+	 * I2C[0]        [26-27]  0x1
+	 * XSMI[0]       [28-29]  0x1 // SCH use SMI[0], reversed due to CPSS problem
+	 * SMI[1]        [30-31]  0x2 // SCH use XSMI[1], reversed due to CPSS problem
+	 * UART[0]       [32-33]  0x1
+	 * OOB_SMI       [34-35]  0x1
+	 * PTP_CLK0_OUT  [36]     0x1
+	 * PTP_PULSE_OUT [37]     0x1
+	 * RCVR_CLK_OUT  [38]     0x1
+	 * GPIO(in/out)  [39]     0x0
+	 * GPIO(in/out)  [40]     0x0
+	 * PTP_REF_CLK   [41]     0x1
+	 * PTP_CLK0      [42]     0x1
+	 * LED0_CLK      [43]     0x1
+	 * LED0_STB      [44]     0x1
+	 * LED0_DATA     [45]     0x1
+	 */
+	/*	     0    1    2    3    4    5    6    7    8    9 */
+	pin-func = < 1    1    1    1    1    1    1    1    1    1
+		     1    1    1    1    1    1    1    1    1    1
+		     3    3    3    3    3    3    1    1    1    1
+		     2    2    1    1    1    1    1    1    1    0
+		     0    1    1    1    1    1    >;
+};
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 45efa24194..2120cb473f 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -97,7 +97,7 @@ config CUSTOMER_BOARD_SUPPORT
 	bool
 
 choice
-	prompt "Armada XP/375/38x/3700/7K/8K board select"
+	prompt "Armada XP/375/38x/3700/7K/8K/Alleycat-5 board select"
 	optional
 
 config TARGET_CLEARFOG
@@ -149,6 +149,10 @@ config TARGET_MVEBU_ARMADA_8K
 	select BOARD_LATE_INIT
 	imply SCSI
 
+config TARGET_MVEBU_ALLEYCAT5
+	bool "Support AlleyCat 5 platforms"
+	select ALLEYCAT_5
+
 config TARGET_OCTEONTX2_CN913x
 	bool "Support CN913x platforms"
 	select ARMADA_8K
@@ -257,6 +261,7 @@ config SYS_BOARD
 	default "x530" if TARGET_X530
 	default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
 	default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
+	default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
 
 config SYS_CONFIG_NAME
 	default "clearfog" if TARGET_CLEARFOG
@@ -277,6 +282,7 @@ config SYS_CONFIG_NAME
 	default "x530" if TARGET_X530
 	default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
 	default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
+	default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
 
 config SYS_VENDOR
 	default "Marvell" if TARGET_DB_MV784MP_GP
@@ -296,6 +302,7 @@ config SYS_VENDOR
 	default "gdsys" if TARGET_CONTROLCENTERDC
 	default "alliedtelesis" if TARGET_X530
 	default "mikrotik" if TARGET_CRS3XX_98DX3236
+	default "Marvell" if TARGET_MVEBU_ALLEYCAT5
 
 config SYS_SOC
 	default "mvebu"
diff --git a/board/Marvell/mvebu_alleycat-5/MAINTAINERS b/board/Marvell/mvebu_alleycat-5/MAINTAINERS
new file mode 100644
index 0000000000..480c07c5f0
--- /dev/null
+++ b/board/Marvell/mvebu_alleycat-5/MAINTAINERS
@@ -0,0 +1,6 @@
+RD-AC5X BOARD
+M:	Chris Packham <chris.packham@alliedtelesis.co.nz>
+S:	Maintained
+F:	board/Marvell/mvebu_alleycat-5/
+F:	include/configs/mvebu_alleycat-5.h
+F:	configs/mvebu_ac5_rd_defconfig
diff --git a/board/Marvell/mvebu_alleycat-5/Makefile b/board/Marvell/mvebu_alleycat-5/Makefile
new file mode 100644
index 0000000000..29254b4d64
--- /dev/null
+++ b/board/Marvell/mvebu_alleycat-5/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:	GPL-2.0+
+
+obj-y	:= board.o
diff --git a/board/Marvell/mvebu_alleycat-5/board.c b/board/Marvell/mvebu_alleycat-5/board.c
new file mode 100644
index 0000000000..2d46775920
--- /dev/null
+++ b/board/Marvell/mvebu_alleycat-5/board.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
diff --git a/configs/mvebu_ac5_rd_defconfig b/configs/mvebu_ac5_rd_defconfig
new file mode 100644
index 0000000000..610d628705
--- /dev/null
+++ b/configs/mvebu_ac5_rd_defconfig
@@ -0,0 +1,84 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_TEXT_BASE=0x200000000
+CONFIG_SYS_MALLOC_LEN=0x900000
+CONFIG_TARGET_MVEBU_ALLEYCAT5=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_SYS_LOAD_ADDR=0x202000000
+CONFIG_SYS_MEMTEST_START=0x200800000
+CONFIG_SYS_MEMTEST_END=0x200ffffff
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x200FF0000
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=-1
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_UBI=y
+CONFIG_MAC_PARTITION=y
+CONFIG_OF_EMBED=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_CLK=y
+CONFIG_CLK_MVEBU=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_MISC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_XENON=y
+CONFIG_MTD=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_MVNETA=y
+CONFIG_MVMDIO=y
+CONFIG_PCI=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ARMADA_8K=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_DM_SCSI=y
+CONFIG_SYS_NS16550=y
+CONFIG_MVEBU_A3700_SPI=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h
new file mode 100644
index 0000000000..41bdfae6c3
--- /dev/null
+++ b/include/configs/mvebu_alleycat-5.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Marvell International Ltd
+ */
+
+#ifndef _CONFIG_MVEBU_ALLEYCAY_5_H
+#define _CONFIG_MVEBU_ALLEYCAY_5_H
+
+#include <asm/arch/soc.h>
+
+/* additions for new ARM relocation support */
+#define CONFIG_SYS_SDRAM_BASE   0x200000000
+
+#define CONFIG_SYS_BAUDRATE_TABLE   { 9600, 19200, 38400, 57600, \
+				      115200, 230400, 460800, 921600 }
+
+/* Default Env vars */
+#define CONFIG_IPADDR           0.0.0.0 /* In order to cause an error */
+#define CONFIG_SERVERIP         0.0.0.0 /* In order to cause an error */
+#define CONFIG_NETMASK          255.255.255.0
+#define CONFIG_GATEWAYIP        0.0.0.0
+#define CONFIG_ROOTPATH                 "/srv/nfs/" /* Default Dir for NFS */
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS   \
+	BOOTENV \
+	"kernel_addr_r=0x202000000\0" \
+	"fdt_addr_r=0x201000000\0"    \
+	"ramdisk_addr_r=0x206000000\0"    \
+	"fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_SYS_TCLK     325000000
+
+#endif /* _CONFIG_MVEBU_ALLEYCAY_5_H */
-- 
2.37.3

Re: [PATCH v4 5/5] arm: mvebu: Add RD-AC5X board

[Stefan Roese]

On 22.09.22 05:31, Chris Packham wrote:
> The RD-AC5X-32G16HVG6HLG-A0 development board main components and
> features include:
> * Main 12V/54V power supply
> * 270 Gbps throughput packet processor on the main board
> * DDR4:
>    * SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
>    * SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
>    * PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
> * 16GB eMMC (Samsung KLMAG1JETD-B041006)
> * 16MB SPI NOR(GD25Q127C)
> * 32 x 1000 Base-T interfaces
> * 16 x 2500 Base-T interfaces
>    * SR1: 88E2540*4
>    * SR2: 88E2580*1+88E2540*2
> * Six (6) x 25G Base-R SFP28 interfaces
> * One (1) x RJ-45 console connector, interfacing to the on board UART
> * One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
> * One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
> * One (1) x RJ-45 1G Base-T Management port, interfacing to the host
>    port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy
> * One (1) x Oculink port, interfacing to the PCIe port for external CPU
>    connection
> * POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~
>    Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881
>    solution)
> * POE total power budget 780W
> * LED interfaces per network port/POE
> * LED interfaces (common) showing system status
> * PTP TC mode Supported (Reserved M.2 connector to support BC mode)
> 
> Signed-off-by: Chris Packham <judge.packham@gmail.com>
> ---
> 
> Changes in v4:
> - Move CONFIG_DISPLAY_BOARDINFO_LATE and CONFIG_ENV_OVERWRITE to
>    the defconfig.
> - Remove CONFIG_BAUDRATE as this is already set in the default config
> - Remove CONFIG_USB_MAX_CONTROLLER_COUNT as this is not needed with
>    DM_USB
> - Remove CONFIG_PREBOOT as we don't have anything to run
> - Remove commented out CONFIG_BOARD_EARLY_INIT_R
> - Remove DEBUG_UART configuration
> - Remove unnecessary console environment variable
> - Remove CONFIG_MVEBU_SAR
> 
> Changes in v3:
> - Remove MMC and UBIFS distroboot options (MMC driver is not currently
>    functional, NAND is not populated on the RD-AC5X board)
> - Remove unnecessary Ethernet configuration
> - Remove unnecessary NAND configuration
> - Remove memory node from dts so the value passed by the DDR FW will be
>    used
> 
> Changes in v2:
> - Use distro boot by default
> - remove unnecessary SPI-NOR partitions
> 
>   arch/arm/dts/Makefile                      |   3 +-
>   arch/arm/dts/ac5-98dx35xx-rd.dts           | 129 +++++++++++++++++++++
>   arch/arm/mach-mvebu/Kconfig                |   9 +-
>   board/Marvell/mvebu_alleycat-5/MAINTAINERS |   6 +
>   board/Marvell/mvebu_alleycat-5/Makefile    |   3 +
>   board/Marvell/mvebu_alleycat-5/board.c     |  28 +++++
>   configs/mvebu_ac5_rd_defconfig             |  84 ++++++++++++++
>   include/configs/mvebu_alleycat-5.h         |  42 +++++++
>   8 files changed, 302 insertions(+), 2 deletions(-)
>   create mode 100644 arch/arm/dts/ac5-98dx35xx-rd.dts
>   create mode 100644 board/Marvell/mvebu_alleycat-5/MAINTAINERS
>   create mode 100644 board/Marvell/mvebu_alleycat-5/Makefile
>   create mode 100644 board/Marvell/mvebu_alleycat-5/board.c
>   create mode 100644 configs/mvebu_ac5_rd_defconfig
>   create mode 100644 include/configs/mvebu_alleycat-5.h
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 965895bc2a..57a5272884 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -274,7 +274,8 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
>   	cn9132-db-A.dtb				\
>   	cn9132-db-B.dtb				\
>   	cn9130-crb-A.dtb			\
> -	cn9130-crb-B.dtb
> +	cn9130-crb-B.dtb			\
> +	ac5-98dx35xx-rd.dtb
>   endif
>   
>   dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
> diff --git a/arch/arm/dts/ac5-98dx35xx-rd.dts b/arch/arm/dts/ac5-98dx35xx-rd.dts
> new file mode 100644
> index 0000000000..d9f217cd4a
> --- /dev/null
> +++ b/arch/arm/dts/ac5-98dx35xx-rd.dts
> @@ -0,0 +1,129 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree For RD-AC5X.
> + *
> + * Copyright (C) 2021 Marvell
> + * Copyright (C) 2022 Allied Telesis Labs
> + */
> +/*
> + * Device Tree file for Marvell Alleycat 5X development board
> + * This board file supports the B configuration of the board
> + */
> +
> +/dts-v1/;
> +
> +#include "ac5-98dx35xx.dtsi"
> +
> +/ {
> +	model = "Marvell RD-AC5X Board";
> +	compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5";
> +
> +	aliases {
> +		serial0 = &uart0;
> +		spiflash0 = &spiflash0;
> +		gpio0 = &gpio0;
> +		gpio1 = &gpio1;
> +		ethernet0 = &eth0;
> +		ethernet1 = &eth1;
> +		spi0 = &spi0;
> +		i2c0 = &i2c0;
> +		i2c1 = &i2c1;
> +		usb0 = &usb0;
> +		usb1 = &usb1;
> +		pinctrl0 = &pinctrl0;
> +		sar-reg0 = "/config-space/sar-reg";
> +	};
> +
> +	usb1phy: usb-phy {
> +		compatible = "usb-nop-xceiv";
> +		#phy-cells = <0>;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&mdio {
> +	phy0: ethernet-phy@0 {
> +	      reg = <0>;
> +	};
> +};
> +
> +&i2c0 {
> +	status = "okay";
> +};
> +
> +&i2c1 {
> +	status = "okay";
> +};
> +
> +&eth0 {
> +	status = "okay";
> +	phy-handle = <&phy0>;
> +};
> +
> +/* USB0 is a host USB */
> +&usb0 {
> +	status = "okay";
> +};
> +
> +/* USB1 is a peripheral USB */
> +&usb1 {
> +	status = "okay";
> +	phys = <&usb1phy>;
> +	phy-names = "usb-phy";
> +	dr_mode = "peripheral";
> +};
> +
> +&spi0 {
> +	status = "okay";
> +
> +	spiflash0: flash@0 {
> +		compatible = "jedec,spi-nor";
> +		spi-max-frequency = <50000000>;
> +		spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
> +		spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
> +		reg = <0>;
> +
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +	};
> +};
> +
> +&pinctrl0 {
> +	/*
> +	 * MPP Bus:     MPP#     mode#
> +	 * eMMC          [0-11]   0x1
> +	 * SPI[0]        [12-17]  0x1
> +	 * TSEN_INT      [18]     0x1
> +	 * DEV_INIT      [19]     0x1
> +	 * SPI[1]        [20-23]  0x3
> +	 * UART[1]       [24-25]  0x3
> +	 * I2C[0]        [26-27]  0x1
> +	 * XSMI[0]       [28-29]  0x1 // SCH use SMI[0], reversed due to CPSS problem
> +	 * SMI[1]        [30-31]  0x2 // SCH use XSMI[1], reversed due to CPSS problem
> +	 * UART[0]       [32-33]  0x1
> +	 * OOB_SMI       [34-35]  0x1
> +	 * PTP_CLK0_OUT  [36]     0x1
> +	 * PTP_PULSE_OUT [37]     0x1
> +	 * RCVR_CLK_OUT  [38]     0x1
> +	 * GPIO(in/out)  [39]     0x0
> +	 * GPIO(in/out)  [40]     0x0
> +	 * PTP_REF_CLK   [41]     0x1
> +	 * PTP_CLK0      [42]     0x1
> +	 * LED0_CLK      [43]     0x1
> +	 * LED0_STB      [44]     0x1
> +	 * LED0_DATA     [45]     0x1
> +	 */
> +	/*	     0    1    2    3    4    5    6    7    8    9 */
> +	pin-func = < 1    1    1    1    1    1    1    1    1    1
> +		     1    1    1    1    1    1    1    1    1    1
> +		     3    3    3    3    3    3    1    1    1    1
> +		     2    2    1    1    1    1    1    1    1    0
> +		     0    1    1    1    1    1    >;
> +};
> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> index 45efa24194..2120cb473f 100644
> --- a/arch/arm/mach-mvebu/Kconfig
> +++ b/arch/arm/mach-mvebu/Kconfig
> @@ -97,7 +97,7 @@ config CUSTOMER_BOARD_SUPPORT
>   	bool
>   
>   choice
> -	prompt "Armada XP/375/38x/3700/7K/8K board select"
> +	prompt "Armada XP/375/38x/3700/7K/8K/Alleycat-5 board select"
>   	optional
>   
>   config TARGET_CLEARFOG
> @@ -149,6 +149,10 @@ config TARGET_MVEBU_ARMADA_8K
>   	select BOARD_LATE_INIT
>   	imply SCSI
>   
> +config TARGET_MVEBU_ALLEYCAT5
> +	bool "Support AlleyCat 5 platforms"
> +	select ALLEYCAT_5
> +
>   config TARGET_OCTEONTX2_CN913x
>   	bool "Support CN913x platforms"
>   	select ARMADA_8K
> @@ -257,6 +261,7 @@ config SYS_BOARD
>   	default "x530" if TARGET_X530
>   	default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
>   	default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
> +	default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
>   
>   config SYS_CONFIG_NAME
>   	default "clearfog" if TARGET_CLEARFOG
> @@ -277,6 +282,7 @@ config SYS_CONFIG_NAME
>   	default "x530" if TARGET_X530
>   	default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
>   	default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
> +	default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
>   
>   config SYS_VENDOR
>   	default "Marvell" if TARGET_DB_MV784MP_GP
> @@ -296,6 +302,7 @@ config SYS_VENDOR
>   	default "gdsys" if TARGET_CONTROLCENTERDC
>   	default "alliedtelesis" if TARGET_X530
>   	default "mikrotik" if TARGET_CRS3XX_98DX3236
> +	default "Marvell" if TARGET_MVEBU_ALLEYCAT5
>   
>   config SYS_SOC
>   	default "mvebu"
> diff --git a/board/Marvell/mvebu_alleycat-5/MAINTAINERS b/board/Marvell/mvebu_alleycat-5/MAINTAINERS
> new file mode 100644
> index 0000000000..480c07c5f0
> --- /dev/null
> +++ b/board/Marvell/mvebu_alleycat-5/MAINTAINERS
> @@ -0,0 +1,6 @@
> +RD-AC5X BOARD
> +M:	Chris Packham <chris.packham@alliedtelesis.co.nz>
> +S:	Maintained
> +F:	board/Marvell/mvebu_alleycat-5/
> +F:	include/configs/mvebu_alleycat-5.h
> +F:	configs/mvebu_ac5_rd_defconfig
> diff --git a/board/Marvell/mvebu_alleycat-5/Makefile b/board/Marvell/mvebu_alleycat-5/Makefile
> new file mode 100644
> index 0000000000..29254b4d64
> --- /dev/null
> +++ b/board/Marvell/mvebu_alleycat-5/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier:	GPL-2.0+
> +
> +obj-y	:= board.o
> diff --git a/board/Marvell/mvebu_alleycat-5/board.c b/board/Marvell/mvebu_alleycat-5/board.c
> new file mode 100644
> index 0000000000..2d46775920
> --- /dev/null
> +++ b/board/Marvell/mvebu_alleycat-5/board.c
> @@ -0,0 +1,28 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include <common.h>
> +#include <asm/global_data.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int board_early_init_f(void)
> +{
> +	return 0;
> +}

Why not remove CONFIG_BOARD_EARLY_INIT_F from defconfig and remove this
empty function? Or do you plan to add some early init code here later?

> +
> +int board_early_init_r(void)
> +{
> +	return 0;
> +}

Same for CONFIG_BOARD_EARLY_INIT_R.

> +
> +int board_init(void)
> +{
> +	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> +
> +	return 0;
> +}
> +
> +int board_late_init(void)
> +{
> +	return 0;
> +}

Same for CONFIG_BOARD_LATE_INIT.

> diff --git a/configs/mvebu_ac5_rd_defconfig b/configs/mvebu_ac5_rd_defconfig
> new file mode 100644
> index 0000000000..610d628705
> --- /dev/null
> +++ b/configs/mvebu_ac5_rd_defconfig
> @@ -0,0 +1,84 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_CPU_INIT=y
> +CONFIG_ARCH_MVEBU=y
> +CONFIG_SYS_TEXT_BASE=0x200000000
> +CONFIG_SYS_MALLOC_LEN=0x900000
> +CONFIG_TARGET_MVEBU_ALLEYCAT5=y
> +CONFIG_ENV_SIZE=0x10000
> +CONFIG_ENV_OFFSET=0x400000
> +CONFIG_ENV_SECT_SIZE=0x10000
> +CONFIG_DM_GPIO=y
> +CONFIG_SYS_LOAD_ADDR=0x202000000
> +CONFIG_SYS_MEMTEST_START=0x200800000
> +CONFIG_SYS_MEMTEST_END=0x200ffffff
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x200FF0000
> +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> +CONFIG_FIT=y
> +CONFIG_BOOTDELAY=-1
> +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
> +CONFIG_SYS_CONSOLE_INFO_QUIET=y
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
> +CONFIG_ARCH_EARLY_INIT_R=y
> +CONFIG_ARCH_MISC_INIT=y
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_CMD_BOOTZ=y
> +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
> +CONFIG_CMD_MEMTEST=y
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_PCI=y
> +CONFIG_CMD_SPI=y
> +CONFIG_CMD_USB=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_TIME=y
> +CONFIG_CMD_MVEBU_BUBT=y
> +CONFIG_CMD_REGULATOR=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_UBI=y
> +CONFIG_MAC_PARTITION=y
> +CONFIG_OF_EMBED=y

IIRC, this option is deprecated. Compiling should complain about
this. Do you really need this?

> +CONFIG_ENV_OVERWRITE=y
> +CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_CLK=y
> +CONFIG_CLK_MVEBU=y
> +CONFIG_DM_PCA953X=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_MVTWSI=y
> +CONFIG_MISC=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_XENON=y
> +CONFIG_MTD=y
> +CONFIG_SPI_FLASH_GIGADEVICE=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_SPI_FLASH_SPANSION=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_PHY_MARVELL=y
> +CONFIG_PHY_GIGE=y
> +CONFIG_E1000=y

Really? Do you have PCI enabled?

> +CONFIG_MVNETA=y
> +CONFIG_MVMDIO=y
> +CONFIG_PCI=y
> +CONFIG_PHY=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_ARMADA_8K=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_DM_RTC=y
> +CONFIG_DM_SCSI=y
> +CONFIG_SYS_NS16550=y
> +CONFIG_MVEBU_A3700_SPI=y
> +CONFIG_DM_THERMAL=y
> +CONFIG_USB=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_HOST_ETHER=y
> +CONFIG_USB_ETHER_ASIX=y
> +CONFIG_USB_ETHER_ASIX88179=y
> +CONFIG_USB_ETHER_MCS7830=y
> +CONFIG_USB_ETHER_RTL8152=y
> +CONFIG_USB_ETHER_SMSC95XX=y
> diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h
> new file mode 100644
> index 0000000000..41bdfae6c3
> --- /dev/null
> +++ b/include/configs/mvebu_alleycat-5.h
> @@ -0,0 +1,42 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2018 Marvell International Ltd
> + */
> +
> +#ifndef _CONFIG_MVEBU_ALLEYCAY_5_H
> +#define _CONFIG_MVEBU_ALLEYCAY_5_H
> +
> +#include <asm/arch/soc.h>
> +
> +/* additions for new ARM relocation support */
> +#define CONFIG_SYS_SDRAM_BASE   0x200000000
> +
> +#define CONFIG_SYS_BAUDRATE_TABLE   { 9600, 19200, 38400, 57600, \
> +				      115200, 230400, 460800, 921600 }
> +
> +/* Default Env vars */
> +#define CONFIG_IPADDR           0.0.0.0 /* In order to cause an error */
> +#define CONFIG_SERVERIP         0.0.0.0 /* In order to cause an error */
> +#define CONFIG_NETMASK          255.255.255.0
> +#define CONFIG_GATEWAYIP        0.0.0.0
> +#define CONFIG_ROOTPATH                 "/srv/nfs/" /* Default Dir for NFS */
> +
> +#define BOOT_TARGET_DEVICES(func) \
> +	func(USB, usb, 0) \
> +	func(DHCP, dhcp, na)
> +
> +#include <config_distro_bootcmd.h>
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS   \
> +	BOOTENV \
> +	"kernel_addr_r=0x202000000\0" \
> +	"fdt_addr_r=0x201000000\0"    \
> +	"ramdisk_addr_r=0x206000000\0"    \
> +	"fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"
> +
> +/*
> + * High Level Configuration Options (easy to change)
> + */
> +#define CONFIG_SYS_TCLK     325000000
> +
> +#endif /* _CONFIG_MVEBU_ALLEYCAY_5_H */
BTW: Did you run checkpatch.pl on the series? This might give some
further ideas on cleanup.

Thanks,
Stefan

Re: [PATCH v4 5/5] arm: mvebu: Add RD-AC5X board

[Chris Packham]

On Thu, Sep 22, 2022 at 5:10 PM Stefan Roese <sr@denx.de> wrote:
>
> On 22.09.22 05:31, Chris Packham wrote:
> > The RD-AC5X-32G16HVG6HLG-A0 development board main components and
> > features include:
> > * Main 12V/54V power supply
> > * 270 Gbps throughput packet processor on the main board
> > * DDR4:
> >    * SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
> >    * SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
> >    * PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
> > * 16GB eMMC (Samsung KLMAG1JETD-B041006)
> > * 16MB SPI NOR(GD25Q127C)
> > * 32 x 1000 Base-T interfaces
> > * 16 x 2500 Base-T interfaces
> >    * SR1: 88E2540*4
> >    * SR2: 88E2580*1+88E2540*2
> > * Six (6) x 25G Base-R SFP28 interfaces
> > * One (1) x RJ-45 console connector, interfacing to the on board UART
> > * One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
> > * One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
> > * One (1) x RJ-45 1G Base-T Management port, interfacing to the host
> >    port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy
> > * One (1) x Oculink port, interfacing to the PCIe port for external CPU
> >    connection
> > * POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~
> >    Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881
> >    solution)
> > * POE total power budget 780W
> > * LED interfaces per network port/POE
> > * LED interfaces (common) showing system status
> > * PTP TC mode Supported (Reserved M.2 connector to support BC mode)
> >
> > Signed-off-by: Chris Packham <judge.packham@gmail.com>
> > ---
> >
> > Changes in v4:
> > - Move CONFIG_DISPLAY_BOARDINFO_LATE and CONFIG_ENV_OVERWRITE to
> >    the defconfig.
> > - Remove CONFIG_BAUDRATE as this is already set in the default config
> > - Remove CONFIG_USB_MAX_CONTROLLER_COUNT as this is not needed with
> >    DM_USB
> > - Remove CONFIG_PREBOOT as we don't have anything to run
> > - Remove commented out CONFIG_BOARD_EARLY_INIT_R
> > - Remove DEBUG_UART configuration
> > - Remove unnecessary console environment variable
> > - Remove CONFIG_MVEBU_SAR
> >
> > Changes in v3:
> > - Remove MMC and UBIFS distroboot options (MMC driver is not currently
> >    functional, NAND is not populated on the RD-AC5X board)
> > - Remove unnecessary Ethernet configuration
> > - Remove unnecessary NAND configuration
> > - Remove memory node from dts so the value passed by the DDR FW will be
> >    used
> >
> > Changes in v2:
> > - Use distro boot by default
> > - remove unnecessary SPI-NOR partitions
> >
> >   arch/arm/dts/Makefile                      |   3 +-
> >   arch/arm/dts/ac5-98dx35xx-rd.dts           | 129 +++++++++++++++++++++
> >   arch/arm/mach-mvebu/Kconfig                |   9 +-
> >   board/Marvell/mvebu_alleycat-5/MAINTAINERS |   6 +
> >   board/Marvell/mvebu_alleycat-5/Makefile    |   3 +
> >   board/Marvell/mvebu_alleycat-5/board.c     |  28 +++++
> >   configs/mvebu_ac5_rd_defconfig             |  84 ++++++++++++++
> >   include/configs/mvebu_alleycat-5.h         |  42 +++++++
> >   8 files changed, 302 insertions(+), 2 deletions(-)
> >   create mode 100644 arch/arm/dts/ac5-98dx35xx-rd.dts
> >   create mode 100644 board/Marvell/mvebu_alleycat-5/MAINTAINERS
> >   create mode 100644 board/Marvell/mvebu_alleycat-5/Makefile
> >   create mode 100644 board/Marvell/mvebu_alleycat-5/board.c
> >   create mode 100644 configs/mvebu_ac5_rd_defconfig
> >   create mode 100644 include/configs/mvebu_alleycat-5.h
> >
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index 965895bc2a..57a5272884 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -274,7 +274,8 @@ dtb-$(CONFIG_ARCH_MVEBU) +=                       \
> >       cn9132-db-A.dtb                         \
> >       cn9132-db-B.dtb                         \
> >       cn9130-crb-A.dtb                        \
> > -     cn9130-crb-B.dtb
> > +     cn9130-crb-B.dtb                        \
> > +     ac5-98dx35xx-rd.dtb
> >   endif
> >
> >   dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
> > diff --git a/arch/arm/dts/ac5-98dx35xx-rd.dts b/arch/arm/dts/ac5-98dx35xx-rd.dts
> > new file mode 100644
> > index 0000000000..d9f217cd4a
> > --- /dev/null
> > +++ b/arch/arm/dts/ac5-98dx35xx-rd.dts
> > @@ -0,0 +1,129 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree For RD-AC5X.
> > + *
> > + * Copyright (C) 2021 Marvell
> > + * Copyright (C) 2022 Allied Telesis Labs
> > + */
> > +/*
> > + * Device Tree file for Marvell Alleycat 5X development board
> > + * This board file supports the B configuration of the board
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "ac5-98dx35xx.dtsi"
> > +
> > +/ {
> > +     model = "Marvell RD-AC5X Board";
> > +     compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5";
> > +
> > +     aliases {
> > +             serial0 = &uart0;
> > +             spiflash0 = &spiflash0;
> > +             gpio0 = &gpio0;
> > +             gpio1 = &gpio1;
> > +             ethernet0 = &eth0;
> > +             ethernet1 = &eth1;
> > +             spi0 = &spi0;
> > +             i2c0 = &i2c0;
> > +             i2c1 = &i2c1;
> > +             usb0 = &usb0;
> > +             usb1 = &usb1;
> > +             pinctrl0 = &pinctrl0;
> > +             sar-reg0 = "/config-space/sar-reg";
> > +     };
> > +
> > +     usb1phy: usb-phy {
> > +             compatible = "usb-nop-xceiv";
> > +             #phy-cells = <0>;
> > +     };
> > +
> > +     chosen {
> > +             stdout-path = "serial0:115200n8";
> > +     };
> > +};
> > +
> > +&uart0 {
> > +     status = "okay";
> > +};
> > +
> > +&mdio {
> > +     phy0: ethernet-phy@0 {
> > +           reg = <0>;
> > +     };
> > +};
> > +
> > +&i2c0 {
> > +     status = "okay";
> > +};
> > +
> > +&i2c1 {
> > +     status = "okay";
> > +};
> > +
> > +&eth0 {
> > +     status = "okay";
> > +     phy-handle = <&phy0>;
> > +};
> > +
> > +/* USB0 is a host USB */
> > +&usb0 {
> > +     status = "okay";
> > +};
> > +
> > +/* USB1 is a peripheral USB */
> > +&usb1 {
> > +     status = "okay";
> > +     phys = <&usb1phy>;
> > +     phy-names = "usb-phy";
> > +     dr_mode = "peripheral";
> > +};
> > +
> > +&spi0 {
> > +     status = "okay";
> > +
> > +     spiflash0: flash@0 {
> > +             compatible = "jedec,spi-nor";
> > +             spi-max-frequency = <50000000>;
> > +             spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
> > +             spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
> > +             reg = <0>;
> > +
> > +             #address-cells = <1>;
> > +             #size-cells = <1>;
> > +     };
> > +};
> > +
> > +&pinctrl0 {
> > +     /*
> > +      * MPP Bus:     MPP#     mode#
> > +      * eMMC          [0-11]   0x1
> > +      * SPI[0]        [12-17]  0x1
> > +      * TSEN_INT      [18]     0x1
> > +      * DEV_INIT      [19]     0x1
> > +      * SPI[1]        [20-23]  0x3
> > +      * UART[1]       [24-25]  0x3
> > +      * I2C[0]        [26-27]  0x1
> > +      * XSMI[0]       [28-29]  0x1 // SCH use SMI[0], reversed due to CPSS problem
> > +      * SMI[1]        [30-31]  0x2 // SCH use XSMI[1], reversed due to CPSS problem
> > +      * UART[0]       [32-33]  0x1
> > +      * OOB_SMI       [34-35]  0x1
> > +      * PTP_CLK0_OUT  [36]     0x1
> > +      * PTP_PULSE_OUT [37]     0x1
> > +      * RCVR_CLK_OUT  [38]     0x1
> > +      * GPIO(in/out)  [39]     0x0
> > +      * GPIO(in/out)  [40]     0x0
> > +      * PTP_REF_CLK   [41]     0x1
> > +      * PTP_CLK0      [42]     0x1
> > +      * LED0_CLK      [43]     0x1
> > +      * LED0_STB      [44]     0x1
> > +      * LED0_DATA     [45]     0x1
> > +      */
> > +     /*           0    1    2    3    4    5    6    7    8    9 */
> > +     pin-func = < 1    1    1    1    1    1    1    1    1    1
> > +                  1    1    1    1    1    1    1    1    1    1
> > +                  3    3    3    3    3    3    1    1    1    1
> > +                  2    2    1    1    1    1    1    1    1    0
> > +                  0    1    1    1    1    1    >;
> > +};
> > diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> > index 45efa24194..2120cb473f 100644
> > --- a/arch/arm/mach-mvebu/Kconfig
> > +++ b/arch/arm/mach-mvebu/Kconfig
> > @@ -97,7 +97,7 @@ config CUSTOMER_BOARD_SUPPORT
> >       bool
> >
> >   choice
> > -     prompt "Armada XP/375/38x/3700/7K/8K board select"
> > +     prompt "Armada XP/375/38x/3700/7K/8K/Alleycat-5 board select"
> >       optional
> >
> >   config TARGET_CLEARFOG
> > @@ -149,6 +149,10 @@ config TARGET_MVEBU_ARMADA_8K
> >       select BOARD_LATE_INIT
> >       imply SCSI
> >
> > +config TARGET_MVEBU_ALLEYCAT5
> > +     bool "Support AlleyCat 5 platforms"
> > +     select ALLEYCAT_5
> > +
> >   config TARGET_OCTEONTX2_CN913x
> >       bool "Support CN913x platforms"
> >       select ARMADA_8K
> > @@ -257,6 +261,7 @@ config SYS_BOARD
> >       default "x530" if TARGET_X530
> >       default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
> >       default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
> > +     default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
> >
> >   config SYS_CONFIG_NAME
> >       default "clearfog" if TARGET_CLEARFOG
> > @@ -277,6 +282,7 @@ config SYS_CONFIG_NAME
> >       default "x530" if TARGET_X530
> >       default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
> >       default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
> > +     default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
> >
> >   config SYS_VENDOR
> >       default "Marvell" if TARGET_DB_MV784MP_GP
> > @@ -296,6 +302,7 @@ config SYS_VENDOR
> >       default "gdsys" if TARGET_CONTROLCENTERDC
> >       default "alliedtelesis" if TARGET_X530
> >       default "mikrotik" if TARGET_CRS3XX_98DX3236
> > +     default "Marvell" if TARGET_MVEBU_ALLEYCAT5
> >
> >   config SYS_SOC
> >       default "mvebu"
> > diff --git a/board/Marvell/mvebu_alleycat-5/MAINTAINERS b/board/Marvell/mvebu_alleycat-5/MAINTAINERS
> > new file mode 100644
> > index 0000000000..480c07c5f0
> > --- /dev/null
> > +++ b/board/Marvell/mvebu_alleycat-5/MAINTAINERS
> > @@ -0,0 +1,6 @@
> > +RD-AC5X BOARD
> > +M:   Chris Packham <chris.packham@alliedtelesis.co.nz>
> > +S:   Maintained
> > +F:   board/Marvell/mvebu_alleycat-5/
> > +F:   include/configs/mvebu_alleycat-5.h
> > +F:   configs/mvebu_ac5_rd_defconfig
> > diff --git a/board/Marvell/mvebu_alleycat-5/Makefile b/board/Marvell/mvebu_alleycat-5/Makefile
> > new file mode 100644
> > index 0000000000..29254b4d64
> > --- /dev/null
> > +++ b/board/Marvell/mvebu_alleycat-5/Makefile
> > @@ -0,0 +1,3 @@
> > +# SPDX-License-Identifier:   GPL-2.0+
> > +
> > +obj-y        := board.o
> > diff --git a/board/Marvell/mvebu_alleycat-5/board.c b/board/Marvell/mvebu_alleycat-5/board.c
> > new file mode 100644
> > index 0000000000..2d46775920
> > --- /dev/null
> > +++ b/board/Marvell/mvebu_alleycat-5/board.c
> > @@ -0,0 +1,28 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +
> > +#include <common.h>
> > +#include <asm/global_data.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +int board_early_init_f(void)
> > +{
> > +     return 0;
> > +}
>
> Why not remove CONFIG_BOARD_EARLY_INIT_F from defconfig and remove this
> empty function? Or do you plan to add some early init code here later?
>

Yeah I did think about doing that. I don't have anything planned to
put in these functions so I'll remove them. If it turns out I need
them later I can always add them when they are needed.

> > +
> > +int board_early_init_r(void)
> > +{
> > +     return 0;
> > +}
>
> Same for CONFIG_BOARD_EARLY_INIT_R.
>
> > +
> > +int board_init(void)
> > +{
> > +     gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> > +
> > +     return 0;
> > +}
> > +
> > +int board_late_init(void)
> > +{
> > +     return 0;
> > +}
>
> Same for CONFIG_BOARD_LATE_INIT.
>
> > diff --git a/configs/mvebu_ac5_rd_defconfig b/configs/mvebu_ac5_rd_defconfig
> > new file mode 100644
> > index 0000000000..610d628705
> > --- /dev/null
> > +++ b/configs/mvebu_ac5_rd_defconfig
> > @@ -0,0 +1,84 @@
> > +CONFIG_ARM=y
> > +CONFIG_ARCH_CPU_INIT=y
> > +CONFIG_ARCH_MVEBU=y
> > +CONFIG_SYS_TEXT_BASE=0x200000000
> > +CONFIG_SYS_MALLOC_LEN=0x900000
> > +CONFIG_TARGET_MVEBU_ALLEYCAT5=y
> > +CONFIG_ENV_SIZE=0x10000
> > +CONFIG_ENV_OFFSET=0x400000
> > +CONFIG_ENV_SECT_SIZE=0x10000
> > +CONFIG_DM_GPIO=y
> > +CONFIG_SYS_LOAD_ADDR=0x202000000
> > +CONFIG_SYS_MEMTEST_START=0x200800000
> > +CONFIG_SYS_MEMTEST_END=0x200ffffff
> > +CONFIG_DISTRO_DEFAULTS=y
> > +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> > +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x200FF0000
> > +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> > +CONFIG_FIT=y
> > +CONFIG_BOOTDELAY=-1
> > +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
> > +CONFIG_SYS_CONSOLE_INFO_QUIET=y
> > +CONFIG_DISPLAY_BOARDINFO_LATE=y
> > +CONFIG_ARCH_EARLY_INIT_R=y
> > +CONFIG_ARCH_MISC_INIT=y
> > +CONFIG_BOARD_EARLY_INIT_F=y
> > +CONFIG_CMD_BOOTZ=y
> > +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
> > +CONFIG_CMD_MEMTEST=y
> > +# CONFIG_CMD_FLASH is not set
> > +CONFIG_CMD_GPIO=y
> > +CONFIG_CMD_I2C=y
> > +CONFIG_CMD_MMC=y
> > +CONFIG_CMD_PCI=y
> > +CONFIG_CMD_SPI=y
> > +CONFIG_CMD_USB=y
> > +# CONFIG_CMD_SETEXPR is not set
> > +CONFIG_CMD_CACHE=y
> > +CONFIG_CMD_TIME=y
> > +CONFIG_CMD_MVEBU_BUBT=y
> > +CONFIG_CMD_REGULATOR=y
> > +CONFIG_CMD_EXT4_WRITE=y
> > +CONFIG_CMD_UBI=y
> > +CONFIG_MAC_PARTITION=y
> > +CONFIG_OF_EMBED=y
>
> IIRC, this option is deprecated. Compiling should complain about
> this. Do you really need this?
>

Doesn't appear to. OF_SEPARATE should work for me.

> > +CONFIG_ENV_OVERWRITE=y
> > +CONFIG_ENV_IS_IN_SPI_FLASH=y
> > +CONFIG_CLK=y
> > +CONFIG_CLK_MVEBU=y
> > +CONFIG_DM_PCA953X=y
> > +CONFIG_DM_I2C=y
> > +CONFIG_SYS_I2C_MVTWSI=y
> > +CONFIG_MISC=y
> > +CONFIG_MMC_SDHCI=y
> > +CONFIG_MMC_SDHCI_XENON=y
> > +CONFIG_MTD=y
> > +CONFIG_SPI_FLASH_GIGADEVICE=y
> > +CONFIG_SPI_FLASH_MACRONIX=y
> > +CONFIG_SPI_FLASH_SPANSION=y
> > +CONFIG_SPI_FLASH_STMICRO=y
> > +CONFIG_PHY_MARVELL=y
> > +CONFIG_PHY_GIGE=y
> > +CONFIG_E1000=y
>
> Really? Do you have PCI enabled?
>

The board does have a PCI connector on it but by now I think I've
dropped pretty much any of the vendor code that would allow it to be
used. I'll drop this and the PCI=y below.

> > +CONFIG_MVNETA=y
> > +CONFIG_MVMDIO=y
> > +CONFIG_PCI=y
> > +CONFIG_PHY=y
> > +CONFIG_PINCTRL=y
> > +CONFIG_PINCTRL_ARMADA_8K=y
> > +CONFIG_DM_REGULATOR_FIXED=y
> > +CONFIG_DM_REGULATOR_GPIO=y
> > +CONFIG_DM_RTC=y
> > +CONFIG_DM_SCSI=y
> > +CONFIG_SYS_NS16550=y
> > +CONFIG_MVEBU_A3700_SPI=y
> > +CONFIG_DM_THERMAL=y
> > +CONFIG_USB=y
> > +CONFIG_USB_XHCI_HCD=y
> > +CONFIG_USB_EHCI_HCD=y
> > +CONFIG_USB_HOST_ETHER=y
> > +CONFIG_USB_ETHER_ASIX=y
> > +CONFIG_USB_ETHER_ASIX88179=y
> > +CONFIG_USB_ETHER_MCS7830=y
> > +CONFIG_USB_ETHER_RTL8152=y
> > +CONFIG_USB_ETHER_SMSC95XX=y
> > diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h
> > new file mode 100644
> > index 0000000000..41bdfae6c3
> > --- /dev/null
> > +++ b/include/configs/mvebu_alleycat-5.h
> > @@ -0,0 +1,42 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (C) 2018 Marvell International Ltd
> > + */
> > +
> > +#ifndef _CONFIG_MVEBU_ALLEYCAY_5_H
> > +#define _CONFIG_MVEBU_ALLEYCAY_5_H
> > +
> > +#include <asm/arch/soc.h>
> > +
> > +/* additions for new ARM relocation support */
> > +#define CONFIG_SYS_SDRAM_BASE   0x200000000
> > +
> > +#define CONFIG_SYS_BAUDRATE_TABLE   { 9600, 19200, 38400, 57600, \
> > +                                   115200, 230400, 460800, 921600 }
> > +
> > +/* Default Env vars */
> > +#define CONFIG_IPADDR           0.0.0.0 /* In order to cause an error */
> > +#define CONFIG_SERVERIP         0.0.0.0 /* In order to cause an error */
> > +#define CONFIG_NETMASK          255.255.255.0
> > +#define CONFIG_GATEWAYIP        0.0.0.0
> > +#define CONFIG_ROOTPATH                 "/srv/nfs/" /* Default Dir for NFS */
> > +
> > +#define BOOT_TARGET_DEVICES(func) \
> > +     func(USB, usb, 0) \
> > +     func(DHCP, dhcp, na)
> > +
> > +#include <config_distro_bootcmd.h>
> > +
> > +#define CONFIG_EXTRA_ENV_SETTINGS   \
> > +     BOOTENV \
> > +     "kernel_addr_r=0x202000000\0" \
> > +     "fdt_addr_r=0x201000000\0"    \
> > +     "ramdisk_addr_r=0x206000000\0"    \
> > +     "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"
> > +
> > +/*
> > + * High Level Configuration Options (easy to change)
> > + */
> > +#define CONFIG_SYS_TCLK     325000000
> > +
> > +#endif /* _CONFIG_MVEBU_ALLEYCAY_5_H */
> BTW: Did you run checkpatch.pl on the series? This might give some
> further ideas on cleanup.

Yes I have been (via patman). It's pretty clean now (a couple of
warning/check messages that I'm electing to leave).

>
> Thanks,
> Stefan

Re: [PATCH v4 5/5] arm: mvebu: Add RD-AC5X board

[Stefan Roese]

Hi Chris,

On 22.09.22 05:31, Chris Packham wrote:
> The RD-AC5X-32G16HVG6HLG-A0 development board main components and
> features include:
> * Main 12V/54V power supply
> * 270 Gbps throughput packet processor on the main board
> * DDR4:
>    * SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
>    * SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
>    * PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
> * 16GB eMMC (Samsung KLMAG1JETD-B041006)
> * 16MB SPI NOR(GD25Q127C)
> * 32 x 1000 Base-T interfaces
> * 16 x 2500 Base-T interfaces
>    * SR1: 88E2540*4
>    * SR2: 88E2580*1+88E2540*2
> * Six (6) x 25G Base-R SFP28 interfaces
> * One (1) x RJ-45 console connector, interfacing to the on board UART
> * One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
> * One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
> * One (1) x RJ-45 1G Base-T Management port, interfacing to the host
>    port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy
> * One (1) x Oculink port, interfacing to the PCIe port for external CPU
>    connection
> * POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~
>    Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881
>    solution)
> * POE total power budget 780W
> * LED interfaces per network port/POE
> * LED interfaces (common) showing system status
> * PTP TC mode Supported (Reserved M.2 connector to support BC mode)
> 
> Signed-off-by: Chris Packham <judge.packham@gmail.com>
> ---
> 
> Changes in v4:
> - Move CONFIG_DISPLAY_BOARDINFO_LATE and CONFIG_ENV_OVERWRITE to
>    the defconfig.
> - Remove CONFIG_BAUDRATE as this is already set in the default config
> - Remove CONFIG_USB_MAX_CONTROLLER_COUNT as this is not needed with
>    DM_USB
> - Remove CONFIG_PREBOOT as we don't have anything to run
> - Remove commented out CONFIG_BOARD_EARLY_INIT_R
> - Remove DEBUG_UART configuration
> - Remove unnecessary console environment variable
> - Remove CONFIG_MVEBU_SAR
> 
> Changes in v3:
> - Remove MMC and UBIFS distroboot options (MMC driver is not currently
>    functional, NAND is not populated on the RD-AC5X board)
> - Remove unnecessary Ethernet configuration
> - Remove unnecessary NAND configuration
> - Remove memory node from dts so the value passed by the DDR FW will be
>    used
> 
> Changes in v2:
> - Use distro boot by default
> - remove unnecessary SPI-NOR partitions
> 
>   arch/arm/dts/Makefile                      |   3 +-
>   arch/arm/dts/ac5-98dx35xx-rd.dts           | 129 +++++++++++++++++++++
>   arch/arm/mach-mvebu/Kconfig                |   9 +-
>   board/Marvell/mvebu_alleycat-5/MAINTAINERS |   6 +
>   board/Marvell/mvebu_alleycat-5/Makefile    |   3 +
>   board/Marvell/mvebu_alleycat-5/board.c     |  28 +++++
>   configs/mvebu_ac5_rd_defconfig             |  84 ++++++++++++++
>   include/configs/mvebu_alleycat-5.h         |  42 +++++++
>   8 files changed, 302 insertions(+), 2 deletions(-)
>   create mode 100644 arch/arm/dts/ac5-98dx35xx-rd.dts
>   create mode 100644 board/Marvell/mvebu_alleycat-5/MAINTAINERS
>   create mode 100644 board/Marvell/mvebu_alleycat-5/Makefile
>   create mode 100644 board/Marvell/mvebu_alleycat-5/board.c
>   create mode 100644 configs/mvebu_ac5_rd_defconfig
>   create mode 100644 include/configs/mvebu_alleycat-5.h

While running a CI build I run into these issues:

CONFIG_SYS_TEXT_BASE is now renamed to CONFIG_TEXT_BASE. I've already
fixes this locally. But now I also get this compilation error:

[stefan@ryzen u-boot-marvell (master)]$ make -sj

Device Tree Source (arch/arm/dts/unset.dtb) is not correctly specified.
Please define 'CONFIG_DEFAULT_DEVICE_TREE'
or build with 'DEVICE_TREE=<device_tree>' argument

make[1]: *** [dts/Makefile:34: arch/arm/dts/unset.dtb] Error 1
make: *** [Makefile:1162: dts/dt.dtb] Error 2

So where is CONFIG_DEFAULT_DEVICE_TREE defined? I might have overlooked
this.

Thanks,
Stefan

> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 965895bc2a..57a5272884 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -274,7 +274,8 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
>   	cn9132-db-A.dtb				\
>   	cn9132-db-B.dtb				\
>   	cn9130-crb-A.dtb			\
> -	cn9130-crb-B.dtb
> +	cn9130-crb-B.dtb			\
> +	ac5-98dx35xx-rd.dtb
>   endif
>   
>   dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
> diff --git a/arch/arm/dts/ac5-98dx35xx-rd.dts b/arch/arm/dts/ac5-98dx35xx-rd.dts
> new file mode 100644
> index 0000000000..d9f217cd4a
> --- /dev/null
> +++ b/arch/arm/dts/ac5-98dx35xx-rd.dts
> @@ -0,0 +1,129 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree For RD-AC5X.
> + *
> + * Copyright (C) 2021 Marvell
> + * Copyright (C) 2022 Allied Telesis Labs
> + */
> +/*
> + * Device Tree file for Marvell Alleycat 5X development board
> + * This board file supports the B configuration of the board
> + */
> +
> +/dts-v1/;
> +
> +#include "ac5-98dx35xx.dtsi"
> +
> +/ {
> +	model = "Marvell RD-AC5X Board";
> +	compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5";
> +
> +	aliases {
> +		serial0 = &uart0;
> +		spiflash0 = &spiflash0;
> +		gpio0 = &gpio0;
> +		gpio1 = &gpio1;
> +		ethernet0 = &eth0;
> +		ethernet1 = &eth1;
> +		spi0 = &spi0;
> +		i2c0 = &i2c0;
> +		i2c1 = &i2c1;
> +		usb0 = &usb0;
> +		usb1 = &usb1;
> +		pinctrl0 = &pinctrl0;
> +		sar-reg0 = "/config-space/sar-reg";
> +	};
> +
> +	usb1phy: usb-phy {
> +		compatible = "usb-nop-xceiv";
> +		#phy-cells = <0>;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&mdio {
> +	phy0: ethernet-phy@0 {
> +	      reg = <0>;
> +	};
> +};
> +
> +&i2c0 {
> +	status = "okay";
> +};
> +
> +&i2c1 {
> +	status = "okay";
> +};
> +
> +&eth0 {
> +	status = "okay";
> +	phy-handle = <&phy0>;
> +};
> +
> +/* USB0 is a host USB */
> +&usb0 {
> +	status = "okay";
> +};
> +
> +/* USB1 is a peripheral USB */
> +&usb1 {
> +	status = "okay";
> +	phys = <&usb1phy>;
> +	phy-names = "usb-phy";
> +	dr_mode = "peripheral";
> +};
> +
> +&spi0 {
> +	status = "okay";
> +
> +	spiflash0: flash@0 {
> +		compatible = "jedec,spi-nor";
> +		spi-max-frequency = <50000000>;
> +		spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
> +		spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
> +		reg = <0>;
> +
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +	};
> +};
> +
> +&pinctrl0 {
> +	/*
> +	 * MPP Bus:     MPP#     mode#
> +	 * eMMC          [0-11]   0x1
> +	 * SPI[0]        [12-17]  0x1
> +	 * TSEN_INT      [18]     0x1
> +	 * DEV_INIT      [19]     0x1
> +	 * SPI[1]        [20-23]  0x3
> +	 * UART[1]       [24-25]  0x3
> +	 * I2C[0]        [26-27]  0x1
> +	 * XSMI[0]       [28-29]  0x1 // SCH use SMI[0], reversed due to CPSS problem
> +	 * SMI[1]        [30-31]  0x2 // SCH use XSMI[1], reversed due to CPSS problem
> +	 * UART[0]       [32-33]  0x1
> +	 * OOB_SMI       [34-35]  0x1
> +	 * PTP_CLK0_OUT  [36]     0x1
> +	 * PTP_PULSE_OUT [37]     0x1
> +	 * RCVR_CLK_OUT  [38]     0x1
> +	 * GPIO(in/out)  [39]     0x0
> +	 * GPIO(in/out)  [40]     0x0
> +	 * PTP_REF_CLK   [41]     0x1
> +	 * PTP_CLK0      [42]     0x1
> +	 * LED0_CLK      [43]     0x1
> +	 * LED0_STB      [44]     0x1
> +	 * LED0_DATA     [45]     0x1
> +	 */
> +	/*	     0    1    2    3    4    5    6    7    8    9 */
> +	pin-func = < 1    1    1    1    1    1    1    1    1    1
> +		     1    1    1    1    1    1    1    1    1    1
> +		     3    3    3    3    3    3    1    1    1    1
> +		     2    2    1    1    1    1    1    1    1    0
> +		     0    1    1    1    1    1    >;
> +};
> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> index 45efa24194..2120cb473f 100644
> --- a/arch/arm/mach-mvebu/Kconfig
> +++ b/arch/arm/mach-mvebu/Kconfig
> @@ -97,7 +97,7 @@ config CUSTOMER_BOARD_SUPPORT
>   	bool
>   
>   choice
> -	prompt "Armada XP/375/38x/3700/7K/8K board select"
> +	prompt "Armada XP/375/38x/3700/7K/8K/Alleycat-5 board select"
>   	optional
>   
>   config TARGET_CLEARFOG
> @@ -149,6 +149,10 @@ config TARGET_MVEBU_ARMADA_8K
>   	select BOARD_LATE_INIT
>   	imply SCSI
>   
> +config TARGET_MVEBU_ALLEYCAT5
> +	bool "Support AlleyCat 5 platforms"
> +	select ALLEYCAT_5
> +
>   config TARGET_OCTEONTX2_CN913x
>   	bool "Support CN913x platforms"
>   	select ARMADA_8K
> @@ -257,6 +261,7 @@ config SYS_BOARD
>   	default "x530" if TARGET_X530
>   	default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
>   	default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
> +	default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
>   
>   config SYS_CONFIG_NAME
>   	default "clearfog" if TARGET_CLEARFOG
> @@ -277,6 +282,7 @@ config SYS_CONFIG_NAME
>   	default "x530" if TARGET_X530
>   	default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
>   	default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
> +	default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
>   
>   config SYS_VENDOR
>   	default "Marvell" if TARGET_DB_MV784MP_GP
> @@ -296,6 +302,7 @@ config SYS_VENDOR
>   	default "gdsys" if TARGET_CONTROLCENTERDC
>   	default "alliedtelesis" if TARGET_X530
>   	default "mikrotik" if TARGET_CRS3XX_98DX3236
> +	default "Marvell" if TARGET_MVEBU_ALLEYCAT5
>   
>   config SYS_SOC
>   	default "mvebu"
> diff --git a/board/Marvell/mvebu_alleycat-5/MAINTAINERS b/board/Marvell/mvebu_alleycat-5/MAINTAINERS
> new file mode 100644
> index 0000000000..480c07c5f0
> --- /dev/null
> +++ b/board/Marvell/mvebu_alleycat-5/MAINTAINERS
> @@ -0,0 +1,6 @@
> +RD-AC5X BOARD
> +M:	Chris Packham <chris.packham@alliedtelesis.co.nz>
> +S:	Maintained
> +F:	board/Marvell/mvebu_alleycat-5/
> +F:	include/configs/mvebu_alleycat-5.h
> +F:	configs/mvebu_ac5_rd_defconfig
> diff --git a/board/Marvell/mvebu_alleycat-5/Makefile b/board/Marvell/mvebu_alleycat-5/Makefile
> new file mode 100644
> index 0000000000..29254b4d64
> --- /dev/null
> +++ b/board/Marvell/mvebu_alleycat-5/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier:	GPL-2.0+
> +
> +obj-y	:= board.o
> diff --git a/board/Marvell/mvebu_alleycat-5/board.c b/board/Marvell/mvebu_alleycat-5/board.c
> new file mode 100644
> index 0000000000..2d46775920
> --- /dev/null
> +++ b/board/Marvell/mvebu_alleycat-5/board.c
> @@ -0,0 +1,28 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include <common.h>
> +#include <asm/global_data.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int board_early_init_f(void)
> +{
> +	return 0;
> +}
> +
> +int board_early_init_r(void)
> +{
> +	return 0;
> +}
> +
> +int board_init(void)
> +{
> +	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> +
> +	return 0;
> +}
> +
> +int board_late_init(void)
> +{
> +	return 0;
> +}
> diff --git a/configs/mvebu_ac5_rd_defconfig b/configs/mvebu_ac5_rd_defconfig
> new file mode 100644
> index 0000000000..610d628705
> --- /dev/null
> +++ b/configs/mvebu_ac5_rd_defconfig
> @@ -0,0 +1,84 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_CPU_INIT=y
> +CONFIG_ARCH_MVEBU=y
> +CONFIG_SYS_TEXT_BASE=0x200000000
> +CONFIG_SYS_MALLOC_LEN=0x900000
> +CONFIG_TARGET_MVEBU_ALLEYCAT5=y
> +CONFIG_ENV_SIZE=0x10000
> +CONFIG_ENV_OFFSET=0x400000
> +CONFIG_ENV_SECT_SIZE=0x10000
> +CONFIG_DM_GPIO=y
> +CONFIG_SYS_LOAD_ADDR=0x202000000
> +CONFIG_SYS_MEMTEST_START=0x200800000
> +CONFIG_SYS_MEMTEST_END=0x200ffffff
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x200FF0000
> +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> +CONFIG_FIT=y
> +CONFIG_BOOTDELAY=-1
> +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
> +CONFIG_SYS_CONSOLE_INFO_QUIET=y
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
> +CONFIG_ARCH_EARLY_INIT_R=y
> +CONFIG_ARCH_MISC_INIT=y
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_CMD_BOOTZ=y
> +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
> +CONFIG_CMD_MEMTEST=y
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_PCI=y
> +CONFIG_CMD_SPI=y
> +CONFIG_CMD_USB=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_TIME=y
> +CONFIG_CMD_MVEBU_BUBT=y
> +CONFIG_CMD_REGULATOR=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_UBI=y
> +CONFIG_MAC_PARTITION=y
> +CONFIG_OF_EMBED=y
> +CONFIG_ENV_OVERWRITE=y
> +CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_CLK=y
> +CONFIG_CLK_MVEBU=y
> +CONFIG_DM_PCA953X=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_MVTWSI=y
> +CONFIG_MISC=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_XENON=y
> +CONFIG_MTD=y
> +CONFIG_SPI_FLASH_GIGADEVICE=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_SPI_FLASH_SPANSION=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_PHY_MARVELL=y
> +CONFIG_PHY_GIGE=y
> +CONFIG_E1000=y
> +CONFIG_MVNETA=y
> +CONFIG_MVMDIO=y
> +CONFIG_PCI=y
> +CONFIG_PHY=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_ARMADA_8K=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_DM_RTC=y
> +CONFIG_DM_SCSI=y
> +CONFIG_SYS_NS16550=y
> +CONFIG_MVEBU_A3700_SPI=y
> +CONFIG_DM_THERMAL=y
> +CONFIG_USB=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_HOST_ETHER=y
> +CONFIG_USB_ETHER_ASIX=y
> +CONFIG_USB_ETHER_ASIX88179=y
> +CONFIG_USB_ETHER_MCS7830=y
> +CONFIG_USB_ETHER_RTL8152=y
> +CONFIG_USB_ETHER_SMSC95XX=y
> diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h
> new file mode 100644
> index 0000000000..41bdfae6c3
> --- /dev/null
> +++ b/include/configs/mvebu_alleycat-5.h
> @@ -0,0 +1,42 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2018 Marvell International Ltd
> + */
> +
> +#ifndef _CONFIG_MVEBU_ALLEYCAY_5_H
> +#define _CONFIG_MVEBU_ALLEYCAY_5_H
> +
> +#include <asm/arch/soc.h>
> +
> +/* additions for new ARM relocation support */
> +#define CONFIG_SYS_SDRAM_BASE   0x200000000
> +
> +#define CONFIG_SYS_BAUDRATE_TABLE   { 9600, 19200, 38400, 57600, \
> +				      115200, 230400, 460800, 921600 }
> +
> +/* Default Env vars */
> +#define CONFIG_IPADDR           0.0.0.0 /* In order to cause an error */
> +#define CONFIG_SERVERIP         0.0.0.0 /* In order to cause an error */
> +#define CONFIG_NETMASK          255.255.255.0
> +#define CONFIG_GATEWAYIP        0.0.0.0
> +#define CONFIG_ROOTPATH                 "/srv/nfs/" /* Default Dir for NFS */
> +
> +#define BOOT_TARGET_DEVICES(func) \
> +	func(USB, usb, 0) \
> +	func(DHCP, dhcp, na)
> +
> +#include <config_distro_bootcmd.h>
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS   \
> +	BOOTENV \
> +	"kernel_addr_r=0x202000000\0" \
> +	"fdt_addr_r=0x201000000\0"    \
> +	"ramdisk_addr_r=0x206000000\0"    \
> +	"fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"
> +
> +/*
> + * High Level Configuration Options (easy to change)
> + */
> +#define CONFIG_SYS_TCLK     325000000
> +
> +#endif /* _CONFIG_MVEBU_ALLEYCAY_5_H */

Viele Grüße,
Stefan Roese

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de

Re: [PATCH v4 5/5] arm: mvebu: Add RD-AC5X board

[Peter Robinson]

On Wed, Nov 2, 2022 at 1:40 PM Stefan Roese <sr@denx.de> wrote:
>
> Hi Chris,
>
> On 22.09.22 05:31, Chris Packham wrote:
> > The RD-AC5X-32G16HVG6HLG-A0 development board main components and
> > features include:
> > * Main 12V/54V power supply
> > * 270 Gbps throughput packet processor on the main board
> > * DDR4:
> >    * SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
> >    * SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
> >    * PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
> > * 16GB eMMC (Samsung KLMAG1JETD-B041006)
> > * 16MB SPI NOR(GD25Q127C)
> > * 32 x 1000 Base-T interfaces
> > * 16 x 2500 Base-T interfaces
> >    * SR1: 88E2540*4
> >    * SR2: 88E2580*1+88E2540*2
> > * Six (6) x 25G Base-R SFP28 interfaces
> > * One (1) x RJ-45 console connector, interfacing to the on board UART
> > * One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
> > * One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
> > * One (1) x RJ-45 1G Base-T Management port, interfacing to the host
> >    port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy
> > * One (1) x Oculink port, interfacing to the PCIe port for external CPU
> >    connection
> > * POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~
> >    Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881
> >    solution)
> > * POE total power budget 780W
> > * LED interfaces per network port/POE
> > * LED interfaces (common) showing system status
> > * PTP TC mode Supported (Reserved M.2 connector to support BC mode)
> >
> > Signed-off-by: Chris Packham <judge.packham@gmail.com>
> > ---
> >
> > Changes in v4:
> > - Move CONFIG_DISPLAY_BOARDINFO_LATE and CONFIG_ENV_OVERWRITE to
> >    the defconfig.
> > - Remove CONFIG_BAUDRATE as this is already set in the default config
> > - Remove CONFIG_USB_MAX_CONTROLLER_COUNT as this is not needed with
> >    DM_USB
> > - Remove CONFIG_PREBOOT as we don't have anything to run
> > - Remove commented out CONFIG_BOARD_EARLY_INIT_R
> > - Remove DEBUG_UART configuration
> > - Remove unnecessary console environment variable
> > - Remove CONFIG_MVEBU_SAR
> >
> > Changes in v3:
> > - Remove MMC and UBIFS distroboot options (MMC driver is not currently
> >    functional, NAND is not populated on the RD-AC5X board)
> > - Remove unnecessary Ethernet configuration
> > - Remove unnecessary NAND configuration
> > - Remove memory node from dts so the value passed by the DDR FW will be
> >    used
> >
> > Changes in v2:
> > - Use distro boot by default
> > - remove unnecessary SPI-NOR partitions
> >
> >   arch/arm/dts/Makefile                      |   3 +-
> >   arch/arm/dts/ac5-98dx35xx-rd.dts           | 129 +++++++++++++++++++++
> >   arch/arm/mach-mvebu/Kconfig                |   9 +-
> >   board/Marvell/mvebu_alleycat-5/MAINTAINERS |   6 +
> >   board/Marvell/mvebu_alleycat-5/Makefile    |   3 +
> >   board/Marvell/mvebu_alleycat-5/board.c     |  28 +++++
> >   configs/mvebu_ac5_rd_defconfig             |  84 ++++++++++++++
> >   include/configs/mvebu_alleycat-5.h         |  42 +++++++
> >   8 files changed, 302 insertions(+), 2 deletions(-)
> >   create mode 100644 arch/arm/dts/ac5-98dx35xx-rd.dts
> >   create mode 100644 board/Marvell/mvebu_alleycat-5/MAINTAINERS
> >   create mode 100644 board/Marvell/mvebu_alleycat-5/Makefile
> >   create mode 100644 board/Marvell/mvebu_alleycat-5/board.c
> >   create mode 100644 configs/mvebu_ac5_rd_defconfig
> >   create mode 100644 include/configs/mvebu_alleycat-5.h
>
> While running a CI build I run into these issues:
>
> CONFIG_SYS_TEXT_BASE is now renamed to CONFIG_TEXT_BASE. I've already
> fixes this locally. But now I also get this compilation error:
>
> [stefan@ryzen u-boot-marvell (master)]$ make -sj
>
> Device Tree Source (arch/arm/dts/unset.dtb) is not correctly specified.
> Please define 'CONFIG_DEFAULT_DEVICE_TREE'
> or build with 'DEVICE_TREE=<device_tree>' argument
>
> make[1]: *** [dts/Makefile:34: arch/arm/dts/unset.dtb] Error 1
> make: *** [Makefile:1162: dts/dt.dtb] Error 2
>
> So where is CONFIG_DEFAULT_DEVICE_TREE defined? I might have overlooked
> this.

It would normally be a line like the following in configs/mvebu_ac5_rd_defconfig
CONFIG_DEFAULT_DEVICE_TREE="ac5-98dx35xx-rd"

> Thanks,
> Stefan
>
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index 965895bc2a..57a5272884 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -274,7 +274,8 @@ dtb-$(CONFIG_ARCH_MVEBU) +=                       \
> >       cn9132-db-A.dtb                         \
> >       cn9132-db-B.dtb                         \
> >       cn9130-crb-A.dtb                        \
> > -     cn9130-crb-B.dtb
> > +     cn9130-crb-B.dtb                        \
> > +     ac5-98dx35xx-rd.dtb
> >   endif
> >
> >   dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
> > diff --git a/arch/arm/dts/ac5-98dx35xx-rd.dts b/arch/arm/dts/ac5-98dx35xx-rd.dts
> > new file mode 100644
> > index 0000000000..d9f217cd4a
> > --- /dev/null
> > +++ b/arch/arm/dts/ac5-98dx35xx-rd.dts
> > @@ -0,0 +1,129 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree For RD-AC5X.
> > + *
> > + * Copyright (C) 2021 Marvell
> > + * Copyright (C) 2022 Allied Telesis Labs
> > + */
> > +/*
> > + * Device Tree file for Marvell Alleycat 5X development board
> > + * This board file supports the B configuration of the board
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "ac5-98dx35xx.dtsi"
> > +
> > +/ {
> > +     model = "Marvell RD-AC5X Board";
> > +     compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5";
> > +
> > +     aliases {
> > +             serial0 = &uart0;
> > +             spiflash0 = &spiflash0;
> > +             gpio0 = &gpio0;
> > +             gpio1 = &gpio1;
> > +             ethernet0 = &eth0;
> > +             ethernet1 = &eth1;
> > +             spi0 = &spi0;
> > +             i2c0 = &i2c0;
> > +             i2c1 = &i2c1;
> > +             usb0 = &usb0;
> > +             usb1 = &usb1;
> > +             pinctrl0 = &pinctrl0;
> > +             sar-reg0 = "/config-space/sar-reg";
> > +     };
> > +
> > +     usb1phy: usb-phy {
> > +             compatible = "usb-nop-xceiv";
> > +             #phy-cells = <0>;
> > +     };
> > +
> > +     chosen {
> > +             stdout-path = "serial0:115200n8";
> > +     };
> > +};
> > +
> > +&uart0 {
> > +     status = "okay";
> > +};
> > +
> > +&mdio {
> > +     phy0: ethernet-phy@0 {
> > +           reg = <0>;
> > +     };
> > +};
> > +
> > +&i2c0 {
> > +     status = "okay";
> > +};
> > +
> > +&i2c1 {
> > +     status = "okay";
> > +};
> > +
> > +&eth0 {
> > +     status = "okay";
> > +     phy-handle = <&phy0>;
> > +};
> > +
> > +/* USB0 is a host USB */
> > +&usb0 {
> > +     status = "okay";
> > +};
> > +
> > +/* USB1 is a peripheral USB */
> > +&usb1 {
> > +     status = "okay";
> > +     phys = <&usb1phy>;
> > +     phy-names = "usb-phy";
> > +     dr_mode = "peripheral";
> > +};
> > +
> > +&spi0 {
> > +     status = "okay";
> > +
> > +     spiflash0: flash@0 {
> > +             compatible = "jedec,spi-nor";
> > +             spi-max-frequency = <50000000>;
> > +             spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
> > +             spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
> > +             reg = <0>;
> > +
> > +             #address-cells = <1>;
> > +             #size-cells = <1>;
> > +     };
> > +};
> > +
> > +&pinctrl0 {
> > +     /*
> > +      * MPP Bus:     MPP#     mode#
> > +      * eMMC          [0-11]   0x1
> > +      * SPI[0]        [12-17]  0x1
> > +      * TSEN_INT      [18]     0x1
> > +      * DEV_INIT      [19]     0x1
> > +      * SPI[1]        [20-23]  0x3
> > +      * UART[1]       [24-25]  0x3
> > +      * I2C[0]        [26-27]  0x1
> > +      * XSMI[0]       [28-29]  0x1 // SCH use SMI[0], reversed due to CPSS problem
> > +      * SMI[1]        [30-31]  0x2 // SCH use XSMI[1], reversed due to CPSS problem
> > +      * UART[0]       [32-33]  0x1
> > +      * OOB_SMI       [34-35]  0x1
> > +      * PTP_CLK0_OUT  [36]     0x1
> > +      * PTP_PULSE_OUT [37]     0x1
> > +      * RCVR_CLK_OUT  [38]     0x1
> > +      * GPIO(in/out)  [39]     0x0
> > +      * GPIO(in/out)  [40]     0x0
> > +      * PTP_REF_CLK   [41]     0x1
> > +      * PTP_CLK0      [42]     0x1
> > +      * LED0_CLK      [43]     0x1
> > +      * LED0_STB      [44]     0x1
> > +      * LED0_DATA     [45]     0x1
> > +      */
> > +     /*           0    1    2    3    4    5    6    7    8    9 */
> > +     pin-func = < 1    1    1    1    1    1    1    1    1    1
> > +                  1    1    1    1    1    1    1    1    1    1
> > +                  3    3    3    3    3    3    1    1    1    1
> > +                  2    2    1    1    1    1    1    1    1    0
> > +                  0    1    1    1    1    1    >;
> > +};
> > diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> > index 45efa24194..2120cb473f 100644
> > --- a/arch/arm/mach-mvebu/Kconfig
> > +++ b/arch/arm/mach-mvebu/Kconfig
> > @@ -97,7 +97,7 @@ config CUSTOMER_BOARD_SUPPORT
> >       bool
> >
> >   choice
> > -     prompt "Armada XP/375/38x/3700/7K/8K board select"
> > +     prompt "Armada XP/375/38x/3700/7K/8K/Alleycat-5 board select"
> >       optional
> >
> >   config TARGET_CLEARFOG
> > @@ -149,6 +149,10 @@ config TARGET_MVEBU_ARMADA_8K
> >       select BOARD_LATE_INIT
> >       imply SCSI
> >
> > +config TARGET_MVEBU_ALLEYCAT5
> > +     bool "Support AlleyCat 5 platforms"
> > +     select ALLEYCAT_5
> > +
> >   config TARGET_OCTEONTX2_CN913x
> >       bool "Support CN913x platforms"
> >       select ARMADA_8K
> > @@ -257,6 +261,7 @@ config SYS_BOARD
> >       default "x530" if TARGET_X530
> >       default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
> >       default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
> > +     default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
> >
> >   config SYS_CONFIG_NAME
> >       default "clearfog" if TARGET_CLEARFOG
> > @@ -277,6 +282,7 @@ config SYS_CONFIG_NAME
> >       default "x530" if TARGET_X530
> >       default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
> >       default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
> > +     default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
> >
> >   config SYS_VENDOR
> >       default "Marvell" if TARGET_DB_MV784MP_GP
> > @@ -296,6 +302,7 @@ config SYS_VENDOR
> >       default "gdsys" if TARGET_CONTROLCENTERDC
> >       default "alliedtelesis" if TARGET_X530
> >       default "mikrotik" if TARGET_CRS3XX_98DX3236
> > +     default "Marvell" if TARGET_MVEBU_ALLEYCAT5
> >
> >   config SYS_SOC
> >       default "mvebu"
> > diff --git a/board/Marvell/mvebu_alleycat-5/MAINTAINERS b/board/Marvell/mvebu_alleycat-5/MAINTAINERS
> > new file mode 100644
> > index 0000000000..480c07c5f0
> > --- /dev/null
> > +++ b/board/Marvell/mvebu_alleycat-5/MAINTAINERS
> > @@ -0,0 +1,6 @@
> > +RD-AC5X BOARD
> > +M:   Chris Packham <chris.packham@alliedtelesis.co.nz>
> > +S:   Maintained
> > +F:   board/Marvell/mvebu_alleycat-5/
> > +F:   include/configs/mvebu_alleycat-5.h
> > +F:   configs/mvebu_ac5_rd_defconfig
> > diff --git a/board/Marvell/mvebu_alleycat-5/Makefile b/board/Marvell/mvebu_alleycat-5/Makefile
> > new file mode 100644
> > index 0000000000..29254b4d64
> > --- /dev/null
> > +++ b/board/Marvell/mvebu_alleycat-5/Makefile
> > @@ -0,0 +1,3 @@
> > +# SPDX-License-Identifier:   GPL-2.0+
> > +
> > +obj-y        := board.o
> > diff --git a/board/Marvell/mvebu_alleycat-5/board.c b/board/Marvell/mvebu_alleycat-5/board.c
> > new file mode 100644
> > index 0000000000..2d46775920
> > --- /dev/null
> > +++ b/board/Marvell/mvebu_alleycat-5/board.c
> > @@ -0,0 +1,28 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +
> > +#include <common.h>
> > +#include <asm/global_data.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +int board_early_init_f(void)
> > +{
> > +     return 0;
> > +}
> > +
> > +int board_early_init_r(void)
> > +{
> > +     return 0;
> > +}
> > +
> > +int board_init(void)
> > +{
> > +     gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> > +
> > +     return 0;
> > +}
> > +
> > +int board_late_init(void)
> > +{
> > +     return 0;
> > +}
> > diff --git a/configs/mvebu_ac5_rd_defconfig b/configs/mvebu_ac5_rd_defconfig
> > new file mode 100644
> > index 0000000000..610d628705
> > --- /dev/null
> > +++ b/configs/mvebu_ac5_rd_defconfig
> > @@ -0,0 +1,84 @@
> > +CONFIG_ARM=y
> > +CONFIG_ARCH_CPU_INIT=y
> > +CONFIG_ARCH_MVEBU=y
> > +CONFIG_SYS_TEXT_BASE=0x200000000
> > +CONFIG_SYS_MALLOC_LEN=0x900000
> > +CONFIG_TARGET_MVEBU_ALLEYCAT5=y
> > +CONFIG_ENV_SIZE=0x10000
> > +CONFIG_ENV_OFFSET=0x400000
> > +CONFIG_ENV_SECT_SIZE=0x10000
> > +CONFIG_DM_GPIO=y
> > +CONFIG_SYS_LOAD_ADDR=0x202000000
> > +CONFIG_SYS_MEMTEST_START=0x200800000
> > +CONFIG_SYS_MEMTEST_END=0x200ffffff
> > +CONFIG_DISTRO_DEFAULTS=y
> > +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> > +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x200FF0000
> > +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> > +CONFIG_FIT=y
> > +CONFIG_BOOTDELAY=-1
> > +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
> > +CONFIG_SYS_CONSOLE_INFO_QUIET=y
> > +CONFIG_DISPLAY_BOARDINFO_LATE=y
> > +CONFIG_ARCH_EARLY_INIT_R=y
> > +CONFIG_ARCH_MISC_INIT=y
> > +CONFIG_BOARD_EARLY_INIT_F=y
> > +CONFIG_CMD_BOOTZ=y
> > +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
> > +CONFIG_CMD_MEMTEST=y
> > +# CONFIG_CMD_FLASH is not set
> > +CONFIG_CMD_GPIO=y
> > +CONFIG_CMD_I2C=y
> > +CONFIG_CMD_MMC=y
> > +CONFIG_CMD_PCI=y
> > +CONFIG_CMD_SPI=y
> > +CONFIG_CMD_USB=y
> > +# CONFIG_CMD_SETEXPR is not set
> > +CONFIG_CMD_CACHE=y
> > +CONFIG_CMD_TIME=y
> > +CONFIG_CMD_MVEBU_BUBT=y
> > +CONFIG_CMD_REGULATOR=y
> > +CONFIG_CMD_EXT4_WRITE=y
> > +CONFIG_CMD_UBI=y
> > +CONFIG_MAC_PARTITION=y
> > +CONFIG_OF_EMBED=y
> > +CONFIG_ENV_OVERWRITE=y
> > +CONFIG_ENV_IS_IN_SPI_FLASH=y
> > +CONFIG_CLK=y
> > +CONFIG_CLK_MVEBU=y
> > +CONFIG_DM_PCA953X=y
> > +CONFIG_DM_I2C=y
> > +CONFIG_SYS_I2C_MVTWSI=y
> > +CONFIG_MISC=y
> > +CONFIG_MMC_SDHCI=y
> > +CONFIG_MMC_SDHCI_XENON=y
> > +CONFIG_MTD=y
> > +CONFIG_SPI_FLASH_GIGADEVICE=y
> > +CONFIG_SPI_FLASH_MACRONIX=y
> > +CONFIG_SPI_FLASH_SPANSION=y
> > +CONFIG_SPI_FLASH_STMICRO=y
> > +CONFIG_PHY_MARVELL=y
> > +CONFIG_PHY_GIGE=y
> > +CONFIG_E1000=y
> > +CONFIG_MVNETA=y
> > +CONFIG_MVMDIO=y
> > +CONFIG_PCI=y
> > +CONFIG_PHY=y
> > +CONFIG_PINCTRL=y
> > +CONFIG_PINCTRL_ARMADA_8K=y
> > +CONFIG_DM_REGULATOR_FIXED=y
> > +CONFIG_DM_REGULATOR_GPIO=y
> > +CONFIG_DM_RTC=y
> > +CONFIG_DM_SCSI=y
> > +CONFIG_SYS_NS16550=y
> > +CONFIG_MVEBU_A3700_SPI=y
> > +CONFIG_DM_THERMAL=y
> > +CONFIG_USB=y
> > +CONFIG_USB_XHCI_HCD=y
> > +CONFIG_USB_EHCI_HCD=y
> > +CONFIG_USB_HOST_ETHER=y
> > +CONFIG_USB_ETHER_ASIX=y
> > +CONFIG_USB_ETHER_ASIX88179=y
> > +CONFIG_USB_ETHER_MCS7830=y
> > +CONFIG_USB_ETHER_RTL8152=y
> > +CONFIG_USB_ETHER_SMSC95XX=y
> > diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h
> > new file mode 100644
> > index 0000000000..41bdfae6c3
> > --- /dev/null
> > +++ b/include/configs/mvebu_alleycat-5.h
> > @@ -0,0 +1,42 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (C) 2018 Marvell International Ltd
> > + */
> > +
> > +#ifndef _CONFIG_MVEBU_ALLEYCAY_5_H
> > +#define _CONFIG_MVEBU_ALLEYCAY_5_H
> > +
> > +#include <asm/arch/soc.h>
> > +
> > +/* additions for new ARM relocation support */
> > +#define CONFIG_SYS_SDRAM_BASE   0x200000000
> > +
> > +#define CONFIG_SYS_BAUDRATE_TABLE   { 9600, 19200, 38400, 57600, \
> > +                                   115200, 230400, 460800, 921600 }
> > +
> > +/* Default Env vars */
> > +#define CONFIG_IPADDR           0.0.0.0 /* In order to cause an error */
> > +#define CONFIG_SERVERIP         0.0.0.0 /* In order to cause an error */
> > +#define CONFIG_NETMASK          255.255.255.0
> > +#define CONFIG_GATEWAYIP        0.0.0.0
> > +#define CONFIG_ROOTPATH                 "/srv/nfs/" /* Default Dir for NFS */
> > +
> > +#define BOOT_TARGET_DEVICES(func) \
> > +     func(USB, usb, 0) \
> > +     func(DHCP, dhcp, na)
> > +
> > +#include <config_distro_bootcmd.h>
> > +
> > +#define CONFIG_EXTRA_ENV_SETTINGS   \
> > +     BOOTENV \
> > +     "kernel_addr_r=0x202000000\0" \
> > +     "fdt_addr_r=0x201000000\0"    \
> > +     "ramdisk_addr_r=0x206000000\0"    \
> > +     "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"
> > +
> > +/*
> > + * High Level Configuration Options (easy to change)
> > + */
> > +#define CONFIG_SYS_TCLK     325000000
> > +
> > +#endif /* _CONFIG_MVEBU_ALLEYCAY_5_H */
>
> Viele Grüße,
> Stefan Roese
>
> --
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de

Re: [PATCH v4 5/5] arm: mvebu: Add RD-AC5X board

[Stefan Roese]

(stripped-down the Cc list a bit)

On 02.11.22 14:49, Peter Robinson wrote:
> On Wed, Nov 2, 2022 at 1:40 PM Stefan Roese <sr@denx.de> wrote:
>>
>> Hi Chris,
>>
>> On 22.09.22 05:31, Chris Packham wrote:
>>> The RD-AC5X-32G16HVG6HLG-A0 development board main components and
>>> features include:
>>> * Main 12V/54V power supply
>>> * 270 Gbps throughput packet processor on the main board
>>> * DDR4:
>>>     * SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
>>>     * SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
>>>     * PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
>>> * 16GB eMMC (Samsung KLMAG1JETD-B041006)
>>> * 16MB SPI NOR(GD25Q127C)
>>> * 32 x 1000 Base-T interfaces
>>> * 16 x 2500 Base-T interfaces
>>>     * SR1: 88E2540*4
>>>     * SR2: 88E2580*1+88E2540*2
>>> * Six (6) x 25G Base-R SFP28 interfaces
>>> * One (1) x RJ-45 console connector, interfacing to the on board UART
>>> * One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
>>> * One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
>>> * One (1) x RJ-45 1G Base-T Management port, interfacing to the host
>>>     port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy
>>> * One (1) x Oculink port, interfacing to the PCIe port for external CPU
>>>     connection
>>> * POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~
>>>     Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881
>>>     solution)
>>> * POE total power budget 780W
>>> * LED interfaces per network port/POE
>>> * LED interfaces (common) showing system status
>>> * PTP TC mode Supported (Reserved M.2 connector to support BC mode)
>>>
>>> Signed-off-by: Chris Packham <judge.packham@gmail.com>
>>> ---
>>>
>>> Changes in v4:
>>> - Move CONFIG_DISPLAY_BOARDINFO_LATE and CONFIG_ENV_OVERWRITE to
>>>     the defconfig.
>>> - Remove CONFIG_BAUDRATE as this is already set in the default config
>>> - Remove CONFIG_USB_MAX_CONTROLLER_COUNT as this is not needed with
>>>     DM_USB
>>> - Remove CONFIG_PREBOOT as we don't have anything to run
>>> - Remove commented out CONFIG_BOARD_EARLY_INIT_R
>>> - Remove DEBUG_UART configuration
>>> - Remove unnecessary console environment variable
>>> - Remove CONFIG_MVEBU_SAR
>>>
>>> Changes in v3:
>>> - Remove MMC and UBIFS distroboot options (MMC driver is not currently
>>>     functional, NAND is not populated on the RD-AC5X board)
>>> - Remove unnecessary Ethernet configuration
>>> - Remove unnecessary NAND configuration
>>> - Remove memory node from dts so the value passed by the DDR FW will be
>>>     used
>>>
>>> Changes in v2:
>>> - Use distro boot by default
>>> - remove unnecessary SPI-NOR partitions
>>>
>>>    arch/arm/dts/Makefile                      |   3 +-
>>>    arch/arm/dts/ac5-98dx35xx-rd.dts           | 129 +++++++++++++++++++++
>>>    arch/arm/mach-mvebu/Kconfig                |   9 +-
>>>    board/Marvell/mvebu_alleycat-5/MAINTAINERS |   6 +
>>>    board/Marvell/mvebu_alleycat-5/Makefile    |   3 +
>>>    board/Marvell/mvebu_alleycat-5/board.c     |  28 +++++
>>>    configs/mvebu_ac5_rd_defconfig             |  84 ++++++++++++++
>>>    include/configs/mvebu_alleycat-5.h         |  42 +++++++
>>>    8 files changed, 302 insertions(+), 2 deletions(-)
>>>    create mode 100644 arch/arm/dts/ac5-98dx35xx-rd.dts
>>>    create mode 100644 board/Marvell/mvebu_alleycat-5/MAINTAINERS
>>>    create mode 100644 board/Marvell/mvebu_alleycat-5/Makefile
>>>    create mode 100644 board/Marvell/mvebu_alleycat-5/board.c
>>>    create mode 100644 configs/mvebu_ac5_rd_defconfig
>>>    create mode 100644 include/configs/mvebu_alleycat-5.h
>>
>> While running a CI build I run into these issues:
>>
>> CONFIG_SYS_TEXT_BASE is now renamed to CONFIG_TEXT_BASE. I've already
>> fixes this locally. But now I also get this compilation error:
>>
>> [stefan@ryzen u-boot-marvell (master)]$ make -sj
>>
>> Device Tree Source (arch/arm/dts/unset.dtb) is not correctly specified.
>> Please define 'CONFIG_DEFAULT_DEVICE_TREE'
>> or build with 'DEVICE_TREE=<device_tree>' argument
>>
>> make[1]: *** [dts/Makefile:34: arch/arm/dts/unset.dtb] Error 1
>> make: *** [Makefile:1162: dts/dt.dtb] Error 2
>>
>> So where is CONFIG_DEFAULT_DEVICE_TREE defined? I might have overlooked
>> this.
> 
> It would normally be a line like the following in configs/mvebu_ac5_rd_defconfig
> CONFIG_DEFAULT_DEVICE_TREE="ac5-98dx35xx-rd"

Right. But I'm wondering how this worked for Chris. He should have
gotten this error as well before submitting this patch.

Thanks,
Stefan

>> Thanks,
>> Stefan
>>
>>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>>> index 965895bc2a..57a5272884 100644
>>> --- a/arch/arm/dts/Makefile
>>> +++ b/arch/arm/dts/Makefile
>>> @@ -274,7 +274,8 @@ dtb-$(CONFIG_ARCH_MVEBU) +=                       \
>>>        cn9132-db-A.dtb                         \
>>>        cn9132-db-B.dtb                         \
>>>        cn9130-crb-A.dtb                        \
>>> -     cn9130-crb-B.dtb
>>> +     cn9130-crb-B.dtb                        \
>>> +     ac5-98dx35xx-rd.dtb
>>>    endif
>>>
>>>    dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
>>> diff --git a/arch/arm/dts/ac5-98dx35xx-rd.dts b/arch/arm/dts/ac5-98dx35xx-rd.dts
>>> new file mode 100644
>>> index 0000000000..d9f217cd4a
>>> --- /dev/null
>>> +++ b/arch/arm/dts/ac5-98dx35xx-rd.dts
>>> @@ -0,0 +1,129 @@
>>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>>> +/*
>>> + * Device Tree For RD-AC5X.
>>> + *
>>> + * Copyright (C) 2021 Marvell
>>> + * Copyright (C) 2022 Allied Telesis Labs
>>> + */
>>> +/*
>>> + * Device Tree file for Marvell Alleycat 5X development board
>>> + * This board file supports the B configuration of the board
>>> + */
>>> +
>>> +/dts-v1/;
>>> +
>>> +#include "ac5-98dx35xx.dtsi"
>>> +
>>> +/ {
>>> +     model = "Marvell RD-AC5X Board";
>>> +     compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5";
>>> +
>>> +     aliases {
>>> +             serial0 = &uart0;
>>> +             spiflash0 = &spiflash0;
>>> +             gpio0 = &gpio0;
>>> +             gpio1 = &gpio1;
>>> +             ethernet0 = &eth0;
>>> +             ethernet1 = &eth1;
>>> +             spi0 = &spi0;
>>> +             i2c0 = &i2c0;
>>> +             i2c1 = &i2c1;
>>> +             usb0 = &usb0;
>>> +             usb1 = &usb1;
>>> +             pinctrl0 = &pinctrl0;
>>> +             sar-reg0 = "/config-space/sar-reg";
>>> +     };
>>> +
>>> +     usb1phy: usb-phy {
>>> +             compatible = "usb-nop-xceiv";
>>> +             #phy-cells = <0>;
>>> +     };
>>> +
>>> +     chosen {
>>> +             stdout-path = "serial0:115200n8";
>>> +     };
>>> +};
>>> +
>>> +&uart0 {
>>> +     status = "okay";
>>> +};
>>> +
>>> +&mdio {
>>> +     phy0: ethernet-phy@0 {
>>> +           reg = <0>;
>>> +     };
>>> +};
>>> +
>>> +&i2c0 {
>>> +     status = "okay";
>>> +};
>>> +
>>> +&i2c1 {
>>> +     status = "okay";
>>> +};
>>> +
>>> +&eth0 {
>>> +     status = "okay";
>>> +     phy-handle = <&phy0>;
>>> +};
>>> +
>>> +/* USB0 is a host USB */
>>> +&usb0 {
>>> +     status = "okay";
>>> +};
>>> +
>>> +/* USB1 is a peripheral USB */
>>> +&usb1 {
>>> +     status = "okay";
>>> +     phys = <&usb1phy>;
>>> +     phy-names = "usb-phy";
>>> +     dr_mode = "peripheral";
>>> +};
>>> +
>>> +&spi0 {
>>> +     status = "okay";
>>> +
>>> +     spiflash0: flash@0 {
>>> +             compatible = "jedec,spi-nor";
>>> +             spi-max-frequency = <50000000>;
>>> +             spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
>>> +             spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
>>> +             reg = <0>;
>>> +
>>> +             #address-cells = <1>;
>>> +             #size-cells = <1>;
>>> +     };
>>> +};
>>> +
>>> +&pinctrl0 {
>>> +     /*
>>> +      * MPP Bus:     MPP#     mode#
>>> +      * eMMC          [0-11]   0x1
>>> +      * SPI[0]        [12-17]  0x1
>>> +      * TSEN_INT      [18]     0x1
>>> +      * DEV_INIT      [19]     0x1
>>> +      * SPI[1]        [20-23]  0x3
>>> +      * UART[1]       [24-25]  0x3
>>> +      * I2C[0]        [26-27]  0x1
>>> +      * XSMI[0]       [28-29]  0x1 // SCH use SMI[0], reversed due to CPSS problem
>>> +      * SMI[1]        [30-31]  0x2 // SCH use XSMI[1], reversed due to CPSS problem
>>> +      * UART[0]       [32-33]  0x1
>>> +      * OOB_SMI       [34-35]  0x1
>>> +      * PTP_CLK0_OUT  [36]     0x1
>>> +      * PTP_PULSE_OUT [37]     0x1
>>> +      * RCVR_CLK_OUT  [38]     0x1
>>> +      * GPIO(in/out)  [39]     0x0
>>> +      * GPIO(in/out)  [40]     0x0
>>> +      * PTP_REF_CLK   [41]     0x1
>>> +      * PTP_CLK0      [42]     0x1
>>> +      * LED0_CLK      [43]     0x1
>>> +      * LED0_STB      [44]     0x1
>>> +      * LED0_DATA     [45]     0x1
>>> +      */
>>> +     /*           0    1    2    3    4    5    6    7    8    9 */
>>> +     pin-func = < 1    1    1    1    1    1    1    1    1    1
>>> +                  1    1    1    1    1    1    1    1    1    1
>>> +                  3    3    3    3    3    3    1    1    1    1
>>> +                  2    2    1    1    1    1    1    1    1    0
>>> +                  0    1    1    1    1    1    >;
>>> +};
>>> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
>>> index 45efa24194..2120cb473f 100644
>>> --- a/arch/arm/mach-mvebu/Kconfig
>>> +++ b/arch/arm/mach-mvebu/Kconfig
>>> @@ -97,7 +97,7 @@ config CUSTOMER_BOARD_SUPPORT
>>>        bool
>>>
>>>    choice
>>> -     prompt "Armada XP/375/38x/3700/7K/8K board select"
>>> +     prompt "Armada XP/375/38x/3700/7K/8K/Alleycat-5 board select"
>>>        optional
>>>
>>>    config TARGET_CLEARFOG
>>> @@ -149,6 +149,10 @@ config TARGET_MVEBU_ARMADA_8K
>>>        select BOARD_LATE_INIT
>>>        imply SCSI
>>>
>>> +config TARGET_MVEBU_ALLEYCAT5
>>> +     bool "Support AlleyCat 5 platforms"
>>> +     select ALLEYCAT_5
>>> +
>>>    config TARGET_OCTEONTX2_CN913x
>>>        bool "Support CN913x platforms"
>>>        select ARMADA_8K
>>> @@ -257,6 +261,7 @@ config SYS_BOARD
>>>        default "x530" if TARGET_X530
>>>        default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
>>>        default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
>>> +     default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
>>>
>>>    config SYS_CONFIG_NAME
>>>        default "clearfog" if TARGET_CLEARFOG
>>> @@ -277,6 +282,7 @@ config SYS_CONFIG_NAME
>>>        default "x530" if TARGET_X530
>>>        default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
>>>        default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
>>> +     default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
>>>
>>>    config SYS_VENDOR
>>>        default "Marvell" if TARGET_DB_MV784MP_GP
>>> @@ -296,6 +302,7 @@ config SYS_VENDOR
>>>        default "gdsys" if TARGET_CONTROLCENTERDC
>>>        default "alliedtelesis" if TARGET_X530
>>>        default "mikrotik" if TARGET_CRS3XX_98DX3236
>>> +     default "Marvell" if TARGET_MVEBU_ALLEYCAT5
>>>
>>>    config SYS_SOC
>>>        default "mvebu"
>>> diff --git a/board/Marvell/mvebu_alleycat-5/MAINTAINERS b/board/Marvell/mvebu_alleycat-5/MAINTAINERS
>>> new file mode 100644
>>> index 0000000000..480c07c5f0
>>> --- /dev/null
>>> +++ b/board/Marvell/mvebu_alleycat-5/MAINTAINERS
>>> @@ -0,0 +1,6 @@
>>> +RD-AC5X BOARD
>>> +M:   Chris Packham <chris.packham@alliedtelesis.co.nz>
>>> +S:   Maintained
>>> +F:   board/Marvell/mvebu_alleycat-5/
>>> +F:   include/configs/mvebu_alleycat-5.h
>>> +F:   configs/mvebu_ac5_rd_defconfig
>>> diff --git a/board/Marvell/mvebu_alleycat-5/Makefile b/board/Marvell/mvebu_alleycat-5/Makefile
>>> new file mode 100644
>>> index 0000000000..29254b4d64
>>> --- /dev/null
>>> +++ b/board/Marvell/mvebu_alleycat-5/Makefile
>>> @@ -0,0 +1,3 @@
>>> +# SPDX-License-Identifier:   GPL-2.0+
>>> +
>>> +obj-y        := board.o
>>> diff --git a/board/Marvell/mvebu_alleycat-5/board.c b/board/Marvell/mvebu_alleycat-5/board.c
>>> new file mode 100644
>>> index 0000000000..2d46775920
>>> --- /dev/null
>>> +++ b/board/Marvell/mvebu_alleycat-5/board.c
>>> @@ -0,0 +1,28 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +
>>> +#include <common.h>
>>> +#include <asm/global_data.h>
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +int board_early_init_f(void)
>>> +{
>>> +     return 0;
>>> +}
>>> +
>>> +int board_early_init_r(void)
>>> +{
>>> +     return 0;
>>> +}
>>> +
>>> +int board_init(void)
>>> +{
>>> +     gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
>>> +
>>> +     return 0;
>>> +}
>>> +
>>> +int board_late_init(void)
>>> +{
>>> +     return 0;
>>> +}
>>> diff --git a/configs/mvebu_ac5_rd_defconfig b/configs/mvebu_ac5_rd_defconfig
>>> new file mode 100644
>>> index 0000000000..610d628705
>>> --- /dev/null
>>> +++ b/configs/mvebu_ac5_rd_defconfig
>>> @@ -0,0 +1,84 @@
>>> +CONFIG_ARM=y
>>> +CONFIG_ARCH_CPU_INIT=y
>>> +CONFIG_ARCH_MVEBU=y
>>> +CONFIG_SYS_TEXT_BASE=0x200000000
>>> +CONFIG_SYS_MALLOC_LEN=0x900000
>>> +CONFIG_TARGET_MVEBU_ALLEYCAT5=y
>>> +CONFIG_ENV_SIZE=0x10000
>>> +CONFIG_ENV_OFFSET=0x400000
>>> +CONFIG_ENV_SECT_SIZE=0x10000
>>> +CONFIG_DM_GPIO=y
>>> +CONFIG_SYS_LOAD_ADDR=0x202000000
>>> +CONFIG_SYS_MEMTEST_START=0x200800000
>>> +CONFIG_SYS_MEMTEST_END=0x200ffffff
>>> +CONFIG_DISTRO_DEFAULTS=y
>>> +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>>> +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x200FF0000
>>> +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>>> +CONFIG_FIT=y
>>> +CONFIG_BOOTDELAY=-1
>>> +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
>>> +CONFIG_SYS_CONSOLE_INFO_QUIET=y
>>> +CONFIG_DISPLAY_BOARDINFO_LATE=y
>>> +CONFIG_ARCH_EARLY_INIT_R=y
>>> +CONFIG_ARCH_MISC_INIT=y
>>> +CONFIG_BOARD_EARLY_INIT_F=y
>>> +CONFIG_CMD_BOOTZ=y
>>> +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
>>> +CONFIG_CMD_MEMTEST=y
>>> +# CONFIG_CMD_FLASH is not set
>>> +CONFIG_CMD_GPIO=y
>>> +CONFIG_CMD_I2C=y
>>> +CONFIG_CMD_MMC=y
>>> +CONFIG_CMD_PCI=y
>>> +CONFIG_CMD_SPI=y
>>> +CONFIG_CMD_USB=y
>>> +# CONFIG_CMD_SETEXPR is not set
>>> +CONFIG_CMD_CACHE=y
>>> +CONFIG_CMD_TIME=y
>>> +CONFIG_CMD_MVEBU_BUBT=y
>>> +CONFIG_CMD_REGULATOR=y
>>> +CONFIG_CMD_EXT4_WRITE=y
>>> +CONFIG_CMD_UBI=y
>>> +CONFIG_MAC_PARTITION=y
>>> +CONFIG_OF_EMBED=y
>>> +CONFIG_ENV_OVERWRITE=y
>>> +CONFIG_ENV_IS_IN_SPI_FLASH=y
>>> +CONFIG_CLK=y
>>> +CONFIG_CLK_MVEBU=y
>>> +CONFIG_DM_PCA953X=y
>>> +CONFIG_DM_I2C=y
>>> +CONFIG_SYS_I2C_MVTWSI=y
>>> +CONFIG_MISC=y
>>> +CONFIG_MMC_SDHCI=y
>>> +CONFIG_MMC_SDHCI_XENON=y
>>> +CONFIG_MTD=y
>>> +CONFIG_SPI_FLASH_GIGADEVICE=y
>>> +CONFIG_SPI_FLASH_MACRONIX=y
>>> +CONFIG_SPI_FLASH_SPANSION=y
>>> +CONFIG_SPI_FLASH_STMICRO=y
>>> +CONFIG_PHY_MARVELL=y
>>> +CONFIG_PHY_GIGE=y
>>> +CONFIG_E1000=y
>>> +CONFIG_MVNETA=y
>>> +CONFIG_MVMDIO=y
>>> +CONFIG_PCI=y
>>> +CONFIG_PHY=y
>>> +CONFIG_PINCTRL=y
>>> +CONFIG_PINCTRL_ARMADA_8K=y
>>> +CONFIG_DM_REGULATOR_FIXED=y
>>> +CONFIG_DM_REGULATOR_GPIO=y
>>> +CONFIG_DM_RTC=y
>>> +CONFIG_DM_SCSI=y
>>> +CONFIG_SYS_NS16550=y
>>> +CONFIG_MVEBU_A3700_SPI=y
>>> +CONFIG_DM_THERMAL=y
>>> +CONFIG_USB=y
>>> +CONFIG_USB_XHCI_HCD=y
>>> +CONFIG_USB_EHCI_HCD=y
>>> +CONFIG_USB_HOST_ETHER=y
>>> +CONFIG_USB_ETHER_ASIX=y
>>> +CONFIG_USB_ETHER_ASIX88179=y
>>> +CONFIG_USB_ETHER_MCS7830=y
>>> +CONFIG_USB_ETHER_RTL8152=y
>>> +CONFIG_USB_ETHER_SMSC95XX=y
>>> diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h
>>> new file mode 100644
>>> index 0000000000..41bdfae6c3
>>> --- /dev/null
>>> +++ b/include/configs/mvebu_alleycat-5.h
>>> @@ -0,0 +1,42 @@
>>> +/* SPDX-License-Identifier: GPL-2.0+ */
>>> +/*
>>> + * Copyright (C) 2018 Marvell International Ltd
>>> + */
>>> +
>>> +#ifndef _CONFIG_MVEBU_ALLEYCAY_5_H
>>> +#define _CONFIG_MVEBU_ALLEYCAY_5_H
>>> +
>>> +#include <asm/arch/soc.h>
>>> +
>>> +/* additions for new ARM relocation support */
>>> +#define CONFIG_SYS_SDRAM_BASE   0x200000000
>>> +
>>> +#define CONFIG_SYS_BAUDRATE_TABLE   { 9600, 19200, 38400, 57600, \
>>> +                                   115200, 230400, 460800, 921600 }
>>> +
>>> +/* Default Env vars */
>>> +#define CONFIG_IPADDR           0.0.0.0 /* In order to cause an error */
>>> +#define CONFIG_SERVERIP         0.0.0.0 /* In order to cause an error */
>>> +#define CONFIG_NETMASK          255.255.255.0
>>> +#define CONFIG_GATEWAYIP        0.0.0.0
>>> +#define CONFIG_ROOTPATH                 "/srv/nfs/" /* Default Dir for NFS */
>>> +
>>> +#define BOOT_TARGET_DEVICES(func) \
>>> +     func(USB, usb, 0) \
>>> +     func(DHCP, dhcp, na)
>>> +
>>> +#include <config_distro_bootcmd.h>
>>> +
>>> +#define CONFIG_EXTRA_ENV_SETTINGS   \
>>> +     BOOTENV \
>>> +     "kernel_addr_r=0x202000000\0" \
>>> +     "fdt_addr_r=0x201000000\0"    \
>>> +     "ramdisk_addr_r=0x206000000\0"    \
>>> +     "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"
>>> +
>>> +/*
>>> + * High Level Configuration Options (easy to change)
>>> + */
>>> +#define CONFIG_SYS_TCLK     325000000
>>> +
>>> +#endif /* _CONFIG_MVEBU_ALLEYCAY_5_H */
>>
>> Viele Grüße,
>> Stefan Roese
>>
>> --
>> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
>> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>> Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de

Viele Grüße,
Stefan Roese

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de

Re: [PATCH v4 5/5] arm: mvebu: Add RD-AC5X board

[Chris Packham]

On Thu, Nov 3, 2022 at 2:40 AM Stefan Roese <sr@denx.de> wrote:
>
> Hi Chris,
>
> On 22.09.22 05:31, Chris Packham wrote:
> > The RD-AC5X-32G16HVG6HLG-A0 development board main components and
> > features include:
> > * Main 12V/54V power supply
> > * 270 Gbps throughput packet processor on the main board
> > * DDR4:
> >    * SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
> >    * SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
> >    * PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
> > * 16GB eMMC (Samsung KLMAG1JETD-B041006)
> > * 16MB SPI NOR(GD25Q127C)
> > * 32 x 1000 Base-T interfaces
> > * 16 x 2500 Base-T interfaces
> >    * SR1: 88E2540*4
> >    * SR2: 88E2580*1+88E2540*2
> > * Six (6) x 25G Base-R SFP28 interfaces
> > * One (1) x RJ-45 console connector, interfacing to the on board UART
> > * One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
> > * One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
> > * One (1) x RJ-45 1G Base-T Management port, interfacing to the host
> >    port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy
> > * One (1) x Oculink port, interfacing to the PCIe port for external CPU
> >    connection
> > * POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~
> >    Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881
> >    solution)
> > * POE total power budget 780W
> > * LED interfaces per network port/POE
> > * LED interfaces (common) showing system status
> > * PTP TC mode Supported (Reserved M.2 connector to support BC mode)
> >
> > Signed-off-by: Chris Packham <judge.packham@gmail.com>
> > ---
> >
> > Changes in v4:
> > - Move CONFIG_DISPLAY_BOARDINFO_LATE and CONFIG_ENV_OVERWRITE to
> >    the defconfig.
> > - Remove CONFIG_BAUDRATE as this is already set in the default config
> > - Remove CONFIG_USB_MAX_CONTROLLER_COUNT as this is not needed with
> >    DM_USB
> > - Remove CONFIG_PREBOOT as we don't have anything to run
> > - Remove commented out CONFIG_BOARD_EARLY_INIT_R
> > - Remove DEBUG_UART configuration
> > - Remove unnecessary console environment variable
> > - Remove CONFIG_MVEBU_SAR
> >
> > Changes in v3:
> > - Remove MMC and UBIFS distroboot options (MMC driver is not currently
> >    functional, NAND is not populated on the RD-AC5X board)
> > - Remove unnecessary Ethernet configuration
> > - Remove unnecessary NAND configuration
> > - Remove memory node from dts so the value passed by the DDR FW will be
> >    used
> >
> > Changes in v2:
> > - Use distro boot by default
> > - remove unnecessary SPI-NOR partitions
> >
> >   arch/arm/dts/Makefile                      |   3 +-
> >   arch/arm/dts/ac5-98dx35xx-rd.dts           | 129 +++++++++++++++++++++
> >   arch/arm/mach-mvebu/Kconfig                |   9 +-
> >   board/Marvell/mvebu_alleycat-5/MAINTAINERS |   6 +
> >   board/Marvell/mvebu_alleycat-5/Makefile    |   3 +
> >   board/Marvell/mvebu_alleycat-5/board.c     |  28 +++++
> >   configs/mvebu_ac5_rd_defconfig             |  84 ++++++++++++++
> >   include/configs/mvebu_alleycat-5.h         |  42 +++++++
> >   8 files changed, 302 insertions(+), 2 deletions(-)
> >   create mode 100644 arch/arm/dts/ac5-98dx35xx-rd.dts
> >   create mode 100644 board/Marvell/mvebu_alleycat-5/MAINTAINERS
> >   create mode 100644 board/Marvell/mvebu_alleycat-5/Makefile
> >   create mode 100644 board/Marvell/mvebu_alleycat-5/board.c
> >   create mode 100644 configs/mvebu_ac5_rd_defconfig
> >   create mode 100644 include/configs/mvebu_alleycat-5.h
>
> While running a CI build I run into these issues:
>
> CONFIG_SYS_TEXT_BASE is now renamed to CONFIG_TEXT_BASE. I've already
> fixes this locally. But now I also get this compilation error:
>
> [stefan@ryzen u-boot-marvell (master)]$ make -sj
>
> Device Tree Source (arch/arm/dts/unset.dtb) is not correctly specified.
> Please define 'CONFIG_DEFAULT_DEVICE_TREE'
> or build with 'DEVICE_TREE=<device_tree>' argument
>
> make[1]: *** [dts/Makefile:34: arch/arm/dts/unset.dtb] Error 1
> make: *** [Makefile:1162: dts/dt.dtb] Error 2
>
> So where is CONFIG_DEFAULT_DEVICE_TREE defined? I might have overlooked
> this.
>

Ah. Because these arm64 SoCs need other components in the "bootloader"
I've been using a meta build system that passes DEVICE_TREE= on the
make command line. I'll rebase the series and add fixup
CONFIG_TEXT_BASE/CONFIG_DEFAULT_DEVICE_TREE.

> Thanks,
> Stefan
>
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index 965895bc2a..57a5272884 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -274,7 +274,8 @@ dtb-$(CONFIG_ARCH_MVEBU) +=                       \
> >       cn9132-db-A.dtb                         \
> >       cn9132-db-B.dtb                         \
> >       cn9130-crb-A.dtb                        \
> > -     cn9130-crb-B.dtb
> > +     cn9130-crb-B.dtb                        \
> > +     ac5-98dx35xx-rd.dtb
> >   endif
> >
> >   dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
> > diff --git a/arch/arm/dts/ac5-98dx35xx-rd.dts b/arch/arm/dts/ac5-98dx35xx-rd.dts
> > new file mode 100644
> > index 0000000000..d9f217cd4a
> > --- /dev/null
> > +++ b/arch/arm/dts/ac5-98dx35xx-rd.dts
> > @@ -0,0 +1,129 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree For RD-AC5X.
> > + *
> > + * Copyright (C) 2021 Marvell
> > + * Copyright (C) 2022 Allied Telesis Labs
> > + */
> > +/*
> > + * Device Tree file for Marvell Alleycat 5X development board
> > + * This board file supports the B configuration of the board
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "ac5-98dx35xx.dtsi"
> > +
> > +/ {
> > +     model = "Marvell RD-AC5X Board";
> > +     compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5";
> > +
> > +     aliases {
> > +             serial0 = &uart0;
> > +             spiflash0 = &spiflash0;
> > +             gpio0 = &gpio0;
> > +             gpio1 = &gpio1;
> > +             ethernet0 = &eth0;
> > +             ethernet1 = &eth1;
> > +             spi0 = &spi0;
> > +             i2c0 = &i2c0;
> > +             i2c1 = &i2c1;
> > +             usb0 = &usb0;
> > +             usb1 = &usb1;
> > +             pinctrl0 = &pinctrl0;
> > +             sar-reg0 = "/config-space/sar-reg";
> > +     };
> > +
> > +     usb1phy: usb-phy {
> > +             compatible = "usb-nop-xceiv";
> > +             #phy-cells = <0>;
> > +     };
> > +
> > +     chosen {
> > +             stdout-path = "serial0:115200n8";
> > +     };
> > +};
> > +
> > +&uart0 {
> > +     status = "okay";
> > +};
> > +
> > +&mdio {
> > +     phy0: ethernet-phy@0 {
> > +           reg = <0>;
> > +     };
> > +};
> > +
> > +&i2c0 {
> > +     status = "okay";
> > +};
> > +
> > +&i2c1 {
> > +     status = "okay";
> > +};
> > +
> > +&eth0 {
> > +     status = "okay";
> > +     phy-handle = <&phy0>;
> > +};
> > +
> > +/* USB0 is a host USB */
> > +&usb0 {
> > +     status = "okay";
> > +};
> > +
> > +/* USB1 is a peripheral USB */
> > +&usb1 {
> > +     status = "okay";
> > +     phys = <&usb1phy>;
> > +     phy-names = "usb-phy";
> > +     dr_mode = "peripheral";
> > +};
> > +
> > +&spi0 {
> > +     status = "okay";
> > +
> > +     spiflash0: flash@0 {
> > +             compatible = "jedec,spi-nor";
> > +             spi-max-frequency = <50000000>;
> > +             spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
> > +             spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
> > +             reg = <0>;
> > +
> > +             #address-cells = <1>;
> > +             #size-cells = <1>;
> > +     };
> > +};
> > +
> > +&pinctrl0 {
> > +     /*
> > +      * MPP Bus:     MPP#     mode#
> > +      * eMMC          [0-11]   0x1
> > +      * SPI[0]        [12-17]  0x1
> > +      * TSEN_INT      [18]     0x1
> > +      * DEV_INIT      [19]     0x1
> > +      * SPI[1]        [20-23]  0x3
> > +      * UART[1]       [24-25]  0x3
> > +      * I2C[0]        [26-27]  0x1
> > +      * XSMI[0]       [28-29]  0x1 // SCH use SMI[0], reversed due to CPSS problem
> > +      * SMI[1]        [30-31]  0x2 // SCH use XSMI[1], reversed due to CPSS problem
> > +      * UART[0]       [32-33]  0x1
> > +      * OOB_SMI       [34-35]  0x1
> > +      * PTP_CLK0_OUT  [36]     0x1
> > +      * PTP_PULSE_OUT [37]     0x1
> > +      * RCVR_CLK_OUT  [38]     0x1
> > +      * GPIO(in/out)  [39]     0x0
> > +      * GPIO(in/out)  [40]     0x0
> > +      * PTP_REF_CLK   [41]     0x1
> > +      * PTP_CLK0      [42]     0x1
> > +      * LED0_CLK      [43]     0x1
> > +      * LED0_STB      [44]     0x1
> > +      * LED0_DATA     [45]     0x1
> > +      */
> > +     /*           0    1    2    3    4    5    6    7    8    9 */
> > +     pin-func = < 1    1    1    1    1    1    1    1    1    1
> > +                  1    1    1    1    1    1    1    1    1    1
> > +                  3    3    3    3    3    3    1    1    1    1
> > +                  2    2    1    1    1    1    1    1    1    0
> > +                  0    1    1    1    1    1    >;
> > +};
> > diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> > index 45efa24194..2120cb473f 100644
> > --- a/arch/arm/mach-mvebu/Kconfig
> > +++ b/arch/arm/mach-mvebu/Kconfig
> > @@ -97,7 +97,7 @@ config CUSTOMER_BOARD_SUPPORT
> >       bool
> >
> >   choice
> > -     prompt "Armada XP/375/38x/3700/7K/8K board select"
> > +     prompt "Armada XP/375/38x/3700/7K/8K/Alleycat-5 board select"
> >       optional
> >
> >   config TARGET_CLEARFOG
> > @@ -149,6 +149,10 @@ config TARGET_MVEBU_ARMADA_8K
> >       select BOARD_LATE_INIT
> >       imply SCSI
> >
> > +config TARGET_MVEBU_ALLEYCAT5
> > +     bool "Support AlleyCat 5 platforms"
> > +     select ALLEYCAT_5
> > +
> >   config TARGET_OCTEONTX2_CN913x
> >       bool "Support CN913x platforms"
> >       select ARMADA_8K
> > @@ -257,6 +261,7 @@ config SYS_BOARD
> >       default "x530" if TARGET_X530
> >       default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
> >       default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
> > +     default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
> >
> >   config SYS_CONFIG_NAME
> >       default "clearfog" if TARGET_CLEARFOG
> > @@ -277,6 +282,7 @@ config SYS_CONFIG_NAME
> >       default "x530" if TARGET_X530
> >       default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
> >       default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
> > +     default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
> >
> >   config SYS_VENDOR
> >       default "Marvell" if TARGET_DB_MV784MP_GP
> > @@ -296,6 +302,7 @@ config SYS_VENDOR
> >       default "gdsys" if TARGET_CONTROLCENTERDC
> >       default "alliedtelesis" if TARGET_X530
> >       default "mikrotik" if TARGET_CRS3XX_98DX3236
> > +     default "Marvell" if TARGET_MVEBU_ALLEYCAT5
> >
> >   config SYS_SOC
> >       default "mvebu"
> > diff --git a/board/Marvell/mvebu_alleycat-5/MAINTAINERS b/board/Marvell/mvebu_alleycat-5/MAINTAINERS
> > new file mode 100644
> > index 0000000000..480c07c5f0
> > --- /dev/null
> > +++ b/board/Marvell/mvebu_alleycat-5/MAINTAINERS
> > @@ -0,0 +1,6 @@
> > +RD-AC5X BOARD
> > +M:   Chris Packham <chris.packham@alliedtelesis.co.nz>
> > +S:   Maintained
> > +F:   board/Marvell/mvebu_alleycat-5/
> > +F:   include/configs/mvebu_alleycat-5.h
> > +F:   configs/mvebu_ac5_rd_defconfig
> > diff --git a/board/Marvell/mvebu_alleycat-5/Makefile b/board/Marvell/mvebu_alleycat-5/Makefile
> > new file mode 100644
> > index 0000000000..29254b4d64
> > --- /dev/null
> > +++ b/board/Marvell/mvebu_alleycat-5/Makefile
> > @@ -0,0 +1,3 @@
> > +# SPDX-License-Identifier:   GPL-2.0+
> > +
> > +obj-y        := board.o
> > diff --git a/board/Marvell/mvebu_alleycat-5/board.c b/board/Marvell/mvebu_alleycat-5/board.c
> > new file mode 100644
> > index 0000000000..2d46775920
> > --- /dev/null
> > +++ b/board/Marvell/mvebu_alleycat-5/board.c
> > @@ -0,0 +1,28 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +
> > +#include <common.h>
> > +#include <asm/global_data.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +int board_early_init_f(void)
> > +{
> > +     return 0;
> > +}
> > +
> > +int board_early_init_r(void)
> > +{
> > +     return 0;
> > +}
> > +
> > +int board_init(void)
> > +{
> > +     gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> > +
> > +     return 0;
> > +}
> > +
> > +int board_late_init(void)
> > +{
> > +     return 0;
> > +}
> > diff --git a/configs/mvebu_ac5_rd_defconfig b/configs/mvebu_ac5_rd_defconfig
> > new file mode 100644
> > index 0000000000..610d628705
> > --- /dev/null
> > +++ b/configs/mvebu_ac5_rd_defconfig
> > @@ -0,0 +1,84 @@
> > +CONFIG_ARM=y
> > +CONFIG_ARCH_CPU_INIT=y
> > +CONFIG_ARCH_MVEBU=y
> > +CONFIG_SYS_TEXT_BASE=0x200000000
> > +CONFIG_SYS_MALLOC_LEN=0x900000
> > +CONFIG_TARGET_MVEBU_ALLEYCAT5=y
> > +CONFIG_ENV_SIZE=0x10000
> > +CONFIG_ENV_OFFSET=0x400000
> > +CONFIG_ENV_SECT_SIZE=0x10000
> > +CONFIG_DM_GPIO=y
> > +CONFIG_SYS_LOAD_ADDR=0x202000000
> > +CONFIG_SYS_MEMTEST_START=0x200800000
> > +CONFIG_SYS_MEMTEST_END=0x200ffffff
> > +CONFIG_DISTRO_DEFAULTS=y
> > +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> > +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x200FF0000
> > +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> > +CONFIG_FIT=y
> > +CONFIG_BOOTDELAY=-1
> > +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
> > +CONFIG_SYS_CONSOLE_INFO_QUIET=y
> > +CONFIG_DISPLAY_BOARDINFO_LATE=y
> > +CONFIG_ARCH_EARLY_INIT_R=y
> > +CONFIG_ARCH_MISC_INIT=y
> > +CONFIG_BOARD_EARLY_INIT_F=y
> > +CONFIG_CMD_BOOTZ=y
> > +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
> > +CONFIG_CMD_MEMTEST=y
> > +# CONFIG_CMD_FLASH is not set
> > +CONFIG_CMD_GPIO=y
> > +CONFIG_CMD_I2C=y
> > +CONFIG_CMD_MMC=y
> > +CONFIG_CMD_PCI=y
> > +CONFIG_CMD_SPI=y
> > +CONFIG_CMD_USB=y
> > +# CONFIG_CMD_SETEXPR is not set
> > +CONFIG_CMD_CACHE=y
> > +CONFIG_CMD_TIME=y
> > +CONFIG_CMD_MVEBU_BUBT=y
> > +CONFIG_CMD_REGULATOR=y
> > +CONFIG_CMD_EXT4_WRITE=y
> > +CONFIG_CMD_UBI=y
> > +CONFIG_MAC_PARTITION=y
> > +CONFIG_OF_EMBED=y
> > +CONFIG_ENV_OVERWRITE=y
> > +CONFIG_ENV_IS_IN_SPI_FLASH=y
> > +CONFIG_CLK=y
> > +CONFIG_CLK_MVEBU=y
> > +CONFIG_DM_PCA953X=y
> > +CONFIG_DM_I2C=y
> > +CONFIG_SYS_I2C_MVTWSI=y
> > +CONFIG_MISC=y
> > +CONFIG_MMC_SDHCI=y
> > +CONFIG_MMC_SDHCI_XENON=y
> > +CONFIG_MTD=y
> > +CONFIG_SPI_FLASH_GIGADEVICE=y
> > +CONFIG_SPI_FLASH_MACRONIX=y
> > +CONFIG_SPI_FLASH_SPANSION=y
> > +CONFIG_SPI_FLASH_STMICRO=y
> > +CONFIG_PHY_MARVELL=y
> > +CONFIG_PHY_GIGE=y
> > +CONFIG_E1000=y
> > +CONFIG_MVNETA=y
> > +CONFIG_MVMDIO=y
> > +CONFIG_PCI=y
> > +CONFIG_PHY=y
> > +CONFIG_PINCTRL=y
> > +CONFIG_PINCTRL_ARMADA_8K=y
> > +CONFIG_DM_REGULATOR_FIXED=y
> > +CONFIG_DM_REGULATOR_GPIO=y
> > +CONFIG_DM_RTC=y
> > +CONFIG_DM_SCSI=y
> > +CONFIG_SYS_NS16550=y
> > +CONFIG_MVEBU_A3700_SPI=y
> > +CONFIG_DM_THERMAL=y
> > +CONFIG_USB=y
> > +CONFIG_USB_XHCI_HCD=y
> > +CONFIG_USB_EHCI_HCD=y
> > +CONFIG_USB_HOST_ETHER=y
> > +CONFIG_USB_ETHER_ASIX=y
> > +CONFIG_USB_ETHER_ASIX88179=y
> > +CONFIG_USB_ETHER_MCS7830=y
> > +CONFIG_USB_ETHER_RTL8152=y
> > +CONFIG_USB_ETHER_SMSC95XX=y
> > diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h
> > new file mode 100644
> > index 0000000000..41bdfae6c3
> > --- /dev/null
> > +++ b/include/configs/mvebu_alleycat-5.h
> > @@ -0,0 +1,42 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (C) 2018 Marvell International Ltd
> > + */
> > +
> > +#ifndef _CONFIG_MVEBU_ALLEYCAY_5_H
> > +#define _CONFIG_MVEBU_ALLEYCAY_5_H
> > +
> > +#include <asm/arch/soc.h>
> > +
> > +/* additions for new ARM relocation support */
> > +#define CONFIG_SYS_SDRAM_BASE   0x200000000
> > +
> > +#define CONFIG_SYS_BAUDRATE_TABLE   { 9600, 19200, 38400, 57600, \
> > +                                   115200, 230400, 460800, 921600 }
> > +
> > +/* Default Env vars */
> > +#define CONFIG_IPADDR           0.0.0.0 /* In order to cause an error */
> > +#define CONFIG_SERVERIP         0.0.0.0 /* In order to cause an error */
> > +#define CONFIG_NETMASK          255.255.255.0
> > +#define CONFIG_GATEWAYIP        0.0.0.0
> > +#define CONFIG_ROOTPATH                 "/srv/nfs/" /* Default Dir for NFS */
> > +
> > +#define BOOT_TARGET_DEVICES(func) \
> > +     func(USB, usb, 0) \
> > +     func(DHCP, dhcp, na)
> > +
> > +#include <config_distro_bootcmd.h>
> > +
> > +#define CONFIG_EXTRA_ENV_SETTINGS   \
> > +     BOOTENV \
> > +     "kernel_addr_r=0x202000000\0" \
> > +     "fdt_addr_r=0x201000000\0"    \
> > +     "ramdisk_addr_r=0x206000000\0"    \
> > +     "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"
> > +
> > +/*
> > + * High Level Configuration Options (easy to change)
> > + */
> > +#define CONFIG_SYS_TCLK     325000000
> > +
> > +#endif /* _CONFIG_MVEBU_ALLEYCAY_5_H */
>
> Viele Grüße,
> Stefan Roese
>
> --
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de

Re: [PATCH v4 5/5] arm: mvebu: Add RD-AC5X board

[Chris Packham]

On Thu, Nov 3, 2022 at 9:29 AM Chris Packham <judge.packham@gmail.com> wrote:
>
> On Thu, Nov 3, 2022 at 2:40 AM Stefan Roese <sr@denx.de> wrote:
> >
> > Hi Chris,
> >
> > On 22.09.22 05:31, Chris Packham wrote:
> > > The RD-AC5X-32G16HVG6HLG-A0 development board main components and
> > > features include:
> > > * Main 12V/54V power supply
> > > * 270 Gbps throughput packet processor on the main board
> > > * DDR4:
> > >    * SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
> > >    * SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
> > >    * PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
> > > * 16GB eMMC (Samsung KLMAG1JETD-B041006)
> > > * 16MB SPI NOR(GD25Q127C)
> > > * 32 x 1000 Base-T interfaces
> > > * 16 x 2500 Base-T interfaces
> > >    * SR1: 88E2540*4
> > >    * SR2: 88E2580*1+88E2540*2
> > > * Six (6) x 25G Base-R SFP28 interfaces
> > > * One (1) x RJ-45 console connector, interfacing to the on board UART
> > > * One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
> > > * One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
> > > * One (1) x RJ-45 1G Base-T Management port, interfacing to the host
> > >    port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy
> > > * One (1) x Oculink port, interfacing to the PCIe port for external CPU
> > >    connection
> > > * POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~
> > >    Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881
> > >    solution)
> > > * POE total power budget 780W
> > > * LED interfaces per network port/POE
> > > * LED interfaces (common) showing system status
> > > * PTP TC mode Supported (Reserved M.2 connector to support BC mode)
> > >
> > > Signed-off-by: Chris Packham <judge.packham@gmail.com>
> > > ---
> > >
> > > Changes in v4:
> > > - Move CONFIG_DISPLAY_BOARDINFO_LATE and CONFIG_ENV_OVERWRITE to
> > >    the defconfig.
> > > - Remove CONFIG_BAUDRATE as this is already set in the default config
> > > - Remove CONFIG_USB_MAX_CONTROLLER_COUNT as this is not needed with
> > >    DM_USB
> > > - Remove CONFIG_PREBOOT as we don't have anything to run
> > > - Remove commented out CONFIG_BOARD_EARLY_INIT_R
> > > - Remove DEBUG_UART configuration
> > > - Remove unnecessary console environment variable
> > > - Remove CONFIG_MVEBU_SAR
> > >
> > > Changes in v3:
> > > - Remove MMC and UBIFS distroboot options (MMC driver is not currently
> > >    functional, NAND is not populated on the RD-AC5X board)
> > > - Remove unnecessary Ethernet configuration
> > > - Remove unnecessary NAND configuration
> > > - Remove memory node from dts so the value passed by the DDR FW will be
> > >    used
> > >
> > > Changes in v2:
> > > - Use distro boot by default
> > > - remove unnecessary SPI-NOR partitions
> > >
> > >   arch/arm/dts/Makefile                      |   3 +-
> > >   arch/arm/dts/ac5-98dx35xx-rd.dts           | 129 +++++++++++++++++++++
> > >   arch/arm/mach-mvebu/Kconfig                |   9 +-
> > >   board/Marvell/mvebu_alleycat-5/MAINTAINERS |   6 +
> > >   board/Marvell/mvebu_alleycat-5/Makefile    |   3 +
> > >   board/Marvell/mvebu_alleycat-5/board.c     |  28 +++++
> > >   configs/mvebu_ac5_rd_defconfig             |  84 ++++++++++++++
> > >   include/configs/mvebu_alleycat-5.h         |  42 +++++++
> > >   8 files changed, 302 insertions(+), 2 deletions(-)
> > >   create mode 100644 arch/arm/dts/ac5-98dx35xx-rd.dts
> > >   create mode 100644 board/Marvell/mvebu_alleycat-5/MAINTAINERS
> > >   create mode 100644 board/Marvell/mvebu_alleycat-5/Makefile
> > >   create mode 100644 board/Marvell/mvebu_alleycat-5/board.c
> > >   create mode 100644 configs/mvebu_ac5_rd_defconfig
> > >   create mode 100644 include/configs/mvebu_alleycat-5.h
> >
> > While running a CI build I run into these issues:
> >
> > CONFIG_SYS_TEXT_BASE is now renamed to CONFIG_TEXT_BASE. I've already
> > fixes this locally. But now I also get this compilation error:
> >
> > [stefan@ryzen u-boot-marvell (master)]$ make -sj
> >
> > Device Tree Source (arch/arm/dts/unset.dtb) is not correctly specified.
> > Please define 'CONFIG_DEFAULT_DEVICE_TREE'
> > or build with 'DEVICE_TREE=<device_tree>' argument
> >
> > make[1]: *** [dts/Makefile:34: arch/arm/dts/unset.dtb] Error 1
> > make: *** [Makefile:1162: dts/dt.dtb] Error 2
> >
> > So where is CONFIG_DEFAULT_DEVICE_TREE defined? I might have overlooked
> > this.
> >
>
> Ah. Because these arm64 SoCs need other components in the "bootloader"
> I've been using a meta build system that passes DEVICE_TREE= on the
> make command line. I'll rebase the series and add fixup
> CONFIG_TEXT_BASE/CONFIG_DEFAULT_DEVICE_TREE.
>

Darn, after rebasing I get

U-Boot 2022.10-01006-g566e5cb656-dirty (Nov 03 2022 - 00:19:33 +0000)

SoC: Alleycat5X 98DX3530M-A1
Clock:  CPU     1500 MHz
       DDR     1200 MHz
       FABRIC     0 MHz
       MSS      200 MHz
Model: Marvell RD-AC5X Board
DRAM:  2 GiB
Core:  25 devices, 16 uclasses, devicetree: separate
Could not initialize timer (err -19)

Could not initialize timer (err -19)

which I think is related to some recent changes requiring timer
configuration. I'm sure I can dig into the required change but has
anyone got any quick pointers of where to look?

> > Thanks,
> > Stefan
> >
> > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > > index 965895bc2a..57a5272884 100644
> > > --- a/arch/arm/dts/Makefile
> > > +++ b/arch/arm/dts/Makefile
> > > @@ -274,7 +274,8 @@ dtb-$(CONFIG_ARCH_MVEBU) +=                       \
> > >       cn9132-db-A.dtb                         \
> > >       cn9132-db-B.dtb                         \
> > >       cn9130-crb-A.dtb                        \
> > > -     cn9130-crb-B.dtb
> > > +     cn9130-crb-B.dtb                        \
> > > +     ac5-98dx35xx-rd.dtb
> > >   endif
> > >
> > >   dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
> > > diff --git a/arch/arm/dts/ac5-98dx35xx-rd.dts b/arch/arm/dts/ac5-98dx35xx-rd.dts
> > > new file mode 100644
> > > index 0000000000..d9f217cd4a
> > > --- /dev/null
> > > +++ b/arch/arm/dts/ac5-98dx35xx-rd.dts
> > > @@ -0,0 +1,129 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > +/*
> > > + * Device Tree For RD-AC5X.
> > > + *
> > > + * Copyright (C) 2021 Marvell
> > > + * Copyright (C) 2022 Allied Telesis Labs
> > > + */
> > > +/*
> > > + * Device Tree file for Marvell Alleycat 5X development board
> > > + * This board file supports the B configuration of the board
> > > + */
> > > +
> > > +/dts-v1/;
> > > +
> > > +#include "ac5-98dx35xx.dtsi"
> > > +
> > > +/ {
> > > +     model = "Marvell RD-AC5X Board";
> > > +     compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5";
> > > +
> > > +     aliases {
> > > +             serial0 = &uart0;
> > > +             spiflash0 = &spiflash0;
> > > +             gpio0 = &gpio0;
> > > +             gpio1 = &gpio1;
> > > +             ethernet0 = &eth0;
> > > +             ethernet1 = &eth1;
> > > +             spi0 = &spi0;
> > > +             i2c0 = &i2c0;
> > > +             i2c1 = &i2c1;
> > > +             usb0 = &usb0;
> > > +             usb1 = &usb1;
> > > +             pinctrl0 = &pinctrl0;
> > > +             sar-reg0 = "/config-space/sar-reg";
> > > +     };
> > > +
> > > +     usb1phy: usb-phy {
> > > +             compatible = "usb-nop-xceiv";
> > > +             #phy-cells = <0>;
> > > +     };
> > > +
> > > +     chosen {
> > > +             stdout-path = "serial0:115200n8";
> > > +     };
> > > +};
> > > +
> > > +&uart0 {
> > > +     status = "okay";
> > > +};
> > > +
> > > +&mdio {
> > > +     phy0: ethernet-phy@0 {
> > > +           reg = <0>;
> > > +     };
> > > +};
> > > +
> > > +&i2c0 {
> > > +     status = "okay";
> > > +};
> > > +
> > > +&i2c1 {
> > > +     status = "okay";
> > > +};
> > > +
> > > +&eth0 {
> > > +     status = "okay";
> > > +     phy-handle = <&phy0>;
> > > +};
> > > +
> > > +/* USB0 is a host USB */
> > > +&usb0 {
> > > +     status = "okay";
> > > +};
> > > +
> > > +/* USB1 is a peripheral USB */
> > > +&usb1 {
> > > +     status = "okay";
> > > +     phys = <&usb1phy>;
> > > +     phy-names = "usb-phy";
> > > +     dr_mode = "peripheral";
> > > +};
> > > +
> > > +&spi0 {
> > > +     status = "okay";
> > > +
> > > +     spiflash0: flash@0 {
> > > +             compatible = "jedec,spi-nor";
> > > +             spi-max-frequency = <50000000>;
> > > +             spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
> > > +             spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
> > > +             reg = <0>;
> > > +
> > > +             #address-cells = <1>;
> > > +             #size-cells = <1>;
> > > +     };
> > > +};
> > > +
> > > +&pinctrl0 {
> > > +     /*
> > > +      * MPP Bus:     MPP#     mode#
> > > +      * eMMC          [0-11]   0x1
> > > +      * SPI[0]        [12-17]  0x1
> > > +      * TSEN_INT      [18]     0x1
> > > +      * DEV_INIT      [19]     0x1
> > > +      * SPI[1]        [20-23]  0x3
> > > +      * UART[1]       [24-25]  0x3
> > > +      * I2C[0]        [26-27]  0x1
> > > +      * XSMI[0]       [28-29]  0x1 // SCH use SMI[0], reversed due to CPSS problem
> > > +      * SMI[1]        [30-31]  0x2 // SCH use XSMI[1], reversed due to CPSS problem
> > > +      * UART[0]       [32-33]  0x1
> > > +      * OOB_SMI       [34-35]  0x1
> > > +      * PTP_CLK0_OUT  [36]     0x1
> > > +      * PTP_PULSE_OUT [37]     0x1
> > > +      * RCVR_CLK_OUT  [38]     0x1
> > > +      * GPIO(in/out)  [39]     0x0
> > > +      * GPIO(in/out)  [40]     0x0
> > > +      * PTP_REF_CLK   [41]     0x1
> > > +      * PTP_CLK0      [42]     0x1
> > > +      * LED0_CLK      [43]     0x1
> > > +      * LED0_STB      [44]     0x1
> > > +      * LED0_DATA     [45]     0x1
> > > +      */
> > > +     /*           0    1    2    3    4    5    6    7    8    9 */
> > > +     pin-func = < 1    1    1    1    1    1    1    1    1    1
> > > +                  1    1    1    1    1    1    1    1    1    1
> > > +                  3    3    3    3    3    3    1    1    1    1
> > > +                  2    2    1    1    1    1    1    1    1    0
> > > +                  0    1    1    1    1    1    >;
> > > +};
> > > diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> > > index 45efa24194..2120cb473f 100644
> > > --- a/arch/arm/mach-mvebu/Kconfig
> > > +++ b/arch/arm/mach-mvebu/Kconfig
> > > @@ -97,7 +97,7 @@ config CUSTOMER_BOARD_SUPPORT
> > >       bool
> > >
> > >   choice
> > > -     prompt "Armada XP/375/38x/3700/7K/8K board select"
> > > +     prompt "Armada XP/375/38x/3700/7K/8K/Alleycat-5 board select"
> > >       optional
> > >
> > >   config TARGET_CLEARFOG
> > > @@ -149,6 +149,10 @@ config TARGET_MVEBU_ARMADA_8K
> > >       select BOARD_LATE_INIT
> > >       imply SCSI
> > >
> > > +config TARGET_MVEBU_ALLEYCAT5
> > > +     bool "Support AlleyCat 5 platforms"
> > > +     select ALLEYCAT_5
> > > +
> > >   config TARGET_OCTEONTX2_CN913x
> > >       bool "Support CN913x platforms"
> > >       select ARMADA_8K
> > > @@ -257,6 +261,7 @@ config SYS_BOARD
> > >       default "x530" if TARGET_X530
> > >       default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
> > >       default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
> > > +     default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
> > >
> > >   config SYS_CONFIG_NAME
> > >       default "clearfog" if TARGET_CLEARFOG
> > > @@ -277,6 +282,7 @@ config SYS_CONFIG_NAME
> > >       default "x530" if TARGET_X530
> > >       default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
> > >       default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
> > > +     default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
> > >
> > >   config SYS_VENDOR
> > >       default "Marvell" if TARGET_DB_MV784MP_GP
> > > @@ -296,6 +302,7 @@ config SYS_VENDOR
> > >       default "gdsys" if TARGET_CONTROLCENTERDC
> > >       default "alliedtelesis" if TARGET_X530
> > >       default "mikrotik" if TARGET_CRS3XX_98DX3236
> > > +     default "Marvell" if TARGET_MVEBU_ALLEYCAT5
> > >
> > >   config SYS_SOC
> > >       default "mvebu"
> > > diff --git a/board/Marvell/mvebu_alleycat-5/MAINTAINERS b/board/Marvell/mvebu_alleycat-5/MAINTAINERS
> > > new file mode 100644
> > > index 0000000000..480c07c5f0
> > > --- /dev/null
> > > +++ b/board/Marvell/mvebu_alleycat-5/MAINTAINERS
> > > @@ -0,0 +1,6 @@
> > > +RD-AC5X BOARD
> > > +M:   Chris Packham <chris.packham@alliedtelesis.co.nz>
> > > +S:   Maintained
> > > +F:   board/Marvell/mvebu_alleycat-5/
> > > +F:   include/configs/mvebu_alleycat-5.h
> > > +F:   configs/mvebu_ac5_rd_defconfig
> > > diff --git a/board/Marvell/mvebu_alleycat-5/Makefile b/board/Marvell/mvebu_alleycat-5/Makefile
> > > new file mode 100644
> > > index 0000000000..29254b4d64
> > > --- /dev/null
> > > +++ b/board/Marvell/mvebu_alleycat-5/Makefile
> > > @@ -0,0 +1,3 @@
> > > +# SPDX-License-Identifier:   GPL-2.0+
> > > +
> > > +obj-y        := board.o
> > > diff --git a/board/Marvell/mvebu_alleycat-5/board.c b/board/Marvell/mvebu_alleycat-5/board.c
> > > new file mode 100644
> > > index 0000000000..2d46775920
> > > --- /dev/null
> > > +++ b/board/Marvell/mvebu_alleycat-5/board.c
> > > @@ -0,0 +1,28 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +
> > > +#include <common.h>
> > > +#include <asm/global_data.h>
> > > +
> > > +DECLARE_GLOBAL_DATA_PTR;
> > > +
> > > +int board_early_init_f(void)
> > > +{
> > > +     return 0;
> > > +}
> > > +
> > > +int board_early_init_r(void)
> > > +{
> > > +     return 0;
> > > +}
> > > +
> > > +int board_init(void)
> > > +{
> > > +     gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> > > +
> > > +     return 0;
> > > +}
> > > +
> > > +int board_late_init(void)
> > > +{
> > > +     return 0;
> > > +}
> > > diff --git a/configs/mvebu_ac5_rd_defconfig b/configs/mvebu_ac5_rd_defconfig
> > > new file mode 100644
> > > index 0000000000..610d628705
> > > --- /dev/null
> > > +++ b/configs/mvebu_ac5_rd_defconfig
> > > @@ -0,0 +1,84 @@
> > > +CONFIG_ARM=y
> > > +CONFIG_ARCH_CPU_INIT=y
> > > +CONFIG_ARCH_MVEBU=y
> > > +CONFIG_SYS_TEXT_BASE=0x200000000
> > > +CONFIG_SYS_MALLOC_LEN=0x900000
> > > +CONFIG_TARGET_MVEBU_ALLEYCAT5=y
> > > +CONFIG_ENV_SIZE=0x10000
> > > +CONFIG_ENV_OFFSET=0x400000
> > > +CONFIG_ENV_SECT_SIZE=0x10000
> > > +CONFIG_DM_GPIO=y
> > > +CONFIG_SYS_LOAD_ADDR=0x202000000
> > > +CONFIG_SYS_MEMTEST_START=0x200800000
> > > +CONFIG_SYS_MEMTEST_END=0x200ffffff
> > > +CONFIG_DISTRO_DEFAULTS=y
> > > +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> > > +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x200FF0000
> > > +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> > > +CONFIG_FIT=y
> > > +CONFIG_BOOTDELAY=-1
> > > +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
> > > +CONFIG_SYS_CONSOLE_INFO_QUIET=y
> > > +CONFIG_DISPLAY_BOARDINFO_LATE=y
> > > +CONFIG_ARCH_EARLY_INIT_R=y
> > > +CONFIG_ARCH_MISC_INIT=y
> > > +CONFIG_BOARD_EARLY_INIT_F=y
> > > +CONFIG_CMD_BOOTZ=y
> > > +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
> > > +CONFIG_CMD_MEMTEST=y
> > > +# CONFIG_CMD_FLASH is not set
> > > +CONFIG_CMD_GPIO=y
> > > +CONFIG_CMD_I2C=y
> > > +CONFIG_CMD_MMC=y
> > > +CONFIG_CMD_PCI=y
> > > +CONFIG_CMD_SPI=y
> > > +CONFIG_CMD_USB=y
> > > +# CONFIG_CMD_SETEXPR is not set
> > > +CONFIG_CMD_CACHE=y
> > > +CONFIG_CMD_TIME=y
> > > +CONFIG_CMD_MVEBU_BUBT=y
> > > +CONFIG_CMD_REGULATOR=y
> > > +CONFIG_CMD_EXT4_WRITE=y
> > > +CONFIG_CMD_UBI=y
> > > +CONFIG_MAC_PARTITION=y
> > > +CONFIG_OF_EMBED=y
> > > +CONFIG_ENV_OVERWRITE=y
> > > +CONFIG_ENV_IS_IN_SPI_FLASH=y
> > > +CONFIG_CLK=y
> > > +CONFIG_CLK_MVEBU=y
> > > +CONFIG_DM_PCA953X=y
> > > +CONFIG_DM_I2C=y
> > > +CONFIG_SYS_I2C_MVTWSI=y
> > > +CONFIG_MISC=y
> > > +CONFIG_MMC_SDHCI=y
> > > +CONFIG_MMC_SDHCI_XENON=y
> > > +CONFIG_MTD=y
> > > +CONFIG_SPI_FLASH_GIGADEVICE=y
> > > +CONFIG_SPI_FLASH_MACRONIX=y
> > > +CONFIG_SPI_FLASH_SPANSION=y
> > > +CONFIG_SPI_FLASH_STMICRO=y
> > > +CONFIG_PHY_MARVELL=y
> > > +CONFIG_PHY_GIGE=y
> > > +CONFIG_E1000=y
> > > +CONFIG_MVNETA=y
> > > +CONFIG_MVMDIO=y
> > > +CONFIG_PCI=y
> > > +CONFIG_PHY=y
> > > +CONFIG_PINCTRL=y
> > > +CONFIG_PINCTRL_ARMADA_8K=y
> > > +CONFIG_DM_REGULATOR_FIXED=y
> > > +CONFIG_DM_REGULATOR_GPIO=y
> > > +CONFIG_DM_RTC=y
> > > +CONFIG_DM_SCSI=y
> > > +CONFIG_SYS_NS16550=y
> > > +CONFIG_MVEBU_A3700_SPI=y
> > > +CONFIG_DM_THERMAL=y
> > > +CONFIG_USB=y
> > > +CONFIG_USB_XHCI_HCD=y
> > > +CONFIG_USB_EHCI_HCD=y
> > > +CONFIG_USB_HOST_ETHER=y
> > > +CONFIG_USB_ETHER_ASIX=y
> > > +CONFIG_USB_ETHER_ASIX88179=y
> > > +CONFIG_USB_ETHER_MCS7830=y
> > > +CONFIG_USB_ETHER_RTL8152=y
> > > +CONFIG_USB_ETHER_SMSC95XX=y
> > > diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h
> > > new file mode 100644
> > > index 0000000000..41bdfae6c3
> > > --- /dev/null
> > > +++ b/include/configs/mvebu_alleycat-5.h
> > > @@ -0,0 +1,42 @@
> > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > +/*
> > > + * Copyright (C) 2018 Marvell International Ltd
> > > + */
> > > +
> > > +#ifndef _CONFIG_MVEBU_ALLEYCAY_5_H
> > > +#define _CONFIG_MVEBU_ALLEYCAY_5_H
> > > +
> > > +#include <asm/arch/soc.h>
> > > +
> > > +/* additions for new ARM relocation support */
> > > +#define CONFIG_SYS_SDRAM_BASE   0x200000000
> > > +
> > > +#define CONFIG_SYS_BAUDRATE_TABLE   { 9600, 19200, 38400, 57600, \
> > > +                                   115200, 230400, 460800, 921600 }
> > > +
> > > +/* Default Env vars */
> > > +#define CONFIG_IPADDR           0.0.0.0 /* In order to cause an error */
> > > +#define CONFIG_SERVERIP         0.0.0.0 /* In order to cause an error */
> > > +#define CONFIG_NETMASK          255.255.255.0
> > > +#define CONFIG_GATEWAYIP        0.0.0.0
> > > +#define CONFIG_ROOTPATH                 "/srv/nfs/" /* Default Dir for NFS */
> > > +
> > > +#define BOOT_TARGET_DEVICES(func) \
> > > +     func(USB, usb, 0) \
> > > +     func(DHCP, dhcp, na)
> > > +
> > > +#include <config_distro_bootcmd.h>
> > > +
> > > +#define CONFIG_EXTRA_ENV_SETTINGS   \
> > > +     BOOTENV \
> > > +     "kernel_addr_r=0x202000000\0" \
> > > +     "fdt_addr_r=0x201000000\0"    \
> > > +     "ramdisk_addr_r=0x206000000\0"    \
> > > +     "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"
> > > +
> > > +/*
> > > + * High Level Configuration Options (easy to change)
> > > + */
> > > +#define CONFIG_SYS_TCLK     325000000
> > > +
> > > +#endif /* _CONFIG_MVEBU_ALLEYCAY_5_H */
> >
> > Viele Grüße,
> > Stefan Roese
> >
> > --
> > DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> > Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de