* [Qemu-devel] [PATCH V2 0/4] target-arm: Initial ARMv8 extended EL support
@ 2015-01-23 16:17 Greg Bellows
2015-01-23 16:17 ` [Qemu-devel] [PATCH V2 1/4] target-arm: Fix RVBAR_EL1 register encoding Greg Bellows
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Greg Bellows @ 2015-01-23 16:17 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: Greg Bellows
These patches add extended EL support for ARMv8. Specifically the following
changes were made:
- Fix issue in RVBAR_EL1 CP register definition
- Add missing RVBAR_ELx CP register definitions
- Add missing SP_ELx CP register definitions
- Add reset support to start in highest EL
---
v1 -> v2
- Added case to allow secure EL1 Linux boot
- Added check for booting Linux into EL2 if enabled
- Removed extraneous SCR.NS setting on reset
- Fixed incorrect EL feature check
- Fixed incorrect RVBAR naming
- Reverted sp_el0_access function naming
Greg Bellows (4):
target-arm: Fix RVBAR_EL1 register encoding
target-arm: Add extended RVBAR support
target-arm: Change reset to highest available EL
target-arm: Add missing SP_ELx register definition
hw/arm/boot.c | 22 ++++++++++++++++++++--
target-arm/cpu.c | 9 ++++++++-
target-arm/helper.c | 39 +++++++++++++++++++++++++++++++++------
3 files changed, 61 insertions(+), 9 deletions(-)
--
1.8.3.2
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH V2 1/4] target-arm: Fix RVBAR_EL1 register encoding
2015-01-23 16:17 [Qemu-devel] [PATCH V2 0/4] target-arm: Initial ARMv8 extended EL support Greg Bellows
@ 2015-01-23 16:17 ` Greg Bellows
2015-01-23 16:25 ` Peter Maydell
2015-01-23 16:17 ` [Qemu-devel] [PATCH V2 2/4] target-arm: Add extended RVBAR support Greg Bellows
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Greg Bellows @ 2015-01-23 16:17 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: Greg Bellows
Fix the RVBAR_EL1 CP register opc2 encoding from 2 to 1
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 1a5e067..c9b1c08 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3055,7 +3055,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
};
ARMCPRegInfo rvbar = {
.name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2,
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
.type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
};
define_one_arm_cp_reg(cpu, &rvbar);
--
1.8.3.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH V2 2/4] target-arm: Add extended RVBAR support
2015-01-23 16:17 [Qemu-devel] [PATCH V2 0/4] target-arm: Initial ARMv8 extended EL support Greg Bellows
2015-01-23 16:17 ` [Qemu-devel] [PATCH V2 1/4] target-arm: Fix RVBAR_EL1 register encoding Greg Bellows
@ 2015-01-23 16:17 ` Greg Bellows
2015-01-23 16:17 ` [Qemu-devel] [PATCH V2 3/4] target-arm: Change reset to highest available EL Greg Bellows
` (2 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Greg Bellows @ 2015-01-23 16:17 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: Greg Bellows
Added RVBAR_EL2 and RVBAR_EL3 CP register support. All RVBAR_EL# registers
point to the same location and only the highest EL version exists at any one
time.
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/helper.c | 31 +++++++++++++++++++++++++------
1 file changed, 25 insertions(+), 6 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c9b1c08..29f3b62 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3053,17 +3053,30 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.resetvalue = cpu->mvfr2 },
REGINFO_SENTINEL
};
- ARMCPRegInfo rvbar = {
- .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
- .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
- };
- define_one_arm_cp_reg(cpu, &rvbar);
+ /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
+ if (!arm_feature(env, ARM_FEATURE_EL3) &&
+ !arm_feature(env, ARM_FEATURE_EL2)) {
+ ARMCPRegInfo rvbar = {
+ .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
+ .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
+ };
+ define_one_arm_cp_reg(cpu, &rvbar);
+ }
define_arm_cp_regs(cpu, v8_idregs);
define_arm_cp_regs(cpu, v8_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_EL2)) {
define_arm_cp_regs(cpu, v8_el2_cp_reginfo);
+ /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
+ if (!arm_feature(env, ARM_FEATURE_EL3)) {
+ ARMCPRegInfo rvbar = {
+ .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
+ .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
+ };
+ define_one_arm_cp_reg(cpu, &rvbar);
+ }
} else {
/* If EL2 is missing but higher ELs are enabled, we need to
* register the no_el2 reginfos.
@@ -3074,6 +3087,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
if (arm_feature(env, ARM_FEATURE_EL3)) {
define_arm_cp_regs(cpu, el3_cp_reginfo);
+ ARMCPRegInfo rvbar = {
+ .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
+ .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar
+ };
+ define_one_arm_cp_reg(cpu, &rvbar);
}
if (arm_feature(env, ARM_FEATURE_MPU)) {
/* These are the MPU registers prior to PMSAv6. Any new
--
1.8.3.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH V2 3/4] target-arm: Change reset to highest available EL
2015-01-23 16:17 [Qemu-devel] [PATCH V2 0/4] target-arm: Initial ARMv8 extended EL support Greg Bellows
2015-01-23 16:17 ` [Qemu-devel] [PATCH V2 1/4] target-arm: Fix RVBAR_EL1 register encoding Greg Bellows
2015-01-23 16:17 ` [Qemu-devel] [PATCH V2 2/4] target-arm: Add extended RVBAR support Greg Bellows
@ 2015-01-23 16:17 ` Greg Bellows
2015-01-23 16:24 ` Peter Maydell
2015-01-23 16:17 ` [Qemu-devel] [PATCH V2 4/4] target-arm: Add missing SP_ELx register definition Greg Bellows
2015-01-27 14:36 ` [Qemu-devel] [PATCH V2 0/4] target-arm: Initial ARMv8 extended EL support Sergey Fedorov
4 siblings, 1 reply; 11+ messages in thread
From: Greg Bellows @ 2015-01-23 16:17 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: Greg Bellows
Update to arm_cpu_reset() to reset into the highest available exception level
based on the set ARM features.
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
---
v1 -> v2
- Added Linux boot into secure EL1
- Added reset to EL2 if enabled
- Removed extraneous SCR.NS reset
- Fixed incorrect feature check
---
hw/arm/boot.c | 22 ++++++++++++++++++++--
target-arm/cpu.c | 9 ++++++++-
2 files changed, 28 insertions(+), 3 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 52ebd8b..a48d1b2 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -463,8 +463,26 @@ static void do_cpu_reset(void *opaque)
* (SCR.NS = 0), we change that here if non-secure boot has been
* requested.
*/
- if (arm_feature(env, ARM_FEATURE_EL3) && !info->secure_boot) {
- env->cp15.scr_el3 |= SCR_NS;
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
+ /* AArch64 is defined to come out of reset into EL3 if enabled.
+ * If we are booting Linux then we need to adjust our EL as
+ * Linux expects us to be in EL2 or EL1. AArch32 resets into
+ * SVC, which Linux expects, so no privilege/exception level to
+ * adjust.
+ */
+ if (env->aarch64) {
+ if (arm_feature(env, ARM_FEATURE_EL2)) {
+ env->pstate = PSTATE_MODE_EL2h;
+ } else {
+ env->pstate = PSTATE_MODE_EL1h;
+ }
+ }
+
+ /* Set to non-secure if not a secure boot */
+ if (!info->secure_boot) {
+ /* Linux expects non-secure state */
+ env->cp15.scr_el3 |= SCR_NS;
+ }
}
if (CPU(cpu) == first_cpu) {
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 285947f..f43e2de 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -113,7 +113,14 @@ static void arm_cpu_reset(CPUState *s)
/* and to the FP/Neon instructions */
env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
#else
- env->pstate = PSTATE_MODE_EL1h;
+ /* Reset into the highest available EL */
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
+ env->pstate = PSTATE_MODE_EL3h;
+ } else if (arm_feature(env, ARM_FEATURE_EL2)) {
+ env->pstate = PSTATE_MODE_EL2h;
+ } else {
+ env->pstate = PSTATE_MODE_EL1h;
+ }
env->pc = cpu->rvbar;
#endif
} else {
--
1.8.3.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH V2 4/4] target-arm: Add missing SP_ELx register definition
2015-01-23 16:17 [Qemu-devel] [PATCH V2 0/4] target-arm: Initial ARMv8 extended EL support Greg Bellows
` (2 preceding siblings ...)
2015-01-23 16:17 ` [Qemu-devel] [PATCH V2 3/4] target-arm: Change reset to highest available EL Greg Bellows
@ 2015-01-23 16:17 ` Greg Bellows
2015-01-27 19:03 ` Peter Maydell
2015-01-27 14:36 ` [Qemu-devel] [PATCH V2 0/4] target-arm: Initial ARMv8 extended EL support Sergey Fedorov
4 siblings, 1 reply; 11+ messages in thread
From: Greg Bellows @ 2015-01-23 16:17 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: Greg Bellows
Added CP register definitions for SP_EL1 and SP_EL2.
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
v1 -> v2
- Remove unnecessary accessfn for SP_EL1/2
- Revert SP_EL0 accessfn name to sp_el0_access
---
target-arm/helper.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 29f3b62..79c54a9 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2329,6 +2329,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.access = PL1_RW, .accessfn = sp_el0_access,
.type = ARM_CP_NO_MIGRATE,
.fieldoffset = offsetof(CPUARMState, sp_el[0]) },
+ { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
+ .access = PL2_RW, .type = ARM_CP_NO_MIGRATE,
+ .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
{ .name = "SPSel", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
.type = ARM_CP_NO_MIGRATE,
@@ -2410,6 +2414,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
.access = PL2_RW, .writefn = vbar_write,
.fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
.resetvalue = 0 },
+ { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
+ .access = PL3_RW, .type = ARM_CP_NO_MIGRATE,
+ .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
REGINFO_SENTINEL
};
--
1.8.3.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH V2 3/4] target-arm: Change reset to highest available EL
2015-01-23 16:17 ` [Qemu-devel] [PATCH V2 3/4] target-arm: Change reset to highest available EL Greg Bellows
@ 2015-01-23 16:24 ` Peter Maydell
0 siblings, 0 replies; 11+ messages in thread
From: Peter Maydell @ 2015-01-23 16:24 UTC (permalink / raw)
To: Greg Bellows; +Cc: QEMU Developers
On 23 January 2015 at 16:17, Greg Bellows <greg.bellows@linaro.org> wrote:
> Update to arm_cpu_reset() to reset into the highest available exception level
> based on the set ARM features.
>
> Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
>
> ---
>
> v1 -> v2
> - Added Linux boot into secure EL1
> - Added reset to EL2 if enabled
> - Removed extraneous SCR.NS reset
> - Fixed incorrect feature check
> ---
> hw/arm/boot.c | 22 ++++++++++++++++++++--
> target-arm/cpu.c | 9 ++++++++-
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH V2 1/4] target-arm: Fix RVBAR_EL1 register encoding
2015-01-23 16:17 ` [Qemu-devel] [PATCH V2 1/4] target-arm: Fix RVBAR_EL1 register encoding Greg Bellows
@ 2015-01-23 16:25 ` Peter Maydell
0 siblings, 0 replies; 11+ messages in thread
From: Peter Maydell @ 2015-01-23 16:25 UTC (permalink / raw)
To: Greg Bellows; +Cc: QEMU Developers
On 23 January 2015 at 16:17, Greg Bellows <greg.bellows@linaro.org> wrote:
> Fix the RVBAR_EL1 CP register opc2 encoding from 2 to 1
>
> Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
> ---
> target-arm/helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 1a5e067..c9b1c08 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -3055,7 +3055,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> };
> ARMCPRegInfo rvbar = {
> .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
> - .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2,
> + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
> .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
> };
> define_one_arm_cp_reg(cpu, &rvbar);
> --
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH V2 0/4] target-arm: Initial ARMv8 extended EL support
2015-01-23 16:17 [Qemu-devel] [PATCH V2 0/4] target-arm: Initial ARMv8 extended EL support Greg Bellows
` (3 preceding siblings ...)
2015-01-23 16:17 ` [Qemu-devel] [PATCH V2 4/4] target-arm: Add missing SP_ELx register definition Greg Bellows
@ 2015-01-27 14:36 ` Sergey Fedorov
2015-01-27 14:39 ` Greg Bellows
4 siblings, 1 reply; 11+ messages in thread
From: Sergey Fedorov @ 2015-01-27 14:36 UTC (permalink / raw)
To: Greg Bellows, qemu-devel, peter.maydell
On 23.01.2015 19:17, Greg Bellows wrote:
> These patches add extended EL support for ARMv8. Specifically the following
> changes were made:
>
> - Fix issue in RVBAR_EL1 CP register definition
> - Add missing RVBAR_ELx CP register definitions
> - Add missing SP_ELx CP register definitions
> - Add reset support to start in highest EL
>
> ---
>
> v1 -> v2
> - Added case to allow secure EL1 Linux boot
> - Added check for booting Linux into EL2 if enabled
> - Removed extraneous SCR.NS setting on reset
> - Fixed incorrect EL feature check
> - Fixed incorrect RVBAR naming
> - Reverted sp_el0_access function naming
>
> Greg Bellows (4):
> target-arm: Fix RVBAR_EL1 register encoding
> target-arm: Add extended RVBAR support
> target-arm: Change reset to highest available EL
> target-arm: Add missing SP_ELx register definition
>
> hw/arm/boot.c | 22 ++++++++++++++++++++--
> target-arm/cpu.c | 9 ++++++++-
> target-arm/helper.c | 39 +++++++++++++++++++++++++++++++++------
> 3 files changed, 61 insertions(+), 9 deletions(-)
>
> --
> 1.8.3.2
>
>
Hi!
Are we going to have AArch64 Virtualization support soon?
Thanks,
Sergey
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH V2 0/4] target-arm: Initial ARMv8 extended EL support
2015-01-27 14:36 ` [Qemu-devel] [PATCH V2 0/4] target-arm: Initial ARMv8 extended EL support Sergey Fedorov
@ 2015-01-27 14:39 ` Greg Bellows
0 siblings, 0 replies; 11+ messages in thread
From: Greg Bellows @ 2015-01-27 14:39 UTC (permalink / raw)
To: Sergey Fedorov, Edgar E. Iglesias; +Cc: Peter Maydell, QEMU Developers
[-- Attachment #1: Type: text/plain, Size: 1543 bytes --]
+Edgar
On Tue, Jan 27, 2015 at 8:36 AM, Sergey Fedorov <serge.fdrv@gmail.com>
wrote:
> On 23.01.2015 19:17, Greg Bellows wrote:
> > These patches add extended EL support for ARMv8. Specifically the
> following
> > changes were made:
> >
> > - Fix issue in RVBAR_EL1 CP register definition
> > - Add missing RVBAR_ELx CP register definitions
> > - Add missing SP_ELx CP register definitions
> > - Add reset support to start in highest EL
> >
> > ---
> >
> > v1 -> v2
> > - Added case to allow secure EL1 Linux boot
> > - Added check for booting Linux into EL2 if enabled
> > - Removed extraneous SCR.NS setting on reset
> > - Fixed incorrect EL feature check
> > - Fixed incorrect RVBAR naming
> > - Reverted sp_el0_access function naming
> >
> > Greg Bellows (4):
> > target-arm: Fix RVBAR_EL1 register encoding
> > target-arm: Add extended RVBAR support
> > target-arm: Change reset to highest available EL
> > target-arm: Add missing SP_ELx register definition
> >
> > hw/arm/boot.c | 22 ++++++++++++++++++++--
> > target-arm/cpu.c | 9 ++++++++-
> > target-arm/helper.c | 39 +++++++++++++++++++++++++++++++++------
> > 3 files changed, 61 insertions(+), 9 deletions(-)
> >
> > --
> > 1.8.3.2
> >
> >
>
> Hi!
>
> Are we going to have AArch64 Virtualization support soon?
>
> Thanks,
> Sergey
>
Hi Sergey,
I am only working on adding AArch64 EL3 support but I copied Edgar who I
believe is working on EL2 support. I don't know what his timeline is.
Greg
[-- Attachment #2: Type: text/html, Size: 2596 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH V2 4/4] target-arm: Add missing SP_ELx register definition
2015-01-23 16:17 ` [Qemu-devel] [PATCH V2 4/4] target-arm: Add missing SP_ELx register definition Greg Bellows
@ 2015-01-27 19:03 ` Peter Maydell
2015-01-27 19:07 ` Greg Bellows
0 siblings, 1 reply; 11+ messages in thread
From: Peter Maydell @ 2015-01-27 19:03 UTC (permalink / raw)
To: Greg Bellows; +Cc: QEMU Developers
On 23 January 2015 at 16:17, Greg Bellows <greg.bellows@linaro.org> wrote:
> Added CP register definitions for SP_EL1 and SP_EL2.
>
> Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>
> ---
>
> v1 -> v2
> - Remove unnecessary accessfn for SP_EL1/2
> - Revert SP_EL0 accessfn name to sp_el0_access
> ---
> target-arm/helper.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 29f3b62..79c54a9 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2329,6 +2329,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
> .access = PL1_RW, .accessfn = sp_el0_access,
> .type = ARM_CP_NO_MIGRATE,
> .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
> + { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
> + .access = PL2_RW, .type = ARM_CP_NO_MIGRATE,
> + .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
> { .name = "SPSel", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
> .type = ARM_CP_NO_MIGRATE,
> @@ -2410,6 +2414,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
> .access = PL2_RW, .writefn = vbar_write,
> .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
> .resetvalue = 0 },
> + { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
> + .access = PL3_RW, .type = ARM_CP_NO_MIGRATE,
> + .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
> REGINFO_SENTINEL
> };
As I was assembling my target-arm queue I found that this patch
and the 'split ARM_CP_NO_MIGRATE' patch semantically conflict;
since this patch happened to be earlier in the queue than that
one, I've resolved this by adding changes to the 'split' patch
which change these ARM_CP_NO_MIGRATE uses to ARM_CP_ALIAS, in
line with how we handled the SP_EL0 regdef.
thanks
-- PMM
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH V2 4/4] target-arm: Add missing SP_ELx register definition
2015-01-27 19:03 ` Peter Maydell
@ 2015-01-27 19:07 ` Greg Bellows
0 siblings, 0 replies; 11+ messages in thread
From: Greg Bellows @ 2015-01-27 19:07 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers
[-- Attachment #1: Type: text/plain, Size: 2300 bytes --]
On Tue, Jan 27, 2015 at 1:03 PM, Peter Maydell <peter.maydell@linaro.org>
wrote:
> On 23 January 2015 at 16:17, Greg Bellows <greg.bellows@linaro.org> wrote:
> > Added CP register definitions for SP_EL1 and SP_EL2.
> >
> > Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
> > Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> >
> > ---
> >
> > v1 -> v2
> > - Remove unnecessary accessfn for SP_EL1/2
> > - Revert SP_EL0 accessfn name to sp_el0_access
> > ---
> > target-arm/helper.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/target-arm/helper.c b/target-arm/helper.c
> > index 29f3b62..79c54a9 100644
> > --- a/target-arm/helper.c
> > +++ b/target-arm/helper.c
> > @@ -2329,6 +2329,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
> > .access = PL1_RW, .accessfn = sp_el0_access,
> > .type = ARM_CP_NO_MIGRATE,
> > .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
> > + { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
> > + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
> > + .access = PL2_RW, .type = ARM_CP_NO_MIGRATE,
> > + .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
> > { .name = "SPSel", .state = ARM_CP_STATE_AA64,
> > .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
> > .type = ARM_CP_NO_MIGRATE,
> > @@ -2410,6 +2414,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
> > .access = PL2_RW, .writefn = vbar_write,
> > .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
> > .resetvalue = 0 },
> > + { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
> > + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
> > + .access = PL3_RW, .type = ARM_CP_NO_MIGRATE,
> > + .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
> > REGINFO_SENTINEL
> > };
>
> As I was assembling my target-arm queue I found that this patch
> and the 'split ARM_CP_NO_MIGRATE' patch semantically conflict;
> since this patch happened to be earlier in the queue than that
> one, I've resolved this by adding changes to the 'split' patch
> which change these ARM_CP_NO_MIGRATE uses to ARM_CP_ALIAS, in
> line with how we handled the SP_EL0 regdef.
>
> thanks
> -- PMM
>
That makes sense.
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^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2015-01-27 19:07 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-01-23 16:17 [Qemu-devel] [PATCH V2 0/4] target-arm: Initial ARMv8 extended EL support Greg Bellows
2015-01-23 16:17 ` [Qemu-devel] [PATCH V2 1/4] target-arm: Fix RVBAR_EL1 register encoding Greg Bellows
2015-01-23 16:25 ` Peter Maydell
2015-01-23 16:17 ` [Qemu-devel] [PATCH V2 2/4] target-arm: Add extended RVBAR support Greg Bellows
2015-01-23 16:17 ` [Qemu-devel] [PATCH V2 3/4] target-arm: Change reset to highest available EL Greg Bellows
2015-01-23 16:24 ` Peter Maydell
2015-01-23 16:17 ` [Qemu-devel] [PATCH V2 4/4] target-arm: Add missing SP_ELx register definition Greg Bellows
2015-01-27 19:03 ` Peter Maydell
2015-01-27 19:07 ` Greg Bellows
2015-01-27 14:36 ` [Qemu-devel] [PATCH V2 0/4] target-arm: Initial ARMv8 extended EL support Sergey Fedorov
2015-01-27 14:39 ` Greg Bellows
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