[PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8

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* [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8
@ 2019-01-11 17:08 Ville Syrjala
  2019-01-11 17:08 ` [PATCH 01/13] drm/i915: Clean up intel_plane_atomic_check_with_state() Ville Syrjala
                   ` (15 more replies)
  0 siblings, 16 replies; 52+ messages in thread
From: Ville Syrjala @ 2019-01-11 17:08 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

I figured I'd post this before we get too deep in the rabbit hole with
the icl stuff. This is just the first part of my color mgmt stuff I've
had cooking for far too long. The rest has to do with expanding the
support for higher precision gamma modes and the pipe csc to all
possible platforms, but that part is not ready yet.

Entire series available here:
git://github.com/vsyrjala/linux.git gamma_mode_10_base

Ville Syrjälä (13):
  drm/i915: Clean up intel_plane_atomic_check_with_state()
  drm/i915: Split the gamma/csc enable bits from the plane_ctl()
    function
  drm/i915: Precompute gamma_mode
  drm/i915: Constify the state arguments to the color management stuff
  drm/i915: Pull GAMMA_MODE write out from haswell_load_luts()
  drm/i915: Split color mgmt based on single vs. double buffered
    registers
  drm/i915: Move LUT programming to happen after vblank waits
  drm/i915: Populate gamma_mode for all platforms
  drm/i915: Track pipe gamma enable/disable in crtc state
  drm/i915: Track pipe csc enable in crtc state
  drm/i915: Turn off pipe gamma when it's not needed.
  drm/i915: Turn off pipe CSC when it's not needed
  drm/i915: Disable pipe gamma when C8 pixel format is used

 drivers/gpu/drm/i915/i915_drv.h           |   4 +-
 drivers/gpu/drm/i915/i915_reg.h           |  22 +-
 drivers/gpu/drm/i915/intel_atomic_plane.c |  41 +--
 drivers/gpu/drm/i915/intel_color.c        | 386 ++++++++++++++--------
 drivers/gpu/drm/i915/intel_display.c      | 257 +++++++++++---
 drivers/gpu/drm/i915/intel_drv.h          |  14 +-
 drivers/gpu/drm/i915/intel_sprite.c       |  67 +++-
 7 files changed, 563 insertions(+), 228 deletions(-)

-- 
2.19.2

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* [PATCH 01/13] drm/i915: Clean up intel_plane_atomic_check_with_state()
  2019-01-11 17:08 [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8 Ville Syrjala
@ 2019-01-11 17:08 ` Ville Syrjala
  2019-01-12  0:41   ` Matt Roper
  2019-01-16 16:08   ` Shankar, Uma
  2019-01-11 17:08 ` [PATCH 02/13] drm/i915: Split the gamma/csc enable bits from the plane_ctl() function Ville Syrjala
                   ` (14 subsequent siblings)
  15 siblings, 2 replies; 52+ messages in thread
From: Ville Syrjala @ 2019-01-11 17:08 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rename some of the state variables in
intel_plane_atomic_check_with_state() to make it less confusing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_atomic_plane.c | 36 +++++++++++------------
 1 file changed, 17 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 683a75dad4fb..50be2c5dd76e 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -110,41 +110,39 @@ intel_plane_destroy_state(struct drm_plane *plane,
 }
 
 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
-					struct intel_crtc_state *crtc_state,
+					struct intel_crtc_state *new_crtc_state,
 					const struct intel_plane_state *old_plane_state,
-					struct intel_plane_state *intel_state)
+					struct intel_plane_state *new_plane_state)
 {
-	struct drm_plane *plane = intel_state->base.plane;
-	struct drm_plane_state *state = &intel_state->base;
-	struct intel_plane *intel_plane = to_intel_plane(plane);
+	struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
 	int ret;
 
-	crtc_state->active_planes &= ~BIT(intel_plane->id);
-	crtc_state->nv12_planes &= ~BIT(intel_plane->id);
-	intel_state->base.visible = false;
+	new_crtc_state->active_planes &= ~BIT(plane->id);
+	new_crtc_state->nv12_planes &= ~BIT(plane->id);
+	new_plane_state->base.visible = false;
 
-	/* If this is a cursor plane, no further checks are needed. */
-	if (!intel_state->base.crtc && !old_plane_state->base.crtc)
+	if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
 		return 0;
 
-	ret = intel_plane->check_plane(crtc_state, intel_state);
+	ret = plane->check_plane(new_crtc_state, new_plane_state);
 	if (ret)
 		return ret;
 
 	/* FIXME pre-g4x don't work like this */
-	if (state->visible)
-		crtc_state->active_planes |= BIT(intel_plane->id);
+	if (new_plane_state->base.visible)
+		new_crtc_state->active_planes |= BIT(plane->id);
 
-	if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
-		crtc_state->nv12_planes |= BIT(intel_plane->id);
+	if (new_plane_state->base.visible &&
+	    new_plane_state->base.fb->format->format == DRM_FORMAT_NV12)
+		new_crtc_state->nv12_planes |= BIT(plane->id);
 
-	if (state->visible || old_plane_state->base.visible)
-		crtc_state->update_planes |= BIT(intel_plane->id);
+	if (new_plane_state->base.visible || old_plane_state->base.visible)
+		new_crtc_state->update_planes |= BIT(plane->id);
 
 	return intel_plane_atomic_calc_changes(old_crtc_state,
-					       &crtc_state->base,
+					       &new_crtc_state->base,
 					       old_plane_state,
-					       state);
+					       &new_plane_state->base);
 }
 
 static int intel_plane_atomic_check(struct drm_plane *plane,
-- 
2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 52+ messages in thread

* Re: [PATCH 01/13] drm/i915: Clean up intel_plane_atomic_check_with_state()
  2019-01-11 17:08 ` [PATCH 01/13] drm/i915: Clean up intel_plane_atomic_check_with_state() Ville Syrjala
@ 2019-01-12  0:41   ` Matt Roper
  2019-01-16 16:08   ` Shankar, Uma
  1 sibling, 0 replies; 52+ messages in thread
From: Matt Roper @ 2019-01-12  0:41 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Jan 11, 2019 at 07:08:11PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Rename some of the state variables in
> intel_plane_atomic_check_with_state() to make it less confusing.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_atomic_plane.c | 36 +++++++++++------------
>  1 file changed, 17 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 683a75dad4fb..50be2c5dd76e 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -110,41 +110,39 @@ intel_plane_destroy_state(struct drm_plane *plane,
>  }
>  
>  int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
> -					struct intel_crtc_state *crtc_state,
> +					struct intel_crtc_state *new_crtc_state,
>  					const struct intel_plane_state *old_plane_state,
> -					struct intel_plane_state *intel_state)
> +					struct intel_plane_state *new_plane_state)
>  {
> -	struct drm_plane *plane = intel_state->base.plane;
> -	struct drm_plane_state *state = &intel_state->base;
> -	struct intel_plane *intel_plane = to_intel_plane(plane);
> +	struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
>  	int ret;
>  
> -	crtc_state->active_planes &= ~BIT(intel_plane->id);
> -	crtc_state->nv12_planes &= ~BIT(intel_plane->id);
> -	intel_state->base.visible = false;
> +	new_crtc_state->active_planes &= ~BIT(plane->id);
> +	new_crtc_state->nv12_planes &= ~BIT(plane->id);
> +	new_plane_state->base.visible = false;
>  
> -	/* If this is a cursor plane, no further checks are needed. */
> -	if (!intel_state->base.crtc && !old_plane_state->base.crtc)
> +	if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
>  		return 0;
>  
> -	ret = intel_plane->check_plane(crtc_state, intel_state);
> +	ret = plane->check_plane(new_crtc_state, new_plane_state);
>  	if (ret)
>  		return ret;
>  
>  	/* FIXME pre-g4x don't work like this */
> -	if (state->visible)
> -		crtc_state->active_planes |= BIT(intel_plane->id);
> +	if (new_plane_state->base.visible)
> +		new_crtc_state->active_planes |= BIT(plane->id);
>  
> -	if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
> -		crtc_state->nv12_planes |= BIT(intel_plane->id);
> +	if (new_plane_state->base.visible &&
> +	    new_plane_state->base.fb->format->format == DRM_FORMAT_NV12)
> +		new_crtc_state->nv12_planes |= BIT(plane->id);
>  
> -	if (state->visible || old_plane_state->base.visible)
> -		crtc_state->update_planes |= BIT(intel_plane->id);
> +	if (new_plane_state->base.visible || old_plane_state->base.visible)
> +		new_crtc_state->update_planes |= BIT(plane->id);
>  
>  	return intel_plane_atomic_calc_changes(old_crtc_state,
> -					       &crtc_state->base,
> +					       &new_crtc_state->base,
>  					       old_plane_state,
> -					       state);
> +					       &new_plane_state->base);
>  }
>  
>  static int intel_plane_atomic_check(struct drm_plane *plane,
> -- 
> 2.19.2
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 01/13] drm/i915: Clean up intel_plane_atomic_check_with_state()
  2019-01-11 17:08 ` [PATCH 01/13] drm/i915: Clean up intel_plane_atomic_check_with_state() Ville Syrjala
  2019-01-12  0:41   ` Matt Roper
@ 2019-01-16 16:08   ` Shankar, Uma
  1 sibling, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-01-16 16:08 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx



>-----Original Message-----
>From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
>Sent: Friday, January 11, 2019 10:38 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma <uma.shankar@intel.com>; Roper, Matthew D
><matthew.d.roper@intel.com>
>Subject: [PATCH 01/13] drm/i915: Clean up
>intel_plane_atomic_check_with_state()
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Rename some of the state variables in
>intel_plane_atomic_check_with_state() to make it less confusing.

Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/intel_atomic_plane.c | 36 +++++++++++------------
> 1 file changed, 17 insertions(+), 19 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
>b/drivers/gpu/drm/i915/intel_atomic_plane.c
>index 683a75dad4fb..50be2c5dd76e 100644
>--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
>+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
>@@ -110,41 +110,39 @@ intel_plane_destroy_state(struct drm_plane *plane,  }
>
> int intel_plane_atomic_check_with_state(const struct intel_crtc_state
>*old_crtc_state,
>-					struct intel_crtc_state *crtc_state,
>+					struct intel_crtc_state *new_crtc_state,
> 					const struct intel_plane_state
>*old_plane_state,
>-					struct intel_plane_state *intel_state)
>+					struct intel_plane_state
>*new_plane_state)
> {
>-	struct drm_plane *plane = intel_state->base.plane;
>-	struct drm_plane_state *state = &intel_state->base;
>-	struct intel_plane *intel_plane = to_intel_plane(plane);
>+	struct intel_plane *plane =
>+to_intel_plane(new_plane_state->base.plane);
> 	int ret;
>
>-	crtc_state->active_planes &= ~BIT(intel_plane->id);
>-	crtc_state->nv12_planes &= ~BIT(intel_plane->id);
>-	intel_state->base.visible = false;
>+	new_crtc_state->active_planes &= ~BIT(plane->id);
>+	new_crtc_state->nv12_planes &= ~BIT(plane->id);
>+	new_plane_state->base.visible = false;
>
>-	/* If this is a cursor plane, no further checks are needed. */
>-	if (!intel_state->base.crtc && !old_plane_state->base.crtc)
>+	if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
> 		return 0;
>
>-	ret = intel_plane->check_plane(crtc_state, intel_state);
>+	ret = plane->check_plane(new_crtc_state, new_plane_state);
> 	if (ret)
> 		return ret;
>
> 	/* FIXME pre-g4x don't work like this */
>-	if (state->visible)
>-		crtc_state->active_planes |= BIT(intel_plane->id);
>+	if (new_plane_state->base.visible)
>+		new_crtc_state->active_planes |= BIT(plane->id);
>
>-	if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
>-		crtc_state->nv12_planes |= BIT(intel_plane->id);
>+	if (new_plane_state->base.visible &&
>+	    new_plane_state->base.fb->format->format == DRM_FORMAT_NV12)
>+		new_crtc_state->nv12_planes |= BIT(plane->id);
>
>-	if (state->visible || old_plane_state->base.visible)
>-		crtc_state->update_planes |= BIT(intel_plane->id);
>+	if (new_plane_state->base.visible || old_plane_state->base.visible)
>+		new_crtc_state->update_planes |= BIT(plane->id);
>
> 	return intel_plane_atomic_calc_changes(old_crtc_state,
>-					       &crtc_state->base,
>+					       &new_crtc_state->base,
> 					       old_plane_state,
>-					       state);
>+					       &new_plane_state->base);
> }
>
> static int intel_plane_atomic_check(struct drm_plane *plane,
>--
>2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* [PATCH 02/13] drm/i915: Split the gamma/csc enable bits from the plane_ctl() function
  2019-01-11 17:08 [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8 Ville Syrjala
  2019-01-11 17:08 ` [PATCH 01/13] drm/i915: Clean up intel_plane_atomic_check_with_state() Ville Syrjala
@ 2019-01-11 17:08 ` Ville Syrjala
  2019-01-12  0:41   ` Matt Roper
  2019-01-11 17:08 ` [PATCH 03/13] drm/i915: Precompute gamma_mode Ville Syrjala
                   ` (13 subsequent siblings)
  15 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjala @ 2019-01-11 17:08 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On g4x+ the pipe gamma enable bit for the primary plane affects
the pipe bottom color as well. The same for the pipe csc enable
bit on ilk+. Thus we must configure those bits correctly even
when the primary plane is disabled.

To make the feasible let's split those settings from the
plane_ctl() function into a seprate funciton that we can
call from the ->disable_plane() hook as well.

For consistency we'll do that on all the plane types. While
that has no real benefits at this time, it'll become useful
when we start to control the pipe gamma/csc enable bits
dynamically when we overhaul the color management code.

On pre-g4x there doesn't appear to be any way to gamma
correct the pipe bottom color, but sticking to the same
pattern doesn't hurt. And it'll still help us to do
crtc state readout correctly for the pipe gamma enable
bit for the color management overhaul.

An alternative apporach would be to still precompute these
bits into plane_state->ctl, but that would require that we
run through the plane check even when the plane isn't logically
enabled on any crtc. Currently that condition causes us to
short circuit the entire thing and not call ->check_plane().
There would also be some chicken and egg problems with
->check_plane() vs. crtc color state check that would
requite splitting certain things into multiple steps.
So all in all this seems like the easier route.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 128 ++++++++++++++++++++-------
 drivers/gpu/drm/i915/intel_drv.h     |   3 +-
 drivers/gpu/drm/i915/intel_sprite.c  |  54 ++++++++---
 3 files changed, 139 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5dc0de89c49e..a3871db4703b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3180,28 +3180,38 @@ i9xx_plane_max_stride(struct intel_plane *plane,
 	}
 }
 
+static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	u32 dspcntr = 0;
+
+	dspcntr |= DISPPLANE_GAMMA_ENABLE;
+
+	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
+
+	if (INTEL_GEN(dev_priv) < 5)
+		dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
+
+	return dspcntr;
+}
+
 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
 			  const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv =
 		to_i915(plane_state->base.plane->dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	const struct drm_framebuffer *fb = plane_state->base.fb;
 	unsigned int rotation = plane_state->base.rotation;
 	u32 dspcntr;
 
-	dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
+	dspcntr = DISPLAY_PLANE_ENABLE;
 
 	if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
 	    IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
 		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
 
-	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
-		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
-
-	if (INTEL_GEN(dev_priv) < 5)
-		dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
-
 	switch (fb->format->format) {
 	case DRM_FORMAT_C8:
 		dspcntr |= DISPPLANE_8BPP;
@@ -3329,11 +3339,13 @@ static void i9xx_update_plane(struct intel_plane *plane,
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
 	u32 linear_offset;
-	u32 dspcntr = plane_state->ctl;
 	int x = plane_state->color_plane[0].x;
 	int y = plane_state->color_plane[0].y;
 	unsigned long irqflags;
 	u32 dspaddr_offset;
+	u32 dspcntr;
+
+	dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
 
 	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
@@ -3393,10 +3405,23 @@ static void i9xx_disable_plane(struct intel_plane *plane,
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
 	unsigned long irqflags;
+	u32 dspcntr;
+
+	/*
+	 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
+	 * enable on ilk+ affect the pipe bottom color as
+	 * well, so we must configure them even if the plane
+	 * is disabled.
+	 *
+	 * On pre-g4x there is no way to gamma correct the
+	 * pipe bottom color but we'll keep on doing this
+	 * anyway.
+	 */
+	dspcntr = i9xx_plane_ctl_crtc(crtc_state);
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
-	I915_WRITE_FW(DSPCNTR(i9xx_plane), 0);
+	I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
 	if (INTEL_GEN(dev_priv) >= 4)
 		I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
 	else
@@ -3631,6 +3656,20 @@ static u32 cnl_plane_ctl_flip(unsigned int reflect)
 	return 0;
 }
 
+u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	u32 plane_ctl = 0;
+
+	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+		return plane_ctl;
+
+	plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
+	plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
+
+	return plane_ctl;
+}
+
 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 		  const struct intel_plane_state *plane_state)
 {
@@ -3645,10 +3684,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 
 	if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
 		plane_ctl |= skl_plane_ctl_alpha(plane_state);
-		plane_ctl |=
-			PLANE_CTL_PIPE_GAMMA_ENABLE |
-			PLANE_CTL_PIPE_CSC_ENABLE |
-			PLANE_CTL_PLANE_GAMMA_DISABLE;
+		plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
 
 		if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 			plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
@@ -3673,19 +3709,27 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 	return plane_ctl;
 }
 
+u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	u32 plane_color_ctl = 0;
+
+	if (INTEL_GEN(dev_priv) >= 11)
+		return plane_color_ctl;
+
+	plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
+	plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
+
+	return plane_color_ctl;
+}
+
 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 			const struct intel_plane_state *plane_state)
 {
-	struct drm_i915_private *dev_priv =
-		to_i915(plane_state->base.plane->dev);
 	const struct drm_framebuffer *fb = plane_state->base.fb;
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	u32 plane_color_ctl = 0;
 
-	if (INTEL_GEN(dev_priv) < 11) {
-		plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
-		plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
-	}
 	plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
 	plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
 
@@ -9867,11 +9911,15 @@ i845_cursor_max_stride(struct intel_plane *plane,
 	return 2048;
 }
 
+static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
+{
+	return CURSOR_GAMMA_ENABLE;
+}
+
 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
 			   const struct intel_plane_state *plane_state)
 {
 	return CURSOR_ENABLE |
-		CURSOR_GAMMA_ENABLE |
 		CURSOR_FORMAT_ARGB |
 		CURSOR_STRIDE(plane_state->color_plane[0].stride);
 }
@@ -9941,7 +9989,9 @@ static void i845_update_cursor(struct intel_plane *plane,
 		unsigned int width = plane_state->base.crtc_w;
 		unsigned int height = plane_state->base.crtc_h;
 
-		cntl = plane_state->ctl;
+		cntl = plane_state->ctl |
+			i845_cursor_ctl_crtc(crtc_state);
+
 		size = (height << 12) | width;
 
 		base = intel_cursor_base(plane_state);
@@ -10006,27 +10056,36 @@ i9xx_cursor_max_stride(struct intel_plane *plane,
 	return plane->base.dev->mode_config.cursor_width * 4;
 }
 
-static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
-			   const struct intel_plane_state *plane_state)
+static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv =
-		to_i915(plane_state->base.plane->dev);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 cntl = 0;
 
-	if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
-		cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
+	if (INTEL_GEN(dev_priv) >= 11)
+		return cntl;
 
-	if (INTEL_GEN(dev_priv) <= 10) {
-		cntl |= MCURSOR_GAMMA_ENABLE;
+	cntl |= MCURSOR_GAMMA_ENABLE;
 
-		if (HAS_DDI(dev_priv))
-			cntl |= MCURSOR_PIPE_CSC_ENABLE;
-	}
+	if (HAS_DDI(dev_priv))
+		cntl |= MCURSOR_PIPE_CSC_ENABLE;
 
 	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
 		cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
 
+	return cntl;
+}
+
+static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
+			   const struct intel_plane_state *plane_state)
+{
+	struct drm_i915_private *dev_priv =
+		to_i915(plane_state->base.plane->dev);
+	u32 cntl = 0;
+
+	if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
+		cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
+
 	switch (plane_state->base.crtc_w) {
 	case 64:
 		cntl |= MCURSOR_MODE_64_ARGB_AX;
@@ -10151,7 +10210,8 @@ static void i9xx_update_cursor(struct intel_plane *plane,
 	unsigned long irqflags;
 
 	if (plane_state && plane_state->base.visible) {
-		cntl = plane_state->ctl;
+		cntl = plane_state->ctl |
+			i9xx_cursor_ctl_crtc(crtc_state);
 
 		if (plane_state->base.crtc_h != plane_state->base.crtc_w)
 			fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3b051fdd0fce..88ac42b2d7ed 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1752,9 +1752,10 @@ static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
 
 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 			const struct intel_plane_state *plane_state);
+u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 		  const struct intel_plane_state *plane_state);
-u32 glk_color_ctl(const struct intel_plane_state *plane_state);
+u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
 		     int plane);
 int skl_check_plane_surface(struct intel_plane_state *plane_state);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 8f3982c03925..a45ef98b2f8d 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -484,9 +484,16 @@ skl_program_plane(struct intel_plane *plane,
 	struct intel_plane *linked = plane_state->linked_plane;
 	const struct drm_framebuffer *fb = plane_state->base.fb;
 	u8 alpha = plane_state->base.alpha >> 8;
+	u32 plane_color_ctl = 0;
 	unsigned long irqflags;
 	u32 keymsk, keymax;
 
+	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
+
+	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+		plane_color_ctl = plane_state->color_ctl |
+			glk_plane_color_ctl_crtc(crtc_state);
+
 	/* Sizes are 0 based */
 	src_w--;
 	src_h--;
@@ -533,8 +540,7 @@ skl_program_plane(struct intel_plane *plane,
 	}
 
 	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
-		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
-			      plane_state->color_ctl);
+		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
 
 	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
 		icl_program_input_csc(plane, crtc_state, plane_state);
@@ -731,6 +737,11 @@ vlv_update_clrc(const struct intel_plane_state *plane_state)
 		      SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
 }
 
+static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
+{
+	return SP_GAMMA_ENABLE;
+}
+
 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
 			  const struct intel_plane_state *plane_state)
 {
@@ -739,7 +750,7 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 	u32 sprctl;
 
-	sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
+	sprctl = SP_ENABLE;
 
 	switch (fb->format->format) {
 	case DRM_FORMAT_YUYV:
@@ -806,7 +817,6 @@ vlv_update_plane(struct intel_plane *plane,
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum pipe pipe = plane->pipe;
 	enum plane_id plane_id = plane->id;
-	u32 sprctl = plane_state->ctl;
 	u32 sprsurf_offset = plane_state->color_plane[0].offset;
 	u32 linear_offset;
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
@@ -817,6 +827,9 @@ vlv_update_plane(struct intel_plane *plane,
 	uint32_t x = plane_state->color_plane[0].x;
 	uint32_t y = plane_state->color_plane[0].y;
 	unsigned long irqflags;
+	u32 sprctl;
+
+	sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);
 
 	/* Sizes are 0 based */
 	crtc_w--;
@@ -897,6 +910,19 @@ vlv_plane_get_hw_state(struct intel_plane *plane,
 	return ret;
 }
 
+static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	u32 sprctl = 0;
+
+	sprctl |= SPRITE_GAMMA_ENABLE;
+
+	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+		sprctl |= SPRITE_PIPE_CSC_ENABLE;
+
+	return sprctl;
+}
+
 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
 			  const struct intel_plane_state *plane_state)
 {
@@ -907,14 +933,11 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 	u32 sprctl;
 
-	sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
+	sprctl = SPRITE_ENABLE;
 
 	if (IS_IVYBRIDGE(dev_priv))
 		sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 
-	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
-		sprctl |= SPRITE_PIPE_CSC_ENABLE;
-
 	switch (fb->format->format) {
 	case DRM_FORMAT_XBGR8888:
 		sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
@@ -966,7 +989,6 @@ ivb_update_plane(struct intel_plane *plane,
 {
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum pipe pipe = plane->pipe;
-	u32 sprctl = plane_state->ctl, sprscale = 0;
 	u32 sprsurf_offset = plane_state->color_plane[0].offset;
 	u32 linear_offset;
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
@@ -978,8 +1000,11 @@ ivb_update_plane(struct intel_plane *plane,
 	uint32_t y = plane_state->color_plane[0].y;
 	uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 	uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
+	u32 sprctl, sprscale = 0;
 	unsigned long irqflags;
 
+	sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);
+
 	/* Sizes are 0 based */
 	src_w--;
 	src_h--;
@@ -1074,6 +1099,11 @@ g4x_sprite_max_stride(struct intel_plane *plane,
 	return 16384;
 }
 
+static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
+{
+	return DVS_GAMMA_ENABLE;
+}
+
 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
 			  const struct intel_plane_state *plane_state)
 {
@@ -1084,7 +1114,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 	u32 dvscntr;
 
-	dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
+	dvscntr = DVS_ENABLE;
 
 	if (IS_GEN(dev_priv, 6))
 		dvscntr |= DVS_TRICKLE_FEED_DISABLE;
@@ -1140,7 +1170,6 @@ g4x_update_plane(struct intel_plane *plane,
 {
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum pipe pipe = plane->pipe;
-	u32 dvscntr = plane_state->ctl, dvsscale = 0;
 	u32 dvssurf_offset = plane_state->color_plane[0].offset;
 	u32 linear_offset;
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
@@ -1152,8 +1181,11 @@ g4x_update_plane(struct intel_plane *plane,
 	uint32_t y = plane_state->color_plane[0].y;
 	uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 	uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
+	u32 dvscntr, dvsscale = 0;
 	unsigned long irqflags;
 
+	dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);
+
 	/* Sizes are 0 based */
 	src_w--;
 	src_h--;
-- 
2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 52+ messages in thread

* Re: [PATCH 02/13] drm/i915: Split the gamma/csc enable bits from the plane_ctl() function
  2019-01-11 17:08 ` [PATCH 02/13] drm/i915: Split the gamma/csc enable bits from the plane_ctl() function Ville Syrjala
@ 2019-01-12  0:41   ` Matt Roper
  2019-01-14 17:11     ` Ville Syrjälä
  0 siblings, 1 reply; 52+ messages in thread
From: Matt Roper @ 2019-01-12  0:41 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Jan 11, 2019 at 07:08:12PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On g4x+ the pipe gamma enable bit for the primary plane affects
> the pipe bottom color as well. The same for the pipe csc enable
> bit on ilk+. Thus we must configure those bits correctly even
> when the primary plane is disabled.

This is only true for <gen9, right?  Starting with gen9, we have
dedicated bits that control this, so I don't think the primay plane's
settings should have any impact when disabled.  I.e., we also need the
bits set in this patch:

        https://patchwork.freedesktop.org/patch/271109/

> To make the feasible let's split those settings from the
> plane_ctl() function into a seprate funciton that we can
> call from the ->disable_plane() hook as well.

Is calling it from ->disable_plane() enough?  If we just disable the
primary plane, then those bits will remain set while the crtc remains
active.  But if you then disable the whole crtc and re-enable it again
later, won't we have lost the bits at that point?


Matt

> 
> For consistency we'll do that on all the plane types. While
> that has no real benefits at this time, it'll become useful
> when we start to control the pipe gamma/csc enable bits
> dynamically when we overhaul the color management code.
> 
> On pre-g4x there doesn't appear to be any way to gamma
> correct the pipe bottom color, but sticking to the same
> pattern doesn't hurt. And it'll still help us to do
> crtc state readout correctly for the pipe gamma enable
> bit for the color management overhaul.
> 
> An alternative apporach would be to still precompute these
> bits into plane_state->ctl, but that would require that we
> run through the plane check even when the plane isn't logically
> enabled on any crtc. Currently that condition causes us to
> short circuit the entire thing and not call ->check_plane().
> There would also be some chicken and egg problems with
> ->check_plane() vs. crtc color state check that would
> requite splitting certain things into multiple steps.
> So all in all this seems like the easier route.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 128 ++++++++++++++++++++-------
>  drivers/gpu/drm/i915/intel_drv.h     |   3 +-
>  drivers/gpu/drm/i915/intel_sprite.c  |  54 ++++++++---
>  3 files changed, 139 insertions(+), 46 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5dc0de89c49e..a3871db4703b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3180,28 +3180,38 @@ i9xx_plane_max_stride(struct intel_plane *plane,
>  	}
>  }
>  
> +static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	u32 dspcntr = 0;
> +
> +	dspcntr |= DISPPLANE_GAMMA_ENABLE;
> +
> +	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> +		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> +
> +	if (INTEL_GEN(dev_priv) < 5)
> +		dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
> +
> +	return dspcntr;
> +}
> +
>  static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
>  			  const struct intel_plane_state *plane_state)
>  {
>  	struct drm_i915_private *dev_priv =
>  		to_i915(plane_state->base.plane->dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	const struct drm_framebuffer *fb = plane_state->base.fb;
>  	unsigned int rotation = plane_state->base.rotation;
>  	u32 dspcntr;
>  
> -	dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
> +	dspcntr = DISPLAY_PLANE_ENABLE;
>  
>  	if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
>  	    IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
>  		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>  
> -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> -		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> -
> -	if (INTEL_GEN(dev_priv) < 5)
> -		dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
> -
>  	switch (fb->format->format) {
>  	case DRM_FORMAT_C8:
>  		dspcntr |= DISPPLANE_8BPP;
> @@ -3329,11 +3339,13 @@ static void i9xx_update_plane(struct intel_plane *plane,
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
>  	u32 linear_offset;
> -	u32 dspcntr = plane_state->ctl;
>  	int x = plane_state->color_plane[0].x;
>  	int y = plane_state->color_plane[0].y;
>  	unsigned long irqflags;
>  	u32 dspaddr_offset;
> +	u32 dspcntr;
> +
> +	dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
>  
>  	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>  
> @@ -3393,10 +3405,23 @@ static void i9xx_disable_plane(struct intel_plane *plane,
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
>  	unsigned long irqflags;
> +	u32 dspcntr;
> +
> +	/*
> +	 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
> +	 * enable on ilk+ affect the pipe bottom color as
> +	 * well, so we must configure them even if the plane
> +	 * is disabled.
> +	 *
> +	 * On pre-g4x there is no way to gamma correct the
> +	 * pipe bottom color but we'll keep on doing this
> +	 * anyway.
> +	 */
> +	dspcntr = i9xx_plane_ctl_crtc(crtc_state);
>  
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
> -	I915_WRITE_FW(DSPCNTR(i9xx_plane), 0);
> +	I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
>  	if (INTEL_GEN(dev_priv) >= 4)
>  		I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
>  	else
> @@ -3631,6 +3656,20 @@ static u32 cnl_plane_ctl_flip(unsigned int reflect)
>  	return 0;
>  }
>  
> +u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	u32 plane_ctl = 0;
> +
> +	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> +		return plane_ctl;
> +
> +	plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
> +	plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
> +
> +	return plane_ctl;
> +}
> +
>  u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>  		  const struct intel_plane_state *plane_state)
>  {
> @@ -3645,10 +3684,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>  
>  	if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
>  		plane_ctl |= skl_plane_ctl_alpha(plane_state);
> -		plane_ctl |=
> -			PLANE_CTL_PIPE_GAMMA_ENABLE |
> -			PLANE_CTL_PIPE_CSC_ENABLE |
> -			PLANE_CTL_PLANE_GAMMA_DISABLE;
> +		plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
>  
>  		if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
>  			plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
> @@ -3673,19 +3709,27 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>  	return plane_ctl;
>  }
>  
> +u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	u32 plane_color_ctl = 0;
> +
> +	if (INTEL_GEN(dev_priv) >= 11)
> +		return plane_color_ctl;
> +
> +	plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
> +	plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
> +
> +	return plane_color_ctl;
> +}
> +
>  u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
>  			const struct intel_plane_state *plane_state)
>  {
> -	struct drm_i915_private *dev_priv =
> -		to_i915(plane_state->base.plane->dev);
>  	const struct drm_framebuffer *fb = plane_state->base.fb;
>  	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>  	u32 plane_color_ctl = 0;
>  
> -	if (INTEL_GEN(dev_priv) < 11) {
> -		plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
> -		plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
> -	}
>  	plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
>  	plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
>  
> @@ -9867,11 +9911,15 @@ i845_cursor_max_stride(struct intel_plane *plane,
>  	return 2048;
>  }
>  
> +static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
> +{
> +	return CURSOR_GAMMA_ENABLE;
> +}
> +
>  static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
>  			   const struct intel_plane_state *plane_state)
>  {
>  	return CURSOR_ENABLE |
> -		CURSOR_GAMMA_ENABLE |
>  		CURSOR_FORMAT_ARGB |
>  		CURSOR_STRIDE(plane_state->color_plane[0].stride);
>  }
> @@ -9941,7 +9989,9 @@ static void i845_update_cursor(struct intel_plane *plane,
>  		unsigned int width = plane_state->base.crtc_w;
>  		unsigned int height = plane_state->base.crtc_h;
>  
> -		cntl = plane_state->ctl;
> +		cntl = plane_state->ctl |
> +			i845_cursor_ctl_crtc(crtc_state);
> +
>  		size = (height << 12) | width;
>  
>  		base = intel_cursor_base(plane_state);
> @@ -10006,27 +10056,36 @@ i9xx_cursor_max_stride(struct intel_plane *plane,
>  	return plane->base.dev->mode_config.cursor_width * 4;
>  }
>  
> -static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
> -			   const struct intel_plane_state *plane_state)
> +static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv =
> -		to_i915(plane_state->base.plane->dev);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	u32 cntl = 0;
>  
> -	if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
> -		cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
> +	if (INTEL_GEN(dev_priv) >= 11)
> +		return cntl;
>  
> -	if (INTEL_GEN(dev_priv) <= 10) {
> -		cntl |= MCURSOR_GAMMA_ENABLE;
> +	cntl |= MCURSOR_GAMMA_ENABLE;
>  
> -		if (HAS_DDI(dev_priv))
> -			cntl |= MCURSOR_PIPE_CSC_ENABLE;
> -	}
> +	if (HAS_DDI(dev_priv))
> +		cntl |= MCURSOR_PIPE_CSC_ENABLE;
>  
>  	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
>  		cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
>  
> +	return cntl;
> +}
> +
> +static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
> +			   const struct intel_plane_state *plane_state)
> +{
> +	struct drm_i915_private *dev_priv =
> +		to_i915(plane_state->base.plane->dev);
> +	u32 cntl = 0;
> +
> +	if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
> +		cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
> +
>  	switch (plane_state->base.crtc_w) {
>  	case 64:
>  		cntl |= MCURSOR_MODE_64_ARGB_AX;
> @@ -10151,7 +10210,8 @@ static void i9xx_update_cursor(struct intel_plane *plane,
>  	unsigned long irqflags;
>  
>  	if (plane_state && plane_state->base.visible) {
> -		cntl = plane_state->ctl;
> +		cntl = plane_state->ctl |
> +			i9xx_cursor_ctl_crtc(crtc_state);
>  
>  		if (plane_state->base.crtc_h != plane_state->base.crtc_w)
>  			fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 3b051fdd0fce..88ac42b2d7ed 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1752,9 +1752,10 @@ static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
>  
>  u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
>  			const struct intel_plane_state *plane_state);
> +u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
>  u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>  		  const struct intel_plane_state *plane_state);
> -u32 glk_color_ctl(const struct intel_plane_state *plane_state);
> +u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
>  u32 skl_plane_stride(const struct intel_plane_state *plane_state,
>  		     int plane);
>  int skl_check_plane_surface(struct intel_plane_state *plane_state);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 8f3982c03925..a45ef98b2f8d 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -484,9 +484,16 @@ skl_program_plane(struct intel_plane *plane,
>  	struct intel_plane *linked = plane_state->linked_plane;
>  	const struct drm_framebuffer *fb = plane_state->base.fb;
>  	u8 alpha = plane_state->base.alpha >> 8;
> +	u32 plane_color_ctl = 0;
>  	unsigned long irqflags;
>  	u32 keymsk, keymax;
>  
> +	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> +
> +	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> +		plane_color_ctl = plane_state->color_ctl |
> +			glk_plane_color_ctl_crtc(crtc_state);
> +
>  	/* Sizes are 0 based */
>  	src_w--;
>  	src_h--;
> @@ -533,8 +540,7 @@ skl_program_plane(struct intel_plane *plane,
>  	}
>  
>  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> -		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
> -			      plane_state->color_ctl);
> +		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
>  
>  	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
>  		icl_program_input_csc(plane, crtc_state, plane_state);
> @@ -731,6 +737,11 @@ vlv_update_clrc(const struct intel_plane_state *plane_state)
>  		      SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
>  }
>  
> +static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
> +{
> +	return SP_GAMMA_ENABLE;
> +}
> +
>  static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
>  			  const struct intel_plane_state *plane_state)
>  {
> @@ -739,7 +750,7 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
>  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
>  	u32 sprctl;
>  
> -	sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
> +	sprctl = SP_ENABLE;
>  
>  	switch (fb->format->format) {
>  	case DRM_FORMAT_YUYV:
> @@ -806,7 +817,6 @@ vlv_update_plane(struct intel_plane *plane,
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	enum pipe pipe = plane->pipe;
>  	enum plane_id plane_id = plane->id;
> -	u32 sprctl = plane_state->ctl;
>  	u32 sprsurf_offset = plane_state->color_plane[0].offset;
>  	u32 linear_offset;
>  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> @@ -817,6 +827,9 @@ vlv_update_plane(struct intel_plane *plane,
>  	uint32_t x = plane_state->color_plane[0].x;
>  	uint32_t y = plane_state->color_plane[0].y;
>  	unsigned long irqflags;
> +	u32 sprctl;
> +
> +	sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);
>  
>  	/* Sizes are 0 based */
>  	crtc_w--;
> @@ -897,6 +910,19 @@ vlv_plane_get_hw_state(struct intel_plane *plane,
>  	return ret;
>  }
>  
> +static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	u32 sprctl = 0;
> +
> +	sprctl |= SPRITE_GAMMA_ENABLE;
> +
> +	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> +		sprctl |= SPRITE_PIPE_CSC_ENABLE;
> +
> +	return sprctl;
> +}
> +
>  static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
>  			  const struct intel_plane_state *plane_state)
>  {
> @@ -907,14 +933,11 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
>  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
>  	u32 sprctl;
>  
> -	sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
> +	sprctl = SPRITE_ENABLE;
>  
>  	if (IS_IVYBRIDGE(dev_priv))
>  		sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
>  
> -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> -		sprctl |= SPRITE_PIPE_CSC_ENABLE;
> -
>  	switch (fb->format->format) {
>  	case DRM_FORMAT_XBGR8888:
>  		sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
> @@ -966,7 +989,6 @@ ivb_update_plane(struct intel_plane *plane,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	enum pipe pipe = plane->pipe;
> -	u32 sprctl = plane_state->ctl, sprscale = 0;
>  	u32 sprsurf_offset = plane_state->color_plane[0].offset;
>  	u32 linear_offset;
>  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> @@ -978,8 +1000,11 @@ ivb_update_plane(struct intel_plane *plane,
>  	uint32_t y = plane_state->color_plane[0].y;
>  	uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
>  	uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
> +	u32 sprctl, sprscale = 0;
>  	unsigned long irqflags;
>  
> +	sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);
> +
>  	/* Sizes are 0 based */
>  	src_w--;
>  	src_h--;
> @@ -1074,6 +1099,11 @@ g4x_sprite_max_stride(struct intel_plane *plane,
>  	return 16384;
>  }
>  
> +static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
> +{
> +	return DVS_GAMMA_ENABLE;
> +}
> +
>  static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
>  			  const struct intel_plane_state *plane_state)
>  {
> @@ -1084,7 +1114,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
>  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
>  	u32 dvscntr;
>  
> -	dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
> +	dvscntr = DVS_ENABLE;
>  
>  	if (IS_GEN(dev_priv, 6))
>  		dvscntr |= DVS_TRICKLE_FEED_DISABLE;
> @@ -1140,7 +1170,6 @@ g4x_update_plane(struct intel_plane *plane,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	enum pipe pipe = plane->pipe;
> -	u32 dvscntr = plane_state->ctl, dvsscale = 0;
>  	u32 dvssurf_offset = plane_state->color_plane[0].offset;
>  	u32 linear_offset;
>  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> @@ -1152,8 +1181,11 @@ g4x_update_plane(struct intel_plane *plane,
>  	uint32_t y = plane_state->color_plane[0].y;
>  	uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
>  	uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
> +	u32 dvscntr, dvsscale = 0;
>  	unsigned long irqflags;
>  
> +	dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);
> +
>  	/* Sizes are 0 based */
>  	src_w--;
>  	src_h--;
> -- 
> 2.19.2
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 02/13] drm/i915: Split the gamma/csc enable bits from the plane_ctl() function
  2019-01-12  0:41   ` Matt Roper
@ 2019-01-14 17:11     ` Ville Syrjälä
  2019-01-14 19:11       ` Ville Syrjälä
  0 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjälä @ 2019-01-14 17:11 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Fri, Jan 11, 2019 at 04:41:37PM -0800, Matt Roper wrote:
> On Fri, Jan 11, 2019 at 07:08:12PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > On g4x+ the pipe gamma enable bit for the primary plane affects
> > the pipe bottom color as well. The same for the pipe csc enable
> > bit on ilk+. Thus we must configure those bits correctly even
> > when the primary plane is disabled.
> 
> This is only true for <gen9, right? Starting with gen9, we have
> dedicated bits that control this, so I don't think the primay plane's
> settings should have any impact when disabled.  I.e., we also need the
> bits set in this patch:
> 
>         https://patchwork.freedesktop.org/patch/271109/

Yes. I had the same bits (or something similar in a later patch in
the series). But we should probably just land your stuff first.

> 
> > To make the feasible let's split those settings from the
> > plane_ctl() function into a seprate funciton that we can
> > call from the ->disable_plane() hook as well.
> 
> Is calling it from ->disable_plane() enough?  If we just disable the
> primary plane, then those bits will remain set while the crtc remains
> active.  But if you then disable the whole crtc and re-enable it again
> later, won't we have lost the bits at that point?

Hmm. Yes, probably.

Just adding a needs_modeset() check into
intel_color_add_affected_planes() (introduced in a later patch)
could be one way. But that means the plane control reg won't be
updated before the pipe is already active. So we might need a
special case for that too.

That said, I kinda hate the pipe enable special cases for the
color management stuff. So I'm wondering if we could eliminate
it all and just rely on the normal pipe+plane update to do
things correctly. But to make that consistent we might have to
have another special case to disable gamma/etc. prior to
enabling the pipe so that it can all be enabled atomically
later. Hmm. I suppose that could be achieved by clearing all
relevant control bits in disable_plane() (or in crtc_disable()
for skl+) if the crtc is no longer active.

And I guess we could still keep the .load_luts() special case
since guaranteeing the atomicity for that isn't as easy.

It would mean the pipe alwasy comes up with gamma and csc
disabled. But since it's all some shade of black anyway I
guess it shouldn't be a big deal.

> 
> 
> Matt
> 
> > 
> > For consistency we'll do that on all the plane types. While
> > that has no real benefits at this time, it'll become useful
> > when we start to control the pipe gamma/csc enable bits
> > dynamically when we overhaul the color management code.
> > 
> > On pre-g4x there doesn't appear to be any way to gamma
> > correct the pipe bottom color, but sticking to the same
> > pattern doesn't hurt. And it'll still help us to do
> > crtc state readout correctly for the pipe gamma enable
> > bit for the color management overhaul.
> > 
> > An alternative apporach would be to still precompute these
> > bits into plane_state->ctl, but that would require that we
> > run through the plane check even when the plane isn't logically
> > enabled on any crtc. Currently that condition causes us to
> > short circuit the entire thing and not call ->check_plane().
> > There would also be some chicken and egg problems with
> > ->check_plane() vs. crtc color state check that would
> > requite splitting certain things into multiple steps.
> > So all in all this seems like the easier route.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 128 ++++++++++++++++++++-------
> >  drivers/gpu/drm/i915/intel_drv.h     |   3 +-
> >  drivers/gpu/drm/i915/intel_sprite.c  |  54 ++++++++---
> >  3 files changed, 139 insertions(+), 46 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 5dc0de89c49e..a3871db4703b 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3180,28 +3180,38 @@ i9xx_plane_max_stride(struct intel_plane *plane,
> >  	}
> >  }
> >  
> > +static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
> > +{
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	u32 dspcntr = 0;
> > +
> > +	dspcntr |= DISPPLANE_GAMMA_ENABLE;
> > +
> > +	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > +		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> > +
> > +	if (INTEL_GEN(dev_priv) < 5)
> > +		dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
> > +
> > +	return dspcntr;
> > +}
> > +
> >  static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
> >  			  const struct intel_plane_state *plane_state)
> >  {
> >  	struct drm_i915_private *dev_priv =
> >  		to_i915(plane_state->base.plane->dev);
> > -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> >  	const struct drm_framebuffer *fb = plane_state->base.fb;
> >  	unsigned int rotation = plane_state->base.rotation;
> >  	u32 dspcntr;
> >  
> > -	dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
> > +	dspcntr = DISPLAY_PLANE_ENABLE;
> >  
> >  	if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
> >  	    IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
> >  		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
> >  
> > -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > -		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> > -
> > -	if (INTEL_GEN(dev_priv) < 5)
> > -		dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
> > -
> >  	switch (fb->format->format) {
> >  	case DRM_FORMAT_C8:
> >  		dspcntr |= DISPPLANE_8BPP;
> > @@ -3329,11 +3339,13 @@ static void i9xx_update_plane(struct intel_plane *plane,
> >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> >  	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> >  	u32 linear_offset;
> > -	u32 dspcntr = plane_state->ctl;
> >  	int x = plane_state->color_plane[0].x;
> >  	int y = plane_state->color_plane[0].y;
> >  	unsigned long irqflags;
> >  	u32 dspaddr_offset;
> > +	u32 dspcntr;
> > +
> > +	dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
> >  
> >  	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
> >  
> > @@ -3393,10 +3405,23 @@ static void i9xx_disable_plane(struct intel_plane *plane,
> >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> >  	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> >  	unsigned long irqflags;
> > +	u32 dspcntr;
> > +
> > +	/*
> > +	 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
> > +	 * enable on ilk+ affect the pipe bottom color as
> > +	 * well, so we must configure them even if the plane
> > +	 * is disabled.
> > +	 *
> > +	 * On pre-g4x there is no way to gamma correct the
> > +	 * pipe bottom color but we'll keep on doing this
> > +	 * anyway.
> > +	 */
> > +	dspcntr = i9xx_plane_ctl_crtc(crtc_state);
> >  
> >  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> >  
> > -	I915_WRITE_FW(DSPCNTR(i9xx_plane), 0);
> > +	I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
> >  	if (INTEL_GEN(dev_priv) >= 4)
> >  		I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
> >  	else
> > @@ -3631,6 +3656,20 @@ static u32 cnl_plane_ctl_flip(unsigned int reflect)
> >  	return 0;
> >  }
> >  
> > +u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> > +	u32 plane_ctl = 0;
> > +
> > +	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > +		return plane_ctl;
> > +
> > +	plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
> > +	plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
> > +
> > +	return plane_ctl;
> > +}
> > +
> >  u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
> >  		  const struct intel_plane_state *plane_state)
> >  {
> > @@ -3645,10 +3684,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
> >  
> >  	if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
> >  		plane_ctl |= skl_plane_ctl_alpha(plane_state);
> > -		plane_ctl |=
> > -			PLANE_CTL_PIPE_GAMMA_ENABLE |
> > -			PLANE_CTL_PIPE_CSC_ENABLE |
> > -			PLANE_CTL_PLANE_GAMMA_DISABLE;
> > +		plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
> >  
> >  		if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
> >  			plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
> > @@ -3673,19 +3709,27 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
> >  	return plane_ctl;
> >  }
> >  
> > +u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> > +	u32 plane_color_ctl = 0;
> > +
> > +	if (INTEL_GEN(dev_priv) >= 11)
> > +		return plane_color_ctl;
> > +
> > +	plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
> > +	plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
> > +
> > +	return plane_color_ctl;
> > +}
> > +
> >  u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> >  			const struct intel_plane_state *plane_state)
> >  {
> > -	struct drm_i915_private *dev_priv =
> > -		to_i915(plane_state->base.plane->dev);
> >  	const struct drm_framebuffer *fb = plane_state->base.fb;
> >  	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> >  	u32 plane_color_ctl = 0;
> >  
> > -	if (INTEL_GEN(dev_priv) < 11) {
> > -		plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
> > -		plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
> > -	}
> >  	plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
> >  	plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
> >  
> > @@ -9867,11 +9911,15 @@ i845_cursor_max_stride(struct intel_plane *plane,
> >  	return 2048;
> >  }
> >  
> > +static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
> > +{
> > +	return CURSOR_GAMMA_ENABLE;
> > +}
> > +
> >  static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
> >  			   const struct intel_plane_state *plane_state)
> >  {
> >  	return CURSOR_ENABLE |
> > -		CURSOR_GAMMA_ENABLE |
> >  		CURSOR_FORMAT_ARGB |
> >  		CURSOR_STRIDE(plane_state->color_plane[0].stride);
> >  }
> > @@ -9941,7 +9989,9 @@ static void i845_update_cursor(struct intel_plane *plane,
> >  		unsigned int width = plane_state->base.crtc_w;
> >  		unsigned int height = plane_state->base.crtc_h;
> >  
> > -		cntl = plane_state->ctl;
> > +		cntl = plane_state->ctl |
> > +			i845_cursor_ctl_crtc(crtc_state);
> > +
> >  		size = (height << 12) | width;
> >  
> >  		base = intel_cursor_base(plane_state);
> > @@ -10006,27 +10056,36 @@ i9xx_cursor_max_stride(struct intel_plane *plane,
> >  	return plane->base.dev->mode_config.cursor_width * 4;
> >  }
> >  
> > -static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
> > -			   const struct intel_plane_state *plane_state)
> > +static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
> >  {
> > -	struct drm_i915_private *dev_priv =
> > -		to_i915(plane_state->base.plane->dev);
> >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  	u32 cntl = 0;
> >  
> > -	if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
> > -		cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
> > +	if (INTEL_GEN(dev_priv) >= 11)
> > +		return cntl;
> >  
> > -	if (INTEL_GEN(dev_priv) <= 10) {
> > -		cntl |= MCURSOR_GAMMA_ENABLE;
> > +	cntl |= MCURSOR_GAMMA_ENABLE;
> >  
> > -		if (HAS_DDI(dev_priv))
> > -			cntl |= MCURSOR_PIPE_CSC_ENABLE;
> > -	}
> > +	if (HAS_DDI(dev_priv))
> > +		cntl |= MCURSOR_PIPE_CSC_ENABLE;
> >  
> >  	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
> >  		cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
> >  
> > +	return cntl;
> > +}
> > +
> > +static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
> > +			   const struct intel_plane_state *plane_state)
> > +{
> > +	struct drm_i915_private *dev_priv =
> > +		to_i915(plane_state->base.plane->dev);
> > +	u32 cntl = 0;
> > +
> > +	if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
> > +		cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
> > +
> >  	switch (plane_state->base.crtc_w) {
> >  	case 64:
> >  		cntl |= MCURSOR_MODE_64_ARGB_AX;
> > @@ -10151,7 +10210,8 @@ static void i9xx_update_cursor(struct intel_plane *plane,
> >  	unsigned long irqflags;
> >  
> >  	if (plane_state && plane_state->base.visible) {
> > -		cntl = plane_state->ctl;
> > +		cntl = plane_state->ctl |
> > +			i9xx_cursor_ctl_crtc(crtc_state);
> >  
> >  		if (plane_state->base.crtc_h != plane_state->base.crtc_w)
> >  			fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 3b051fdd0fce..88ac42b2d7ed 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1752,9 +1752,10 @@ static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
> >  
> >  u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> >  			const struct intel_plane_state *plane_state);
> > +u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
> >  u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
> >  		  const struct intel_plane_state *plane_state);
> > -u32 glk_color_ctl(const struct intel_plane_state *plane_state);
> > +u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
> >  u32 skl_plane_stride(const struct intel_plane_state *plane_state,
> >  		     int plane);
> >  int skl_check_plane_surface(struct intel_plane_state *plane_state);
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > index 8f3982c03925..a45ef98b2f8d 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -484,9 +484,16 @@ skl_program_plane(struct intel_plane *plane,
> >  	struct intel_plane *linked = plane_state->linked_plane;
> >  	const struct drm_framebuffer *fb = plane_state->base.fb;
> >  	u8 alpha = plane_state->base.alpha >> 8;
> > +	u32 plane_color_ctl = 0;
> >  	unsigned long irqflags;
> >  	u32 keymsk, keymax;
> >  
> > +	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> > +
> > +	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > +		plane_color_ctl = plane_state->color_ctl |
> > +			glk_plane_color_ctl_crtc(crtc_state);
> > +
> >  	/* Sizes are 0 based */
> >  	src_w--;
> >  	src_h--;
> > @@ -533,8 +540,7 @@ skl_program_plane(struct intel_plane *plane,
> >  	}
> >  
> >  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > -		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
> > -			      plane_state->color_ctl);
> > +		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
> >  
> >  	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
> >  		icl_program_input_csc(plane, crtc_state, plane_state);
> > @@ -731,6 +737,11 @@ vlv_update_clrc(const struct intel_plane_state *plane_state)
> >  		      SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
> >  }
> >  
> > +static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
> > +{
> > +	return SP_GAMMA_ENABLE;
> > +}
> > +
> >  static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
> >  			  const struct intel_plane_state *plane_state)
> >  {
> > @@ -739,7 +750,7 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
> >  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> >  	u32 sprctl;
> >  
> > -	sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
> > +	sprctl = SP_ENABLE;
> >  
> >  	switch (fb->format->format) {
> >  	case DRM_FORMAT_YUYV:
> > @@ -806,7 +817,6 @@ vlv_update_plane(struct intel_plane *plane,
> >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> >  	enum pipe pipe = plane->pipe;
> >  	enum plane_id plane_id = plane->id;
> > -	u32 sprctl = plane_state->ctl;
> >  	u32 sprsurf_offset = plane_state->color_plane[0].offset;
> >  	u32 linear_offset;
> >  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > @@ -817,6 +827,9 @@ vlv_update_plane(struct intel_plane *plane,
> >  	uint32_t x = plane_state->color_plane[0].x;
> >  	uint32_t y = plane_state->color_plane[0].y;
> >  	unsigned long irqflags;
> > +	u32 sprctl;
> > +
> > +	sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);
> >  
> >  	/* Sizes are 0 based */
> >  	crtc_w--;
> > @@ -897,6 +910,19 @@ vlv_plane_get_hw_state(struct intel_plane *plane,
> >  	return ret;
> >  }
> >  
> > +static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> > +	u32 sprctl = 0;
> > +
> > +	sprctl |= SPRITE_GAMMA_ENABLE;
> > +
> > +	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > +		sprctl |= SPRITE_PIPE_CSC_ENABLE;
> > +
> > +	return sprctl;
> > +}
> > +
> >  static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
> >  			  const struct intel_plane_state *plane_state)
> >  {
> > @@ -907,14 +933,11 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
> >  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> >  	u32 sprctl;
> >  
> > -	sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
> > +	sprctl = SPRITE_ENABLE;
> >  
> >  	if (IS_IVYBRIDGE(dev_priv))
> >  		sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
> >  
> > -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > -		sprctl |= SPRITE_PIPE_CSC_ENABLE;
> > -
> >  	switch (fb->format->format) {
> >  	case DRM_FORMAT_XBGR8888:
> >  		sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
> > @@ -966,7 +989,6 @@ ivb_update_plane(struct intel_plane *plane,
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> >  	enum pipe pipe = plane->pipe;
> > -	u32 sprctl = plane_state->ctl, sprscale = 0;
> >  	u32 sprsurf_offset = plane_state->color_plane[0].offset;
> >  	u32 linear_offset;
> >  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > @@ -978,8 +1000,11 @@ ivb_update_plane(struct intel_plane *plane,
> >  	uint32_t y = plane_state->color_plane[0].y;
> >  	uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
> >  	uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
> > +	u32 sprctl, sprscale = 0;
> >  	unsigned long irqflags;
> >  
> > +	sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);
> > +
> >  	/* Sizes are 0 based */
> >  	src_w--;
> >  	src_h--;
> > @@ -1074,6 +1099,11 @@ g4x_sprite_max_stride(struct intel_plane *plane,
> >  	return 16384;
> >  }
> >  
> > +static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
> > +{
> > +	return DVS_GAMMA_ENABLE;
> > +}
> > +
> >  static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
> >  			  const struct intel_plane_state *plane_state)
> >  {
> > @@ -1084,7 +1114,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
> >  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> >  	u32 dvscntr;
> >  
> > -	dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
> > +	dvscntr = DVS_ENABLE;
> >  
> >  	if (IS_GEN(dev_priv, 6))
> >  		dvscntr |= DVS_TRICKLE_FEED_DISABLE;
> > @@ -1140,7 +1170,6 @@ g4x_update_plane(struct intel_plane *plane,
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> >  	enum pipe pipe = plane->pipe;
> > -	u32 dvscntr = plane_state->ctl, dvsscale = 0;
> >  	u32 dvssurf_offset = plane_state->color_plane[0].offset;
> >  	u32 linear_offset;
> >  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > @@ -1152,8 +1181,11 @@ g4x_update_plane(struct intel_plane *plane,
> >  	uint32_t y = plane_state->color_plane[0].y;
> >  	uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
> >  	uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
> > +	u32 dvscntr, dvsscale = 0;
> >  	unsigned long irqflags;
> >  
> > +	dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);
> > +
> >  	/* Sizes are 0 based */
> >  	src_w--;
> >  	src_h--;
> > -- 
> > 2.19.2
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 02/13] drm/i915: Split the gamma/csc enable bits from the plane_ctl() function
  2019-01-14 17:11     ` Ville Syrjälä
@ 2019-01-14 19:11       ` Ville Syrjälä
  2019-01-16 17:11         ` Shankar, Uma
  0 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjälä @ 2019-01-14 19:11 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Mon, Jan 14, 2019 at 07:11:10PM +0200, Ville Syrjälä wrote:
> On Fri, Jan 11, 2019 at 04:41:37PM -0800, Matt Roper wrote:
> > On Fri, Jan 11, 2019 at 07:08:12PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > On g4x+ the pipe gamma enable bit for the primary plane affects
> > > the pipe bottom color as well. The same for the pipe csc enable
> > > bit on ilk+. Thus we must configure those bits correctly even
> > > when the primary plane is disabled.
> > 
> > This is only true for <gen9, right? Starting with gen9, we have
> > dedicated bits that control this, so I don't think the primay plane's
> > settings should have any impact when disabled.  I.e., we also need the
> > bits set in this patch:
> > 
> >         https://patchwork.freedesktop.org/patch/271109/
> 
> Yes. I had the same bits (or something similar in a later patch in
> the series). But we should probably just land your stuff first.
> 
> > 
> > > To make the feasible let's split those settings from the
> > > plane_ctl() function into a seprate funciton that we can
> > > call from the ->disable_plane() hook as well.
> > 
> > Is calling it from ->disable_plane() enough?  If we just disable the
> > primary plane, then those bits will remain set while the crtc remains
> > active.  But if you then disable the whole crtc and re-enable it again
> > later, won't we have lost the bits at that point?
> 
> Hmm. Yes, probably.
> 
> Just adding a needs_modeset() check into
> intel_color_add_affected_planes() (introduced in a later patch)
> could be one way. But that means the plane control reg won't be
> updated before the pipe is already active. So we might need a
> special case for that too.
> 
> That said, I kinda hate the pipe enable special cases for the
> color management stuff. So I'm wondering if we could eliminate
> it all and just rely on the normal pipe+plane update to do
> things correctly. But to make that consistent we might have to
> have another special case to disable gamma/etc. prior to
> enabling the pipe so that it can all be enabled atomically
> later. Hmm. I suppose that could be achieved by clearing all
> relevant control bits in disable_plane() (or in crtc_disable()
> for skl+) if the crtc is no longer active.
> 
> And I guess we could still keep the .load_luts() special case
> since guaranteeing the atomicity for that isn't as easy.
> 
> It would mean the pipe alwasy comes up with gamma and csc
> disabled. But since it's all some shade of black anyway I
> guess it shouldn't be a big deal.

Bah. That won't actually work without more hacks for the
case where the crtc was enabled already. I guess I'll just
have to stick an explicit primary->disable_plane() call
into the crtc_enable() path :(

> 
> > 
> > 
> > Matt
> > 
> > > 
> > > For consistency we'll do that on all the plane types. While
> > > that has no real benefits at this time, it'll become useful
> > > when we start to control the pipe gamma/csc enable bits
> > > dynamically when we overhaul the color management code.
> > > 
> > > On pre-g4x there doesn't appear to be any way to gamma
> > > correct the pipe bottom color, but sticking to the same
> > > pattern doesn't hurt. And it'll still help us to do
> > > crtc state readout correctly for the pipe gamma enable
> > > bit for the color management overhaul.
> > > 
> > > An alternative apporach would be to still precompute these
> > > bits into plane_state->ctl, but that would require that we
> > > run through the plane check even when the plane isn't logically
> > > enabled on any crtc. Currently that condition causes us to
> > > short circuit the entire thing and not call ->check_plane().
> > > There would also be some chicken and egg problems with
> > > ->check_plane() vs. crtc color state check that would
> > > requite splitting certain things into multiple steps.
> > > So all in all this seems like the easier route.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_display.c | 128 ++++++++++++++++++++-------
> > >  drivers/gpu/drm/i915/intel_drv.h     |   3 +-
> > >  drivers/gpu/drm/i915/intel_sprite.c  |  54 ++++++++---
> > >  3 files changed, 139 insertions(+), 46 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index 5dc0de89c49e..a3871db4703b 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -3180,28 +3180,38 @@ i9xx_plane_max_stride(struct intel_plane *plane,
> > >  	}
> > >  }
> > >  
> > > +static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
> > > +{
> > > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > +	u32 dspcntr = 0;
> > > +
> > > +	dspcntr |= DISPPLANE_GAMMA_ENABLE;
> > > +
> > > +	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > > +		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> > > +
> > > +	if (INTEL_GEN(dev_priv) < 5)
> > > +		dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
> > > +
> > > +	return dspcntr;
> > > +}
> > > +
> > >  static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
> > >  			  const struct intel_plane_state *plane_state)
> > >  {
> > >  	struct drm_i915_private *dev_priv =
> > >  		to_i915(plane_state->base.plane->dev);
> > > -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > >  	const struct drm_framebuffer *fb = plane_state->base.fb;
> > >  	unsigned int rotation = plane_state->base.rotation;
> > >  	u32 dspcntr;
> > >  
> > > -	dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
> > > +	dspcntr = DISPLAY_PLANE_ENABLE;
> > >  
> > >  	if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
> > >  	    IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
> > >  		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
> > >  
> > > -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > > -		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> > > -
> > > -	if (INTEL_GEN(dev_priv) < 5)
> > > -		dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
> > > -
> > >  	switch (fb->format->format) {
> > >  	case DRM_FORMAT_C8:
> > >  		dspcntr |= DISPPLANE_8BPP;
> > > @@ -3329,11 +3339,13 @@ static void i9xx_update_plane(struct intel_plane *plane,
> > >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > >  	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> > >  	u32 linear_offset;
> > > -	u32 dspcntr = plane_state->ctl;
> > >  	int x = plane_state->color_plane[0].x;
> > >  	int y = plane_state->color_plane[0].y;
> > >  	unsigned long irqflags;
> > >  	u32 dspaddr_offset;
> > > +	u32 dspcntr;
> > > +
> > > +	dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
> > >  
> > >  	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
> > >  
> > > @@ -3393,10 +3405,23 @@ static void i9xx_disable_plane(struct intel_plane *plane,
> > >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > >  	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> > >  	unsigned long irqflags;
> > > +	u32 dspcntr;
> > > +
> > > +	/*
> > > +	 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
> > > +	 * enable on ilk+ affect the pipe bottom color as
> > > +	 * well, so we must configure them even if the plane
> > > +	 * is disabled.
> > > +	 *
> > > +	 * On pre-g4x there is no way to gamma correct the
> > > +	 * pipe bottom color but we'll keep on doing this
> > > +	 * anyway.
> > > +	 */
> > > +	dspcntr = i9xx_plane_ctl_crtc(crtc_state);
> > >  
> > >  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> > >  
> > > -	I915_WRITE_FW(DSPCNTR(i9xx_plane), 0);
> > > +	I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
> > >  	if (INTEL_GEN(dev_priv) >= 4)
> > >  		I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
> > >  	else
> > > @@ -3631,6 +3656,20 @@ static u32 cnl_plane_ctl_flip(unsigned int reflect)
> > >  	return 0;
> > >  }
> > >  
> > > +u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
> > > +{
> > > +	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> > > +	u32 plane_ctl = 0;
> > > +
> > > +	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > > +		return plane_ctl;
> > > +
> > > +	plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
> > > +	plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
> > > +
> > > +	return plane_ctl;
> > > +}
> > > +
> > >  u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
> > >  		  const struct intel_plane_state *plane_state)
> > >  {
> > > @@ -3645,10 +3684,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
> > >  
> > >  	if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
> > >  		plane_ctl |= skl_plane_ctl_alpha(plane_state);
> > > -		plane_ctl |=
> > > -			PLANE_CTL_PIPE_GAMMA_ENABLE |
> > > -			PLANE_CTL_PIPE_CSC_ENABLE |
> > > -			PLANE_CTL_PLANE_GAMMA_DISABLE;
> > > +		plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
> > >  
> > >  		if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
> > >  			plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
> > > @@ -3673,19 +3709,27 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
> > >  	return plane_ctl;
> > >  }
> > >  
> > > +u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
> > > +{
> > > +	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> > > +	u32 plane_color_ctl = 0;
> > > +
> > > +	if (INTEL_GEN(dev_priv) >= 11)
> > > +		return plane_color_ctl;
> > > +
> > > +	plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
> > > +	plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
> > > +
> > > +	return plane_color_ctl;
> > > +}
> > > +
> > >  u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> > >  			const struct intel_plane_state *plane_state)
> > >  {
> > > -	struct drm_i915_private *dev_priv =
> > > -		to_i915(plane_state->base.plane->dev);
> > >  	const struct drm_framebuffer *fb = plane_state->base.fb;
> > >  	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> > >  	u32 plane_color_ctl = 0;
> > >  
> > > -	if (INTEL_GEN(dev_priv) < 11) {
> > > -		plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
> > > -		plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
> > > -	}
> > >  	plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
> > >  	plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
> > >  
> > > @@ -9867,11 +9911,15 @@ i845_cursor_max_stride(struct intel_plane *plane,
> > >  	return 2048;
> > >  }
> > >  
> > > +static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
> > > +{
> > > +	return CURSOR_GAMMA_ENABLE;
> > > +}
> > > +
> > >  static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
> > >  			   const struct intel_plane_state *plane_state)
> > >  {
> > >  	return CURSOR_ENABLE |
> > > -		CURSOR_GAMMA_ENABLE |
> > >  		CURSOR_FORMAT_ARGB |
> > >  		CURSOR_STRIDE(plane_state->color_plane[0].stride);
> > >  }
> > > @@ -9941,7 +9989,9 @@ static void i845_update_cursor(struct intel_plane *plane,
> > >  		unsigned int width = plane_state->base.crtc_w;
> > >  		unsigned int height = plane_state->base.crtc_h;
> > >  
> > > -		cntl = plane_state->ctl;
> > > +		cntl = plane_state->ctl |
> > > +			i845_cursor_ctl_crtc(crtc_state);
> > > +
> > >  		size = (height << 12) | width;
> > >  
> > >  		base = intel_cursor_base(plane_state);
> > > @@ -10006,27 +10056,36 @@ i9xx_cursor_max_stride(struct intel_plane *plane,
> > >  	return plane->base.dev->mode_config.cursor_width * 4;
> > >  }
> > >  
> > > -static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
> > > -			   const struct intel_plane_state *plane_state)
> > > +static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
> > >  {
> > > -	struct drm_i915_private *dev_priv =
> > > -		to_i915(plane_state->base.plane->dev);
> > >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > >  	u32 cntl = 0;
> > >  
> > > -	if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
> > > -		cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
> > > +	if (INTEL_GEN(dev_priv) >= 11)
> > > +		return cntl;
> > >  
> > > -	if (INTEL_GEN(dev_priv) <= 10) {
> > > -		cntl |= MCURSOR_GAMMA_ENABLE;
> > > +	cntl |= MCURSOR_GAMMA_ENABLE;
> > >  
> > > -		if (HAS_DDI(dev_priv))
> > > -			cntl |= MCURSOR_PIPE_CSC_ENABLE;
> > > -	}
> > > +	if (HAS_DDI(dev_priv))
> > > +		cntl |= MCURSOR_PIPE_CSC_ENABLE;
> > >  
> > >  	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
> > >  		cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
> > >  
> > > +	return cntl;
> > > +}
> > > +
> > > +static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
> > > +			   const struct intel_plane_state *plane_state)
> > > +{
> > > +	struct drm_i915_private *dev_priv =
> > > +		to_i915(plane_state->base.plane->dev);
> > > +	u32 cntl = 0;
> > > +
> > > +	if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
> > > +		cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
> > > +
> > >  	switch (plane_state->base.crtc_w) {
> > >  	case 64:
> > >  		cntl |= MCURSOR_MODE_64_ARGB_AX;
> > > @@ -10151,7 +10210,8 @@ static void i9xx_update_cursor(struct intel_plane *plane,
> > >  	unsigned long irqflags;
> > >  
> > >  	if (plane_state && plane_state->base.visible) {
> > > -		cntl = plane_state->ctl;
> > > +		cntl = plane_state->ctl |
> > > +			i9xx_cursor_ctl_crtc(crtc_state);
> > >  
> > >  		if (plane_state->base.crtc_h != plane_state->base.crtc_w)
> > >  			fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > > index 3b051fdd0fce..88ac42b2d7ed 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -1752,9 +1752,10 @@ static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
> > >  
> > >  u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> > >  			const struct intel_plane_state *plane_state);
> > > +u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
> > >  u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
> > >  		  const struct intel_plane_state *plane_state);
> > > -u32 glk_color_ctl(const struct intel_plane_state *plane_state);
> > > +u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
> > >  u32 skl_plane_stride(const struct intel_plane_state *plane_state,
> > >  		     int plane);
> > >  int skl_check_plane_surface(struct intel_plane_state *plane_state);
> > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > > index 8f3982c03925..a45ef98b2f8d 100644
> > > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > > @@ -484,9 +484,16 @@ skl_program_plane(struct intel_plane *plane,
> > >  	struct intel_plane *linked = plane_state->linked_plane;
> > >  	const struct drm_framebuffer *fb = plane_state->base.fb;
> > >  	u8 alpha = plane_state->base.alpha >> 8;
> > > +	u32 plane_color_ctl = 0;
> > >  	unsigned long irqflags;
> > >  	u32 keymsk, keymax;
> > >  
> > > +	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> > > +
> > > +	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > > +		plane_color_ctl = plane_state->color_ctl |
> > > +			glk_plane_color_ctl_crtc(crtc_state);
> > > +
> > >  	/* Sizes are 0 based */
> > >  	src_w--;
> > >  	src_h--;
> > > @@ -533,8 +540,7 @@ skl_program_plane(struct intel_plane *plane,
> > >  	}
> > >  
> > >  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > > -		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
> > > -			      plane_state->color_ctl);
> > > +		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
> > >  
> > >  	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
> > >  		icl_program_input_csc(plane, crtc_state, plane_state);
> > > @@ -731,6 +737,11 @@ vlv_update_clrc(const struct intel_plane_state *plane_state)
> > >  		      SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
> > >  }
> > >  
> > > +static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
> > > +{
> > > +	return SP_GAMMA_ENABLE;
> > > +}
> > > +
> > >  static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
> > >  			  const struct intel_plane_state *plane_state)
> > >  {
> > > @@ -739,7 +750,7 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
> > >  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > >  	u32 sprctl;
> > >  
> > > -	sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
> > > +	sprctl = SP_ENABLE;
> > >  
> > >  	switch (fb->format->format) {
> > >  	case DRM_FORMAT_YUYV:
> > > @@ -806,7 +817,6 @@ vlv_update_plane(struct intel_plane *plane,
> > >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > >  	enum pipe pipe = plane->pipe;
> > >  	enum plane_id plane_id = plane->id;
> > > -	u32 sprctl = plane_state->ctl;
> > >  	u32 sprsurf_offset = plane_state->color_plane[0].offset;
> > >  	u32 linear_offset;
> > >  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > > @@ -817,6 +827,9 @@ vlv_update_plane(struct intel_plane *plane,
> > >  	uint32_t x = plane_state->color_plane[0].x;
> > >  	uint32_t y = plane_state->color_plane[0].y;
> > >  	unsigned long irqflags;
> > > +	u32 sprctl;
> > > +
> > > +	sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);
> > >  
> > >  	/* Sizes are 0 based */
> > >  	crtc_w--;
> > > @@ -897,6 +910,19 @@ vlv_plane_get_hw_state(struct intel_plane *plane,
> > >  	return ret;
> > >  }
> > >  
> > > +static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
> > > +{
> > > +	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> > > +	u32 sprctl = 0;
> > > +
> > > +	sprctl |= SPRITE_GAMMA_ENABLE;
> > > +
> > > +	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > > +		sprctl |= SPRITE_PIPE_CSC_ENABLE;
> > > +
> > > +	return sprctl;
> > > +}
> > > +
> > >  static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
> > >  			  const struct intel_plane_state *plane_state)
> > >  {
> > > @@ -907,14 +933,11 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
> > >  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > >  	u32 sprctl;
> > >  
> > > -	sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
> > > +	sprctl = SPRITE_ENABLE;
> > >  
> > >  	if (IS_IVYBRIDGE(dev_priv))
> > >  		sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
> > >  
> > > -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > > -		sprctl |= SPRITE_PIPE_CSC_ENABLE;
> > > -
> > >  	switch (fb->format->format) {
> > >  	case DRM_FORMAT_XBGR8888:
> > >  		sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
> > > @@ -966,7 +989,6 @@ ivb_update_plane(struct intel_plane *plane,
> > >  {
> > >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > >  	enum pipe pipe = plane->pipe;
> > > -	u32 sprctl = plane_state->ctl, sprscale = 0;
> > >  	u32 sprsurf_offset = plane_state->color_plane[0].offset;
> > >  	u32 linear_offset;
> > >  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > > @@ -978,8 +1000,11 @@ ivb_update_plane(struct intel_plane *plane,
> > >  	uint32_t y = plane_state->color_plane[0].y;
> > >  	uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
> > >  	uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
> > > +	u32 sprctl, sprscale = 0;
> > >  	unsigned long irqflags;
> > >  
> > > +	sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);
> > > +
> > >  	/* Sizes are 0 based */
> > >  	src_w--;
> > >  	src_h--;
> > > @@ -1074,6 +1099,11 @@ g4x_sprite_max_stride(struct intel_plane *plane,
> > >  	return 16384;
> > >  }
> > >  
> > > +static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
> > > +{
> > > +	return DVS_GAMMA_ENABLE;
> > > +}
> > > +
> > >  static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
> > >  			  const struct intel_plane_state *plane_state)
> > >  {
> > > @@ -1084,7 +1114,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
> > >  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > >  	u32 dvscntr;
> > >  
> > > -	dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
> > > +	dvscntr = DVS_ENABLE;
> > >  
> > >  	if (IS_GEN(dev_priv, 6))
> > >  		dvscntr |= DVS_TRICKLE_FEED_DISABLE;
> > > @@ -1140,7 +1170,6 @@ g4x_update_plane(struct intel_plane *plane,
> > >  {
> > >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > >  	enum pipe pipe = plane->pipe;
> > > -	u32 dvscntr = plane_state->ctl, dvsscale = 0;
> > >  	u32 dvssurf_offset = plane_state->color_plane[0].offset;
> > >  	u32 linear_offset;
> > >  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > > @@ -1152,8 +1181,11 @@ g4x_update_plane(struct intel_plane *plane,
> > >  	uint32_t y = plane_state->color_plane[0].y;
> > >  	uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
> > >  	uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
> > > +	u32 dvscntr, dvsscale = 0;
> > >  	unsigned long irqflags;
> > >  
> > > +	dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);
> > > +
> > >  	/* Sizes are 0 based */
> > >  	src_w--;
> > >  	src_h--;
> > > -- 
> > > 2.19.2
> > > 
> > 
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > IoTG Platform Enabling & Development
> > Intel Corporation
> > (916) 356-2795
> 
> -- 
> Ville Syrjälä
> Intel
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 02/13] drm/i915: Split the gamma/csc enable bits from the plane_ctl() function
  2019-01-14 19:11       ` Ville Syrjälä
@ 2019-01-16 17:11         ` Shankar, Uma
  2019-01-17 16:34           ` Ville Syrjälä
  0 siblings, 1 reply; 52+ messages in thread
From: Shankar, Uma @ 2019-01-16 17:11 UTC (permalink / raw)
  To: Ville Syrjälä, Roper, Matthew D; +Cc: intel-gfx



>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Ville Syrjälä
>Sent: Tuesday, January 15, 2019 12:42 AM
>To: Roper, Matthew D <matthew.d.roper@intel.com>
>Cc: intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 02/13] drm/i915: Split the gamma/csc enable bits
>from the plane_ctl() function
>
>On Mon, Jan 14, 2019 at 07:11:10PM +0200, Ville Syrjälä wrote:
>> On Fri, Jan 11, 2019 at 04:41:37PM -0800, Matt Roper wrote:
>> > On Fri, Jan 11, 2019 at 07:08:12PM +0200, Ville Syrjala wrote:
>> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > >
>> > > On g4x+ the pipe gamma enable bit for the primary plane affects
>> > > the pipe bottom color as well. The same for the pipe csc enable
>> > > bit on ilk+. Thus we must configure those bits correctly even when
>> > > the primary plane is disabled.
>> >
>> > This is only true for <gen9, right? Starting with gen9, we have
>> > dedicated bits that control this, so I don't think the primay
>> > plane's settings should have any impact when disabled.  I.e., we
>> > also need the bits set in this patch:
>> >
>> >         https://patchwork.freedesktop.org/patch/271109/
>>
>> Yes. I had the same bits (or something similar in a later patch in the
>> series). But we should probably just land your stuff first.
>>
>> >
>> > > To make the feasible let's split those settings from the
>> > > plane_ctl() function into a seprate funciton that we can call from

Typo here.

>> > > the ->disable_plane() hook as well.
>> >
>> > Is calling it from ->disable_plane() enough?  If we just disable the
>> > primary plane, then those bits will remain set while the crtc
>> > remains active.  But if you then disable the whole crtc and
>> > re-enable it again later, won't we have lost the bits at that point?

Just curious, once crtc is re-enabled plane enable will eventually happen
where this can again be enabled. So is this the corner case where crtc gets 
enabled and primary plane is not enabled and it works with just overlays ?

If this is the case, why not just explicitly enable these separately in crtc enable
sequence and not rely on primary plane enabling path to set this for us. What
could be the potential problem if we do this ?

>>
>> Hmm. Yes, probably.
>>
>> Just adding a needs_modeset() check into
>> intel_color_add_affected_planes() (introduced in a later patch) could
>> be one way. But that means the plane control reg won't be updated
>> before the pipe is already active. So we might need a special case for
>> that too.
>>
>> That said, I kinda hate the pipe enable special cases for the color
>> management stuff. So I'm wondering if we could eliminate it all and
>> just rely on the normal pipe+plane update to do things correctly. But
>> to make that consistent we might have to have another special case to
>> disable gamma/etc. prior to enabling the pipe so that it can all be
>> enabled atomically later. Hmm. I suppose that could be achieved by
>> clearing all relevant control bits in disable_plane() (or in
>> crtc_disable() for skl+) if the crtc is no longer active.
>>
>> And I guess we could still keep the .load_luts() special case since
>> guaranteeing the atomicity for that isn't as easy.
>>
>> It would mean the pipe alwasy comes up with gamma and csc disabled.
>> But since it's all some shade of black anyway I guess it shouldn't be
>> a big deal.
>
>Bah. That won't actually work without more hacks for the case where the crtc
>was enabled already. I guess I'll just have to stick an explicit primary-
>>disable_plane() call into the crtc_enable() path :(

>>
>> >
>> >
>> > Matt
>> >
>> > >
>> > > For consistency we'll do that on all the plane types. While that
>> > > has no real benefits at this time, it'll become useful when we
>> > > start to control the pipe gamma/csc enable bits dynamically when
>> > > we overhaul the color management code.
>> > >
>> > > On pre-g4x there doesn't appear to be any way to gamma correct the
>> > > pipe bottom color, but sticking to the same pattern doesn't hurt.
>> > > And it'll still help us to do crtc state readout correctly for the
>> > > pipe gamma enable bit for the color management overhaul.
>> > >
>> > > An alternative apporach would be to still precompute these bits

Typo in approach.

>> > > into plane_state->ctl, but that would require that we run through
>> > > the plane check even when the plane isn't logically enabled on any
>> > > crtc. Currently that condition causes us to short circuit the
>> > > entire thing and not call ->check_plane().
>> > > There would also be some chicken and egg problems with
>> > > ->check_plane() vs. crtc color state check that would
>> > > requite splitting certain things into multiple steps.
>> > > So all in all this seems like the easier route.
>> > >
>> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > > ---
>> > >  drivers/gpu/drm/i915/intel_display.c | 128 ++++++++++++++++++++-------
>> > >  drivers/gpu/drm/i915/intel_drv.h     |   3 +-
>> > >  drivers/gpu/drm/i915/intel_sprite.c  |  54 ++++++++---
>> > >  3 files changed, 139 insertions(+), 46 deletions(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
>> > > b/drivers/gpu/drm/i915/intel_display.c
>> > > index 5dc0de89c49e..a3871db4703b 100644
>> > > --- a/drivers/gpu/drm/i915/intel_display.c
>> > > +++ b/drivers/gpu/drm/i915/intel_display.c
>> > > @@ -3180,28 +3180,38 @@ i9xx_plane_max_stride(struct intel_plane
>*plane,
>> > >  	}
>> > >  }
>> > >
>> > > +static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state
>> > > +*crtc_state) {
>> > > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> > > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > > +	u32 dspcntr = 0;
>> > > +
>> > > +	dspcntr |= DISPPLANE_GAMMA_ENABLE;
>> > > +
>> > > +	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>> > > +		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
>> > > +
>> > > +	if (INTEL_GEN(dev_priv) < 5)
>> > > +		dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
>> > > +
>> > > +	return dspcntr;
>> > > +}
>> > > +
>> > >  static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
>> > >  			  const struct intel_plane_state *plane_state)  {
>> > >  	struct drm_i915_private *dev_priv =
>> > >  		to_i915(plane_state->base.plane->dev);
>> > > -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> > >  	const struct drm_framebuffer *fb = plane_state->base.fb;
>> > >  	unsigned int rotation = plane_state->base.rotation;
>> > >  	u32 dspcntr;
>> > >
>> > > -	dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
>> > > +	dspcntr = DISPLAY_PLANE_ENABLE;
>> > >
>> > >  	if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
>> > >  	    IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
>> > >  		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>> > >
>> > > -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>> > > -		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
>> > > -
>> > > -	if (INTEL_GEN(dev_priv) < 5)
>> > > -		dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
>> > > -
>> > >  	switch (fb->format->format) {
>> > >  	case DRM_FORMAT_C8:
>> > >  		dspcntr |= DISPPLANE_8BPP;
>> > > @@ -3329,11 +3339,13 @@ static void i9xx_update_plane(struct
>intel_plane *plane,
>> > >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>> > >  	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
>> > >  	u32 linear_offset;
>> > > -	u32 dspcntr = plane_state->ctl;
>> > >  	int x = plane_state->color_plane[0].x;
>> > >  	int y = plane_state->color_plane[0].y;
>> > >  	unsigned long irqflags;
>> > >  	u32 dspaddr_offset;
>> > > +	u32 dspcntr;
>> > > +
>> > > +	dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
>> > >
>> > >  	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>> > >
>> > > @@ -3393,10 +3405,23 @@ static void i9xx_disable_plane(struct
>intel_plane *plane,
>> > >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>> > >  	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
>> > >  	unsigned long irqflags;
>> > > +	u32 dspcntr;
>> > > +
>> > > +	/*
>> > > +	 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
>> > > +	 * enable on ilk+ affect the pipe bottom color as
>> > > +	 * well, so we must configure them even if the plane
>> > > +	 * is disabled.
>> > > +	 *
>> > > +	 * On pre-g4x there is no way to gamma correct the
>> > > +	 * pipe bottom color but we'll keep on doing this
>> > > +	 * anyway.
>> > > +	 */
>> > > +	dspcntr = i9xx_plane_ctl_crtc(crtc_state);
>> > >
>> > >  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>> > >
>> > > -	I915_WRITE_FW(DSPCNTR(i9xx_plane), 0);
>> > > +	I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
>> > >  	if (INTEL_GEN(dev_priv) >= 4)
>> > >  		I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
>> > >  	else
>> > > @@ -3631,6 +3656,20 @@ static u32 cnl_plane_ctl_flip(unsigned int
>reflect)
>> > >  	return 0;
>> > >  }
>> > >
>> > > +u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
>> > > +{
>> > > +	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>> > > +	u32 plane_ctl = 0;
>> > > +
>> > > +	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>> > > +		return plane_ctl;
>> > > +
>> > > +	plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
>> > > +	plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
>> > > +
>> > > +	return plane_ctl;
>> > > +}
>> > > +
>> > >  u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>> > >  		  const struct intel_plane_state *plane_state)  { @@ -3645,10
>> > > +3684,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state
>> > > *crtc_state,
>> > >
>> > >  	if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
>> > >  		plane_ctl |= skl_plane_ctl_alpha(plane_state);
>> > > -		plane_ctl |=
>> > > -			PLANE_CTL_PIPE_GAMMA_ENABLE |
>> > > -			PLANE_CTL_PIPE_CSC_ENABLE |
>> > > -			PLANE_CTL_PLANE_GAMMA_DISABLE;
>> > > +		plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
>> > >
>> > >  		if (plane_state->base.color_encoding ==
>DRM_COLOR_YCBCR_BT709)
>> > >  			plane_ctl |=
>PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
>> > > @@ -3673,19 +3709,27 @@ u32 skl_plane_ctl(const struct intel_crtc_state
>*crtc_state,
>> > >  	return plane_ctl;
>> > >  }
>> > >
>> > > +u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state
>> > > +*crtc_state) {
>> > > +	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>> > > +	u32 plane_color_ctl = 0;
>> > > +
>> > > +	if (INTEL_GEN(dev_priv) >= 11)
>> > > +		return plane_color_ctl;
>> > > +
>> > > +	plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
>> > > +	plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
>> > > +
>> > > +	return plane_color_ctl;
>> > > +}
>> > > +
>> > >  u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
>> > >  			const struct intel_plane_state *plane_state)  {
>> > > -	struct drm_i915_private *dev_priv =
>> > > -		to_i915(plane_state->base.plane->dev);
>> > >  	const struct drm_framebuffer *fb = plane_state->base.fb;
>> > >  	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>> > >  	u32 plane_color_ctl = 0;
>> > >
>> > > -	if (INTEL_GEN(dev_priv) < 11) {
>> > > -		plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
>> > > -		plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
>> > > -	}
>> > >  	plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
>> > >  	plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
>> > >
>> > > @@ -9867,11 +9911,15 @@ i845_cursor_max_stride(struct intel_plane
>*plane,
>> > >  	return 2048;
>> > >  }
>> > >
>> > > +static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state
>> > > +*crtc_state) {

May be we can make this inline function.

>> > > +	return CURSOR_GAMMA_ENABLE;
>> > > +}
>> > > +
>> > >  static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
>> > >  			   const struct intel_plane_state *plane_state)  {
>> > >  	return CURSOR_ENABLE |
>> > > -		CURSOR_GAMMA_ENABLE |
>> > >  		CURSOR_FORMAT_ARGB |
>> > >  		CURSOR_STRIDE(plane_state->color_plane[0].stride);
>> > >  }
>> > > @@ -9941,7 +9989,9 @@ static void i845_update_cursor(struct intel_plane
>*plane,
>> > >  		unsigned int width = plane_state->base.crtc_w;
>> > >  		unsigned int height = plane_state->base.crtc_h;
>> > >
>> > > -		cntl = plane_state->ctl;
>> > > +		cntl = plane_state->ctl |
>> > > +			i845_cursor_ctl_crtc(crtc_state);
>> > > +
>> > >  		size = (height << 12) | width;
>> > >
>> > >  		base = intel_cursor_base(plane_state); @@ -10006,27
>+10056,36
>> > > @@ i9xx_cursor_max_stride(struct intel_plane *plane,
>> > >  	return plane->base.dev->mode_config.cursor_width * 4;  }
>> > >
>> > > -static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
>> > > -			   const struct intel_plane_state *plane_state)
>> > > +static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state
>> > > +*crtc_state)
>> > >  {
>> > > -	struct drm_i915_private *dev_priv =
>> > > -		to_i915(plane_state->base.plane->dev);
>> > >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> > > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > >  	u32 cntl = 0;
>> > >
>> > > -	if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
>> > > -		cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
>> > > +	if (INTEL_GEN(dev_priv) >= 11)
>> > > +		return cntl;
>> > >
>> > > -	if (INTEL_GEN(dev_priv) <= 10) {
>> > > -		cntl |= MCURSOR_GAMMA_ENABLE;
>> > > +	cntl |= MCURSOR_GAMMA_ENABLE;
>> > >
>> > > -		if (HAS_DDI(dev_priv))
>> > > -			cntl |= MCURSOR_PIPE_CSC_ENABLE;
>> > > -	}
>> > > +	if (HAS_DDI(dev_priv))
>> > > +		cntl |= MCURSOR_PIPE_CSC_ENABLE;
>> > >
>> > >  	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
>> > >  		cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
>> > >
>> > > +	return cntl;
>> > > +}
>> > > +
>> > > +static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
>> > > +			   const struct intel_plane_state *plane_state) {
>> > > +	struct drm_i915_private *dev_priv =
>> > > +		to_i915(plane_state->base.plane->dev);
>> > > +	u32 cntl = 0;
>> > > +
>> > > +	if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
>> > > +		cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
>> > > +
>> > >  	switch (plane_state->base.crtc_w) {
>> > >  	case 64:
>> > >  		cntl |= MCURSOR_MODE_64_ARGB_AX; @@ -10151,7 +10210,8
>@@ static
>> > > void i9xx_update_cursor(struct intel_plane *plane,
>> > >  	unsigned long irqflags;
>> > >
>> > >  	if (plane_state && plane_state->base.visible) {
>> > > -		cntl = plane_state->ctl;
>> > > +		cntl = plane_state->ctl |
>> > > +			i9xx_cursor_ctl_crtc(crtc_state);
>> > >
>> > >  		if (plane_state->base.crtc_h != plane_state->base.crtc_w)
>> > >  			fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h
>- 1);
>> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
>> > > b/drivers/gpu/drm/i915/intel_drv.h
>> > > index 3b051fdd0fce..88ac42b2d7ed 100644
>> > > --- a/drivers/gpu/drm/i915/intel_drv.h
>> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
>> > > @@ -1752,9 +1752,10 @@ static inline u32
>> > > intel_plane_ggtt_offset(const struct intel_plane_state *state)
>> > >
>> > >  u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
>> > >  			const struct intel_plane_state *plane_state);
>> > > +u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state
>> > > +*crtc_state);
>> > >  u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>> > >  		  const struct intel_plane_state *plane_state);
>> > > -u32 glk_color_ctl(const struct intel_plane_state *plane_state);
>> > > +u32 skl_plane_ctl_crtc(const struct intel_crtc_state
>> > > +*crtc_state);
>> > >  u32 skl_plane_stride(const struct intel_plane_state *plane_state,
>> > >  		     int plane);
>> > >  int skl_check_plane_surface(struct intel_plane_state
>> > > *plane_state); diff --git a/drivers/gpu/drm/i915/intel_sprite.c
>> > > b/drivers/gpu/drm/i915/intel_sprite.c
>> > > index 8f3982c03925..a45ef98b2f8d 100644
>> > > --- a/drivers/gpu/drm/i915/intel_sprite.c
>> > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> > > @@ -484,9 +484,16 @@ skl_program_plane(struct intel_plane *plane,
>> > >  	struct intel_plane *linked = plane_state->linked_plane;
>> > >  	const struct drm_framebuffer *fb = plane_state->base.fb;
>> > >  	u8 alpha = plane_state->base.alpha >> 8;
>> > > +	u32 plane_color_ctl = 0;
>> > >  	unsigned long irqflags;
>> > >  	u32 keymsk, keymax;
>> > >
>> > > +	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
>> > > +
>> > > +	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>> > > +		plane_color_ctl = plane_state->color_ctl |
>> > > +			glk_plane_color_ctl_crtc(crtc_state);
>> > > +
>> > >  	/* Sizes are 0 based */
>> > >  	src_w--;
>> > >  	src_h--;
>> > > @@ -533,8 +540,7 @@ skl_program_plane(struct intel_plane *plane,
>> > >  	}
>> > >
>> > >  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>> > > -		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
>> > > -			      plane_state->color_ctl);
>> > > +		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
>> > > +plane_color_ctl);
>> > >
>> > >  	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
>> > >  		icl_program_input_csc(plane, crtc_state, plane_state); @@
>> > > -731,6 +737,11 @@ vlv_update_clrc(const struct intel_plane_state
>*plane_state)
>> > >  		      SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));  }
>> > >
>> > > +static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state
>> > > +*crtc_state) {

This as well and other similar ones.

>> > > +	return SP_GAMMA_ENABLE;
>> > > +}
>> > > +
>> > >  static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
>> > >  			  const struct intel_plane_state *plane_state)  { @@ -
>739,7
>> > > +750,7 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state
>*crtc_state,
>> > >  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
>> > >  	u32 sprctl;
>> > >
>> > > -	sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
>> > > +	sprctl = SP_ENABLE;
>> > >
>> > >  	switch (fb->format->format) {
>> > >  	case DRM_FORMAT_YUYV:
>> > > @@ -806,7 +817,6 @@ vlv_update_plane(struct intel_plane *plane,
>> > >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>> > >  	enum pipe pipe = plane->pipe;
>> > >  	enum plane_id plane_id = plane->id;
>> > > -	u32 sprctl = plane_state->ctl;
>> > >  	u32 sprsurf_offset = plane_state->color_plane[0].offset;
>> > >  	u32 linear_offset;
>> > >  	const struct drm_intel_sprite_colorkey *key =
>> > > &plane_state->ckey; @@ -817,6 +827,9 @@ vlv_update_plane(struct
>intel_plane *plane,
>> > >  	uint32_t x = plane_state->color_plane[0].x;
>> > >  	uint32_t y = plane_state->color_plane[0].y;
>> > >  	unsigned long irqflags;
>> > > +	u32 sprctl;
>> > > +
>> > > +	sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);
>> > >
>> > >  	/* Sizes are 0 based */
>> > >  	crtc_w--;
>> > > @@ -897,6 +910,19 @@ vlv_plane_get_hw_state(struct intel_plane *plane,
>> > >  	return ret;
>> > >  }
>> > >
>> > > +static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state
>> > > +*crtc_state) {
>> > > +	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>> > > +	u32 sprctl = 0;
>> > > +
>> > > +	sprctl |= SPRITE_GAMMA_ENABLE;
>> > > +
>> > > +	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>> > > +		sprctl |= SPRITE_PIPE_CSC_ENABLE;
>> > > +
>> > > +	return sprctl;
>> > > +}
>> > > +
>> > >  static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
>> > >  			  const struct intel_plane_state *plane_state)  { @@ -
>907,14
>> > > +933,11 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state
>*crtc_state,
>> > >  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
>> > >  	u32 sprctl;
>> > >
>> > > -	sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
>> > > +	sprctl = SPRITE_ENABLE;
>> > >
>> > >  	if (IS_IVYBRIDGE(dev_priv))
>> > >  		sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
>> > >
>> > > -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>> > > -		sprctl |= SPRITE_PIPE_CSC_ENABLE;
>> > > -
>> > >  	switch (fb->format->format) {
>> > >  	case DRM_FORMAT_XBGR8888:
>> > >  		sprctl |= SPRITE_FORMAT_RGBX888 |
>SPRITE_RGB_ORDER_RGBX; @@
>> > > -966,7 +989,6 @@ ivb_update_plane(struct intel_plane *plane,  {
>> > >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>> > >  	enum pipe pipe = plane->pipe;
>> > > -	u32 sprctl = plane_state->ctl, sprscale = 0;
>> > >  	u32 sprsurf_offset = plane_state->color_plane[0].offset;
>> > >  	u32 linear_offset;
>> > >  	const struct drm_intel_sprite_colorkey *key =
>> > > &plane_state->ckey; @@ -978,8 +1000,11 @@ ivb_update_plane(struct
>intel_plane *plane,
>> > >  	uint32_t y = plane_state->color_plane[0].y;
>> > >  	uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
>> > >  	uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
>> > > +	u32 sprctl, sprscale = 0;
>> > >  	unsigned long irqflags;
>> > >
>> > > +	sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);
>> > > +
>> > >  	/* Sizes are 0 based */
>> > >  	src_w--;
>> > >  	src_h--;
>> > > @@ -1074,6 +1099,11 @@ g4x_sprite_max_stride(struct intel_plane
>*plane,
>> > >  	return 16384;
>> > >  }
>> > >
>> > > +static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state
>> > > +*crtc_state) {
>> > > +	return DVS_GAMMA_ENABLE;
>> > > +}
>> > > +
>> > >  static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
>> > >  			  const struct intel_plane_state *plane_state)  { @@ -
>1084,7
>> > > +1114,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state
>*crtc_state,
>> > >  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
>> > >  	u32 dvscntr;
>> > >
>> > > -	dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
>> > > +	dvscntr = DVS_ENABLE;
>> > >
>> > >  	if (IS_GEN(dev_priv, 6))
>> > >  		dvscntr |= DVS_TRICKLE_FEED_DISABLE; @@ -1140,7 +1170,6
>@@
>> > > g4x_update_plane(struct intel_plane *plane,  {
>> > >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>> > >  	enum pipe pipe = plane->pipe;
>> > > -	u32 dvscntr = plane_state->ctl, dvsscale = 0;
>> > >  	u32 dvssurf_offset = plane_state->color_plane[0].offset;
>> > >  	u32 linear_offset;
>> > >  	const struct drm_intel_sprite_colorkey *key =
>> > > &plane_state->ckey; @@ -1152,8 +1181,11 @@ g4x_update_plane(struct
>intel_plane *plane,
>> > >  	uint32_t y = plane_state->color_plane[0].y;
>> > >  	uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
>> > >  	uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
>> > > +	u32 dvscntr, dvsscale = 0;
>> > >  	unsigned long irqflags;
>> > >
>> > > +	dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);
>> > > +
>> > >  	/* Sizes are 0 based */
>> > >  	src_w--;
>> > >  	src_h--;
>> > > --
>> > > 2.19.2
>> > >
>> >
>> > --
>> > Matt Roper
>> > Graphics Software Engineer
>> > IoTG Platform Enabling & Development Intel Corporation
>> > (916) 356-2795
>>
>> --
>> Ville Syrjälä
>> Intel
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>--
>Ville Syrjälä
>Intel
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 02/13] drm/i915: Split the gamma/csc enable bits from the plane_ctl() function
  2019-01-16 17:11         ` Shankar, Uma
@ 2019-01-17 16:34           ` Ville Syrjälä
  0 siblings, 0 replies; 52+ messages in thread
From: Ville Syrjälä @ 2019-01-17 16:34 UTC (permalink / raw)
  To: Shankar, Uma; +Cc: intel-gfx

On Wed, Jan 16, 2019 at 05:11:26PM +0000, Shankar, Uma wrote:
> 
> 
> >-----Original Message-----
> >From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
> >Ville Syrjälä
> >Sent: Tuesday, January 15, 2019 12:42 AM
> >To: Roper, Matthew D <matthew.d.roper@intel.com>
> >Cc: intel-gfx@lists.freedesktop.org
> >Subject: Re: [Intel-gfx] [PATCH 02/13] drm/i915: Split the gamma/csc enable bits
> >from the plane_ctl() function
> >
> >On Mon, Jan 14, 2019 at 07:11:10PM +0200, Ville Syrjälä wrote:
> >> On Fri, Jan 11, 2019 at 04:41:37PM -0800, Matt Roper wrote:
> >> > On Fri, Jan 11, 2019 at 07:08:12PM +0200, Ville Syrjala wrote:
> >> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> > >
> >> > > On g4x+ the pipe gamma enable bit for the primary plane affects
> >> > > the pipe bottom color as well. The same for the pipe csc enable
> >> > > bit on ilk+. Thus we must configure those bits correctly even when
> >> > > the primary plane is disabled.
> >> >
> >> > This is only true for <gen9, right? Starting with gen9, we have
> >> > dedicated bits that control this, so I don't think the primay
> >> > plane's settings should have any impact when disabled.  I.e., we
> >> > also need the bits set in this patch:
> >> >
> >> >         https://patchwork.freedesktop.org/patch/271109/
> >>
> >> Yes. I had the same bits (or something similar in a later patch in the
> >> series). But we should probably just land your stuff first.
> >>
> >> >
> >> > > To make the feasible let's split those settings from the
> >> > > plane_ctl() function into a seprate funciton that we can call from
> 
> Typo here.
> 
> >> > > the ->disable_plane() hook as well.
> >> >
> >> > Is calling it from ->disable_plane() enough?  If we just disable the
> >> > primary plane, then those bits will remain set while the crtc
> >> > remains active.  But if you then disable the whole crtc and
> >> > re-enable it again later, won't we have lost the bits at that point?
> 
> Just curious, once crtc is re-enabled plane enable will eventually happen
> where this can again be enabled. So is this the corner case where crtc gets 
> enabled and primary plane is not enabled and it works with just overlays ?

Yes.

> 
> If this is the case, why not just explicitly enable these separately in crtc enable
> sequence and not rely on primary plane enabling path to set this for us. What
> could be the potential problem if we do this ?

We have to configure them whenever gamma_enable/csc_enable change. Not
just crtc_enable. So we'd have to duplicate the DSPCNTR reg writes in
color_commit()/something which would also mean doing an ugly RMW since
we wouldn't have the plane state around. Much cleaner to just add the
plane to the state and let the normal codepath handle it.

> 
> >>
> >> Hmm. Yes, probably.
> >>
> >> Just adding a needs_modeset() check into
> >> intel_color_add_affected_planes() (introduced in a later patch) could
> >> be one way. But that means the plane control reg won't be updated
> >> before the pipe is already active. So we might need a special case for
> >> that too.
> >>
> >> That said, I kinda hate the pipe enable special cases for the color
> >> management stuff. So I'm wondering if we could eliminate it all and
> >> just rely on the normal pipe+plane update to do things correctly. But
> >> to make that consistent we might have to have another special case to
> >> disable gamma/etc. prior to enabling the pipe so that it can all be
> >> enabled atomically later. Hmm. I suppose that could be achieved by
> >> clearing all relevant control bits in disable_plane() (or in
> >> crtc_disable() for skl+) if the crtc is no longer active.
> >>
> >> And I guess we could still keep the .load_luts() special case since
> >> guaranteeing the atomicity for that isn't as easy.
> >>
> >> It would mean the pipe alwasy comes up with gamma and csc disabled.
> >> But since it's all some shade of black anyway I guess it shouldn't be
> >> a big deal.
> >
> >Bah. That won't actually work without more hacks for the case where the crtc
> >was enabled already. I guess I'll just have to stick an explicit primary-
> >>disable_plane() call into the crtc_enable() path :(
> 
> >>
> >> >
> >> >
> >> > Matt
> >> >
> >> > >
> >> > > For consistency we'll do that on all the plane types. While that
> >> > > has no real benefits at this time, it'll become useful when we
> >> > > start to control the pipe gamma/csc enable bits dynamically when
> >> > > we overhaul the color management code.
> >> > >
> >> > > On pre-g4x there doesn't appear to be any way to gamma correct the
> >> > > pipe bottom color, but sticking to the same pattern doesn't hurt.
> >> > > And it'll still help us to do crtc state readout correctly for the
> >> > > pipe gamma enable bit for the color management overhaul.
> >> > >
> >> > > An alternative apporach would be to still precompute these bits
> 
> Typo in approach.
> 
> >> > > into plane_state->ctl, but that would require that we run through
> >> > > the plane check even when the plane isn't logically enabled on any
> >> > > crtc. Currently that condition causes us to short circuit the
> >> > > entire thing and not call ->check_plane().
> >> > > There would also be some chicken and egg problems with
> >> > > ->check_plane() vs. crtc color state check that would
> >> > > requite splitting certain things into multiple steps.
> >> > > So all in all this seems like the easier route.
> >> > >
> >> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> > > ---
> >> > >  drivers/gpu/drm/i915/intel_display.c | 128 ++++++++++++++++++++-------
> >> > >  drivers/gpu/drm/i915/intel_drv.h     |   3 +-
> >> > >  drivers/gpu/drm/i915/intel_sprite.c  |  54 ++++++++---
> >> > >  3 files changed, 139 insertions(+), 46 deletions(-)
> >> > >
> >> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> >> > > b/drivers/gpu/drm/i915/intel_display.c
> >> > > index 5dc0de89c49e..a3871db4703b 100644
> >> > > --- a/drivers/gpu/drm/i915/intel_display.c
> >> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> >> > > @@ -3180,28 +3180,38 @@ i9xx_plane_max_stride(struct intel_plane
> >*plane,
> >> > >  	}
> >> > >  }
> >> > >
> >> > > +static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state
> >> > > +*crtc_state) {
> >> > > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> >> > > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> > > +	u32 dspcntr = 0;
> >> > > +
> >> > > +	dspcntr |= DISPPLANE_GAMMA_ENABLE;
> >> > > +
> >> > > +	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> >> > > +		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> >> > > +
> >> > > +	if (INTEL_GEN(dev_priv) < 5)
> >> > > +		dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
> >> > > +
> >> > > +	return dspcntr;
> >> > > +}
> >> > > +
> >> > >  static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
> >> > >  			  const struct intel_plane_state *plane_state)  {
> >> > >  	struct drm_i915_private *dev_priv =
> >> > >  		to_i915(plane_state->base.plane->dev);
> >> > > -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> >> > >  	const struct drm_framebuffer *fb = plane_state->base.fb;
> >> > >  	unsigned int rotation = plane_state->base.rotation;
> >> > >  	u32 dspcntr;
> >> > >
> >> > > -	dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
> >> > > +	dspcntr = DISPLAY_PLANE_ENABLE;
> >> > >
> >> > >  	if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
> >> > >  	    IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
> >> > >  		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
> >> > >
> >> > > -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> >> > > -		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> >> > > -
> >> > > -	if (INTEL_GEN(dev_priv) < 5)
> >> > > -		dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
> >> > > -
> >> > >  	switch (fb->format->format) {
> >> > >  	case DRM_FORMAT_C8:
> >> > >  		dspcntr |= DISPPLANE_8BPP;
> >> > > @@ -3329,11 +3339,13 @@ static void i9xx_update_plane(struct
> >intel_plane *plane,
> >> > >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> >> > >  	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> >> > >  	u32 linear_offset;
> >> > > -	u32 dspcntr = plane_state->ctl;
> >> > >  	int x = plane_state->color_plane[0].x;
> >> > >  	int y = plane_state->color_plane[0].y;
> >> > >  	unsigned long irqflags;
> >> > >  	u32 dspaddr_offset;
> >> > > +	u32 dspcntr;
> >> > > +
> >> > > +	dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
> >> > >
> >> > >  	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
> >> > >
> >> > > @@ -3393,10 +3405,23 @@ static void i9xx_disable_plane(struct
> >intel_plane *plane,
> >> > >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> >> > >  	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> >> > >  	unsigned long irqflags;
> >> > > +	u32 dspcntr;
> >> > > +
> >> > > +	/*
> >> > > +	 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
> >> > > +	 * enable on ilk+ affect the pipe bottom color as
> >> > > +	 * well, so we must configure them even if the plane
> >> > > +	 * is disabled.
> >> > > +	 *
> >> > > +	 * On pre-g4x there is no way to gamma correct the
> >> > > +	 * pipe bottom color but we'll keep on doing this
> >> > > +	 * anyway.
> >> > > +	 */
> >> > > +	dspcntr = i9xx_plane_ctl_crtc(crtc_state);
> >> > >
> >> > >  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> >> > >
> >> > > -	I915_WRITE_FW(DSPCNTR(i9xx_plane), 0);
> >> > > +	I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
> >> > >  	if (INTEL_GEN(dev_priv) >= 4)
> >> > >  		I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
> >> > >  	else
> >> > > @@ -3631,6 +3656,20 @@ static u32 cnl_plane_ctl_flip(unsigned int
> >reflect)
> >> > >  	return 0;
> >> > >  }
> >> > >
> >> > > +u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
> >> > > +{
> >> > > +	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> >> > > +	u32 plane_ctl = 0;
> >> > > +
> >> > > +	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> >> > > +		return plane_ctl;
> >> > > +
> >> > > +	plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
> >> > > +	plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
> >> > > +
> >> > > +	return plane_ctl;
> >> > > +}
> >> > > +
> >> > >  u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
> >> > >  		  const struct intel_plane_state *plane_state)  { @@ -3645,10
> >> > > +3684,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state
> >> > > *crtc_state,
> >> > >
> >> > >  	if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
> >> > >  		plane_ctl |= skl_plane_ctl_alpha(plane_state);
> >> > > -		plane_ctl |=
> >> > > -			PLANE_CTL_PIPE_GAMMA_ENABLE |
> >> > > -			PLANE_CTL_PIPE_CSC_ENABLE |
> >> > > -			PLANE_CTL_PLANE_GAMMA_DISABLE;
> >> > > +		plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
> >> > >
> >> > >  		if (plane_state->base.color_encoding ==
> >DRM_COLOR_YCBCR_BT709)
> >> > >  			plane_ctl |=
> >PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
> >> > > @@ -3673,19 +3709,27 @@ u32 skl_plane_ctl(const struct intel_crtc_state
> >*crtc_state,
> >> > >  	return plane_ctl;
> >> > >  }
> >> > >
> >> > > +u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state
> >> > > +*crtc_state) {
> >> > > +	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> >> > > +	u32 plane_color_ctl = 0;
> >> > > +
> >> > > +	if (INTEL_GEN(dev_priv) >= 11)
> >> > > +		return plane_color_ctl;
> >> > > +
> >> > > +	plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
> >> > > +	plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
> >> > > +
> >> > > +	return plane_color_ctl;
> >> > > +}
> >> > > +
> >> > >  u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> >> > >  			const struct intel_plane_state *plane_state)  {
> >> > > -	struct drm_i915_private *dev_priv =
> >> > > -		to_i915(plane_state->base.plane->dev);
> >> > >  	const struct drm_framebuffer *fb = plane_state->base.fb;
> >> > >  	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> >> > >  	u32 plane_color_ctl = 0;
> >> > >
> >> > > -	if (INTEL_GEN(dev_priv) < 11) {
> >> > > -		plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
> >> > > -		plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
> >> > > -	}
> >> > >  	plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
> >> > >  	plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
> >> > >
> >> > > @@ -9867,11 +9911,15 @@ i845_cursor_max_stride(struct intel_plane
> >*plane,
> >> > >  	return 2048;
> >> > >  }
> >> > >
> >> > > +static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state
> >> > > +*crtc_state) {
> 
> May be we can make this inline function.

The compiler will inline if it deems it beneficial.

> 
> >> > > +	return CURSOR_GAMMA_ENABLE;
> >> > > +}
> >> > > +
> >> > >  static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
> >> > >  			   const struct intel_plane_state *plane_state)  {
> >> > >  	return CURSOR_ENABLE |
> >> > > -		CURSOR_GAMMA_ENABLE |
> >> > >  		CURSOR_FORMAT_ARGB |
> >> > >  		CURSOR_STRIDE(plane_state->color_plane[0].stride);
> >> > >  }
> >> > > @@ -9941,7 +9989,9 @@ static void i845_update_cursor(struct intel_plane
> >*plane,
> >> > >  		unsigned int width = plane_state->base.crtc_w;
> >> > >  		unsigned int height = plane_state->base.crtc_h;
> >> > >
> >> > > -		cntl = plane_state->ctl;
> >> > > +		cntl = plane_state->ctl |
> >> > > +			i845_cursor_ctl_crtc(crtc_state);
> >> > > +
> >> > >  		size = (height << 12) | width;
> >> > >
> >> > >  		base = intel_cursor_base(plane_state); @@ -10006,27
> >+10056,36
> >> > > @@ i9xx_cursor_max_stride(struct intel_plane *plane,
> >> > >  	return plane->base.dev->mode_config.cursor_width * 4;  }
> >> > >
> >> > > -static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
> >> > > -			   const struct intel_plane_state *plane_state)
> >> > > +static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state
> >> > > +*crtc_state)
> >> > >  {
> >> > > -	struct drm_i915_private *dev_priv =
> >> > > -		to_i915(plane_state->base.plane->dev);
> >> > >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> >> > > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> > >  	u32 cntl = 0;
> >> > >
> >> > > -	if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
> >> > > -		cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
> >> > > +	if (INTEL_GEN(dev_priv) >= 11)
> >> > > +		return cntl;
> >> > >
> >> > > -	if (INTEL_GEN(dev_priv) <= 10) {
> >> > > -		cntl |= MCURSOR_GAMMA_ENABLE;
> >> > > +	cntl |= MCURSOR_GAMMA_ENABLE;
> >> > >
> >> > > -		if (HAS_DDI(dev_priv))
> >> > > -			cntl |= MCURSOR_PIPE_CSC_ENABLE;
> >> > > -	}
> >> > > +	if (HAS_DDI(dev_priv))
> >> > > +		cntl |= MCURSOR_PIPE_CSC_ENABLE;
> >> > >
> >> > >  	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
> >> > >  		cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
> >> > >
> >> > > +	return cntl;
> >> > > +}
> >> > > +
> >> > > +static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
> >> > > +			   const struct intel_plane_state *plane_state) {
> >> > > +	struct drm_i915_private *dev_priv =
> >> > > +		to_i915(plane_state->base.plane->dev);
> >> > > +	u32 cntl = 0;
> >> > > +
> >> > > +	if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
> >> > > +		cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
> >> > > +
> >> > >  	switch (plane_state->base.crtc_w) {
> >> > >  	case 64:
> >> > >  		cntl |= MCURSOR_MODE_64_ARGB_AX; @@ -10151,7 +10210,8
> >@@ static
> >> > > void i9xx_update_cursor(struct intel_plane *plane,
> >> > >  	unsigned long irqflags;
> >> > >
> >> > >  	if (plane_state && plane_state->base.visible) {
> >> > > -		cntl = plane_state->ctl;
> >> > > +		cntl = plane_state->ctl |
> >> > > +			i9xx_cursor_ctl_crtc(crtc_state);
> >> > >
> >> > >  		if (plane_state->base.crtc_h != plane_state->base.crtc_w)
> >> > >  			fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h
> >- 1);
> >> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> >> > > b/drivers/gpu/drm/i915/intel_drv.h
> >> > > index 3b051fdd0fce..88ac42b2d7ed 100644
> >> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> >> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> >> > > @@ -1752,9 +1752,10 @@ static inline u32
> >> > > intel_plane_ggtt_offset(const struct intel_plane_state *state)
> >> > >
> >> > >  u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> >> > >  			const struct intel_plane_state *plane_state);
> >> > > +u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state
> >> > > +*crtc_state);
> >> > >  u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
> >> > >  		  const struct intel_plane_state *plane_state);
> >> > > -u32 glk_color_ctl(const struct intel_plane_state *plane_state);
> >> > > +u32 skl_plane_ctl_crtc(const struct intel_crtc_state
> >> > > +*crtc_state);
> >> > >  u32 skl_plane_stride(const struct intel_plane_state *plane_state,
> >> > >  		     int plane);
> >> > >  int skl_check_plane_surface(struct intel_plane_state
> >> > > *plane_state); diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> >> > > b/drivers/gpu/drm/i915/intel_sprite.c
> >> > > index 8f3982c03925..a45ef98b2f8d 100644
> >> > > --- a/drivers/gpu/drm/i915/intel_sprite.c
> >> > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> >> > > @@ -484,9 +484,16 @@ skl_program_plane(struct intel_plane *plane,
> >> > >  	struct intel_plane *linked = plane_state->linked_plane;
> >> > >  	const struct drm_framebuffer *fb = plane_state->base.fb;
> >> > >  	u8 alpha = plane_state->base.alpha >> 8;
> >> > > +	u32 plane_color_ctl = 0;
> >> > >  	unsigned long irqflags;
> >> > >  	u32 keymsk, keymax;
> >> > >
> >> > > +	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> >> > > +
> >> > > +	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> >> > > +		plane_color_ctl = plane_state->color_ctl |
> >> > > +			glk_plane_color_ctl_crtc(crtc_state);
> >> > > +
> >> > >  	/* Sizes are 0 based */
> >> > >  	src_w--;
> >> > >  	src_h--;
> >> > > @@ -533,8 +540,7 @@ skl_program_plane(struct intel_plane *plane,
> >> > >  	}
> >> > >
> >> > >  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> >> > > -		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
> >> > > -			      plane_state->color_ctl);
> >> > > +		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
> >> > > +plane_color_ctl);
> >> > >
> >> > >  	if (fb->format->is_yuv && icl_is_hdr_plane(plane))
> >> > >  		icl_program_input_csc(plane, crtc_state, plane_state); @@
> >> > > -731,6 +737,11 @@ vlv_update_clrc(const struct intel_plane_state
> >*plane_state)
> >> > >  		      SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));  }
> >> > >
> >> > > +static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state
> >> > > +*crtc_state) {
> 
> This as well and other similar ones.
> 
> >> > > +	return SP_GAMMA_ENABLE;
> >> > > +}
> >> > > +
> >> > >  static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
> >> > >  			  const struct intel_plane_state *plane_state)  { @@ -
> >739,7
> >> > > +750,7 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state
> >*crtc_state,
> >> > >  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> >> > >  	u32 sprctl;
> >> > >
> >> > > -	sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
> >> > > +	sprctl = SP_ENABLE;
> >> > >
> >> > >  	switch (fb->format->format) {
> >> > >  	case DRM_FORMAT_YUYV:
> >> > > @@ -806,7 +817,6 @@ vlv_update_plane(struct intel_plane *plane,
> >> > >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> >> > >  	enum pipe pipe = plane->pipe;
> >> > >  	enum plane_id plane_id = plane->id;
> >> > > -	u32 sprctl = plane_state->ctl;
> >> > >  	u32 sprsurf_offset = plane_state->color_plane[0].offset;
> >> > >  	u32 linear_offset;
> >> > >  	const struct drm_intel_sprite_colorkey *key =
> >> > > &plane_state->ckey; @@ -817,6 +827,9 @@ vlv_update_plane(struct
> >intel_plane *plane,
> >> > >  	uint32_t x = plane_state->color_plane[0].x;
> >> > >  	uint32_t y = plane_state->color_plane[0].y;
> >> > >  	unsigned long irqflags;
> >> > > +	u32 sprctl;
> >> > > +
> >> > > +	sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);
> >> > >
> >> > >  	/* Sizes are 0 based */
> >> > >  	crtc_w--;
> >> > > @@ -897,6 +910,19 @@ vlv_plane_get_hw_state(struct intel_plane *plane,
> >> > >  	return ret;
> >> > >  }
> >> > >
> >> > > +static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state
> >> > > +*crtc_state) {
> >> > > +	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> >> > > +	u32 sprctl = 0;
> >> > > +
> >> > > +	sprctl |= SPRITE_GAMMA_ENABLE;
> >> > > +
> >> > > +	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> >> > > +		sprctl |= SPRITE_PIPE_CSC_ENABLE;
> >> > > +
> >> > > +	return sprctl;
> >> > > +}
> >> > > +
> >> > >  static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
> >> > >  			  const struct intel_plane_state *plane_state)  { @@ -
> >907,14
> >> > > +933,11 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state
> >*crtc_state,
> >> > >  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> >> > >  	u32 sprctl;
> >> > >
> >> > > -	sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
> >> > > +	sprctl = SPRITE_ENABLE;
> >> > >
> >> > >  	if (IS_IVYBRIDGE(dev_priv))
> >> > >  		sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
> >> > >
> >> > > -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> >> > > -		sprctl |= SPRITE_PIPE_CSC_ENABLE;
> >> > > -
> >> > >  	switch (fb->format->format) {
> >> > >  	case DRM_FORMAT_XBGR8888:
> >> > >  		sprctl |= SPRITE_FORMAT_RGBX888 |
> >SPRITE_RGB_ORDER_RGBX; @@
> >> > > -966,7 +989,6 @@ ivb_update_plane(struct intel_plane *plane,  {
> >> > >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> >> > >  	enum pipe pipe = plane->pipe;
> >> > > -	u32 sprctl = plane_state->ctl, sprscale = 0;
> >> > >  	u32 sprsurf_offset = plane_state->color_plane[0].offset;
> >> > >  	u32 linear_offset;
> >> > >  	const struct drm_intel_sprite_colorkey *key =
> >> > > &plane_state->ckey; @@ -978,8 +1000,11 @@ ivb_update_plane(struct
> >intel_plane *plane,
> >> > >  	uint32_t y = plane_state->color_plane[0].y;
> >> > >  	uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
> >> > >  	uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
> >> > > +	u32 sprctl, sprscale = 0;
> >> > >  	unsigned long irqflags;
> >> > >
> >> > > +	sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);
> >> > > +
> >> > >  	/* Sizes are 0 based */
> >> > >  	src_w--;
> >> > >  	src_h--;
> >> > > @@ -1074,6 +1099,11 @@ g4x_sprite_max_stride(struct intel_plane
> >*plane,
> >> > >  	return 16384;
> >> > >  }
> >> > >
> >> > > +static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state
> >> > > +*crtc_state) {
> >> > > +	return DVS_GAMMA_ENABLE;
> >> > > +}
> >> > > +
> >> > >  static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
> >> > >  			  const struct intel_plane_state *plane_state)  { @@ -
> >1084,7
> >> > > +1114,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state
> >*crtc_state,
> >> > >  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> >> > >  	u32 dvscntr;
> >> > >
> >> > > -	dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
> >> > > +	dvscntr = DVS_ENABLE;
> >> > >
> >> > >  	if (IS_GEN(dev_priv, 6))
> >> > >  		dvscntr |= DVS_TRICKLE_FEED_DISABLE; @@ -1140,7 +1170,6
> >@@
> >> > > g4x_update_plane(struct intel_plane *plane,  {
> >> > >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> >> > >  	enum pipe pipe = plane->pipe;
> >> > > -	u32 dvscntr = plane_state->ctl, dvsscale = 0;
> >> > >  	u32 dvssurf_offset = plane_state->color_plane[0].offset;
> >> > >  	u32 linear_offset;
> >> > >  	const struct drm_intel_sprite_colorkey *key =
> >> > > &plane_state->ckey; @@ -1152,8 +1181,11 @@ g4x_update_plane(struct
> >intel_plane *plane,
> >> > >  	uint32_t y = plane_state->color_plane[0].y;
> >> > >  	uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
> >> > >  	uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
> >> > > +	u32 dvscntr, dvsscale = 0;
> >> > >  	unsigned long irqflags;
> >> > >
> >> > > +	dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);
> >> > > +
> >> > >  	/* Sizes are 0 based */
> >> > >  	src_w--;
> >> > >  	src_h--;
> >> > > --
> >> > > 2.19.2
> >> > >
> >> >
> >> > --
> >> > Matt Roper
> >> > Graphics Software Engineer
> >> > IoTG Platform Enabling & Development Intel Corporation
> >> > (916) 356-2795
> >>
> >> --
> >> Ville Syrjälä
> >> Intel
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> >--
> >Ville Syrjälä
> >Intel
> >_______________________________________________
> >Intel-gfx mailing list
> >Intel-gfx@lists.freedesktop.org
> >https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* [PATCH 03/13] drm/i915: Precompute gamma_mode
  2019-01-11 17:08 [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8 Ville Syrjala
  2019-01-11 17:08 ` [PATCH 01/13] drm/i915: Clean up intel_plane_atomic_check_with_state() Ville Syrjala
  2019-01-11 17:08 ` [PATCH 02/13] drm/i915: Split the gamma/csc enable bits from the plane_ctl() function Ville Syrjala
@ 2019-01-11 17:08 ` Ville Syrjala
  2019-01-12  0:41   ` Matt Roper
  2019-01-11 17:08 ` [PATCH 04/13] drm/i915: Constify the state arguments to the color management stuff Ville Syrjala
                   ` (12 subsequent siblings)
  15 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjala @ 2019-01-11 17:08 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We shouldn't be computing gamma mode during the commit phase.
Move it to the check phase.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_color.c | 44 +++++++++++++++++-------------
 1 file changed, 25 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 37fd9ddf762e..b10e66ce3970 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -375,8 +375,7 @@ static void haswell_load_luts(struct intel_crtc_state *crtc_state)
 		reenable_ips = true;
 	}
 
-	crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
-	I915_WRITE(GAMMA_MODE(crtc->pipe), GAMMA_MODE_MODE_8BIT);
+	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
 
 	i9xx_load_luts(crtc_state);
 
@@ -476,9 +475,7 @@ static void broadwell_load_luts(struct intel_crtc_state *crtc_state)
 	bdw_load_gamma_lut(crtc_state,
 			   INTEL_INFO(dev_priv)->color.degamma_lut_size);
 
-	crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
-	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
-	POSTING_READ(GAMMA_MODE(pipe));
+	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
 
 	/*
 	 * Reset the index, otherwise it prevents the legacy palette to be
@@ -532,9 +529,7 @@ static void glk_load_luts(struct intel_crtc_state *crtc_state)
 
 	bdw_load_gamma_lut(crtc_state, 0);
 
-	crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
-	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT);
-	POSTING_READ(GAMMA_MODE(pipe));
+	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
 }
 
 /* Loads the palette/gamma unit for the CRTC on CherryView. */
@@ -608,29 +603,40 @@ void intel_color_load_luts(struct intel_crtc_state *crtc_state)
 int intel_color_check(struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
+	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
 	size_t gamma_length, degamma_length;
 
 	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 
 	/*
-	 * We allow both degamma & gamma luts at the right size or
-	 * NULL.
+	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
+	 * size (256 entries).
 	 */
-	if ((!crtc_state->base.degamma_lut ||
-	     drm_color_lut_size(crtc_state->base.degamma_lut) == degamma_length) &&
-	    (!crtc_state->base.gamma_lut ||
-	     drm_color_lut_size(crtc_state->base.gamma_lut) == gamma_length))
+	if (crtc_state_is_legacy_gamma(crtc_state)) {
+		crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
 		return 0;
+	}
 
 	/*
-	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
-	 * size (256 entries).
+	 * We allow both degamma & gamma luts at the right size or
+	 * NULL.
 	 */
-	if (crtc_state_is_legacy_gamma(crtc_state))
-		return 0;
+	if (degamma_lut && drm_color_lut_size(degamma_lut) != degamma_length)
+		return -EINVAL;
+
+	if (gamma_lut && drm_color_lut_size(gamma_lut) != gamma_length)
+		return -EINVAL;
+
+	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+		crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
+	else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
+		crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
+	else
+		crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
 
-	return -EINVAL;
+	return 0;
 }
 
 void intel_color_init(struct intel_crtc *crtc)
-- 
2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 52+ messages in thread

* Re: [PATCH 03/13] drm/i915: Precompute gamma_mode
  2019-01-11 17:08 ` [PATCH 03/13] drm/i915: Precompute gamma_mode Ville Syrjala
@ 2019-01-12  0:41   ` Matt Roper
  2019-01-16 17:18     ` Shankar, Uma
  0 siblings, 1 reply; 52+ messages in thread
From: Matt Roper @ 2019-01-12  0:41 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Jan 11, 2019 at 07:08:13PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We shouldn't be computing gamma mode during the commit phase.
> Move it to the check phase.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Looks like this also drops the posting reads, but I don't see anything
in the bspec that indicates those were necessary in the first place.

> ---
>  drivers/gpu/drm/i915/intel_color.c | 44 +++++++++++++++++-------------
>  1 file changed, 25 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 37fd9ddf762e..b10e66ce3970 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -375,8 +375,7 @@ static void haswell_load_luts(struct intel_crtc_state *crtc_state)
>  		reenable_ips = true;
>  	}
>  
> -	crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> -	I915_WRITE(GAMMA_MODE(crtc->pipe), GAMMA_MODE_MODE_8BIT);
> +	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
>  
>  	i9xx_load_luts(crtc_state);
>  
> @@ -476,9 +475,7 @@ static void broadwell_load_luts(struct intel_crtc_state *crtc_state)
>  	bdw_load_gamma_lut(crtc_state,
>  			   INTEL_INFO(dev_priv)->color.degamma_lut_size);
>  
> -	crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
> -	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
> -	POSTING_READ(GAMMA_MODE(pipe));
> +	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
>  
>  	/*
>  	 * Reset the index, otherwise it prevents the legacy palette to be
> @@ -532,9 +529,7 @@ static void glk_load_luts(struct intel_crtc_state *crtc_state)
>  
>  	bdw_load_gamma_lut(crtc_state, 0);
>  
> -	crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
> -	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT);
> -	POSTING_READ(GAMMA_MODE(pipe));
> +	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
>  }
>  
>  /* Loads the palette/gamma unit for the CRTC on CherryView. */
> @@ -608,29 +603,40 @@ void intel_color_load_luts(struct intel_crtc_state *crtc_state)
>  int intel_color_check(struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> +	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
>  	size_t gamma_length, degamma_length;
>  
>  	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>  	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>  
>  	/*
> -	 * We allow both degamma & gamma luts at the right size or
> -	 * NULL.
> +	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
> +	 * size (256 entries).
>  	 */

Minor nit:  now that the order of tests is swapped, you probably want
to move the "also" from this comment down to the one below.

Otherwise,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> -	if ((!crtc_state->base.degamma_lut ||
> -	     drm_color_lut_size(crtc_state->base.degamma_lut) == degamma_length) &&
> -	    (!crtc_state->base.gamma_lut ||
> -	     drm_color_lut_size(crtc_state->base.gamma_lut) == gamma_length))
> +	if (crtc_state_is_legacy_gamma(crtc_state)) {
> +		crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
>  		return 0;
> +	}
>  
>  	/*
> -	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
> -	 * size (256 entries).
> +	 * We allow both degamma & gamma luts at the right size or
> +	 * NULL.
>  	 */
> -	if (crtc_state_is_legacy_gamma(crtc_state))
> -		return 0;
> +	if (degamma_lut && drm_color_lut_size(degamma_lut) != degamma_length)
> +		return -EINVAL;
> +
> +	if (gamma_lut && drm_color_lut_size(gamma_lut) != gamma_length)
> +		return -EINVAL;
> +
> +	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> +		crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
> +	else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> +		crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
> +	else
> +		crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
>  
> -	return -EINVAL;
> +	return 0;
>  }
>  
>  void intel_color_init(struct intel_crtc *crtc)
> -- 
> 2.19.2
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 03/13] drm/i915: Precompute gamma_mode
  2019-01-12  0:41   ` Matt Roper
@ 2019-01-16 17:18     ` Shankar, Uma
  0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-01-16 17:18 UTC (permalink / raw)
  To: Roper, Matthew D, Ville Syrjala; +Cc: intel-gfx



>-----Original Message-----
>From: Roper, Matthew D
>Sent: Saturday, January 12, 2019 6:12 AM
>To: Ville Syrjala <ville.syrjala@linux.intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>
>Subject: Re: [PATCH 03/13] drm/i915: Precompute gamma_mode
>
>On Fri, Jan 11, 2019 at 07:08:13PM +0200, Ville Syrjala wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> We shouldn't be computing gamma mode during the commit phase.
>> Move it to the check phase.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Looks like this also drops the posting reads, but I don't see anything in the bspec
>that indicates those were necessary in the first place.
>
>> ---
>>  drivers/gpu/drm/i915/intel_color.c | 44
>> +++++++++++++++++-------------
>>  1 file changed, 25 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index 37fd9ddf762e..b10e66ce3970 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -375,8 +375,7 @@ static void haswell_load_luts(struct intel_crtc_state
>*crtc_state)
>>  		reenable_ips = true;
>>  	}
>>
>> -	crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
>> -	I915_WRITE(GAMMA_MODE(crtc->pipe), GAMMA_MODE_MODE_8BIT);
>> +	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
>>
>>  	i9xx_load_luts(crtc_state);
>>
>> @@ -476,9 +475,7 @@ static void broadwell_load_luts(struct intel_crtc_state
>*crtc_state)
>>  	bdw_load_gamma_lut(crtc_state,
>>  			   INTEL_INFO(dev_priv)->color.degamma_lut_size);
>>
>> -	crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
>> -	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
>> -	POSTING_READ(GAMMA_MODE(pipe));
>> +	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
>>
>>  	/*
>>  	 * Reset the index, otherwise it prevents the legacy palette to be
>> @@ -532,9 +529,7 @@ static void glk_load_luts(struct intel_crtc_state
>> *crtc_state)
>>
>>  	bdw_load_gamma_lut(crtc_state, 0);
>>
>> -	crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
>> -	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT);
>> -	POSTING_READ(GAMMA_MODE(pipe));
>> +	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
>>  }
>>
>>  /* Loads the palette/gamma unit for the CRTC on CherryView. */ @@
>> -608,29 +603,40 @@ void intel_color_load_luts(struct intel_crtc_state
>> *crtc_state)  int intel_color_check(struct intel_crtc_state
>> *crtc_state)  {
>>  	struct drm_i915_private *dev_priv =
>> to_i915(crtc_state->base.crtc->dev);
>> +	const struct drm_property_blob *gamma_lut = crtc_state-
>>base.gamma_lut;
>> +	const struct drm_property_blob *degamma_lut =
>> +crtc_state->base.degamma_lut;
>>  	size_t gamma_length, degamma_length;
>>
>>  	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>>  	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>>
>>  	/*
>> -	 * We allow both degamma & gamma luts at the right size or
>> -	 * NULL.
>> +	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
>> +	 * size (256 entries).
>>  	 */
>
>Minor nit:  now that the order of tests is swapped, you probably want to move
>the "also" from this comment down to the one below.
>
>Otherwise,
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Looks ok to me as well.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>
>> -	if ((!crtc_state->base.degamma_lut ||
>> -	     drm_color_lut_size(crtc_state->base.degamma_lut) ==
>degamma_length) &&
>> -	    (!crtc_state->base.gamma_lut ||
>> -	     drm_color_lut_size(crtc_state->base.gamma_lut) == gamma_length))
>> +	if (crtc_state_is_legacy_gamma(crtc_state)) {
>> +		crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
>>  		return 0;
>> +	}
>>
>>  	/*
>> -	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
>> -	 * size (256 entries).
>> +	 * We allow both degamma & gamma luts at the right size or
>> +	 * NULL.
>>  	 */
>> -	if (crtc_state_is_legacy_gamma(crtc_state))
>> -		return 0;
>> +	if (degamma_lut && drm_color_lut_size(degamma_lut) !=
>degamma_length)
>> +		return -EINVAL;
>> +
>> +	if (gamma_lut && drm_color_lut_size(gamma_lut) != gamma_length)
>> +		return -EINVAL;
>> +
>> +	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>> +		crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
>> +	else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
>> +		crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
>> +	else
>> +		crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
>>
>> -	return -EINVAL;
>> +	return 0;
>>  }
>>
>>  void intel_color_init(struct intel_crtc *crtc)
>> --
>> 2.19.2
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>IoTG Platform Enabling & Development
>Intel Corporation
>(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* [PATCH 04/13] drm/i915: Constify the state arguments to the color management stuff
  2019-01-11 17:08 [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8 Ville Syrjala
                   ` (2 preceding siblings ...)
  2019-01-11 17:08 ` [PATCH 03/13] drm/i915: Precompute gamma_mode Ville Syrjala
@ 2019-01-11 17:08 ` Ville Syrjala
  2019-01-12  0:42   ` Matt Roper
  2019-01-11 17:08 ` [PATCH 05/13] drm/i915: Pull GAMMA_MODE write out from haswell_load_luts() Ville Syrjala
                   ` (11 subsequent siblings)
  15 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjala @ 2019-01-11 17:08 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pass the crtc state etc. as const to the color management commit
functions. And while at it polish some of the local variables.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h    |   4 +-
 drivers/gpu/drm/i915/intel_color.c | 128 ++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_drv.h   |   4 +-
 3 files changed, 73 insertions(+), 63 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5df26ccda8a4..7182a580002c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -320,8 +320,8 @@ struct drm_i915_display_funcs {
 	/* display clock increase/decrease */
 	/* pll clock increase/decrease */
 
-	void (*load_csc_matrix)(struct intel_crtc_state *crtc_state);
-	void (*load_luts)(struct intel_crtc_state *crtc_state);
+	void (*load_csc_matrix)(const struct intel_crtc_state *crtc_state);
+	void (*load_luts)(const struct intel_crtc_state *crtc_state);
 };
 
 #define CSR_VERSION(major, minor)	((major) << 16 | (minor))
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index b10e66ce3970..0dfd104b89d7 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -74,12 +74,12 @@
 #define ILK_CSC_COEFF_1_0		\
 	((7 << 12) | ILK_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
 
-static bool lut_is_legacy(struct drm_property_blob *lut)
+static bool lut_is_legacy(const struct drm_property_blob *lut)
 {
 	return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
 }
 
-static bool crtc_state_is_legacy_gamma(struct intel_crtc_state *crtc_state)
+static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state)
 {
 	return !crtc_state->base.degamma_lut &&
 		!crtc_state->base.ctm &&
@@ -115,8 +115,8 @@ static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
 
 static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
 {
-	int pipe = crtc->pipe;
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
 
 	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
 	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
@@ -137,13 +137,14 @@ static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
 	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
 }
 
-static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
+static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int i, pipe = crtc->pipe;
-	uint16_t coeffs[9] = { 0, };
 	bool limited_color_range = false;
+	enum pipe pipe = crtc->pipe;
+	u16 coeffs[9] = {};
+	int i;
 
 	/*
 	 * FIXME if there's a gamma LUT after the CSC, we should
@@ -256,15 +257,15 @@ static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
 /*
  * Set up the pipe CSC unit on CherryView.
  */
-static void cherryview_load_csc_matrix(struct intel_crtc_state *crtc_state)
+static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_device *dev = crtc_state->base.crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	int pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
 	uint32_t mode;
 
 	if (crtc_state->base.ctm) {
-		struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
+		const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
 		uint16_t coeffs[9] = { 0, };
 		int i;
 
@@ -303,18 +304,17 @@ static void cherryview_load_csc_matrix(struct intel_crtc_state *crtc_state)
 	I915_WRITE(CGM_PIPE_MODE(pipe), mode);
 }
 
-void intel_color_set_csc(struct intel_crtc_state *crtc_state)
+void intel_color_set_csc(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_device *dev = crtc_state->base.crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 
 	if (dev_priv->display.load_csc_matrix)
 		dev_priv->display.load_csc_matrix(crtc_state);
 }
 
 /* Loads the legacy palette/gamma unit for the CRTC. */
-static void i9xx_load_luts_internal(struct intel_crtc_state *crtc_state,
-				    struct drm_property_blob *blob)
+static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
+				    const struct drm_property_blob *blob)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -329,7 +329,8 @@ static void i9xx_load_luts_internal(struct intel_crtc_state *crtc_state,
 	}
 
 	if (blob) {
-		struct drm_color_lut *lut = blob->data;
+		const struct drm_color_lut *lut = blob->data;
+
 		for (i = 0; i < 256; i++) {
 			uint32_t word =
 				(drm_color_lut_extract(lut[i].red, 8) << 16) |
@@ -353,13 +354,13 @@ static void i9xx_load_luts_internal(struct intel_crtc_state *crtc_state,
 	}
 }
 
-static void i9xx_load_luts(struct intel_crtc_state *crtc_state)
+static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
 }
 
 /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
-static void haswell_load_luts(struct intel_crtc_state *crtc_state)
+static void haswell_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -383,17 +384,19 @@ static void haswell_load_luts(struct intel_crtc_state *crtc_state)
 		hsw_enable_ips(crtc_state);
 }
 
-static void bdw_load_degamma_lut(struct intel_crtc_state *crtc_state)
+static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
-	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
 	uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
+	enum pipe pipe = crtc->pipe;
 
 	I915_WRITE(PREC_PAL_INDEX(pipe),
 		   PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
 
-	if (crtc_state->base.degamma_lut) {
-		struct drm_color_lut *lut = crtc_state->base.degamma_lut->data;
+	if (degamma_lut) {
+		const struct drm_color_lut *lut = degamma_lut->data;
 
 		for (i = 0; i < lut_size; i++) {
 			uint32_t word =
@@ -413,11 +416,13 @@ static void bdw_load_degamma_lut(struct intel_crtc_state *crtc_state)
 	}
 }
 
-static void bdw_load_gamma_lut(struct intel_crtc_state *crtc_state, u32 offset)
+static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 offset)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
-	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 	uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	enum pipe pipe = crtc->pipe;
 
 	WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
 
@@ -426,8 +431,8 @@ static void bdw_load_gamma_lut(struct intel_crtc_state *crtc_state, u32 offset)
 		   PAL_PREC_AUTO_INCREMENT |
 		   offset);
 
-	if (crtc_state->base.gamma_lut) {
-		struct drm_color_lut *lut = crtc_state->base.gamma_lut->data;
+	if (gamma_lut) {
+		const struct drm_color_lut *lut = gamma_lut->data;
 
 		for (i = 0; i < lut_size; i++) {
 			uint32_t word =
@@ -461,10 +466,11 @@ static void bdw_load_gamma_lut(struct intel_crtc_state *crtc_state, u32 offset)
 }
 
 /* Loads the palette/gamma unit for the CRTC on Broadwell+. */
-static void broadwell_load_luts(struct intel_crtc_state *crtc_state)
+static void broadwell_load_luts(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
-	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
 
 	if (crtc_state_is_legacy_gamma(crtc_state)) {
 		haswell_load_luts(crtc_state);
@@ -484,10 +490,11 @@ static void broadwell_load_luts(struct intel_crtc_state *crtc_state)
 	I915_WRITE(PREC_PAL_INDEX(pipe), 0);
 }
 
-static void glk_load_degamma_lut(struct intel_crtc_state *crtc_state)
+static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
-	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
 	const uint32_t lut_size = 33;
 	uint32_t i;
 
@@ -514,11 +521,11 @@ static void glk_load_degamma_lut(struct intel_crtc_state *crtc_state)
 		I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16));
 }
 
-static void glk_load_luts(struct intel_crtc_state *crtc_state)
+static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_device *dev = crtc_state->base.crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
 
 	glk_load_degamma_lut(crtc_state);
 
@@ -532,28 +539,29 @@ static void glk_load_luts(struct intel_crtc_state *crtc_state)
 	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
 }
 
-/* Loads the palette/gamma unit for the CRTC on CherryView. */
-static void cherryview_load_luts(struct intel_crtc_state *crtc_state)
+static void cherryview_load_luts(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_crtc *crtc = crtc_state->base.crtc;
-	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
-	enum pipe pipe = to_intel_crtc(crtc)->pipe;
-	struct drm_color_lut *lut;
-	uint32_t i, lut_size;
-	uint32_t word0, word1;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
+	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
+	enum pipe pipe = crtc->pipe;
 
 	if (crtc_state_is_legacy_gamma(crtc_state)) {
 		/* Turn off degamma/gamma on CGM block. */
 		I915_WRITE(CGM_PIPE_MODE(pipe),
 			   (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0));
-		i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
+		i9xx_load_luts_internal(crtc_state, gamma_lut);
 		return;
 	}
 
-	if (crtc_state->base.degamma_lut) {
-		lut = crtc_state->base.degamma_lut->data;
-		lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
+	if (degamma_lut) {
+		const struct drm_color_lut *lut = degamma_lut->data;
+		int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
+
 		for (i = 0; i < lut_size; i++) {
+			u32 word0, word1;
+
 			/* Write LUT in U0.14 format. */
 			word0 =
 			(drm_color_lut_extract(lut[i].green, 14) << 16) |
@@ -565,10 +573,13 @@ static void cherryview_load_luts(struct intel_crtc_state *crtc_state)
 		}
 	}
 
-	if (crtc_state->base.gamma_lut) {
-		lut = crtc_state->base.gamma_lut->data;
-		lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	if (gamma_lut) {
+		const struct drm_color_lut *lut = gamma_lut->data;
+		int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+
 		for (i = 0; i < lut_size; i++) {
+			u32 word0, word1;
+
 			/* Write LUT in U0.10 format. */
 			word0 =
 			(drm_color_lut_extract(lut[i].green, 10) << 16) |
@@ -582,8 +593,8 @@ static void cherryview_load_luts(struct intel_crtc_state *crtc_state)
 
 	I915_WRITE(CGM_PIPE_MODE(pipe),
 		   (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0) |
-		   (crtc_state->base.degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
-		   (crtc_state->base.gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
+		   (degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
+		   (gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
 
 	/*
 	 * Also program a linear LUT in the legacy block (behind the
@@ -592,10 +603,9 @@ static void cherryview_load_luts(struct intel_crtc_state *crtc_state)
 	i9xx_load_luts_internal(crtc_state, NULL);
 }
 
-void intel_color_load_luts(struct intel_crtc_state *crtc_state)
+void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_device *dev = crtc_state->base.crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 
 	dev_priv->display.load_luts(crtc_state);
 }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 88ac42b2d7ed..96743f50b13a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2338,8 +2338,8 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 /* intel_color.c */
 void intel_color_init(struct intel_crtc *crtc);
 int intel_color_check(struct intel_crtc_state *crtc_state);
-void intel_color_set_csc(struct intel_crtc_state *crtc_state);
-void intel_color_load_luts(struct intel_crtc_state *crtc_state);
+void intel_color_set_csc(const struct intel_crtc_state *crtc_state);
+void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
 
 /* intel_lspcon.c */
 bool lspcon_init(struct intel_digital_port *intel_dig_port);
-- 
2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 52+ messages in thread

* Re: [PATCH 04/13] drm/i915: Constify the state arguments to the color management stuff
  2019-01-11 17:08 ` [PATCH 04/13] drm/i915: Constify the state arguments to the color management stuff Ville Syrjala
@ 2019-01-12  0:42   ` Matt Roper
  2019-01-16 17:21     ` Shankar, Uma
  0 siblings, 1 reply; 52+ messages in thread
From: Matt Roper @ 2019-01-12  0:42 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Jan 11, 2019 at 07:08:14PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Pass the crtc state etc. as const to the color management commit
> functions. And while at it polish some of the local variables.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h    |   4 +-
>  drivers/gpu/drm/i915/intel_color.c | 128 ++++++++++++++++-------------
>  drivers/gpu/drm/i915/intel_drv.h   |   4 +-
>  3 files changed, 73 insertions(+), 63 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5df26ccda8a4..7182a580002c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -320,8 +320,8 @@ struct drm_i915_display_funcs {
>  	/* display clock increase/decrease */
>  	/* pll clock increase/decrease */
>  
> -	void (*load_csc_matrix)(struct intel_crtc_state *crtc_state);
> -	void (*load_luts)(struct intel_crtc_state *crtc_state);
> +	void (*load_csc_matrix)(const struct intel_crtc_state *crtc_state);
> +	void (*load_luts)(const struct intel_crtc_state *crtc_state);
>  };
>  
>  #define CSR_VERSION(major, minor)	((major) << 16 | (minor))
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index b10e66ce3970..0dfd104b89d7 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -74,12 +74,12 @@
>  #define ILK_CSC_COEFF_1_0		\
>  	((7 << 12) | ILK_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
>  
> -static bool lut_is_legacy(struct drm_property_blob *lut)
> +static bool lut_is_legacy(const struct drm_property_blob *lut)
>  {
>  	return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
>  }
>  
> -static bool crtc_state_is_legacy_gamma(struct intel_crtc_state *crtc_state)
> +static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state)
>  {
>  	return !crtc_state->base.degamma_lut &&
>  		!crtc_state->base.ctm &&
> @@ -115,8 +115,8 @@ static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
>  
>  static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
>  {
> -	int pipe = crtc->pipe;
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum pipe pipe = crtc->pipe;
>  
>  	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
>  	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
> @@ -137,13 +137,14 @@ static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
>  	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
>  }
>  
> -static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
> +static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	int i, pipe = crtc->pipe;
> -	uint16_t coeffs[9] = { 0, };
>  	bool limited_color_range = false;
> +	enum pipe pipe = crtc->pipe;
> +	u16 coeffs[9] = {};
> +	int i;
>  
>  	/*
>  	 * FIXME if there's a gamma LUT after the CSC, we should
> @@ -256,15 +257,15 @@ static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
>  /*
>   * Set up the pipe CSC unit on CherryView.
>   */
> -static void cherryview_load_csc_matrix(struct intel_crtc_state *crtc_state)
> +static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_device *dev = crtc_state->base.crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -	int pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum pipe pipe = crtc->pipe;
>  	uint32_t mode;
>  
>  	if (crtc_state->base.ctm) {
> -		struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
> +		const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
>  		uint16_t coeffs[9] = { 0, };
>  		int i;
>  
> @@ -303,18 +304,17 @@ static void cherryview_load_csc_matrix(struct intel_crtc_state *crtc_state)
>  	I915_WRITE(CGM_PIPE_MODE(pipe), mode);
>  }
>  
> -void intel_color_set_csc(struct intel_crtc_state *crtc_state)
> +void intel_color_set_csc(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_device *dev = crtc_state->base.crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>  
>  	if (dev_priv->display.load_csc_matrix)
>  		dev_priv->display.load_csc_matrix(crtc_state);
>  }
>  
>  /* Loads the legacy palette/gamma unit for the CRTC. */
> -static void i9xx_load_luts_internal(struct intel_crtc_state *crtc_state,
> -				    struct drm_property_blob *blob)
> +static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
> +				    const struct drm_property_blob *blob)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -329,7 +329,8 @@ static void i9xx_load_luts_internal(struct intel_crtc_state *crtc_state,
>  	}
>  
>  	if (blob) {
> -		struct drm_color_lut *lut = blob->data;
> +		const struct drm_color_lut *lut = blob->data;
> +
>  		for (i = 0; i < 256; i++) {
>  			uint32_t word =
>  				(drm_color_lut_extract(lut[i].red, 8) << 16) |
> @@ -353,13 +354,13 @@ static void i9xx_load_luts_internal(struct intel_crtc_state *crtc_state,
>  	}
>  }
>  
> -static void i9xx_load_luts(struct intel_crtc_state *crtc_state)
> +static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
>  {
>  	i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
>  }
>  
>  /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
> -static void haswell_load_luts(struct intel_crtc_state *crtc_state)
> +static void haswell_load_luts(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -383,17 +384,19 @@ static void haswell_load_luts(struct intel_crtc_state *crtc_state)
>  		hsw_enable_ips(crtc_state);
>  }
>  
> -static void bdw_load_degamma_lut(struct intel_crtc_state *crtc_state)
> +static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> -	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
>  	uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> +	enum pipe pipe = crtc->pipe;
>  
>  	I915_WRITE(PREC_PAL_INDEX(pipe),
>  		   PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
>  
> -	if (crtc_state->base.degamma_lut) {
> -		struct drm_color_lut *lut = crtc_state->base.degamma_lut->data;
> +	if (degamma_lut) {
> +		const struct drm_color_lut *lut = degamma_lut->data;
>  
>  		for (i = 0; i < lut_size; i++) {
>  			uint32_t word =
> @@ -413,11 +416,13 @@ static void bdw_load_degamma_lut(struct intel_crtc_state *crtc_state)
>  	}
>  }
>  
> -static void bdw_load_gamma_lut(struct intel_crtc_state *crtc_state, u32 offset)
> +static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 offset)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> -	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
>  	uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> +	enum pipe pipe = crtc->pipe;
>  
>  	WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
>  
> @@ -426,8 +431,8 @@ static void bdw_load_gamma_lut(struct intel_crtc_state *crtc_state, u32 offset)
>  		   PAL_PREC_AUTO_INCREMENT |
>  		   offset);
>  
> -	if (crtc_state->base.gamma_lut) {
> -		struct drm_color_lut *lut = crtc_state->base.gamma_lut->data;
> +	if (gamma_lut) {
> +		const struct drm_color_lut *lut = gamma_lut->data;
>  
>  		for (i = 0; i < lut_size; i++) {
>  			uint32_t word =
> @@ -461,10 +466,11 @@ static void bdw_load_gamma_lut(struct intel_crtc_state *crtc_state, u32 offset)
>  }
>  
>  /* Loads the palette/gamma unit for the CRTC on Broadwell+. */
> -static void broadwell_load_luts(struct intel_crtc_state *crtc_state)
> +static void broadwell_load_luts(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> -	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum pipe pipe = crtc->pipe;
>  
>  	if (crtc_state_is_legacy_gamma(crtc_state)) {
>  		haswell_load_luts(crtc_state);
> @@ -484,10 +490,11 @@ static void broadwell_load_luts(struct intel_crtc_state *crtc_state)
>  	I915_WRITE(PREC_PAL_INDEX(pipe), 0);
>  }
>  
> -static void glk_load_degamma_lut(struct intel_crtc_state *crtc_state)
> +static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> -	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum pipe pipe = crtc->pipe;
>  	const uint32_t lut_size = 33;
>  	uint32_t i;
>  
> @@ -514,11 +521,11 @@ static void glk_load_degamma_lut(struct intel_crtc_state *crtc_state)
>  		I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16));
>  }
>  
> -static void glk_load_luts(struct intel_crtc_state *crtc_state)
> +static void glk_load_luts(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_device *dev = crtc_state->base.crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum pipe pipe = crtc->pipe;
>  
>  	glk_load_degamma_lut(crtc_state);
>  
> @@ -532,28 +539,29 @@ static void glk_load_luts(struct intel_crtc_state *crtc_state)
>  	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
>  }
>  
> -/* Loads the palette/gamma unit for the CRTC on CherryView. */
> -static void cherryview_load_luts(struct intel_crtc_state *crtc_state)
> +static void cherryview_load_luts(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_crtc *crtc = crtc_state->base.crtc;
> -	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> -	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> -	struct drm_color_lut *lut;
> -	uint32_t i, lut_size;
> -	uint32_t word0, word1;
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> +	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
> +	enum pipe pipe = crtc->pipe;
>  
>  	if (crtc_state_is_legacy_gamma(crtc_state)) {
>  		/* Turn off degamma/gamma on CGM block. */
>  		I915_WRITE(CGM_PIPE_MODE(pipe),
>  			   (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0));
> -		i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
> +		i9xx_load_luts_internal(crtc_state, gamma_lut);
>  		return;
>  	}
>  
> -	if (crtc_state->base.degamma_lut) {
> -		lut = crtc_state->base.degamma_lut->data;
> -		lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> +	if (degamma_lut) {
> +		const struct drm_color_lut *lut = degamma_lut->data;
> +		int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> +
>  		for (i = 0; i < lut_size; i++) {
> +			u32 word0, word1;
> +
>  			/* Write LUT in U0.14 format. */
>  			word0 =
>  			(drm_color_lut_extract(lut[i].green, 14) << 16) |
> @@ -565,10 +573,13 @@ static void cherryview_load_luts(struct intel_crtc_state *crtc_state)
>  		}
>  	}
>  
> -	if (crtc_state->base.gamma_lut) {
> -		lut = crtc_state->base.gamma_lut->data;
> -		lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> +	if (gamma_lut) {
> +		const struct drm_color_lut *lut = gamma_lut->data;
> +		int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> +
>  		for (i = 0; i < lut_size; i++) {
> +			u32 word0, word1;
> +
>  			/* Write LUT in U0.10 format. */
>  			word0 =
>  			(drm_color_lut_extract(lut[i].green, 10) << 16) |
> @@ -582,8 +593,8 @@ static void cherryview_load_luts(struct intel_crtc_state *crtc_state)
>  
>  	I915_WRITE(CGM_PIPE_MODE(pipe),
>  		   (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0) |
> -		   (crtc_state->base.degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
> -		   (crtc_state->base.gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
> +		   (degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
> +		   (gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
>  
>  	/*
>  	 * Also program a linear LUT in the legacy block (behind the
> @@ -592,10 +603,9 @@ static void cherryview_load_luts(struct intel_crtc_state *crtc_state)
>  	i9xx_load_luts_internal(crtc_state, NULL);
>  }
>  
> -void intel_color_load_luts(struct intel_crtc_state *crtc_state)
> +void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_device *dev = crtc_state->base.crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>  
>  	dev_priv->display.load_luts(crtc_state);
>  }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 88ac42b2d7ed..96743f50b13a 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2338,8 +2338,8 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
>  /* intel_color.c */
>  void intel_color_init(struct intel_crtc *crtc);
>  int intel_color_check(struct intel_crtc_state *crtc_state);
> -void intel_color_set_csc(struct intel_crtc_state *crtc_state);
> -void intel_color_load_luts(struct intel_crtc_state *crtc_state);
> +void intel_color_set_csc(const struct intel_crtc_state *crtc_state);
> +void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
>  
>  /* intel_lspcon.c */
>  bool lspcon_init(struct intel_digital_port *intel_dig_port);
> -- 
> 2.19.2
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 04/13] drm/i915: Constify the state arguments to the color management stuff
  2019-01-12  0:42   ` Matt Roper
@ 2019-01-16 17:21     ` Shankar, Uma
  0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-01-16 17:21 UTC (permalink / raw)
  To: Roper, Matthew D, Ville Syrjala; +Cc: intel-gfx



>-----Original Message-----
>From: Roper, Matthew D
>Sent: Saturday, January 12, 2019 6:12 AM
>To: Ville Syrjala <ville.syrjala@linux.intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>
>Subject: Re: [PATCH 04/13] drm/i915: Constify the state arguments to the color
>management stuff
>
>On Fri, Jan 11, 2019 at 07:08:14PM +0200, Ville Syrjala wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Pass the crtc state etc. as const to the color management commit
>> functions. And while at it polish some of the local variables.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>> ---
>>  drivers/gpu/drm/i915/i915_drv.h    |   4 +-
>>  drivers/gpu/drm/i915/intel_color.c | 128 ++++++++++++++++-------------
>>  drivers/gpu/drm/i915/intel_drv.h   |   4 +-
>>  3 files changed, 73 insertions(+), 63 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h index 5df26ccda8a4..7182a580002c
>> 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -320,8 +320,8 @@ struct drm_i915_display_funcs {
>>  	/* display clock increase/decrease */
>>  	/* pll clock increase/decrease */
>>
>> -	void (*load_csc_matrix)(struct intel_crtc_state *crtc_state);
>> -	void (*load_luts)(struct intel_crtc_state *crtc_state);
>> +	void (*load_csc_matrix)(const struct intel_crtc_state *crtc_state);
>> +	void (*load_luts)(const struct intel_crtc_state *crtc_state);
>>  };
>>
>>  #define CSR_VERSION(major, minor)	((major) << 16 | (minor))
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index b10e66ce3970..0dfd104b89d7 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -74,12 +74,12 @@
>>  #define ILK_CSC_COEFF_1_0		\
>>  	((7 << 12) | ILK_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
>>
>> -static bool lut_is_legacy(struct drm_property_blob *lut)
>> +static bool lut_is_legacy(const struct drm_property_blob *lut)
>>  {
>>  	return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;  }
>>
>> -static bool crtc_state_is_legacy_gamma(struct intel_crtc_state
>> *crtc_state)
>> +static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state
>> +*crtc_state)
>>  {
>>  	return !crtc_state->base.degamma_lut &&
>>  		!crtc_state->base.ctm &&
>> @@ -115,8 +115,8 @@ static u64 *ctm_mult_by_limited(u64 *result, const
>> u64 *input)
>>
>>  static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
>> {
>> -	int pipe = crtc->pipe;
>>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> +	enum pipe pipe = crtc->pipe;
>>
>>  	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
>>  	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); @@ -137,13 +137,14 @@
>> static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
>>  	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
>>  }
>>
>> -static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
>> +static void ilk_load_csc_matrix(const struct intel_crtc_state
>> +*crtc_state)
>>  {
>>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> -	int i, pipe = crtc->pipe;
>> -	uint16_t coeffs[9] = { 0, };
>>  	bool limited_color_range = false;
>> +	enum pipe pipe = crtc->pipe;
>> +	u16 coeffs[9] = {};
>> +	int i;
>>
>>  	/*
>>  	 * FIXME if there's a gamma LUT after the CSC, we should @@ -256,15
>> +257,15 @@ static void ilk_load_csc_matrix(struct intel_crtc_state
>> *crtc_state)
>>  /*
>>   * Set up the pipe CSC unit on CherryView.
>>   */
>> -static void cherryview_load_csc_matrix(struct intel_crtc_state
>> *crtc_state)
>> +static void cherryview_load_csc_matrix(const struct intel_crtc_state
>> +*crtc_state)
>>  {
>> -	struct drm_device *dev = crtc_state->base.crtc->dev;
>> -	struct drm_i915_private *dev_priv = to_i915(dev);
>> -	int pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> +	enum pipe pipe = crtc->pipe;
>>  	uint32_t mode;
>>
>>  	if (crtc_state->base.ctm) {
>> -		struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
>> +		const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
>>  		uint16_t coeffs[9] = { 0, };
>>  		int i;
>>
>> @@ -303,18 +304,17 @@ static void cherryview_load_csc_matrix(struct
>intel_crtc_state *crtc_state)
>>  	I915_WRITE(CGM_PIPE_MODE(pipe), mode);  }
>>
>> -void intel_color_set_csc(struct intel_crtc_state *crtc_state)
>> +void intel_color_set_csc(const struct intel_crtc_state *crtc_state)
>>  {
>> -	struct drm_device *dev = crtc_state->base.crtc->dev;
>> -	struct drm_i915_private *dev_priv = to_i915(dev);
>> +	struct drm_i915_private *dev_priv =
>> +to_i915(crtc_state->base.crtc->dev);
>>
>>  	if (dev_priv->display.load_csc_matrix)
>>  		dev_priv->display.load_csc_matrix(crtc_state);
>>  }
>>
>>  /* Loads the legacy palette/gamma unit for the CRTC. */ -static void
>> i9xx_load_luts_internal(struct intel_crtc_state *crtc_state,
>> -				    struct drm_property_blob *blob)
>> +static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
>> +				    const struct drm_property_blob *blob)
>>  {
>>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@
>> -329,7 +329,8 @@ static void i9xx_load_luts_internal(struct intel_crtc_state
>*crtc_state,
>>  	}
>>
>>  	if (blob) {
>> -		struct drm_color_lut *lut = blob->data;
>> +		const struct drm_color_lut *lut = blob->data;
>> +
>>  		for (i = 0; i < 256; i++) {
>>  			uint32_t word =
>>  				(drm_color_lut_extract(lut[i].red, 8) << 16) |
>@@ -353,13 +354,13
>> @@ static void i9xx_load_luts_internal(struct intel_crtc_state *crtc_state,
>>  	}
>>  }
>>
>> -static void i9xx_load_luts(struct intel_crtc_state *crtc_state)
>> +static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
>>  {
>>  	i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);  }
>>
>>  /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
>> -static void haswell_load_luts(struct intel_crtc_state *crtc_state)
>> +static void haswell_load_luts(const struct intel_crtc_state
>> +*crtc_state)
>>  {
>>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@
>> -383,17 +384,19 @@ static void haswell_load_luts(struct intel_crtc_state
>*crtc_state)
>>  		hsw_enable_ips(crtc_state);
>>  }
>>
>> -static void bdw_load_degamma_lut(struct intel_crtc_state *crtc_state)
>> +static void bdw_load_degamma_lut(const struct intel_crtc_state
>> +*crtc_state)
>>  {
>> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>> -	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> +	const struct drm_property_blob *degamma_lut =
>> +crtc_state->base.degamma_lut;
>>  	uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>> +	enum pipe pipe = crtc->pipe;
>>
>>  	I915_WRITE(PREC_PAL_INDEX(pipe),
>>  		   PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
>>
>> -	if (crtc_state->base.degamma_lut) {
>> -		struct drm_color_lut *lut = crtc_state->base.degamma_lut-
>>data;
>> +	if (degamma_lut) {
>> +		const struct drm_color_lut *lut = degamma_lut->data;
>>
>>  		for (i = 0; i < lut_size; i++) {
>>  			uint32_t word =
>> @@ -413,11 +416,13 @@ static void bdw_load_degamma_lut(struct
>intel_crtc_state *crtc_state)
>>  	}
>>  }
>>
>> -static void bdw_load_gamma_lut(struct intel_crtc_state *crtc_state,
>> u32 offset)
>> +static void bdw_load_gamma_lut(const struct intel_crtc_state
>> +*crtc_state, u32 offset)
>>  {
>> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>> -	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> +	const struct drm_property_blob *gamma_lut =
>> +crtc_state->base.gamma_lut;
>>  	uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>> +	enum pipe pipe = crtc->pipe;
>>
>>  	WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
>>
>> @@ -426,8 +431,8 @@ static void bdw_load_gamma_lut(struct
>intel_crtc_state *crtc_state, u32 offset)
>>  		   PAL_PREC_AUTO_INCREMENT |
>>  		   offset);
>>
>> -	if (crtc_state->base.gamma_lut) {
>> -		struct drm_color_lut *lut = crtc_state->base.gamma_lut->data;
>> +	if (gamma_lut) {
>> +		const struct drm_color_lut *lut = gamma_lut->data;
>>
>>  		for (i = 0; i < lut_size; i++) {
>>  			uint32_t word =
>> @@ -461,10 +466,11 @@ static void bdw_load_gamma_lut(struct
>> intel_crtc_state *crtc_state, u32 offset)  }
>>
>>  /* Loads the palette/gamma unit for the CRTC on Broadwell+. */
>> -static void broadwell_load_luts(struct intel_crtc_state *crtc_state)
>> +static void broadwell_load_luts(const struct intel_crtc_state
>> +*crtc_state)
>>  {
>> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>> -	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> +	enum pipe pipe = crtc->pipe;
>>
>>  	if (crtc_state_is_legacy_gamma(crtc_state)) {
>>  		haswell_load_luts(crtc_state);
>> @@ -484,10 +490,11 @@ static void broadwell_load_luts(struct
>intel_crtc_state *crtc_state)
>>  	I915_WRITE(PREC_PAL_INDEX(pipe), 0);  }
>>
>> -static void glk_load_degamma_lut(struct intel_crtc_state *crtc_state)
>> +static void glk_load_degamma_lut(const struct intel_crtc_state
>> +*crtc_state)
>>  {
>> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>> -	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> +	enum pipe pipe = crtc->pipe;
>>  	const uint32_t lut_size = 33;
>>  	uint32_t i;
>>
>> @@ -514,11 +521,11 @@ static void glk_load_degamma_lut(struct
>intel_crtc_state *crtc_state)
>>  		I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16));  }
>>
>> -static void glk_load_luts(struct intel_crtc_state *crtc_state)
>> +static void glk_load_luts(const struct intel_crtc_state *crtc_state)
>>  {
>> -	struct drm_device *dev = crtc_state->base.crtc->dev;
>> -	struct drm_i915_private *dev_priv = to_i915(dev);
>> -	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> +	enum pipe pipe = crtc->pipe;
>>
>>  	glk_load_degamma_lut(crtc_state);
>>
>> @@ -532,28 +539,29 @@ static void glk_load_luts(struct intel_crtc_state
>*crtc_state)
>>  	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);  }
>>
>> -/* Loads the palette/gamma unit for the CRTC on CherryView. */
>> -static void cherryview_load_luts(struct intel_crtc_state *crtc_state)
>> +static void cherryview_load_luts(const struct intel_crtc_state
>> +*crtc_state)
>>  {
>> -	struct drm_crtc *crtc = crtc_state->base.crtc;
>> -	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>> -	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>> -	struct drm_color_lut *lut;
>> -	uint32_t i, lut_size;
>> -	uint32_t word0, word1;
>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> +	const struct drm_property_blob *gamma_lut = crtc_state-
>>base.gamma_lut;
>> +	const struct drm_property_blob *degamma_lut = crtc_state-
>>base.degamma_lut;
>> +	enum pipe pipe = crtc->pipe;
>>
>>  	if (crtc_state_is_legacy_gamma(crtc_state)) {
>>  		/* Turn off degamma/gamma on CGM block. */
>>  		I915_WRITE(CGM_PIPE_MODE(pipe),
>>  			   (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0));
>> -		i9xx_load_luts_internal(crtc_state, crtc_state-
>>base.gamma_lut);
>> +		i9xx_load_luts_internal(crtc_state, gamma_lut);
>>  		return;
>>  	}
>>
>> -	if (crtc_state->base.degamma_lut) {
>> -		lut = crtc_state->base.degamma_lut->data;
>> -		lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>> +	if (degamma_lut) {
>> +		const struct drm_color_lut *lut = degamma_lut->data;
>> +		int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>> +
>>  		for (i = 0; i < lut_size; i++) {
>> +			u32 word0, word1;
>> +
>>  			/* Write LUT in U0.14 format. */
>>  			word0 =
>>  			(drm_color_lut_extract(lut[i].green, 14) << 16) | @@ -
>565,10
>> +573,13 @@ static void cherryview_load_luts(struct intel_crtc_state
>*crtc_state)
>>  		}
>>  	}
>>
>> -	if (crtc_state->base.gamma_lut) {
>> -		lut = crtc_state->base.gamma_lut->data;
>> -		lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>> +	if (gamma_lut) {
>> +		const struct drm_color_lut *lut = gamma_lut->data;
>> +		int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>> +
>>  		for (i = 0; i < lut_size; i++) {
>> +			u32 word0, word1;
>> +
>>  			/* Write LUT in U0.10 format. */
>>  			word0 =
>>  			(drm_color_lut_extract(lut[i].green, 10) << 16) | @@ -
>582,8 +593,8
>> @@ static void cherryview_load_luts(struct intel_crtc_state
>> *crtc_state)
>>
>>  	I915_WRITE(CGM_PIPE_MODE(pipe),
>>  		   (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0) |
>> -		   (crtc_state->base.degamma_lut ?
>CGM_PIPE_MODE_DEGAMMA : 0) |
>> -		   (crtc_state->base.gamma_lut ? CGM_PIPE_MODE_GAMMA :
>0));
>> +		   (degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
>> +		   (gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
>>
>>  	/*
>>  	 * Also program a linear LUT in the legacy block (behind the @@
>> -592,10 +603,9 @@ static void cherryview_load_luts(struct intel_crtc_state
>*crtc_state)
>>  	i9xx_load_luts_internal(crtc_state, NULL);  }
>>
>> -void intel_color_load_luts(struct intel_crtc_state *crtc_state)
>> +void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
>>  {
>> -	struct drm_device *dev = crtc_state->base.crtc->dev;
>> -	struct drm_i915_private *dev_priv = to_i915(dev);
>> +	struct drm_i915_private *dev_priv =
>> +to_i915(crtc_state->base.crtc->dev);
>>
>>  	dev_priv->display.load_luts(crtc_state);
>>  }
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>> b/drivers/gpu/drm/i915/intel_drv.h
>> index 88ac42b2d7ed..96743f50b13a 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -2338,8 +2338,8 @@ int intel_plane_atomic_check_with_state(const
>> struct intel_crtc_state *old_crtc_
>>  /* intel_color.c */
>>  void intel_color_init(struct intel_crtc *crtc);  int
>> intel_color_check(struct intel_crtc_state *crtc_state); -void
>> intel_color_set_csc(struct intel_crtc_state *crtc_state); -void
>> intel_color_load_luts(struct intel_crtc_state *crtc_state);
>> +void intel_color_set_csc(const struct intel_crtc_state *crtc_state);
>> +void intel_color_load_luts(const struct intel_crtc_state
>> +*crtc_state);
>>
>>  /* intel_lspcon.c */
>>  bool lspcon_init(struct intel_digital_port *intel_dig_port);
>> --
>> 2.19.2
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>IoTG Platform Enabling & Development
>Intel Corporation
>(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* [PATCH 05/13] drm/i915: Pull GAMMA_MODE write out from haswell_load_luts()
  2019-01-11 17:08 [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8 Ville Syrjala
                   ` (3 preceding siblings ...)
  2019-01-11 17:08 ` [PATCH 04/13] drm/i915: Constify the state arguments to the color management stuff Ville Syrjala
@ 2019-01-11 17:08 ` Ville Syrjala
  2019-01-12  0:57   ` Matt Roper
  2019-01-11 17:08 ` [PATCH 06/13] drm/i915: Split color mgmt based on single vs. double buffered registers Ville Syrjala
                   ` (10 subsequent siblings)
  15 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjala @ 2019-01-11 17:08 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

For bdw+ let's move the GAMMA_MODE write for the legacy LUT
mode into the .load_luts() funciton directly, rather than
relying on haswell_load_luts(). We'll be getting rid of
haswell_load_luts() entirely soon, and it's anyway cleaner
to have the GAMMA_MODE write in a single place.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_color.c | 36 +++++++++++++++++-------------
 1 file changed, 20 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 0dfd104b89d7..df3567686c45 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -473,21 +473,20 @@ static void broadwell_load_luts(const struct intel_crtc_state *crtc_state)
 	enum pipe pipe = crtc->pipe;
 
 	if (crtc_state_is_legacy_gamma(crtc_state)) {
-		haswell_load_luts(crtc_state);
-		return;
-	}
+		i9xx_load_luts(crtc_state);
+	} else {
+		bdw_load_degamma_lut(crtc_state);
+		bdw_load_gamma_lut(crtc_state,
+				   INTEL_INFO(dev_priv)->color.degamma_lut_size);
 
-	bdw_load_degamma_lut(crtc_state);
-	bdw_load_gamma_lut(crtc_state,
-			   INTEL_INFO(dev_priv)->color.degamma_lut_size);
+		/*
+		 * Reset the index, otherwise it prevents the legacy palette to be
+		 * written properly.
+		 */
+		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
+	}
 
 	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
-
-	/*
-	 * Reset the index, otherwise it prevents the legacy palette to be
-	 * written properly.
-	 */
-	I915_WRITE(PREC_PAL_INDEX(pipe), 0);
 }
 
 static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
@@ -530,11 +529,16 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 	glk_load_degamma_lut(crtc_state);
 
 	if (crtc_state_is_legacy_gamma(crtc_state)) {
-		haswell_load_luts(crtc_state);
-		return;
-	}
+		i9xx_load_luts(crtc_state);
+	} else {
+		bdw_load_gamma_lut(crtc_state, 0);
 
-	bdw_load_gamma_lut(crtc_state, 0);
+		/*
+		 * Reset the index, otherwise it prevents the legacy palette to be
+		 * written properly.
+		 */
+		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
+	}
 
 	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
 }
-- 
2.19.2

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 52+ messages in thread

* Re: [PATCH 05/13] drm/i915: Pull GAMMA_MODE write out from haswell_load_luts()
  2019-01-11 17:08 ` [PATCH 05/13] drm/i915: Pull GAMMA_MODE write out from haswell_load_luts() Ville Syrjala
@ 2019-01-12  0:57   ` Matt Roper
  2019-01-16 17:26     ` Shankar, Uma
  0 siblings, 1 reply; 52+ messages in thread
From: Matt Roper @ 2019-01-12  0:57 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Jan 11, 2019 at 07:08:15PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> For bdw+ let's move the GAMMA_MODE write for the legacy LUT
> mode into the .load_luts() funciton directly, rather than
> relying on haswell_load_luts(). We'll be getting rid of
> haswell_load_luts() entirely soon, and it's anyway cleaner
> to have the GAMMA_MODE write in a single place.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_color.c | 36 +++++++++++++++++-------------
>  1 file changed, 20 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 0dfd104b89d7..df3567686c45 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -473,21 +473,20 @@ static void broadwell_load_luts(const struct intel_crtc_state *crtc_state)
>  	enum pipe pipe = crtc->pipe;
>  
>  	if (crtc_state_is_legacy_gamma(crtc_state)) {
> -		haswell_load_luts(crtc_state);
> -		return;
> -	}
> +		i9xx_load_luts(crtc_state);
> +	} else {
> +		bdw_load_degamma_lut(crtc_state);
> +		bdw_load_gamma_lut(crtc_state,
> +				   INTEL_INFO(dev_priv)->color.degamma_lut_size);
>  
> -	bdw_load_degamma_lut(crtc_state);
> -	bdw_load_gamma_lut(crtc_state,
> -			   INTEL_INFO(dev_priv)->color.degamma_lut_size);
> +		/*
> +		 * Reset the index, otherwise it prevents the legacy palette to be
> +		 * written properly.
> +		 */
> +		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
> +	}
>  
>  	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
> -
> -	/*
> -	 * Reset the index, otherwise it prevents the legacy palette to be
> -	 * written properly.
> -	 */
> -	I915_WRITE(PREC_PAL_INDEX(pipe), 0);
>  }
>  
>  static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
> @@ -530,11 +529,16 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
>  	glk_load_degamma_lut(crtc_state);
>  
>  	if (crtc_state_is_legacy_gamma(crtc_state)) {
> -		haswell_load_luts(crtc_state);
> -		return;
> -	}
> +		i9xx_load_luts(crtc_state);
> +	} else {
> +		bdw_load_gamma_lut(crtc_state, 0);
>  
> -	bdw_load_gamma_lut(crtc_state, 0);
> +		/*
> +		 * Reset the index, otherwise it prevents the legacy palette to be
> +		 * written properly.
> +		 */
> +		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
> +	}
>  
>  	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
>  }
> -- 
> 2.19.2
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 05/13] drm/i915: Pull GAMMA_MODE write out from haswell_load_luts()
  2019-01-12  0:57   ` Matt Roper
@ 2019-01-16 17:26     ` Shankar, Uma
  0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-01-16 17:26 UTC (permalink / raw)
  To: Roper, Matthew D, Ville Syrjala; +Cc: intel-gfx



>-----Original Message-----
>From: Roper, Matthew D
>Sent: Saturday, January 12, 2019 6:27 AM
>To: Ville Syrjala <ville.syrjala@linux.intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>
>Subject: Re: [PATCH 05/13] drm/i915: Pull GAMMA_MODE write out from
>haswell_load_luts()
>
>On Fri, Jan 11, 2019 at 07:08:15PM +0200, Ville Syrjala wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> For bdw+ let's move the GAMMA_MODE write for the legacy LUT mode into
>> the .load_luts() funciton directly, rather than relying on
>> haswell_load_luts(). We'll be getting rid of
>> haswell_load_luts() entirely soon, and it's anyway cleaner to have the
>> GAMMA_MODE write in a single place.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>> ---
>>  drivers/gpu/drm/i915/intel_color.c | 36
>> +++++++++++++++++-------------
>>  1 file changed, 20 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index 0dfd104b89d7..df3567686c45 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -473,21 +473,20 @@ static void broadwell_load_luts(const struct
>intel_crtc_state *crtc_state)
>>  	enum pipe pipe = crtc->pipe;
>>
>>  	if (crtc_state_is_legacy_gamma(crtc_state)) {
>> -		haswell_load_luts(crtc_state);
>> -		return;
>> -	}
>> +		i9xx_load_luts(crtc_state);
>> +	} else {
>> +		bdw_load_degamma_lut(crtc_state);
>> +		bdw_load_gamma_lut(crtc_state,
>> +				   INTEL_INFO(dev_priv)-
>>color.degamma_lut_size);
>>
>> -	bdw_load_degamma_lut(crtc_state);
>> -	bdw_load_gamma_lut(crtc_state,
>> -			   INTEL_INFO(dev_priv)->color.degamma_lut_size);
>> +		/*
>> +		 * Reset the index, otherwise it prevents the legacy palette to be
>> +		 * written properly.
>> +		 */
>> +		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
>> +	}
>>
>>  	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
>> -
>> -	/*
>> -	 * Reset the index, otherwise it prevents the legacy palette to be
>> -	 * written properly.
>> -	 */
>> -	I915_WRITE(PREC_PAL_INDEX(pipe), 0);
>>  }
>>
>>  static void glk_load_degamma_lut(const struct intel_crtc_state
>> *crtc_state) @@ -530,11 +529,16 @@ static void glk_load_luts(const struct
>intel_crtc_state *crtc_state)
>>  	glk_load_degamma_lut(crtc_state);
>>
>>  	if (crtc_state_is_legacy_gamma(crtc_state)) {
>> -		haswell_load_luts(crtc_state);
>> -		return;
>> -	}
>> +		i9xx_load_luts(crtc_state);
>> +	} else {
>> +		bdw_load_gamma_lut(crtc_state, 0);
>>
>> -	bdw_load_gamma_lut(crtc_state, 0);
>> +		/*
>> +		 * Reset the index, otherwise it prevents the legacy palette to be
>> +		 * written properly.
>> +		 */
>> +		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
>> +	}
>>
>>  	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);  }
>> --
>> 2.19.2
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>IoTG Platform Enabling & Development
>Intel Corporation
>(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* [PATCH 06/13] drm/i915: Split color mgmt based on single vs. double buffered registers
  2019-01-11 17:08 [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8 Ville Syrjala
                   ` (4 preceding siblings ...)
  2019-01-11 17:08 ` [PATCH 05/13] drm/i915: Pull GAMMA_MODE write out from haswell_load_luts() Ville Syrjala
@ 2019-01-11 17:08 ` Ville Syrjala
  2019-01-15  0:56   ` Matt Roper
  2019-01-11 17:08 ` [PATCH 07/13] drm/i915: Move LUT programming to happen after vblank waits Ville Syrjala
                   ` (9 subsequent siblings)
  15 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjala @ 2019-01-11 17:08 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Split the color managemnt hooks along the single vs. double
buffered registers line. Of the currently progammed registers
GAMMA_MODE and the ilk+ pipe CSC are double buffered, the
LUTS and CHV CGM block are single buffered.

The double buffered register will be programmed during the
normal pipe update with evasion, and also during pipe enable
so that the settings will already be correct when the pipe
starts up before the planes are enabled.

The single buffered registers are currently programmed before
the vblank evade. Which is totally wrong, but we'll correct
that later.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  2 +-
 drivers/gpu/drm/i915/intel_color.c   | 49 +++++++++++++---------------
 drivers/gpu/drm/i915/intel_display.c | 16 +++++----
 drivers/gpu/drm/i915/intel_drv.h     |  2 +-
 4 files changed, 34 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7182a580002c..354858b2019b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -320,7 +320,7 @@ struct drm_i915_display_funcs {
 	/* display clock increase/decrease */
 	/* pll clock increase/decrease */
 
-	void (*load_csc_matrix)(const struct intel_crtc_state *crtc_state);
+	void (*color_commit)(const struct intel_crtc_state *crtc_state);
 	void (*load_luts)(const struct intel_crtc_state *crtc_state);
 };
 
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index df3567686c45..f9e0855162f3 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -304,14 +304,6 @@ static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state
 	I915_WRITE(CGM_PIPE_MODE(pipe), mode);
 }
 
-void intel_color_set_csc(const struct intel_crtc_state *crtc_state)
-{
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
-
-	if (dev_priv->display.load_csc_matrix)
-		dev_priv->display.load_csc_matrix(crtc_state);
-}
-
 /* Loads the legacy palette/gamma unit for the CRTC. */
 static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
 				    const struct drm_property_blob *blob)
@@ -359,6 +351,16 @@ static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
 	i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
 }
 
+static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
+
+	ilk_load_csc_matrix(crtc_state);
+}
+
 /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
 static void haswell_load_luts(const struct intel_crtc_state *crtc_state)
 {
@@ -376,8 +378,6 @@ static void haswell_load_luts(const struct intel_crtc_state *crtc_state)
 		reenable_ips = true;
 	}
 
-	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
-
 	i9xx_load_luts(crtc_state);
 
 	if (reenable_ips)
@@ -485,8 +485,6 @@ static void broadwell_load_luts(const struct intel_crtc_state *crtc_state)
 		 */
 		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
 	}
-
-	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
 }
 
 static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
@@ -539,8 +537,6 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 		 */
 		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
 	}
-
-	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
 }
 
 static void cherryview_load_luts(const struct intel_crtc_state *crtc_state)
@@ -551,10 +547,9 @@ static void cherryview_load_luts(const struct intel_crtc_state *crtc_state)
 	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
 	enum pipe pipe = crtc->pipe;
 
+	cherryview_load_csc_matrix(crtc_state);
+
 	if (crtc_state_is_legacy_gamma(crtc_state)) {
-		/* Turn off degamma/gamma on CGM block. */
-		I915_WRITE(CGM_PIPE_MODE(pipe),
-			   (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0));
 		i9xx_load_luts_internal(crtc_state, gamma_lut);
 		return;
 	}
@@ -595,11 +590,6 @@ static void cherryview_load_luts(const struct intel_crtc_state *crtc_state)
 		}
 	}
 
-	I915_WRITE(CGM_PIPE_MODE(pipe),
-		   (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0) |
-		   (degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
-		   (gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
-
 	/*
 	 * Also program a linear LUT in the legacy block (behind the
 	 * CGM block).
@@ -614,6 +604,14 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
 	dev_priv->display.load_luts(crtc_state);
 }
 
+void intel_color_commit(const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+
+	if (dev_priv->display.color_commit)
+		dev_priv->display.color_commit(crtc_state);
+}
+
 int intel_color_check(struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
@@ -660,18 +658,17 @@ void intel_color_init(struct intel_crtc *crtc)
 	drm_mode_crtc_set_gamma_size(&crtc->base, 256);
 
 	if (IS_CHERRYVIEW(dev_priv)) {
-		dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
 		dev_priv->display.load_luts = cherryview_load_luts;
 	} else if (IS_HASWELL(dev_priv)) {
-		dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
 		dev_priv->display.load_luts = haswell_load_luts;
+		dev_priv->display.color_commit = hsw_color_commit;
 	} else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
 		   IS_BROXTON(dev_priv)) {
-		dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
 		dev_priv->display.load_luts = broadwell_load_luts;
+		dev_priv->display.color_commit = hsw_color_commit;
 	} else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
-		dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
 		dev_priv->display.load_luts = glk_load_luts;
+		dev_priv->display.color_commit = hsw_color_commit;
 	} else {
 		dev_priv->display.load_luts = i9xx_load_luts;
 	}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a3871db4703b..96c78566b8e6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5705,6 +5705,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
 	 * clocks enabled
 	 */
 	intel_color_load_luts(pipe_config);
+	intel_color_commit(pipe_config);
 
 	if (dev_priv->display.initial_watermarks != NULL)
 		dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
@@ -5815,8 +5816,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	haswell_set_pipemisc(pipe_config);
 
-	intel_color_set_csc(pipe_config);
-
 	intel_crtc->active = true;
 
 	/* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
@@ -5835,6 +5834,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 	 * clocks enabled
 	 */
 	intel_color_load_luts(pipe_config);
+	intel_color_commit(pipe_config);
 
 	/*
 	 * Display WA #1153: enable hardware to bypass the alpha math
@@ -6180,8 +6180,6 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	i9xx_set_pipeconf(pipe_config);
 
-	intel_color_set_csc(pipe_config);
-
 	intel_crtc->active = true;
 
 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
@@ -6201,6 +6199,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
 	i9xx_pfit_enable(pipe_config);
 
 	intel_color_load_luts(pipe_config);
+	intel_color_commit(pipe_config);
 
 	dev_priv->display.initial_watermarks(old_intel_state,
 					     pipe_config);
@@ -6257,6 +6256,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
 	i9xx_pfit_enable(pipe_config);
 
 	intel_color_load_luts(pipe_config);
+	intel_color_commit(pipe_config);
 
 	if (dev_priv->display.initial_watermarks != NULL)
 		dev_priv->display.initial_watermarks(old_intel_state,
@@ -13634,10 +13634,8 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
 
 	if (!modeset &&
 	    (intel_cstate->base.color_mgmt_changed ||
-	     intel_cstate->update_pipe)) {
-		intel_color_set_csc(intel_cstate);
+	     intel_cstate->update_pipe))
 		intel_color_load_luts(intel_cstate);
-	}
 
 	/* Perform vblank evasion around commit operation */
 	intel_pipe_update_start(intel_cstate);
@@ -13645,6 +13643,10 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
 	if (modeset)
 		goto out;
 
+	if (intel_cstate->base.color_mgmt_changed ||
+	    intel_cstate->update_pipe)
+		intel_color_commit(intel_cstate);
+
 	if (intel_cstate->update_pipe)
 		intel_update_pipe_config(old_intel_cstate, intel_cstate);
 	else if (INTEL_GEN(dev_priv) >= 9)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 96743f50b13a..59f8d4270e82 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2338,7 +2338,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 /* intel_color.c */
 void intel_color_init(struct intel_crtc *crtc);
 int intel_color_check(struct intel_crtc_state *crtc_state);
-void intel_color_set_csc(const struct intel_crtc_state *crtc_state);
+void intel_color_commit(const struct intel_crtc_state *crtc_state);
 void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
 
 /* intel_lspcon.c */
-- 
2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 52+ messages in thread

* Re: [PATCH 06/13] drm/i915: Split color mgmt based on single vs. double buffered registers
  2019-01-11 17:08 ` [PATCH 06/13] drm/i915: Split color mgmt based on single vs. double buffered registers Ville Syrjala
@ 2019-01-15  0:56   ` Matt Roper
  2019-01-16 18:22     ` Shankar, Uma
  0 siblings, 1 reply; 52+ messages in thread
From: Matt Roper @ 2019-01-15  0:56 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Jan 11, 2019 at 07:08:16PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Split the color managemnt hooks along the single vs. double
> buffered registers line. Of the currently progammed registers
> GAMMA_MODE and the ilk+ pipe CSC are double buffered, the
> LUTS and CHV CGM block are single buffered.
> 
> The double buffered register will be programmed during the
> normal pipe update with evasion, and also during pipe enable
> so that the settings will already be correct when the pipe
> starts up before the planes are enabled.
> 
> The single buffered registers are currently programmed before
> the vblank evade. Which is totally wrong, but we'll correct
> that later.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  2 +-
>  drivers/gpu/drm/i915/intel_color.c   | 49 +++++++++++++---------------
>  drivers/gpu/drm/i915/intel_display.c | 16 +++++----
>  drivers/gpu/drm/i915/intel_drv.h     |  2 +-
>  4 files changed, 34 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7182a580002c..354858b2019b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -320,7 +320,7 @@ struct drm_i915_display_funcs {
>  	/* display clock increase/decrease */
>  	/* pll clock increase/decrease */
>  
> -	void (*load_csc_matrix)(const struct intel_crtc_state *crtc_state);
> +	void (*color_commit)(const struct intel_crtc_state *crtc_state);
>  	void (*load_luts)(const struct intel_crtc_state *crtc_state);

Logic-wise this patch looks good, but we should probably add some
kerneldoc to these to make it clear that color_commit() is programming
anything that's expected to take effect at the vblank, and load_luts()
takes effect immediately when called.


>  };
>  
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index df3567686c45..f9e0855162f3 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -304,14 +304,6 @@ static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state
>  	I915_WRITE(CGM_PIPE_MODE(pipe), mode);
>  }
>  
> -void intel_color_set_csc(const struct intel_crtc_state *crtc_state)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> -
> -	if (dev_priv->display.load_csc_matrix)
> -		dev_priv->display.load_csc_matrix(crtc_state);
> -}
> -
>  /* Loads the legacy palette/gamma unit for the CRTC. */
>  static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
>  				    const struct drm_property_blob *blob)
> @@ -359,6 +351,16 @@ static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
>  	i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
>  }
>  
> +static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +
> +	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
> +
> +	ilk_load_csc_matrix(crtc_state);
> +}
> +
>  /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
>  static void haswell_load_luts(const struct intel_crtc_state *crtc_state)
>  {
> @@ -376,8 +378,6 @@ static void haswell_load_luts(const struct intel_crtc_state *crtc_state)
>  		reenable_ips = true;
>  	}
>  
> -	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
> -
>  	i9xx_load_luts(crtc_state);
>  
>  	if (reenable_ips)
> @@ -485,8 +485,6 @@ static void broadwell_load_luts(const struct intel_crtc_state *crtc_state)
>  		 */
>  		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
>  	}
> -
> -	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
>  }
>  
>  static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
> @@ -539,8 +537,6 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
>  		 */
>  		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
>  	}
> -
> -	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
>  }
>  
>  static void cherryview_load_luts(const struct intel_crtc_state *crtc_state)
> @@ -551,10 +547,9 @@ static void cherryview_load_luts(const struct intel_crtc_state *crtc_state)
>  	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
>  	enum pipe pipe = crtc->pipe;
>  
> +	cherryview_load_csc_matrix(crtc_state);
> +

Might be worth adding a comment here to note that CHV's CSC is
single-buffered since this is different from our other platforms and
doesn't seem to be spelled out anywhere in the bspec that I can find
either.


Matt

>  	if (crtc_state_is_legacy_gamma(crtc_state)) {
> -		/* Turn off degamma/gamma on CGM block. */
> -		I915_WRITE(CGM_PIPE_MODE(pipe),
> -			   (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0));
>  		i9xx_load_luts_internal(crtc_state, gamma_lut);
>  		return;
>  	}
> @@ -595,11 +590,6 @@ static void cherryview_load_luts(const struct intel_crtc_state *crtc_state)
>  		}
>  	}
>  
> -	I915_WRITE(CGM_PIPE_MODE(pipe),
> -		   (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0) |
> -		   (degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
> -		   (gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
> -
>  	/*
>  	 * Also program a linear LUT in the legacy block (behind the
>  	 * CGM block).
> @@ -614,6 +604,14 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
>  	dev_priv->display.load_luts(crtc_state);
>  }
>  
> +void intel_color_commit(const struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +
> +	if (dev_priv->display.color_commit)
> +		dev_priv->display.color_commit(crtc_state);
> +}
> +
>  int intel_color_check(struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> @@ -660,18 +658,17 @@ void intel_color_init(struct intel_crtc *crtc)
>  	drm_mode_crtc_set_gamma_size(&crtc->base, 256);
>  
>  	if (IS_CHERRYVIEW(dev_priv)) {
> -		dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
>  		dev_priv->display.load_luts = cherryview_load_luts;
>  	} else if (IS_HASWELL(dev_priv)) {
> -		dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
>  		dev_priv->display.load_luts = haswell_load_luts;
> +		dev_priv->display.color_commit = hsw_color_commit;
>  	} else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
>  		   IS_BROXTON(dev_priv)) {
> -		dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
>  		dev_priv->display.load_luts = broadwell_load_luts;
> +		dev_priv->display.color_commit = hsw_color_commit;
>  	} else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> -		dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
>  		dev_priv->display.load_luts = glk_load_luts;
> +		dev_priv->display.color_commit = hsw_color_commit;
>  	} else {
>  		dev_priv->display.load_luts = i9xx_load_luts;
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a3871db4703b..96c78566b8e6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5705,6 +5705,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
>  	 * clocks enabled
>  	 */
>  	intel_color_load_luts(pipe_config);
> +	intel_color_commit(pipe_config);
>  
>  	if (dev_priv->display.initial_watermarks != NULL)
>  		dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
> @@ -5815,8 +5816,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>  
>  	haswell_set_pipemisc(pipe_config);
>  
> -	intel_color_set_csc(pipe_config);
> -
>  	intel_crtc->active = true;
>  
>  	/* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
> @@ -5835,6 +5834,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>  	 * clocks enabled
>  	 */
>  	intel_color_load_luts(pipe_config);
> +	intel_color_commit(pipe_config);
>  
>  	/*
>  	 * Display WA #1153: enable hardware to bypass the alpha math
> @@ -6180,8 +6180,6 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>  
>  	i9xx_set_pipeconf(pipe_config);
>  
> -	intel_color_set_csc(pipe_config);
> -
>  	intel_crtc->active = true;
>  
>  	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> @@ -6201,6 +6199,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>  	i9xx_pfit_enable(pipe_config);
>  
>  	intel_color_load_luts(pipe_config);
> +	intel_color_commit(pipe_config);
>  
>  	dev_priv->display.initial_watermarks(old_intel_state,
>  					     pipe_config);
> @@ -6257,6 +6256,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
>  	i9xx_pfit_enable(pipe_config);
>  
>  	intel_color_load_luts(pipe_config);
> +	intel_color_commit(pipe_config);
>  
>  	if (dev_priv->display.initial_watermarks != NULL)
>  		dev_priv->display.initial_watermarks(old_intel_state,
> @@ -13634,10 +13634,8 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
>  
>  	if (!modeset &&
>  	    (intel_cstate->base.color_mgmt_changed ||
> -	     intel_cstate->update_pipe)) {
> -		intel_color_set_csc(intel_cstate);
> +	     intel_cstate->update_pipe))
>  		intel_color_load_luts(intel_cstate);
> -	}
>  
>  	/* Perform vblank evasion around commit operation */
>  	intel_pipe_update_start(intel_cstate);
> @@ -13645,6 +13643,10 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
>  	if (modeset)
>  		goto out;
>  
> +	if (intel_cstate->base.color_mgmt_changed ||
> +	    intel_cstate->update_pipe)
> +		intel_color_commit(intel_cstate);
> +
>  	if (intel_cstate->update_pipe)
>  		intel_update_pipe_config(old_intel_cstate, intel_cstate);
>  	else if (INTEL_GEN(dev_priv) >= 9)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 96743f50b13a..59f8d4270e82 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2338,7 +2338,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
>  /* intel_color.c */
>  void intel_color_init(struct intel_crtc *crtc);
>  int intel_color_check(struct intel_crtc_state *crtc_state);
> -void intel_color_set_csc(const struct intel_crtc_state *crtc_state);
> +void intel_color_commit(const struct intel_crtc_state *crtc_state);
>  void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
>  
>  /* intel_lspcon.c */
> -- 
> 2.19.2
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 06/13] drm/i915: Split color mgmt based on single vs. double buffered registers
  2019-01-15  0:56   ` Matt Roper
@ 2019-01-16 18:22     ` Shankar, Uma
  0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-01-16 18:22 UTC (permalink / raw)
  To: Roper, Matthew D, Ville Syrjala; +Cc: intel-gfx



>-----Original Message-----
>From: Roper, Matthew D
>Sent: Tuesday, January 15, 2019 6:27 AM
>To: Ville Syrjala <ville.syrjala@linux.intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>
>Subject: Re: [PATCH 06/13] drm/i915: Split color mgmt based on single vs. double
>buffered registers
>
>On Fri, Jan 11, 2019 at 07:08:16PM +0200, Ville Syrjala wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Split the color managemnt hooks along the single vs. double buffered

Typo in management.

>> registers line. Of the currently progammed registers GAMMA_MODE and

Typo in programmed.

>> the ilk+ pipe CSC are double buffered, the LUTS and CHV CGM block are
>> single buffered.
>>
>> The double buffered register will be programmed during the normal pipe
>> update with evasion, and also during pipe enable so that the settings
>> will already be correct when the pipe starts up before the planes are
>> enabled.
>>
>> The single buffered registers are currently programmed before the
>> vblank evade. Which is totally wrong, but we'll correct that later.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h      |  2 +-
>>  drivers/gpu/drm/i915/intel_color.c   | 49 +++++++++++++---------------
>>  drivers/gpu/drm/i915/intel_display.c | 16 +++++----
>>  drivers/gpu/drm/i915/intel_drv.h     |  2 +-
>>  4 files changed, 34 insertions(+), 35 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h index 7182a580002c..354858b2019b
>> 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -320,7 +320,7 @@ struct drm_i915_display_funcs {
>>  	/* display clock increase/decrease */
>>  	/* pll clock increase/decrease */
>>
>> -	void (*load_csc_matrix)(const struct intel_crtc_state *crtc_state);
>> +	void (*color_commit)(const struct intel_crtc_state *crtc_state);
>>  	void (*load_luts)(const struct intel_crtc_state *crtc_state);
>
>Logic-wise this patch looks good, but we should probably add some kerneldoc to
>these to make it clear that color_commit() is programming anything that's
>expected to take effect at the vblank, and load_luts() takes effect immediately
>when called.

This documentation or some comments in the function description in code will
definitely help. 

>
>>  };
>>
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index df3567686c45..f9e0855162f3 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -304,14 +304,6 @@ static void cherryview_load_csc_matrix(const struct
>intel_crtc_state *crtc_state
>>  	I915_WRITE(CGM_PIPE_MODE(pipe), mode);  }
>>
>> -void intel_color_set_csc(const struct intel_crtc_state *crtc_state)
>> -{
>> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>> -
>> -	if (dev_priv->display.load_csc_matrix)
>> -		dev_priv->display.load_csc_matrix(crtc_state);
>> -}
>> -
>>  /* Loads the legacy palette/gamma unit for the CRTC. */  static void
>> i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
>>  				    const struct drm_property_blob *blob) @@ -
>359,6 +351,16 @@
>> static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
>>  	i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);  }
>>
>> +static void hsw_color_commit(const struct intel_crtc_state
>> +*crtc_state) {
>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> +
>> +	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
>> +
>> +	ilk_load_csc_matrix(crtc_state);

One issue which I see here is that we are mixing programming of csc and gamma mode
in a common function. There may be situations where we don't want either a csc or
gamma to be enabled. Also more so since the respective blocks are implemented as
separate properties. Not sure if this will cause any real issue though.

>> +}
>> +
>>  /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
>> static void haswell_load_luts(const struct intel_crtc_state
>> *crtc_state)  { @@ -376,8 +378,6 @@ static void
>> haswell_load_luts(const struct intel_crtc_state *crtc_state)
>>  		reenable_ips = true;
>>  	}
>>
>> -	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
>> -
>>  	i9xx_load_luts(crtc_state);
>>
>>  	if (reenable_ips)
>> @@ -485,8 +485,6 @@ static void broadwell_load_luts(const struct
>intel_crtc_state *crtc_state)
>>  		 */
>>  		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
>>  	}
>> -
>> -	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
>>  }
>>
>>  static void glk_load_degamma_lut(const struct intel_crtc_state
>> *crtc_state) @@ -539,8 +537,6 @@ static void glk_load_luts(const struct
>intel_crtc_state *crtc_state)
>>  		 */
>>  		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
>>  	}
>> -
>> -	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
>>  }
>>
>>  static void cherryview_load_luts(const struct intel_crtc_state
>> *crtc_state) @@ -551,10 +547,9 @@ static void cherryview_load_luts(const
>struct intel_crtc_state *crtc_state)
>>  	const struct drm_property_blob *degamma_lut = crtc_state-
>>base.degamma_lut;
>>  	enum pipe pipe = crtc->pipe;
>>
>> +	cherryview_load_csc_matrix(crtc_state);
>> +
>
>Might be worth adding a comment here to note that CHV's CSC is single-buffered
>since this is different from our other platforms and doesn't seem to be spelled out
>anywhere in the bspec that I can find either.
>
>
>Matt
>
>>  	if (crtc_state_is_legacy_gamma(crtc_state)) {
>> -		/* Turn off degamma/gamma on CGM block. */
>> -		I915_WRITE(CGM_PIPE_MODE(pipe),
>> -			   (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0));
>>  		i9xx_load_luts_internal(crtc_state, gamma_lut);
>>  		return;
>>  	}
>> @@ -595,11 +590,6 @@ static void cherryview_load_luts(const struct
>intel_crtc_state *crtc_state)
>>  		}
>>  	}
>>
>> -	I915_WRITE(CGM_PIPE_MODE(pipe),
>> -		   (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0) |
>> -		   (degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
>> -		   (gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
>> -
>>  	/*
>>  	 * Also program a linear LUT in the legacy block (behind the
>>  	 * CGM block).
>> @@ -614,6 +604,14 @@ void intel_color_load_luts(const struct
>intel_crtc_state *crtc_state)
>>  	dev_priv->display.load_luts(crtc_state);
>>  }
>>
>> +void intel_color_commit(const struct intel_crtc_state *crtc_state) {
>> +	struct drm_i915_private *dev_priv =
>> +to_i915(crtc_state->base.crtc->dev);
>> +
>> +	if (dev_priv->display.color_commit)
>> +		dev_priv->display.color_commit(crtc_state);
>> +}
>> +
>>  int intel_color_check(struct intel_crtc_state *crtc_state)  {
>>  	struct drm_i915_private *dev_priv =
>> to_i915(crtc_state->base.crtc->dev);
>> @@ -660,18 +658,17 @@ void intel_color_init(struct intel_crtc *crtc)
>>  	drm_mode_crtc_set_gamma_size(&crtc->base, 256);
>>
>>  	if (IS_CHERRYVIEW(dev_priv)) {
>> -		dev_priv->display.load_csc_matrix =
>cherryview_load_csc_matrix;
>>  		dev_priv->display.load_luts = cherryview_load_luts;
>>  	} else if (IS_HASWELL(dev_priv)) {
>> -		dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
>>  		dev_priv->display.load_luts = haswell_load_luts;
>> +		dev_priv->display.color_commit = hsw_color_commit;
>>  	} else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
>>  		   IS_BROXTON(dev_priv)) {
>> -		dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
>>  		dev_priv->display.load_luts = broadwell_load_luts;
>> +		dev_priv->display.color_commit = hsw_color_commit;
>>  	} else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>> -		dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
>>  		dev_priv->display.load_luts = glk_load_luts;
>> +		dev_priv->display.color_commit = hsw_color_commit;
>>  	} else {
>>  		dev_priv->display.load_luts = i9xx_load_luts;
>>  	}
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index a3871db4703b..96c78566b8e6 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -5705,6 +5705,7 @@ static void ironlake_crtc_enable(struct
>intel_crtc_state *pipe_config,
>>  	 * clocks enabled
>>  	 */
>>  	intel_color_load_luts(pipe_config);
>> +	intel_color_commit(pipe_config);
>>
>>  	if (dev_priv->display.initial_watermarks != NULL)
>>  		dev_priv->display.initial_watermarks(old_intel_state,
>pipe_config);
>> @@ -5815,8 +5816,6 @@ static void haswell_crtc_enable(struct
>> intel_crtc_state *pipe_config,
>>
>>  	haswell_set_pipemisc(pipe_config);
>>
>> -	intel_color_set_csc(pipe_config);
>> -
>>  	intel_crtc->active = true;
>>
>>  	/* Display WA #1180: WaDisableScalarClockGating: glk, cnl */ @@
>> -5835,6 +5834,7 @@ static void haswell_crtc_enable(struct intel_crtc_state
>*pipe_config,
>>  	 * clocks enabled
>>  	 */
>>  	intel_color_load_luts(pipe_config);
>> +	intel_color_commit(pipe_config);
>>
>>  	/*
>>  	 * Display WA #1153: enable hardware to bypass the alpha math @@
>> -6180,8 +6180,6 @@ static void valleyview_crtc_enable(struct
>> intel_crtc_state *pipe_config,
>>
>>  	i9xx_set_pipeconf(pipe_config);
>>
>> -	intel_color_set_csc(pipe_config);
>> -
>>  	intel_crtc->active = true;
>>
>>  	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); @@
>> -6201,6 +6199,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state
>*pipe_config,
>>  	i9xx_pfit_enable(pipe_config);
>>
>>  	intel_color_load_luts(pipe_config);
>> +	intel_color_commit(pipe_config);
>>
>>  	dev_priv->display.initial_watermarks(old_intel_state,
>>  					     pipe_config);
>> @@ -6257,6 +6256,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state
>*pipe_config,
>>  	i9xx_pfit_enable(pipe_config);
>>
>>  	intel_color_load_luts(pipe_config);
>> +	intel_color_commit(pipe_config);
>>
>>  	if (dev_priv->display.initial_watermarks != NULL)
>>  		dev_priv->display.initial_watermarks(old_intel_state,
>> @@ -13634,10 +13634,8 @@ static void intel_begin_crtc_commit(struct
>> drm_crtc *crtc,
>>
>>  	if (!modeset &&
>>  	    (intel_cstate->base.color_mgmt_changed ||
>> -	     intel_cstate->update_pipe)) {
>> -		intel_color_set_csc(intel_cstate);
>> +	     intel_cstate->update_pipe))
>>  		intel_color_load_luts(intel_cstate);
>> -	}
>>
>>  	/* Perform vblank evasion around commit operation */
>>  	intel_pipe_update_start(intel_cstate);
>> @@ -13645,6 +13643,10 @@ static void intel_begin_crtc_commit(struct
>drm_crtc *crtc,
>>  	if (modeset)
>>  		goto out;
>>
>> +	if (intel_cstate->base.color_mgmt_changed ||
>> +	    intel_cstate->update_pipe)
>> +		intel_color_commit(intel_cstate);
>> +
>>  	if (intel_cstate->update_pipe)
>>  		intel_update_pipe_config(old_intel_cstate, intel_cstate);
>>  	else if (INTEL_GEN(dev_priv) >= 9)
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>> b/drivers/gpu/drm/i915/intel_drv.h
>> index 96743f50b13a..59f8d4270e82 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -2338,7 +2338,7 @@ int intel_plane_atomic_check_with_state(const
>> struct intel_crtc_state *old_crtc_
>>  /* intel_color.c */
>>  void intel_color_init(struct intel_crtc *crtc);  int
>> intel_color_check(struct intel_crtc_state *crtc_state); -void
>> intel_color_set_csc(const struct intel_crtc_state *crtc_state);
>> +void intel_color_commit(const struct intel_crtc_state *crtc_state);
>>  void intel_color_load_luts(const struct intel_crtc_state
>> *crtc_state);
>>
>>  /* intel_lspcon.c */
>> --
>> 2.19.2
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>IoTG Platform Enabling & Development
>Intel Corporation
>(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* [PATCH 07/13] drm/i915: Move LUT programming to happen after vblank waits
  2019-01-11 17:08 [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8 Ville Syrjala
                   ` (5 preceding siblings ...)
  2019-01-11 17:08 ` [PATCH 06/13] drm/i915: Split color mgmt based on single vs. double buffered registers Ville Syrjala
@ 2019-01-11 17:08 ` Ville Syrjala
  2019-01-16 17:38   ` Matt Roper
  2019-01-11 17:08 ` [PATCH 08/13] drm/i915: Populate gamma_mode for all platforms Ville Syrjala
                   ` (8 subsequent siblings)
  15 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjala @ 2019-01-11 17:08 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The LUTs are single buffered so we should program them after
the double buffered pipe updates have been latched by the
hardware.

We'll also fix up the IPS vs. split gamma w/a to do the IPS
disable like everyone else. Note that this is currently dead
code as we don't use the split gamma mode on HSW, but that
will be fixed up shortly.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_color.c   | 25 +--------------
 drivers/gpu/drm/i915/intel_display.c | 47 ++++++++++++++++++++++++----
 2 files changed, 42 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index f9e0855162f3..0c0da7ed0fd7 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -361,29 +361,6 @@ static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
 	ilk_load_csc_matrix(crtc_state);
 }
 
-/* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
-static void haswell_load_luts(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	bool reenable_ips = false;
-
-	/*
-	 * Workaround : Do not read or write the pipe palette/gamma data while
-	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
-	 */
-	if (IS_HASWELL(dev_priv) && crtc_state->ips_enabled &&
-	    (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
-		hsw_disable_ips(crtc_state);
-		reenable_ips = true;
-	}
-
-	i9xx_load_luts(crtc_state);
-
-	if (reenable_ips)
-		hsw_enable_ips(crtc_state);
-}
-
 static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -660,7 +637,7 @@ void intel_color_init(struct intel_crtc *crtc)
 	if (IS_CHERRYVIEW(dev_priv)) {
 		dev_priv->display.load_luts = cherryview_load_luts;
 	} else if (IS_HASWELL(dev_priv)) {
-		dev_priv->display.load_luts = haswell_load_luts;
+		dev_priv->display.load_luts = i9xx_load_luts;
 		dev_priv->display.color_commit = hsw_color_commit;
 	} else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
 		   IS_BROXTON(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 96c78566b8e6..1caee4128974 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5299,24 +5299,54 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
 				       const struct intel_crtc_state *new_crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
 	if (!old_crtc_state->ips_enabled)
 		return false;
 
 	if (needs_modeset(&new_crtc_state->base))
 		return true;
 
+	/*
+	 * Workaround : Do not read or write the pipe palette/gamma data while
+	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
+	 *
+	 * Disable IPS before we program the LUT.
+	 */
+	if (IS_HASWELL(dev_priv) &&
+	    (new_crtc_state->base.color_mgmt_changed ||
+	     new_crtc_state->update_pipe) &&
+	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
+		return true;
+
 	return !new_crtc_state->ips_enabled;
 }
 
 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
 				       const struct intel_crtc_state *new_crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
 	if (!new_crtc_state->ips_enabled)
 		return false;
 
 	if (needs_modeset(&new_crtc_state->base))
 		return true;
 
+	/*
+	 * Workaround : Do not read or write the pipe palette/gamma data while
+	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
+	 *
+	 * Re-enable IPS after the LUT has been programmed.
+	 */
+	if (IS_HASWELL(dev_priv) &&
+	    (new_crtc_state->base.color_mgmt_changed ||
+	     new_crtc_state->update_pipe) &&
+	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
+		return true;
+
 	/*
 	 * We can't read out IPS on broadwell, assume the worst and
 	 * forcibly enable IPS on the first fastset.
@@ -11050,7 +11080,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
 			return ret;
 	}
 
-	if (crtc_state->color_mgmt_changed) {
+	if (mode_changed || crtc_state->color_mgmt_changed) {
 		ret = intel_color_check(pipe_config);
 		if (ret)
 			return ret;
@@ -13117,6 +13147,16 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
 	 */
 	drm_atomic_helper_wait_for_flip_done(dev, state);
 
+	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
+		new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
+
+		if (new_crtc_state->active &&
+		    !needs_modeset(new_crtc_state) &&
+		    (new_intel_crtc_state->base.color_mgmt_changed ||
+		     new_intel_crtc_state->update_pipe))
+			intel_color_load_luts(new_intel_crtc_state);
+	}
+
 	/*
 	 * Now that the vblank has passed, we can go ahead and program the
 	 * optimal watermarks on platforms that need two-step watermark
@@ -13632,11 +13672,6 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
 		intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
 	bool modeset = needs_modeset(&intel_cstate->base);
 
-	if (!modeset &&
-	    (intel_cstate->base.color_mgmt_changed ||
-	     intel_cstate->update_pipe))
-		intel_color_load_luts(intel_cstate);
-
 	/* Perform vblank evasion around commit operation */
 	intel_pipe_update_start(intel_cstate);
 
-- 
2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 52+ messages in thread

* Re: [PATCH 07/13] drm/i915: Move LUT programming to happen after vblank waits
  2019-01-11 17:08 ` [PATCH 07/13] drm/i915: Move LUT programming to happen after vblank waits Ville Syrjala
@ 2019-01-16 17:38   ` Matt Roper
  2019-01-16 18:02     ` Ville Syrjälä
  2019-01-17 15:00     ` Ville Syrjälä
  0 siblings, 2 replies; 52+ messages in thread
From: Matt Roper @ 2019-01-16 17:38 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Jan 11, 2019 at 07:08:17PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The LUTs are single buffered so we should program them after
> the double buffered pipe updates have been latched by the
> hardware.
> 
> We'll also fix up the IPS vs. split gamma w/a to do the IPS
> disable like everyone else. Note that this is currently dead
> code as we don't use the split gamma mode on HSW, but that
> will be fixed up shortly.

I don't think this is quite dead code...we don't use split gamma
ourselves, but we could potentially inherit that setup from the BIOS
(which will stick around until it eventually gets clobbered by the first
modeset/fastset).

Uma's series added some logic to sanitize the LUT's immediately on boot,
but that hasn't landed yet.


> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_color.c   | 25 +--------------
>  drivers/gpu/drm/i915/intel_display.c | 47 ++++++++++++++++++++++++----
>  2 files changed, 42 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index f9e0855162f3..0c0da7ed0fd7 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -361,29 +361,6 @@ static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
>  	ilk_load_csc_matrix(crtc_state);
>  }
>  
> -/* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
> -static void haswell_load_luts(const struct intel_crtc_state *crtc_state)
> -{
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	bool reenable_ips = false;
> -
> -	/*
> -	 * Workaround : Do not read or write the pipe palette/gamma data while
> -	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
> -	 */
> -	if (IS_HASWELL(dev_priv) && crtc_state->ips_enabled &&
> -	    (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
> -		hsw_disable_ips(crtc_state);
> -		reenable_ips = true;
> -	}
> -
> -	i9xx_load_luts(crtc_state);
> -
> -	if (reenable_ips)
> -		hsw_enable_ips(crtc_state);
> -}
> -
>  static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> @@ -660,7 +637,7 @@ void intel_color_init(struct intel_crtc *crtc)
>  	if (IS_CHERRYVIEW(dev_priv)) {
>  		dev_priv->display.load_luts = cherryview_load_luts;
>  	} else if (IS_HASWELL(dev_priv)) {
> -		dev_priv->display.load_luts = haswell_load_luts;
> +		dev_priv->display.load_luts = i9xx_load_luts;
>  		dev_priv->display.color_commit = hsw_color_commit;
>  	} else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
>  		   IS_BROXTON(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 96c78566b8e6..1caee4128974 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5299,24 +5299,54 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
>  static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
>  				       const struct intel_crtc_state *new_crtc_state)
>  {
> +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +
>  	if (!old_crtc_state->ips_enabled)
>  		return false;
>  
>  	if (needs_modeset(&new_crtc_state->base))
>  		return true;
>  
> +	/*
> +	 * Workaround : Do not read or write the pipe palette/gamma data while
> +	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
> +	 *
> +	 * Disable IPS before we program the LUT.
> +	 */
> +	if (IS_HASWELL(dev_priv) &&
> +	    (new_crtc_state->base.color_mgmt_changed ||
> +	     new_crtc_state->update_pipe) &&
> +	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)

Wouldn't we want old_crtc_state for the gamma_mode test?  We need to
disable IPS if we're already in split gamma mode (inherited from BIOS),
regardless of whether we're moving to non-split gamma.


Matt

> +		return true;
> +
>  	return !new_crtc_state->ips_enabled;
>  }
>  
>  static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
>  				       const struct intel_crtc_state *new_crtc_state)
>  {
> +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +
>  	if (!new_crtc_state->ips_enabled)
>  		return false;
>  
>  	if (needs_modeset(&new_crtc_state->base))
>  		return true;
>  
> +	/*
> +	 * Workaround : Do not read or write the pipe palette/gamma data while
> +	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
> +	 *
> +	 * Re-enable IPS after the LUT has been programmed.
> +	 */
> +	if (IS_HASWELL(dev_priv) &&
> +	    (new_crtc_state->base.color_mgmt_changed ||
> +	     new_crtc_state->update_pipe) &&
> +	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
> +		return true;
> +
>  	/*
>  	 * We can't read out IPS on broadwell, assume the worst and
>  	 * forcibly enable IPS on the first fastset.
> @@ -11050,7 +11080,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
>  			return ret;
>  	}
>  
> -	if (crtc_state->color_mgmt_changed) {
> +	if (mode_changed || crtc_state->color_mgmt_changed) {
>  		ret = intel_color_check(pipe_config);
>  		if (ret)
>  			return ret;
> @@ -13117,6 +13147,16 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
>  	 */
>  	drm_atomic_helper_wait_for_flip_done(dev, state);
>  
> +	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
> +		new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
> +
> +		if (new_crtc_state->active &&
> +		    !needs_modeset(new_crtc_state) &&
> +		    (new_intel_crtc_state->base.color_mgmt_changed ||
> +		     new_intel_crtc_state->update_pipe))
> +			intel_color_load_luts(new_intel_crtc_state);
> +	}
> +
>  	/*
>  	 * Now that the vblank has passed, we can go ahead and program the
>  	 * optimal watermarks on platforms that need two-step watermark
> @@ -13632,11 +13672,6 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
>  		intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
>  	bool modeset = needs_modeset(&intel_cstate->base);
>  
> -	if (!modeset &&
> -	    (intel_cstate->base.color_mgmt_changed ||
> -	     intel_cstate->update_pipe))
> -		intel_color_load_luts(intel_cstate);
> -
>  	/* Perform vblank evasion around commit operation */
>  	intel_pipe_update_start(intel_cstate);
>  
> -- 
> 2.19.2
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 07/13] drm/i915: Move LUT programming to happen after vblank waits
  2019-01-16 17:38   ` Matt Roper
@ 2019-01-16 18:02     ` Ville Syrjälä
  2019-01-17 15:00     ` Ville Syrjälä
  1 sibling, 0 replies; 52+ messages in thread
From: Ville Syrjälä @ 2019-01-16 18:02 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Wed, Jan 16, 2019 at 09:38:59AM -0800, Matt Roper wrote:
> On Fri, Jan 11, 2019 at 07:08:17PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The LUTs are single buffered so we should program them after
> > the double buffered pipe updates have been latched by the
> > hardware.
> > 
> > We'll also fix up the IPS vs. split gamma w/a to do the IPS
> > disable like everyone else. Note that this is currently dead
> > code as we don't use the split gamma mode on HSW, but that
> > will be fixed up shortly.
> 
> I don't think this is quite dead code...we don't use split gamma
> ourselves, but we could potentially inherit that setup from the BIOS
> (which will stick around until it eventually gets clobbered by the first
> modeset/fastset).
> 
> Uma's series added some logic to sanitize the LUT's immediately on boot,
> but that hasn't landed yet.
> 
> 
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_color.c   | 25 +--------------
> >  drivers/gpu/drm/i915/intel_display.c | 47 ++++++++++++++++++++++++----
> >  2 files changed, 42 insertions(+), 30 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> > index f9e0855162f3..0c0da7ed0fd7 100644
> > --- a/drivers/gpu/drm/i915/intel_color.c
> > +++ b/drivers/gpu/drm/i915/intel_color.c
> > @@ -361,29 +361,6 @@ static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
> >  	ilk_load_csc_matrix(crtc_state);
> >  }
> >  
> > -/* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
> > -static void haswell_load_luts(const struct intel_crtc_state *crtc_state)
> > -{
> > -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > -	bool reenable_ips = false;
> > -
> > -	/*
> > -	 * Workaround : Do not read or write the pipe palette/gamma data while
> > -	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
> > -	 */
> > -	if (IS_HASWELL(dev_priv) && crtc_state->ips_enabled &&
> > -	    (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
> > -		hsw_disable_ips(crtc_state);
> > -		reenable_ips = true;
> > -	}
> > -
> > -	i9xx_load_luts(crtc_state);
> > -
> > -	if (reenable_ips)
> > -		hsw_enable_ips(crtc_state);
> > -}
> > -
> >  static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state)
> >  {
> >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > @@ -660,7 +637,7 @@ void intel_color_init(struct intel_crtc *crtc)
> >  	if (IS_CHERRYVIEW(dev_priv)) {
> >  		dev_priv->display.load_luts = cherryview_load_luts;
> >  	} else if (IS_HASWELL(dev_priv)) {
> > -		dev_priv->display.load_luts = haswell_load_luts;
> > +		dev_priv->display.load_luts = i9xx_load_luts;
> >  		dev_priv->display.color_commit = hsw_color_commit;
> >  	} else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
> >  		   IS_BROXTON(dev_priv)) {
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 96c78566b8e6..1caee4128974 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5299,24 +5299,54 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
> >  static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
> >  				       const struct intel_crtc_state *new_crtc_state)
> >  {
> > +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +
> >  	if (!old_crtc_state->ips_enabled)
> >  		return false;
> >  
> >  	if (needs_modeset(&new_crtc_state->base))
> >  		return true;
> >  
> > +	/*
> > +	 * Workaround : Do not read or write the pipe palette/gamma data while
> > +	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
> > +	 *
> > +	 * Disable IPS before we program the LUT.
> > +	 */
> > +	if (IS_HASWELL(dev_priv) &&
> > +	    (new_crtc_state->base.color_mgmt_changed ||
> > +	     new_crtc_state->update_pipe) &&
> > +	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
> 
> Wouldn't we want old_crtc_state for the gamma_mode test?  We need to
> disable IPS if we're already in split gamma mode (inherited from BIOS),
> regardless of whether we're moving to non-split gamma.

We're going to update the gamma mode before programming the LUT.

But I think I'll probably change this to disable IPS around all LUT
updates to prevent IPS from using the old LUT during the vblank. That's
assuming IPS does actually prefill during vblank (which would make sense
to me).


> 
> 
> Matt
> 
> > +		return true;
> > +
> >  	return !new_crtc_state->ips_enabled;
> >  }
> >  
> >  static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
> >  				       const struct intel_crtc_state *new_crtc_state)
> >  {
> > +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +
> >  	if (!new_crtc_state->ips_enabled)
> >  		return false;
> >  
> >  	if (needs_modeset(&new_crtc_state->base))
> >  		return true;
> >  
> > +	/*
> > +	 * Workaround : Do not read or write the pipe palette/gamma data while
> > +	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
> > +	 *
> > +	 * Re-enable IPS after the LUT has been programmed.
> > +	 */
> > +	if (IS_HASWELL(dev_priv) &&
> > +	    (new_crtc_state->base.color_mgmt_changed ||
> > +	     new_crtc_state->update_pipe) &&
> > +	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
> > +		return true;
> > +
> >  	/*
> >  	 * We can't read out IPS on broadwell, assume the worst and
> >  	 * forcibly enable IPS on the first fastset.
> > @@ -11050,7 +11080,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
> >  			return ret;
> >  	}
> >  
> > -	if (crtc_state->color_mgmt_changed) {
> > +	if (mode_changed || crtc_state->color_mgmt_changed) {
> >  		ret = intel_color_check(pipe_config);
> >  		if (ret)
> >  			return ret;
> > @@ -13117,6 +13147,16 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
> >  	 */
> >  	drm_atomic_helper_wait_for_flip_done(dev, state);
> >  
> > +	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
> > +		new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
> > +
> > +		if (new_crtc_state->active &&
> > +		    !needs_modeset(new_crtc_state) &&
> > +		    (new_intel_crtc_state->base.color_mgmt_changed ||
> > +		     new_intel_crtc_state->update_pipe))
> > +			intel_color_load_luts(new_intel_crtc_state);
> > +	}
> > +
> >  	/*
> >  	 * Now that the vblank has passed, we can go ahead and program the
> >  	 * optimal watermarks on platforms that need two-step watermark
> > @@ -13632,11 +13672,6 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
> >  		intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
> >  	bool modeset = needs_modeset(&intel_cstate->base);
> >  
> > -	if (!modeset &&
> > -	    (intel_cstate->base.color_mgmt_changed ||
> > -	     intel_cstate->update_pipe))
> > -		intel_color_load_luts(intel_cstate);
> > -
> >  	/* Perform vblank evasion around commit operation */
> >  	intel_pipe_update_start(intel_cstate);
> >  
> > -- 
> > 2.19.2
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 07/13] drm/i915: Move LUT programming to happen after vblank waits
  2019-01-16 17:38   ` Matt Roper
  2019-01-16 18:02     ` Ville Syrjälä
@ 2019-01-17 15:00     ` Ville Syrjälä
  1 sibling, 0 replies; 52+ messages in thread
From: Ville Syrjälä @ 2019-01-17 15:00 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Wed, Jan 16, 2019 at 09:38:59AM -0800, Matt Roper wrote:
> On Fri, Jan 11, 2019 at 07:08:17PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The LUTs are single buffered so we should program them after
> > the double buffered pipe updates have been latched by the
> > hardware.
> > 
> > We'll also fix up the IPS vs. split gamma w/a to do the IPS
> > disable like everyone else. Note that this is currently dead
> > code as we don't use the split gamma mode on HSW, but that
> > will be fixed up shortly.
> 
> I don't think this is quite dead code...we don't use split gamma
> ourselves, but we could potentially inherit that setup from the BIOS
> (which will stick around until it eventually gets clobbered by the first
> modeset/fastset).
> 
> Uma's series added some logic to sanitize the LUT's immediately on boot,
> but that hasn't landed yet.

With the gamma_enable/csc_enable flags properly tracked we shouldn't
need anything like that. Or am I missing something?

> 
> 
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_color.c   | 25 +--------------
> >  drivers/gpu/drm/i915/intel_display.c | 47 ++++++++++++++++++++++++----
> >  2 files changed, 42 insertions(+), 30 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> > index f9e0855162f3..0c0da7ed0fd7 100644
> > --- a/drivers/gpu/drm/i915/intel_color.c
> > +++ b/drivers/gpu/drm/i915/intel_color.c
> > @@ -361,29 +361,6 @@ static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
> >  	ilk_load_csc_matrix(crtc_state);
> >  }
> >  
> > -/* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
> > -static void haswell_load_luts(const struct intel_crtc_state *crtc_state)
> > -{
> > -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > -	bool reenable_ips = false;
> > -
> > -	/*
> > -	 * Workaround : Do not read or write the pipe palette/gamma data while
> > -	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
> > -	 */
> > -	if (IS_HASWELL(dev_priv) && crtc_state->ips_enabled &&
> > -	    (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
> > -		hsw_disable_ips(crtc_state);
> > -		reenable_ips = true;
> > -	}
> > -
> > -	i9xx_load_luts(crtc_state);
> > -
> > -	if (reenable_ips)
> > -		hsw_enable_ips(crtc_state);
> > -}
> > -
> >  static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state)
> >  {
> >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > @@ -660,7 +637,7 @@ void intel_color_init(struct intel_crtc *crtc)
> >  	if (IS_CHERRYVIEW(dev_priv)) {
> >  		dev_priv->display.load_luts = cherryview_load_luts;
> >  	} else if (IS_HASWELL(dev_priv)) {
> > -		dev_priv->display.load_luts = haswell_load_luts;
> > +		dev_priv->display.load_luts = i9xx_load_luts;
> >  		dev_priv->display.color_commit = hsw_color_commit;
> >  	} else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
> >  		   IS_BROXTON(dev_priv)) {
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 96c78566b8e6..1caee4128974 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5299,24 +5299,54 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
> >  static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
> >  				       const struct intel_crtc_state *new_crtc_state)
> >  {
> > +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +
> >  	if (!old_crtc_state->ips_enabled)
> >  		return false;
> >  
> >  	if (needs_modeset(&new_crtc_state->base))
> >  		return true;
> >  
> > +	/*
> > +	 * Workaround : Do not read or write the pipe palette/gamma data while
> > +	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
> > +	 *
> > +	 * Disable IPS before we program the LUT.
> > +	 */
> > +	if (IS_HASWELL(dev_priv) &&
> > +	    (new_crtc_state->base.color_mgmt_changed ||
> > +	     new_crtc_state->update_pipe) &&
> > +	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
> 
> Wouldn't we want old_crtc_state for the gamma_mode test?  We need to
> disable IPS if we're already in split gamma mode (inherited from BIOS),
> regardless of whether we're moving to non-split gamma.
> 
> 
> Matt
> 
> > +		return true;
> > +
> >  	return !new_crtc_state->ips_enabled;
> >  }
> >  
> >  static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
> >  				       const struct intel_crtc_state *new_crtc_state)
> >  {
> > +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +
> >  	if (!new_crtc_state->ips_enabled)
> >  		return false;
> >  
> >  	if (needs_modeset(&new_crtc_state->base))
> >  		return true;
> >  
> > +	/*
> > +	 * Workaround : Do not read or write the pipe palette/gamma data while
> > +	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
> > +	 *
> > +	 * Re-enable IPS after the LUT has been programmed.
> > +	 */
> > +	if (IS_HASWELL(dev_priv) &&
> > +	    (new_crtc_state->base.color_mgmt_changed ||
> > +	     new_crtc_state->update_pipe) &&
> > +	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
> > +		return true;
> > +
> >  	/*
> >  	 * We can't read out IPS on broadwell, assume the worst and
> >  	 * forcibly enable IPS on the first fastset.
> > @@ -11050,7 +11080,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
> >  			return ret;
> >  	}
> >  
> > -	if (crtc_state->color_mgmt_changed) {
> > +	if (mode_changed || crtc_state->color_mgmt_changed) {
> >  		ret = intel_color_check(pipe_config);
> >  		if (ret)
> >  			return ret;
> > @@ -13117,6 +13147,16 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
> >  	 */
> >  	drm_atomic_helper_wait_for_flip_done(dev, state);
> >  
> > +	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
> > +		new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
> > +
> > +		if (new_crtc_state->active &&
> > +		    !needs_modeset(new_crtc_state) &&
> > +		    (new_intel_crtc_state->base.color_mgmt_changed ||
> > +		     new_intel_crtc_state->update_pipe))
> > +			intel_color_load_luts(new_intel_crtc_state);
> > +	}
> > +
> >  	/*
> >  	 * Now that the vblank has passed, we can go ahead and program the
> >  	 * optimal watermarks on platforms that need two-step watermark
> > @@ -13632,11 +13672,6 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
> >  		intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
> >  	bool modeset = needs_modeset(&intel_cstate->base);
> >  
> > -	if (!modeset &&
> > -	    (intel_cstate->base.color_mgmt_changed ||
> > -	     intel_cstate->update_pipe))
> > -		intel_color_load_luts(intel_cstate);
> > -
> >  	/* Perform vblank evasion around commit operation */
> >  	intel_pipe_update_start(intel_cstate);
> >  
> > -- 
> > 2.19.2
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* [PATCH 08/13] drm/i915: Populate gamma_mode for all platforms
  2019-01-11 17:08 [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8 Ville Syrjala
                   ` (6 preceding siblings ...)
  2019-01-11 17:08 ` [PATCH 07/13] drm/i915: Move LUT programming to happen after vblank waits Ville Syrjala
@ 2019-01-11 17:08 ` Ville Syrjala
  2019-01-16 18:31   ` Matt Roper
  2019-01-11 17:08 ` [PATCH 09/13] drm/i915: Track pipe gamma enable/disable in crtc state Ville Syrjala
                   ` (7 subsequent siblings)
  15 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjala @ 2019-01-11 17:08 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On pre-HSW gamma mode is configured via PIPECONF. The bits are
the same except shifted up, so we can reuse just store them in
crtc_state->gamma_mode in the HSW+ way, allowing us to share
some code later.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 10 ++++-
 drivers/gpu/drm/i915/intel_color.c   | 60 +++++++++++++++++++++-------
 drivers/gpu/drm/i915/intel_display.c | 14 ++++++-
 3 files changed, 66 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 44958d994bfa..9d17ba199be4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5578,9 +5578,15 @@ enum {
 #define   PIPECONF_SINGLE_WIDE	0
 #define   PIPECONF_PIPE_UNLOCKED 0
 #define   PIPECONF_PIPE_LOCKED	(1 << 25)
-#define   PIPECONF_PALETTE	0
-#define   PIPECONF_GAMMA		(1 << 24)
 #define   PIPECONF_FORCE_BORDER	(1 << 25)
+#define   PIPECONF_GAMMA_MODE_MASK_I9XX	(1 << 24) /* gmch */
+#define   PIPECONF_GAMMA_MODE_MASK_ILK	(3 << 24) /* ilk-ivb */
+#define   PIPECONF_GAMMA_MODE_8BIT	(0 << 24) /* gmch,ilk-ivb */
+#define   PIPECONF_GAMMA_MODE_10BIT	(1 << 24) /* gmch,ilk-ivb */
+#define   PIPECONF_GAMMA_MODE_12BIT	(2 << 24) /* ilk-ivb */
+#define   PIPECONF_GAMMA_MODE_SPLIT	(3 << 24) /* ivb */
+#define   PIPECONF_GAMMA_MODE(x)	((x)<<24) /* pass in GAMMA_MODE_MODE_* */
+#define   PIPECONF_GAMMA_MODE_SHIFT	24
 #define   PIPECONF_INTERLACE_MASK	(7 << 21)
 #define   PIPECONF_INTERLACE_MASK_HSW	(3 << 21)
 /* Note that pre-gen3 does not support interlaced display directly. Panel
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 0c0da7ed0fd7..6fdbfa8c4008 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -351,6 +351,32 @@ static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
 	i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
 }
 
+static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+	u32 val;
+
+	val = I915_READ(PIPECONF(pipe));
+	val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX;
+	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
+	I915_WRITE(PIPECONF(pipe), val);
+}
+
+static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+	u32 val;
+
+	val = I915_READ(PIPECONF(pipe));
+	val &= ~PIPECONF_GAMMA_MODE_MASK_ILK;
+	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
+	I915_WRITE(PIPECONF(pipe), val);
+}
+
 static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -585,8 +611,7 @@ void intel_color_commit(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 
-	if (dev_priv->display.color_commit)
-		dev_priv->display.color_commit(crtc_state);
+	dev_priv->display.color_commit(crtc_state);
 }
 
 int intel_color_check(struct intel_crtc_state *crtc_state)
@@ -634,20 +659,25 @@ void intel_color_init(struct intel_crtc *crtc)
 
 	drm_mode_crtc_set_gamma_size(&crtc->base, 256);
 
-	if (IS_CHERRYVIEW(dev_priv)) {
-		dev_priv->display.load_luts = cherryview_load_luts;
-	} else if (IS_HASWELL(dev_priv)) {
-		dev_priv->display.load_luts = i9xx_load_luts;
-		dev_priv->display.color_commit = hsw_color_commit;
-	} else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
-		   IS_BROXTON(dev_priv)) {
-		dev_priv->display.load_luts = broadwell_load_luts;
-		dev_priv->display.color_commit = hsw_color_commit;
-	} else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
-		dev_priv->display.load_luts = glk_load_luts;
-		dev_priv->display.color_commit = hsw_color_commit;
+	if (HAS_GMCH_DISPLAY(dev_priv)) {
+		if (IS_CHERRYVIEW(dev_priv))
+			dev_priv->display.load_luts = cherryview_load_luts;
+		else
+			dev_priv->display.load_luts = i9xx_load_luts;
+
+		dev_priv->display.color_commit = i9xx_color_commit;
 	} else {
-		dev_priv->display.load_luts = i9xx_load_luts;
+		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+			dev_priv->display.load_luts = glk_load_luts;
+		else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
+			dev_priv->display.load_luts = broadwell_load_luts;
+		else
+			dev_priv->display.load_luts = i9xx_load_luts;
+
+		if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
+			dev_priv->display.color_commit = hsw_color_commit;
+		else
+			dev_priv->display.color_commit = ilk_color_commit;
 	}
 
 	/* Enable color management support when we have degamma & gamma LUTs. */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1caee4128974..90afcae91b30 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3415,7 +3415,7 @@ static void i9xx_disable_plane(struct intel_plane *plane,
 	 *
 	 * On pre-g4x there is no way to gamma correct the
 	 * pipe bottom color but we'll keep on doing this
-	 * anyway.
+	 * anyway so that the crtc state readout works correctly.
 	 */
 	dspcntr = i9xx_plane_ctl_crtc(crtc_state);
 
@@ -7627,6 +7627,8 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
 	     crtc_state->limited_color_range)
 		pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
 
+	pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
+
 	I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
 	POSTING_READ(PIPECONF(crtc->pipe));
 }
@@ -8077,6 +8079,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 	    (tmp & PIPECONF_COLOR_RANGE_SELECT))
 		pipe_config->limited_color_range = true;
 
+	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
+		PIPECONF_GAMMA_MODE_SHIFT;
+
 	if (INTEL_GEN(dev_priv) < 4)
 		pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
 
@@ -8616,6 +8621,8 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->limited_color_range)
 		val |= PIPECONF_COLOR_RANGE_SELECT;
 
+	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
+
 	I915_WRITE(PIPECONF(pipe), val);
 	POSTING_READ(PIPECONF(pipe));
 }
@@ -9147,6 +9154,9 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 	if (tmp & PIPECONF_COLOR_RANGE_SELECT)
 		pipe_config->limited_color_range = true;
 
+	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
+		PIPECONF_GAMMA_MODE_SHIFT;
+
 	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
 		struct intel_shared_dpll *pll;
 		enum intel_dpll_id pll_id;
@@ -11977,6 +11987,8 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
 
 	PIPE_CONF_CHECK_BOOL(double_wide);
 
+	PIPE_CONF_CHECK_X(gamma_mode);
+
 	PIPE_CONF_CHECK_P(shared_dpll);
 	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
 	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
-- 
2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 52+ messages in thread

* Re: [PATCH 08/13] drm/i915: Populate gamma_mode for all platforms
  2019-01-11 17:08 ` [PATCH 08/13] drm/i915: Populate gamma_mode for all platforms Ville Syrjala
@ 2019-01-16 18:31   ` Matt Roper
  2019-01-16 18:58     ` Ville Syrjälä
  0 siblings, 1 reply; 52+ messages in thread
From: Matt Roper @ 2019-01-16 18:31 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Jan 11, 2019 at 07:08:18PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On pre-HSW gamma mode is configured via PIPECONF. The bits are
> the same except shifted up, so we can reuse just store them in
> crtc_state->gamma_mode in the HSW+ way, allowing us to share
> some code later.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      | 10 ++++-
>  drivers/gpu/drm/i915/intel_color.c   | 60 +++++++++++++++++++++-------
>  drivers/gpu/drm/i915/intel_display.c | 14 ++++++-
>  3 files changed, 66 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 44958d994bfa..9d17ba199be4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5578,9 +5578,15 @@ enum {
>  #define   PIPECONF_SINGLE_WIDE	0
>  #define   PIPECONF_PIPE_UNLOCKED 0
>  #define   PIPECONF_PIPE_LOCKED	(1 << 25)
> -#define   PIPECONF_PALETTE	0
> -#define   PIPECONF_GAMMA		(1 << 24)
>  #define   PIPECONF_FORCE_BORDER	(1 << 25)
> +#define   PIPECONF_GAMMA_MODE_MASK_I9XX	(1 << 24) /* gmch */
> +#define   PIPECONF_GAMMA_MODE_MASK_ILK	(3 << 24) /* ilk-ivb */
> +#define   PIPECONF_GAMMA_MODE_8BIT	(0 << 24) /* gmch,ilk-ivb */
> +#define   PIPECONF_GAMMA_MODE_10BIT	(1 << 24) /* gmch,ilk-ivb */
> +#define   PIPECONF_GAMMA_MODE_12BIT	(2 << 24) /* ilk-ivb */
> +#define   PIPECONF_GAMMA_MODE_SPLIT	(3 << 24) /* ivb */
> +#define   PIPECONF_GAMMA_MODE(x)	((x)<<24) /* pass in GAMMA_MODE_MODE_* */
> +#define   PIPECONF_GAMMA_MODE_SHIFT	24
>  #define   PIPECONF_INTERLACE_MASK	(7 << 21)
>  #define   PIPECONF_INTERLACE_MASK_HSW	(3 << 21)
>  /* Note that pre-gen3 does not support interlaced display directly. Panel
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 0c0da7ed0fd7..6fdbfa8c4008 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -351,6 +351,32 @@ static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
>  	i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
>  }
>  
> +static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum pipe pipe = crtc->pipe;
> +	u32 val;
> +
> +	val = I915_READ(PIPECONF(pipe));
> +	val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX;
> +	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> +	I915_WRITE(PIPECONF(pipe), val);
> +}
> +
> +static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum pipe pipe = crtc->pipe;
> +	u32 val;
> +
> +	val = I915_READ(PIPECONF(pipe));
> +	val &= ~PIPECONF_GAMMA_MODE_MASK_ILK;
> +	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> +	I915_WRITE(PIPECONF(pipe), val);
> +}

Could we just set color_commit to i9xx_set_pipeconf and
ironlake_set_pipeconf to handle these without the r-m-w?


Matt

> +
>  static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> @@ -585,8 +611,7 @@ void intel_color_commit(const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>  
> -	if (dev_priv->display.color_commit)
> -		dev_priv->display.color_commit(crtc_state);
> +	dev_priv->display.color_commit(crtc_state);
>  }
>  
>  int intel_color_check(struct intel_crtc_state *crtc_state)
> @@ -634,20 +659,25 @@ void intel_color_init(struct intel_crtc *crtc)
>  
>  	drm_mode_crtc_set_gamma_size(&crtc->base, 256);
>  
> -	if (IS_CHERRYVIEW(dev_priv)) {
> -		dev_priv->display.load_luts = cherryview_load_luts;
> -	} else if (IS_HASWELL(dev_priv)) {
> -		dev_priv->display.load_luts = i9xx_load_luts;
> -		dev_priv->display.color_commit = hsw_color_commit;
> -	} else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
> -		   IS_BROXTON(dev_priv)) {
> -		dev_priv->display.load_luts = broadwell_load_luts;
> -		dev_priv->display.color_commit = hsw_color_commit;
> -	} else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> -		dev_priv->display.load_luts = glk_load_luts;
> -		dev_priv->display.color_commit = hsw_color_commit;
> +	if (HAS_GMCH_DISPLAY(dev_priv)) {
> +		if (IS_CHERRYVIEW(dev_priv))
> +			dev_priv->display.load_luts = cherryview_load_luts;
> +		else
> +			dev_priv->display.load_luts = i9xx_load_luts;
> +
> +		dev_priv->display.color_commit = i9xx_color_commit;
>  	} else {
> -		dev_priv->display.load_luts = i9xx_load_luts;
> +		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> +			dev_priv->display.load_luts = glk_load_luts;
> +		else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> +			dev_priv->display.load_luts = broadwell_load_luts;
> +		else
> +			dev_priv->display.load_luts = i9xx_load_luts;
> +
> +		if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
> +			dev_priv->display.color_commit = hsw_color_commit;
> +		else
> +			dev_priv->display.color_commit = ilk_color_commit;
>  	}
>  
>  	/* Enable color management support when we have degamma & gamma LUTs. */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 1caee4128974..90afcae91b30 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3415,7 +3415,7 @@ static void i9xx_disable_plane(struct intel_plane *plane,
>  	 *
>  	 * On pre-g4x there is no way to gamma correct the
>  	 * pipe bottom color but we'll keep on doing this
> -	 * anyway.
> +	 * anyway so that the crtc state readout works correctly.
>  	 */
>  	dspcntr = i9xx_plane_ctl_crtc(crtc_state);
>  
> @@ -7627,6 +7627,8 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
>  	     crtc_state->limited_color_range)
>  		pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
>  
> +	pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> +
>  	I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
>  	POSTING_READ(PIPECONF(crtc->pipe));
>  }
> @@ -8077,6 +8079,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  	    (tmp & PIPECONF_COLOR_RANGE_SELECT))
>  		pipe_config->limited_color_range = true;
>  
> +	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
> +		PIPECONF_GAMMA_MODE_SHIFT;
> +
>  	if (INTEL_GEN(dev_priv) < 4)
>  		pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
>  
> @@ -8616,6 +8621,8 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
>  	if (crtc_state->limited_color_range)
>  		val |= PIPECONF_COLOR_RANGE_SELECT;
>  
> +	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> +
>  	I915_WRITE(PIPECONF(pipe), val);
>  	POSTING_READ(PIPECONF(pipe));
>  }
> @@ -9147,6 +9154,9 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
>  	if (tmp & PIPECONF_COLOR_RANGE_SELECT)
>  		pipe_config->limited_color_range = true;
>  
> +	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
> +		PIPECONF_GAMMA_MODE_SHIFT;
> +
>  	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
>  		struct intel_shared_dpll *pll;
>  		enum intel_dpll_id pll_id;
> @@ -11977,6 +11987,8 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
>  
>  	PIPE_CONF_CHECK_BOOL(double_wide);
>  
> +	PIPE_CONF_CHECK_X(gamma_mode);
> +
>  	PIPE_CONF_CHECK_P(shared_dpll);
>  	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
>  	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
> -- 
> 2.19.2
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 08/13] drm/i915: Populate gamma_mode for all platforms
  2019-01-16 18:31   ` Matt Roper
@ 2019-01-16 18:58     ` Ville Syrjälä
  2019-01-16 19:51       ` Ville Syrjälä
  0 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjälä @ 2019-01-16 18:58 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Wed, Jan 16, 2019 at 10:31:56AM -0800, Matt Roper wrote:
> On Fri, Jan 11, 2019 at 07:08:18PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > On pre-HSW gamma mode is configured via PIPECONF. The bits are
> > the same except shifted up, so we can reuse just store them in
> > crtc_state->gamma_mode in the HSW+ way, allowing us to share
> > some code later.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      | 10 ++++-
> >  drivers/gpu/drm/i915/intel_color.c   | 60 +++++++++++++++++++++-------
> >  drivers/gpu/drm/i915/intel_display.c | 14 ++++++-
> >  3 files changed, 66 insertions(+), 18 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 44958d994bfa..9d17ba199be4 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5578,9 +5578,15 @@ enum {
> >  #define   PIPECONF_SINGLE_WIDE	0
> >  #define   PIPECONF_PIPE_UNLOCKED 0
> >  #define   PIPECONF_PIPE_LOCKED	(1 << 25)
> > -#define   PIPECONF_PALETTE	0
> > -#define   PIPECONF_GAMMA		(1 << 24)
> >  #define   PIPECONF_FORCE_BORDER	(1 << 25)
> > +#define   PIPECONF_GAMMA_MODE_MASK_I9XX	(1 << 24) /* gmch */
> > +#define   PIPECONF_GAMMA_MODE_MASK_ILK	(3 << 24) /* ilk-ivb */
> > +#define   PIPECONF_GAMMA_MODE_8BIT	(0 << 24) /* gmch,ilk-ivb */
> > +#define   PIPECONF_GAMMA_MODE_10BIT	(1 << 24) /* gmch,ilk-ivb */
> > +#define   PIPECONF_GAMMA_MODE_12BIT	(2 << 24) /* ilk-ivb */
> > +#define   PIPECONF_GAMMA_MODE_SPLIT	(3 << 24) /* ivb */
> > +#define   PIPECONF_GAMMA_MODE(x)	((x)<<24) /* pass in GAMMA_MODE_MODE_* */
> > +#define   PIPECONF_GAMMA_MODE_SHIFT	24
> >  #define   PIPECONF_INTERLACE_MASK	(7 << 21)
> >  #define   PIPECONF_INTERLACE_MASK_HSW	(3 << 21)
> >  /* Note that pre-gen3 does not support interlaced display directly. Panel
> > diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> > index 0c0da7ed0fd7..6fdbfa8c4008 100644
> > --- a/drivers/gpu/drm/i915/intel_color.c
> > +++ b/drivers/gpu/drm/i915/intel_color.c
> > @@ -351,6 +351,32 @@ static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
> >  	i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
> >  }
> >  
> > +static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
> > +{
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	enum pipe pipe = crtc->pipe;
> > +	u32 val;
> > +
> > +	val = I915_READ(PIPECONF(pipe));
> > +	val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX;
> > +	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> > +	I915_WRITE(PIPECONF(pipe), val);
> > +}
> > +
> > +static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
> > +{
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	enum pipe pipe = crtc->pipe;
> > +	u32 val;
> > +
> > +	val = I915_READ(PIPECONF(pipe));
> > +	val &= ~PIPECONF_GAMMA_MODE_MASK_ILK;
> > +	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> > +	I915_WRITE(PIPECONF(pipe), val);
> > +}
> 
> Could we just set color_commit to i9xx_set_pipeconf and
> ironlake_set_pipeconf to handle these without the r-m-w?

Perhaps. But not quite sure if we have any magic restrictions
in the crtc enable sequence that would prevent that.

> 
> 
> Matt
> 
> > +
> >  static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
> >  {
> >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > @@ -585,8 +611,7 @@ void intel_color_commit(const struct intel_crtc_state *crtc_state)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> >  
> > -	if (dev_priv->display.color_commit)
> > -		dev_priv->display.color_commit(crtc_state);
> > +	dev_priv->display.color_commit(crtc_state);
> >  }
> >  
> >  int intel_color_check(struct intel_crtc_state *crtc_state)
> > @@ -634,20 +659,25 @@ void intel_color_init(struct intel_crtc *crtc)
> >  
> >  	drm_mode_crtc_set_gamma_size(&crtc->base, 256);
> >  
> > -	if (IS_CHERRYVIEW(dev_priv)) {
> > -		dev_priv->display.load_luts = cherryview_load_luts;
> > -	} else if (IS_HASWELL(dev_priv)) {
> > -		dev_priv->display.load_luts = i9xx_load_luts;
> > -		dev_priv->display.color_commit = hsw_color_commit;
> > -	} else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
> > -		   IS_BROXTON(dev_priv)) {
> > -		dev_priv->display.load_luts = broadwell_load_luts;
> > -		dev_priv->display.color_commit = hsw_color_commit;
> > -	} else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> > -		dev_priv->display.load_luts = glk_load_luts;
> > -		dev_priv->display.color_commit = hsw_color_commit;
> > +	if (HAS_GMCH_DISPLAY(dev_priv)) {
> > +		if (IS_CHERRYVIEW(dev_priv))
> > +			dev_priv->display.load_luts = cherryview_load_luts;
> > +		else
> > +			dev_priv->display.load_luts = i9xx_load_luts;
> > +
> > +		dev_priv->display.color_commit = i9xx_color_commit;
> >  	} else {
> > -		dev_priv->display.load_luts = i9xx_load_luts;
> > +		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> > +			dev_priv->display.load_luts = glk_load_luts;
> > +		else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> > +			dev_priv->display.load_luts = broadwell_load_luts;
> > +		else
> > +			dev_priv->display.load_luts = i9xx_load_luts;
> > +
> > +		if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
> > +			dev_priv->display.color_commit = hsw_color_commit;
> > +		else
> > +			dev_priv->display.color_commit = ilk_color_commit;
> >  	}
> >  
> >  	/* Enable color management support when we have degamma & gamma LUTs. */
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 1caee4128974..90afcae91b30 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3415,7 +3415,7 @@ static void i9xx_disable_plane(struct intel_plane *plane,
> >  	 *
> >  	 * On pre-g4x there is no way to gamma correct the
> >  	 * pipe bottom color but we'll keep on doing this
> > -	 * anyway.
> > +	 * anyway so that the crtc state readout works correctly.
> >  	 */
> >  	dspcntr = i9xx_plane_ctl_crtc(crtc_state);
> >  
> > @@ -7627,6 +7627,8 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
> >  	     crtc_state->limited_color_range)
> >  		pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
> >  
> > +	pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> > +
> >  	I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
> >  	POSTING_READ(PIPECONF(crtc->pipe));
> >  }
> > @@ -8077,6 +8079,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> >  	    (tmp & PIPECONF_COLOR_RANGE_SELECT))
> >  		pipe_config->limited_color_range = true;
> >  
> > +	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
> > +		PIPECONF_GAMMA_MODE_SHIFT;
> > +
> >  	if (INTEL_GEN(dev_priv) < 4)
> >  		pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
> >  
> > @@ -8616,6 +8621,8 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
> >  	if (crtc_state->limited_color_range)
> >  		val |= PIPECONF_COLOR_RANGE_SELECT;
> >  
> > +	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> > +
> >  	I915_WRITE(PIPECONF(pipe), val);
> >  	POSTING_READ(PIPECONF(pipe));
> >  }
> > @@ -9147,6 +9154,9 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
> >  	if (tmp & PIPECONF_COLOR_RANGE_SELECT)
> >  		pipe_config->limited_color_range = true;
> >  
> > +	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
> > +		PIPECONF_GAMMA_MODE_SHIFT;
> > +
> >  	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
> >  		struct intel_shared_dpll *pll;
> >  		enum intel_dpll_id pll_id;
> > @@ -11977,6 +11987,8 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
> >  
> >  	PIPE_CONF_CHECK_BOOL(double_wide);
> >  
> > +	PIPE_CONF_CHECK_X(gamma_mode);
> > +
> >  	PIPE_CONF_CHECK_P(shared_dpll);
> >  	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> >  	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
> > -- 
> > 2.19.2
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 08/13] drm/i915: Populate gamma_mode for all platforms
  2019-01-16 18:58     ` Ville Syrjälä
@ 2019-01-16 19:51       ` Ville Syrjälä
  2019-01-29 15:59         ` Ville Syrjälä
  0 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjälä @ 2019-01-16 19:51 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Wed, Jan 16, 2019 at 08:58:04PM +0200, Ville Syrjälä wrote:
> On Wed, Jan 16, 2019 at 10:31:56AM -0800, Matt Roper wrote:
> > On Fri, Jan 11, 2019 at 07:08:18PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > On pre-HSW gamma mode is configured via PIPECONF. The bits are
> > > the same except shifted up, so we can reuse just store them in
> > > crtc_state->gamma_mode in the HSW+ way, allowing us to share
> > > some code later.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h      | 10 ++++-
> > >  drivers/gpu/drm/i915/intel_color.c   | 60 +++++++++++++++++++++-------
> > >  drivers/gpu/drm/i915/intel_display.c | 14 ++++++-
> > >  3 files changed, 66 insertions(+), 18 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 44958d994bfa..9d17ba199be4 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -5578,9 +5578,15 @@ enum {
> > >  #define   PIPECONF_SINGLE_WIDE	0
> > >  #define   PIPECONF_PIPE_UNLOCKED 0
> > >  #define   PIPECONF_PIPE_LOCKED	(1 << 25)
> > > -#define   PIPECONF_PALETTE	0
> > > -#define   PIPECONF_GAMMA		(1 << 24)
> > >  #define   PIPECONF_FORCE_BORDER	(1 << 25)
> > > +#define   PIPECONF_GAMMA_MODE_MASK_I9XX	(1 << 24) /* gmch */
> > > +#define   PIPECONF_GAMMA_MODE_MASK_ILK	(3 << 24) /* ilk-ivb */
> > > +#define   PIPECONF_GAMMA_MODE_8BIT	(0 << 24) /* gmch,ilk-ivb */
> > > +#define   PIPECONF_GAMMA_MODE_10BIT	(1 << 24) /* gmch,ilk-ivb */
> > > +#define   PIPECONF_GAMMA_MODE_12BIT	(2 << 24) /* ilk-ivb */
> > > +#define   PIPECONF_GAMMA_MODE_SPLIT	(3 << 24) /* ivb */
> > > +#define   PIPECONF_GAMMA_MODE(x)	((x)<<24) /* pass in GAMMA_MODE_MODE_* */
> > > +#define   PIPECONF_GAMMA_MODE_SHIFT	24
> > >  #define   PIPECONF_INTERLACE_MASK	(7 << 21)
> > >  #define   PIPECONF_INTERLACE_MASK_HSW	(3 << 21)
> > >  /* Note that pre-gen3 does not support interlaced display directly. Panel
> > > diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> > > index 0c0da7ed0fd7..6fdbfa8c4008 100644
> > > --- a/drivers/gpu/drm/i915/intel_color.c
> > > +++ b/drivers/gpu/drm/i915/intel_color.c
> > > @@ -351,6 +351,32 @@ static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
> > >  	i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
> > >  }
> > >  
> > > +static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
> > > +{
> > > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > +	enum pipe pipe = crtc->pipe;
> > > +	u32 val;
> > > +
> > > +	val = I915_READ(PIPECONF(pipe));
> > > +	val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX;
> > > +	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> > > +	I915_WRITE(PIPECONF(pipe), val);
> > > +}
> > > +
> > > +static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
> > > +{
> > > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > +	enum pipe pipe = crtc->pipe;
> > > +	u32 val;
> > > +
> > > +	val = I915_READ(PIPECONF(pipe));
> > > +	val &= ~PIPECONF_GAMMA_MODE_MASK_ILK;
> > > +	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> > > +	I915_WRITE(PIPECONF(pipe), val);
> > > +}
> > 
> > Could we just set color_commit to i9xx_set_pipeconf and
> > ironlake_set_pipeconf to handle these without the r-m-w?
> 
> Perhaps. But not quite sure if we have any magic restrictions
> in the crtc enable sequence that would prevent that.

I guess we could always keep the double set_pipeconf() in the
crtc enable path so that we won't have to think whether to move the
color_commit() earlier or the set_pipeconf() later.

> 
> > 
> > 
> > Matt
> > 
> > > +
> > >  static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
> > >  {
> > >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > > @@ -585,8 +611,7 @@ void intel_color_commit(const struct intel_crtc_state *crtc_state)
> > >  {
> > >  	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> > >  
> > > -	if (dev_priv->display.color_commit)
> > > -		dev_priv->display.color_commit(crtc_state);
> > > +	dev_priv->display.color_commit(crtc_state);
> > >  }
> > >  
> > >  int intel_color_check(struct intel_crtc_state *crtc_state)
> > > @@ -634,20 +659,25 @@ void intel_color_init(struct intel_crtc *crtc)
> > >  
> > >  	drm_mode_crtc_set_gamma_size(&crtc->base, 256);
> > >  
> > > -	if (IS_CHERRYVIEW(dev_priv)) {
> > > -		dev_priv->display.load_luts = cherryview_load_luts;
> > > -	} else if (IS_HASWELL(dev_priv)) {
> > > -		dev_priv->display.load_luts = i9xx_load_luts;
> > > -		dev_priv->display.color_commit = hsw_color_commit;
> > > -	} else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
> > > -		   IS_BROXTON(dev_priv)) {
> > > -		dev_priv->display.load_luts = broadwell_load_luts;
> > > -		dev_priv->display.color_commit = hsw_color_commit;
> > > -	} else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> > > -		dev_priv->display.load_luts = glk_load_luts;
> > > -		dev_priv->display.color_commit = hsw_color_commit;
> > > +	if (HAS_GMCH_DISPLAY(dev_priv)) {
> > > +		if (IS_CHERRYVIEW(dev_priv))
> > > +			dev_priv->display.load_luts = cherryview_load_luts;
> > > +		else
> > > +			dev_priv->display.load_luts = i9xx_load_luts;
> > > +
> > > +		dev_priv->display.color_commit = i9xx_color_commit;
> > >  	} else {
> > > -		dev_priv->display.load_luts = i9xx_load_luts;
> > > +		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> > > +			dev_priv->display.load_luts = glk_load_luts;
> > > +		else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> > > +			dev_priv->display.load_luts = broadwell_load_luts;
> > > +		else
> > > +			dev_priv->display.load_luts = i9xx_load_luts;
> > > +
> > > +		if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
> > > +			dev_priv->display.color_commit = hsw_color_commit;
> > > +		else
> > > +			dev_priv->display.color_commit = ilk_color_commit;
> > >  	}
> > >  
> > >  	/* Enable color management support when we have degamma & gamma LUTs. */
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index 1caee4128974..90afcae91b30 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -3415,7 +3415,7 @@ static void i9xx_disable_plane(struct intel_plane *plane,
> > >  	 *
> > >  	 * On pre-g4x there is no way to gamma correct the
> > >  	 * pipe bottom color but we'll keep on doing this
> > > -	 * anyway.
> > > +	 * anyway so that the crtc state readout works correctly.
> > >  	 */
> > >  	dspcntr = i9xx_plane_ctl_crtc(crtc_state);
> > >  
> > > @@ -7627,6 +7627,8 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
> > >  	     crtc_state->limited_color_range)
> > >  		pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
> > >  
> > > +	pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> > > +
> > >  	I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
> > >  	POSTING_READ(PIPECONF(crtc->pipe));
> > >  }
> > > @@ -8077,6 +8079,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> > >  	    (tmp & PIPECONF_COLOR_RANGE_SELECT))
> > >  		pipe_config->limited_color_range = true;
> > >  
> > > +	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
> > > +		PIPECONF_GAMMA_MODE_SHIFT;
> > > +
> > >  	if (INTEL_GEN(dev_priv) < 4)
> > >  		pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
> > >  
> > > @@ -8616,6 +8621,8 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
> > >  	if (crtc_state->limited_color_range)
> > >  		val |= PIPECONF_COLOR_RANGE_SELECT;
> > >  
> > > +	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> > > +
> > >  	I915_WRITE(PIPECONF(pipe), val);
> > >  	POSTING_READ(PIPECONF(pipe));
> > >  }
> > > @@ -9147,6 +9154,9 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
> > >  	if (tmp & PIPECONF_COLOR_RANGE_SELECT)
> > >  		pipe_config->limited_color_range = true;
> > >  
> > > +	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
> > > +		PIPECONF_GAMMA_MODE_SHIFT;
> > > +
> > >  	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
> > >  		struct intel_shared_dpll *pll;
> > >  		enum intel_dpll_id pll_id;
> > > @@ -11977,6 +11987,8 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
> > >  
> > >  	PIPE_CONF_CHECK_BOOL(double_wide);
> > >  
> > > +	PIPE_CONF_CHECK_X(gamma_mode);
> > > +
> > >  	PIPE_CONF_CHECK_P(shared_dpll);
> > >  	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> > >  	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
> > > -- 
> > > 2.19.2
> > > 
> > 
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > IoTG Platform Enabling & Development
> > Intel Corporation
> > (916) 356-2795
> 
> -- 
> Ville Syrjälä
> Intel
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 08/13] drm/i915: Populate gamma_mode for all platforms
  2019-01-16 19:51       ` Ville Syrjälä
@ 2019-01-29 15:59         ` Ville Syrjälä
  0 siblings, 0 replies; 52+ messages in thread
From: Ville Syrjälä @ 2019-01-29 15:59 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Wed, Jan 16, 2019 at 09:51:01PM +0200, Ville Syrjälä wrote:
> On Wed, Jan 16, 2019 at 08:58:04PM +0200, Ville Syrjälä wrote:
> > On Wed, Jan 16, 2019 at 10:31:56AM -0800, Matt Roper wrote:
> > > On Fri, Jan 11, 2019 at 07:08:18PM +0200, Ville Syrjala wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > On pre-HSW gamma mode is configured via PIPECONF. The bits are
> > > > the same except shifted up, so we can reuse just store them in
> > > > crtc_state->gamma_mode in the HSW+ way, allowing us to share
> > > > some code later.
> > > > 
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/i915_reg.h      | 10 ++++-
> > > >  drivers/gpu/drm/i915/intel_color.c   | 60 +++++++++++++++++++++-------
> > > >  drivers/gpu/drm/i915/intel_display.c | 14 ++++++-
> > > >  3 files changed, 66 insertions(+), 18 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 44958d994bfa..9d17ba199be4 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -5578,9 +5578,15 @@ enum {
> > > >  #define   PIPECONF_SINGLE_WIDE	0
> > > >  #define   PIPECONF_PIPE_UNLOCKED 0
> > > >  #define   PIPECONF_PIPE_LOCKED	(1 << 25)
> > > > -#define   PIPECONF_PALETTE	0
> > > > -#define   PIPECONF_GAMMA		(1 << 24)
> > > >  #define   PIPECONF_FORCE_BORDER	(1 << 25)
> > > > +#define   PIPECONF_GAMMA_MODE_MASK_I9XX	(1 << 24) /* gmch */
> > > > +#define   PIPECONF_GAMMA_MODE_MASK_ILK	(3 << 24) /* ilk-ivb */
> > > > +#define   PIPECONF_GAMMA_MODE_8BIT	(0 << 24) /* gmch,ilk-ivb */
> > > > +#define   PIPECONF_GAMMA_MODE_10BIT	(1 << 24) /* gmch,ilk-ivb */
> > > > +#define   PIPECONF_GAMMA_MODE_12BIT	(2 << 24) /* ilk-ivb */
> > > > +#define   PIPECONF_GAMMA_MODE_SPLIT	(3 << 24) /* ivb */
> > > > +#define   PIPECONF_GAMMA_MODE(x)	((x)<<24) /* pass in GAMMA_MODE_MODE_* */
> > > > +#define   PIPECONF_GAMMA_MODE_SHIFT	24
> > > >  #define   PIPECONF_INTERLACE_MASK	(7 << 21)
> > > >  #define   PIPECONF_INTERLACE_MASK_HSW	(3 << 21)
> > > >  /* Note that pre-gen3 does not support interlaced display directly. Panel
> > > > diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> > > > index 0c0da7ed0fd7..6fdbfa8c4008 100644
> > > > --- a/drivers/gpu/drm/i915/intel_color.c
> > > > +++ b/drivers/gpu/drm/i915/intel_color.c
> > > > @@ -351,6 +351,32 @@ static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
> > > >  	i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
> > > >  }
> > > >  
> > > > +static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
> > > > +{
> > > > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > > > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > > +	enum pipe pipe = crtc->pipe;
> > > > +	u32 val;
> > > > +
> > > > +	val = I915_READ(PIPECONF(pipe));
> > > > +	val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX;
> > > > +	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> > > > +	I915_WRITE(PIPECONF(pipe), val);
> > > > +}
> > > > +
> > > > +static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
> > > > +{
> > > > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > > > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > > +	enum pipe pipe = crtc->pipe;
> > > > +	u32 val;
> > > > +
> > > > +	val = I915_READ(PIPECONF(pipe));
> > > > +	val &= ~PIPECONF_GAMMA_MODE_MASK_ILK;
> > > > +	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> > > > +	I915_WRITE(PIPECONF(pipe), val);
> > > > +}
> > > 
> > > Could we just set color_commit to i9xx_set_pipeconf and
> > > ironlake_set_pipeconf to handle these without the r-m-w?
> > 
> > Perhaps. But not quite sure if we have any magic restrictions
> > in the crtc enable sequence that would prevent that.
> 
> I guess we could always keep the double set_pipeconf() in the
> crtc enable path so that we won't have to think whether to move the
> color_commit() earlier or the set_pipeconf() later.

Actually on second thought we can't avoid the RMW without more
restructuring because ironlake_set_pipeconf() & co. get called before
we enable the pipe and thus won't set the enable bit. So I think I'm
going to stick with the original patch for now.

> 
> > 
> > > 
> > > 
> > > Matt
> > > 
> > > > +
> > > >  static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
> > > >  {
> > > >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > > > @@ -585,8 +611,7 @@ void intel_color_commit(const struct intel_crtc_state *crtc_state)
> > > >  {
> > > >  	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> > > >  
> > > > -	if (dev_priv->display.color_commit)
> > > > -		dev_priv->display.color_commit(crtc_state);
> > > > +	dev_priv->display.color_commit(crtc_state);
> > > >  }
> > > >  
> > > >  int intel_color_check(struct intel_crtc_state *crtc_state)
> > > > @@ -634,20 +659,25 @@ void intel_color_init(struct intel_crtc *crtc)
> > > >  
> > > >  	drm_mode_crtc_set_gamma_size(&crtc->base, 256);
> > > >  
> > > > -	if (IS_CHERRYVIEW(dev_priv)) {
> > > > -		dev_priv->display.load_luts = cherryview_load_luts;
> > > > -	} else if (IS_HASWELL(dev_priv)) {
> > > > -		dev_priv->display.load_luts = i9xx_load_luts;
> > > > -		dev_priv->display.color_commit = hsw_color_commit;
> > > > -	} else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
> > > > -		   IS_BROXTON(dev_priv)) {
> > > > -		dev_priv->display.load_luts = broadwell_load_luts;
> > > > -		dev_priv->display.color_commit = hsw_color_commit;
> > > > -	} else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> > > > -		dev_priv->display.load_luts = glk_load_luts;
> > > > -		dev_priv->display.color_commit = hsw_color_commit;
> > > > +	if (HAS_GMCH_DISPLAY(dev_priv)) {
> > > > +		if (IS_CHERRYVIEW(dev_priv))
> > > > +			dev_priv->display.load_luts = cherryview_load_luts;
> > > > +		else
> > > > +			dev_priv->display.load_luts = i9xx_load_luts;
> > > > +
> > > > +		dev_priv->display.color_commit = i9xx_color_commit;
> > > >  	} else {
> > > > -		dev_priv->display.load_luts = i9xx_load_luts;
> > > > +		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> > > > +			dev_priv->display.load_luts = glk_load_luts;
> > > > +		else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> > > > +			dev_priv->display.load_luts = broadwell_load_luts;
> > > > +		else
> > > > +			dev_priv->display.load_luts = i9xx_load_luts;
> > > > +
> > > > +		if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
> > > > +			dev_priv->display.color_commit = hsw_color_commit;
> > > > +		else
> > > > +			dev_priv->display.color_commit = ilk_color_commit;
> > > >  	}
> > > >  
> > > >  	/* Enable color management support when we have degamma & gamma LUTs. */
> > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > > index 1caee4128974..90afcae91b30 100644
> > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > @@ -3415,7 +3415,7 @@ static void i9xx_disable_plane(struct intel_plane *plane,
> > > >  	 *
> > > >  	 * On pre-g4x there is no way to gamma correct the
> > > >  	 * pipe bottom color but we'll keep on doing this
> > > > -	 * anyway.
> > > > +	 * anyway so that the crtc state readout works correctly.
> > > >  	 */
> > > >  	dspcntr = i9xx_plane_ctl_crtc(crtc_state);
> > > >  
> > > > @@ -7627,6 +7627,8 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
> > > >  	     crtc_state->limited_color_range)
> > > >  		pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
> > > >  
> > > > +	pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> > > > +
> > > >  	I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
> > > >  	POSTING_READ(PIPECONF(crtc->pipe));
> > > >  }
> > > > @@ -8077,6 +8079,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> > > >  	    (tmp & PIPECONF_COLOR_RANGE_SELECT))
> > > >  		pipe_config->limited_color_range = true;
> > > >  
> > > > +	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
> > > > +		PIPECONF_GAMMA_MODE_SHIFT;
> > > > +
> > > >  	if (INTEL_GEN(dev_priv) < 4)
> > > >  		pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
> > > >  
> > > > @@ -8616,6 +8621,8 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
> > > >  	if (crtc_state->limited_color_range)
> > > >  		val |= PIPECONF_COLOR_RANGE_SELECT;
> > > >  
> > > > +	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> > > > +
> > > >  	I915_WRITE(PIPECONF(pipe), val);
> > > >  	POSTING_READ(PIPECONF(pipe));
> > > >  }
> > > > @@ -9147,6 +9154,9 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
> > > >  	if (tmp & PIPECONF_COLOR_RANGE_SELECT)
> > > >  		pipe_config->limited_color_range = true;
> > > >  
> > > > +	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
> > > > +		PIPECONF_GAMMA_MODE_SHIFT;
> > > > +
> > > >  	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
> > > >  		struct intel_shared_dpll *pll;
> > > >  		enum intel_dpll_id pll_id;
> > > > @@ -11977,6 +11987,8 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
> > > >  
> > > >  	PIPE_CONF_CHECK_BOOL(double_wide);
> > > >  
> > > > +	PIPE_CONF_CHECK_X(gamma_mode);
> > > > +
> > > >  	PIPE_CONF_CHECK_P(shared_dpll);
> > > >  	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> > > >  	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
> > > > -- 
> > > > 2.19.2
> > > > 
> > > 
> > > -- 
> > > Matt Roper
> > > Graphics Software Engineer
> > > IoTG Platform Enabling & Development
> > > Intel Corporation
> > > (916) 356-2795
> > 
> > -- 
> > Ville Syrjälä
> > Intel
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* [PATCH 09/13] drm/i915: Track pipe gamma enable/disable in crtc state
  2019-01-11 17:08 [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8 Ville Syrjala
                   ` (7 preceding siblings ...)
  2019-01-11 17:08 ` [PATCH 08/13] drm/i915: Populate gamma_mode for all platforms Ville Syrjala
@ 2019-01-11 17:08 ` Ville Syrjala
  2019-01-16 19:36   ` Matt Roper
  2019-01-11 17:08 ` [PATCH 10/13] drm/i915: Track pipe csc enable " Ville Syrjala
                   ` (6 subsequent siblings)
  15 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjala @ 2019-01-11 17:08 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Track whether pipe gamma is enabled or disabled. For now we
stick to the current behaviour of always enabling gamma. But
we do get working state readout for this now. On SKL+ we use
the pipe bottom color as our hardware state. On pre-SKL we
read the state back from the primary plane control register.
That only really correct for g4x+, as older platforms never
gamma correct pipe bottom color. But doing the readout the
same way on all platforms is fine, and there is no other way
to do it really.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  8 ++++
 drivers/gpu/drm/i915/intel_color.c   | 24 +++++++++++-
 drivers/gpu/drm/i915/intel_display.c | 56 ++++++++++++++++++++++------
 drivers/gpu/drm/i915/intel_drv.h     |  3 ++
 drivers/gpu/drm/i915/intel_sprite.c  | 17 +++++++--
 5 files changed, 92 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9d17ba199be4..7f0913bc1b47 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5707,6 +5707,14 @@ enum {
 #define   PIPEMISC_DITHER_TYPE_SP	(0 << 2)
 #define PIPEMISC(pipe)			_MMIO_PIPE2(pipe, _PIPE_MISC_A)
 
+/* SKL+ pipe bottom color */
+#define _PIPE_BOTTOM_COLOR_A		0x70034
+#define _PIPE_BOTTOM_COLOR_B		0x71034
+#define   PIPE_BOTTOM_GAMMA_ENABLE	(1 << 31)
+#define   PIPE_BOTTOM_CSC_ENABLE	(1 << 30)
+#define   PIPE_BOTTOM_COLOR_MASK	0x3FFFFFFF
+#define PIPE_BOTTOM_COLOR(pipe)		_MMIO_PIPE2(pipe, _PIPE_BOTTOM_COLOR_A)
+
 #define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)
 #define   PIPEB_LINE_COMPARE_INT_EN		(1 << 29)
 #define   PIPEB_HLINE_INT_EN			(1 << 28)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 6fdbfa8c4008..313b281204fa 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -387,6 +387,24 @@ static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
 	ilk_load_csc_matrix(crtc_state);
 }
 
+static void skl_color_commit(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+	u32 val;
+
+	val = 0;
+	if (crtc_state->gamma_enable)
+		val |= PIPE_BOTTOM_GAMMA_ENABLE;
+	val |= PIPE_BOTTOM_CSC_ENABLE;
+	I915_WRITE(PIPE_BOTTOM_COLOR(pipe), val);
+
+	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
+
+	ilk_load_csc_matrix(crtc_state);
+}
+
 static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -624,6 +642,8 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
 	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 
+	crtc_state->gamma_enable = true;
+
 	/*
 	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
 	 * size (256 entries).
@@ -674,7 +694,9 @@ void intel_color_init(struct intel_crtc *crtc)
 		else
 			dev_priv->display.load_luts = i9xx_load_luts;
 
-		if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
+		if (INTEL_GEN(dev_priv) >= 9)
+			dev_priv->display.color_commit = skl_color_commit;
+		else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
 			dev_priv->display.color_commit = hsw_color_commit;
 		else
 			dev_priv->display.color_commit = ilk_color_commit;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 90afcae91b30..896ce95790cb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3186,7 +3186,8 @@ static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 dspcntr = 0;
 
-	dspcntr |= DISPPLANE_GAMMA_ENABLE;
+	if (crtc_state->gamma_enable)
+		dspcntr |= DISPPLANE_GAMMA_ENABLE;
 
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
@@ -3664,7 +3665,9 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
 	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 		return plane_ctl;
 
-	plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
+	if (crtc_state->gamma_enable)
+		plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
+
 	plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
 
 	return plane_ctl;
@@ -3717,7 +3720,9 @@ u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
 	if (INTEL_GEN(dev_priv) >= 11)
 		return plane_color_ctl;
 
-	plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
+	if (crtc_state->gamma_enable)
+		plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
+
 	plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
 
 	return plane_color_ctl;
@@ -3925,7 +3930,6 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta
 		   ((new_crtc_state->pipe_src_w - 1) << 16) |
 		   (new_crtc_state->pipe_src_h - 1));
 
-	/* on skylake this is done by detaching scalers */
 	if (INTEL_GEN(dev_priv) >= 9) {
 		skl_detach_scalers(new_crtc_state);
 
@@ -8036,6 +8040,20 @@ static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc,
 	pipe_config->output_format = output;
 }
 
+static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
+	u32 tmp;
+
+	tmp = I915_READ(DSPCNTR(i9xx_plane));
+
+	if (tmp & DISPPLANE_GAMMA_ENABLE)
+		crtc_state->gamma_enable = true;
+}
+
 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 				 struct intel_crtc_state *pipe_config)
 {
@@ -8082,6 +8100,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
 		PIPECONF_GAMMA_MODE_SHIFT;
 
+	i9xx_get_pipe_color_config(pipe_config);
+
 	if (INTEL_GEN(dev_priv) < 4)
 		pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
 
@@ -9157,6 +9177,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
 		PIPECONF_GAMMA_MODE_SHIFT;
 
+	i9xx_get_pipe_color_config(pipe_config);
+
 	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
 		struct intel_shared_dpll *pll;
 		enum intel_dpll_id pll_id;
@@ -9785,6 +9807,15 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 	pipe_config->gamma_mode =
 		I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
 
+	if (INTEL_GEN(dev_priv) >= 9) {
+		u32 tmp = I915_READ(PIPE_BOTTOM_COLOR(crtc->pipe));
+
+		if (tmp & PIPE_BOTTOM_GAMMA_ENABLE)
+			pipe_config->gamma_enable = true;
+	} else {
+		i9xx_get_pipe_color_config(pipe_config);
+	}
+
 	power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
 	if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
 		power_domain_mask |= BIT_ULL(power_domain);
@@ -9953,7 +9984,12 @@ i845_cursor_max_stride(struct intel_plane *plane,
 
 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
 {
-	return CURSOR_GAMMA_ENABLE;
+	u32 cntl = 0;
+
+	if (crtc_state->gamma_enable)
+		cntl |= CURSOR_GAMMA_ENABLE;
+
+	return cntl;
 }
 
 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
@@ -10105,7 +10141,8 @@ static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
 	if (INTEL_GEN(dev_priv) >= 11)
 		return cntl;
 
-	cntl |= MCURSOR_GAMMA_ENABLE;
+	if (crtc_state->gamma_enable)
+		cntl = MCURSOR_GAMMA_ENABLE;
 
 	if (HAS_DDI(dev_priv))
 		cntl |= MCURSOR_PIPE_CSC_ENABLE;
@@ -11094,12 +11131,6 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
 		ret = intel_color_check(pipe_config);
 		if (ret)
 			return ret;
-
-		/*
-		 * Changing color management on Intel hardware is
-		 * handled as part of planes update.
-		 */
-		crtc_state->planes_changed = true;
 	}
 
 	ret = 0;
@@ -11988,6 +12019,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
 	PIPE_CONF_CHECK_BOOL(double_wide);
 
 	PIPE_CONF_CHECK_X(gamma_mode);
+	PIPE_CONF_CHECK_BOOL(gamma_enable);
 
 	PIPE_CONF_CHECK_P(shared_dpll);
 	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 59f8d4270e82..eee734b48919 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -946,6 +946,9 @@ struct intel_crtc_state {
 	/* Output down scaling is done in LSPCON device */
 	bool lspcon_downsampling;
 
+	/* enable pipe gamma? */
+	bool gamma_enable;
+
 	/* Display Stream compression state */
 	struct {
 		bool compression_enable;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index a45ef98b2f8d..034a355692db 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -739,7 +739,12 @@ vlv_update_clrc(const struct intel_plane_state *plane_state)
 
 static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
 {
-	return SP_GAMMA_ENABLE;
+	u32 sprctl = 0;
+
+	if (crtc_state->gamma_enable)
+		sprctl |= SP_GAMMA_ENABLE;
+
+	return sprctl;
 }
 
 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
@@ -915,7 +920,8 @@ static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 	u32 sprctl = 0;
 
-	sprctl |= SPRITE_GAMMA_ENABLE;
+	if (crtc_state->gamma_enable)
+		sprctl |= SPRITE_GAMMA_ENABLE;
 
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		sprctl |= SPRITE_PIPE_CSC_ENABLE;
@@ -1101,7 +1107,12 @@ g4x_sprite_max_stride(struct intel_plane *plane,
 
 static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
 {
-	return DVS_GAMMA_ENABLE;
+	u32 dvscntr = 0;
+
+	if (crtc_state->gamma_enable)
+		dvscntr |= DVS_GAMMA_ENABLE;
+
+	return dvscntr;
 }
 
 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
-- 
2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 52+ messages in thread

* Re: [PATCH 09/13] drm/i915: Track pipe gamma enable/disable in crtc state
  2019-01-11 17:08 ` [PATCH 09/13] drm/i915: Track pipe gamma enable/disable in crtc state Ville Syrjala
@ 2019-01-16 19:36   ` Matt Roper
  2019-01-17  5:14     ` Shankar, Uma
  0 siblings, 1 reply; 52+ messages in thread
From: Matt Roper @ 2019-01-16 19:36 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Jan 11, 2019 at 07:08:19PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Track whether pipe gamma is enabled or disabled. For now we
> stick to the current behaviour of always enabling gamma. But
> we do get working state readout for this now. On SKL+ we use
> the pipe bottom color as our hardware state. On pre-SKL we
> read the state back from the primary plane control register.
> That only really correct for g4x+, as older platforms never
> gamma correct pipe bottom color. But doing the readout the
> same way on all platforms is fine, and there is no other way
> to do it really.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  8 ++++
>  drivers/gpu/drm/i915/intel_color.c   | 24 +++++++++++-
>  drivers/gpu/drm/i915/intel_display.c | 56 ++++++++++++++++++++++------
>  drivers/gpu/drm/i915/intel_drv.h     |  3 ++
>  drivers/gpu/drm/i915/intel_sprite.c  | 17 +++++++--
>  5 files changed, 92 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9d17ba199be4..7f0913bc1b47 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5707,6 +5707,14 @@ enum {
>  #define   PIPEMISC_DITHER_TYPE_SP	(0 << 2)
>  #define PIPEMISC(pipe)			_MMIO_PIPE2(pipe, _PIPE_MISC_A)
>  
> +/* SKL+ pipe bottom color */
> +#define _PIPE_BOTTOM_COLOR_A		0x70034
> +#define _PIPE_BOTTOM_COLOR_B		0x71034
> +#define   PIPE_BOTTOM_GAMMA_ENABLE	(1 << 31)
> +#define   PIPE_BOTTOM_CSC_ENABLE	(1 << 30)
> +#define   PIPE_BOTTOM_COLOR_MASK	0x3FFFFFFF
> +#define PIPE_BOTTOM_COLOR(pipe)		_MMIO_PIPE2(pipe, _PIPE_BOTTOM_COLOR_A)
> +
>  #define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)
>  #define   PIPEB_LINE_COMPARE_INT_EN		(1 << 29)
>  #define   PIPEB_HLINE_INT_EN			(1 << 28)
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 6fdbfa8c4008..313b281204fa 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -387,6 +387,24 @@ static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
>  	ilk_load_csc_matrix(crtc_state);
>  }
>  
> +static void skl_color_commit(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum pipe pipe = crtc->pipe;
> +	u32 val;
> +
> +	val = 0;
> +	if (crtc_state->gamma_enable)
> +		val |= PIPE_BOTTOM_GAMMA_ENABLE;
> +	val |= PIPE_BOTTOM_CSC_ENABLE;
> +	I915_WRITE(PIPE_BOTTOM_COLOR(pipe), val);
> +
> +	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
> +
> +	ilk_load_csc_matrix(crtc_state);
> +}
> +
>  static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> @@ -624,6 +642,8 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
>  	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>  	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>  
> +	crtc_state->gamma_enable = true;
> +
>  	/*
>  	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
>  	 * size (256 entries).
> @@ -674,7 +694,9 @@ void intel_color_init(struct intel_crtc *crtc)
>  		else
>  			dev_priv->display.load_luts = i9xx_load_luts;
>  
> -		if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
> +		if (INTEL_GEN(dev_priv) >= 9)
> +			dev_priv->display.color_commit = skl_color_commit;
> +		else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
>  			dev_priv->display.color_commit = hsw_color_commit;
>  		else
>  			dev_priv->display.color_commit = ilk_color_commit;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 90afcae91b30..896ce95790cb 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3186,7 +3186,8 @@ static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	u32 dspcntr = 0;
>  
> -	dspcntr |= DISPPLANE_GAMMA_ENABLE;
> +	if (crtc_state->gamma_enable)
> +		dspcntr |= DISPPLANE_GAMMA_ENABLE;
>  
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>  		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> @@ -3664,7 +3665,9 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>  		return plane_ctl;
>  
> -	plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
> +	if (crtc_state->gamma_enable)
> +		plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
> +
>  	plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
>  
>  	return plane_ctl;
> @@ -3717,7 +3720,9 @@ u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  	if (INTEL_GEN(dev_priv) >= 11)
>  		return plane_color_ctl;
>  
> -	plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
> +	if (crtc_state->gamma_enable)
> +		plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
> +
>  	plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
>  
>  	return plane_color_ctl;
> @@ -3925,7 +3930,6 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta
>  		   ((new_crtc_state->pipe_src_w - 1) << 16) |
>  		   (new_crtc_state->pipe_src_h - 1));
>  
> -	/* on skylake this is done by detaching scalers */
>  	if (INTEL_GEN(dev_priv) >= 9) {
>  		skl_detach_scalers(new_crtc_state);
>  
> @@ -8036,6 +8040,20 @@ static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc,
>  	pipe_config->output_format = output;
>  }
>  
> +static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> +	u32 tmp;
> +
> +	tmp = I915_READ(DSPCNTR(i9xx_plane));
> +
> +	if (tmp & DISPPLANE_GAMMA_ENABLE)
> +		crtc_state->gamma_enable = true;
> +}
> +
>  static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  				 struct intel_crtc_state *pipe_config)
>  {
> @@ -8082,6 +8100,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
>  		PIPECONF_GAMMA_MODE_SHIFT;
>  
> +	i9xx_get_pipe_color_config(pipe_config);
> +
>  	if (INTEL_GEN(dev_priv) < 4)
>  		pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
>  
> @@ -9157,6 +9177,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
>  	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
>  		PIPECONF_GAMMA_MODE_SHIFT;
>  
> +	i9xx_get_pipe_color_config(pipe_config);
> +
>  	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
>  		struct intel_shared_dpll *pll;
>  		enum intel_dpll_id pll_id;
> @@ -9785,6 +9807,15 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>  	pipe_config->gamma_mode =
>  		I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
>  
> +	if (INTEL_GEN(dev_priv) >= 9) {
> +		u32 tmp = I915_READ(PIPE_BOTTOM_COLOR(crtc->pipe));
> +
> +		if (tmp & PIPE_BOTTOM_GAMMA_ENABLE)
> +			pipe_config->gamma_enable = true;
> +	} else {
> +		i9xx_get_pipe_color_config(pipe_config);
> +	}
> +
>  	power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
>  	if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
>  		power_domain_mask |= BIT_ULL(power_domain);
> @@ -9953,7 +9984,12 @@ i845_cursor_max_stride(struct intel_plane *plane,
>  
>  static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  {
> -	return CURSOR_GAMMA_ENABLE;
> +	u32 cntl = 0;
> +
> +	if (crtc_state->gamma_enable)
> +		cntl |= CURSOR_GAMMA_ENABLE;
> +
> +	return cntl;
>  }
>  
>  static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
> @@ -10105,7 +10141,8 @@ static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  	if (INTEL_GEN(dev_priv) >= 11)
>  		return cntl;
>  
> -	cntl |= MCURSOR_GAMMA_ENABLE;
> +	if (crtc_state->gamma_enable)
> +		cntl = MCURSOR_GAMMA_ENABLE;
>  
>  	if (HAS_DDI(dev_priv))
>  		cntl |= MCURSOR_PIPE_CSC_ENABLE;
> @@ -11094,12 +11131,6 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
>  		ret = intel_color_check(pipe_config);
>  		if (ret)
>  			return ret;
> -
> -		/*
> -		 * Changing color management on Intel hardware is
> -		 * handled as part of planes update.
> -		 */
> -		crtc_state->planes_changed = true;
>  	}
>  
>  	ret = 0;
> @@ -11988,6 +12019,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
>  	PIPE_CONF_CHECK_BOOL(double_wide);
>  
>  	PIPE_CONF_CHECK_X(gamma_mode);
> +	PIPE_CONF_CHECK_BOOL(gamma_enable);
>  
>  	PIPE_CONF_CHECK_P(shared_dpll);
>  	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 59f8d4270e82..eee734b48919 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -946,6 +946,9 @@ struct intel_crtc_state {
>  	/* Output down scaling is done in LSPCON device */
>  	bool lspcon_downsampling;
>  
> +	/* enable pipe gamma? */
> +	bool gamma_enable;
> +
>  	/* Display Stream compression state */
>  	struct {
>  		bool compression_enable;
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index a45ef98b2f8d..034a355692db 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -739,7 +739,12 @@ vlv_update_clrc(const struct intel_plane_state *plane_state)
>  
>  static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  {
> -	return SP_GAMMA_ENABLE;
> +	u32 sprctl = 0;
> +
> +	if (crtc_state->gamma_enable)
> +		sprctl |= SP_GAMMA_ENABLE;
> +
> +	return sprctl;
>  }
>  
>  static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
> @@ -915,7 +920,8 @@ static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>  	u32 sprctl = 0;
>  
> -	sprctl |= SPRITE_GAMMA_ENABLE;
> +	if (crtc_state->gamma_enable)
> +		sprctl |= SPRITE_GAMMA_ENABLE;
>  
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>  		sprctl |= SPRITE_PIPE_CSC_ENABLE;
> @@ -1101,7 +1107,12 @@ g4x_sprite_max_stride(struct intel_plane *plane,
>  
>  static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  {
> -	return DVS_GAMMA_ENABLE;
> +	u32 dvscntr = 0;
> +
> +	if (crtc_state->gamma_enable)
> +		dvscntr |= DVS_GAMMA_ENABLE;
> +
> +	return dvscntr;
>  }
>  
>  static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
> -- 
> 2.19.2
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 09/13] drm/i915: Track pipe gamma enable/disable in crtc state
  2019-01-16 19:36   ` Matt Roper
@ 2019-01-17  5:14     ` Shankar, Uma
  2019-01-17 14:57       ` Ville Syrjälä
  0 siblings, 1 reply; 52+ messages in thread
From: Shankar, Uma @ 2019-01-17  5:14 UTC (permalink / raw)
  To: Roper, Matthew D, Ville Syrjala; +Cc: intel-gfx



>-----Original Message-----
>From: Roper, Matthew D
>Sent: Thursday, January 17, 2019 1:07 AM
>To: Ville Syrjala <ville.syrjala@linux.intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>
>Subject: Re: [PATCH 09/13] drm/i915: Track pipe gamma enable/disable in crtc
>state
>
>On Fri, Jan 11, 2019 at 07:08:19PM +0200, Ville Syrjala wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Track whether pipe gamma is enabled or disabled. For now we stick to
>> the current behaviour of always enabling gamma. But we do get working
>> state readout for this now. On SKL+ we use the pipe bottom color as
>> our hardware state. On pre-SKL we read the state back from the primary
>> plane control register.
>> That only really correct for g4x+, as older platforms never gamma
>> correct pipe bottom color. But doing the readout the same way on all
>> platforms is fine, and there is no other way to do it really.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h      |  8 ++++
>>  drivers/gpu/drm/i915/intel_color.c   | 24 +++++++++++-
>>  drivers/gpu/drm/i915/intel_display.c | 56 ++++++++++++++++++++++------
>>  drivers/gpu/drm/i915/intel_drv.h     |  3 ++
>>  drivers/gpu/drm/i915/intel_sprite.c  | 17 +++++++--
>>  5 files changed, 92 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index 9d17ba199be4..7f0913bc1b47
>> 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -5707,6 +5707,14 @@ enum {
>>  #define   PIPEMISC_DITHER_TYPE_SP	(0 << 2)
>>  #define PIPEMISC(pipe)			_MMIO_PIPE2(pipe,
>_PIPE_MISC_A)
>>
>> +/* SKL+ pipe bottom color */
>> +#define _PIPE_BOTTOM_COLOR_A		0x70034
>> +#define _PIPE_BOTTOM_COLOR_B		0x71034
>> +#define   PIPE_BOTTOM_GAMMA_ENABLE	(1 << 31)
>> +#define   PIPE_BOTTOM_CSC_ENABLE	(1 << 30)
>> +#define   PIPE_BOTTOM_COLOR_MASK	0x3FFFFFFF
>> +#define PIPE_BOTTOM_COLOR(pipe)		_MMIO_PIPE2(pipe,
>_PIPE_BOTTOM_COLOR_A)
>> +
>>  #define VLV_DPFLIPSTAT
>	_MMIO(VLV_DISPLAY_BASE + 0x70028)
>>  #define   PIPEB_LINE_COMPARE_INT_EN		(1 << 29)
>>  #define   PIPEB_HLINE_INT_EN			(1 << 28)
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index 6fdbfa8c4008..313b281204fa 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -387,6 +387,24 @@ static void hsw_color_commit(const struct
>intel_crtc_state *crtc_state)
>>  	ilk_load_csc_matrix(crtc_state);
>>  }
>>
>> +static void skl_color_commit(const struct intel_crtc_state
>> +*crtc_state) {
>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> +	enum pipe pipe = crtc->pipe;
>> +	u32 val;
>> +
>> +	val = 0;

We can initialize this above itself.

>> +	if (crtc_state->gamma_enable)
>> +		val |= PIPE_BOTTOM_GAMMA_ENABLE;
>> +	val |= PIPE_BOTTOM_CSC_ENABLE;
>> +	I915_WRITE(PIPE_BOTTOM_COLOR(pipe), val);
>> +
>> +	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
>> +
>> +	ilk_load_csc_matrix(crtc_state);
>> +}
>> +
>>  static void bdw_load_degamma_lut(const struct intel_crtc_state
>> *crtc_state)  {
>>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> @@ -624,6 +642,8 @@ int intel_color_check(struct intel_crtc_state
>*crtc_state)
>>  	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>>  	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>>
>> +	crtc_state->gamma_enable = true;
>> +
>>  	/*
>>  	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
>>  	 * size (256 entries).
>> @@ -674,7 +694,9 @@ void intel_color_init(struct intel_crtc *crtc)
>>  		else
>>  			dev_priv->display.load_luts = i9xx_load_luts;
>>
>> -		if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
>> +		if (INTEL_GEN(dev_priv) >= 9)
>> +			dev_priv->display.color_commit = skl_color_commit;
>> +		else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
>>  			dev_priv->display.color_commit = hsw_color_commit;
>>  		else
>>  			dev_priv->display.color_commit = ilk_color_commit; diff
>--git
>> a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 90afcae91b30..896ce95790cb 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -3186,7 +3186,8 @@ static u32 i9xx_plane_ctl_crtc(const struct
>intel_crtc_state *crtc_state)
>>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>>  	u32 dspcntr = 0;
>>
>> -	dspcntr |= DISPPLANE_GAMMA_ENABLE;
>> +	if (crtc_state->gamma_enable)
>> +		dspcntr |= DISPPLANE_GAMMA_ENABLE;
>>
>>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>>  		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; @@ -3664,7 +3665,9
>@@ u32
>> skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
>>  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>>  		return plane_ctl;
>>
>> -	plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
>> +	if (crtc_state->gamma_enable)
>> +		plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
>> +
>>  	plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
>>
>>  	return plane_ctl;
>> @@ -3717,7 +3720,9 @@ u32 glk_plane_color_ctl_crtc(const struct
>intel_crtc_state *crtc_state)
>>  	if (INTEL_GEN(dev_priv) >= 11)
>>  		return plane_color_ctl;
>>
>> -	plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
>> +	if (crtc_state->gamma_enable)
>> +		plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
>> +
>>  	plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
>>
>>  	return plane_color_ctl;
>> @@ -3925,7 +3930,6 @@ static void intel_update_pipe_config(const struct
>intel_crtc_state *old_crtc_sta
>>  		   ((new_crtc_state->pipe_src_w - 1) << 16) |
>>  		   (new_crtc_state->pipe_src_h - 1));
>>
>> -	/* on skylake this is done by detaching scalers */

Is this intentional ? Seems unrelated to the patch.

With the above minor nits fixed:
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>>  	if (INTEL_GEN(dev_priv) >= 9) {
>>  		skl_detach_scalers(new_crtc_state);
>>
>> @@ -8036,6 +8040,20 @@ static void intel_get_crtc_ycbcr_config(struct
>intel_crtc *crtc,
>>  	pipe_config->output_format = output;  }
>>
>> +static void i9xx_get_pipe_color_config(struct intel_crtc_state
>> +*crtc_state) {
>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> +	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> +	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
>> +	u32 tmp;
>> +
>> +	tmp = I915_READ(DSPCNTR(i9xx_plane));
>> +
>> +	if (tmp & DISPPLANE_GAMMA_ENABLE)
>> +		crtc_state->gamma_enable = true;
>> +}
>> +
>>  static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>>  				 struct intel_crtc_state *pipe_config)  { @@ -
>8082,6 +8100,8 @@
>> static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>>  	pipe_config->gamma_mode = (tmp &
>PIPECONF_GAMMA_MODE_MASK_I9XX) >>
>>  		PIPECONF_GAMMA_MODE_SHIFT;
>>
>> +	i9xx_get_pipe_color_config(pipe_config);
>> +
>>  	if (INTEL_GEN(dev_priv) < 4)
>>  		pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
>>
>> @@ -9157,6 +9177,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc
>*crtc,
>>  	pipe_config->gamma_mode = (tmp &
>PIPECONF_GAMMA_MODE_MASK_ILK) >>
>>  		PIPECONF_GAMMA_MODE_SHIFT;
>>
>> +	i9xx_get_pipe_color_config(pipe_config);
>> +
>>  	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
>>  		struct intel_shared_dpll *pll;
>>  		enum intel_dpll_id pll_id;
>> @@ -9785,6 +9807,15 @@ static bool haswell_get_pipe_config(struct
>intel_crtc *crtc,
>>  	pipe_config->gamma_mode =
>>  		I915_READ(GAMMA_MODE(crtc->pipe)) &
>GAMMA_MODE_MODE_MASK;
>>
>> +	if (INTEL_GEN(dev_priv) >= 9) {
>> +		u32 tmp = I915_READ(PIPE_BOTTOM_COLOR(crtc->pipe));
>> +
>> +		if (tmp & PIPE_BOTTOM_GAMMA_ENABLE)
>> +			pipe_config->gamma_enable = true;
>> +	} else {
>> +		i9xx_get_pipe_color_config(pipe_config);
>> +	}
>> +
>>  	power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
>>  	if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
>>  		power_domain_mask |= BIT_ULL(power_domain); @@ -9953,7
>+9984,12 @@
>> i845_cursor_max_stride(struct intel_plane *plane,
>>
>>  static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state
>> *crtc_state)  {
>> -	return CURSOR_GAMMA_ENABLE;
>> +	u32 cntl = 0;
>> +
>> +	if (crtc_state->gamma_enable)
>> +		cntl |= CURSOR_GAMMA_ENABLE;
>> +
>> +	return cntl;
>>  }
>>
>>  static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
>> @@ -10105,7 +10141,8 @@ static u32 i9xx_cursor_ctl_crtc(const struct
>intel_crtc_state *crtc_state)
>>  	if (INTEL_GEN(dev_priv) >= 11)
>>  		return cntl;
>>
>> -	cntl |= MCURSOR_GAMMA_ENABLE;
>> +	if (crtc_state->gamma_enable)
>> +		cntl = MCURSOR_GAMMA_ENABLE;
>>
>>  	if (HAS_DDI(dev_priv))
>>  		cntl |= MCURSOR_PIPE_CSC_ENABLE;
>> @@ -11094,12 +11131,6 @@ static int intel_crtc_atomic_check(struct
>drm_crtc *crtc,
>>  		ret = intel_color_check(pipe_config);
>>  		if (ret)
>>  			return ret;
>> -
>> -		/*
>> -		 * Changing color management on Intel hardware is
>> -		 * handled as part of planes update.
>> -		 */
>> -		crtc_state->planes_changed = true;
>>  	}
>>
>>  	ret = 0;
>> @@ -11988,6 +12019,7 @@ intel_pipe_config_compare(struct
>drm_i915_private *dev_priv,
>>  	PIPE_CONF_CHECK_BOOL(double_wide);
>>
>>  	PIPE_CONF_CHECK_X(gamma_mode);
>> +	PIPE_CONF_CHECK_BOOL(gamma_enable);
>>
>>  	PIPE_CONF_CHECK_P(shared_dpll);
>>  	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>> b/drivers/gpu/drm/i915/intel_drv.h
>> index 59f8d4270e82..eee734b48919 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -946,6 +946,9 @@ struct intel_crtc_state {
>>  	/* Output down scaling is done in LSPCON device */
>>  	bool lspcon_downsampling;
>>
>> +	/* enable pipe gamma? */
>> +	bool gamma_enable;
>> +
>>  	/* Display Stream compression state */
>>  	struct {
>>  		bool compression_enable;
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
>> b/drivers/gpu/drm/i915/intel_sprite.c
>> index a45ef98b2f8d..034a355692db 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -739,7 +739,12 @@ vlv_update_clrc(const struct intel_plane_state
>> *plane_state)
>>
>>  static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state
>> *crtc_state)  {
>> -	return SP_GAMMA_ENABLE;
>> +	u32 sprctl = 0;
>> +
>> +	if (crtc_state->gamma_enable)
>> +		sprctl |= SP_GAMMA_ENABLE;
>> +
>> +	return sprctl;
>>  }
>>
>>  static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
>> @@ -915,7 +920,8 @@ static u32 ivb_sprite_ctl_crtc(const struct
>intel_crtc_state *crtc_state)
>>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>>  	u32 sprctl = 0;
>>
>> -	sprctl |= SPRITE_GAMMA_ENABLE;
>> +	if (crtc_state->gamma_enable)
>> +		sprctl |= SPRITE_GAMMA_ENABLE;
>>
>>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>>  		sprctl |= SPRITE_PIPE_CSC_ENABLE;
>> @@ -1101,7 +1107,12 @@ g4x_sprite_max_stride(struct intel_plane
>> *plane,
>>
>>  static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state
>> *crtc_state)  {
>> -	return DVS_GAMMA_ENABLE;
>> +	u32 dvscntr = 0;
>> +
>> +	if (crtc_state->gamma_enable)
>> +		dvscntr |= DVS_GAMMA_ENABLE;
>> +
>> +	return dvscntr;
>>  }
>>
>>  static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
>> --
>> 2.19.2
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>IoTG Platform Enabling & Development
>Intel Corporation
>(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 09/13] drm/i915: Track pipe gamma enable/disable in crtc state
  2019-01-17  5:14     ` Shankar, Uma
@ 2019-01-17 14:57       ` Ville Syrjälä
  0 siblings, 0 replies; 52+ messages in thread
From: Ville Syrjälä @ 2019-01-17 14:57 UTC (permalink / raw)
  To: Shankar, Uma; +Cc: intel-gfx

On Thu, Jan 17, 2019 at 05:14:06AM +0000, Shankar, Uma wrote:
> 
> 
> >-----Original Message-----
> >From: Roper, Matthew D
> >Sent: Thursday, January 17, 2019 1:07 AM
> >To: Ville Syrjala <ville.syrjala@linux.intel.com>
> >Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>
> >Subject: Re: [PATCH 09/13] drm/i915: Track pipe gamma enable/disable in crtc
> >state
> >
> >On Fri, Jan 11, 2019 at 07:08:19PM +0200, Ville Syrjala wrote:
> >> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>
> >> Track whether pipe gamma is enabled or disabled. For now we stick to
> >> the current behaviour of always enabling gamma. But we do get working
> >> state readout for this now. On SKL+ we use the pipe bottom color as
> >> our hardware state. On pre-SKL we read the state back from the primary
> >> plane control register.
> >> That only really correct for g4x+, as older platforms never gamma
> >> correct pipe bottom color. But doing the readout the same way on all
> >> platforms is fine, and there is no other way to do it really.
> >>
> >> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> >
> >> ---
> >>  drivers/gpu/drm/i915/i915_reg.h      |  8 ++++
> >>  drivers/gpu/drm/i915/intel_color.c   | 24 +++++++++++-
> >>  drivers/gpu/drm/i915/intel_display.c | 56 ++++++++++++++++++++++------
> >>  drivers/gpu/drm/i915/intel_drv.h     |  3 ++
> >>  drivers/gpu/drm/i915/intel_sprite.c  | 17 +++++++--
> >>  5 files changed, 92 insertions(+), 16 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >> b/drivers/gpu/drm/i915/i915_reg.h index 9d17ba199be4..7f0913bc1b47
> >> 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -5707,6 +5707,14 @@ enum {
> >>  #define   PIPEMISC_DITHER_TYPE_SP	(0 << 2)
> >>  #define PIPEMISC(pipe)			_MMIO_PIPE2(pipe,
> >_PIPE_MISC_A)
> >>
> >> +/* SKL+ pipe bottom color */
> >> +#define _PIPE_BOTTOM_COLOR_A		0x70034
> >> +#define _PIPE_BOTTOM_COLOR_B		0x71034
> >> +#define   PIPE_BOTTOM_GAMMA_ENABLE	(1 << 31)
> >> +#define   PIPE_BOTTOM_CSC_ENABLE	(1 << 30)
> >> +#define   PIPE_BOTTOM_COLOR_MASK	0x3FFFFFFF
> >> +#define PIPE_BOTTOM_COLOR(pipe)		_MMIO_PIPE2(pipe,
> >_PIPE_BOTTOM_COLOR_A)
> >> +
> >>  #define VLV_DPFLIPSTAT
> >	_MMIO(VLV_DISPLAY_BASE + 0x70028)
> >>  #define   PIPEB_LINE_COMPARE_INT_EN		(1 << 29)
> >>  #define   PIPEB_HLINE_INT_EN			(1 << 28)
> >> diff --git a/drivers/gpu/drm/i915/intel_color.c
> >> b/drivers/gpu/drm/i915/intel_color.c
> >> index 6fdbfa8c4008..313b281204fa 100644
> >> --- a/drivers/gpu/drm/i915/intel_color.c
> >> +++ b/drivers/gpu/drm/i915/intel_color.c
> >> @@ -387,6 +387,24 @@ static void hsw_color_commit(const struct
> >intel_crtc_state *crtc_state)
> >>  	ilk_load_csc_matrix(crtc_state);
> >>  }
> >>
> >> +static void skl_color_commit(const struct intel_crtc_state
> >> +*crtc_state) {
> >> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> >> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> +	enum pipe pipe = crtc->pipe;
> >> +	u32 val;
> >> +
> >> +	val = 0;
> 
> We can initialize this above itself.

Ack.

> 
> >> +	if (crtc_state->gamma_enable)
> >> +		val |= PIPE_BOTTOM_GAMMA_ENABLE;
> >> +	val |= PIPE_BOTTOM_CSC_ENABLE;
> >> +	I915_WRITE(PIPE_BOTTOM_COLOR(pipe), val);
> >> +
> >> +	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
> >> +
> >> +	ilk_load_csc_matrix(crtc_state);
> >> +}
> >> +
> >>  static void bdw_load_degamma_lut(const struct intel_crtc_state
> >> *crtc_state)  {
> >>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> >> @@ -624,6 +642,8 @@ int intel_color_check(struct intel_crtc_state
> >*crtc_state)
> >>  	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> >>  	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> >>
> >> +	crtc_state->gamma_enable = true;
> >> +
> >>  	/*
> >>  	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
> >>  	 * size (256 entries).
> >> @@ -674,7 +694,9 @@ void intel_color_init(struct intel_crtc *crtc)
> >>  		else
> >>  			dev_priv->display.load_luts = i9xx_load_luts;
> >>
> >> -		if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
> >> +		if (INTEL_GEN(dev_priv) >= 9)
> >> +			dev_priv->display.color_commit = skl_color_commit;
> >> +		else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> >>  			dev_priv->display.color_commit = hsw_color_commit;
> >>  		else
> >>  			dev_priv->display.color_commit = ilk_color_commit; diff
> >--git
> >> a/drivers/gpu/drm/i915/intel_display.c
> >> b/drivers/gpu/drm/i915/intel_display.c
> >> index 90afcae91b30..896ce95790cb 100644
> >> --- a/drivers/gpu/drm/i915/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/intel_display.c
> >> @@ -3186,7 +3186,8 @@ static u32 i9xx_plane_ctl_crtc(const struct
> >intel_crtc_state *crtc_state)
> >>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >>  	u32 dspcntr = 0;
> >>
> >> -	dspcntr |= DISPPLANE_GAMMA_ENABLE;
> >> +	if (crtc_state->gamma_enable)
> >> +		dspcntr |= DISPPLANE_GAMMA_ENABLE;
> >>
> >>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> >>  		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; @@ -3664,7 +3665,9
> >@@ u32
> >> skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
> >>  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> >>  		return plane_ctl;
> >>
> >> -	plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
> >> +	if (crtc_state->gamma_enable)
> >> +		plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
> >> +
> >>  	plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
> >>
> >>  	return plane_ctl;
> >> @@ -3717,7 +3720,9 @@ u32 glk_plane_color_ctl_crtc(const struct
> >intel_crtc_state *crtc_state)
> >>  	if (INTEL_GEN(dev_priv) >= 11)
> >>  		return plane_color_ctl;
> >>
> >> -	plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
> >> +	if (crtc_state->gamma_enable)
> >> +		plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
> >> +
> >>  	plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
> >>
> >>  	return plane_color_ctl;
> >> @@ -3925,7 +3930,6 @@ static void intel_update_pipe_config(const struct
> >intel_crtc_state *old_crtc_sta
> >>  		   ((new_crtc_state->pipe_src_w - 1) << 16) |
> >>  		   (new_crtc_state->pipe_src_h - 1));
> >>
> >> -	/* on skylake this is done by detaching scalers */
> 
> Is this intentional ? Seems unrelated to the patch.

Some random rebase fail probably.

> 
> With the above minor nits fixed:
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> 
> >>  	if (INTEL_GEN(dev_priv) >= 9) {
> >>  		skl_detach_scalers(new_crtc_state);
> >>
> >> @@ -8036,6 +8040,20 @@ static void intel_get_crtc_ycbcr_config(struct
> >intel_crtc *crtc,
> >>  	pipe_config->output_format = output;  }
> >>
> >> +static void i9xx_get_pipe_color_config(struct intel_crtc_state
> >> +*crtc_state) {
> >> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> >> +	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> >> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> +	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> >> +	u32 tmp;
> >> +
> >> +	tmp = I915_READ(DSPCNTR(i9xx_plane));
> >> +
> >> +	if (tmp & DISPPLANE_GAMMA_ENABLE)
> >> +		crtc_state->gamma_enable = true;
> >> +}
> >> +
> >>  static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> >>  				 struct intel_crtc_state *pipe_config)  { @@ -
> >8082,6 +8100,8 @@
> >> static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> >>  	pipe_config->gamma_mode = (tmp &
> >PIPECONF_GAMMA_MODE_MASK_I9XX) >>
> >>  		PIPECONF_GAMMA_MODE_SHIFT;
> >>
> >> +	i9xx_get_pipe_color_config(pipe_config);
> >> +
> >>  	if (INTEL_GEN(dev_priv) < 4)
> >>  		pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
> >>
> >> @@ -9157,6 +9177,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc
> >*crtc,
> >>  	pipe_config->gamma_mode = (tmp &
> >PIPECONF_GAMMA_MODE_MASK_ILK) >>
> >>  		PIPECONF_GAMMA_MODE_SHIFT;
> >>
> >> +	i9xx_get_pipe_color_config(pipe_config);
> >> +
> >>  	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
> >>  		struct intel_shared_dpll *pll;
> >>  		enum intel_dpll_id pll_id;
> >> @@ -9785,6 +9807,15 @@ static bool haswell_get_pipe_config(struct
> >intel_crtc *crtc,
> >>  	pipe_config->gamma_mode =
> >>  		I915_READ(GAMMA_MODE(crtc->pipe)) &
> >GAMMA_MODE_MODE_MASK;
> >>
> >> +	if (INTEL_GEN(dev_priv) >= 9) {
> >> +		u32 tmp = I915_READ(PIPE_BOTTOM_COLOR(crtc->pipe));
> >> +
> >> +		if (tmp & PIPE_BOTTOM_GAMMA_ENABLE)
> >> +			pipe_config->gamma_enable = true;
> >> +	} else {
> >> +		i9xx_get_pipe_color_config(pipe_config);
> >> +	}
> >> +
> >>  	power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
> >>  	if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
> >>  		power_domain_mask |= BIT_ULL(power_domain); @@ -9953,7
> >+9984,12 @@
> >> i845_cursor_max_stride(struct intel_plane *plane,
> >>
> >>  static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state
> >> *crtc_state)  {
> >> -	return CURSOR_GAMMA_ENABLE;
> >> +	u32 cntl = 0;
> >> +
> >> +	if (crtc_state->gamma_enable)
> >> +		cntl |= CURSOR_GAMMA_ENABLE;
> >> +
> >> +	return cntl;
> >>  }
> >>
> >>  static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
> >> @@ -10105,7 +10141,8 @@ static u32 i9xx_cursor_ctl_crtc(const struct
> >intel_crtc_state *crtc_state)
> >>  	if (INTEL_GEN(dev_priv) >= 11)
> >>  		return cntl;
> >>
> >> -	cntl |= MCURSOR_GAMMA_ENABLE;
> >> +	if (crtc_state->gamma_enable)
> >> +		cntl = MCURSOR_GAMMA_ENABLE;
> >>
> >>  	if (HAS_DDI(dev_priv))
> >>  		cntl |= MCURSOR_PIPE_CSC_ENABLE;
> >> @@ -11094,12 +11131,6 @@ static int intel_crtc_atomic_check(struct
> >drm_crtc *crtc,
> >>  		ret = intel_color_check(pipe_config);
> >>  		if (ret)
> >>  			return ret;
> >> -
> >> -		/*
> >> -		 * Changing color management on Intel hardware is
> >> -		 * handled as part of planes update.
> >> -		 */
> >> -		crtc_state->planes_changed = true;
> >>  	}
> >>
> >>  	ret = 0;
> >> @@ -11988,6 +12019,7 @@ intel_pipe_config_compare(struct
> >drm_i915_private *dev_priv,
> >>  	PIPE_CONF_CHECK_BOOL(double_wide);
> >>
> >>  	PIPE_CONF_CHECK_X(gamma_mode);
> >> +	PIPE_CONF_CHECK_BOOL(gamma_enable);
> >>
> >>  	PIPE_CONF_CHECK_P(shared_dpll);
> >>  	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> >> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> >> b/drivers/gpu/drm/i915/intel_drv.h
> >> index 59f8d4270e82..eee734b48919 100644
> >> --- a/drivers/gpu/drm/i915/intel_drv.h
> >> +++ b/drivers/gpu/drm/i915/intel_drv.h
> >> @@ -946,6 +946,9 @@ struct intel_crtc_state {
> >>  	/* Output down scaling is done in LSPCON device */
> >>  	bool lspcon_downsampling;
> >>
> >> +	/* enable pipe gamma? */
> >> +	bool gamma_enable;
> >> +
> >>  	/* Display Stream compression state */
> >>  	struct {
> >>  		bool compression_enable;
> >> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> >> b/drivers/gpu/drm/i915/intel_sprite.c
> >> index a45ef98b2f8d..034a355692db 100644
> >> --- a/drivers/gpu/drm/i915/intel_sprite.c
> >> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> >> @@ -739,7 +739,12 @@ vlv_update_clrc(const struct intel_plane_state
> >> *plane_state)
> >>
> >>  static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state
> >> *crtc_state)  {
> >> -	return SP_GAMMA_ENABLE;
> >> +	u32 sprctl = 0;
> >> +
> >> +	if (crtc_state->gamma_enable)
> >> +		sprctl |= SP_GAMMA_ENABLE;
> >> +
> >> +	return sprctl;
> >>  }
> >>
> >>  static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
> >> @@ -915,7 +920,8 @@ static u32 ivb_sprite_ctl_crtc(const struct
> >intel_crtc_state *crtc_state)
> >>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> >>  	u32 sprctl = 0;
> >>
> >> -	sprctl |= SPRITE_GAMMA_ENABLE;
> >> +	if (crtc_state->gamma_enable)
> >> +		sprctl |= SPRITE_GAMMA_ENABLE;
> >>
> >>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> >>  		sprctl |= SPRITE_PIPE_CSC_ENABLE;
> >> @@ -1101,7 +1107,12 @@ g4x_sprite_max_stride(struct intel_plane
> >> *plane,
> >>
> >>  static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state
> >> *crtc_state)  {
> >> -	return DVS_GAMMA_ENABLE;
> >> +	u32 dvscntr = 0;
> >> +
> >> +	if (crtc_state->gamma_enable)
> >> +		dvscntr |= DVS_GAMMA_ENABLE;
> >> +
> >> +	return dvscntr;
> >>  }
> >>
> >>  static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
> >> --
> >> 2.19.2
> >>
> >
> >--
> >Matt Roper
> >Graphics Software Engineer
> >IoTG Platform Enabling & Development
> >Intel Corporation
> >(916) 356-2795

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* [PATCH 10/13] drm/i915: Track pipe csc enable in crtc state
  2019-01-11 17:08 [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8 Ville Syrjala
                   ` (8 preceding siblings ...)
  2019-01-11 17:08 ` [PATCH 09/13] drm/i915: Track pipe gamma enable/disable in crtc state Ville Syrjala
@ 2019-01-11 17:08 ` Ville Syrjala
  2019-01-16 19:43   ` Matt Roper
  2019-01-11 17:08 ` [PATCH 11/13] drm/i915: Turn off pipe gamma when it's not needed Ville Syrjala
                   ` (5 subsequent siblings)
  15 siblings, 1 reply; 52+ messages in thread
From: Ville Syrjala @ 2019-01-11 17:08 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Just like we did for pipe gamma, let's also track the pipe csc
state. The hardware only exists on ILK+, and currently we always
enable it on hsw+ and never on any other platforms. Just like
with pipe gamma, the primary plane control register is used
for the readout on pre-SKL, and the pipe bottom color register
on SKL+.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  4 ++--
 drivers/gpu/drm/i915/intel_color.c   |  7 ++++++-
 drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++++----
 drivers/gpu/drm/i915/intel_drv.h     |  3 +++
 drivers/gpu/drm/i915/intel_sprite.c  |  6 ++++--
 5 files changed, 29 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7f0913bc1b47..8848721dd691 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6120,7 +6120,7 @@ enum {
 #define   MCURSOR_PIPE_SELECT_SHIFT	28
 #define   MCURSOR_PIPE_SELECT(pipe)	((pipe) << 28)
 #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
-#define   MCURSOR_PIPE_CSC_ENABLE (1 << 24)
+#define   MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
 #define   MCURSOR_ROTATE_180	(1 << 15)
 #define   MCURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
 #define _CURABASE		0x70084
@@ -6175,7 +6175,7 @@ enum {
 #define   DISPPLANE_RGBA888			(0xf << 26)
 #define   DISPPLANE_STEREO_ENABLE		(1 << 25)
 #define   DISPPLANE_STEREO_DISABLE		0
-#define   DISPPLANE_PIPE_CSC_ENABLE		(1 << 24)
+#define   DISPPLANE_PIPE_CSC_ENABLE		(1 << 24) /* ilk+ */
 #define   DISPPLANE_SEL_PIPE_SHIFT		24
 #define   DISPPLANE_SEL_PIPE_MASK		(3 << DISPPLANE_SEL_PIPE_SHIFT)
 #define   DISPPLANE_SEL_PIPE(pipe)		((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 313b281204fa..8d7ea902a34b 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -397,7 +397,8 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state)
 	val = 0;
 	if (crtc_state->gamma_enable)
 		val |= PIPE_BOTTOM_GAMMA_ENABLE;
-	val |= PIPE_BOTTOM_CSC_ENABLE;
+	if (crtc_state->csc_enable)
+		val |= PIPE_BOTTOM_CSC_ENABLE;
 	I915_WRITE(PIPE_BOTTOM_COLOR(pipe), val);
 
 	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
@@ -644,6 +645,10 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
 
 	crtc_state->gamma_enable = true;
 
+	if (INTEL_GEN(dev_priv) >= 9 ||
+	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+		crtc_state->csc_enable = true;
+
 	/*
 	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
 	 * size (256 entries).
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 896ce95790cb..2e66b398167e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3189,7 +3189,7 @@ static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->gamma_enable)
 		dspcntr |= DISPPLANE_GAMMA_ENABLE;
 
-	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+	if (crtc_state->csc_enable)
 		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
 
 	if (INTEL_GEN(dev_priv) < 5)
@@ -3668,7 +3668,8 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->gamma_enable)
 		plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
 
-	plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
+	if (crtc_state->csc_enable)
+		plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
 
 	return plane_ctl;
 }
@@ -3723,7 +3724,8 @@ u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->gamma_enable)
 		plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
 
-	plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
+	if (crtc_state->csc_enable)
+		plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
 
 	return plane_color_ctl;
 }
@@ -8052,6 +8054,10 @@ static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
 
 	if (tmp & DISPPLANE_GAMMA_ENABLE)
 		crtc_state->gamma_enable = true;
+
+	if (!HAS_GMCH_DISPLAY(dev_priv) &&
+	    tmp & DISPPLANE_PIPE_CSC_ENABLE)
+		crtc_state->csc_enable = true;
 }
 
 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
@@ -9812,6 +9818,9 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 
 		if (tmp & PIPE_BOTTOM_GAMMA_ENABLE)
 			pipe_config->gamma_enable = true;
+
+		if (tmp & PIPE_BOTTOM_CSC_ENABLE)
+			pipe_config->csc_enable = true;
 	} else {
 		i9xx_get_pipe_color_config(pipe_config);
 	}
@@ -10144,7 +10153,7 @@ static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->gamma_enable)
 		cntl = MCURSOR_GAMMA_ENABLE;
 
-	if (HAS_DDI(dev_priv))
+	if (crtc_state->csc_enable)
 		cntl |= MCURSOR_PIPE_CSC_ENABLE;
 
 	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
@@ -12020,6 +12029,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
 
 	PIPE_CONF_CHECK_X(gamma_mode);
 	PIPE_CONF_CHECK_BOOL(gamma_enable);
+	PIPE_CONF_CHECK_BOOL(csc_enable);
 
 	PIPE_CONF_CHECK_P(shared_dpll);
 	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index eee734b48919..a4496f799af3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -949,6 +949,9 @@ struct intel_crtc_state {
 	/* enable pipe gamma? */
 	bool gamma_enable;
 
+	/* enable pipe csc? */
+	bool csc_enable;
+
 	/* Display Stream compression state */
 	struct {
 		bool compression_enable;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 034a355692db..1fe983f0ef51 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -917,13 +917,12 @@ vlv_plane_get_hw_state(struct intel_plane *plane,
 
 static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 	u32 sprctl = 0;
 
 	if (crtc_state->gamma_enable)
 		sprctl |= SPRITE_GAMMA_ENABLE;
 
-	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+	if (crtc_state->csc_enable)
 		sprctl |= SPRITE_PIPE_CSC_ENABLE;
 
 	return sprctl;
@@ -1112,6 +1111,9 @@ static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->gamma_enable)
 		dvscntr |= DVS_GAMMA_ENABLE;
 
+	if (crtc_state->csc_enable)
+		dvscntr |= DVS_PIPE_CSC_ENABLE;
+
 	return dvscntr;
 }
 
-- 
2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 52+ messages in thread

* Re: [PATCH 10/13] drm/i915: Track pipe csc enable in crtc state
  2019-01-11 17:08 ` [PATCH 10/13] drm/i915: Track pipe csc enable " Ville Syrjala
@ 2019-01-16 19:43   ` Matt Roper
  2019-01-17  5:17     ` Shankar, Uma
  0 siblings, 1 reply; 52+ messages in thread
From: Matt Roper @ 2019-01-16 19:43 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Jan 11, 2019 at 07:08:20PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Just like we did for pipe gamma, let's also track the pipe csc
> state. The hardware only exists on ILK+, and currently we always
> enable it on hsw+ and never on any other platforms. Just like
> with pipe gamma, the primary plane control register is used
> for the readout on pre-SKL, and the pipe bottom color register
> on SKL+.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  4 ++--
>  drivers/gpu/drm/i915/intel_color.c   |  7 ++++++-
>  drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++++----
>  drivers/gpu/drm/i915/intel_drv.h     |  3 +++
>  drivers/gpu/drm/i915/intel_sprite.c  |  6 ++++--
>  5 files changed, 29 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7f0913bc1b47..8848721dd691 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6120,7 +6120,7 @@ enum {
>  #define   MCURSOR_PIPE_SELECT_SHIFT	28
>  #define   MCURSOR_PIPE_SELECT(pipe)	((pipe) << 28)
>  #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
> -#define   MCURSOR_PIPE_CSC_ENABLE (1 << 24)
> +#define   MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
>  #define   MCURSOR_ROTATE_180	(1 << 15)
>  #define   MCURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
>  #define _CURABASE		0x70084
> @@ -6175,7 +6175,7 @@ enum {
>  #define   DISPPLANE_RGBA888			(0xf << 26)
>  #define   DISPPLANE_STEREO_ENABLE		(1 << 25)
>  #define   DISPPLANE_STEREO_DISABLE		0
> -#define   DISPPLANE_PIPE_CSC_ENABLE		(1 << 24)
> +#define   DISPPLANE_PIPE_CSC_ENABLE		(1 << 24) /* ilk+ */
>  #define   DISPPLANE_SEL_PIPE_SHIFT		24
>  #define   DISPPLANE_SEL_PIPE_MASK		(3 << DISPPLANE_SEL_PIPE_SHIFT)
>  #define   DISPPLANE_SEL_PIPE(pipe)		((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 313b281204fa..8d7ea902a34b 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -397,7 +397,8 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state)
>  	val = 0;
>  	if (crtc_state->gamma_enable)
>  		val |= PIPE_BOTTOM_GAMMA_ENABLE;
> -	val |= PIPE_BOTTOM_CSC_ENABLE;
> +	if (crtc_state->csc_enable)
> +		val |= PIPE_BOTTOM_CSC_ENABLE;
>  	I915_WRITE(PIPE_BOTTOM_COLOR(pipe), val);
>  
>  	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
> @@ -644,6 +645,10 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
>  
>  	crtc_state->gamma_enable = true;
>  
> +	if (INTEL_GEN(dev_priv) >= 9 ||
> +	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> +		crtc_state->csc_enable = true;
> +
>  	/*
>  	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
>  	 * size (256 entries).
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 896ce95790cb..2e66b398167e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3189,7 +3189,7 @@ static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  	if (crtc_state->gamma_enable)
>  		dspcntr |= DISPPLANE_GAMMA_ENABLE;
>  
> -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> +	if (crtc_state->csc_enable)
>  		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
>  
>  	if (INTEL_GEN(dev_priv) < 5)
> @@ -3668,7 +3668,8 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  	if (crtc_state->gamma_enable)
>  		plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
>  
> -	plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
> +	if (crtc_state->csc_enable)
> +		plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
>  
>  	return plane_ctl;
>  }
> @@ -3723,7 +3724,8 @@ u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  	if (crtc_state->gamma_enable)
>  		plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
>  
> -	plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
> +	if (crtc_state->csc_enable)
> +		plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
>  
>  	return plane_color_ctl;
>  }
> @@ -8052,6 +8054,10 @@ static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
>  
>  	if (tmp & DISPPLANE_GAMMA_ENABLE)
>  		crtc_state->gamma_enable = true;
> +
> +	if (!HAS_GMCH_DISPLAY(dev_priv) &&
> +	    tmp & DISPPLANE_PIPE_CSC_ENABLE)
> +		crtc_state->csc_enable = true;
>  }
>  
>  static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> @@ -9812,6 +9818,9 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>  
>  		if (tmp & PIPE_BOTTOM_GAMMA_ENABLE)
>  			pipe_config->gamma_enable = true;
> +
> +		if (tmp & PIPE_BOTTOM_CSC_ENABLE)
> +			pipe_config->csc_enable = true;
>  	} else {
>  		i9xx_get_pipe_color_config(pipe_config);
>  	}
> @@ -10144,7 +10153,7 @@ static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  	if (crtc_state->gamma_enable)
>  		cntl = MCURSOR_GAMMA_ENABLE;
>  
> -	if (HAS_DDI(dev_priv))
> +	if (crtc_state->csc_enable)
>  		cntl |= MCURSOR_PIPE_CSC_ENABLE;
>  
>  	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
> @@ -12020,6 +12029,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
>  
>  	PIPE_CONF_CHECK_X(gamma_mode);
>  	PIPE_CONF_CHECK_BOOL(gamma_enable);
> +	PIPE_CONF_CHECK_BOOL(csc_enable);
>  
>  	PIPE_CONF_CHECK_P(shared_dpll);
>  	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index eee734b48919..a4496f799af3 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -949,6 +949,9 @@ struct intel_crtc_state {
>  	/* enable pipe gamma? */
>  	bool gamma_enable;
>  
> +	/* enable pipe csc? */
> +	bool csc_enable;
> +
>  	/* Display Stream compression state */
>  	struct {
>  		bool compression_enable;
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 034a355692db..1fe983f0ef51 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -917,13 +917,12 @@ vlv_plane_get_hw_state(struct intel_plane *plane,
>  
>  static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>  	u32 sprctl = 0;
>  
>  	if (crtc_state->gamma_enable)
>  		sprctl |= SPRITE_GAMMA_ENABLE;
>  
> -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> +	if (crtc_state->csc_enable)
>  		sprctl |= SPRITE_PIPE_CSC_ENABLE;
>  
>  	return sprctl;
> @@ -1112,6 +1111,9 @@ static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  	if (crtc_state->gamma_enable)
>  		dvscntr |= DVS_GAMMA_ENABLE;
>  
> +	if (crtc_state->csc_enable)
> +		dvscntr |= DVS_PIPE_CSC_ENABLE;
> +
>  	return dvscntr;
>  }
>  
> -- 
> 2.19.2
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 10/13] drm/i915: Track pipe csc enable in crtc state
  2019-01-16 19:43   ` Matt Roper
@ 2019-01-17  5:17     ` Shankar, Uma
  0 siblings, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-01-17  5:17 UTC (permalink / raw)
  To: Roper, Matthew D, Ville Syrjala; +Cc: intel-gfx



>-----Original Message-----
>From: Roper, Matthew D
>Sent: Thursday, January 17, 2019 1:14 AM
>To: Ville Syrjala <ville.syrjala@linux.intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>
>Subject: Re: [PATCH 10/13] drm/i915: Track pipe csc enable in crtc state
>
>On Fri, Jan 11, 2019 at 07:08:20PM +0200, Ville Syrjala wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Just like we did for pipe gamma, let's also track the pipe csc state.
>> The hardware only exists on ILK+, and currently we always enable it on
>> hsw+ and never on any other platforms. Just like with pipe gamma, the
>> primary plane control register is used for the readout on pre-SKL, and
>> the pipe bottom color register on SKL+.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>> ---
>>  drivers/gpu/drm/i915/i915_reg.h      |  4 ++--
>>  drivers/gpu/drm/i915/intel_color.c   |  7 ++++++-
>>  drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++++----
>>  drivers/gpu/drm/i915/intel_drv.h     |  3 +++
>>  drivers/gpu/drm/i915/intel_sprite.c  |  6 ++++--
>>  5 files changed, 29 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index 7f0913bc1b47..8848721dd691
>> 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6120,7 +6120,7 @@ enum {
>>  #define   MCURSOR_PIPE_SELECT_SHIFT	28
>>  #define   MCURSOR_PIPE_SELECT(pipe)	((pipe) << 28)
>>  #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
>> -#define   MCURSOR_PIPE_CSC_ENABLE (1 << 24)
>> +#define   MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
>>  #define   MCURSOR_ROTATE_180	(1 << 15)
>>  #define   MCURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
>>  #define _CURABASE		0x70084
>> @@ -6175,7 +6175,7 @@ enum {
>>  #define   DISPPLANE_RGBA888			(0xf << 26)
>>  #define   DISPPLANE_STEREO_ENABLE		(1 << 25)
>>  #define   DISPPLANE_STEREO_DISABLE		0
>> -#define   DISPPLANE_PIPE_CSC_ENABLE		(1 << 24)
>> +#define   DISPPLANE_PIPE_CSC_ENABLE		(1 << 24) /* ilk+ */
>>  #define   DISPPLANE_SEL_PIPE_SHIFT		24
>>  #define   DISPPLANE_SEL_PIPE_MASK		(3 <<
>DISPPLANE_SEL_PIPE_SHIFT)
>>  #define   DISPPLANE_SEL_PIPE(pipe)		((pipe) <<
>DISPPLANE_SEL_PIPE_SHIFT)
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index 313b281204fa..8d7ea902a34b 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -397,7 +397,8 @@ static void skl_color_commit(const struct
>intel_crtc_state *crtc_state)
>>  	val = 0;
>>  	if (crtc_state->gamma_enable)
>>  		val |= PIPE_BOTTOM_GAMMA_ENABLE;
>> -	val |= PIPE_BOTTOM_CSC_ENABLE;
>> +	if (crtc_state->csc_enable)
>> +		val |= PIPE_BOTTOM_CSC_ENABLE;
>>  	I915_WRITE(PIPE_BOTTOM_COLOR(pipe), val);
>>
>>  	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
>@@
>> -644,6 +645,10 @@ int intel_color_check(struct intel_crtc_state
>> *crtc_state)
>>
>>  	crtc_state->gamma_enable = true;
>>
>> +	if (INTEL_GEN(dev_priv) >= 9 ||
>> +	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
>> +		crtc_state->csc_enable = true;
>> +
>>  	/*
>>  	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
>>  	 * size (256 entries).
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 896ce95790cb..2e66b398167e 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -3189,7 +3189,7 @@ static u32 i9xx_plane_ctl_crtc(const struct
>intel_crtc_state *crtc_state)
>>  	if (crtc_state->gamma_enable)
>>  		dspcntr |= DISPPLANE_GAMMA_ENABLE;
>>
>> -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>> +	if (crtc_state->csc_enable)
>>  		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
>>
>>  	if (INTEL_GEN(dev_priv) < 5)
>> @@ -3668,7 +3668,8 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state
>*crtc_state)
>>  	if (crtc_state->gamma_enable)
>>  		plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
>>
>> -	plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
>> +	if (crtc_state->csc_enable)
>> +		plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
>>
>>  	return plane_ctl;
>>  }
>> @@ -3723,7 +3724,8 @@ u32 glk_plane_color_ctl_crtc(const struct
>intel_crtc_state *crtc_state)
>>  	if (crtc_state->gamma_enable)
>>  		plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
>>
>> -	plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
>> +	if (crtc_state->csc_enable)
>> +		plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
>>
>>  	return plane_color_ctl;
>>  }
>> @@ -8052,6 +8054,10 @@ static void i9xx_get_pipe_color_config(struct
>> intel_crtc_state *crtc_state)
>>
>>  	if (tmp & DISPPLANE_GAMMA_ENABLE)
>>  		crtc_state->gamma_enable = true;
>> +
>> +	if (!HAS_GMCH_DISPLAY(dev_priv) &&
>> +	    tmp & DISPPLANE_PIPE_CSC_ENABLE)
>> +		crtc_state->csc_enable = true;
>>  }
>>
>>  static bool i9xx_get_pipe_config(struct intel_crtc *crtc, @@ -9812,6
>> +9818,9 @@ static bool haswell_get_pipe_config(struct intel_crtc
>> *crtc,
>>
>>  		if (tmp & PIPE_BOTTOM_GAMMA_ENABLE)
>>  			pipe_config->gamma_enable = true;
>> +
>> +		if (tmp & PIPE_BOTTOM_CSC_ENABLE)
>> +			pipe_config->csc_enable = true;
>>  	} else {
>>  		i9xx_get_pipe_color_config(pipe_config);
>>  	}
>> @@ -10144,7 +10153,7 @@ static u32 i9xx_cursor_ctl_crtc(const struct
>intel_crtc_state *crtc_state)
>>  	if (crtc_state->gamma_enable)
>>  		cntl = MCURSOR_GAMMA_ENABLE;
>>
>> -	if (HAS_DDI(dev_priv))
>> +	if (crtc_state->csc_enable)
>>  		cntl |= MCURSOR_PIPE_CSC_ENABLE;
>>
>>  	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) @@ -12020,6
>> +12029,7 @@ intel_pipe_config_compare(struct drm_i915_private
>> *dev_priv,
>>
>>  	PIPE_CONF_CHECK_X(gamma_mode);
>>  	PIPE_CONF_CHECK_BOOL(gamma_enable);
>> +	PIPE_CONF_CHECK_BOOL(csc_enable);
>>
>>  	PIPE_CONF_CHECK_P(shared_dpll);
>>  	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>> b/drivers/gpu/drm/i915/intel_drv.h
>> index eee734b48919..a4496f799af3 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -949,6 +949,9 @@ struct intel_crtc_state {
>>  	/* enable pipe gamma? */
>>  	bool gamma_enable;
>>
>> +	/* enable pipe csc? */
>> +	bool csc_enable;
>> +
>>  	/* Display Stream compression state */
>>  	struct {
>>  		bool compression_enable;
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
>> b/drivers/gpu/drm/i915/intel_sprite.c
>> index 034a355692db..1fe983f0ef51 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -917,13 +917,12 @@ vlv_plane_get_hw_state(struct intel_plane
>> *plane,
>>
>>  static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state
>> *crtc_state)  {
>> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>>  	u32 sprctl = 0;
>>
>>  	if (crtc_state->gamma_enable)
>>  		sprctl |= SPRITE_GAMMA_ENABLE;
>>
>> -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>> +	if (crtc_state->csc_enable)
>>  		sprctl |= SPRITE_PIPE_CSC_ENABLE;
>>
>>  	return sprctl;
>> @@ -1112,6 +1111,9 @@ static u32 g4x_sprite_ctl_crtc(const struct
>intel_crtc_state *crtc_state)
>>  	if (crtc_state->gamma_enable)
>>  		dvscntr |= DVS_GAMMA_ENABLE;
>>
>> +	if (crtc_state->csc_enable)
>> +		dvscntr |= DVS_PIPE_CSC_ENABLE;
>> +
>>  	return dvscntr;
>>  }
>>
>> --
>> 2.19.2
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>IoTG Platform Enabling & Development
>Intel Corporation
>(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* [PATCH 11/13] drm/i915: Turn off pipe gamma when it's not needed.
  2019-01-11 17:08 [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8 Ville Syrjala
                   ` (9 preceding siblings ...)
  2019-01-11 17:08 ` [PATCH 10/13] drm/i915: Track pipe csc enable " Ville Syrjala
@ 2019-01-11 17:08 ` Ville Syrjala
  2019-01-17  5:32   ` Shankar, Uma
  2019-01-17 18:40   ` Matt Roper
  2019-01-11 17:08 ` [PATCH 12/13] drm/i915: Turn off pipe CSC " Ville Syrjala
                   ` (4 subsequent siblings)
  15 siblings, 2 replies; 52+ messages in thread
From: Ville Syrjala @ 2019-01-11 17:08 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The pipe internal precision is higher than what we currently program to
the degamma/gamma LUTs. We can get a higher quality image by bypassing
the LUTs when they're not needed. Let's do that.

Each plane has its own control bit for this, so we have to update
all active planes. The way we've done this we don't actually have
to run through the whole .check_plane() thing. And we actually
do the .color_check() after .check_plane() so we couldn't even do
that without shuffling the code around.

Additionally on pre-skl we have to update the primary plane regardless
of whether it's active or not on account of the primayr plane gamma
enable bit also affecting the pipe bottom color.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_color.c | 55 ++++++++++++++++++++++++++++--
 1 file changed, 53 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 8d7ea902a34b..a8b7428a64bf 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -633,27 +633,78 @@ void intel_color_commit(const struct intel_crtc_state *crtc_state)
 	dev_priv->display.color_commit(crtc_state);
 }
 
+static bool need_plane_update(struct intel_plane *plane,
+			      const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+
+	/*
+	 * On pre-SKL the pipe gamma enable and pipe csc enable for
+	 * the pipe bottom color are configured via the primary plane.
+	 * We have to reconfigure that even if the plane is inactive.
+	 */
+	return crtc_state->active_planes & BIT(plane->id) ||
+		(INTEL_GEN(dev_priv) < 9 &&
+		 plane->id == PLANE_PRIMARY);
+}
+
+static int
+intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_atomic_state *state =
+		to_intel_atomic_state(new_crtc_state->base.state);
+	const struct intel_crtc_state *old_crtc_state =
+		intel_atomic_get_old_crtc_state(state, crtc);
+	struct intel_plane *plane;
+
+	if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable)
+		return 0;
+
+	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+		struct intel_plane_state *plane_state;
+
+		if (!need_plane_update(plane, new_crtc_state))
+			continue;
+
+		plane_state = intel_atomic_get_plane_state(state, plane);
+		if (IS_ERR(plane_state))
+			return PTR_ERR(plane_state);
+
+		new_crtc_state->update_planes |= BIT(plane->id);
+	}
+
+	return 0;
+}
+
 int intel_color_check(struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
 	size_t gamma_length, degamma_length;
+	int ret;
 
 	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 
-	crtc_state->gamma_enable = true;
+	crtc_state->gamma_enable = gamma_lut || degamma_lut;
 
 	if (INTEL_GEN(dev_priv) >= 9 ||
 	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
 		crtc_state->csc_enable = true;
 
+	ret = intel_color_add_affected_planes(crtc_state);
+	if (ret)
+		return ret;
+
 	/*
 	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
 	 * size (256 entries).
 	 */
-	if (crtc_state_is_legacy_gamma(crtc_state)) {
+	if (!crtc_state->gamma_enable ||
+	    crtc_state_is_legacy_gamma(crtc_state)) {
 		crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
 		return 0;
 	}
-- 
2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 52+ messages in thread

* Re: [PATCH 11/13] drm/i915: Turn off pipe gamma when it's not needed.
  2019-01-11 17:08 ` [PATCH 11/13] drm/i915: Turn off pipe gamma when it's not needed Ville Syrjala
@ 2019-01-17  5:32   ` Shankar, Uma
  2019-01-17 18:40   ` Matt Roper
  1 sibling, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-01-17  5:32 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx



>-----Original Message-----
>From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
>Sent: Friday, January 11, 2019 10:38 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma <uma.shankar@intel.com>; Roper, Matthew D
><matthew.d.roper@intel.com>
>Subject: [PATCH 11/13] drm/i915: Turn off pipe gamma when it's not needed.

Full stop can be dropped.

>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>The pipe internal precision is higher than what we currently program to the
>degamma/gamma LUTs. We can get a higher quality image by bypassing the LUTs
>when they're not needed. Let's do that.
>
>Each plane has its own control bit for this, so we have to update all active planes.
>The way we've done this we don't actually have to run through the whole
>.check_plane() thing. And we actually do the .color_check() after .check_plane()
>so we couldn't even do that without shuffling the code around.
>
>Additionally on pre-skl we have to update the primary plane regardless of
>whether it's active or not on account of the primayr plane gamma enable bit also

Typo in primary.

Overall looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>affecting the pipe bottom color.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/intel_color.c | 55 ++++++++++++++++++++++++++++--
> 1 file changed, 53 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_color.c
>b/drivers/gpu/drm/i915/intel_color.c
>index 8d7ea902a34b..a8b7428a64bf 100644
>--- a/drivers/gpu/drm/i915/intel_color.c
>+++ b/drivers/gpu/drm/i915/intel_color.c
>@@ -633,27 +633,78 @@ void intel_color_commit(const struct intel_crtc_state
>*crtc_state)
> 	dev_priv->display.color_commit(crtc_state);
> }
>
>+static bool need_plane_update(struct intel_plane *plane,
>+			      const struct intel_crtc_state *crtc_state) {
>+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>+
>+	/*
>+	 * On pre-SKL the pipe gamma enable and pipe csc enable for
>+	 * the pipe bottom color are configured via the primary plane.
>+	 * We have to reconfigure that even if the plane is inactive.
>+	 */
>+	return crtc_state->active_planes & BIT(plane->id) ||
>+		(INTEL_GEN(dev_priv) < 9 &&
>+		 plane->id == PLANE_PRIMARY);
>+}
>+
>+static int
>+intel_color_add_affected_planes(struct intel_crtc_state
>+*new_crtc_state) {
>+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
>+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>+	struct intel_atomic_state *state =
>+		to_intel_atomic_state(new_crtc_state->base.state);
>+	const struct intel_crtc_state *old_crtc_state =
>+		intel_atomic_get_old_crtc_state(state, crtc);
>+	struct intel_plane *plane;
>+
>+	if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable)
>+		return 0;
>+
>+	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
>+		struct intel_plane_state *plane_state;
>+
>+		if (!need_plane_update(plane, new_crtc_state))
>+			continue;
>+
>+		plane_state = intel_atomic_get_plane_state(state, plane);
>+		if (IS_ERR(plane_state))
>+			return PTR_ERR(plane_state);
>+
>+		new_crtc_state->update_planes |= BIT(plane->id);
>+	}
>+
>+	return 0;
>+}
>+
> int intel_color_check(struct intel_crtc_state *crtc_state)  {
> 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> 	const struct drm_property_blob *gamma_lut = crtc_state-
>>base.gamma_lut;
> 	const struct drm_property_blob *degamma_lut = crtc_state-
>>base.degamma_lut;
> 	size_t gamma_length, degamma_length;
>+	int ret;
>
> 	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> 	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>
>-	crtc_state->gamma_enable = true;
>+	crtc_state->gamma_enable = gamma_lut || degamma_lut;
>
> 	if (INTEL_GEN(dev_priv) >= 9 ||
> 	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> 		crtc_state->csc_enable = true;
>
>+	ret = intel_color_add_affected_planes(crtc_state);
>+	if (ret)
>+		return ret;
>+
> 	/*
> 	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
> 	 * size (256 entries).
> 	 */
>-	if (crtc_state_is_legacy_gamma(crtc_state)) {
>+	if (!crtc_state->gamma_enable ||
>+	    crtc_state_is_legacy_gamma(crtc_state)) {
> 		crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> 		return 0;
> 	}
>--
>2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 11/13] drm/i915: Turn off pipe gamma when it's not needed.
  2019-01-11 17:08 ` [PATCH 11/13] drm/i915: Turn off pipe gamma when it's not needed Ville Syrjala
  2019-01-17  5:32   ` Shankar, Uma
@ 2019-01-17 18:40   ` Matt Roper
  2019-01-17 18:48     ` Ville Syrjälä
  1 sibling, 1 reply; 52+ messages in thread
From: Matt Roper @ 2019-01-17 18:40 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Jan 11, 2019 at 07:08:21PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The pipe internal precision is higher than what we currently program to
> the degamma/gamma LUTs. We can get a higher quality image by bypassing
> the LUTs when they're not needed. Let's do that.
> 
> Each plane has its own control bit for this, so we have to update
> all active planes. The way we've done this we don't actually have
> to run through the whole .check_plane() thing. And we actually
> do the .color_check() after .check_plane() so we couldn't even do
> that without shuffling the code around.
> 
> Additionally on pre-skl we have to update the primary plane regardless
> of whether it's active or not on account of the primayr plane gamma

s/primayr/primary/

> enable bit also affecting the pipe bottom color.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_color.c | 55 ++++++++++++++++++++++++++++--
>  1 file changed, 53 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 8d7ea902a34b..a8b7428a64bf 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -633,27 +633,78 @@ void intel_color_commit(const struct intel_crtc_state *crtc_state)
>  	dev_priv->display.color_commit(crtc_state);
>  }
>  
> +static bool need_plane_update(struct intel_plane *plane,
> +			      const struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +
> +	/*
> +	 * On pre-SKL the pipe gamma enable and pipe csc enable for
> +	 * the pipe bottom color are configured via the primary plane.
> +	 * We have to reconfigure that even if the plane is inactive.
> +	 */
> +	return crtc_state->active_planes & BIT(plane->id) ||
> +		(INTEL_GEN(dev_priv) < 9 &&
> +		 plane->id == PLANE_PRIMARY);
> +}
> +
> +static int
> +intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct intel_atomic_state *state =
> +		to_intel_atomic_state(new_crtc_state->base.state);
> +	const struct intel_crtc_state *old_crtc_state =
> +		intel_atomic_get_old_crtc_state(state, crtc);
> +	struct intel_plane *plane;
> +
> +	if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable)
> +		return 0;
> +
> +	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> +		struct intel_plane_state *plane_state;
> +
> +		if (!need_plane_update(plane, new_crtc_state))
> +			continue;
> +
> +		plane_state = intel_atomic_get_plane_state(state, plane);
> +		if (IS_ERR(plane_state))
> +			return PTR_ERR(plane_state);
> +
> +		new_crtc_state->update_planes |= BIT(plane->id);
> +	}
> +
> +	return 0;
> +}
> +
>  int intel_color_check(struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>  	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
>  	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
>  	size_t gamma_length, degamma_length;
> +	int ret;
>  
>  	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>  	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>  
> -	crtc_state->gamma_enable = true;
> +	crtc_state->gamma_enable = gamma_lut || degamma_lut;
>  
>  	if (INTEL_GEN(dev_priv) >= 9 ||
>  	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
>  		crtc_state->csc_enable = true;
>  
> +	ret = intel_color_add_affected_planes(crtc_state);
> +	if (ret)
> +		return ret;
> +
>  	/*
>  	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
>  	 * size (256 entries).
>  	 */
> -	if (crtc_state_is_legacy_gamma(crtc_state)) {
> +	if (!crtc_state->gamma_enable ||
> +	    crtc_state_is_legacy_gamma(crtc_state)) {
>  		crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;

If none of our planes are actually using the gamma, what does switching
back to 8bit mode do for us?

Regardless,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>


>  		return 0;
>  	}
> -- 
> 2.19.2
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 11/13] drm/i915: Turn off pipe gamma when it's not needed.
  2019-01-17 18:40   ` Matt Roper
@ 2019-01-17 18:48     ` Ville Syrjälä
  0 siblings, 0 replies; 52+ messages in thread
From: Ville Syrjälä @ 2019-01-17 18:48 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Thu, Jan 17, 2019 at 10:40:23AM -0800, Matt Roper wrote:
> On Fri, Jan 11, 2019 at 07:08:21PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The pipe internal precision is higher than what we currently program to
> > the degamma/gamma LUTs. We can get a higher quality image by bypassing
> > the LUTs when they're not needed. Let's do that.
> > 
> > Each plane has its own control bit for this, so we have to update
> > all active planes. The way we've done this we don't actually have
> > to run through the whole .check_plane() thing. And we actually
> > do the .color_check() after .check_plane() so we couldn't even do
> > that without shuffling the code around.
> > 
> > Additionally on pre-skl we have to update the primary plane regardless
> > of whether it's active or not on account of the primayr plane gamma
> 
> s/primayr/primary/
> 
> > enable bit also affecting the pipe bottom color.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_color.c | 55 ++++++++++++++++++++++++++++--
> >  1 file changed, 53 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> > index 8d7ea902a34b..a8b7428a64bf 100644
> > --- a/drivers/gpu/drm/i915/intel_color.c
> > +++ b/drivers/gpu/drm/i915/intel_color.c
> > @@ -633,27 +633,78 @@ void intel_color_commit(const struct intel_crtc_state *crtc_state)
> >  	dev_priv->display.color_commit(crtc_state);
> >  }
> >  
> > +static bool need_plane_update(struct intel_plane *plane,
> > +			      const struct intel_crtc_state *crtc_state)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > +
> > +	/*
> > +	 * On pre-SKL the pipe gamma enable and pipe csc enable for
> > +	 * the pipe bottom color are configured via the primary plane.
> > +	 * We have to reconfigure that even if the plane is inactive.
> > +	 */
> > +	return crtc_state->active_planes & BIT(plane->id) ||
> > +		(INTEL_GEN(dev_priv) < 9 &&
> > +		 plane->id == PLANE_PRIMARY);
> > +}
> > +
> > +static int
> > +intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
> > +{
> > +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	struct intel_atomic_state *state =
> > +		to_intel_atomic_state(new_crtc_state->base.state);
> > +	const struct intel_crtc_state *old_crtc_state =
> > +		intel_atomic_get_old_crtc_state(state, crtc);
> > +	struct intel_plane *plane;
> > +
> > +	if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable)
> > +		return 0;
> > +
> > +	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> > +		struct intel_plane_state *plane_state;
> > +
> > +		if (!need_plane_update(plane, new_crtc_state))
> > +			continue;
> > +
> > +		plane_state = intel_atomic_get_plane_state(state, plane);
> > +		if (IS_ERR(plane_state))
> > +			return PTR_ERR(plane_state);
> > +
> > +		new_crtc_state->update_planes |= BIT(plane->id);
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> >  int intel_color_check(struct intel_crtc_state *crtc_state)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> >  	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> >  	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
> >  	size_t gamma_length, degamma_length;
> > +	int ret;
> >  
> >  	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> >  	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> >  
> > -	crtc_state->gamma_enable = true;
> > +	crtc_state->gamma_enable = gamma_lut || degamma_lut;
> >  
> >  	if (INTEL_GEN(dev_priv) >= 9 ||
> >  	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> >  		crtc_state->csc_enable = true;
> >  
> > +	ret = intel_color_add_affected_planes(crtc_state);
> > +	if (ret)
> > +		return ret;
> > +
> >  	/*
> >  	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
> >  	 * size (256 entries).
> >  	 */
> > -	if (crtc_state_is_legacy_gamma(crtc_state)) {
> > +	if (!crtc_state->gamma_enable ||
> > +	    crtc_state_is_legacy_gamma(crtc_state)) {
> >  		crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> 
> If none of our planes are actually using the gamma, what does switching
> back to 8bit mode do for us?

Hopefilly nothing. Just a matter of selecting something for
consistency.

> 
> Regardless,
> 
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> 
> 
> >  		return 0;
> >  	}
> > -- 
> > 2.19.2
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* [PATCH 12/13] drm/i915: Turn off pipe CSC when it's not needed
  2019-01-11 17:08 [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8 Ville Syrjala
                   ` (10 preceding siblings ...)
  2019-01-11 17:08 ` [PATCH 11/13] drm/i915: Turn off pipe gamma when it's not needed Ville Syrjala
@ 2019-01-11 17:08 ` Ville Syrjala
  2019-01-17  5:37   ` Shankar, Uma
  2019-01-17 18:54   ` Matt Roper
  2019-01-11 17:08 ` [PATCH 13/13] drm/i915: Disable pipe gamma when C8 pixel format is used Ville Syrjala
                   ` (3 subsequent siblings)
  15 siblings, 2 replies; 52+ messages in thread
From: Ville Syrjala @ 2019-01-11 17:08 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

As with pipe gamma we can avoid the potential precision loss from
the pipe csc unit when there is no need to use it. And again
we need the same logic for updating the planes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_color.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index a8b7428a64bf..789b04bb51d2 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -659,7 +659,8 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
 		intel_atomic_get_old_crtc_state(state, crtc);
 	struct intel_plane *plane;
 
-	if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable)
+	if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
+	    new_crtc_state->csc_enable == old_crtc_state->csc_enable)
 		return 0;
 
 	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
@@ -684,6 +685,7 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
 	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
 	size_t gamma_length, degamma_length;
+	bool limited_color_range = false;
 	int ret;
 
 	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
@@ -693,7 +695,11 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
 
 	if (INTEL_GEN(dev_priv) >= 9 ||
 	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
-		crtc_state->csc_enable = true;
+		limited_color_range = crtc_state->limited_color_range;
+
+	crtc_state->csc_enable =
+		crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
+		crtc_state->base.ctm || limited_color_range;
 
 	ret = intel_color_add_affected_planes(crtc_state);
 	if (ret)
-- 
2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 52+ messages in thread

* Re: [PATCH 12/13] drm/i915: Turn off pipe CSC when it's not needed
  2019-01-11 17:08 ` [PATCH 12/13] drm/i915: Turn off pipe CSC " Ville Syrjala
@ 2019-01-17  5:37   ` Shankar, Uma
  2019-01-17 18:54   ` Matt Roper
  1 sibling, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-01-17  5:37 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx



>-----Original Message-----
>From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
>Sent: Friday, January 11, 2019 10:38 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma <uma.shankar@intel.com>; Roper, Matthew D
><matthew.d.roper@intel.com>
>Subject: [PATCH 12/13] drm/i915: Turn off pipe CSC when it's not needed
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>As with pipe gamma we can avoid the potential precision loss from the pipe csc
>unit when there is no need to use it. And again we need the same logic for
>updating the planes.

Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/intel_color.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_color.c
>b/drivers/gpu/drm/i915/intel_color.c
>index a8b7428a64bf..789b04bb51d2 100644
>--- a/drivers/gpu/drm/i915/intel_color.c
>+++ b/drivers/gpu/drm/i915/intel_color.c
>@@ -659,7 +659,8 @@ intel_color_add_affected_planes(struct intel_crtc_state
>*new_crtc_state)
> 		intel_atomic_get_old_crtc_state(state, crtc);
> 	struct intel_plane *plane;
>
>-	if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable)
>+	if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable
>&&
>+	    new_crtc_state->csc_enable == old_crtc_state->csc_enable)
> 		return 0;
>
> 	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { @@ -684,6
>+685,7 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
> 	const struct drm_property_blob *gamma_lut = crtc_state-
>>base.gamma_lut;
> 	const struct drm_property_blob *degamma_lut = crtc_state-
>>base.degamma_lut;
> 	size_t gamma_length, degamma_length;
>+	bool limited_color_range = false;
> 	int ret;
>
> 	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>@@ -693,7 +695,11 @@ int intel_color_check(struct intel_crtc_state
>*crtc_state)
>
> 	if (INTEL_GEN(dev_priv) >= 9 ||
> 	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
>-		crtc_state->csc_enable = true;
>+		limited_color_range = crtc_state->limited_color_range;
>+
>+	crtc_state->csc_enable =
>+		crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
>+		crtc_state->base.ctm || limited_color_range;
>
> 	ret = intel_color_add_affected_planes(crtc_state);
> 	if (ret)
>--
>2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 12/13] drm/i915: Turn off pipe CSC when it's not needed
  2019-01-11 17:08 ` [PATCH 12/13] drm/i915: Turn off pipe CSC " Ville Syrjala
  2019-01-17  5:37   ` Shankar, Uma
@ 2019-01-17 18:54   ` Matt Roper
  1 sibling, 0 replies; 52+ messages in thread
From: Matt Roper @ 2019-01-17 18:54 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Jan 11, 2019 at 07:08:22PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> As with pipe gamma we can avoid the potential precision loss from
> the pipe csc unit when there is no need to use it. And again
> we need the same logic for updating the planes.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_color.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index a8b7428a64bf..789b04bb51d2 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -659,7 +659,8 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
>  		intel_atomic_get_old_crtc_state(state, crtc);
>  	struct intel_plane *plane;
>  
> -	if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable)
> +	if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
> +	    new_crtc_state->csc_enable == old_crtc_state->csc_enable)
>  		return 0;
>  
>  	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> @@ -684,6 +685,7 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
>  	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
>  	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
>  	size_t gamma_length, degamma_length;
> +	bool limited_color_range = false;
>  	int ret;
>  
>  	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> @@ -693,7 +695,11 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
>  
>  	if (INTEL_GEN(dev_priv) >= 9 ||
>  	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> -		crtc_state->csc_enable = true;
> +		limited_color_range = crtc_state->limited_color_range;
> +
> +	crtc_state->csc_enable =
> +		crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
> +		crtc_state->base.ctm || limited_color_range;
>  
>  	ret = intel_color_add_affected_planes(crtc_state);
>  	if (ret)
> -- 
> 2.19.2
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* [PATCH 13/13] drm/i915: Disable pipe gamma when C8 pixel format is used
  2019-01-11 17:08 [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8 Ville Syrjala
                   ` (11 preceding siblings ...)
  2019-01-11 17:08 ` [PATCH 12/13] drm/i915: Turn off pipe CSC " Ville Syrjala
@ 2019-01-11 17:08 ` Ville Syrjala
  2019-01-17  5:58   ` Shankar, Uma
  2019-01-17 19:13   ` Matt Roper
  2019-01-11 17:25 ` ✗ Fi.CI.CHECKPATCH: warning for Enable/disable gamma/csc dynamically and fix C8 Patchwork
                   ` (2 subsequent siblings)
  15 siblings, 2 replies; 52+ messages in thread
From: Ville Syrjala @ 2019-01-11 17:08 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Planes scanning out C8 will want to use the legacy lut as
their palette. That means the LUT content are unikely to
be useful for gamma correction on other planes. Thus we
should disable pipe gamma for all the other planes. And
we should reject any non legacy LUT configurations when
C8 planes are present.

Fixes the appearance of the hw cursor when running
X -depth 8.

Note that CHV with it's independent CGM degamma/gamma LUTs
could probably use the CGM for gamma correction even when
the legacy LUT is used for C8. But that would require a
new uapi for configuring the legacy LUT and CGM LUTs at
the same time. Totally not worth it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_atomic_plane.c | 5 +++++
 drivers/gpu/drm/i915/intel_color.c        | 8 +++++++-
 drivers/gpu/drm/i915/intel_drv.h          | 1 +
 3 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 50be2c5dd76e..f311763867c4 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -119,6 +119,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 
 	new_crtc_state->active_planes &= ~BIT(plane->id);
 	new_crtc_state->nv12_planes &= ~BIT(plane->id);
+	new_crtc_state->c8_planes &= ~BIT(plane->id);
 	new_plane_state->base.visible = false;
 
 	if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
@@ -136,6 +137,10 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 	    new_plane_state->base.fb->format->format == DRM_FORMAT_NV12)
 		new_crtc_state->nv12_planes |= BIT(plane->id);
 
+	if (new_plane_state->base.visible &&
+	    new_plane_state->base.fb->format->format == DRM_FORMAT_C8)
+		new_crtc_state->c8_planes |= BIT(plane->id);
+
 	if (new_plane_state->base.visible || old_plane_state->base.visible)
 		new_crtc_state->update_planes |= BIT(plane->id);
 
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 789b04bb51d2..c8d12653d77f 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -691,7 +691,13 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
 	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 
-	crtc_state->gamma_enable = gamma_lut || degamma_lut;
+	/* C8 needs the legacy LUT all to itself */
+	if (crtc_state->c8_planes &&
+	    !crtc_state_is_legacy_gamma(crtc_state))
+		return -EINVAL;
+
+	crtc_state->gamma_enable = (gamma_lut || degamma_lut) &&
+		!crtc_state->c8_planes;
 
 	if (INTEL_GEN(dev_priv) >= 9 ||
 	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a4496f799af3..4d9ea05a6825 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -930,6 +930,7 @@ struct intel_crtc_state {
 	/* bitmask of visible planes (enum plane_id) */
 	u8 active_planes;
 	u8 nv12_planes;
+	u8 c8_planes;
 
 	/* bitmask of planes that will be updated during the commit */
 	u8 update_planes;
-- 
2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 52+ messages in thread

* Re: [PATCH 13/13] drm/i915: Disable pipe gamma when C8 pixel format is used
  2019-01-11 17:08 ` [PATCH 13/13] drm/i915: Disable pipe gamma when C8 pixel format is used Ville Syrjala
@ 2019-01-17  5:58   ` Shankar, Uma
  2019-01-17 19:13   ` Matt Roper
  1 sibling, 0 replies; 52+ messages in thread
From: Shankar, Uma @ 2019-01-17  5:58 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx



>-----Original Message-----
>From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
>Sent: Friday, January 11, 2019 10:38 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma <uma.shankar@intel.com>; Roper, Matthew D
><matthew.d.roper@intel.com>
>Subject: [PATCH 13/13] drm/i915: Disable pipe gamma when C8 pixel format is
>used
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Planes scanning out C8 will want to use the legacy lut as their palette. That means
>the LUT content are unikely to be useful for gamma correction on other planes.

Typo in unlikely.

With this fixed.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>Thus we should disable pipe gamma for all the other planes. And we should reject
>any non legacy LUT configurations when
>C8 planes are present.
>
>Fixes the appearance of the hw cursor when running X -depth 8.
>
>Note that CHV with it's independent CGM degamma/gamma LUTs could probably
>use the CGM for gamma correction even when the legacy LUT is used for C8. But
>that would require a new uapi for configuring the legacy LUT and CGM LUTs at
>the same time. Totally not worth it.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/intel_atomic_plane.c | 5 +++++
> drivers/gpu/drm/i915/intel_color.c        | 8 +++++++-
> drivers/gpu/drm/i915/intel_drv.h          | 1 +
> 3 files changed, 13 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
>b/drivers/gpu/drm/i915/intel_atomic_plane.c
>index 50be2c5dd76e..f311763867c4 100644
>--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
>+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
>@@ -119,6 +119,7 @@ int intel_plane_atomic_check_with_state(const struct
>intel_crtc_state *old_crtc_
>
> 	new_crtc_state->active_planes &= ~BIT(plane->id);
> 	new_crtc_state->nv12_planes &= ~BIT(plane->id);
>+	new_crtc_state->c8_planes &= ~BIT(plane->id);
> 	new_plane_state->base.visible = false;
>
> 	if (!new_plane_state->base.crtc && !old_plane_state->base.crtc) @@ -
>136,6 +137,10 @@ int intel_plane_atomic_check_with_state(const struct
>intel_crtc_state *old_crtc_
> 	    new_plane_state->base.fb->format->format == DRM_FORMAT_NV12)
> 		new_crtc_state->nv12_planes |= BIT(plane->id);
>
>+	if (new_plane_state->base.visible &&
>+	    new_plane_state->base.fb->format->format == DRM_FORMAT_C8)
>+		new_crtc_state->c8_planes |= BIT(plane->id);
>+
> 	if (new_plane_state->base.visible || old_plane_state->base.visible)
> 		new_crtc_state->update_planes |= BIT(plane->id);
>
>diff --git a/drivers/gpu/drm/i915/intel_color.c
>b/drivers/gpu/drm/i915/intel_color.c
>index 789b04bb51d2..c8d12653d77f 100644
>--- a/drivers/gpu/drm/i915/intel_color.c
>+++ b/drivers/gpu/drm/i915/intel_color.c
>@@ -691,7 +691,13 @@ int intel_color_check(struct intel_crtc_state
>*crtc_state)
> 	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> 	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>
>-	crtc_state->gamma_enable = gamma_lut || degamma_lut;
>+	/* C8 needs the legacy LUT all to itself */
>+	if (crtc_state->c8_planes &&
>+	    !crtc_state_is_legacy_gamma(crtc_state))
>+		return -EINVAL;
>+
>+	crtc_state->gamma_enable = (gamma_lut || degamma_lut) &&
>+		!crtc_state->c8_planes;
>
> 	if (INTEL_GEN(dev_priv) >= 9 ||
> 	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) diff --git
>a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>index a4496f799af3..4d9ea05a6825 100644
>--- a/drivers/gpu/drm/i915/intel_drv.h
>+++ b/drivers/gpu/drm/i915/intel_drv.h
>@@ -930,6 +930,7 @@ struct intel_crtc_state {
> 	/* bitmask of visible planes (enum plane_id) */
> 	u8 active_planes;
> 	u8 nv12_planes;
>+	u8 c8_planes;
>
> 	/* bitmask of planes that will be updated during the commit */
> 	u8 update_planes;
>--
>2.19.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 13/13] drm/i915: Disable pipe gamma when C8 pixel format is used
  2019-01-11 17:08 ` [PATCH 13/13] drm/i915: Disable pipe gamma when C8 pixel format is used Ville Syrjala
  2019-01-17  5:58   ` Shankar, Uma
@ 2019-01-17 19:13   ` Matt Roper
  2019-01-17 19:27     ` Ville Syrjälä
  1 sibling, 1 reply; 52+ messages in thread
From: Matt Roper @ 2019-01-17 19:13 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Jan 11, 2019 at 07:08:23PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Planes scanning out C8 will want to use the legacy lut as
> their palette. That means the LUT content are unikely to
> be useful for gamma correction on other planes. Thus we
> should disable pipe gamma for all the other planes. And
> we should reject any non legacy LUT configurations when
> C8 planes are present.
> 
> Fixes the appearance of the hw cursor when running
> X -depth 8.
> 
> Note that CHV with it's independent CGM degamma/gamma LUTs
> could probably use the CGM for gamma correction even when
> the legacy LUT is used for C8. But that would require a
> new uapi for configuring the legacy LUT and CGM LUTs at
> the same time. Totally not worth it.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_atomic_plane.c | 5 +++++
>  drivers/gpu/drm/i915/intel_color.c        | 8 +++++++-
>  drivers/gpu/drm/i915/intel_drv.h          | 1 +
>  3 files changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 50be2c5dd76e..f311763867c4 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -119,6 +119,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
>  
>  	new_crtc_state->active_planes &= ~BIT(plane->id);
>  	new_crtc_state->nv12_planes &= ~BIT(plane->id);
> +	new_crtc_state->c8_planes &= ~BIT(plane->id);
>  	new_plane_state->base.visible = false;
>  
>  	if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
> @@ -136,6 +137,10 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
>  	    new_plane_state->base.fb->format->format == DRM_FORMAT_NV12)
>  		new_crtc_state->nv12_planes |= BIT(plane->id);
>  
> +	if (new_plane_state->base.visible &&
> +	    new_plane_state->base.fb->format->format == DRM_FORMAT_C8)
> +		new_crtc_state->c8_planes |= BIT(plane->id);
> +
>  	if (new_plane_state->base.visible || old_plane_state->base.visible)
>  		new_crtc_state->update_planes |= BIT(plane->id);
>  
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 789b04bb51d2..c8d12653d77f 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -691,7 +691,13 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
>  	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>  	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>  
> -	crtc_state->gamma_enable = gamma_lut || degamma_lut;
> +	/* C8 needs the legacy LUT all to itself */
> +	if (crtc_state->c8_planes &&
> +	    !crtc_state_is_legacy_gamma(crtc_state))
> +		return -EINVAL;
> +
> +	crtc_state->gamma_enable = (gamma_lut || degamma_lut) &&
> +		!crtc_state->c8_planes;

It's not really clear to me from the bspec...the legacy gamma will still
get used as the c8 palette even when the pipe gamma enable bit is off
for the plane?  If so,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

>  
>  	if (INTEL_GEN(dev_priv) >= 9 ||
>  	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index a4496f799af3..4d9ea05a6825 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -930,6 +930,7 @@ struct intel_crtc_state {
>  	/* bitmask of visible planes (enum plane_id) */
>  	u8 active_planes;
>  	u8 nv12_planes;
> +	u8 c8_planes;
>  
>  	/* bitmask of planes that will be updated during the commit */
>  	u8 update_planes;
> -- 
> 2.19.2
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* Re: [PATCH 13/13] drm/i915: Disable pipe gamma when C8 pixel format is used
  2019-01-17 19:13   ` Matt Roper
@ 2019-01-17 19:27     ` Ville Syrjälä
  0 siblings, 0 replies; 52+ messages in thread
From: Ville Syrjälä @ 2019-01-17 19:27 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Thu, Jan 17, 2019 at 11:13:58AM -0800, Matt Roper wrote:
> On Fri, Jan 11, 2019 at 07:08:23PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Planes scanning out C8 will want to use the legacy lut as
> > their palette. That means the LUT content are unikely to
> > be useful for gamma correction on other planes. Thus we
> > should disable pipe gamma for all the other planes. And
> > we should reject any non legacy LUT configurations when
> > C8 planes are present.
> > 
> > Fixes the appearance of the hw cursor when running
> > X -depth 8.
> > 
> > Note that CHV with it's independent CGM degamma/gamma LUTs
> > could probably use the CGM for gamma correction even when
> > the legacy LUT is used for C8. But that would require a
> > new uapi for configuring the legacy LUT and CGM LUTs at
> > the same time. Totally not worth it.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_atomic_plane.c | 5 +++++
> >  drivers/gpu/drm/i915/intel_color.c        | 8 +++++++-
> >  drivers/gpu/drm/i915/intel_drv.h          | 1 +
> >  3 files changed, 13 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
> > index 50be2c5dd76e..f311763867c4 100644
> > --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> > @@ -119,6 +119,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
> >  
> >  	new_crtc_state->active_planes &= ~BIT(plane->id);
> >  	new_crtc_state->nv12_planes &= ~BIT(plane->id);
> > +	new_crtc_state->c8_planes &= ~BIT(plane->id);
> >  	new_plane_state->base.visible = false;
> >  
> >  	if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
> > @@ -136,6 +137,10 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
> >  	    new_plane_state->base.fb->format->format == DRM_FORMAT_NV12)
> >  		new_crtc_state->nv12_planes |= BIT(plane->id);
> >  
> > +	if (new_plane_state->base.visible &&
> > +	    new_plane_state->base.fb->format->format == DRM_FORMAT_C8)
> > +		new_crtc_state->c8_planes |= BIT(plane->id);
> > +
> >  	if (new_plane_state->base.visible || old_plane_state->base.visible)
> >  		new_crtc_state->update_planes |= BIT(plane->id);
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> > index 789b04bb51d2..c8d12653d77f 100644
> > --- a/drivers/gpu/drm/i915/intel_color.c
> > +++ b/drivers/gpu/drm/i915/intel_color.c
> > @@ -691,7 +691,13 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
> >  	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> >  	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> >  
> > -	crtc_state->gamma_enable = gamma_lut || degamma_lut;
> > +	/* C8 needs the legacy LUT all to itself */
> > +	if (crtc_state->c8_planes &&
> > +	    !crtc_state_is_legacy_gamma(crtc_state))
> > +		return -EINVAL;
> > +
> > +	crtc_state->gamma_enable = (gamma_lut || degamma_lut) &&
> > +		!crtc_state->c8_planes;
> 
> It's not really clear to me from the bspec...the legacy gamma will still
> get used as the c8 palette even when the pipe gamma enable bit is off
> for the plane?

Yes. At least it did on all the platforms I tried, which IIRC
were quite a few.

> If so,
> 
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> 
> >  
> >  	if (INTEL_GEN(dev_priv) >= 9 ||
> >  	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index a4496f799af3..4d9ea05a6825 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -930,6 +930,7 @@ struct intel_crtc_state {
> >  	/* bitmask of visible planes (enum plane_id) */
> >  	u8 active_planes;
> >  	u8 nv12_planes;
> > +	u8 c8_planes;
> >  
> >  	/* bitmask of planes that will be updated during the commit */
> >  	u8 update_planes;
> > -- 
> > 2.19.2
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* ✗ Fi.CI.CHECKPATCH: warning for Enable/disable gamma/csc dynamically and fix C8
  2019-01-11 17:08 [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8 Ville Syrjala
                   ` (12 preceding siblings ...)
  2019-01-11 17:08 ` [PATCH 13/13] drm/i915: Disable pipe gamma when C8 pixel format is used Ville Syrjala
@ 2019-01-11 17:25 ` Patchwork
  2019-01-11 17:44 ` ✓ Fi.CI.BAT: success " Patchwork
  2019-01-11 22:03 ` ✓ Fi.CI.IGT: " Patchwork
  15 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2019-01-11 17:25 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

== Series Details ==

Series: Enable/disable gamma/csc dynamically and fix C8
URL   : https://patchwork.freedesktop.org/series/55081/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
066d50880adb drm/i915: Clean up intel_plane_atomic_check_with_state()
43cec2bfb86d drm/i915: Split the gamma/csc enable bits from the plane_ctl() function
c0564fda1b3b drm/i915: Precompute gamma_mode
9c79ce51c6e6 drm/i915: Constify the state arguments to the color management stuff
e4f2442c4803 drm/i915: Pull GAMMA_MODE write out from haswell_load_luts()
eb35618583b0 drm/i915: Split color mgmt based on single vs. double buffered registers
544c73d70496 drm/i915: Move LUT programming to happen after vblank waits
d957bacac7cd drm/i915: Populate gamma_mode for all platforms
-:34: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#34: FILE: drivers/gpu/drm/i915/i915_reg.h:5588:
+#define   PIPECONF_GAMMA_MODE(x)	((x)<<24) /* pass in GAMMA_MODE_MODE_* */
                                 	    ^

total: 0 errors, 0 warnings, 1 checks, 146 lines checked
7fb08d2ae464 drm/i915: Track pipe gamma enable/disable in crtc state
88de7f4faa5a drm/i915: Track pipe csc enable in crtc state
da7ea155c150 drm/i915: Turn off pipe gamma when it's not needed.
00cf0ace1712 drm/i915: Turn off pipe CSC when it's not needed
cb493c538af7 drm/i915: Disable pipe gamma when C8 pixel format is used

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* ✓ Fi.CI.BAT: success for Enable/disable gamma/csc dynamically and fix C8
  2019-01-11 17:08 [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8 Ville Syrjala
                   ` (13 preceding siblings ...)
  2019-01-11 17:25 ` ✗ Fi.CI.CHECKPATCH: warning for Enable/disable gamma/csc dynamically and fix C8 Patchwork
@ 2019-01-11 17:44 ` Patchwork
  2019-01-11 22:03 ` ✓ Fi.CI.IGT: " Patchwork
  15 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2019-01-11 17:44 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

== Series Details ==

Series: Enable/disable gamma/csc dynamically and fix C8
URL   : https://patchwork.freedesktop.org/series/55081/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5404 -> Patchwork_11280
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/55081/revisions/1/mbox/

Known issues
------------

  Here are the changes found in Patchwork_11280 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live_contexts:
    - fi-icl-u2:          NOTRUN -> DMESG-FAIL [fdo#108569]

  * igt@pm_rpm@basic-rte:
    - fi-bsw-kefka:       PASS -> FAIL [fdo#108800]

  
#### Possible fixes ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       FAIL [fdo#108767] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
  [fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316


Participating hosts (45 -> 40)
------------------------------

  Additional (3): fi-byt-j1900 fi-icl-u2 fi-hsw-peppy 
  Missing    (8): fi-kbl-soraka fi-ilk-m540 fi-bdw-5557u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-bdw-samus fi-skl-6600u 


Build changes
-------------

    * Linux: CI_DRM_5404 -> Patchwork_11280

  CI_DRM_5404: c51dc608699b2dcfe6d2f6981773f98d1b9f0c86 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4763: 805a99409542d7d72dda3b6dcd284a8869a3de16 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11280: cb493c538af7fb058a44b179ee6b9b771282ce3f @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

cb493c538af7 drm/i915: Disable pipe gamma when C8 pixel format is used
00cf0ace1712 drm/i915: Turn off pipe CSC when it's not needed
da7ea155c150 drm/i915: Turn off pipe gamma when it's not needed.
88de7f4faa5a drm/i915: Track pipe csc enable in crtc state
7fb08d2ae464 drm/i915: Track pipe gamma enable/disable in crtc state
d957bacac7cd drm/i915: Populate gamma_mode for all platforms
544c73d70496 drm/i915: Move LUT programming to happen after vblank waits
eb35618583b0 drm/i915: Split color mgmt based on single vs. double buffered registers
e4f2442c4803 drm/i915: Pull GAMMA_MODE write out from haswell_load_luts()
9c79ce51c6e6 drm/i915: Constify the state arguments to the color management stuff
c0564fda1b3b drm/i915: Precompute gamma_mode
43cec2bfb86d drm/i915: Split the gamma/csc enable bits from the plane_ctl() function
066d50880adb drm/i915: Clean up intel_plane_atomic_check_with_state()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11280/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

* ✓ Fi.CI.IGT: success for Enable/disable gamma/csc dynamically and fix C8
  2019-01-11 17:08 [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8 Ville Syrjala
                   ` (14 preceding siblings ...)
  2019-01-11 17:44 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-01-11 22:03 ` Patchwork
  15 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2019-01-11 22:03 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

== Series Details ==

Series: Enable/disable gamma/csc dynamically and fix C8
URL   : https://patchwork.freedesktop.org/series/55081/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5404_full -> Patchwork_11280_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_11280_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_schedule@pi-ringfull-render:
    - shard-skl:          NOTRUN -> FAIL [fdo#103158]

  * igt@kms_atomic_transition@plane-all-transition-nonblocking-fencing:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#107724] / [fdo#109225] +1

  * igt@kms_available_modes_crc@available_mode_test_crc:
    - shard-apl:          PASS -> FAIL [fdo#106641]
    - shard-skl:          NOTRUN -> FAIL [fdo#106641]

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#107956]
    - shard-hsw:          PASS -> DMESG-WARN [fdo#107956]

  * igt@kms_cursor_crc@cursor-256x256-random:
    - shard-glk:          PASS -> FAIL [fdo#103232] +20

  * igt@kms_cursor_crc@cursor-64x64-random:
    - shard-iclb:         NOTRUN -> FAIL [fdo#103232]

  * igt@kms_fbcon_fbt@psr:
    - shard-skl:          NOTRUN -> FAIL [fdo#107882]

  * igt@kms_flip@modeset-vs-vblank-race-interruptible:
    - shard-glk:          PASS -> FAIL [fdo#103060] +1

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
    - shard-apl:          PASS -> FAIL [fdo#103167] +1

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-glk:          PASS -> FAIL [fdo#103167] +2

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
    - shard-iclb:         PASS -> DMESG-FAIL [fdo#107724]

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +6

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
    - shard-iclb:         PASS -> FAIL [fdo#103167] +4

  * igt@kms_panel_fitting@legacy:
    - shard-skl:          NOTRUN -> FAIL [fdo#105456]

  * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#106885]
    - shard-iclb:         NOTRUN -> FAIL [fdo#108948]

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
    - shard-skl:          NOTRUN -> FAIL [fdo#108145] +2

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
    - shard-glk:          PASS -> FAIL [fdo#103166] +3
    - shard-iclb:         PASS -> FAIL [fdo#103166] +3

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-none:
    - shard-apl:          PASS -> FAIL [fdo#103166]

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
    - shard-iclb:         NOTRUN -> FAIL [fdo#103166]

  * igt@kms_rmfb@rmfb-ioctl:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#107724] +15

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-glk:          PASS -> DMESG-FAIL [fdo#105763] / [fdo#106538]

  * igt@kms_sysfs_edid_timing:
    - shard-iclb:         PASS -> FAIL [fdo#100047]

  * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
    - shard-iclb:         PASS -> INCOMPLETE [fdo#107713] +1

  * igt@pm_rpm@gem-pread:
    - shard-skl:          NOTRUN -> INCOMPLETE [fdo#107807] +1

  * igt@pm_rpm@system-suspend:
    - shard-iclb:         PASS -> INCOMPLETE [fdo#107713] / [fdo#108840]

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@vecs0-dirty-switch:
    - shard-apl:          INCOMPLETE [fdo#103927] -> PASS

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
    - shard-skl:          DMESG-WARN [fdo#107956] -> PASS

  * igt@kms_color@pipe-b-degamma:
    - shard-apl:          FAIL [fdo#104782] -> PASS

  * igt@kms_cursor_crc@cursor-128x128-random:
    - shard-skl:          FAIL [fdo#103232] -> PASS

  * igt@kms_cursor_crc@cursor-128x128-suspend:
    - shard-skl:          INCOMPLETE [fdo#104108] -> PASS

  * igt@kms_cursor_crc@cursor-64x21-random:
    - shard-apl:          FAIL [fdo#103232] -> PASS +2

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-iclb:         INCOMPLETE [fdo#107713] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-apl:          FAIL [fdo#103167] -> PASS +4

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
    - shard-iclb:         FAIL [fdo#103167] -> PASS +6

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-glk:          FAIL [fdo#103167] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
    - shard-iclb:         FAIL [fdo#105683] / [fdo#108040] -> PASS +1

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-render:
    - shard-skl:          FAIL [fdo#103167] -> PASS +4

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-skl:          INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS

  * igt@kms_plane@plane-position-covered-pipe-a-planes:
    - shard-iclb:         FAIL [fdo#103166] -> PASS +3

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          FAIL [fdo#107815] / [fdo#108145] -> PASS

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          FAIL [fdo#107815] -> PASS

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
    - shard-apl:          FAIL [fdo#103166] -> PASS

  * igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
    - shard-iclb:         DMESG-WARN [fdo#107724] -> PASS

  * igt@kms_setmode@basic:
    - shard-hsw:          FAIL [fdo#99912] -> PASS

  * igt@pm_rc6_residency@rc6-accuracy:
    - shard-snb:          {SKIP} [fdo#109271] -> PASS

  
#### Warnings ####

  * igt@i915_suspend@shrink:
    - shard-skl:          INCOMPLETE [fdo#106886] -> DMESG-WARN [fdo#107886] / [fdo#109244]

  * igt@kms_ccs@pipe-c-crc-primary-basic:
    - shard-iclb:         FAIL [fdo#107725] -> DMESG-WARN [fdo#107724] / [fdo#108336]

  * igt@kms_universal_plane@disable-primary-vs-flip-pipe-f:
    - shard-apl:          {SKIP} [fdo#109271] / [fdo#109278] -> INCOMPLETE [fdo#103927]

  * igt@pm_backlight@fade_with_suspend:
    - shard-skl:          INCOMPLETE [fdo#107773] -> FAIL [fdo#107847]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
  [fdo#105456]: https://bugs.freedesktop.org/show_bug.cgi?id=105456
  [fdo#105683]: https://bugs.freedesktop.org/show_bug.cgi?id=105683
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
  [fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
  [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
  [fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
  [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
  [fdo#107847]: https://bugs.freedesktop.org/show_bug.cgi?id=107847
  [fdo#107882]: https://bugs.freedesktop.org/show_bug.cgi?id=107882
  [fdo#107886]: https://bugs.freedesktop.org/show_bug.cgi?id=107886
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336
  [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
  [fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
  [fdo#109225]: https://bugs.freedesktop.org/show_bug.cgi?id=109225
  [fdo#109244]: https://bugs.freedesktop.org/show_bug.cgi?id=109244
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109277]: https://bugs.freedesktop.org/show_bug.cgi?id=109277
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109281]: https://bugs.freedesktop.org/show_bug.cgi?id=109281
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109286]: https://bugs.freedesktop.org/show_bug.cgi?id=109286
  [fdo#109287]: https://bugs.freedesktop.org/show_bug.cgi?id=109287
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109290]: https://bugs.freedesktop.org/show_bug.cgi?id=109290
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (7 -> 6)
------------------------------

  Missing    (1): shard-kbl 


Build changes
-------------

    * Linux: CI_DRM_5404 -> Patchwork_11280

  CI_DRM_5404: c51dc608699b2dcfe6d2f6981773f98d1b9f0c86 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4763: 805a99409542d7d72dda3b6dcd284a8869a3de16 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11280: cb493c538af7fb058a44b179ee6b9b771282ce3f @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11280/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 52+ messages in thread

end of thread, other threads:[~2019-01-29 15:59 UTC | newest]

Thread overview: 52+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-11 17:08 [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8 Ville Syrjala
2019-01-11 17:08 ` [PATCH 01/13] drm/i915: Clean up intel_plane_atomic_check_with_state() Ville Syrjala
2019-01-12  0:41   ` Matt Roper
2019-01-16 16:08   ` Shankar, Uma
2019-01-11 17:08 ` [PATCH 02/13] drm/i915: Split the gamma/csc enable bits from the plane_ctl() function Ville Syrjala
2019-01-12  0:41   ` Matt Roper
2019-01-14 17:11     ` Ville Syrjälä
2019-01-14 19:11       ` Ville Syrjälä
2019-01-16 17:11         ` Shankar, Uma
2019-01-17 16:34           ` Ville Syrjälä
2019-01-11 17:08 ` [PATCH 03/13] drm/i915: Precompute gamma_mode Ville Syrjala
2019-01-12  0:41   ` Matt Roper
2019-01-16 17:18     ` Shankar, Uma
2019-01-11 17:08 ` [PATCH 04/13] drm/i915: Constify the state arguments to the color management stuff Ville Syrjala
2019-01-12  0:42   ` Matt Roper
2019-01-16 17:21     ` Shankar, Uma
2019-01-11 17:08 ` [PATCH 05/13] drm/i915: Pull GAMMA_MODE write out from haswell_load_luts() Ville Syrjala
2019-01-12  0:57   ` Matt Roper
2019-01-16 17:26     ` Shankar, Uma
2019-01-11 17:08 ` [PATCH 06/13] drm/i915: Split color mgmt based on single vs. double buffered registers Ville Syrjala
2019-01-15  0:56   ` Matt Roper
2019-01-16 18:22     ` Shankar, Uma
2019-01-11 17:08 ` [PATCH 07/13] drm/i915: Move LUT programming to happen after vblank waits Ville Syrjala
2019-01-16 17:38   ` Matt Roper
2019-01-16 18:02     ` Ville Syrjälä
2019-01-17 15:00     ` Ville Syrjälä
2019-01-11 17:08 ` [PATCH 08/13] drm/i915: Populate gamma_mode for all platforms Ville Syrjala
2019-01-16 18:31   ` Matt Roper
2019-01-16 18:58     ` Ville Syrjälä
2019-01-16 19:51       ` Ville Syrjälä
2019-01-29 15:59         ` Ville Syrjälä
2019-01-11 17:08 ` [PATCH 09/13] drm/i915: Track pipe gamma enable/disable in crtc state Ville Syrjala
2019-01-16 19:36   ` Matt Roper
2019-01-17  5:14     ` Shankar, Uma
2019-01-17 14:57       ` Ville Syrjälä
2019-01-11 17:08 ` [PATCH 10/13] drm/i915: Track pipe csc enable " Ville Syrjala
2019-01-16 19:43   ` Matt Roper
2019-01-17  5:17     ` Shankar, Uma
2019-01-11 17:08 ` [PATCH 11/13] drm/i915: Turn off pipe gamma when it's not needed Ville Syrjala
2019-01-17  5:32   ` Shankar, Uma
2019-01-17 18:40   ` Matt Roper
2019-01-17 18:48     ` Ville Syrjälä
2019-01-11 17:08 ` [PATCH 12/13] drm/i915: Turn off pipe CSC " Ville Syrjala
2019-01-17  5:37   ` Shankar, Uma
2019-01-17 18:54   ` Matt Roper
2019-01-11 17:08 ` [PATCH 13/13] drm/i915: Disable pipe gamma when C8 pixel format is used Ville Syrjala
2019-01-17  5:58   ` Shankar, Uma
2019-01-17 19:13   ` Matt Roper
2019-01-17 19:27     ` Ville Syrjälä
2019-01-11 17:25 ` ✗ Fi.CI.CHECKPATCH: warning for Enable/disable gamma/csc dynamically and fix C8 Patchwork
2019-01-11 17:44 ` ✓ Fi.CI.BAT: success " Patchwork
2019-01-11 22:03 ` ✓ Fi.CI.IGT: " Patchwork

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