[PATCH 0/9] pinctrl: tegra: Support SFIO/GPIO programming

[PATCH 0/9] pinctrl: tegra: Support SFIO/GPIO programming

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Hi,

NVIDIA Tegra186 and later have a bit in the pin controller that defines
whether a pin is used in special function (SFIO) mode or in general
purpose (GPIO) mode. On early Tegra SoC generations, this bit was part
of the GPIO controller.

The pin configuration on Tegra186 and later (and partially on Tegra210)
is typically static, so there is little need to reconfigure these pins.
However, there's a special case on Tegra194 where the PCIe CLKREQ and
RST pins for controller 5 may need to be reprogrammed in the kernel,
depending on whether the controller runs in endpoint mode or in root
port mode.

This series of patches establishes the mapping of these two pins to
their GPIO equivalents and implements the code necessary to switch
between SFIO and GPIO modes when the kernel requests or releases the
GPIOs, respectively.

Thierry

Thierry Reding (9):
  gpio: Support GPIO controllers without pin-ranges
  gpio: tegra186: Add support for pin ranges
  gpio: tegra186: Add Tegra194 pin ranges for GG.0 and GG.1
  pinctrl: tegra: Fix whitespace issues for improved readability
  pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo
  pinctrl: tegra: Pass struct tegra_pmx for pin range check
  pinctrl: tegra: Do not add default pin range on Tegra194
  pinctrl: tegra: Renumber the GG.0 and GG.1 pins
  pinctrl: tegra: Add SFIO/GPIO programming on Tegra194

 drivers/gpio/gpio-tegra186.c             | 64 ++++++++++++++++++++++++
 drivers/gpio/gpiolib.c                   |  5 +-
 drivers/pinctrl/tegra/pinctrl-tegra.c    | 52 +++++++++++++++++--
 drivers/pinctrl/tegra/pinctrl-tegra.h    |  5 +-
 drivers/pinctrl/tegra/pinctrl-tegra194.c | 47 +++++++++--------
 5 files changed, 144 insertions(+), 29 deletions(-)

-- 
2.24.1

[PATCH 1/9] gpio: Support GPIO controllers without pin-ranges

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Wake gpiochip_generic_request() call into the pinctrl helpers only if a
GPIO controller had any pin-ranges assigned to it. This allows a driver
to unconditionally use this helper if it supports multiple devices of
which only a subset have pin-ranges assigned to them.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpio/gpiolib.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index f31b1d46599e..12f3c339da78 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -2792,7 +2792,10 @@ static inline void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip)
  */
 int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset)
 {
-	return pinctrl_gpio_request(chip->gpiodev->base + offset);
+	if (!list_empty(&chip->gpiodev->pin_ranges))
+		return pinctrl_gpio_request(chip->gpiodev->base + offset);
+
+	return 0;
 }
 EXPORT_SYMBOL_GPL(gpiochip_generic_request);
 
-- 
2.24.1

[PATCH 2/9] gpio: tegra186: Add support for pin ranges

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Add support for Tegra SoC generations to specify a list of pin ranges
that map GPIOs to ranges of pins in the pin controller.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpio/gpio-tegra186.c | 56 ++++++++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c
index de241263d4be..1086c1fcaf49 100644
--- a/drivers/gpio/gpio-tegra186.c
+++ b/drivers/gpio/gpio-tegra186.c
@@ -58,11 +58,20 @@ struct tegra_gpio_port {
 	unsigned int pins;
 };
 
+struct tegra186_pin_range {
+	unsigned int offset;
+	const char *group;
+};
+
 struct tegra_gpio_soc {
 	const struct tegra_gpio_port *ports;
 	unsigned int num_ports;
 	const char *name;
 	unsigned int instance;
+
+	const struct tegra186_pin_range *pin_ranges;
+	unsigned int num_pin_ranges;
+	const char *pinmux;
 };
 
 struct tegra_gpio {
@@ -254,6 +263,50 @@ static int tegra186_gpio_set_config(struct gpio_chip *chip,
 	return 0;
 }
 
+static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
+{
+	struct tegra_gpio *gpio = gpiochip_get_data(chip);
+	struct pinctrl_dev *pctldev;
+	struct device_node *np;
+	unsigned int i, j;
+	int err;
+
+	if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
+		return 0;
+
+	np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
+	if (!np)
+		return -ENODEV;
+
+	pctldev = of_pinctrl_get(np);
+	of_node_put(np);
+	if (!pctldev)
+		return -EPROBE_DEFER;
+
+	for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
+		unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
+		const char *group = gpio->soc->pin_ranges[i].group;
+
+		port = pin / 8;
+		pin = pin % 8;
+
+		if (port >= gpio->soc->num_ports) {
+			dev_warn(chip->parent, "invalid port %u for %s\n",
+				 port, group);
+			continue;
+		}
+
+		for (j = 0; j < port; j++)
+			pin += gpio->soc->ports[j].pins;
+
+		err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
+		if (err < 0)
+			return err;
+	}
+
+	return 0;
+}
+
 static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
 				  const struct of_phandle_args *spec,
 				  u32 *flags)
@@ -578,12 +631,15 @@ static int tegra186_gpio_probe(struct platform_device *pdev)
 	gpio->gpio.label = gpio->soc->name;
 	gpio->gpio.parent = &pdev->dev;
 
+	gpio->gpio.request = gpiochip_generic_request;
+	gpio->gpio.free = gpiochip_generic_free;
 	gpio->gpio.get_direction = tegra186_gpio_get_direction;
 	gpio->gpio.direction_input = tegra186_gpio_direction_input;
 	gpio->gpio.direction_output = tegra186_gpio_direction_output;
 	gpio->gpio.get = tegra186_gpio_get,
 	gpio->gpio.set = tegra186_gpio_set;
 	gpio->gpio.set_config = tegra186_gpio_set_config;
+	gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
 
 	gpio->gpio.base = -1;
 
-- 
2.24.1

[PATCH 3/9] gpio: tegra186: Add Tegra194 pin ranges for GG.0 and GG.1

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

The GG.0 and GG.1 GPIOs serve as CLKREQ and RST pins, respectively, for
PCIe controller 5 on Tegra194. When this controller is configured in
endpoint mode, these pins need to be used as GPIOs by the PCIe endpoint
driver. Typically the mode programming of these pins (GPIO vs. SFIO) is
performed by early boot firmware to ensure that the configuration is
consistent.

However, the GG.0 and GG.1 pins are part of a special power partition
that is not enabled during early boot, and hence the early boot firmware
cannot program these pins to be GPIOs (they are SFIO by default). Adding
them as pin ranges for the pin controller allows the pin controller to
be involved when these pins are requested as GPIOs and allows the proper
programming to take place.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpio/gpio-tegra186.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c
index 1086c1fcaf49..79b553dc39a3 100644
--- a/drivers/gpio/gpio-tegra186.c
+++ b/drivers/gpio/gpio-tegra186.c
@@ -839,11 +839,19 @@ static const struct tegra_gpio_port tegra194_main_ports[] = {
 	TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
 };
 
+static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
+	{ TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
+	{ TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
+};
+
 static const struct tegra_gpio_soc tegra194_main_soc = {
 	.num_ports = ARRAY_SIZE(tegra194_main_ports),
 	.ports = tegra194_main_ports,
 	.name = "tegra194-gpio",
 	.instance = 0,
+	.num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
+	.pin_ranges = tegra194_main_pin_ranges,
+	.pinmux = "nvidia,tegra194-pinmux",
 };
 
 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins)	\
-- 
2.24.1

[PATCH 4/9] pinctrl: tegra: Fix whitespace issues for improved readability

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Fix a few whitespace inconsistencies to make the code easier to read.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/pinctrl/tegra/pinctrl-tegra194.c | 33 ++++++++++++------------
 1 file changed, 17 insertions(+), 16 deletions(-)

diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c
index daf44cf240c9..d4e84530158c 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra194.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c
@@ -59,6 +59,7 @@ enum tegra_mux_dt {
 	{					\
 		.name = #lid,			\
 	}
+
 static struct tegra_function tegra194_functions[] = {
 	TEGRA_PIN_FUNCTION(rsvd0),
 	TEGRA_PIN_FUNCTION(rsvd1),
@@ -70,7 +71,7 @@ static struct tegra_function tegra194_functions[] = {
 #define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b,	\
 			     drvup_w, slwr_b, slwr_w, slwf_b,	\
 			     slwf_w, bank)			\
-		.drv_reg = ((r)),			\
+		.drv_reg = ((r)),				\
 		.drv_bank = bank,				\
 		.drvdn_bit = drvdn_b,				\
 		.drvdn_width = drvdn_w,				\
@@ -89,7 +90,7 @@ static struct tegra_function tegra194_functions[] = {
 		.hsm_bit = -1,					\
 		.mux_bank = bank,				\
 		.mux_bit = 0,					\
-		.pupd_reg = ((r)),		\
+		.pupd_reg = ((r)),				\
 		.pupd_bank = bank,				\
 		.pupd_bit = 2,					\
 		.tri_reg = ((r)),				\
@@ -109,20 +110,20 @@ static struct tegra_function tegra194_functions[] = {
 
 #define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_lpbk,	\
 		 e_input, e_lpdr, e_od, schmitt_b, drvtype, io_rail)	\
-	{							\
-		.name = #pg_name,				\
-		.pins = pg_name##_pins,				\
-		.npins = ARRAY_SIZE(pg_name##_pins),		\
-			.funcs = {				\
-				TEGRA_MUX_##f0,			\
-				TEGRA_MUX_##f1,			\
-				TEGRA_MUX_##f2,			\
-				TEGRA_MUX_##f3,			\
-			},					\
-		PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk,	\
-				     e_input, e_od,		\
-				     schmitt_b, drvtype),	\
-		drive_##pg_name,				\
+	{								\
+		.name = #pg_name,					\
+		.pins = pg_name##_pins,					\
+		.npins = ARRAY_SIZE(pg_name##_pins),			\
+			.funcs = {					\
+				TEGRA_MUX_##f0,				\
+				TEGRA_MUX_##f1,				\
+				TEGRA_MUX_##f2,				\
+				TEGRA_MUX_##f3,				\
+			},						\
+		PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk,		\
+				     e_input, e_od,			\
+				     schmitt_b, drvtype),		\
+		drive_##pg_name,					\
 	}
 
 static const struct tegra_pingroup tegra194_groups[] = {
-- 
2.24.1

[PATCH 5/9] pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Properly spell "Schmitt" in the kerneldoc for pin group definitions.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/pinctrl/tegra/pinctrl-tegra.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h
index 0fc82eea9cf1..520865979d4a 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.h
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.h
@@ -107,7 +107,7 @@ struct tegra_function {
  *			drvup, slwr, slwf, and drvtype parameters.
  * @drv_bank:		Drive fields register bank.
  * @hsm_bit:		High Speed Mode register bit.
- * @schmitt_bit:	Scmitt register bit.
+ * @schmitt_bit:	Schmitt register bit.
  * @lpmd_bit:		Low Power Mode register bit.
  * @drvdn_bit:		Drive Down register bit.
  * @drvdn_width:	Drive Down field width.
-- 
2.24.1

[PATCH 6/9] pinctrl: tegra: Pass struct tegra_pmx for pin range check

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Pass the struct tegra_pmx when checking for the pin range in device
tree. This makes the call site a bit easier to read and will help keep
that readability in a subsequent patch.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/pinctrl/tegra/pinctrl-tegra.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index cefbbb8d1a68..c8246cc2c4fd 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -689,12 +689,12 @@ const struct dev_pm_ops tegra_pinctrl_pm = {
 	.resume = &tegra_pinctrl_resume
 };
 
-static bool gpio_node_has_range(const char *compatible)
+static bool tegra_pinctrl_gpio_node_has_range(struct tegra_pmx *pmx)
 {
 	struct device_node *np;
 	bool has_prop = false;
 
-	np = of_find_compatible_node(NULL, NULL, compatible);
+	np = of_find_compatible_node(NULL, NULL, pmx->soc->gpio_compatible);
 	if (!np)
 		return has_prop;
 
@@ -794,7 +794,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
 
 	tegra_pinctrl_clear_parked_bits(pmx);
 
-	if (!gpio_node_has_range(pmx->soc->gpio_compatible))
+	if (!tegra_pinctrl_gpio_node_has_range(pmx))
 		pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
 
 	platform_set_drvdata(pdev, pmx);
-- 
2.24.1

[PATCH 7/9] pinctrl: tegra: Do not add default pin range on Tegra194

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

On Tegra194, almost all of the pin control programming happens in early
boot firmware, so there is no use in having a pin range defined for all
the pins.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/pinctrl/tegra/pinctrl-tegra.c    | 2 +-
 drivers/pinctrl/tegra/pinctrl-tegra194.c | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index c8246cc2c4fd..65511bf27d34 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -794,7 +794,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
 
 	tegra_pinctrl_clear_parked_bits(pmx);
 
-	if (!tegra_pinctrl_gpio_node_has_range(pmx))
+	if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx))
 		pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
 
 	platform_set_drvdata(pdev, pmx);
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c
index d4e84530158c..61fc7e680788 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra194.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c
@@ -134,7 +134,6 @@ static const struct tegra_pingroup tegra194_groups[] = {
 };
 
 static const struct tegra_pinctrl_soc_data tegra194_pinctrl = {
-	.ngpios = TEGRA_PIN_NUM_GPIOS,
 	.pins = tegra194_pins,
 	.npins = ARRAY_SIZE(tegra194_pins),
 	.functions = tegra194_functions,
-- 
2.24.1

[PATCH 8/9] pinctrl: tegra: Renumber the GG.0 and GG.1 pins

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

There is no need to define these at a specific offset since they are the
only pins defined for this SoC generation. Begin numbering them at 0.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/pinctrl/tegra/pinctrl-tegra194.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c
index 61fc7e680788..61afe5fe9dec 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra194.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c
@@ -24,17 +24,14 @@
 
 /* Define unique ID for each pins */
 enum pin_id {
-	TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0 = 256,
-	TEGRA_PIN_PEX_L5_RST_N_PGG1 = 257,
-	TEGRA_PIN_NUM_GPIOS = 258,
+	TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
+	TEGRA_PIN_PEX_L5_RST_N_PGG1,
 };
 
 /* Table for pin descriptor */
 static const struct pinctrl_pin_desc tegra194_pins[] = {
-	PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
-		    "TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0"),
-	PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1,
-		    "TEGRA_PIN_PEX_L5_RST_N_PGG1"),
+	PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, "PEX_L5_CLKREQ_N_PGG0"),
+	PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1, "PEX_L5_RST_N_PGG1"),
 };
 
 static const unsigned int pex_l5_clkreq_n_pgg0_pins[] = {
-- 
2.24.1

[PATCH 9/9] pinctrl: tegra: Add SFIO/GPIO programming on Tegra194

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Prior to Tegra186, the selection of SFIO vs. GPIO modes was done as part
of the GPIO controller's register programming. Starting with Tegra186, a
pin is configured as GPIO or SFIO with a bit in a configuration register
of the pin controller.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/pinctrl/tegra/pinctrl-tegra.c    | 46 ++++++++++++++++++++++++
 drivers/pinctrl/tegra/pinctrl-tegra.h    |  3 ++
 drivers/pinctrl/tegra/pinctrl-tegra194.c |  2 ++
 3 files changed, 51 insertions(+)

diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index 65511bf27d34..21661f6490d6 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -275,11 +275,57 @@ static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
 	return 0;
 }
 
+static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
+					     struct pinctrl_gpio_range *range,
+					     unsigned int offset)
+{
+	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+	const struct tegra_pingroup *group;
+	u32 value;
+
+	if (!pmx->soc->sfsel_in_mux)
+		return 0;
+
+	group = &pmx->soc->groups[offset];
+
+	if (group->mux_reg < 0 || group->sfsel_bit < 0)
+		return -EINVAL;
+
+	value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
+	value &= ~BIT(group->sfsel_bit);
+	pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
+
+	return 0;
+}
+
+static void tegra_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev,
+					    struct pinctrl_gpio_range *range,
+					    unsigned int offset)
+{
+	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+	const struct tegra_pingroup *group;
+	u32 value;
+
+	if (!pmx->soc->sfsel_in_mux)
+		return;
+
+	group = &pmx->soc->groups[offset];
+
+	if (group->mux_reg < 0 || group->sfsel_bit < 0)
+		return;
+
+	value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
+	value |= BIT(group->sfsel_bit);
+	pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
+}
+
 static const struct pinmux_ops tegra_pinmux_ops = {
 	.get_functions_count = tegra_pinctrl_get_funcs_count,
 	.get_function_name = tegra_pinctrl_get_func_name,
 	.get_function_groups = tegra_pinctrl_get_func_groups,
 	.set_mux = tegra_pinctrl_set_mux,
+	.gpio_request_enable = tegra_pinctrl_gpio_request_enable,
+	.gpio_disable_free = tegra_pinctrl_gpio_disable_free,
 };
 
 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h
index 520865979d4a..fcad7f74c5a2 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.h
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.h
@@ -107,6 +107,7 @@ struct tegra_function {
  *			drvup, slwr, slwf, and drvtype parameters.
  * @drv_bank:		Drive fields register bank.
  * @hsm_bit:		High Speed Mode register bit.
+ * @sfsel_bit:		GPIO/SFIO selection register bit.
  * @schmitt_bit:	Schmitt register bit.
  * @lpmd_bit:		Low Power Mode register bit.
  * @drvdn_bit:		Drive Down register bit.
@@ -153,6 +154,7 @@ struct tegra_pingroup {
 	s32 ioreset_bit:6;
 	s32 rcv_sel_bit:6;
 	s32 hsm_bit:6;
+	s32 sfsel_bit:6;
 	s32 schmitt_bit:6;
 	s32 lpmd_bit:6;
 	s32 drvdn_bit:6;
@@ -192,6 +194,7 @@ struct tegra_pinctrl_soc_data {
 	bool hsm_in_mux;
 	bool schmitt_in_mux;
 	bool drvtype_in_mux;
+	bool sfsel_in_mux;
 };
 
 extern const struct dev_pm_ops tegra_pinctrl_pm;
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c
index 61afe5fe9dec..2e0b5f7bb095 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra194.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c
@@ -95,6 +95,7 @@ static struct tegra_function tegra194_functions[] = {
 		.tri_bit = 4,					\
 		.einput_bit = e_input,				\
 		.odrain_bit = e_od,				\
+		.sfsel_bit = 10,				\
 		.schmitt_bit = schmitt_b,			\
 		.drvtype_bit = 13,				\
 		.drv_reg = -1,					\
@@ -140,6 +141,7 @@ static const struct tegra_pinctrl_soc_data tegra194_pinctrl = {
 	.hsm_in_mux = true,
 	.schmitt_in_mux = true,
 	.drvtype_in_mux = true,
+	.sfsel_in_mux = true,
 };
 
 static int tegra194_pinctrl_probe(struct platform_device *pdev)
-- 
2.24.1

Re: [PATCH 0/9] pinctrl: tegra: Support SFIO/GPIO programming

[Vidya Sagar]

On 3/19/2020 5:57 PM, Thierry Reding wrote:
> External email: Use caution opening links or attachments
> 
> 
> From: Thierry Reding <treding@nvidia.com>
> 
> Hi,
> 
> NVIDIA Tegra186 and later have a bit in the pin controller that defines
> whether a pin is used in special function (SFIO) mode or in general
> purpose (GPIO) mode. On early Tegra SoC generations, this bit was part
> of the GPIO controller.
> 
> The pin configuration on Tegra186 and later (and partially on Tegra210)
> is typically static, so there is little need to reconfigure these pins.
> However, there's a special case on Tegra194 where the PCIe CLKREQ and
> RST pins for controller 5 may need to be reprogrammed in the kernel,
> depending on whether the controller runs in endpoint mode or in root
> port mode.
> 
> This series of patches establishes the mapping of these two pins to
> their GPIO equivalents and implements the code necessary to switch
> between SFIO and GPIO modes when the kernel requests or releases the
> GPIOs, respectively.
> 
> Thierry
> 
> Thierry Reding (9):
>    gpio: Support GPIO controllers without pin-ranges
>    gpio: tegra186: Add support for pin ranges
>    gpio: tegra186: Add Tegra194 pin ranges for GG.0 and GG.1
>    pinctrl: tegra: Fix whitespace issues for improved readability
>    pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo
>    pinctrl: tegra: Pass struct tegra_pmx for pin range check
>    pinctrl: tegra: Do not add default pin range on Tegra194
>    pinctrl: tegra: Renumber the GG.0 and GG.1 pins
>    pinctrl: tegra: Add SFIO/GPIO programming on Tegra194
> 
>   drivers/gpio/gpio-tegra186.c             | 64 ++++++++++++++++++++++++
>   drivers/gpio/gpiolib.c                   |  5 +-
>   drivers/pinctrl/tegra/pinctrl-tegra.c    | 52 +++++++++++++++++--
>   drivers/pinctrl/tegra/pinctrl-tegra.h    |  5 +-
>   drivers/pinctrl/tegra/pinctrl-tegra194.c | 47 +++++++++--------
>   5 files changed, 144 insertions(+), 29 deletions(-)
> 
> --
> 2.24.1
> 
Tested-by: Vidya Sagar <vidyas@nvidia.com>

Re: [PATCH 1/9] gpio: Support GPIO controllers without pin-ranges

[Vidya Sagar]

On 3/19/2020 5:57 PM, Thierry Reding wrote:
> External email: Use caution opening links or attachments
> 
> 
> From: Thierry Reding <treding@nvidia.com>
> 
> Wake gpiochip_generic_request() call into the pinctrl helpers only if a
> GPIO controller had any pin-ranges assigned to it. This allows a driver
> to unconditionally use this helper if it supports multiple devices of
> which only a subset have pin-ranges assigned to them.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>   drivers/gpio/gpiolib.c | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
> index f31b1d46599e..12f3c339da78 100644
> --- a/drivers/gpio/gpiolib.c
> +++ b/drivers/gpio/gpiolib.c
> @@ -2792,7 +2792,10 @@ static inline void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip)
>    */
>   int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset)
>   {
> -       return pinctrl_gpio_request(chip->gpiodev->base + offset);
> +       if (!list_empty(&chip->gpiodev->pin_ranges))
> +               return pinctrl_gpio_request(chip->gpiodev->base + offset);
> +
> +       return 0;
>   }
>   EXPORT_SYMBOL_GPL(gpiochip_generic_request);
> 
> --
> 2.24.1
> 
Tested-by: Vidya Sagar <vidyas@nvidia.com>

Re: [PATCH 2/9] gpio: tegra186: Add support for pin ranges

[Vidya Sagar]

On 3/19/2020 5:57 PM, Thierry Reding wrote:
> External email: Use caution opening links or attachments
> 
> 
> From: Thierry Reding <treding@nvidia.com>
> 
> Add support for Tegra SoC generations to specify a list of pin ranges
> that map GPIOs to ranges of pins in the pin controller.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>   drivers/gpio/gpio-tegra186.c | 56 ++++++++++++++++++++++++++++++++++++
>   1 file changed, 56 insertions(+)
> 
> diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c
> index de241263d4be..1086c1fcaf49 100644
> --- a/drivers/gpio/gpio-tegra186.c
> +++ b/drivers/gpio/gpio-tegra186.c
> @@ -58,11 +58,20 @@ struct tegra_gpio_port {
>          unsigned int pins;
>   };
> 
> +struct tegra186_pin_range {
> +       unsigned int offset;
> +       const char *group;
> +};
> +
>   struct tegra_gpio_soc {
>          const struct tegra_gpio_port *ports;
>          unsigned int num_ports;
>          const char *name;
>          unsigned int instance;
> +
> +       const struct tegra186_pin_range *pin_ranges;
> +       unsigned int num_pin_ranges;
> +       const char *pinmux;
>   };
> 
>   struct tegra_gpio {
> @@ -254,6 +263,50 @@ static int tegra186_gpio_set_config(struct gpio_chip *chip,
>          return 0;
>   }
> 
> +static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
> +{
> +       struct tegra_gpio *gpio = gpiochip_get_data(chip);
> +       struct pinctrl_dev *pctldev;
> +       struct device_node *np;
> +       unsigned int i, j;
> +       int err;
> +
> +       if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
> +               return 0;
> +
> +       np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
> +       if (!np)
> +               return -ENODEV;
> +
> +       pctldev = of_pinctrl_get(np);
> +       of_node_put(np);
> +       if (!pctldev)
> +               return -EPROBE_DEFER;
> +
> +       for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
> +               unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
> +               const char *group = gpio->soc->pin_ranges[i].group;
> +
> +               port = pin / 8;
> +               pin = pin % 8;
> +
> +               if (port >= gpio->soc->num_ports) {
> +                       dev_warn(chip->parent, "invalid port %u for %s\n",
> +                                port, group);
> +                       continue;
> +               }
> +
> +               for (j = 0; j < port; j++)
> +                       pin += gpio->soc->ports[j].pins;
> +
> +               err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
> +               if (err < 0)
> +                       return err;
> +       }
> +
> +       return 0;
> +}
> +
>   static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
>                                    const struct of_phandle_args *spec,
>                                    u32 *flags)
> @@ -578,12 +631,15 @@ static int tegra186_gpio_probe(struct platform_device *pdev)
>          gpio->gpio.label = gpio->soc->name;
>          gpio->gpio.parent = &pdev->dev;
> 
> +       gpio->gpio.request = gpiochip_generic_request;
> +       gpio->gpio.free = gpiochip_generic_free;
>          gpio->gpio.get_direction = tegra186_gpio_get_direction;
>          gpio->gpio.direction_input = tegra186_gpio_direction_input;
>          gpio->gpio.direction_output = tegra186_gpio_direction_output;
>          gpio->gpio.get = tegra186_gpio_get,
>          gpio->gpio.set = tegra186_gpio_set;
>          gpio->gpio.set_config = tegra186_gpio_set_config;
> +       gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
> 
>          gpio->gpio.base = -1;
> 
> --
> 2.24.1
> 
Tested-by: Vidya Sagar <vidyas@nvidia.com>

Re: [PATCH 3/9] gpio: tegra186: Add Tegra194 pin ranges for GG.0 and GG.1

[Vidya Sagar]

On 3/19/2020 5:57 PM, Thierry Reding wrote:
> External email: Use caution opening links or attachments
> 
> 
> From: Thierry Reding <treding@nvidia.com>
> 
> The GG.0 and GG.1 GPIOs serve as CLKREQ and RST pins, respectively, for
> PCIe controller 5 on Tegra194. When this controller is configured in
> endpoint mode, these pins need to be used as GPIOs by the PCIe endpoint
> driver. Typically the mode programming of these pins (GPIO vs. SFIO) is
> performed by early boot firmware to ensure that the configuration is
> consistent.
> 
> However, the GG.0 and GG.1 pins are part of a special power partition
> that is not enabled during early boot, and hence the early boot firmware
> cannot program these pins to be GPIOs (they are SFIO by default). Adding
> them as pin ranges for the pin controller allows the pin controller to
> be involved when these pins are requested as GPIOs and allows the proper
> programming to take place.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>   drivers/gpio/gpio-tegra186.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c
> index 1086c1fcaf49..79b553dc39a3 100644
> --- a/drivers/gpio/gpio-tegra186.c
> +++ b/drivers/gpio/gpio-tegra186.c
> @@ -839,11 +839,19 @@ static const struct tegra_gpio_port tegra194_main_ports[] = {
>          TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
>   };
> 
> +static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
> +       { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
> +       { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
> +};
> +
>   static const struct tegra_gpio_soc tegra194_main_soc = {
>          .num_ports = ARRAY_SIZE(tegra194_main_ports),
>          .ports = tegra194_main_ports,
>          .name = "tegra194-gpio",
>          .instance = 0,
> +       .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
> +       .pin_ranges = tegra194_main_pin_ranges,
> +       .pinmux = "nvidia,tegra194-pinmux",
>   };
> 
>   #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins)     \
> --
> 2.24.1
> 
Tested-by: Vidya Sagar <vidyas@nvidia.com>

Re: [PATCH 4/9] pinctrl: tegra: Fix whitespace issues for improved readability

[Vidya Sagar]

On 3/19/2020 5:57 PM, Thierry Reding wrote:
> External email: Use caution opening links or attachments
> 
> 
> From: Thierry Reding <treding@nvidia.com>
> 
> Fix a few whitespace inconsistencies to make the code easier to read.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>   drivers/pinctrl/tegra/pinctrl-tegra194.c | 33 ++++++++++++------------
>   1 file changed, 17 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c
> index daf44cf240c9..d4e84530158c 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra194.c
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c
> @@ -59,6 +59,7 @@ enum tegra_mux_dt {
>          {                                       \
>                  .name = #lid,                   \
>          }
> +
>   static struct tegra_function tegra194_functions[] = {
>          TEGRA_PIN_FUNCTION(rsvd0),
>          TEGRA_PIN_FUNCTION(rsvd1),
> @@ -70,7 +71,7 @@ static struct tegra_function tegra194_functions[] = {
>   #define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b,     \
>                               drvup_w, slwr_b, slwr_w, slwf_b,   \
>                               slwf_w, bank)                      \
> -               .drv_reg = ((r)),                       \
> +               .drv_reg = ((r)),                               \
>                  .drv_bank = bank,                               \
>                  .drvdn_bit = drvdn_b,                           \
>                  .drvdn_width = drvdn_w,                         \
> @@ -89,7 +90,7 @@ static struct tegra_function tegra194_functions[] = {
>                  .hsm_bit = -1,                                  \
>                  .mux_bank = bank,                               \
>                  .mux_bit = 0,                                   \
> -               .pupd_reg = ((r)),              \
> +               .pupd_reg = ((r)),                              \
>                  .pupd_bank = bank,                              \
>                  .pupd_bit = 2,                                  \
>                  .tri_reg = ((r)),                               \
> @@ -109,20 +110,20 @@ static struct tegra_function tegra194_functions[] = {
> 
>   #define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_lpbk,       \
>                   e_input, e_lpdr, e_od, schmitt_b, drvtype, io_rail)    \
> -       {                                                       \
> -               .name = #pg_name,                               \
> -               .pins = pg_name##_pins,                         \
> -               .npins = ARRAY_SIZE(pg_name##_pins),            \
> -                       .funcs = {                              \
> -                               TEGRA_MUX_##f0,                 \
> -                               TEGRA_MUX_##f1,                 \
> -                               TEGRA_MUX_##f2,                 \
> -                               TEGRA_MUX_##f3,                 \
> -                       },                                      \
> -               PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk,     \
> -                                    e_input, e_od,             \
> -                                    schmitt_b, drvtype),       \
> -               drive_##pg_name,                                \
> +       {                                                               \
> +               .name = #pg_name,                                       \
> +               .pins = pg_name##_pins,                                 \
> +               .npins = ARRAY_SIZE(pg_name##_pins),                    \
> +                       .funcs = {                                      \
> +                               TEGRA_MUX_##f0,                         \
> +                               TEGRA_MUX_##f1,                         \
> +                               TEGRA_MUX_##f2,                         \
> +                               TEGRA_MUX_##f3,                         \
> +                       },                                              \
> +               PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk,             \
> +                                    e_input, e_od,                     \
> +                                    schmitt_b, drvtype),               \
> +               drive_##pg_name,                                        \
>          }
> 
>   static const struct tegra_pingroup tegra194_groups[] = {
> --
> 2.24.1
> 
Tested-by: Vidya Sagar <vidyas@nvidia.com>

Re: [PATCH 5/9] pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo

[Vidya Sagar]

On 3/19/2020 5:57 PM, Thierry Reding wrote:
> External email: Use caution opening links or attachments
> 
> 
> From: Thierry Reding <treding@nvidia.com>
> 
> Properly spell "Schmitt" in the kerneldoc for pin group definitions.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>   drivers/pinctrl/tegra/pinctrl-tegra.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h
> index 0fc82eea9cf1..520865979d4a 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra.h
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h
> @@ -107,7 +107,7 @@ struct tegra_function {
>    *                     drvup, slwr, slwf, and drvtype parameters.
>    * @drv_bank:          Drive fields register bank.
>    * @hsm_bit:           High Speed Mode register bit.
> - * @schmitt_bit:       Scmitt register bit.
> + * @schmitt_bit:       Schmitt register bit.
>    * @lpmd_bit:          Low Power Mode register bit.
>    * @drvdn_bit:         Drive Down register bit.
>    * @drvdn_width:       Drive Down field width.
> --
> 2.24.1
> 
Tested-by: Vidya Sagar <vidyas@nvidia.com>

Re: [PATCH 6/9] pinctrl: tegra: Pass struct tegra_pmx for pin range check

[Vidya Sagar]

On 3/19/2020 5:57 PM, Thierry Reding wrote:
> External email: Use caution opening links or attachments
> 
> 
> From: Thierry Reding <treding@nvidia.com>
> 
> Pass the struct tegra_pmx when checking for the pin range in device
> tree. This makes the call site a bit easier to read and will help keep
> that readability in a subsequent patch.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>   drivers/pinctrl/tegra/pinctrl-tegra.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
> index cefbbb8d1a68..c8246cc2c4fd 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
> @@ -689,12 +689,12 @@ const struct dev_pm_ops tegra_pinctrl_pm = {
>          .resume = &tegra_pinctrl_resume
>   };
> 
> -static bool gpio_node_has_range(const char *compatible)
> +static bool tegra_pinctrl_gpio_node_has_range(struct tegra_pmx *pmx)
>   {
>          struct device_node *np;
>          bool has_prop = false;
> 
> -       np = of_find_compatible_node(NULL, NULL, compatible);
> +       np = of_find_compatible_node(NULL, NULL, pmx->soc->gpio_compatible);
>          if (!np)
>                  return has_prop;
> 
> @@ -794,7 +794,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
> 
>          tegra_pinctrl_clear_parked_bits(pmx);
> 
> -       if (!gpio_node_has_range(pmx->soc->gpio_compatible))
> +       if (!tegra_pinctrl_gpio_node_has_range(pmx))
>                  pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
> 
>          platform_set_drvdata(pdev, pmx);
> --
> 2.24.1
> 
Tested-by: Vidya Sagar <vidyas@nvidia.com>

Re: [PATCH 7/9] pinctrl: tegra: Do not add default pin range on Tegra194

[Vidya Sagar]

On 3/19/2020 5:57 PM, Thierry Reding wrote:
> External email: Use caution opening links or attachments
> 
> 
> From: Thierry Reding <treding@nvidia.com>
> 
> On Tegra194, almost all of the pin control programming happens in early
> boot firmware, so there is no use in having a pin range defined for all
> the pins.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>   drivers/pinctrl/tegra/pinctrl-tegra.c    | 2 +-
>   drivers/pinctrl/tegra/pinctrl-tegra194.c | 1 -
>   2 files changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
> index c8246cc2c4fd..65511bf27d34 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
> @@ -794,7 +794,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
> 
>          tegra_pinctrl_clear_parked_bits(pmx);
> 
> -       if (!tegra_pinctrl_gpio_node_has_range(pmx))
> +       if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx))
>                  pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
> 
>          platform_set_drvdata(pdev, pmx);
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c
> index d4e84530158c..61fc7e680788 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra194.c
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c
> @@ -134,7 +134,6 @@ static const struct tegra_pingroup tegra194_groups[] = {
>   };
> 
>   static const struct tegra_pinctrl_soc_data tegra194_pinctrl = {
> -       .ngpios = TEGRA_PIN_NUM_GPIOS,
>          .pins = tegra194_pins,
>          .npins = ARRAY_SIZE(tegra194_pins),
>          .functions = tegra194_functions,
> --
> 2.24.1
> 
Tested-by: Vidya Sagar <vidyas@nvidia.com>

Re: [PATCH 8/9] pinctrl: tegra: Renumber the GG.0 and GG.1 pins

[Vidya Sagar]

On 3/19/2020 5:57 PM, Thierry Reding wrote:
> External email: Use caution opening links or attachments
> 
> 
> From: Thierry Reding <treding@nvidia.com>
> 
> There is no need to define these at a specific offset since they are the
> only pins defined for this SoC generation. Begin numbering them at 0.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>   drivers/pinctrl/tegra/pinctrl-tegra194.c | 11 ++++-------
>   1 file changed, 4 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c
> index 61fc7e680788..61afe5fe9dec 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra194.c
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c
> @@ -24,17 +24,14 @@
> 
>   /* Define unique ID for each pins */
>   enum pin_id {
> -       TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0 = 256,
> -       TEGRA_PIN_PEX_L5_RST_N_PGG1 = 257,
> -       TEGRA_PIN_NUM_GPIOS = 258,
> +       TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
> +       TEGRA_PIN_PEX_L5_RST_N_PGG1,
>   };
> 
>   /* Table for pin descriptor */
>   static const struct pinctrl_pin_desc tegra194_pins[] = {
> -       PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
> -                   "TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0"),
> -       PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1,
> -                   "TEGRA_PIN_PEX_L5_RST_N_PGG1"),
> +       PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, "PEX_L5_CLKREQ_N_PGG0"),
> +       PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1, "PEX_L5_RST_N_PGG1"),
>   };
> 
>   static const unsigned int pex_l5_clkreq_n_pgg0_pins[] = {
> --
> 2.24.1
> 
Tested-by: Vidya Sagar <vidyas@nvidia.com>

Re: [PATCH 9/9] pinctrl: tegra: Add SFIO/GPIO programming on Tegra194

[Vidya Sagar]

On 3/19/2020 5:57 PM, Thierry Reding wrote:
> External email: Use caution opening links or attachments
> 
> 
> From: Thierry Reding <treding@nvidia.com>
> 
> Prior to Tegra186, the selection of SFIO vs. GPIO modes was done as part
> of the GPIO controller's register programming. Starting with Tegra186, a
> pin is configured as GPIO or SFIO with a bit in a configuration register
> of the pin controller.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>   drivers/pinctrl/tegra/pinctrl-tegra.c    | 46 ++++++++++++++++++++++++
>   drivers/pinctrl/tegra/pinctrl-tegra.h    |  3 ++
>   drivers/pinctrl/tegra/pinctrl-tegra194.c |  2 ++
>   3 files changed, 51 insertions(+)
> 
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
> index 65511bf27d34..21661f6490d6 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
> @@ -275,11 +275,57 @@ static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
>          return 0;
>   }
> 
> +static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
> +                                            struct pinctrl_gpio_range *range,
> +                                            unsigned int offset)
> +{
> +       struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
> +       const struct tegra_pingroup *group;
> +       u32 value;
> +
> +       if (!pmx->soc->sfsel_in_mux)
> +               return 0;
> +
> +       group = &pmx->soc->groups[offset];
> +
> +       if (group->mux_reg < 0 || group->sfsel_bit < 0)
> +               return -EINVAL;
> +
> +       value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
> +       value &= ~BIT(group->sfsel_bit);
> +       pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
> +
> +       return 0;
> +}
> +
> +static void tegra_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev,
> +                                           struct pinctrl_gpio_range *range,
> +                                           unsigned int offset)
> +{
> +       struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
> +       const struct tegra_pingroup *group;
> +       u32 value;
> +
> +       if (!pmx->soc->sfsel_in_mux)
> +               return;
> +
> +       group = &pmx->soc->groups[offset];
> +
> +       if (group->mux_reg < 0 || group->sfsel_bit < 0)
> +               return;
> +
> +       value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
> +       value |= BIT(group->sfsel_bit);
> +       pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
> +}
> +
>   static const struct pinmux_ops tegra_pinmux_ops = {
>          .get_functions_count = tegra_pinctrl_get_funcs_count,
>          .get_function_name = tegra_pinctrl_get_func_name,
>          .get_function_groups = tegra_pinctrl_get_func_groups,
>          .set_mux = tegra_pinctrl_set_mux,
> +       .gpio_request_enable = tegra_pinctrl_gpio_request_enable,
> +       .gpio_disable_free = tegra_pinctrl_gpio_disable_free,
>   };
> 
>   static int tegra_pinconf_reg(struct tegra_pmx *pmx,
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h
> index 520865979d4a..fcad7f74c5a2 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra.h
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h
> @@ -107,6 +107,7 @@ struct tegra_function {
>    *                     drvup, slwr, slwf, and drvtype parameters.
>    * @drv_bank:          Drive fields register bank.
>    * @hsm_bit:           High Speed Mode register bit.
> + * @sfsel_bit:         GPIO/SFIO selection register bit.
>    * @schmitt_bit:       Schmitt register bit.
>    * @lpmd_bit:          Low Power Mode register bit.
>    * @drvdn_bit:         Drive Down register bit.
> @@ -153,6 +154,7 @@ struct tegra_pingroup {
>          s32 ioreset_bit:6;
>          s32 rcv_sel_bit:6;
>          s32 hsm_bit:6;
> +       s32 sfsel_bit:6;
>          s32 schmitt_bit:6;
>          s32 lpmd_bit:6;
>          s32 drvdn_bit:6;
> @@ -192,6 +194,7 @@ struct tegra_pinctrl_soc_data {
>          bool hsm_in_mux;
>          bool schmitt_in_mux;
>          bool drvtype_in_mux;
> +       bool sfsel_in_mux;
>   };
> 
>   extern const struct dev_pm_ops tegra_pinctrl_pm;
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c
> index 61afe5fe9dec..2e0b5f7bb095 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra194.c
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c
> @@ -95,6 +95,7 @@ static struct tegra_function tegra194_functions[] = {
>                  .tri_bit = 4,                                   \
>                  .einput_bit = e_input,                          \
>                  .odrain_bit = e_od,                             \
> +               .sfsel_bit = 10,                                \
>                  .schmitt_bit = schmitt_b,                       \
>                  .drvtype_bit = 13,                              \
>                  .drv_reg = -1,                                  \
> @@ -140,6 +141,7 @@ static const struct tegra_pinctrl_soc_data tegra194_pinctrl = {
>          .hsm_in_mux = true,
>          .schmitt_in_mux = true,
>          .drvtype_in_mux = true,
> +       .sfsel_in_mux = true,
>   };
> 
>   static int tegra194_pinctrl_probe(struct platform_device *pdev)
> --
> 2.24.1
> 
Tested-by: Vidya Sagar <vidyas@nvidia.com>

Re: [PATCH 0/9] pinctrl: tegra: Support SFIO/GPIO programming

[Linus Walleij]

On Thu, Mar 19, 2020 at 1:27 PM Thierry Reding <thierry.reding@gmail.com> wrote:

> This series of patches establishes the mapping of these two pins to
> their GPIO equivalents and implements the code necessary to switch
> between SFIO and GPIO modes when the kernel requests or releases the
> GPIOs, respectively.

Is it possible to apply the gpio and pinctrl patches to
each tree separately?

Yours,
Linus Walleij

Re: [PATCH 0/9] pinctrl: tegra: Support SFIO/GPIO programming

[Thierry Reding]

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On Fri, Mar 20, 2020 at 08:37:48PM +0100, Linus Walleij wrote:
> On Thu, Mar 19, 2020 at 1:27 PM Thierry Reding <thierry.reding@gmail.com> wrote:
> 
> > This series of patches establishes the mapping of these two pins to
> > their GPIO equivalents and implements the code necessary to switch
> > between SFIO and GPIO modes when the kernel requests or releases the
> > GPIOs, respectively.
> 
> Is it possible to apply the gpio and pinctrl patches to
> each tree separately?

Yes, that should be possible. There's a dependency from patches 2 & 3 on
patch 1, but since they are all for the same tree that should be fine.
The dependency also is only a runtime dependency where the GPIO driver
would defer probe indefinitely because no pin range would ever be added.
So as long as patches 1-3 are applied in the order given in this series,
everything should be okay.

Thierry

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Re: [PATCH 1/9] gpio: Support GPIO controllers without pin-ranges

[Linus Walleij]

On Thu, Mar 19, 2020 at 1:27 PM Thierry Reding <thierry.reding@gmail.com> wrote:

> From: Thierry Reding <treding@nvidia.com>
>
> Wake gpiochip_generic_request() call into the pinctrl helpers only if a
> GPIO controller had any pin-ranges assigned to it. This allows a driver
> to unconditionally use this helper if it supports multiple devices of
> which only a subset have pin-ranges assigned to them.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>

Patch applied.

We have some drivers like this:
drivers/gpio/gpio-pl061.c:

        if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
                pl061->gc.request = gpiochip_generic_request;
                pl061->gc.free = gpiochip_generic_free;
        }

Should we just make a patch assigning these callbacks
unconditionally as a follow-up?

Yours,
Linus Walleij

Re: [PATCH 3/9] gpio: tegra186: Add Tegra194 pin ranges for GG.0 and GG.1

[Linus Walleij]

On Thu, Mar 19, 2020 at 1:27 PM Thierry Reding <thierry.reding@gmail.com> wrote:

> From: Thierry Reding <treding@nvidia.com>
>
> The GG.0 and GG.1 GPIOs serve as CLKREQ and RST pins, respectively, for
> PCIe controller 5 on Tegra194. When this controller is configured in
> endpoint mode, these pins need to be used as GPIOs by the PCIe endpoint
> driver. Typically the mode programming of these pins (GPIO vs. SFIO) is
> performed by early boot firmware to ensure that the configuration is
> consistent.
>
> However, the GG.0 and GG.1 pins are part of a special power partition
> that is not enabled during early boot, and hence the early boot firmware
> cannot program these pins to be GPIOs (they are SFIO by default). Adding
> them as pin ranges for the pin controller allows the pin controller to
> be involved when these pins are requested as GPIOs and allows the proper
> programming to take place.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>

Patch applied!

Yours,
Linus Walleij

Re: [PATCH 2/9] gpio: tegra186: Add support for pin ranges

[Linus Walleij]

On Thu, Mar 19, 2020 at 1:27 PM Thierry Reding <thierry.reding@gmail.com> wrote:

> From: Thierry Reding <treding@nvidia.com>
>
> Add support for Tegra SoC generations to specify a list of pin ranges
> that map GPIOs to ranges of pins in the pin controller.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>

Patch applied!

Yours,
Linus Walleij

Re: [PATCH 4/9] pinctrl: tegra: Fix whitespace issues for improved readability

[Linus Walleij]

On Thu, Mar 19, 2020 at 1:27 PM Thierry Reding <thierry.reding@gmail.com> wrote:

> From: Thierry Reding <treding@nvidia.com>
>
> Fix a few whitespace inconsistencies to make the code easier to read.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>

Patch applied!

Yours,
Linus Walleij

Re: [PATCH 5/9] pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo

[Linus Walleij]

On Thu, Mar 19, 2020 at 1:27 PM Thierry Reding <thierry.reding@gmail.com> wrote:

> From: Thierry Reding <treding@nvidia.com>
>
> Properly spell "Schmitt" in the kerneldoc for pin group definitions.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>

Patch applied!

Yours,
Linus Walleij

Re: [PATCH 6/9] pinctrl: tegra: Pass struct tegra_pmx for pin range check

[Linus Walleij]

On Thu, Mar 19, 2020 at 1:27 PM Thierry Reding <thierry.reding@gmail.com> wrote:

> From: Thierry Reding <treding@nvidia.com>
>
> Pass the struct tegra_pmx when checking for the pin range in device
> tree. This makes the call site a bit easier to read and will help keep
> that readability in a subsequent patch.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>

Patch applied!

Yours,
Linus Walleij

Re: [PATCH 7/9] pinctrl: tegra: Do not add default pin range on Tegra194

[Linus Walleij]

On Thu, Mar 19, 2020 at 1:28 PM Thierry Reding <thierry.reding@gmail.com> wrote:

> From: Thierry Reding <treding@nvidia.com>
>
> On Tegra194, almost all of the pin control programming happens in early
> boot firmware, so there is no use in having a pin range defined for all
> the pins.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>

Patch applied!

Yours,
Linus Walleij

Re: [PATCH 8/9] pinctrl: tegra: Renumber the GG.0 and GG.1 pins

[Linus Walleij]

On Thu, Mar 19, 2020 at 1:28 PM Thierry Reding <thierry.reding@gmail.com> wrote:

> From: Thierry Reding <treding@nvidia.com>
>
> There is no need to define these at a specific offset since they are the
> only pins defined for this SoC generation. Begin numbering them at 0.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>

Patch applied!

Yours,
Linus Walleij

Re: [PATCH 9/9] pinctrl: tegra: Add SFIO/GPIO programming on Tegra194

[Linus Walleij]

On Thu, Mar 19, 2020 at 1:28 PM Thierry Reding <thierry.reding@gmail.com> wrote:

> From: Thierry Reding <treding@nvidia.com>
>
> Prior to Tegra186, the selection of SFIO vs. GPIO modes was done as part
> of the GPIO controller's register programming. Starting with Tegra186, a
> pin is configured as GPIO or SFIO with a bit in a configuration register
> of the pin controller.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>

Patch applied!

Yours,
Linus Walleij

Re: [PATCH 1/9] gpio: Support GPIO controllers without pin-ranges

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1009 bytes --]

On Fri, Mar 27, 2020 at 11:37:07AM +0100, Linus Walleij wrote:
> On Thu, Mar 19, 2020 at 1:27 PM Thierry Reding <thierry.reding@gmail.com> wrote:
> 
> > From: Thierry Reding <treding@nvidia.com>
> >
> > Wake gpiochip_generic_request() call into the pinctrl helpers only if a
> > GPIO controller had any pin-ranges assigned to it. This allows a driver
> > to unconditionally use this helper if it supports multiple devices of
> > which only a subset have pin-ranges assigned to them.
> >
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> 
> Patch applied.
> 
> We have some drivers like this:
> drivers/gpio/gpio-pl061.c:
> 
>         if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
>                 pl061->gc.request = gpiochip_generic_request;
>                 pl061->gc.free = gpiochip_generic_free;
>         }
> 
> Should we just make a patch assigning these callbacks
> unconditionally as a follow-up?

Yeah, that's a good idea. I'll look into it.

Thierry

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Re: [PATCH 2/9] gpio: tegra186: Add support for pin ranges

[Thierry Reding]

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On Fri, Mar 27, 2020 at 11:39:35AM +0100, Linus Walleij wrote:
> On Thu, Mar 19, 2020 at 1:27 PM Thierry Reding <thierry.reding@gmail.com> wrote:
> 
> > From: Thierry Reding <treding@nvidia.com>
> >
> > Add support for Tegra SoC generations to specify a list of pin ranges
> > that map GPIOs to ranges of pins in the pin controller.
> >
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> 
> Patch applied!

Hi Linus,

I see patch 1 applied to gpio/for-next, but patches 2 and 3 don't seem
to be in linux-next yet. Did anything go wrong with those?

Thierry

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