From: Jisheng Zhang <Jisheng.Zhang@synaptics.com> To: Vidya Sagar <vidyas@nvidia.com> Cc: Kishon Vijay Abraham I <kishon@ti.com>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Rob Herring <robh@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>, Jingoo Han <jingoohan1@gmail.com>, Kukjin Kim <kgene@kernel.org>, Krzysztof Kozlowski <krzk@kernel.org>, Richard Zhu <hongxing.zhu@nxp.com>, Lucas Stach <l.stach@pengutronix.de>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, "Pengutronix Kernel Team" <kernel@pengutronix.de>, Fabio Estevam <festevam@gmail.com>, "NXP Linux Team" <linux-imx@nxp.com>, Yue Wang <yue.wang@Amlogic.com>, "Kevin Hilman" <khilman@baylibre.com>, Neil Armstrong <narmstrong@baylibre.com>, Jerome Brunet <jbrunet@baylibre.com>, Martin Blumenstingl <martin.blumenstingl@googlemail.com>, Jesper Nilsson <jesper.nilsson@axis.com>, Gustavo Pimentel <gustavo.pimentel@synopsys.com>, Xiaowei Song <songxiaowei@hisilicon.com>, Binghui Wang <wangbinghui@hisilicon.com>, Andy Gross <agross@kernel.org>, Bjorn Andersson <bjorn.andersson@linaro.org>, Stanimir Varbanov <svarbanov@mm-sol.com>, Pratyush Anand <pratyush.anand@gmail.com>, Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, "Kunihiko Hayashi" <hayashi.kunihiko@socionext.com>, Masahiro Yamada <yamada.masahiro@socionext.com>, "linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>, "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "linux-samsung-soc@vger.kernel.org" <linux-samsung-soc@vger.kernel.org>, "linux-amlogic@lists.infradead.org" <linux-amlogic@lists.infradead.org>, "linux-arm-kernel@axis.com" <linux-arm-kernel@axis.com>, "linux-arm-msm@vger.kernel.org" <linux-arm-msm@vger.kernel.org>, "linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org> Subject: [PATCH] PCI: dwc: Move dw_pcie_msi_init() from each users to designware host Date: Fri, 9 Oct 2020 16:37:47 +0800 [thread overview] Message-ID: <20201009163747.64b1de4a@xhacker.debian> (raw) In-Reply-To: <435c8cf8-8f4a-c491-4aca-3ec5b7abe49a@nvidia.com> Let the designware host take care the integrated msi init rather than duplicate dw_pcie_msi_init() in each users. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> --- Hi Vidya, After V7, only this patch is left, others in v2 are not needed. There's one more clean up chance -- we can also move dw_pcie_free_msi() to designware host and make it static if we can clean up dra7xx. I see Rob is working on some larger MSI clean-ups, maybe this will be done in his clean-ups. Thanks drivers/pci/controller/dwc/pci-dra7xx.c | 1 - drivers/pci/controller/dwc/pci-exynos.c | 2 -- drivers/pci/controller/dwc/pci-imx6.c | 1 - drivers/pci/controller/dwc/pci-meson.c | 2 -- drivers/pci/controller/dwc/pcie-artpec6.c | 1 - drivers/pci/controller/dwc/pcie-designware-host.c | 5 +++-- drivers/pci/controller/dwc/pcie-designware-plat.c | 1 - drivers/pci/controller/dwc/pcie-designware.h | 5 ----- drivers/pci/controller/dwc/pcie-histb.c | 1 - drivers/pci/controller/dwc/pcie-kirin.c | 1 - drivers/pci/controller/dwc/pcie-qcom.c | 1 - drivers/pci/controller/dwc/pcie-spear13xx.c | 4 +--- drivers/pci/controller/dwc/pcie-tegra194.c | 2 -- drivers/pci/controller/dwc/pcie-uniphier.c | 2 -- 14 files changed, 4 insertions(+), 25 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c index 6d012d2b1e90..a5edaa6b6b58 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -185,7 +185,6 @@ static int dra7xx_pcie_host_init(struct pcie_port *pp) dra7xx_pcie_establish_link(pci); dw_pcie_wait_for_link(pci); - dw_pcie_msi_init(pp); dra7xx_pcie_enable_interrupts(dra7xx); return 0; diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c index 242683cde04a..97c166885277 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -298,8 +298,6 @@ static void exynos_pcie_msi_init(struct exynos_pcie *ep) struct pcie_port *pp = &pci->pp; u32 val; - dw_pcie_msi_init(pp); - /* enable MSI interrupt */ val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_EN_LEVEL); val |= IRQ_MSI_ENABLE; diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 337c74cbdfdb..cf52eb5d7d2e 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -836,7 +836,6 @@ static int imx6_pcie_host_init(struct pcie_port *pp) imx6_setup_phy_mpll(imx6_pcie); dw_pcie_setup_rc(pp); imx6_pcie_establish_link(imx6_pcie); - dw_pcie_msi_init(pp); return 0; } diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c index 33deb290c4e7..11bfc42fac1c 100644 --- a/drivers/pci/controller/dwc/pci-meson.c +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -387,8 +387,6 @@ static int meson_pcie_host_init(struct pcie_port *pp) if (ret) return ret; - dw_pcie_msi_init(pp); - return 0; } diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c index 929448e9e0bc..73d4bf99c737 100644 --- a/drivers/pci/controller/dwc/pcie-artpec6.c +++ b/drivers/pci/controller/dwc/pcie-artpec6.c @@ -331,7 +331,6 @@ static int artpec6_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); artpec6_pcie_establish_link(pci); dw_pcie_wait_for_link(pci); - dw_pcie_msi_init(pp); return 0; } diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index d02c7e74738d..7622f114223e 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -275,7 +275,7 @@ void dw_pcie_free_msi(struct pcie_port *pp) } } -void dw_pcie_msi_init(struct pcie_port *pp) +static void dw_pcie_msi_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); u64 msi_target = (u64)pp->msi_data; @@ -287,7 +287,6 @@ void dw_pcie_msi_init(struct pcie_port *pp) dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target)); dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); } -EXPORT_SYMBOL_GPL(dw_pcie_msi_init); int dw_pcie_host_init(struct pcie_port *pp) { @@ -545,6 +544,8 @@ void dw_pcie_setup_rc(struct pcie_port *pp) ~0); } } + if (pci_msi_enabled() && pp->msi_data) + dw_pcie_msi_init(pp); /* Setup RC BARs */ dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004); diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index e3e300669ed5..9ccf69a3dcf4 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -39,7 +39,6 @@ static int dw_plat_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); dw_pcie_wait_for_link(pci); - dw_pcie_msi_init(pp); return 0; } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 9d2f511f13fa..f9f6b276a11a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -365,7 +365,6 @@ static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci) #ifdef CONFIG_PCIE_DW_HOST irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); -void dw_pcie_msi_init(struct pcie_port *pp); void dw_pcie_free_msi(struct pcie_port *pp); void dw_pcie_setup_rc(struct pcie_port *pp); int dw_pcie_host_init(struct pcie_port *pp); @@ -379,10 +378,6 @@ static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) return IRQ_NONE; } -static inline void dw_pcie_msi_init(struct pcie_port *pp) -{ -} - static inline void dw_pcie_free_msi(struct pcie_port *pp) { } diff --git a/drivers/pci/controller/dwc/pcie-histb.c b/drivers/pci/controller/dwc/pcie-histb.c index afc1abbe49aa..aa9eaee2c4bd 100644 --- a/drivers/pci/controller/dwc/pcie-histb.c +++ b/drivers/pci/controller/dwc/pcie-histb.c @@ -202,7 +202,6 @@ static int histb_pcie_host_init(struct pcie_port *pp) pp->bridge->ops = &histb_pci_ops; histb_pcie_establish_link(pp); - dw_pcie_msi_init(pp); return 0; } diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 6f01ae013326..dc30e43a6be9 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -429,7 +429,6 @@ static int kirin_pcie_host_init(struct pcie_port *pp) pp->bridge->ops = &kirin_pci_ops; kirin_pcie_establish_link(pp); - dw_pcie_msi_init(pp); return 0; } diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 5eb28251dbee..4f66e534e011 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1271,7 +1271,6 @@ static int qcom_pcie_host_init(struct pcie_port *pp) } dw_pcie_setup_rc(pp); - dw_pcie_msi_init(pp); qcom_ep_reset_deassert(pcie); diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/controller/dwc/pcie-spear13xx.c index e348225f651f..c75550573a1e 100644 --- a/drivers/pci/controller/dwc/pcie-spear13xx.c +++ b/drivers/pci/controller/dwc/pcie-spear13xx.c @@ -129,11 +129,9 @@ static void spear13xx_pcie_enable_interrupts(struct spear13xx_pcie *spear13xx_pc struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; /* Enable MSI interrupt */ - if (IS_ENABLED(CONFIG_PCI_MSI)) { - dw_pcie_msi_init(pp); + if (IS_ENABLED(CONFIG_PCI_MSI)) writel(readl(&app_reg->int_mask) | MSI_CTRL_INT, &app_reg->int_mask); - } } static int spear13xx_pcie_link_up(struct dw_pcie *pci) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index aa511ec0d800..b093be21cab2 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -772,8 +772,6 @@ static void tegra_pcie_enable_msi_interrupts(struct pcie_port *pp) struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); u32 val; - dw_pcie_msi_init(pp); - /* Enable MSI interrupt generation */ val = appl_readl(pcie, APPL_INTR_EN_L0_0); val |= APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN; diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c index 48176265c867..c19bdfed4337 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -322,8 +322,6 @@ static int uniphier_pcie_host_init(struct pcie_port *pp) if (ret) return ret; - dw_pcie_msi_init(pp); - return 0; } -- 2.28.0
prev parent reply other threads:[~2020-10-09 8:38 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-09-24 11:05 [PATCH v2 0/5] PCI: dwc: improve msi handling Jisheng Zhang 2020-09-24 11:05 ` [PATCH v2 1/5] PCI: dwc: Call dma_unmap_page() before freeing the msi page Jisheng Zhang 2020-09-24 11:48 ` Gustavo Pimentel 2020-09-24 11:06 ` [PATCH v2 2/5] PCI: dwc: Check alloc_page() return value Jisheng Zhang 2020-09-24 11:47 ` Gustavo Pimentel 2020-09-29 17:29 ` Marc Zyngier 2020-09-30 1:23 ` Jisheng Zhang 2020-09-24 11:06 ` [PATCH v2 3/5] PCI: dwc: Rename dw_pcie_free_msi to dw_pcie_msi_deinit Jisheng Zhang 2020-09-24 11:49 ` Gustavo Pimentel 2020-09-24 11:07 ` [PATCH v2 4/5] PCI: dwc: Skip PCIE_MSI_INTR0* programming if MSI is disabled Jisheng Zhang 2020-09-24 11:49 ` Gustavo Pimentel 2020-09-24 11:07 ` [PATCH v2 5/5] PCI: dwc: Move dw_pcie_msi_init() from each users to designware host Jisheng Zhang 2020-10-08 5:43 ` Vidya Sagar 2021-03-07 22:10 ` Krzysztof Wilczyński 2021-03-11 6:50 ` Jisheng Zhang 2020-09-25 8:53 ` [PATCH v2 0/5] PCI: dwc: improve msi handling Jon Hunter 2020-09-25 9:17 ` Jisheng Zhang 2020-09-25 9:27 ` Jisheng Zhang 2020-09-25 15:13 ` Jon Hunter 2020-09-27 8:28 ` Jisheng Zhang 2020-09-28 17:46 ` Jon Hunter 2020-09-29 10:48 ` Jisheng Zhang 2020-09-29 13:22 ` Jon Hunter 2020-09-29 17:25 ` Marc Zyngier 2020-09-29 18:02 ` Jon Hunter 2020-09-29 18:12 ` Marc Zyngier 2020-10-06 6:26 ` Vidya Sagar 2020-10-06 6:36 ` Jisheng Zhang 2020-10-08 5:32 ` Vidya Sagar 2020-10-09 8:37 ` Jisheng Zhang [this message]
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20201009163747.64b1de4a@xhacker.debian \ --to=jisheng.zhang@synaptics.com \ --cc=agross@kernel.org \ --cc=bhelgaas@google.com \ --cc=bjorn.andersson@linaro.org \ --cc=festevam@gmail.com \ --cc=gustavo.pimentel@synopsys.com \ --cc=hayashi.kunihiko@socionext.com \ --cc=hongxing.zhu@nxp.com \ --cc=jbrunet@baylibre.com \ --cc=jesper.nilsson@axis.com \ --cc=jingoohan1@gmail.com \ --cc=jonathanh@nvidia.com \ --cc=kernel@pengutronix.de \ --cc=kgene@kernel.org \ --cc=khilman@baylibre.com \ --cc=kishon@ti.com \ --cc=krzk@kernel.org \ --cc=l.stach@pengutronix.de \ --cc=linux-amlogic@lists.infradead.org \ --cc=linux-arm-kernel@axis.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-arm-msm@vger.kernel.org \ --cc=linux-imx@nxp.com \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-omap@vger.kernel.org \ --cc=linux-pci@vger.kernel.org \ --cc=linux-samsung-soc@vger.kernel.org \ --cc=linux-tegra@vger.kernel.org \ --cc=lorenzo.pieralisi@arm.com \ --cc=martin.blumenstingl@googlemail.com \ --cc=narmstrong@baylibre.com \ --cc=pratyush.anand@gmail.com \ --cc=robh@kernel.org \ --cc=s.hauer@pengutronix.de \ --cc=shawnguo@kernel.org \ --cc=songxiaowei@hisilicon.com \ --cc=svarbanov@mm-sol.com \ --cc=thierry.reding@gmail.com \ --cc=vidyas@nvidia.com \ --cc=wangbinghui@hisilicon.com \ --cc=yamada.masahiro@socionext.com \ --cc=yue.wang@Amlogic.com \ --subject='Re: [PATCH] PCI: dwc: Move dw_pcie_msi_init() from each users to designware host' \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: link
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).