* [PATCH 4/6] reset: sunxi: Add compatible for Allwinner H3 bus resets @ 2015-10-21 16:20 Jens Kuske 2015-10-21 16:20 ` [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Jens Kuske ` (2 more replies) 0 siblings, 3 replies; 26+ messages in thread From: Jens Kuske @ 2015-10-21 16:20 UTC (permalink / raw) To: Maxime Ripard, Chen-Yu Tsai, Michael Turquette, Linus Walleij, Rob Herring, Philipp Zabel, Emilio López Cc: Vishnu Patekar, Hans de Goede, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Jens Kuske Adding a new compatible allows us to define SoC specific behaviour if necessary, for example forcing a particular device out of reset even if no driver is actually using it. Signed-off-by: Jens Kuske <jenskuske@gmail.com> --- Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt | 1 + drivers/reset/reset-sunxi.c | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt b/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt index c8f7757..e11f023 100644 --- a/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt +++ b/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt @@ -8,6 +8,7 @@ Required properties: - compatible: Should be one of the following: "allwinner,sun6i-a31-ahb1-reset" "allwinner,sun6i-a31-clock-reset" + "allwinner,sun8i-h3-bus-reset" - reg: should be register base and length as documented in the datasheet - #reset-cells: 1, see below diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c index 3d95c87..6f12b5c 100644 --- a/drivers/reset/reset-sunxi.c +++ b/drivers/reset/reset-sunxi.c @@ -124,6 +124,7 @@ err_alloc: */ static const struct of_device_id sunxi_early_reset_dt_ids[] __initdata = { { .compatible = "allwinner,sun6i-a31-ahb1-reset", }, + { .compatible = "allwinner,sun8i-h3-bus-reset", }, { /* sentinel */ }, }; -- 2.6.1 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-10-21 16:20 [PATCH 4/6] reset: sunxi: Add compatible for Allwinner H3 bus resets Jens Kuske @ 2015-10-21 16:20 ` Jens Kuske 2015-10-22 8:05 ` Maxime Ripard ` (2 more replies) 2015-10-21 16:20 ` [PATCH 6/6] ARM: dts: sun8i: Add Orange Pi Plus support Jens Kuske 2015-10-22 7:58 ` [PATCH 4/6] reset: sunxi: Add compatible for Allwinner H3 bus resets Maxime Ripard 2 siblings, 3 replies; 26+ messages in thread From: Jens Kuske @ 2015-10-21 16:20 UTC (permalink / raw) To: Maxime Ripard, Chen-Yu Tsai, Michael Turquette, Linus Walleij, Rob Herring, Philipp Zabel, Emilio López Cc: Vishnu Patekar, Hans de Goede, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Jens Kuske The Allwinner H3 is a home entertainment system oriented SoC with four Cortex-A7 cores and a Mali-400MP2 GPU. Signed-off-by: Jens Kuske <jenskuske@gmail.com> --- arch/arm/boot/dts/sun8i-h3.dtsi | 499 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 499 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi new file mode 100644 index 0000000..4114e17 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -0,0 +1,499 @@ +/* + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "skeleton.dtsi" + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <24000000>; + arm,cpu-registers-not-fw-configured; + }; + + memory { + reg = <0x40000000 0x80000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + pll1: clk@01c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll1"; + }; + + /* dummy clock until actually implemented */ + pll5: pll5_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "pll5"; + }; + + pll6: clk@01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun6i-a31-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6", "pll6x2", "pll6d2"; + }; + + pll8: clk@01c20044 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-pll6-clk"; + reg = <0x01c20044 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll8", "pll8x2"; + }; + + cpu: cpu_clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-cpu-clk"; + reg = <0x01c20050 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; + clock-output-names = "cpu"; + }; + + axi: axi_clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-axi-clk"; + reg = <0x01c20050 0x4>; + clocks = <&cpu>; + clock-output-names = "axi"; + }; + + ahb1: ahb1_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-ahb1-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; + clock-output-names = "ahb1"; + }; + + ahb2: ahb2_clk@01c2005c { + #clock-cells = <0>; + compatible = "allwinner,sun8i-h3-ahb2-clk"; + reg = <0x01c2005c 0x4>; + clocks = <&ahb1>, <&pll6 2>; + clock-output-names = "ahb2"; + }; + + apb1: apb1_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb1>; + clock-output-names = "apb1"; + }; + + apb2: apb2_clk@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb1-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; + clock-output-names = "apb2"; + }; + + bus_gates: clk@01c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun8i-h3-bus-gates-clk"; + reg = <0x01c20060 0x14>; + clock-indices = <5>, <6>, <8>, + <9>, <10>, <13>, + <14>, <17>, <18>, + <19>, <20>, + <21>, <23>, + <24>, <25>, + <26>, <27>, + <28>, <29>, + <30>, <31>, <32>, + <35>, <36>, <37>, + <40>, <41>, <43>, + <44>, <52>, <53>, + <54>, <64>, + <65>, <69>, <72>, + <76>, <77>, <78>, + <96>, <97>, <98>, + <112>, <113>, + <114>, <115>, <116>, + <128>, <135>; + clocks = <&ahb1>, <&ahb1>, <&ahb1>, + <&ahb1>, <&ahb1>, <&ahb1>, + <&ahb1>, <&ahb2>, <&ahb1>, + <&ahb1>, <&ahb1>, + <&ahb1>, <&ahb1>, + <&ahb1>, <&ahb1>, + <&ahb1>, <&ahb1>, + <&ahb1>, <&ahb2>, + <&ahb2>, <&ahb2>, <&ahb1>, + <&ahb1>, <&ahb1>, <&ahb1>, + <&ahb1>, <&ahb1>, <&ahb1>, + <&ahb1>, <&ahb1>, <&ahb1>, + <&ahb1>, <&apb1>, + <&apb1>, <&apb1>, <&apb1>, + <&apb1>, <&apb1>, <&apb1>, + <&apb2>, <&apb2>, <&apb2>, + <&apb2>, <&apb2>, + <&apb2>, <&apb2>, <&apb2>, + <&ahb1>, <&ahb1>; + clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0", + "ahb1_mmc1", "ahb1_mmc2", "ahb1_nand", + "ahb1_sdram", "ahb2_gmac", "ahb1_ts", + "ahb1_hstimer", "ahb1_spi0", + "ahb1_spi1", "ahb1_otg", + "ahb1_otg_ehci0", "ahb1_ehic1", + "ahb1_ehic2", "ahb1_ehic3", + "ahb1_otg_ohci0", "ahb2_ohic1", + "ahb2_ohic2", "ahb2_ohic3", "ahb1_ve", + "ahb1_lcd0", "ahb1_lcd1", "ahb1_deint", + "ahb1_csi", "ahb1_tve", "ahb1_hdmi", + "ahb1_de", "ahb1_gpu", "ahb1_msgbox", + "ahb1_spinlock", "apb1_codec", + "apb1_spdif", "apb1_pio", "apb1_ths", + "apb1_i2s0", "apb1_i2s1", "apb1_i2s2", + "apb2_i2c0", "apb2_i2c1", "apb2_i2c2", + "apb2_uart0", "apb2_uart1", + "apb2_uart2", "apb2_uart3", "apb2_scr", + "ahb1_ephy", "ahb1_dbg"; + }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; + clock-output-names = "mmc0", + "mmc0_output", + "mmc0_sample"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; + clock-output-names = "mmc1", + "mmc1_output", + "mmc1_sample"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; + clock-output-names = "mmc2", + "mmc2_output", + "mmc2_sample"; + }; + + mbus_clk: clk@01c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-mbus-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5>; + clock-output-names = "mbus"; + }; + }; + + soc@01c00000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dma: dma-controller@01c02000 { + compatible = "allwinner,sun8i-h3-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 6>; + resets = <&bus_rst 6>; + #dma-cells = <1>; + }; + + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&bus_gates 8>, + <&mmc0_clk 0>, + <&mmc0_clk 1>, + <&mmc0_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&bus_rst 8>; + reset-names = "ahb"; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&bus_gates 9>, + <&mmc1_clk 0>, + <&mmc1_clk 1>, + <&mmc1_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&bus_rst 9>; + reset-names = "ahb"; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&bus_gates 10>, + <&mmc2_clk 0>, + <&mmc2_clk 1>, + <&mmc2_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&bus_rst 10>; + reset-names = "ahb"; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + pio: pinctrl@01c20800 { + compatible = "allwinner,sun8i-h3-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 69>; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <2>; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PA4", "PA5"; + allwinner,function = "uart0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc0_cd_pin: mmc0_cd_pin@0 { + allwinner,pins = "PF6"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + mmc1_pins_a: mmc1@0 { + allwinner,pins = "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + allwinner,function = "mmc1"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + }; + + bus_rst: reset@01c202c0 { + #reset-cells = <1>; + compatible = "allwinner,sun8i-h3-bus-reset"; + reg = <0x01c202c0 0x1c>; + }; + + timer@01c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0xa0>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>; + }; + + wdt0: watchdog@01c20ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + }; + + uart0: serial@01c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 112>; + resets = <&bus_rst 208>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart1: serial@01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 113>; + resets = <&bus_rst 209>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@01c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 114>; + resets = <&bus_rst 210>; + dmas = <&dma 8>, <&dma 8>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart3: serial@01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 115>; + resets = <&bus_rst 211>; + dmas = <&dma 9>, <&dma 9>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x1000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + rtc: rtc@01f00000 { + compatible = "allwinner,sun6i-a31-rtc"; + reg = <0x01f00000 0x54>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +}; -- 2.6.1 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-10-21 16:20 ` [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Jens Kuske @ 2015-10-22 8:05 ` Maxime Ripard 2015-10-22 8:29 ` Jean-Francois Moine 2015-10-22 17:30 ` Jean-Francois Moine 2015-10-23 18:14 ` Maxime Ripard 2 siblings, 1 reply; 26+ messages in thread From: Maxime Ripard @ 2015-10-22 8:05 UTC (permalink / raw) To: Jens Kuske Cc: Chen-Yu Tsai, Michael Turquette, Linus Walleij, Rob Herring, Philipp Zabel, Emilio López, Vishnu Patekar, Hans de Goede, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 10801 bytes --] Hi, On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > The Allwinner H3 is a home entertainment system oriented SoC with > four Cortex-A7 cores and a Mali-400MP2 GPU. > > Signed-off-by: Jens Kuske <jenskuske@gmail.com> > --- > arch/arm/boot/dts/sun8i-h3.dtsi | 499 ++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 499 insertions(+) > create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi > new file mode 100644 > index 0000000..4114e17 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > @@ -0,0 +1,499 @@ > +/* > + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#include "skeleton.dtsi" > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/pinctrl/sun4i-a10.h> > + > +/ { > + interrupt-parent = <&gic>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0>; > + }; > + > + cpu@1 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <1>; > + }; > + > + cpu@2 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <2>; > + }; > + > + cpu@3 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <3>; > + }; > + }; > + > + timer { > + compatible = "arm,armv7-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; > + clock-frequency = <24000000>; > + arm,cpu-registers-not-fw-configured; > + }; > + > + memory { > + reg = <0x40000000 0x80000000>; > + }; > + > + clocks { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + osc24M: osc24M_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + clock-output-names = "osc24M"; > + }; > + > + osc32k: osc32k_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <32768>; > + clock-output-names = "osc32k"; > + }; > + > + pll1: clk@01c20000 { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-a23-pll1-clk"; > + reg = <0x01c20000 0x4>; > + clocks = <&osc24M>; > + clock-output-names = "pll1"; > + }; > + > + /* dummy clock until actually implemented */ > + pll5: pll5_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <0>; > + clock-output-names = "pll5"; > + }; > + > + pll6: clk@01c20028 { > + #clock-cells = <1>; > + compatible = "allwinner,sun6i-a31-pll6-clk"; > + reg = <0x01c20028 0x4>; > + clocks = <&osc24M>; > + clock-output-names = "pll6", "pll6x2", "pll6d2"; > + }; > + > + pll8: clk@01c20044 { > + #clock-cells = <0>; > + compatible = "allwinner,sun6i-a31-pll6-clk"; > + reg = <0x01c20044 0x4>; > + clocks = <&osc24M>; > + clock-output-names = "pll8", "pll8x2"; > + }; > + > + cpu: cpu_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-cpu-clk"; > + reg = <0x01c20050 0x4>; > + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; > + clock-output-names = "cpu"; > + }; > + > + axi: axi_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-axi-clk"; > + reg = <0x01c20050 0x4>; > + clocks = <&cpu>; > + clock-output-names = "axi"; > + }; > + > + ahb1: ahb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun6i-a31-ahb1-clk"; > + reg = <0x01c20054 0x4>; > + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; > + clock-output-names = "ahb1"; > + }; > + > + ahb2: ahb2_clk@01c2005c { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-h3-ahb2-clk"; > + reg = <0x01c2005c 0x4>; > + clocks = <&ahb1>, <&pll6 2>; > + clock-output-names = "ahb2"; > + }; > + > + apb1: apb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb0-clk"; > + reg = <0x01c20054 0x4>; > + clocks = <&ahb1>; > + clock-output-names = "apb1"; > + }; > + > + apb2: apb2_clk@01c20058 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb1-clk"; > + reg = <0x01c20058 0x4>; > + clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; > + clock-output-names = "apb2"; > + }; > + > + bus_gates: clk@01c20060 { > + #clock-cells = <1>; > + compatible = "allwinner,sun8i-h3-bus-gates-clk"; > + reg = <0x01c20060 0x14>; > + clock-indices = <5>, <6>, <8>, > + <9>, <10>, <13>, > + <14>, <17>, <18>, > + <19>, <20>, > + <21>, <23>, > + <24>, <25>, > + <26>, <27>, > + <28>, <29>, > + <30>, <31>, <32>, > + <35>, <36>, <37>, > + <40>, <41>, <43>, > + <44>, <52>, <53>, > + <54>, <64>, > + <65>, <69>, <72>, > + <76>, <77>, <78>, > + <96>, <97>, <98>, > + <112>, <113>, > + <114>, <115>, <116>, > + <128>, <135>; > + clocks = <&ahb1>, <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb2>, <&ahb1>, > + <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb2>, > + <&ahb2>, <&ahb2>, <&ahb1>, > + <&ahb1>, <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, <&ahb1>, > + <&ahb1>, <&apb1>, > + <&apb1>, <&apb1>, <&apb1>, > + <&apb1>, <&apb1>, <&apb1>, > + <&apb2>, <&apb2>, <&apb2>, > + <&apb2>, <&apb2>, > + <&apb2>, <&apb2>, <&apb2>, > + <&ahb1>, <&ahb1>; > + clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0", > + "ahb1_mmc1", "ahb1_mmc2", "ahb1_nand", > + "ahb1_sdram", "ahb2_gmac", "ahb1_ts", > + "ahb1_hstimer", "ahb1_spi0", > + "ahb1_spi1", "ahb1_otg", > + "ahb1_otg_ehci0", "ahb1_ehic1", > + "ahb1_ehic2", "ahb1_ehic3", > + "ahb1_otg_ohci0", "ahb2_ohic1", > + "ahb2_ohic2", "ahb2_ohic3", "ahb1_ve", > + "ahb1_lcd0", "ahb1_lcd1", "ahb1_deint", > + "ahb1_csi", "ahb1_tve", "ahb1_hdmi", > + "ahb1_de", "ahb1_gpu", "ahb1_msgbox", > + "ahb1_spinlock", "apb1_codec", > + "apb1_spdif", "apb1_pio", "apb1_ths", > + "apb1_i2s0", "apb1_i2s1", "apb1_i2s2", > + "apb2_i2c0", "apb2_i2c1", "apb2_i2c2", > + "apb2_uart0", "apb2_uart1", > + "apb2_uart2", "apb2_uart3", "apb2_scr", > + "ahb1_ephy", "ahb1_dbg"; > + }; > + > + mmc0_clk: clk@01c20088 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c20088 0x4>; > + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; > + clock-output-names = "mmc0", > + "mmc0_output", > + "mmc0_sample"; > + }; > + > + mmc1_clk: clk@01c2008c { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c2008c 0x4>; > + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; > + clock-output-names = "mmc1", > + "mmc1_output", > + "mmc1_sample"; > + }; > + > + mmc2_clk: clk@01c20090 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c20090 0x4>; > + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; > + clock-output-names = "mmc2", > + "mmc2_output", > + "mmc2_sample"; > + }; > + > + mbus_clk: clk@01c2015c { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-a23-mbus-clk"; > + reg = <0x01c2015c 0x4>; > + clocks = <&osc24M>, <&pll6 1>, <&pll5>; > + clock-output-names = "mbus"; > + }; > + }; > + > + soc@01c00000 { We had some issues with this in the past, especially since it's wrong and the SoC registers definitions start at 0, with the SRAMs. It would be better if you removed it entirely like we did in the A80 DTSI. > + uart0: serial@01c28000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28000 0x400>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&bus_gates 112>; > + resets = <&bus_rst 208>; It's a bit weird that the clocks and reset indices don't match, usually they do. What's even weirder is that there's a 96 offset between the two (4 * 32), is this expected? Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-10-22 8:05 ` Maxime Ripard @ 2015-10-22 8:29 ` Jean-Francois Moine 2015-10-22 8:47 ` Maxime Ripard 0 siblings, 1 reply; 26+ messages in thread From: Jean-Francois Moine @ 2015-10-22 8:29 UTC (permalink / raw) To: Maxime Ripard Cc: Jens Kuske, devicetree, Vishnu Patekar, Emilio López, Michael Turquette, linux-sunxi, linux-kernel, Hans de Goede, Chen-Yu Tsai, Rob Herring, Philipp Zabel, Linus Walleij, linux-arm-kernel On Thu, 22 Oct 2015 10:05:08 +0200 Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > > + uart0: serial@01c28000 { > > + compatible = "snps,dw-apb-uart"; > > + reg = <0x01c28000 0x400>; > > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; > > + reg-shift = <2>; > > + reg-io-width = <4>; > > + clocks = <&bus_gates 112>; > > + resets = <&bus_rst 208>; > > It's a bit weird that the clocks and reset indices don't match, > usually they do. > > What's even weirder is that there's a 96 offset between the two (4 * > 32), is this expected? Yes, this is conform to the H3 documentation. -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/ ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-10-22 8:29 ` Jean-Francois Moine @ 2015-10-22 8:47 ` Maxime Ripard 2015-10-22 8:57 ` Jean-Francois Moine 0 siblings, 1 reply; 26+ messages in thread From: Maxime Ripard @ 2015-10-22 8:47 UTC (permalink / raw) To: Jean-Francois Moine Cc: Jens Kuske, devicetree, Vishnu Patekar, Emilio López, Michael Turquette, linux-sunxi, linux-kernel, Hans de Goede, Chen-Yu Tsai, Rob Herring, Philipp Zabel, Linus Walleij, linux-arm-kernel [-- Attachment #1: Type: text/plain, Size: 990 bytes --] On Thu, Oct 22, 2015 at 10:29:59AM +0200, Jean-Francois Moine wrote: > On Thu, 22 Oct 2015 10:05:08 +0200 > Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > > > > + uart0: serial@01c28000 { > > > + compatible = "snps,dw-apb-uart"; > > > + reg = <0x01c28000 0x400>; > > > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; > > > + reg-shift = <2>; > > > + reg-io-width = <4>; > > > + clocks = <&bus_gates 112>; > > > + resets = <&bus_rst 208>; > > > > It's a bit weird that the clocks and reset indices don't match, > > usually they do. > > > > What's even weirder is that there's a 96 offset between the two (4 * > > 32), is this expected? > > Yes, this is conform to the H3 documentation. Not really. The uart0 reset is the bit 16, in the reset register 4. 4 * 32 + 16 = 44. Not 112, but still not 208 either. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-10-22 8:47 ` Maxime Ripard @ 2015-10-22 8:57 ` Jean-Francois Moine 2015-10-22 9:14 ` Maxime Ripard 0 siblings, 1 reply; 26+ messages in thread From: Jean-Francois Moine @ 2015-10-22 8:57 UTC (permalink / raw) To: Maxime Ripard Cc: Jens Kuske, devicetree, Vishnu Patekar, Emilio López, Michael Turquette, linux-sunxi, linux-kernel, Hans de Goede, Chen-Yu Tsai, Rob Herring, Philipp Zabel, Linus Walleij, linux-arm-kernel On Thu, 22 Oct 2015 10:47:35 +0200 Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > Not really. The uart0 reset is the bit 16, in the reset register 4. > > 4 * 32 + 16 = 44. > > Not 112, but still not 208 either. The registers are numbered 1..5, then (4 - 1) * 32 + 16 = 112 -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/ ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-10-22 8:57 ` Jean-Francois Moine @ 2015-10-22 9:14 ` Maxime Ripard 2015-10-22 11:30 ` Jens Kuske 0 siblings, 1 reply; 26+ messages in thread From: Maxime Ripard @ 2015-10-22 9:14 UTC (permalink / raw) To: Jean-Francois Moine Cc: Jens Kuske, devicetree, Vishnu Patekar, Emilio López, Michael Turquette, linux-sunxi, linux-kernel, Hans de Goede, Chen-Yu Tsai, Rob Herring, Philipp Zabel, Linus Walleij, linux-arm-kernel [-- Attachment #1: Type: text/plain, Size: 622 bytes --] On Thu, Oct 22, 2015 at 10:57:45AM +0200, Jean-Francois Moine wrote: > On Thu, 22 Oct 2015 10:47:35 +0200 > Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > > > Not really. The uart0 reset is the bit 16, in the reset register 4. > > > > 4 * 32 + 16 = 44. > > > > Not 112, but still not 208 either. > > The registers are numbered 1..5, then > > (4 - 1) * 32 + 16 = 112 Not on my version, and even then, UARTs are on the last reset register, which would still make 144. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-10-22 9:14 ` Maxime Ripard @ 2015-10-22 11:30 ` Jens Kuske 2015-10-23 18:09 ` Maxime Ripard 0 siblings, 1 reply; 26+ messages in thread From: Jens Kuske @ 2015-10-22 11:30 UTC (permalink / raw) To: Maxime Ripard Cc: Jean-Francois Moine, devicetree, Vishnu Patekar, Emilio López, Michael Turquette, linux-sunxi, linux-kernel, Hans de Goede, Chen-Yu Tsai, Rob Herring, Philipp Zabel, Linus Walleij, linux-arm-kernel On 22/10/15 11:14, Maxime Ripard wrote: > On Thu, Oct 22, 2015 at 10:57:45AM +0200, Jean-Francois Moine wrote: >> On Thu, 22 Oct 2015 10:47:35 +0200 >> Maxime Ripard <maxime.ripard@free-electrons.com> wrote: >> >>> Not really. The uart0 reset is the bit 16, in the reset register 4. >>> >>> 4 * 32 + 16 = 44. >>> >>> Not 112, but still not 208 either. >> >> The registers are numbered 1..5, then >> >> (4 - 1) * 32 + 16 = 112 > > Not on my version, and even then, UARTs are on the last reset > register, which would still make 144. > > Maxime > There are holes between reg2 and reg3 and reg4 for some reason, but even if we would correct that with some of_xlate() function they won't completely line up with the gates. Jens ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-10-22 11:30 ` Jens Kuske @ 2015-10-23 18:09 ` Maxime Ripard 0 siblings, 0 replies; 26+ messages in thread From: Maxime Ripard @ 2015-10-23 18:09 UTC (permalink / raw) To: Jens Kuske Cc: Jean-Francois Moine, devicetree, Vishnu Patekar, Emilio López, Michael Turquette, linux-sunxi, linux-kernel, Hans de Goede, Chen-Yu Tsai, Rob Herring, Philipp Zabel, Linus Walleij, linux-arm-kernel [-- Attachment #1: Type: text/plain, Size: 1092 bytes --] On Thu, Oct 22, 2015 at 01:30:42PM +0200, Jens Kuske wrote: > On 22/10/15 11:14, Maxime Ripard wrote: > > On Thu, Oct 22, 2015 at 10:57:45AM +0200, Jean-Francois Moine wrote: > >> On Thu, 22 Oct 2015 10:47:35 +0200 > >> Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > >> > >>> Not really. The uart0 reset is the bit 16, in the reset register 4. > >>> > >>> 4 * 32 + 16 = 44. > >>> > >>> Not 112, but still not 208 either. > >> > >> The registers are numbered 1..5, then > >> > >> (4 - 1) * 32 + 16 = 112 > > > > Not on my version, and even then, UARTs are on the last reset > > register, which would still make 144. > > > > Maxime > > > > There are holes between reg2 and reg3 and reg4 for some reason, but even > if we would correct that with some of_xlate() function they won't > completely line up with the gates. Indeed. Still, dealing with the holes and sticking to what the datasheet says seems like the right solution. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-10-21 16:20 ` [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Jens Kuske 2015-10-22 8:05 ` Maxime Ripard @ 2015-10-22 17:30 ` Jean-Francois Moine 2015-10-23 18:14 ` Maxime Ripard 2 siblings, 0 replies; 26+ messages in thread From: Jean-Francois Moine @ 2015-10-22 17:30 UTC (permalink / raw) To: Jens Kuske Cc: Maxime Ripard, Chen-Yu Tsai, Michael Turquette, Linus Walleij, Rob Herring, Philipp Zabel, Emilio López, devicetree, Vishnu Patekar, linux-kernel, Hans de Goede, linux-sunxi, linux-arm-kernel On Wed, 21 Oct 2015 18:20:27 +0200 Jens Kuske <jenskuske@gmail.com> wrote: > The Allwinner H3 is a home entertainment system oriented SoC with > four Cortex-A7 cores and a Mali-400MP2 GPU. > > Signed-off-by: Jens Kuske <jenskuske@gmail.com> > --- > arch/arm/boot/dts/sun8i-h3.dtsi | 499 ++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 499 insertions(+) > create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi > new file mode 100644 > index 0000000..4114e17 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > @@ -0,0 +1,499 @@ [snip] > + pll6: clk@01c20028 { > + #clock-cells = <1>; > + compatible = "allwinner,sun6i-a31-pll6-clk"; > + reg = <0x01c20028 0x4>; > + clocks = <&osc24M>; > + clock-output-names = "pll6", "pll6x2", "pll6d2"; > + }; > + > + pll8: clk@01c20044 { > + #clock-cells = <0>; Should be <1> > + compatible = "allwinner,sun6i-a31-pll6-clk"; > + reg = <0x01c20044 0x4>; > + clocks = <&osc24M>; > + clock-output-names = "pll8", "pll8x2"; > + }; > + > + cpu: cpu_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-cpu-clk"; > + reg = <0x01c20050 0x4>; > + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; > + clock-output-names = "cpu"; > + }; [snip] -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/ ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-10-21 16:20 ` [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Jens Kuske 2015-10-22 8:05 ` Maxime Ripard 2015-10-22 17:30 ` Jean-Francois Moine @ 2015-10-23 18:14 ` Maxime Ripard 2015-10-23 19:20 ` Jean-Francois Moine 2015-10-24 8:39 ` Hans de Goede 2 siblings, 2 replies; 26+ messages in thread From: Maxime Ripard @ 2015-10-23 18:14 UTC (permalink / raw) To: Jens Kuske Cc: Chen-Yu Tsai, Michael Turquette, Linus Walleij, Rob Herring, Philipp Zabel, Emilio López, Vishnu Patekar, Hans de Goede, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 1850 bytes --] On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + bus_gates: clk@01c20060 { > + #clock-cells = <1>; > + compatible = "allwinner,sun8i-h3-bus-gates-clk"; > + reg = <0x01c20060 0x14>; > + clock-indices = <5>, <6>, <8>, > + <9>, <10>, <13>, > + <14>, <17>, <18>, > + <19>, <20>, > + <21>, <23>, > + <24>, <25>, > + <26>, <27>, > + <28>, <29>, > + <30>, <31>, <32>, > + <35>, <36>, <37>, > + <40>, <41>, <43>, > + <44>, <52>, <53>, > + <54>, <64>, > + <65>, <69>, <72>, > + <76>, <77>, <78>, > + <96>, <97>, <98>, > + <112>, <113>, > + <114>, <115>, <116>, > + <128>, <135>; > + clocks = <&ahb1>, <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb2>, <&ahb1>, > + <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb2>, > + <&ahb2>, <&ahb2>, <&ahb1>, > + <&ahb1>, <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, <&ahb1>, > + <&ahb1>, <&apb1>, > + <&apb1>, <&apb1>, <&apb1>, > + <&apb1>, <&apb1>, <&apb1>, > + <&apb2>, <&apb2>, <&apb2>, > + <&apb2>, <&apb2>, > + <&apb2>, <&apb2>, <&apb2>, > + <&ahb1>, <&ahb1>; This is not really what I had in mind... This IP has 2 parents, and only two parents. The mapping between the IPs should be done in the driver itself, not in the DT where it is very error prone and barely readable. And note that I never have expected you to use clk-simple-gates either. This is a complicated clock, unlike the other we've seen so far, it definitely deserves a driver of its own. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-10-23 18:14 ` Maxime Ripard @ 2015-10-23 19:20 ` Jean-Francois Moine 2015-10-24 7:13 ` Maxime Ripard 2015-10-24 8:39 ` Hans de Goede 1 sibling, 1 reply; 26+ messages in thread From: Jean-Francois Moine @ 2015-10-23 19:20 UTC (permalink / raw) To: Maxime Ripard Cc: Jens Kuske, devicetree, Vishnu Patekar, Emilio López, Michael Turquette, linux-sunxi, linux-kernel, Hans de Goede, Chen-Yu Tsai, Rob Herring, Philipp Zabel, Linus Walleij, linux-arm-kernel On Fri, 23 Oct 2015 20:14:06 +0200 Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > > + bus_gates: clk@01c20060 { > > + #clock-cells = <1>; > > + compatible = "allwinner,sun8i-h3-bus-gates-clk"; > > + reg = <0x01c20060 0x14>; > > + clock-indices = <5>, <6>, <8>, > > + <9>, <10>, <13>, > > + <14>, <17>, <18>, > > + <19>, <20>, > > + <21>, <23>, > > + <24>, <25>, > > + <26>, <27>, > > + <28>, <29>, > > + <30>, <31>, <32>, > > + <35>, <36>, <37>, > > + <40>, <41>, <43>, > > + <44>, <52>, <53>, > > + <54>, <64>, > > + <65>, <69>, <72>, > > + <76>, <77>, <78>, > > + <96>, <97>, <98>, > > + <112>, <113>, > > + <114>, <115>, <116>, > > + <128>, <135>; > > + clocks = <&ahb1>, <&ahb1>, <&ahb1>, > > + <&ahb1>, <&ahb1>, <&ahb1>, > > + <&ahb1>, <&ahb2>, <&ahb1>, > > + <&ahb1>, <&ahb1>, > > + <&ahb1>, <&ahb1>, > > + <&ahb1>, <&ahb1>, > > + <&ahb1>, <&ahb1>, > > + <&ahb1>, <&ahb2>, > > + <&ahb2>, <&ahb2>, <&ahb1>, > > + <&ahb1>, <&ahb1>, <&ahb1>, > > + <&ahb1>, <&ahb1>, <&ahb1>, > > + <&ahb1>, <&ahb1>, <&ahb1>, > > + <&ahb1>, <&apb1>, > > + <&apb1>, <&apb1>, <&apb1>, > > + <&apb1>, <&apb1>, <&apb1>, > > + <&apb2>, <&apb2>, <&apb2>, > > + <&apb2>, <&apb2>, > > + <&apb2>, <&apb2>, <&apb2>, > > + <&ahb1>, <&ahb1>; > > This is not really what I had in mind... > > This IP has 2 parents, and only two parents. The mapping between the > IPs should be done in the driver itself, not in the DT where it is > very error prone and barely readable. > > And note that I never have expected you to use clk-simple-gates > either. This is a complicated clock, unlike the other we've seen so > far, it definitely deserves a driver of its own. It seems that Allwinner puts the gate definitions anywhere in the array of registers, so, I think that the H3 scheme will not be the last complicated one, and if the parent clocks are in the code instead of in the DT, we will have more and more code to develop. An other way to describe the gates would be to add containers per parent (with still a small patch in the clk-simple-gates): bus_gates: clk@01c20060 { #clock-cells = <1>; compatible = "allwinner,sun8i-h3-bus-gates-clk"; reg = <0x01c20060 0x14>; ahb1_gates { clocks = <&ahb1>; clock-indices = <5>, <6>, <8>, <9>, <10>, <13>, <14>, <18>, <19>, <20>, ...; }; clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2", "ahb1_nand", "ahb1_sdram", "ahb1_ts", "ahb1_hstimer", "ahb1_spi0", ...; }; ahb2_gates { clocks = <&ahb2>; clock-indices = <17>, <29>, <30>, <31>, <32>, ...; clock-output-names = "ahb2_gmac", "ahb2_ohic1", "ahb2_ohic2", "ahb2_ohic3", "ahb1_ve", ...; }; apb1_gates { ... }; apb2_gates { ... }; }; -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/ ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-10-23 19:20 ` Jean-Francois Moine @ 2015-10-24 7:13 ` Maxime Ripard 2015-10-24 8:47 ` Jean-Francois Moine 0 siblings, 1 reply; 26+ messages in thread From: Maxime Ripard @ 2015-10-24 7:13 UTC (permalink / raw) To: Jean-Francois Moine Cc: Jens Kuske, devicetree, Vishnu Patekar, Emilio López, Michael Turquette, linux-sunxi, linux-kernel, Hans de Goede, Chen-Yu Tsai, Rob Herring, Philipp Zabel, Linus Walleij, linux-arm-kernel [-- Attachment #1: Type: text/plain, Size: 3751 bytes --] On Fri, Oct 23, 2015 at 09:20:13PM +0200, Jean-Francois Moine wrote: > On Fri, 23 Oct 2015 20:14:06 +0200 > Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > > > On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > > > + bus_gates: clk@01c20060 { > > > + #clock-cells = <1>; > > > + compatible = "allwinner,sun8i-h3-bus-gates-clk"; > > > + reg = <0x01c20060 0x14>; > > > + clock-indices = <5>, <6>, <8>, > > > + <9>, <10>, <13>, > > > + <14>, <17>, <18>, > > > + <19>, <20>, > > > + <21>, <23>, > > > + <24>, <25>, > > > + <26>, <27>, > > > + <28>, <29>, > > > + <30>, <31>, <32>, > > > + <35>, <36>, <37>, > > > + <40>, <41>, <43>, > > > + <44>, <52>, <53>, > > > + <54>, <64>, > > > + <65>, <69>, <72>, > > > + <76>, <77>, <78>, > > > + <96>, <97>, <98>, > > > + <112>, <113>, > > > + <114>, <115>, <116>, > > > + <128>, <135>; > > > + clocks = <&ahb1>, <&ahb1>, <&ahb1>, > > > + <&ahb1>, <&ahb1>, <&ahb1>, > > > + <&ahb1>, <&ahb2>, <&ahb1>, > > > + <&ahb1>, <&ahb1>, > > > + <&ahb1>, <&ahb1>, > > > + <&ahb1>, <&ahb1>, > > > + <&ahb1>, <&ahb1>, > > > + <&ahb1>, <&ahb2>, > > > + <&ahb2>, <&ahb2>, <&ahb1>, > > > + <&ahb1>, <&ahb1>, <&ahb1>, > > > + <&ahb1>, <&ahb1>, <&ahb1>, > > > + <&ahb1>, <&ahb1>, <&ahb1>, > > > + <&ahb1>, <&apb1>, > > > + <&apb1>, <&apb1>, <&apb1>, > > > + <&apb1>, <&apb1>, <&apb1>, > > > + <&apb2>, <&apb2>, <&apb2>, > > > + <&apb2>, <&apb2>, > > > + <&apb2>, <&apb2>, <&apb2>, > > > + <&ahb1>, <&ahb1>; > > > > This is not really what I had in mind... > > > > This IP has 2 parents, and only two parents. The mapping between the > > IPs should be done in the driver itself, not in the DT where it is > > very error prone and barely readable. > > > > And note that I never have expected you to use clk-simple-gates > > either. This is a complicated clock, unlike the other we've seen so > > far, it definitely deserves a driver of its own. > > It seems that Allwinner puts the gate definitions anywhere in the array > of registers, so, I think that the H3 scheme will not be the last > complicated one, Maybe, but that's the first one. It doesn't prevent us from reusing the driver later if it happens. > and if the parent clocks are in the code instead of in the DT, we > will have more and more code to develop. I never asked that either. > An other way to describe the gates would be to add containers per parent > (with still a small patch in the clk-simple-gates): > > bus_gates: clk@01c20060 { > #clock-cells = <1>; > compatible = "allwinner,sun8i-h3-bus-gates-clk"; > reg = <0x01c20060 0x14>; > ahb1_gates { > clocks = <&ahb1>; > clock-indices = <5>, <6>, <8>, > <9>, <10>, <13>, > <14>, <18>, > <19>, <20>, > ...; > }; > clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0", > "ahb1_mmc1", "ahb1_mmc2", "ahb1_nand", > "ahb1_sdram", "ahb1_ts", > "ahb1_hstimer", "ahb1_spi0", > ...; > }; > ahb2_gates { > clocks = <&ahb2>; > clock-indices = <17>, <29>, > <30>, <31>, <32>, > ...; > clock-output-names = "ahb2_gmac", "ahb2_ohic1", > "ahb2_ohic2", "ahb2_ohic3", "ahb1_ve", > ...; > }; > apb1_gates { > ... > }; > apb2_gates { > ... > }; > }; Or simply bus_gates { clocks = <&ahb1>, <&ahb2>; clock-indices = <5>, <6>, <8>, ... clock-output-names = "bus_ce", "bus_dma", "bus_mmc0" }; Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-10-24 7:13 ` Maxime Ripard @ 2015-10-24 8:47 ` Jean-Francois Moine 2015-10-26 21:06 ` Maxime Ripard 0 siblings, 1 reply; 26+ messages in thread From: Jean-Francois Moine @ 2015-10-24 8:47 UTC (permalink / raw) To: Maxime Ripard Cc: Jens Kuske, devicetree, Vishnu Patekar, Emilio López, Michael Turquette, linux-sunxi, linux-kernel, Hans de Goede, Chen-Yu Tsai, Rob Herring, Philipp Zabel, Linus Walleij, linux-arm-kernel On Sat, 24 Oct 2015 09:13:28 +0200 Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > Or simply > > bus_gates { > clocks = <&ahb1>, <&ahb2>; > clock-indices = <5>, <6>, <8>, ... > clock-output-names = "bus_ce", "bus_dma", "bus_mmc0" > }; I don't understand: the apb1, apb2, ahb1 and ahb2 clocks may be programmed independently to different frequencies and you have to know which of them is the parent of each leaf clock. So, either you hard-code the parents as Jens did in a first proposal, or you define the full list of parents in the DT as in the last proposal, or you use a container per parent in the DT as I proposed. There could be an other solution using the output clock name to define the parent clock: bus_gates { clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; clock-indices = <5>, <6>, <8>, ... clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0" }; with the documentation: "the clocks MUST be defined in order: ahb1, ahb2, apb1, apb2." and the code if (strncmp(clock_name, "ahb1", 4) == 0) clk_parent = of_clk_get_parent_name(node, 0); else if (..) but it seems a bit hacky. -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/ ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-10-24 8:47 ` Jean-Francois Moine @ 2015-10-26 21:06 ` Maxime Ripard 2015-10-27 8:12 ` [linux-sunxi] " Hans de Goede 0 siblings, 1 reply; 26+ messages in thread From: Maxime Ripard @ 2015-10-26 21:06 UTC (permalink / raw) To: Jean-Francois Moine Cc: Jens Kuske, devicetree, Vishnu Patekar, Emilio López, Michael Turquette, linux-sunxi, linux-kernel, Hans de Goede, Chen-Yu Tsai, Rob Herring, Philipp Zabel, Linus Walleij, linux-arm-kernel [-- Attachment #1: Type: text/plain, Size: 1651 bytes --] On Sat, Oct 24, 2015 at 10:47:49AM +0200, Jean-Francois Moine wrote: > On Sat, 24 Oct 2015 09:13:28 +0200 > Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > > > Or simply > > > > bus_gates { > > clocks = <&ahb1>, <&ahb2>; > > clock-indices = <5>, <6>, <8>, ... > > clock-output-names = "bus_ce", "bus_dma", "bus_mmc0" > > }; > > I don't understand: the apb1, apb2, ahb1 and ahb2 clocks may be > programmed independently to different frequencies I don't understand why you're talking about frequencies here. > and you have to know which of them is the parent of each leaf clock. Indeed, but that's also doable here. Just not in the DT. > So, either you hard-code the parents as Jens did in a first proposal, > or you define the full list of parents in the DT as in the last > proposal, or you use a container per parent in the DT as I proposed. > > There could be an other solution using the output clock name to define > the parent clock: > > bus_gates { > clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; > clock-indices = <5>, <6>, <8>, ... > clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0" > }; > > with the documentation: > > "the clocks MUST be defined in order: ahb1, ahb2, apb1, apb2." > > and the code > > if (strncmp(clock_name, "ahb1", 4) == 0) > clk_parent = of_clk_get_parent_name(node, 0); > else if (..) > > but it seems a bit hacky. It's exactly what I suggested, without the string comparison, but relying on the ID instead. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [linux-sunxi] Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-10-26 21:06 ` Maxime Ripard @ 2015-10-27 8:12 ` Hans de Goede 0 siblings, 0 replies; 26+ messages in thread From: Hans de Goede @ 2015-10-27 8:12 UTC (permalink / raw) To: Maxime Ripard, Jean-Francois Moine Cc: Jens Kuske, devicetree, Vishnu Patekar, Emilio López, Michael Turquette, linux-sunxi, linux-kernel, Chen-Yu Tsai, Rob Herring, Philipp Zabel, Linus Walleij, linux-arm-kernel Hi, On 26-10-15 22:06, Maxime Ripard wrote: > On Sat, Oct 24, 2015 at 10:47:49AM +0200, Jean-Francois Moine wrote: >> On Sat, 24 Oct 2015 09:13:28 +0200 >> Maxime Ripard <maxime.ripard@free-electrons.com> wrote: >> >>> Or simply >>> >>> bus_gates { >>> clocks = <&ahb1>, <&ahb2>; >>> clock-indices = <5>, <6>, <8>, ... >>> clock-output-names = "bus_ce", "bus_dma", "bus_mmc0" >>> }; >> >> I don't understand: the apb1, apb2, ahb1 and ahb2 clocks may be >> programmed independently to different frequencies > > I don't understand why you're talking about frequencies here. > >> and you have to know which of them is the parent of each leaf clock. > > Indeed, but that's also doable here. Just not in the DT. > >> So, either you hard-code the parents as Jens did in a first proposal, >> or you define the full list of parents in the DT as in the last >> proposal, or you use a container per parent in the DT as I proposed. >> >> There could be an other solution using the output clock name to define >> the parent clock: >> >> bus_gates { >> clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; >> clock-indices = <5>, <6>, <8>, ... >> clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0" >> }; >> >> with the documentation: >> >> "the clocks MUST be defined in order: ahb1, ahb2, apb1, apb2." >> >> and the code >> >> if (strncmp(clock_name, "ahb1", 4) == 0) >> clk_parent = of_clk_get_parent_name(node, 0); >> else if (..) >> >> but it seems a bit hacky. > > It's exactly what I suggested, without the string comparison, but > relying on the ID instead. I'm not following you here, what do you mean with "the ID" ? Regards, Hans ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [linux-sunxi] Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-10-23 18:14 ` Maxime Ripard 2015-10-23 19:20 ` Jean-Francois Moine @ 2015-10-24 8:39 ` Hans de Goede 2015-10-26 21:00 ` Maxime Ripard 1 sibling, 1 reply; 26+ messages in thread From: Hans de Goede @ 2015-10-24 8:39 UTC (permalink / raw) To: Maxime Ripard, Jens Kuske Cc: Chen-Yu Tsai, Michael Turquette, Linus Walleij, Rob Herring, Philipp Zabel, Emilio López, Vishnu Patekar, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi Hi, On 10/23/2015 08:14 PM, Maxime Ripard wrote: > On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: >> + bus_gates: clk@01c20060 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun8i-h3-bus-gates-clk"; >> + reg = <0x01c20060 0x14>; >> + clock-indices = <5>, <6>, <8>, >> + <9>, <10>, <13>, >> + <14>, <17>, <18>, >> + <19>, <20>, >> + <21>, <23>, >> + <24>, <25>, >> + <26>, <27>, >> + <28>, <29>, >> + <30>, <31>, <32>, >> + <35>, <36>, <37>, >> + <40>, <41>, <43>, >> + <44>, <52>, <53>, >> + <54>, <64>, >> + <65>, <69>, <72>, >> + <76>, <77>, <78>, >> + <96>, <97>, <98>, >> + <112>, <113>, >> + <114>, <115>, <116>, >> + <128>, <135>; >> + clocks = <&ahb1>, <&ahb1>, <&ahb1>, >> + <&ahb1>, <&ahb1>, <&ahb1>, >> + <&ahb1>, <&ahb2>, <&ahb1>, >> + <&ahb1>, <&ahb1>, >> + <&ahb1>, <&ahb1>, >> + <&ahb1>, <&ahb1>, >> + <&ahb1>, <&ahb1>, >> + <&ahb1>, <&ahb2>, >> + <&ahb2>, <&ahb2>, <&ahb1>, >> + <&ahb1>, <&ahb1>, <&ahb1>, >> + <&ahb1>, <&ahb1>, <&ahb1>, >> + <&ahb1>, <&ahb1>, <&ahb1>, >> + <&ahb1>, <&apb1>, >> + <&apb1>, <&apb1>, <&apb1>, >> + <&apb1>, <&apb1>, <&apb1>, >> + <&apb2>, <&apb2>, <&apb2>, >> + <&apb2>, <&apb2>, >> + <&apb2>, <&apb2>, <&apb2>, >> + <&ahb1>, <&ahb1>; > > This is not really what I had in mind... I came to the same solution independently, I took my inspiration from the rockchip clocks driver which is dealing with this problem in the same way, so there is precedent for doing things this way, and this does give us lot of flexibility. Given that I expect other new allwinnner SoCs to have the same problem I believe it is good to have that flexibility. > This IP has 2 parents, and only two parents. Nope it has 4: apb1, apb2, ahb1 and ahb2. > The mapping between the > IPs should be done in the driver itself, not in the DT where it is > very error prone and barely readable. It is just as error prone and barely readable in C-code, see Jens original patchset, he did an array of clock indices there (range 0-3 with an index into the parent clocks array), which is arguably even more unreadable since there is an extra level of indirection here. The problem with the unreadability simply comes from allwinner's decision to no longer have a gates register per bus but instead shove everything in a single bit-array in random order, there is nothing we can do to fix that. Also the argument "this belongs in the driver not in the DT" is a bit inconsistent with the moving of the mask of valid gates from the driver into the clock-indices in devicetree. The way things are done here actually are doing pretty much the same thing, putting info which could be derived from the compatible string into devicetree. Last as said already there is precedent for doing things this way in the rockchip driver, and given that 2 people have come up with this approach independently of of each other this clearly seems to be the most straight-foward / logical way to deal with this. > And note that I never have expected you to use clk-simple-gates > either. This is a complicated clock No it is not complicated, have you looked at the changes to the simple-clk-gates driver which Jean Francois Moine suggested? Those 5 extra lines (4 new lines) are all that is needed when going with the approach of listing a parent per gate. This is actually still a quite simple clock, we only need to find a way to specify a parent per gate, preferably via DT since this gives us greater flexibility which will be quite useful when adding support for other SoCs. Regards, Hans ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [linux-sunxi] Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-10-24 8:39 ` Hans de Goede @ 2015-10-26 21:00 ` Maxime Ripard 0 siblings, 0 replies; 26+ messages in thread From: Maxime Ripard @ 2015-10-26 21:00 UTC (permalink / raw) To: Hans de Goede Cc: Jens Kuske, Chen-Yu Tsai, Michael Turquette, Linus Walleij, Rob Herring, Philipp Zabel, Emilio López, Vishnu Patekar, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 5592 bytes --] On Sat, Oct 24, 2015 at 10:39:49AM +0200, Hans de Goede wrote: > Hi, > > On 10/23/2015 08:14 PM, Maxime Ripard wrote: > >On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > >>+ bus_gates: clk@01c20060 { > >>+ #clock-cells = <1>; > >>+ compatible = "allwinner,sun8i-h3-bus-gates-clk"; > >>+ reg = <0x01c20060 0x14>; > >>+ clock-indices = <5>, <6>, <8>, > >>+ <9>, <10>, <13>, > >>+ <14>, <17>, <18>, > >>+ <19>, <20>, > >>+ <21>, <23>, > >>+ <24>, <25>, > >>+ <26>, <27>, > >>+ <28>, <29>, > >>+ <30>, <31>, <32>, > >>+ <35>, <36>, <37>, > >>+ <40>, <41>, <43>, > >>+ <44>, <52>, <53>, > >>+ <54>, <64>, > >>+ <65>, <69>, <72>, > >>+ <76>, <77>, <78>, > >>+ <96>, <97>, <98>, > >>+ <112>, <113>, > >>+ <114>, <115>, <116>, > >>+ <128>, <135>; > >>+ clocks = <&ahb1>, <&ahb1>, <&ahb1>, > >>+ <&ahb1>, <&ahb1>, <&ahb1>, > >>+ <&ahb1>, <&ahb2>, <&ahb1>, > >>+ <&ahb1>, <&ahb1>, > >>+ <&ahb1>, <&ahb1>, > >>+ <&ahb1>, <&ahb1>, > >>+ <&ahb1>, <&ahb1>, > >>+ <&ahb1>, <&ahb2>, > >>+ <&ahb2>, <&ahb2>, <&ahb1>, > >>+ <&ahb1>, <&ahb1>, <&ahb1>, > >>+ <&ahb1>, <&ahb1>, <&ahb1>, > >>+ <&ahb1>, <&ahb1>, <&ahb1>, > >>+ <&ahb1>, <&apb1>, > >>+ <&apb1>, <&apb1>, <&apb1>, > >>+ <&apb1>, <&apb1>, <&apb1>, > >>+ <&apb2>, <&apb2>, <&apb2>, > >>+ <&apb2>, <&apb2>, > >>+ <&apb2>, <&apb2>, <&apb2>, > >>+ <&ahb1>, <&ahb1>; > > > >This is not really what I had in mind... > > I came to the same solution independently, I took my inspiration from > the rockchip clocks driver which is dealing with this problem in the > same way, so there is precedent for doing things this way, and this > does give us lot of flexibility. Given that I expect other new allwinnner > SoCs to have the same problem I believe it is good to have that > flexibility. The rockchip clocks driver are very different from our own regarding the DT bindings. Being consistent within our own platform seems to bring much more value than getting bits and pieces here and there when it's convenient. Plus, you actually forgot in your argument to mention that this binding was documented as deprecated, and not used anywhere since 3.17... So apparently, someone tried that, and finally changed its mind. Again, this is clearly a workaround, with no way to easily identify if a given clock has the right parent afterwards. We can't review it properly, and it's going to be a pain to fix after the facts. Having some association masks in the driver itself, using the BIT macro, will be much easier to maintain in the long run. > >This IP has 2 parents, and only two parents. > > Nope it has 4: apb1, apb2, ahb1 and ahb2. The point still remains though. > >The mapping between the IPs should be done in the driver itself, > >not in the DT where it is very error prone and barely readable. > > It is just as error prone and barely readable in C-code, see Jens original > patchset, he did an array of clock indices there (range 0-3 with an index > into the parent clocks array), which is arguably even more unreadable since > there is an extra level of indirection here. I agree, and it's why I suggested another approach at the time. > The problem with the unreadability simply comes from allwinner's decision > to no longer have a gates register per bus but instead shove everything > in a single bit-array in random order, there is nothing we can do to fix > that. Indeed. Except one solution is easier to maintain than the other. > Also the argument "this belongs in the driver not in the DT" is a > bit inconsistent with the moving of the mask of valid gates from the > driver into the clock-indices in devicetree. Except I never used that argument. > The way things are done here actually are doing pretty much the same > thing, putting info which could be derived from the compatible > string into devicetree. > > Last as said already there is precedent for doing things this way > in the rockchip driver, and given that 2 people have come up > with this approach independently of of each other this clearly > seems to be the most straight-foward / logical way to deal with > this. > > >And note that I never have expected you to use clk-simple-gates > >either. This is a complicated clock > > No it is not complicated, have you looked at the changes to the > simple-clk-gates driver which Jean Francois Moine suggested? > > Those 5 extra lines (4 new lines) are all that is needed when > going with the approach of listing a parent per gate. This is > actually still a quite simple clock, we only need to find a way > to specify a parent per gate, preferably via DT since this gives > us greater flexibility which will be quite useful when adding > support for other SoCs. The problem boils down to this: so far, we've used one DT node per clock controller (and we won't change that, sorry). The clocks property is defined as "List of phandle and clock specifier pairs, one pair for each clock input to the device.". There's only 4 clock inputs. Really. What this clock controller controls is whether one of these four input will be output, and that's pretty much it. The routing between the input and output pins is internal to the controller, just like it should be internal to the driver. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 6/6] ARM: dts: sun8i: Add Orange Pi Plus support 2015-10-21 16:20 [PATCH 4/6] reset: sunxi: Add compatible for Allwinner H3 bus resets Jens Kuske 2015-10-21 16:20 ` [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Jens Kuske @ 2015-10-21 16:20 ` Jens Kuske 2015-10-22 7:58 ` [PATCH 4/6] reset: sunxi: Add compatible for Allwinner H3 bus resets Maxime Ripard 2 siblings, 0 replies; 26+ messages in thread From: Jens Kuske @ 2015-10-21 16:20 UTC (permalink / raw) To: Maxime Ripard, Chen-Yu Tsai, Michael Turquette, Linus Walleij, Rob Herring, Philipp Zabel, Emilio López Cc: Vishnu Patekar, Hans de Goede, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Jens Kuske The Orange Pi Plus is a SBC based on the Allwinner H3 SoC with 8GB eMMC, multiple USB ports through a USB hub chip, SATA through a USB-SATA bridge, one uSD slot, a 10/100/1000M ethernet port, WiFi, HDMI, headphone jack, IR receiver, a microphone, a CSI connector and a 40-pin GPIO header. Signed-off-by: Jens Kuske <jenskuske@gmail.com> --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 77 ++++++++++++++++++++++++++++ 2 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 35a3cf4..bedf51b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -643,7 +643,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a33-ga10h-v1.1.dtb \ sun8i-a33-ippo-q8h-v1.2.dtb \ sun8i-a33-q8-tablet.dtb \ - sun8i-a33-sinlinx-sina33.dtb + sun8i-a33-sinlinx-sina33.dtb \ + sun8i-h3-orangepi-plus.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts new file mode 100644 index 0000000..e67df59 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Xunlong Orange Pi Plus"; + compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; -- 2.6.1 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 4/6] reset: sunxi: Add compatible for Allwinner H3 bus resets 2015-10-21 16:20 [PATCH 4/6] reset: sunxi: Add compatible for Allwinner H3 bus resets Jens Kuske 2015-10-21 16:20 ` [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Jens Kuske 2015-10-21 16:20 ` [PATCH 6/6] ARM: dts: sun8i: Add Orange Pi Plus support Jens Kuske @ 2015-10-22 7:58 ` Maxime Ripard 2015-10-27 16:54 ` Jens Kuske 2 siblings, 1 reply; 26+ messages in thread From: Maxime Ripard @ 2015-10-22 7:58 UTC (permalink / raw) To: Jens Kuske Cc: Chen-Yu Tsai, Michael Turquette, Linus Walleij, Rob Herring, Philipp Zabel, Emilio López, Vishnu Patekar, Hans de Goede, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 493 bytes --] On Wed, Oct 21, 2015 at 06:20:26PM +0200, Jens Kuske wrote: > Adding a new compatible allows us to define SoC specific behaviour > if necessary, for example forcing a particular device out of reset > even if no driver is actually using it. > > Signed-off-by: Jens Kuske <jenskuske@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 4/6] reset: sunxi: Add compatible for Allwinner H3 bus resets 2015-10-22 7:58 ` [PATCH 4/6] reset: sunxi: Add compatible for Allwinner H3 bus resets Maxime Ripard @ 2015-10-27 16:54 ` Jens Kuske 0 siblings, 0 replies; 26+ messages in thread From: Jens Kuske @ 2015-10-27 16:54 UTC (permalink / raw) To: Philipp Zabel Cc: Maxime Ripard, Chen-Yu Tsai, Michael Turquette, Linus Walleij, Rob Herring, Emilio López, Vishnu Patekar, Hans de Goede, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi On 22/10/15 09:58, Maxime Ripard wrote: > On Wed, Oct 21, 2015 at 06:20:26PM +0200, Jens Kuske wrote: >> Adding a new compatible allows us to define SoC specific behaviour >> if necessary, for example forcing a particular device out of reset >> even if no driver is actually using it. >> >> Signed-off-by: Jens Kuske <jenskuske@gmail.com> > > Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> > > Thanks! > Maxime > Hi, I've send a new version of this patch, please don't apply this version. Jens ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support @ 2015-05-06 9:31 Jens Kuske 2015-05-06 9:31 ` [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Jens Kuske 0 siblings, 1 reply; 26+ messages in thread From: Jens Kuske @ 2015-05-06 9:31 UTC (permalink / raw) To: Maxime Ripard, Emilio López, Mike Turquette, Linus Walleij, Vinod Koul, Rob Herring Cc: Jens Kuske, Chen-Yu Tsai, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi Hi everyone, This patch series introduces basic kernel support for Allwinner's H3 SoC, mainly basic clocks and pinctrl. It also adds interrupts, timers, watchdog, RTC, dmaengine, MMC and UARTs, which are mostly compatible to those in earlier SoCs like A23 and A31, and can simply be reused. These patches are based on Maxime's sunxi/for-next branch from git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux.git Patch 1 adds machine support for the H3. Patch 2 adds support for the basic clocks. The AHB1/AHB2 split could need some discussion. Patch 3 adds the pin sets for the H3 main PIO. Patch 4 adds the H3 specific parameters to the sun6i dmaengine driver. Patch 5 adds the DTSI for the H3. Patch 6 adds a DT for the Orange Pi Plus SBC, which these patches were developed and tested with. Regards, Jens Jens Kuske (6): ARM: sunxi: Introduce Allwinner H3 support clk: sunxi: Add H3 clocks support pinctrl: sunxi: Add H3 PIO controller support dmaengine: sun6i: Add support for Allwinner H3 (sun8i) variant ARM: dts: sunxi: Add Allwinner H3 DTSI ARM: dts: sun8i: Add Orange Pi Plus support Documentation/devicetree/bindings/arm/sunxi.txt | 1 + Documentation/devicetree/bindings/clock/sunxi.txt | 7 + .../devicetree/bindings/dma/sun6i-dma.txt | 5 +- .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 82 ++++ arch/arm/boot/dts/sun8i-h3.dtsi | 468 ++++++++++++++++++ arch/arm/mach-sunxi/Kconfig | 2 +- arch/arm/mach-sunxi/sunxi.c | 3 +- drivers/clk/sunxi/clk-sunxi.c | 46 +- drivers/dma/sun6i-dma.c | 12 + drivers/pinctrl/sunxi/Kconfig | 4 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c | 521 +++++++++++++++++++++ 14 files changed, 1151 insertions(+), 5 deletions(-) create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c -- 2.3.7 ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-05-06 9:31 [PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support Jens Kuske @ 2015-05-06 9:31 ` Jens Kuske 2015-05-06 12:19 ` Maxime Ripard 0 siblings, 1 reply; 26+ messages in thread From: Jens Kuske @ 2015-05-06 9:31 UTC (permalink / raw) To: Maxime Ripard, Emilio López, Mike Turquette, Linus Walleij, Vinod Koul, Rob Herring Cc: Jens Kuske, Chen-Yu Tsai, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi The Allwinner H3 is a home entertainment system oriented SoC with four Cortex-A7 cores and a Mali-400MP2 GPU. Signed-off-by: Jens Kuske <jenskuske@gmail.com> --- arch/arm/boot/dts/sun8i-h3.dtsi | 468 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 468 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi new file mode 100644 index 0000000..53aab95 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -0,0 +1,468 @@ +/* + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "skeleton.dtsi" + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + }; + }; + + memory { + reg = <0x40000000 0x80000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + pll1: clk@01c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll1"; + }; + + pll6: clk@01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun8i-h3-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6", "pll6x2", "pll6d2"; + }; + + pll8: clk@01c20044 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-h3-pll8-clk"; + reg = <0x01c20044 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll8"; + }; + + cpu: cpu_clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-cpu-clk"; + reg = <0x01c20050 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; + clock-output-names = "cpu"; + }; + + axi: axi_clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-axi-clk"; + reg = <0x01c20050 0x4>; + clocks = <&cpu>; + clock-output-names = "axi"; + }; + + ahb1: ahb1_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-ahb1-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; + clock-output-names = "ahb1"; + }; + + ahb2: ahb2_clk@01c2005c { + #clock-cells = <0>; + compatible = "allwinner,sun8i-h3-ahb2-clk"; + reg = <0x01c2005c 0x4>; + clocks = <&ahb1>, <&pll6 2>; + clock-output-names = "ahb2"; + }; + + apb1: apb1_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb1>; + clock-output-names = "apb1"; + }; + + apb2: apb2_clk@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb1-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; + clock-output-names = "apb2"; + }; + + ahb1_gates: ahb1_gates_clk@01c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun8i-h3-ahb1-gates-clk"; + reg = <0x01c20060 0x14>; + clocks = <&ahb1>; + clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0", + "ahb1_mmc1", "ahb1_mmc2", "ahb1_nand", + "ahb1_sdram", "ahb1_ts", "ahb1_hstimer", + "ahb1_spi0", "ahb1_spi1", "ahb1_otg", + "ahb1_otg_ehci0", "ahb1_ehic1", + "ahb1_ehic2", "ahb1_ehic3", + "ahb1_otg_ohci0", "ahb1_ve", + "ahb1_lcd0", "ahb1_lcd1", "ahb1_deint", + "ahb1_csi", "ahb1_tve", "ahb1_hdmi", + "ahb1_de", "ahb1_gpu", "ahb1_msgbox", + "ahb1_spinlock", "ahb1_ephy", "ahb1_dbg"; + }; + + ahb2_gates: ahb2_gates_clk@01c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun8i-h3-ahb2-gates-clk"; + reg = <0x01c20060 0x4>; + clocks = <&ahb2>; + clock-output-names = "ahb2_gmac", "ahb2_ohic1", + "ahb2_ohic2", "ahb2_ohic3"; + }; + + apb1_gates: clk@01c20068 { + #clock-cells = <1>; + compatible = "allwinner,sun8i-h3-apb1-gates-clk"; + reg = <0x01c20068 0x4>; + clocks = <&apb1>; + clock-output-names = "apb1_codec", "apb1_spdif", + "apb1_pio", "apb1_ths", "apb1_i2s0", + "apb1_i2s1", "apb1_i2s2"; + }; + + apb2_gates: clk@01c2006c { + #clock-cells = <1>; + compatible = "allwinner,sun8i-h3-apb2-gates-clk"; + reg = <0x01c2006c 0x4>; + clocks = <&apb2>; + clock-output-names = "apb2_i2c0", "apb2_i2c1", + "apb2_i2c2", "apb2_uart0", + "apb2_uart1", "apb2_uart2", + "apb2_uart3", "apb2_sim"; + }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 0>, <&pll8>; + clock-output-names = "mmc0", + "mmc0_output", + "mmc0_sample"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 0>, <&pll8>; + clock-output-names = "mmc1", + "mmc1_output", + "mmc1_sample"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 0>, <&pll8>; + clock-output-names = "mmc2", + "mmc2_output", + "mmc2_sample"; + }; + }; + + soc@01c00000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dma: dma-controller@01c02000 { + compatible = "allwinner,sun8i-h3-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ahb1_gates 6>; + resets = <&ahb12_rst 6>; + #dma-cells = <1>; + }; + + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb1_gates 8>, + <&mmc0_clk 0>, + <&mmc0_clk 1>, + <&mmc0_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ahb12_rst 8>; + reset-names = "ahb"; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb1_gates 9>, + <&mmc1_clk 0>, + <&mmc1_clk 1>, + <&mmc1_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ahb12_rst 9>; + reset-names = "ahb"; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb1_gates 10>, + <&mmc2_clk 0>, + <&mmc2_clk 1>, + <&mmc2_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ahb12_rst 10>; + reset-names = "ahb"; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pio: pinctrl@01c20800 { + compatible = "allwinner,sun8i-h3-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&apb1_gates 5>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #size-cells = <0>; + #gpio-cells = <3>; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PA4", "PA5"; + allwinner,function = "uart0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc0_cd_pin: mmc0_cd_pin@0 { + allwinner,pins = "PF6"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + mmc1_pins_a: mmc1@0 { + allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5"; + allwinner,function = "mmc1"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + }; + + ahb12_rst: reset@01c202c0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x01c202c0 0xc>; + }; + + apb1_rst: reset@01c202d0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x01c202d0 0x4>; + }; + + apb2_rst: reset@01c202d8 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x01c202d8 0x4>; + }; + + timer@01c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0xa0>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>; + }; + + wdt0: watchdog@01c20ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + }; + + uart0: serial@01c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 16>; + resets = <&apb2_rst 16>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart1: serial@01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 17>; + resets = <&apb2_rst 17>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@01c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 18>; + resets = <&apb2_rst 18>; + dmas = <&dma 8>, <&dma 8>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart3: serial@01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 19>; + resets = <&apb2_rst 19>; + dmas = <&dma 9>, <&dma 9>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x1000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + rtc: rtc@01f00000 { + compatible = "allwinner,sun6i-a31-rtc"; + reg = <0x01f00000 0x54>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +}; -- 2.3.7 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-05-06 9:31 ` [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Jens Kuske @ 2015-05-06 12:19 ` Maxime Ripard 2015-05-06 20:47 ` Jens Kuske 0 siblings, 1 reply; 26+ messages in thread From: Maxime Ripard @ 2015-05-06 12:19 UTC (permalink / raw) To: Jens Kuske Cc: Emilio López, Mike Turquette, Linus Walleij, Vinod Koul, Rob Herring, Chen-Yu Tsai, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 15847 bytes --] On Wed, May 06, 2015 at 11:31:32AM +0200, Jens Kuske wrote: > The Allwinner H3 is a home entertainment system oriented SoC with > four Cortex-A7 cores and a Mali-400MP2 GPU. > > Signed-off-by: Jens Kuske <jenskuske@gmail.com> > --- > arch/arm/boot/dts/sun8i-h3.dtsi | 468 ++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 468 insertions(+) > create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi > new file mode 100644 > index 0000000..53aab95 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > @@ -0,0 +1,468 @@ > +/* > + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public > + * License along with this file; if not, write to the Free > + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, > + * MA 02110-1301 USA Could you remove that last paragraph? It generates a checkpatch warning. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#include "skeleton.dtsi" > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/pinctrl/sun4i-a10.h> > + > +/ { > + interrupt-parent = <&gic>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0>; > + }; > + > + cpu@1 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <1>; > + }; > + > + cpu@2 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <2>; > + }; > + > + cpu@3 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <3>; > + }; > + }; > + > + memory { > + reg = <0x40000000 0x80000000>; > + }; > + > + clocks { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + osc24M: osc24M_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + clock-output-names = "osc24M"; > + }; > + > + osc32k: osc32k_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <32768>; > + clock-output-names = "osc32k"; > + }; > + > + pll1: clk@01c20000 { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-a23-pll1-clk"; > + reg = <0x01c20000 0x4>; > + clocks = <&osc24M>; > + clock-output-names = "pll1"; > + }; > + > + pll6: clk@01c20028 { > + #clock-cells = <1>; > + compatible = "allwinner,sun8i-h3-pll6-clk"; > + reg = <0x01c20028 0x4>; > + clocks = <&osc24M>; > + clock-output-names = "pll6", "pll6x2", "pll6d2"; > + }; > + > + pll8: clk@01c20044 { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-h3-pll8-clk"; > + reg = <0x01c20044 0x4>; > + clocks = <&osc24M>; > + clock-output-names = "pll8"; > + }; > + > + cpu: cpu_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-cpu-clk"; > + reg = <0x01c20050 0x4>; > + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; > + clock-output-names = "cpu"; > + }; > + > + axi: axi_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-axi-clk"; > + reg = <0x01c20050 0x4>; > + clocks = <&cpu>; > + clock-output-names = "axi"; > + }; > + > + ahb1: ahb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun6i-a31-ahb1-clk"; > + reg = <0x01c20054 0x4>; > + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; > + clock-output-names = "ahb1"; > + }; > + > + ahb2: ahb2_clk@01c2005c { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-h3-ahb2-clk"; > + reg = <0x01c2005c 0x4>; > + clocks = <&ahb1>, <&pll6 2>; > + clock-output-names = "ahb2"; > + }; > + > + apb1: apb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb0-clk"; > + reg = <0x01c20054 0x4>; > + clocks = <&ahb1>; > + clock-output-names = "apb1"; > + }; > + > + apb2: apb2_clk@01c20058 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb1-clk"; > + reg = <0x01c20058 0x4>; > + clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; > + clock-output-names = "apb2"; > + }; > + > + ahb1_gates: ahb1_gates_clk@01c20060 { > + #clock-cells = <1>; > + compatible = "allwinner,sun8i-h3-ahb1-gates-clk"; > + reg = <0x01c20060 0x14>; > + clocks = <&ahb1>; > + clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0", > + "ahb1_mmc1", "ahb1_mmc2", "ahb1_nand", > + "ahb1_sdram", "ahb1_ts", "ahb1_hstimer", > + "ahb1_spi0", "ahb1_spi1", "ahb1_otg", > + "ahb1_otg_ehci0", "ahb1_ehic1", > + "ahb1_ehic2", "ahb1_ehic3", > + "ahb1_otg_ohci0", "ahb1_ve", > + "ahb1_lcd0", "ahb1_lcd1", "ahb1_deint", > + "ahb1_csi", "ahb1_tve", "ahb1_hdmi", > + "ahb1_de", "ahb1_gpu", "ahb1_msgbox", > + "ahb1_spinlock", "ahb1_ephy", "ahb1_dbg"; > + }; > + > + ahb2_gates: ahb2_gates_clk@01c20060 { > + #clock-cells = <1>; > + compatible = "allwinner,sun8i-h3-ahb2-gates-clk"; > + reg = <0x01c20060 0x4>; > + clocks = <&ahb2>; > + clock-output-names = "ahb2_gmac", "ahb2_ohic1", > + "ahb2_ohic2", "ahb2_ohic3"; > + }; > + > + apb1_gates: clk@01c20068 { > + #clock-cells = <1>; > + compatible = "allwinner,sun8i-h3-apb1-gates-clk"; > + reg = <0x01c20068 0x4>; > + clocks = <&apb1>; > + clock-output-names = "apb1_codec", "apb1_spdif", > + "apb1_pio", "apb1_ths", "apb1_i2s0", > + "apb1_i2s1", "apb1_i2s2"; > + }; > + > + apb2_gates: clk@01c2006c { > + #clock-cells = <1>; > + compatible = "allwinner,sun8i-h3-apb2-gates-clk"; > + reg = <0x01c2006c 0x4>; > + clocks = <&apb2>; > + clock-output-names = "apb2_i2c0", "apb2_i2c1", > + "apb2_i2c2", "apb2_uart0", > + "apb2_uart1", "apb2_uart2", > + "apb2_uart3", "apb2_sim"; I'd prefer if the clocks on a new line were right-aligned (like you did for the mmc clocks just below). > + }; > + > + mmc0_clk: clk@01c20088 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c20088 0x4>; > + clocks = <&osc24M>, <&pll6 0>, <&pll8>; > + clock-output-names = "mmc0", > + "mmc0_output", > + "mmc0_sample"; > + }; > + > + mmc1_clk: clk@01c2008c { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c2008c 0x4>; > + clocks = <&osc24M>, <&pll6 0>, <&pll8>; > + clock-output-names = "mmc1", > + "mmc1_output", > + "mmc1_sample"; > + }; > + > + mmc2_clk: clk@01c20090 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c20090 0x4>; > + clocks = <&osc24M>, <&pll6 0>, <&pll8>; > + clock-output-names = "mmc2", > + "mmc2_output", > + "mmc2_sample"; > + }; > + }; > + > + soc@01c00000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + dma: dma-controller@01c02000 { > + compatible = "allwinner,sun8i-h3-dma"; > + reg = <0x01c02000 0x1000>; > + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ahb1_gates 6>; > + resets = <&ahb12_rst 6>; > + #dma-cells = <1>; > + }; > + > + mmc0: mmc@01c0f000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c0f000 0x1000>; > + clocks = <&ahb1_gates 8>, > + <&mmc0_clk 0>, > + <&mmc0_clk 1>, > + <&mmc0_clk 2>; > + clock-names = "ahb", > + "mmc", > + "output", > + "sample"; > + resets = <&ahb12_rst 8>; > + reset-names = "ahb"; > + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + mmc1: mmc@01c10000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c10000 0x1000>; > + clocks = <&ahb1_gates 9>, > + <&mmc1_clk 0>, > + <&mmc1_clk 1>, > + <&mmc1_clk 2>; > + clock-names = "ahb", > + "mmc", > + "output", > + "sample"; > + resets = <&ahb12_rst 9>; > + reset-names = "ahb"; > + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + mmc2: mmc@01c11000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c11000 0x1000>; > + clocks = <&ahb1_gates 10>, > + <&mmc2_clk 0>, > + <&mmc2_clk 1>, > + <&mmc2_clk 2>; > + clock-names = "ahb", > + "mmc", > + "output", > + "sample"; > + resets = <&ahb12_rst 10>; > + reset-names = "ahb"; > + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + pio: pinctrl@01c20800 { > + compatible = "allwinner,sun8i-h3-pinctrl"; > + reg = <0x01c20800 0x400>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&apb1_gates 5>; > + gpio-controller; > + interrupt-controller; > + #interrupt-cells = <2>; > + #size-cells = <0>; > + #gpio-cells = <3>; > + > + uart0_pins_a: uart0@0 { > + allwinner,pins = "PA4", "PA5"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + mmc0_pins_a: mmc0@0 { > + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; Could you have spaces between the commas, and wrap the line at 80 chars? > + allwinner,function = "mmc0"; > + allwinner,drive = <SUN4I_PINCTRL_30_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + mmc0_cd_pin: mmc0_cd_pin@0 { > + allwinner,pins = "PF6"; > + allwinner,function = "gpio_in"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; > + }; > + > + mmc1_pins_a: mmc1@0 { > + allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5"; > + allwinner,function = "mmc1"; > + allwinner,drive = <SUN4I_PINCTRL_30_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + }; > + > + ahb12_rst: reset@01c202c0 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-clock-reset"; > + reg = <0x01c202c0 0xc>; > + }; This reset controller also resets the timers, it should be initialised much earlier. What about having an allwinner,sun8i-h3-bus-reset, and adding it to the list of compatibles to initialise earlier in drivers/reset/reset-sunxi.c? Of course, it would cover the other reset controllers that you have below. > + apb1_rst: reset@01c202d0 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-clock-reset"; > + reg = <0x01c202d0 0x4>; > + }; > + > + apb2_rst: reset@01c202d8 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-clock-reset"; > + reg = <0x01c202d8 0x4>; > + }; > + > + timer@01c20c00 { > + compatible = "allwinner,sun4i-a10-timer"; > + reg = <0x01c20c00 0xa0>; > + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc24M>; > + }; > + > + wdt0: watchdog@01c20ca0 { > + compatible = "allwinner,sun6i-a31-wdt"; > + reg = <0x01c20ca0 0x20>; > + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + uart0: serial@01c28000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28000 0x400>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&apb2_gates 16>; > + resets = <&apb2_rst 16>; > + dmas = <&dma 6>, <&dma 6>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + uart1: serial@01c28400 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28400 0x400>; > + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&apb2_gates 17>; > + resets = <&apb2_rst 17>; > + dmas = <&dma 7>, <&dma 7>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + uart2: serial@01c28800 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28800 0x400>; > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&apb2_gates 18>; > + resets = <&apb2_rst 18>; > + dmas = <&dma 8>, <&dma 8>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + uart3: serial@01c28c00 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28c00 0x400>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&apb2_gates 19>; > + resets = <&apb2_rst 19>; > + dmas = <&dma 9>, <&dma 9>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + gic: interrupt-controller@01c81000 { > + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; > + reg = <0x01c81000 0x1000>, > + <0x01c82000 0x1000>, > + <0x01c84000 0x2000>, > + <0x01c86000 0x2000>; > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + }; > + > + rtc: rtc@01f00000 { > + compatible = "allwinner,sun6i-a31-rtc"; > + reg = <0x01f00000 0x54>; > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > +}; > -- > 2.3.7 > Have you tested the architected timers? Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-05-06 12:19 ` Maxime Ripard @ 2015-05-06 20:47 ` Jens Kuske 2015-05-09 11:44 ` Maxime Ripard 0 siblings, 1 reply; 26+ messages in thread From: Jens Kuske @ 2015-05-06 20:47 UTC (permalink / raw) To: Maxime Ripard Cc: Emilio López, Mike Turquette, Linus Walleij, Vinod Koul, Rob Herring, Chen-Yu Tsai, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi Hi, On 06/05/15 14:19, Maxime Ripard wrote: > On Wed, May 06, 2015 at 11:31:32AM +0200, Jens Kuske wrote: >> The Allwinner H3 is a home entertainment system oriented SoC with >> four Cortex-A7 cores and a Mali-400MP2 GPU. >> >> Signed-off-by: Jens Kuske <jenskuske@gmail.com> >> --- >> arch/arm/boot/dts/sun8i-h3.dtsi | 468 ++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 468 insertions(+) >> create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi >> >> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi >> new file mode 100644 >> index 0000000..53aab95 >> --- /dev/null >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi >> @@ -0,0 +1,468 @@ >> +/* >> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> >> + * >> + * This file is dual-licensed: you can use it either under the terms >> + * of the GPL or the X11 license, at your option. Note that this dual >> + * licensing only applies to this file, and not this project as a >> + * whole. >> + * >> + * a) This file is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License as >> + * published by the Free Software Foundation; either version 2 of the >> + * License, or (at your option) any later version. >> + * >> + * This file is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * You should have received a copy of the GNU General Public >> + * License along with this file; if not, write to the Free >> + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, >> + * MA 02110-1301 USA > > Could you remove that last paragraph? > It generates a checkpatch warning. Sure, will be removed. Just copied it from some other sunxi dtsi. > >> + * >> + * Or, alternatively, >> + * >> + * b) Permission is hereby granted, free of charge, to any person >> + * obtaining a copy of this software and associated documentation >> + * files (the "Software"), to deal in the Software without >> + * restriction, including without limitation the rights to use, >> + * copy, modify, merge, publish, distribute, sublicense, and/or >> + * sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following >> + * conditions: >> + * >> + * The above copyright notice and this permission notice shall be >> + * included in all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> + * OTHER DEALINGS IN THE SOFTWARE. >> + */ >> + >> +#include "skeleton.dtsi" >> + >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/pinctrl/sun4i-a10.h> >> + >> +/ { >> + interrupt-parent = <&gic>; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu@0 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <0>; >> + }; >> + >> + cpu@1 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <1>; >> + }; >> + >> + cpu@2 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <2>; >> + }; >> + >> + cpu@3 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <3>; >> + }; >> + }; >> + >> + memory { >> + reg = <0x40000000 0x80000000>; >> + }; >> + >> + clocks { >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + osc24M: osc24M_clk { >> + #clock-cells = <0>; >> + compatible = "fixed-clock"; >> + clock-frequency = <24000000>; >> + clock-output-names = "osc24M"; >> + }; >> + >> + osc32k: osc32k_clk { >> + #clock-cells = <0>; >> + compatible = "fixed-clock"; >> + clock-frequency = <32768>; >> + clock-output-names = "osc32k"; >> + }; >> + >> + pll1: clk@01c20000 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun8i-a23-pll1-clk"; >> + reg = <0x01c20000 0x4>; >> + clocks = <&osc24M>; >> + clock-output-names = "pll1"; >> + }; >> + >> + pll6: clk@01c20028 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun8i-h3-pll6-clk"; >> + reg = <0x01c20028 0x4>; >> + clocks = <&osc24M>; >> + clock-output-names = "pll6", "pll6x2", "pll6d2"; >> + }; >> + >> + pll8: clk@01c20044 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun8i-h3-pll8-clk"; >> + reg = <0x01c20044 0x4>; >> + clocks = <&osc24M>; >> + clock-output-names = "pll8"; >> + }; >> + >> + cpu: cpu_clk@01c20050 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-cpu-clk"; >> + reg = <0x01c20050 0x4>; >> + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; >> + clock-output-names = "cpu"; >> + }; >> + >> + axi: axi_clk@01c20050 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-axi-clk"; >> + reg = <0x01c20050 0x4>; >> + clocks = <&cpu>; >> + clock-output-names = "axi"; >> + }; >> + >> + ahb1: ahb1_clk@01c20054 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun6i-a31-ahb1-clk"; >> + reg = <0x01c20054 0x4>; >> + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; >> + clock-output-names = "ahb1"; >> + }; >> + >> + ahb2: ahb2_clk@01c2005c { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun8i-h3-ahb2-clk"; >> + reg = <0x01c2005c 0x4>; >> + clocks = <&ahb1>, <&pll6 2>; >> + clock-output-names = "ahb2"; >> + }; >> + >> + apb1: apb1_clk@01c20054 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-apb0-clk"; >> + reg = <0x01c20054 0x4>; >> + clocks = <&ahb1>; >> + clock-output-names = "apb1"; >> + }; >> + >> + apb2: apb2_clk@01c20058 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-apb1-clk"; >> + reg = <0x01c20058 0x4>; >> + clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; >> + clock-output-names = "apb2"; >> + }; >> + >> + ahb1_gates: ahb1_gates_clk@01c20060 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun8i-h3-ahb1-gates-clk"; >> + reg = <0x01c20060 0x14>; >> + clocks = <&ahb1>; >> + clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0", >> + "ahb1_mmc1", "ahb1_mmc2", "ahb1_nand", >> + "ahb1_sdram", "ahb1_ts", "ahb1_hstimer", >> + "ahb1_spi0", "ahb1_spi1", "ahb1_otg", >> + "ahb1_otg_ehci0", "ahb1_ehic1", >> + "ahb1_ehic2", "ahb1_ehic3", >> + "ahb1_otg_ohci0", "ahb1_ve", >> + "ahb1_lcd0", "ahb1_lcd1", "ahb1_deint", >> + "ahb1_csi", "ahb1_tve", "ahb1_hdmi", >> + "ahb1_de", "ahb1_gpu", "ahb1_msgbox", >> + "ahb1_spinlock", "ahb1_ephy", "ahb1_dbg"; >> + }; >> + >> + ahb2_gates: ahb2_gates_clk@01c20060 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun8i-h3-ahb2-gates-clk"; >> + reg = <0x01c20060 0x4>; >> + clocks = <&ahb2>; >> + clock-output-names = "ahb2_gmac", "ahb2_ohic1", >> + "ahb2_ohic2", "ahb2_ohic3"; >> + }; >> + >> + apb1_gates: clk@01c20068 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun8i-h3-apb1-gates-clk"; >> + reg = <0x01c20068 0x4>; >> + clocks = <&apb1>; >> + clock-output-names = "apb1_codec", "apb1_spdif", >> + "apb1_pio", "apb1_ths", "apb1_i2s0", >> + "apb1_i2s1", "apb1_i2s2"; >> + }; >> + >> + apb2_gates: clk@01c2006c { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun8i-h3-apb2-gates-clk"; >> + reg = <0x01c2006c 0x4>; >> + clocks = <&apb2>; >> + clock-output-names = "apb2_i2c0", "apb2_i2c1", >> + "apb2_i2c2", "apb2_uart0", >> + "apb2_uart1", "apb2_uart2", >> + "apb2_uart3", "apb2_sim"; > > I'd prefer if the clocks on a new line were right-aligned (like you > did for the mmc clocks just below). Copied again, but yes, I'll fix them. And apb2_sim gets renamed to apb2_scr as mentioned in the pinctrl thread. > >> + }; >> + >> + mmc0_clk: clk@01c20088 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun4i-a10-mmc-clk"; >> + reg = <0x01c20088 0x4>; >> + clocks = <&osc24M>, <&pll6 0>, <&pll8>; >> + clock-output-names = "mmc0", >> + "mmc0_output", >> + "mmc0_sample"; >> + }; >> + >> + mmc1_clk: clk@01c2008c { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun4i-a10-mmc-clk"; >> + reg = <0x01c2008c 0x4>; >> + clocks = <&osc24M>, <&pll6 0>, <&pll8>; >> + clock-output-names = "mmc1", >> + "mmc1_output", >> + "mmc1_sample"; >> + }; >> + >> + mmc2_clk: clk@01c20090 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun4i-a10-mmc-clk"; >> + reg = <0x01c20090 0x4>; >> + clocks = <&osc24M>, <&pll6 0>, <&pll8>; >> + clock-output-names = "mmc2", >> + "mmc2_output", >> + "mmc2_sample"; >> + }; >> + }; >> + >> + soc@01c00000 { >> + compatible = "simple-bus"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + dma: dma-controller@01c02000 { >> + compatible = "allwinner,sun8i-h3-dma"; >> + reg = <0x01c02000 0x1000>; >> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ahb1_gates 6>; >> + resets = <&ahb12_rst 6>; >> + #dma-cells = <1>; >> + }; >> + >> + mmc0: mmc@01c0f000 { >> + compatible = "allwinner,sun5i-a13-mmc"; >> + reg = <0x01c0f000 0x1000>; >> + clocks = <&ahb1_gates 8>, >> + <&mmc0_clk 0>, >> + <&mmc0_clk 1>, >> + <&mmc0_clk 2>; >> + clock-names = "ahb", >> + "mmc", >> + "output", >> + "sample"; >> + resets = <&ahb12_rst 8>; >> + reset-names = "ahb"; >> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; >> + status = "disabled"; >> + }; >> + >> + mmc1: mmc@01c10000 { >> + compatible = "allwinner,sun5i-a13-mmc"; >> + reg = <0x01c10000 0x1000>; >> + clocks = <&ahb1_gates 9>, >> + <&mmc1_clk 0>, >> + <&mmc1_clk 1>, >> + <&mmc1_clk 2>; >> + clock-names = "ahb", >> + "mmc", >> + "output", >> + "sample"; >> + resets = <&ahb12_rst 9>; >> + reset-names = "ahb"; >> + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; >> + status = "disabled"; >> + }; >> + >> + mmc2: mmc@01c11000 { >> + compatible = "allwinner,sun5i-a13-mmc"; >> + reg = <0x01c11000 0x1000>; >> + clocks = <&ahb1_gates 10>, >> + <&mmc2_clk 0>, >> + <&mmc2_clk 1>, >> + <&mmc2_clk 2>; >> + clock-names = "ahb", >> + "mmc", >> + "output", >> + "sample"; >> + resets = <&ahb12_rst 10>; >> + reset-names = "ahb"; >> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; >> + status = "disabled"; >> + }; >> + >> + pio: pinctrl@01c20800 { >> + compatible = "allwinner,sun8i-h3-pinctrl"; >> + reg = <0x01c20800 0x400>; >> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&apb1_gates 5>; >> + gpio-controller; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + #size-cells = <0>; >> + #gpio-cells = <3>; >> + >> + uart0_pins_a: uart0@0 { >> + allwinner,pins = "PA4", "PA5"; >> + allwinner,function = "uart0"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + >> + mmc0_pins_a: mmc0@0 { >> + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; > > Could you have spaces between the commas, and wrap the line at 80 > chars? ok > >> + allwinner,function = "mmc0"; >> + allwinner,drive = <SUN4I_PINCTRL_30_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + >> + mmc0_cd_pin: mmc0_cd_pin@0 { >> + allwinner,pins = "PF6"; >> + allwinner,function = "gpio_in"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; >> + }; >> + >> + mmc1_pins_a: mmc1@0 { >> + allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5"; >> + allwinner,function = "mmc1"; >> + allwinner,drive = <SUN4I_PINCTRL_30_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + }; >> + >> + ahb12_rst: reset@01c202c0 { >> + #reset-cells = <1>; >> + compatible = "allwinner,sun6i-a31-clock-reset"; >> + reg = <0x01c202c0 0xc>; >> + }; > > This reset controller also resets the timers, it should be initialised > much earlier. > > What about having an allwinner,sun8i-h3-bus-reset, and adding it to > the list of compatibles to initialise earlier in > drivers/reset/reset-sunxi.c? > > Of course, it would cover the other reset controllers that you have > below. > You mean using a single bus_rst instead of the three? Or, why not using allwinner,sun6i-a31-ahb1-reset for ahb12_rst and adding a .init_time = sun6i_timer_init to the sun8i machine. I'm a bit confused here now, because for A23, which is almost identical, it got removed after your comment: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265064.html > >> + apb1_rst: reset@01c202d0 { >> + #reset-cells = <1>; >> + compatible = "allwinner,sun6i-a31-clock-reset"; >> + reg = <0x01c202d0 0x4>; >> + }; >> + >> + apb2_rst: reset@01c202d8 { >> + #reset-cells = <1>; >> + compatible = "allwinner,sun6i-a31-clock-reset"; >> + reg = <0x01c202d8 0x4>; >> + }; >> + >> + timer@01c20c00 { >> + compatible = "allwinner,sun4i-a10-timer"; >> + reg = <0x01c20c00 0xa0>; >> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&osc24M>; >> + }; >> + >> + wdt0: watchdog@01c20ca0 { >> + compatible = "allwinner,sun6i-a31-wdt"; >> + reg = <0x01c20ca0 0x20>; >> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + >> + uart0: serial@01c28000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x01c28000 0x400>; >> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + clocks = <&apb2_gates 16>; >> + resets = <&apb2_rst 16>; >> + dmas = <&dma 6>, <&dma 6>; >> + dma-names = "rx", "tx"; >> + status = "disabled"; >> + }; >> + >> + uart1: serial@01c28400 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x01c28400 0x400>; >> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + clocks = <&apb2_gates 17>; >> + resets = <&apb2_rst 17>; >> + dmas = <&dma 7>, <&dma 7>; >> + dma-names = "rx", "tx"; >> + status = "disabled"; >> + }; >> + >> + uart2: serial@01c28800 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x01c28800 0x400>; >> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + clocks = <&apb2_gates 18>; >> + resets = <&apb2_rst 18>; >> + dmas = <&dma 8>, <&dma 8>; >> + dma-names = "rx", "tx"; >> + status = "disabled"; >> + }; >> + >> + uart3: serial@01c28c00 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x01c28c00 0x400>; >> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + clocks = <&apb2_gates 19>; >> + resets = <&apb2_rst 19>; >> + dmas = <&dma 9>, <&dma 9>; >> + dma-names = "rx", "tx"; >> + status = "disabled"; >> + }; >> + >> + gic: interrupt-controller@01c81000 { >> + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; >> + reg = <0x01c81000 0x1000>, >> + <0x01c82000 0x1000>, >> + <0x01c84000 0x2000>, >> + <0x01c86000 0x2000>; >> + interrupt-controller; >> + #interrupt-cells = <3>; >> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; >> + }; >> + >> + rtc: rtc@01f00000 { >> + compatible = "allwinner,sun6i-a31-rtc"; >> + reg = <0x01f00000 0x54>; >> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + }; >> +}; >> -- >> 2.3.7 >> > > Have you tested the architected timers? Not yet, but I'll look into it. Jens ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-05-06 20:47 ` Jens Kuske @ 2015-05-09 11:44 ` Maxime Ripard 2015-05-11 8:11 ` Chen-Yu Tsai 0 siblings, 1 reply; 26+ messages in thread From: Maxime Ripard @ 2015-05-09 11:44 UTC (permalink / raw) To: Jens Kuske Cc: Emilio López, Mike Turquette, Linus Walleij, Vinod Koul, Rob Herring, Chen-Yu Tsai, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 2134 bytes --] On Wed, May 06, 2015 at 10:47:33PM +0200, Jens Kuske wrote: > >> + * You should have received a copy of the GNU General Public > >> + * License along with this file; if not, write to the Free > >> + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, > >> + * MA 02110-1301 USA > > > > Could you remove that last paragraph? > > It generates a checkpatch warning. > > Sure, will be removed. Just copied it from some other sunxi dtsi. Yeah, I know, I'm even the one that introduced this in the first place :) I sent a patch earlier this week to remove it from the other DT. > >> + ahb12_rst: reset@01c202c0 { > >> + #reset-cells = <1>; > >> + compatible = "allwinner,sun6i-a31-clock-reset"; > >> + reg = <0x01c202c0 0xc>; > >> + }; > > > > This reset controller also resets the timers, it should be initialised > > much earlier. > > > > What about having an allwinner,sun8i-h3-bus-reset, and adding it to > > the list of compatibles to initialise earlier in > > drivers/reset/reset-sunxi.c? > > > > Of course, it would cover the other reset controllers that you have > > below. > > > > You mean using a single bus_rst instead of the three? Yes. > Or, why not using allwinner,sun6i-a31-ahb1-reset for ahb12_rst Strictly speaking, they do not control the same set of devices. I'd prefer to have a different compatible in case we need to setup a particular behaviour on a given SoC (for example, force out of reset a particular device, even if no driver is actually using it), without impacting the other. > and adding a .init_time = sun6i_timer_init to the sun8i machine. But we will need to do that yes. > I'm a bit confused here now, because for A23, which is almost > identical, it got removed after your comment: > http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265064.html Hmmmm, I think I somehow overlooked the fact that the timer was there, even though Chen-Yu said it. My bad :/ Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI 2015-05-09 11:44 ` Maxime Ripard @ 2015-05-11 8:11 ` Chen-Yu Tsai 0 siblings, 0 replies; 26+ messages in thread From: Chen-Yu Tsai @ 2015-05-11 8:11 UTC (permalink / raw) To: Maxime Ripard, Jens Kuske Cc: Emilio López, Mike Turquette, Linus Walleij, Vinod Koul, Rob Herring, Chen-Yu Tsai, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi On Sat, May 9, 2015 at 7:44 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > On Wed, May 06, 2015 at 10:47:33PM +0200, Jens Kuske wrote: >> >> + * You should have received a copy of the GNU General Public >> >> + * License along with this file; if not, write to the Free >> >> + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, >> >> + * MA 02110-1301 USA >> > >> > Could you remove that last paragraph? >> > It generates a checkpatch warning. >> >> Sure, will be removed. Just copied it from some other sunxi dtsi. > > Yeah, I know, I'm even the one that introduced this in the first place > :) > > I sent a patch earlier this week to remove it from the other DT. > >> >> + ahb12_rst: reset@01c202c0 { >> >> + #reset-cells = <1>; >> >> + compatible = "allwinner,sun6i-a31-clock-reset"; >> >> + reg = <0x01c202c0 0xc>; >> >> + }; >> > >> > This reset controller also resets the timers, it should be initialised >> > much earlier. >> > >> > What about having an allwinner,sun8i-h3-bus-reset, and adding it to >> > the list of compatibles to initialise earlier in >> > drivers/reset/reset-sunxi.c? >> > >> > Of course, it would cover the other reset controllers that you have >> > below. >> > >> >> You mean using a single bus_rst instead of the three? > > Yes. > >> Or, why not using allwinner,sun6i-a31-ahb1-reset for ahb12_rst > > Strictly speaking, they do not control the same set of devices. I'd > prefer to have a different compatible in case we need to setup a > particular behaviour on a given SoC (for example, force out of reset a > particular device, even if no driver is actually using it), without > impacting the other. > >> and adding a .init_time = sun6i_timer_init to the sun8i machine. > > But we will need to do that yes. > >> I'm a bit confused here now, because for A23, which is almost >> identical, it got removed after your comment: >> http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/265064.html > > Hmmmm, I think I somehow overlooked the fact that the timer was there, > even though Chen-Yu said it. My bad :/ On the A23, the high speed timer block only has 1 timer. The sun5i-hrtimer driver requires 2, and turns out we weren't using them anyway, so I just dropped sun5i-hrtimer support on A23. If the other sun8i SoCs have 2 or more timers, feel free to support them. ChenYu ^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2015-10-27 16:54 UTC | newest] Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2015-10-21 16:20 [PATCH 4/6] reset: sunxi: Add compatible for Allwinner H3 bus resets Jens Kuske 2015-10-21 16:20 ` [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Jens Kuske 2015-10-22 8:05 ` Maxime Ripard 2015-10-22 8:29 ` Jean-Francois Moine 2015-10-22 8:47 ` Maxime Ripard 2015-10-22 8:57 ` Jean-Francois Moine 2015-10-22 9:14 ` Maxime Ripard 2015-10-22 11:30 ` Jens Kuske 2015-10-23 18:09 ` Maxime Ripard 2015-10-22 17:30 ` Jean-Francois Moine 2015-10-23 18:14 ` Maxime Ripard 2015-10-23 19:20 ` Jean-Francois Moine 2015-10-24 7:13 ` Maxime Ripard 2015-10-24 8:47 ` Jean-Francois Moine 2015-10-26 21:06 ` Maxime Ripard 2015-10-27 8:12 ` [linux-sunxi] " Hans de Goede 2015-10-24 8:39 ` Hans de Goede 2015-10-26 21:00 ` Maxime Ripard 2015-10-21 16:20 ` [PATCH 6/6] ARM: dts: sun8i: Add Orange Pi Plus support Jens Kuske 2015-10-22 7:58 ` [PATCH 4/6] reset: sunxi: Add compatible for Allwinner H3 bus resets Maxime Ripard 2015-10-27 16:54 ` Jens Kuske -- strict thread matches above, loose matches on Subject: below -- 2015-05-06 9:31 [PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support Jens Kuske 2015-05-06 9:31 ` [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Jens Kuske 2015-05-06 12:19 ` Maxime Ripard 2015-05-06 20:47 ` Jens Kuske 2015-05-09 11:44 ` Maxime Ripard 2015-05-11 8:11 ` Chen-Yu Tsai
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